/* ** ################################################################### ** Processors: MCXN946VDF_cm33_core1 ** MCXN946VNL_cm33_core1 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 2.0, 2023-02-01 ** Build: b240510 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN946_cm33_core1 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2024 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2022-10-01) ** Initial version ** - rev. 2.0 (2023-02-01) ** Initial version based on Rev. 2 Draft B ** ** ################################################################### */ /*! * @file MCXN946_cm33_core1.h * @version 2.0 * @date 2023-02-01 * @brief CMSIS Peripheral Access Layer for MCXN946_cm33_core1 * * CMSIS Peripheral Access Layer for MCXN946_cm33_core1 */ #if !defined(MCXN946_CM33_CORE1_H_) #define MCXN946_CM33_CORE1_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ /* Device specific interrupts */ OR_IRQn = 0, /**< OR IRQ */ EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ Reserved65_IRQn = 49, /**< Reserved interrupt */ USB0_FS_IRQn = 50, /**< Universal Serial Bus - Full Speed interrupt */ USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ CAN1_IRQn = 63, /**< Controller Area Network 1 interrupt */ Reserved80_IRQn = 64, /**< Reserved interrupt */ Reserved81_IRQn = 65, /**< Reserved interrupt */ USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ Reserved85_IRQn = 69, /**< Reserved interrupt */ PLU_IRQn = 70, /**< Programmable Logic Unit interrupt */ Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ ELS_IRQn = 73, /**< ELS interrupt */ PKC_IRQn = 74, /**< PKC interrupt */ PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ PQ_IRQn = 76, /**< Power Quad interrupt */ EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ NPU_IRQn = 97, /**< NPU interrupt */ GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ TSI_END_OF_SCAN_IRQn = 101, /**< TSI End of Scan interrupt */ TSI_OUT_OF_SCAN_IRQn = 102, /**< TSI Out of Scan interrupt */ EMVSIM0_IRQn = 103, /**< EMVSIM0 interrupt */ EMVSIM1_IRQn = 104, /**< EMVSIM1 interrupt */ FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ DAC1_IRQn = 107, /**< Digital-to-Analog Converter 1 - General Purpose interrupt */ DAC2_IRQn = 108, /**< 14-bit Digital-to-Analog Converter interrupt */ HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ FLEXPWM1_RELOAD_ERROR_IRQn = 118, /**< FlexPWM1_reload_error interrupt */ FLEXPWM1_FAULT_IRQn = 119, /**< FlexPWM1_fault interrupt */ FLEXPWM1_SUBMODULE0_IRQn = 120, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ FLEXPWM1_SUBMODULE1_IRQn = 121, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ FLEXPWM1_SUBMODULE2_IRQn = 122, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ FLEXPWM1_SUBMODULE3_IRQn = 123, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ QDC1_COMPARE_IRQn = 128, /**< QDC1_Compare interrupt */ QDC1_HOME_IRQn = 129, /**< QDC1_Home interrupt */ QDC1_WDG_SAB_IRQn = 130, /**< QDC1_WDG_IRQ/SAB interrupt */ QDC1_IDX_IRQn = 131, /**< QDC1_IDX interrupt */ ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ BSP32_IRQn = 133, /**< CoolFlux BSP32 interrupt */ ELS_ERR_IRQn = 134, /**< ELS error interrupt */ PKC_ERR_IRQn = 135, /**< PKC error interrupt */ ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ ETHERNET_IRQn = 139, /**< Ethernet QoS interrupt */ ETHERNET_PMT_IRQn = 140, /**< Ethernet QoS power management interrupt */ ETHERNET_MACLP_IRQn = 141, /**< Ethernet QoS MAC interrupt */ SINC_FILTER_IRQn = 142, /**< SINC Filter interrupt */ LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ SCG_IRQn = 145, /**< System Clock Generator interrupt */ SPC_IRQn = 146, /**< System Power Controller interrupt */ WUU_IRQn = 147, /**< Wake Up Unit interrupt */ PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ ETB0_IRQn = 149, /**< ETB counter expires interrupt */ Reserved166_IRQn = 150, /**< Reserved interrupt */ Reserved167_IRQn = 151, /**< Reserved interrupt */ WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M33 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration * @{ */ #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ #define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ #define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ #include "core_cm33.h" /* Core Peripheral Access Layer */ #include "system_MCXN946_cm33_core1.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Mapping Information ---------------------------------------------------------------------------- */ /*! * @addtogroup Mapping_Information Mapping Information * @{ */ /** Mapping Information */ /*! * @addtogroup dma_request * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ /*! * @brief Structure for the DMA hardware request * * Defines the structure for the DMA hardware request collections. The user can configure the * hardware request to trigger the DMA transfer accordingly. The index * of the hardware request varies according to the to SoC. */ typedef enum _dma_request_source { kDma0RequestMuxFlexSpi0Rx = 1U, /**< FlexSPI0 Receive event */ kDma1RequestMuxFlexSpi0Rx = 1U, /**< FlexSPI0 Receive event */ kDma0RequestMuxFlexSpi0Tx = 2U, /**< FlexSPI0 Transmit event */ kDma1RequestMuxFlexSpi0Tx = 2U, /**< FlexSPI0 Transmit event */ kDma0RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ kDma1RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ kDma0RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ kDma1RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ kDma0RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ kDma1RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ kDma0RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ kDma1RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ kDma0RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ kDma1RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ kDma0RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ kDma1RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ kDma0RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ kDma1RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ kDma0RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ kDma1RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ kDma0RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ kDma1RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ kDma0RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ kDma1RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ kDma0RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ kDma1RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ kDma0RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ kDma1RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ kDma0RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ kDma1RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ kDma0RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ kDma1RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ kDma0RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ kDma1RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ kDma0RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ kDma1RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ kDma0RequestMuxSct0Dma0 = 19U, /**< SCT0 DMA0 */ kDma1RequestMuxSct0Dma0 = 19U, /**< SCT0 DMA0 */ kDma0RequestMuxSct0Dma1 = 20U, /**< SCT0 DMA1 */ kDma1RequestMuxSct0Dma1 = 20U, /**< SCT0 DMA1 */ kDma0RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ kDma1RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ kDma0RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ kDma1RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ kDma0RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ kDma1RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ kDma0RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ kDma1RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ kDma0RequestMuxDac0FifoRequest = 25U, /**< DAC0 FIFO_request */ kDma1RequestMuxDac0FifoRequest = 25U, /**< DAC0 FIFO_request */ kDma0RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ kDma1RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ kDma0RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ kDma1RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ kDma0RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ kDma1RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ kDma0RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ kDma1RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ kDma0RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ kDma1RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ kDma0RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ kDma1RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ kDma0RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ kDma1RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ kDma0RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ kDma1RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ kDma0RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ kDma1RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ kDma0RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ kDma1RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ kDma0RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ kDma1RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ kDma0RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ kDma1RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ kDma0RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ kDma1RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ kDma0RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ kDma1RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ kDma0RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ kDma1RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ kDma0RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ kDma1RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ kDma0RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ kDma1RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ kDma0RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ kDma1RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ kDma0RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ kDma1RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ kDma0RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ kDma1RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ kDma0RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ kDma1RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ kDma0RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ kDma1RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ kDma0RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ kDma1RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ kDma0RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ kDma1RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ kDma0RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ kDma1RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ kDma0RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ kDma1RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ kDma0RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ kDma1RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ kDma0RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ kDma1RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ kDma0RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ kDma1RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ kDma0RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ kDma1RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ kDma0RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ kDma1RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ kDma0RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ kDma1RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ kDma0RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ kDma1RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ kDma0RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ kDma0RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ kDma0RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ kDma0RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ kDma0RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ kDma0RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ kDma0RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ kDma0RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ kDma0RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ kDma1RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ kDma0RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ kDma1RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ kDma0RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ kDma1RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ kDma0RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ kDma1RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ kDma0RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ kDma1RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ kDma0RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ kDma1RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ kDma0RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ kDma1RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ kDma0RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ kDma1RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ kDma0RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ kDma1RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ kDma0RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ kDma1RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ kDma0RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ kDma1RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ kDma0RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ kDma1RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ kDma0RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ kDma1RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ kDma0RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ kDma1RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ kDma0RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ kDma1RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ kDma0RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ kDma1RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ kDma0RequestMuxLpFlexcomm8Rx = 85U, /**< LP_FLEXCOMM8 Receive request */ kDma1RequestMuxLpFlexcomm8Rx = 85U, /**< LP_FLEXCOMM8 Receive request */ kDma0RequestMuxLpFlexcomm8Tx = 86U, /**< LP_FLEXCOMM8 Transmit request */ kDma1RequestMuxLpFlexcomm8Tx = 86U, /**< LP_FLEXCOMM8 Transmit request */ kDma0RequestMuxLpFlexcomm9Rx = 87U, /**< LP_FLEXCOMM9 Receive request */ kDma1RequestMuxLpFlexcomm9Rx = 87U, /**< LP_FLEXCOMM9 Receive request */ kDma0RequestMuxLpFlexcomm9Tx = 88U, /**< LP_FLEXCOMM9 Transmit request */ kDma1RequestMuxLpFlexcomm9Tx = 88U, /**< LP_FLEXCOMM9 Transmit request */ kDma0RequestMuxEmvSim0Rx = 91U, /**< EMVSIM0 Receive request */ kDma1RequestMuxEmvSim0Rx = 91U, /**< EMVSIM0 Receive request */ kDma0RequestMuxEmvSim0Tx = 92U, /**< EMVSIM0 Transmit request */ kDma1RequestMuxEmvSim0Tx = 92U, /**< EMVSIM0 Transmit request */ kDma0RequestMuxEmvSim1Rx = 93U, /**< EMVSIM1 Receive request */ kDma1RequestMuxEmvSim1Rx = 93U, /**< EMVSIM1 Receive request */ kDma0RequestMuxEmvSim1Tx = 94U, /**< EMVSIM1 Transmit request */ kDma1RequestMuxEmvSim1Tx = 94U, /**< EMVSIM1 Transmit request */ kDma0RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ kDma1RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ kDma0RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ kDma1RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ kDma0RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ kDma1RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ kDma0RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ kDma1RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ kDma0RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ kDma1RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ kDma0RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ kDma1RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ kDma0RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ kDma1RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ kDma0RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ kDma1RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ kDma0RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ kDma1RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ kDma0RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ kDma1RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ kDma0RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ kDma1RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ kDma0RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ kDma1RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ kDma0RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ kDma1RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ kDma0RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ kDma1RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ kDma0RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ kDma1RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ kDma0RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ kDma1RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ kDma0RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ kDma1RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ kDma0RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ kDma1RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ kDma0RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ kDma1RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ kDma0RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ kDma1RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ kDma0RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ kDma1RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ kDma0RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ kDma1RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ kDma0RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ kDma1RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ kDma0RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ kDma1RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ kDma0RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ kDma1RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ kDma0RequestMuxTsi0EndOfScan = 120U, /**< TSI0 End of Scan */ kDma1RequestMuxTsi0EndOfScan = 120U, /**< TSI0 End of Scan */ kDma0RequestMuxTsi0OutOfRange = 121U, /**< TSI0 Out of Range */ kDma1RequestMuxTsi0OutOfRange = 121U, /**< TSI0 Out of Range */ } dma_request_source_t; /* @} */ /*! * @addtogroup eim_memory_channel * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ /*! * @brief Structure for the eim_memory_channel * * Defines the structure for the EIM resource collections. */ typedef enum _eim_memory_channel { kEIM_MemoryChannelRAMX = 0U, /**< Memory RAMX */ kEIM_MemoryChannelRAMA = 1U, /**< Memory RAMA */ kEIM_MemoryChannelRAMB = 2U, /**< Memory RAMB */ kEIM_MemoryChannelRAMC = 3U, /**< Memory RAMC */ kEIM_MemoryChannelRAMD = 4U, /**< Memory RAMD */ kEIM_MemoryChannelRAME = 5U, /**< Memory RAME */ kEIM_MemoryChannelRAMF = 6U, /**< Memory RAMF */ kEIM_MemoryChannelLPCACRAM = 7U, /**< Memory LPCACRAM */ kEIM_MemoryChannelPKCRAM = 8U, /**< Memory PKCRAM */ } eim_memory_channel_t; /* @} */ /*! * @addtogroup eim_error_injection_channel_enable * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ /*! * @brief Structure for the eim_error_injection_channel_enable * * Defines the structure for the EIM error injection resource collections. */ typedef enum _eim_error_injection_channel_enable { kEIM_MemoryChannelRAMXEnable = 0x80000000U, /**< Memory channel 0(RAMX) error injection enable */ kEIM_MemoryChannelRAMAEnable = 0x40000000U, /**< Memory channel 1(RAMA) error injection enable */ kEIM_MemoryChannelRAMBEnable = 0x20000000U, /**< Memory channel 2(RAMB) error injection enable */ kEIM_MemoryChannelRAMCEnable = 0x10000000U, /**< Memory channel 3(RAMC) error injection enable */ kEIM_MemoryChannelRAMDEnable = 0x8000000U, /**< Memory channel 4(RAMD) error injection enable */ kEIM_MemoryChannelRAMEEnable = 0x4000000U, /**< Memory channel 5(RAME) error injection enable */ kEIM_MemoryChannelRAMFEnable = 0x2000000U, /**< Memory channel 6(RAMF) error injection enable */ kEIM_MemoryChannelLPCACRAMEnable = 0x1000000U, /**< Memory channel 7(LPCACRAM) error injection enable */ kEIM_MemoryChannelPKCRAMEnable = 0x800000U, /**< Memory channel 8(PKCRAM) error injection enable */ } eim_error_injection_channel_enable_t; /* @} */ /*! * @addtogroup erm_memory_channel * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ /*! * @brief Structure for the erm_memory_channel * * Defines the structure for the ERM resource collections. */ typedef enum _erm_memory_channel { kERM_MemoryChannelRAMX = 0U, /**< Memory RAMX */ kERM_MemoryChannelRAMA = 1U, /**< Memory RAMA */ kERM_MemoryChannelRAMB = 2U, /**< Memory RAMB */ kERM_MemoryChannelRAMC = 3U, /**< Memory RAMC */ kERM_MemoryChannelRAMD = 4U, /**< Memory RAMD */ kERM_MemoryChannelRAME = 5U, /**< Memory RAME */ kERM_MemoryChannelRAMF = 6U, /**< Memory RAMF */ kERM_MemoryChannelLPCACRAM = 7U, /**< Memory LPCACRAM */ kERM_MemoryChannelPKCRAM = 8U, /**< Memory PKCRAM */ kERM_MemoryChannelFLASH = 9U, /**< Memory FLASH */ } erm_memory_channel_t; /* @} */ /*! * @} */ /* end of group Mapping_Information */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #else #pragma push #pragma anon_unions #endif #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ __IO uint32_t STAT; /**< Status Register, offset: 0x14 */ __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ __IO uint32_t CFG; /**< Configuration Register, offset: 0x20 */ __IO uint32_t PAUSE; /**< Pause Register, offset: 0x24 */ uint8_t RESERVED_1[12]; __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ uint8_t RESERVED_2[4]; __IO uint32_t OFSTRIM; /**< Offset Trim Register, offset: 0x40 */ uint8_t RESERVED_3[92]; __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_4[48]; __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ uint8_t RESERVED_5[8]; __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ struct { /* offset: 0x100, array step: 0x8 */ __IO uint32_t CMDL; /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ __IO uint32_t CMDH; /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */ } CMD[15]; uint8_t RESERVED_6[136]; __IO uint32_t CV[15]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_7[196]; __I uint32_t RESFIFO[2]; /**< Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_8[248]; __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_9[124]; __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define ADC_VERID_RES_MASK (0x1U) #define ADC_VERID_RES_SHIFT (0U) /*! RES - Resolution * 0b0..Up to 13-bit differential or 12-bit single-ended resolution supported. * 0b1..Up to 16-bit differential or 16-bit single-ended resolution supported. CMDLn[MODE] available for * selecting the resolution of conversions for the associated command. */ #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) #define ADC_VERID_DIFFEN_MASK (0x2U) #define ADC_VERID_DIFFEN_SHIFT (1U) /*! DIFFEN - Differential Supported * 0b0..Not supported * 0b1..Supported. CMDLn[CTYPE] controls fields implemented. */ #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) #define ADC_VERID_MVI_MASK (0x8U) #define ADC_VERID_MVI_SHIFT (3U) /*! MVI - Multiple Vref Implemented * 0b0..Single VREFH input supported. * 0b1..Multiple VREFH inputs supported. */ #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) #define ADC_VERID_CSW_MASK (0x70U) #define ADC_VERID_CSW_SHIFT (4U) /*! CSW - Channel Scale Width * 0b000..Not supported. * 0b001..Supported with one-bit CSCALE control field. * 0b110..Supported with six-bit CSCALE control field. */ #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) #define ADC_VERID_VR1RNGI_MASK (0x100U) #define ADC_VERID_VR1RNGI_SHIFT (8U) /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented * 0b0..Range control not required. * 0b1..Range control required. */ #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) #define ADC_VERID_IADCKI_MASK (0x200U) #define ADC_VERID_IADCKI_SHIFT (9U) /*! IADCKI - Internal ADC Clock Implemented * 0b0..Not implemented * 0b1..Implemented */ #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) #define ADC_VERID_CALOFSI_MASK (0x400U) #define ADC_VERID_CALOFSI_SHIFT (10U) /*! CALOFSI - Calibration Function Implemented * 0b0..Not implemented * 0b1..Implemented */ #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) #define ADC_VERID_NUM_SEC_MASK (0x800U) #define ADC_VERID_NUM_SEC_SHIFT (11U) /*! NUM_SEC - Number of Single-Ended Outputs Supported * 0b0..One * 0b1..Two */ #define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) #define ADC_VERID_NUM_FIFO_MASK (0x7000U) #define ADC_VERID_NUM_FIFO_SHIFT (12U) /*! NUM_FIFO - Number of FIFOs * 0b000..N/A * 0b001..One * 0b010..Two * 0b011..Three * 0b100..Four */ #define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) #define ADC_VERID_MINOR_MASK (0xFF0000U) #define ADC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) #define ADC_VERID_MAJOR_MASK (0xFF000000U) #define ADC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) #define ADC_PARAM_TRIG_NUM_SHIFT (0U) /*! TRIG_NUM - Trigger Number */ #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) #define ADC_PARAM_FIFOSIZE_SHIFT (8U) /*! FIFOSIZE - Result FIFO Depth * 0b00000001..2 * 0b00000100..4 * 0b00001000..8 * 0b00010000..16 * 0b00100000..32 * 0b01000000..64 */ #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) #define ADC_PARAM_CV_NUM_SHIFT (16U) /*! CV_NUM - Compare Value Number */ #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) #define ADC_PARAM_CMD_NUM_SHIFT (24U) /*! CMD_NUM - Command Buffer Number */ #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) /*! @} */ /*! @name CTRL - Control Register */ /*! @{ */ #define ADC_CTRL_ADCEN_MASK (0x1U) #define ADC_CTRL_ADCEN_SHIFT (0U) /*! ADCEN - ADC Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) #define ADC_CTRL_RST_MASK (0x2U) #define ADC_CTRL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..ADC logic is not reset. * 0b1..ADC logic is reset. */ #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) #define ADC_CTRL_DOZEN_MASK (0x4U) #define ADC_CTRL_DOZEN_SHIFT (2U) /*! DOZEN - Doze Enable * 0b0..ADC is enabled in low-power mode. * 0b1..ADC is disabled in low-power mode. */ #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) #define ADC_CTRL_CAL_REQ_MASK (0x8U) #define ADC_CTRL_CAL_REQ_SHIFT (3U) /*! CAL_REQ - Auto-Calibration Request * 0b0..No request made. * 0b1..Request has been made. */ #define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) #define ADC_CTRL_CALOFS_MASK (0x10U) #define ADC_CTRL_CALOFS_SHIFT (4U) /*! CALOFS - Offset Calibration Request * 0b0..Calibration function disabled * 0b1..Request for offset calibration function */ #define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) #define ADC_CTRL_RSTFIFO0_MASK (0x100U) #define ADC_CTRL_RSTFIFO0_SHIFT (8U) /*! RSTFIFO0 - Reset FIFO 0 * 0b0..No effect. * 0b1..FIFO 0 is reset. */ #define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) #define ADC_CTRL_RSTFIFO1_MASK (0x200U) #define ADC_CTRL_RSTFIFO1_SHIFT (9U) /*! RSTFIFO1 - Reset FIFO 1 * 0b0..No effect. * 0b1..FIFO 1 is reset. */ #define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) #define ADC_CTRL_CAL_AVGS_MASK (0xF0000U) #define ADC_CTRL_CAL_AVGS_SHIFT (16U) /*! CAL_AVGS - Auto-Calibration Averages * 0b0000..Single conversion. * 0b0001..2 conversions averaged. * 0b0010..4 conversions averaged. * 0b0011..8 conversions averaged. * 0b0100..16 conversions averaged. * 0b0101..32 conversions averaged. * 0b0110..64 conversions averaged. * 0b0111..128 conversions averaged. * 0b1000..256 conversions averaged. * 0b1001..512 conversions averaged. * 0b1010..1024 conversions averaged. */ #define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) /*! @} */ /*! @name STAT - Status Register */ /*! @{ */ #define ADC_STAT_RDY0_MASK (0x1U) #define ADC_STAT_RDY0_SHIFT (0U) /*! RDY0 - Result FIFO 0 Ready Flag * 0b0..Not above watermark * 0b1..Above watermark */ #define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) #define ADC_STAT_FOF0_MASK (0x2U) #define ADC_STAT_FOF0_SHIFT (1U) /*! FOF0 - Result FIFO 0 Overflow Flag * 0b0..No result FIFO 0 overflow has occurred since the last time that the flag was cleared. * 0b1..At least one result FIFO 0 overflow has occurred since the last time that the flag was cleared. */ #define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) #define ADC_STAT_RDY1_MASK (0x4U) #define ADC_STAT_RDY1_SHIFT (2U) /*! RDY1 - Result FIFO1 Ready Flag * 0b0..Not above watermark * 0b1..Above watermark */ #define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) #define ADC_STAT_FOF1_MASK (0x8U) #define ADC_STAT_FOF1_SHIFT (3U) /*! FOF1 - Result FIFO1 Overflow Flag * 0b0..No result FIFO1 overflow has occurred since the last time that the flag was cleared. * 0b1..At least one result FIFO1 overflow has occurred since the last time that the flag was cleared. */ #define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) #define ADC_STAT_TEXC_INT_MASK (0x100U) #define ADC_STAT_TEXC_INT_SHIFT (8U) /*! TEXC_INT - Interrupt Flag For High-Priority Trigger Exception * 0b0..No trigger exceptions have occurred. * 0b1..A trigger exception has occurred and is pending acknowledgment. */ #define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) #define ADC_STAT_TCOMP_INT_MASK (0x200U) #define ADC_STAT_TCOMP_INT_SHIFT (9U) /*! TCOMP_INT - Interrupt Flag For Trigger Completion * 0b0..Either IE[TCOMP_IE] = 0, or no trigger sequences have run to completion. * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. */ #define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) #define ADC_STAT_CAL_RDY_MASK (0x400U) #define ADC_STAT_CAL_RDY_SHIFT (10U) /*! CAL_RDY - Calibration Ready * 0b0..Calibration is incomplete or has not been run. * 0b1..ADC is calibrated. */ #define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) #define ADC_STAT_ADC_ACTIVE_MASK (0x800U) #define ADC_STAT_ADC_ACTIVE_SHIFT (11U) /*! ADC_ACTIVE - ADC Active * 0b0..ADC is idle. There are no pending triggers to service and no active commands are being processed. * 0b1..ADC is processing a conversion, running through the power-up delay, or servicing a trigger. */ #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) #define ADC_STAT_TRGACT_MASK (0x30000U) #define ADC_STAT_TRGACT_SHIFT (16U) /*! TRGACT - Trigger Active * 0b00..Command (sequence) associated with Trigger 0 currently being executed. * 0b01..Command (sequence) associated with Trigger 1 currently being executed. * 0b10..Command (sequence) associated with Trigger 2 currently being executed. * 0b11..Command (sequence) associated with Trigger 3 currently being executed. */ #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) #define ADC_STAT_CMDACT_MASK (0xF000000U) #define ADC_STAT_CMDACT_SHIFT (24U) /*! CMDACT - Command Active * 0b0000..No command currently in progress. * 0b0001..Command 1 currently being executed. * 0b0010..Command 2 currently being executed. * 0b0011-0b1111..Associated command number currently being executed. */ #define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) /*! @} */ /*! @name IE - Interrupt Enable Register */ /*! @{ */ #define ADC_IE_FWMIE0_MASK (0x1U) #define ADC_IE_FWMIE0_SHIFT (0U) /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) #define ADC_IE_FOFIE0_MASK (0x2U) #define ADC_IE_FOFIE0_SHIFT (1U) /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) #define ADC_IE_FWMIE1_MASK (0x4U) #define ADC_IE_FWMIE1_SHIFT (2U) /*! FWMIE1 - FIFO1 Watermark Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) #define ADC_IE_FOFIE1_MASK (0x8U) #define ADC_IE_FOFIE1_SHIFT (3U) /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) #define ADC_IE_TEXC_IE_MASK (0x100U) #define ADC_IE_TEXC_IE_SHIFT (8U) /*! TEXC_IE - Trigger Exception Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) #define ADC_IE_TCOMP_IE_MASK (0xF0000U) #define ADC_IE_TCOMP_IE_SHIFT (16U) /*! TCOMP_IE - Trigger Completion Interrupt Enable * 0b0000..All disabled * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. * 0b0011-0b1110..Associated trigger completion interrupts are enabled. * 0b1111..All enabled */ #define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) /*! @} */ /*! @name DE - DMA Enable Register */ /*! @{ */ #define ADC_DE_FWMDE0_MASK (0x1U) #define ADC_DE_FWMDE0_SHIFT (0U) /*! FWMDE0 - FIFO 0 Watermark DMA Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) #define ADC_DE_FWMDE1_MASK (0x2U) #define ADC_DE_FWMDE1_SHIFT (1U) /*! FWMDE1 - FIFO1 Watermark DMA Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) /*! @} */ /*! @name CFG - Configuration Register */ /*! @{ */ #define ADC_CFG_TPRICTRL_MASK (0x3U) #define ADC_CFG_TPRICTRL_SHIFT (0U) /*! TPRICTRL - ADC Trigger Priority Control * 0b00..Current conversion is aborted and the new command specified by the trigger is started. * 0b01..Current command is stopped after completing the current conversion. If averaging is enabled, the * averaging loop is completed. CMDHn[LOOP] is ignored and the higher-priority trigger is serviced. * 0b10..Current command is completed (averaging, looping, compare) before servicing the higher-priority trigger. * 0b11.. */ #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) #define ADC_CFG_PWRSEL_MASK (0x30U) #define ADC_CFG_PWRSEL_SHIFT (4U) /*! PWRSEL - Power Configuration Select * 0b0x..Low power * 0b1x..High power */ #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) #define ADC_CFG_REFSEL_MASK (0xC0U) #define ADC_CFG_REFSEL_SHIFT (6U) /*! REFSEL - Voltage Reference Selection * 0b00..Option 1 * 0b01..Option 2 * 0b10..Option 3 * 0b11.. */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) #define ADC_CFG_TRES_MASK (0x100U) #define ADC_CFG_TRES_SHIFT (8U) /*! TRES - Trigger Resume Enable * 0b0..Not automatically resumed or restarted * 0b1..Automatically resumed or restarted */ #define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) #define ADC_CFG_TCMDRES_MASK (0x200U) #define ADC_CFG_TCMDRES_SHIFT (9U) /*! TCMDRES - Trigger Command Resume * 0b0..Trigger sequence automatically restarted. * 0b1..Trigger sequence resumed from the command that was executed prior to the exception. */ #define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) #define ADC_CFG_HPT_EXDI_MASK (0x400U) #define ADC_CFG_HPT_EXDI_SHIFT (10U) /*! HPT_EXDI - High-Priority Trigger Exception Disable * 0b0..Enabled * 0b1..Disabled */ #define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) #define ADC_CFG_PUDLY_MASK (0xFF0000U) #define ADC_CFG_PUDLY_SHIFT (16U) /*! PUDLY - Power-up Delay */ #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) #define ADC_CFG_PWREN_MASK (0x10000000U) #define ADC_CFG_PWREN_SHIFT (28U) /*! PWREN - ADC Analog Pre-Enable * 0b0..ADC analog circuits are only enabled while conversions are active. Analog startup delays affect performance. * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays, at the cost * of higher DC current consumption. A single power-up delay (CFG[PUDLY]) is executed immediately once PWREN * is set. No detected triggers begin ADC operation until the power-up delay time has passed. After this * initial delay expires, the analog circuits remain pre-enabled, and no additional delays are executed. */ #define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) /*! @} */ /*! @name PAUSE - Pause Register */ /*! @{ */ #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) /*! PAUSEDLY - Pause Delay */ #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) #define ADC_PAUSE_PAUSEEN_SHIFT (31U) /*! PAUSEEN - Pause Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) /*! @} */ /*! @name SWTRIG - Software Trigger Register */ /*! @{ */ #define ADC_SWTRIG_SWT0_MASK (0x1U) #define ADC_SWTRIG_SWT0_SHIFT (0U) /*! SWT0 - Software Trigger 0 * 0b0..No trigger 0 event generated. * 0b1..Trigger 0 event generated. */ #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) #define ADC_SWTRIG_SWT1_MASK (0x2U) #define ADC_SWTRIG_SWT1_SHIFT (1U) /*! SWT1 - Software Trigger 1 * 0b0..No trigger 1 event generated. * 0b1..Trigger 1 event generated. */ #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) #define ADC_SWTRIG_SWT2_MASK (0x4U) #define ADC_SWTRIG_SWT2_SHIFT (2U) /*! SWT2 - Software Trigger 2 * 0b0..No trigger 2 event generated. * 0b1..Trigger 2 event generated. */ #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) #define ADC_SWTRIG_SWT3_MASK (0x8U) #define ADC_SWTRIG_SWT3_SHIFT (3U) /*! SWT3 - Software Trigger 3 * 0b0..No trigger 3 event generated. * 0b1..Trigger 3 event generated. */ #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) /*! @} */ /*! @name TSTAT - Trigger Status Register */ /*! @{ */ #define ADC_TSTAT_TEXC_NUM_MASK (0xFU) #define ADC_TSTAT_TEXC_NUM_SHIFT (0U) /*! TEXC_NUM - Trigger Exception Number * 0b0000..No triggers have been interrupted by a high-priority exception. * 0b0001..Trigger 0 has been interrupted by a high-priority exception. * 0b0010..Trigger 1 has been interrupted by a high-priority exception. * 0b0011-0b1110..Associated trigger sequence has interrupted by a high-priority exception. * 0b1111..Every trigger sequence has been interrupted by a high-priority exception. */ #define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) #define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) #define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) /*! TCOMP_FLAG - Trigger Completion Flag * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. * 0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts. * 0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts. * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. */ #define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) /*! @} */ /*! @name OFSTRIM - Offset Trim Register */ /*! @{ */ #define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) #define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) /*! OFSTRIM_A - Trim for Offset */ #define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) #define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) #define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) /*! OFSTRIM_B - Trim for Offset */ #define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) /*! @} */ /*! @name TCTRL - Trigger Control Register */ /*! @{ */ #define ADC_TCTRL_HTEN_MASK (0x1U) #define ADC_TCTRL_HTEN_SHIFT (0U) /*! HTEN - Trigger Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) #define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) #define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) /*! FIFO_SEL_A - SAR Result Destination for Channel A * 0b0..FIFO 0 * 0b1..FIFO 1 */ #define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) #define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) #define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) /*! FIFO_SEL_B - SAR Result Destination for Channel B * 0b0..FIFO 0 * 0b1..FIFO 1 */ #define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) #define ADC_TCTRL_TPRI_MASK (0x300U) #define ADC_TCTRL_TPRI_SHIFT (8U) /*! TPRI - Trigger Priority Setting * 0b00..Highest priority, Level 1 * 0b01-0b10..Set to corresponding priority level. * 0b11..Lowest priority, Level 4 */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) #define ADC_TCTRL_RSYNC_MASK (0x8000U) #define ADC_TCTRL_RSYNC_SHIFT (15U) /*! RSYNC - Trigger Resync * 0b0..Disable * 0b1..Enable */ #define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) /*! TDLY - Trigger Delay Select */ #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) #define ADC_TCTRL_TCMD_MASK (0xF000000U) #define ADC_TCTRL_TCMD_SHIFT (24U) /*! TCMD - Trigger Command Select * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. * 0b0001..CMD1 * 0b0010-0b1110..Corresponding CMD is executed * 0b1111..CMD15 */ #define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) /*! @} */ /* The count of ADC_TCTRL */ #define ADC_TCTRL_COUNT (4U) /*! @name FCTRL - FIFO Control Register */ /*! @{ */ #define ADC_FCTRL_FCOUNT_MASK (0x1FU) #define ADC_FCTRL_FCOUNT_SHIFT (0U) /*! FCOUNT - Result FIFO Counter */ #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) #define ADC_FCTRL_FWMARK_MASK (0xF0000U) #define ADC_FCTRL_FWMARK_SHIFT (16U) /*! FWMARK - Watermark Level Selection */ #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) /*! @} */ /* The count of ADC_FCTRL */ #define ADC_FCTRL_COUNT (2U) /*! @name GCC - Gain Calibration Control */ /*! @{ */ #define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) #define ADC_GCC_GAIN_CAL_SHIFT (0U) /*! GAIN_CAL - Gain Calibration Value */ #define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) #define ADC_GCC_RDY_MASK (0x1000000U) #define ADC_GCC_RDY_SHIFT (24U) /*! RDY - Gain Calibration Value Valid * 0b0..Invalid * 0b1..Valid */ #define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) /*! @} */ /* The count of ADC_GCC */ #define ADC_GCC_COUNT (2U) /*! @name GCR - Gain Calculation Result */ /*! @{ */ #define ADC_GCR_GCALR_MASK (0xFFFFU) #define ADC_GCR_GCALR_SHIFT (0U) /*! GCALR - Gain Calculation Result */ #define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) #define ADC_GCR_RDY_MASK (0x1000000U) #define ADC_GCR_RDY_SHIFT (24U) /*! RDY - Gain Calculation Ready * 0b0..Invalid * 0b1..Valid */ #define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) /*! @} */ /* The count of ADC_GCR */ #define ADC_GCR_COUNT (2U) /*! @name CMDL - Command Low Buffer Register */ /*! @{ */ #define ADC_CMDL_ADCH_MASK (0x1FU) #define ADC_CMDL_ADCH_SHIFT (0U) /*! ADCH - Input Channel Select * 0b00000..CH0A or CH0B or CH0A/CH0B pair. * 0b00001..CH1A or CH1B or CH1A/CH1B pair. * 0b00010..CH2A or CH2B or CH2A/CH2B pair. * 0b00011..CH3A or CH3B or CH3A/CH3B pair. * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. * 0b11110..CH30A or CH30B or CH30A/CH30B pair. * 0b11111..CH31A or CH31B or CH31A/CH31B pair. */ #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) #define ADC_CMDL_CTYPE_MASK (0x60U) #define ADC_CMDL_CTYPE_SHIFT (5U) /*! CTYPE - Conversion Type * 0b00..Single-Ended mode. Only A-side channel is converted. * 0b01..Single-Ended mode. Only B-side channel is converted. * 0b10..Differential mode. A-B. * 0b11..Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. */ #define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) #define ADC_CMDL_MODE_MASK (0x80U) #define ADC_CMDL_MODE_SHIFT (7U) /*! MODE - Select Resolution of Conversions * 0b0..Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. * 0b1..High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. */ #define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) #define ADC_CMDL_ALTB_ADCH_MASK (0x1F0000U) #define ADC_CMDL_ALTB_ADCH_SHIFT (16U) /*! ALTB_ADCH - Alternate Channel B Input Channel Select * 0b00000..Select CH0B * 0b00001..Select CH1B * 0b00010..Select CH2B * 0b00011..Select CH3B * 0b00100-0b11101..Select corresponding channel CHnB * 0b11110..Select CH30B * 0b11111..Select CH31B */ #define ADC_CMDL_ALTB_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK) #define ADC_CMDL_ALTBEN_MASK (0x200000U) #define ADC_CMDL_ALTBEN_SHIFT (21U) /*! ALTBEN - Alternate Channel B Select Enable * 0b0..ALTBEN_ADCH disabled. Channel-A and Channel-B inputs are selected based on ADCH settings. * 0b1..ALTBEN_ADCH enabled. Channel-A inputs are selected by ADCH setting and Channel-B inputs are selected by ALTB_ADCH setting. */ #define ADC_CMDL_ALTBEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK) /*! @} */ /* The count of ADC_CMDL */ #define ADC_CMDL_COUNT (15U) /*! @name CMDH - Command High Buffer Register */ /*! @{ */ #define ADC_CMDH_CMPEN_MASK (0x3U) #define ADC_CMDH_CMPEN_SHIFT (0U) /*! CMPEN - Compare Function Enable * 0b00..Disabled * 0b01.. * 0b10..Enabled. Store on true. * 0b11..Enabled. Repeat channel acquisition (sample, convert, and compare) until true. */ #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) #define ADC_CMDH_WAIT_TRIG_MASK (0x4U) #define ADC_CMDH_WAIT_TRIG_SHIFT (2U) /*! WAIT_TRIG - Wait for Trigger Assertion Before Execution * 0b0..Command executes automatically. * 0b1..Active trigger must be asserted again before executing this command. */ #define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) #define ADC_CMDH_LWI_MASK (0x80U) #define ADC_CMDH_LWI_SHIFT (7U) /*! LWI - Loop with Increment * 0b0..Disabled * 0b1..Enabled */ #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) #define ADC_CMDH_STS_MASK (0x700U) #define ADC_CMDH_STS_SHIFT (8U) /*! STS - Sample Time Select * 0b000..Minimum sample time of 3.5 ADCK cycles. * 0b001..5.5 ADCK cycles * 0b010..7.5 ADCK cycles * 0b011..11.5 ADCK cycles * 0b100..19.5 ADCK cycles * 0b101..35.5 ADCK cycles * 0b110..67.5 ADCK cycles * 0b111..131.5 ADCK cycles */ #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) #define ADC_CMDH_AVGS_MASK (0xF000U) #define ADC_CMDH_AVGS_SHIFT (12U) /*! AVGS - Hardware Average Select * 0b0000..Single conversion * 0b0001..2 * 0b0010..4 * 0b0011..8 * 0b0100..16 * 0b0101..32 * 0b0110..64 * 0b0111..128 * 0b1000..256 * 0b1001..512 * 0b1010..1024 */ #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) #define ADC_CMDH_LOOP_MASK (0xF0000U) #define ADC_CMDH_LOOP_SHIFT (16U) /*! LOOP - Loop Count Select * 0b0000..Looping not enabled. Command executes one time. * 0b0001..Loop one time. Command executes two times. * 0b0010..Loop two times. Command executes three times. * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP + 1 times. * 0b1111..Loop 15 times. Command executes 16 times. */ #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) #define ADC_CMDH_NEXT_MASK (0xF000000U) #define ADC_CMDH_NEXT_SHIFT (24U) /*! NEXT - Next Command Select * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority * trigger pending, begin command associated with lower priority trigger. * 0b0001..CMD1 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command * 0b1111..CMD15 */ #define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) /*! @} */ /* The count of ADC_CMDH */ #define ADC_CMDH_COUNT (15U) /*! @name CV - Compare Value Register */ /*! @{ */ #define ADC_CV_CVL_MASK (0xFFFFU) #define ADC_CV_CVL_SHIFT (0U) /*! CVL - Compare Value Low */ #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) #define ADC_CV_CVH_MASK (0xFFFF0000U) #define ADC_CV_CVH_SHIFT (16U) /*! CVH - Compare Value High */ #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) /*! @} */ /* The count of ADC_CV */ #define ADC_CV_COUNT (15U) /*! @name RESFIFO - Data Result FIFO Register */ /*! @{ */ #define ADC_RESFIFO_D_MASK (0xFFFFU) #define ADC_RESFIFO_D_SHIFT (0U) /*! D - Data Result */ #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) #define ADC_RESFIFO_TSRC_MASK (0x30000U) #define ADC_RESFIFO_TSRC_SHIFT (16U) /*! TSRC - Trigger Source * 0b00..Trigger source 0 * 0b01..Trigger source 1 * 0b10..Trigger source 2 * 0b11..Trigger source 3 */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) /*! LOOPCNT - Loop Count Value * 0b0000..Result is from initial conversion in command. * 0b0001..Result is from second conversion in command. * 0b0010-0b1110..Result is from (LOOPCNT + 1) conversion in command. * 0b1111..Result is from 16th conversion in command. */ #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) #define ADC_RESFIFO_CMDSRC_SHIFT (24U) /*! CMDSRC - Command Buffer Source * 0b0000..Not a valid value CMDSRC value for a data word in RESFIFO. 0h is only found in the initial FIFO state, * prior to the storage of an ADC conversion result into a RESFIFO buffer. * 0b0001..CMD1 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. * 0b1111..CMD15 */ #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) #define ADC_RESFIFO_VALID_MASK (0x80000000U) #define ADC_RESFIFO_VALID_SHIFT (31U) /*! VALID - FIFO Entry is Valid * 0b0..FIFO is empty. Discard any read from RESFIFO. * 0b1..FIFO contains data. FIFO record read from RESFIFO is valid. */ #define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) /*! @} */ /* The count of ADC_RESFIFO */ #define ADC_RESFIFO_COUNT (2U) /*! @name CAL_GAR - Calibration General A-Side Registers */ /*! @{ */ #define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) /* Merged from fields with different position or width, of widths (11, 12, 13, 14, 15, 16), largest definition used */ #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) /*! CAL_GAR_VAL - Calibration General A Side Register Element */ #define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) /* Merged from fields with different position or width, of widths (11, 12, 13, 14, 15, 16), largest definition used */ /*! @} */ /* The count of ADC_CAL_GAR */ #define ADC_CAL_GAR_COUNT (33U) /*! @name CAL_GBR - Calibration General B-Side Registers */ /*! @{ */ #define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) /* Merged from fields with different position or width, of widths (11, 12, 13, 14, 15, 16), largest definition used */ #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) /*! CAL_GBR_VAL - Calibration General B Side Register Element */ #define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) /* Merged from fields with different position or width, of widths (11, 12, 13, 14, 15, 16), largest definition used */ /*! @} */ /* The count of ADC_CAL_GBR */ #define ADC_CAL_GBR_COUNT (33U) /*! * @} */ /* end of group ADC_Register_Masks */ /* ADC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral ADC0 base address */ #define ADC0_BASE (0x5010D000u) /** Peripheral ADC0 base address */ #define ADC0_BASE_NS (0x4010D000u) /** Peripheral ADC0 base pointer */ #define ADC0 ((ADC_Type *)ADC0_BASE) /** Peripheral ADC0 base pointer */ #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) /** Peripheral ADC1 base address */ #define ADC1_BASE (0x5010E000u) /** Peripheral ADC1 base address */ #define ADC1_BASE_NS (0x4010E000u) /** Peripheral ADC1 base pointer */ #define ADC1 ((ADC_Type *)ADC1_BASE) /** Peripheral ADC1 base pointer */ #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0, ADC1 } /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } #else /** Peripheral ADC0 base address */ #define ADC0_BASE (0x4010D000u) /** Peripheral ADC0 base pointer */ #define ADC0 ((ADC_Type *)ADC0_BASE) /** Peripheral ADC1 base address */ #define ADC1_BASE (0x4010E000u) /** Peripheral ADC1 base pointer */ #define ADC1 ((ADC_Type *)ADC1_BASE) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0, ADC1 } #endif /** Interrupt vectors for the ADC peripheral type */ #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AHBSC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AHBSC_Peripheral_Access_Layer AHBSC Peripheral Access Layer * @{ */ /** AHBSC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[16]; __IO uint32_t FLASH00_MEM_RULE[4]; /**< Flash Memory Rule, array offset: 0x10, array step: 0x4 */ __IO uint32_t FLASH01_MEM_RULE[4]; /**< Flash Memory Rule, array offset: 0x20, array step: 0x4 */ __IO uint32_t FLASH02_MEM_RULE; /**< Flash Memory Rule, offset: 0x30 */ uint8_t RESERVED_1[12]; __IO uint32_t FLASH03_MEM_RULE; /**< Flash Memory Rule, offset: 0x40 */ uint8_t RESERVED_2[28]; __IO uint32_t ROM_MEM_RULE[4]; /**< ROM Memory Rule, array offset: 0x60, array step: 0x4 */ uint8_t RESERVED_3[16]; __IO uint32_t RAMX_MEM_RULE[3]; /**< RAMX Memory Rule, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_4[20]; __IO uint32_t RAMA_MEM_RULE; /**< RAMA Memory Rule 0, offset: 0xA0 */ uint8_t RESERVED_5[28]; __IO uint32_t RAMB_MEM_RULE; /**< RAMB Memory Rule, offset: 0xC0 */ uint8_t RESERVED_6[28]; __IO uint32_t RAMC_MEM_RULE[2]; /**< RAMC Memory Rule, array offset: 0xE0, array step: 0x4 */ uint8_t RESERVED_7[24]; __IO uint32_t RAMD_MEM_RULE[2]; /**< RAMD Memory Rule, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_8[24]; __IO uint32_t RAME_MEM_RULE[2]; /**< RAME Memory Rule, array offset: 0x120, array step: 0x4 */ uint8_t RESERVED_9[24]; __IO uint32_t RAMF_MEM_RULE[2]; /**< RAMF Memory Rule, array offset: 0x140, array step: 0x4 */ uint8_t RESERVED_10[24]; __IO uint32_t RAMG_MEM_RULE[2]; /**< RAMG Memory Rule, array offset: 0x160, array step: 0x4 */ uint8_t RESERVED_11[24]; __IO uint32_t RAMH_MEM_RULE; /**< RAMH Memory Rule, offset: 0x180 */ uint8_t RESERVED_12[28]; __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE0; /**< APB Bridge Group 0 Memory Rule 0, offset: 0x1A0 */ __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE1; /**< APB Bridge Group 0 Memory Rule 1, offset: 0x1A4 */ __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE2; /**< APB Bridge Group 0 Rule 2, offset: 0x1A8 */ __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE3; /**< APB Bridge Group 0 Memory Rule 3, offset: 0x1AC */ __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE0; /**< APB Bridge Group 1 Memory Rule 0, offset: 0x1B0 */ __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE1; /**< APB Bridge Group 1 Memory Rule 1, offset: 0x1B4 */ uint8_t RESERVED_13[4]; __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE2; /**< APB Bridge Group 1 Memory Rule 2, offset: 0x1BC */ __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE0; /**< AIPS Bridge Group 0 Memory Rule 0, offset: 0x1C0 */ __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE1; /**< AIPS Bridge Group 0 Memory Rule 1, offset: 0x1C4 */ __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE2; /**< AIPS Bridge Group 0 Memory Rule 2, offset: 0x1C8 */ __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE3; /**< AIPS Bridge Group 0 Memory Rule 3, offset: 0x1CC */ __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 0, offset: 0x1D0 */ __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 1, offset: 0x1D4 */ __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 2, offset: 0x1D8 */ uint8_t RESERVED_14[4]; __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE0; /**< AIPS Bridge Group 1 Rule 0, offset: 0x1E0 */ __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE1; /**< AIPS Bridge Group 1 Rule 1, offset: 0x1E4 */ uint8_t RESERVED_15[8]; __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 0, offset: 0x1F0 */ __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 1, offset: 0x1F4 */ __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 2, offset: 0x1F8 */ uint8_t RESERVED_16[4]; __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE0; /**< AIPS Bridge Group 2 Rule 0, offset: 0x200 */ __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE1; /**< AIPS Bridge Group 2 Memory Rule 1, offset: 0x204 */ uint8_t RESERVED_17[24]; __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE0; /**< AIPS Bridge Group 3 Rule 0, offset: 0x220 */ __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE1; /**< AIPS Bridge Group 3 Memory Rule 1, offset: 0x224 */ __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE2; /**< AIPS Bridge Group 3 Rule 2, offset: 0x228 */ __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE3; /**< AIPS Bridge Group 3 Rule 3, offset: 0x22C */ uint8_t RESERVED_18[16]; __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE0; /**< AIPS Bridge Group 4 Rule 0, offset: 0x240 */ __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE1; /**< AIPS Bridge Group 4 Rule 1, offset: 0x244 */ __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE2; /**< AIPS Bridge Group 4 Rule 2, offset: 0x248 */ __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE3; /**< AIPS Bridge Group 4 Rule 3, offset: 0x24C */ __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_RULE0; /**< AHB Secure Control Peripheral Rule 0, offset: 0x250 */ uint8_t RESERVED_19[28]; __IO uint32_t FLEXSPI0_REGION0_MEM_RULE[4]; /**< FLEXSPI0 Region 0 Memory Rule, array offset: 0x270, array step: 0x4 */ struct { /* offset: 0x280, array step: 0x10 */ __IO uint32_t FLEXSPI0_REGION_MEM_RULE0; /**< FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 6 Memory Rule 0, array offset: 0x280, array step: 0x10 */ uint8_t RESERVED_0[12]; } FLEXSPI0_REGION1_6_MEM_RULE[6]; __IO uint32_t FLEXSPI0_REGION7_MEM_RULE[4]; /**< FLEXSPI0 Region 7 Memory Rule, array offset: 0x2E0, array step: 0x4 */ struct { /* offset: 0x2F0, array step: 0x10 */ __IO uint32_t FLEXSPI0_REGION_MEM_RULE0; /**< FLEXSPI0 Region 8 Memory Rule 0..FLEXSPI0 Region 13 Memory Rule 0, array offset: 0x2F0, array step: 0x10 */ uint8_t RESERVED_0[12]; } FLEXSPI0_REGION8_13_MEM_RULE[6]; uint8_t RESERVED_20[2736]; __I uint32_t SEC_VIO_ADDR[32]; /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */ __I uint32_t SEC_VIO_MISC_INFO[32]; /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */ __IO uint32_t SEC_VIO_INFO_VALID; /**< Security Violation Info Validity for Address, offset: 0xF00 */ uint8_t RESERVED_21[124]; __IO uint32_t SEC_GPIO_MASK[2]; /**< GPIO Mask for Port 0..GPIO Mask for Port 1, array offset: 0xF80, array step: 0x4 */ uint8_t RESERVED_22[16]; __IO uint32_t SEC_CPU1_INT_MASK0; /**< Secure Interrupt Mask 0 for CPU1, offset: 0xF98 */ __IO uint32_t SEC_CPU1_INT_MASK1; /**< Secure Interrupt Mask 1 for CPU1, offset: 0xF9C */ __IO uint32_t SEC_CPU1_INT_MASK2; /**< Secure Interrupt Mask 2 for CPU1, offset: 0xFA0 */ __IO uint32_t SEC_CPU1_INT_MASK3; /**< Secure Interrupt Mask 3 for CPU1, offset: 0xFA4 */ __IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0xFA8 */ uint8_t RESERVED_23[16]; __IO uint32_t SEC_GP_REG_LOCK; /**< Secure Mask Lock, offset: 0xFBC */ uint8_t RESERVED_24[16]; __IO uint32_t MASTER_SEC_LEVEL; /**< Master Secure Level, offset: 0xFD0 */ __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< Master Secure Level, offset: 0xFD4 */ uint8_t RESERVED_25[20]; __IO uint32_t CPU0_LOCK_REG; /**< Miscellaneous CPU0 Control Signals, offset: 0xFEC */ __IO uint32_t CPU1_LOCK_REG; /**< Miscellaneous CPU1 Control Signals, offset: 0xFF0 */ uint8_t RESERVED_26[4]; __IO uint32_t MISC_CTRL_DP_REG; /**< Secure Control Duplicate, offset: 0xFF8 */ __IO uint32_t MISC_CTRL_REG; /**< Secure Control, offset: 0xFFC */ } AHBSC_Type; /* ---------------------------------------------------------------------------- -- AHBSC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AHBSC_Register_Masks AHBSC Register Masks * @{ */ /*! @name FLASH00_MEM_RULE - Flash Memory Rule */ /*! @{ */ #define AHBSC_FLASH00_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH00_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE0_MASK) #define AHBSC_FLASH00_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH00_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE1_MASK) #define AHBSC_FLASH00_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH00_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE2_MASK) #define AHBSC_FLASH00_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH00_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE3_MASK) #define AHBSC_FLASH00_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH00_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE4_MASK) #define AHBSC_FLASH00_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH00_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE5_MASK) #define AHBSC_FLASH00_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH00_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE6_MASK) #define AHBSC_FLASH00_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH00_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_FLASH00_MEM_RULE */ #define AHBSC_FLASH00_MEM_RULE_COUNT (4U) /*! @name FLASH01_MEM_RULE - Flash Memory Rule */ /*! @{ */ #define AHBSC_FLASH01_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_FLASH01_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH01_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE0_MASK) #define AHBSC_FLASH01_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_FLASH01_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH01_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE1_MASK) #define AHBSC_FLASH01_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_FLASH01_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH01_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE2_MASK) #define AHBSC_FLASH01_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_FLASH01_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH01_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE3_MASK) #define AHBSC_FLASH01_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_FLASH01_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH01_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE4_MASK) #define AHBSC_FLASH01_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_FLASH01_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH01_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE5_MASK) #define AHBSC_FLASH01_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_FLASH01_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH01_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE6_MASK) #define AHBSC_FLASH01_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_FLASH01_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH01_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH01_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH01_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_FLASH01_MEM_RULE */ #define AHBSC_FLASH01_MEM_RULE_COUNT (4U) /*! @name FLASH02_MEM_RULE - Flash Memory Rule */ /*! @{ */ #define AHBSC_FLASH02_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH02_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE0_MASK) #define AHBSC_FLASH02_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH02_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE1_MASK) #define AHBSC_FLASH02_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH02_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE2_MASK) #define AHBSC_FLASH02_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH02_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE3_MASK) /*! @} */ /*! @name FLASH03_MEM_RULE - Flash Memory Rule */ /*! @{ */ #define AHBSC_FLASH03_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH03_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE0_MASK) #define AHBSC_FLASH03_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH03_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE1_MASK) #define AHBSC_FLASH03_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH03_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE2_MASK) #define AHBSC_FLASH03_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH03_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE3_MASK) #define AHBSC_FLASH03_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH03_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE4_MASK) #define AHBSC_FLASH03_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH03_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE5_MASK) #define AHBSC_FLASH03_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH03_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE6_MASK) #define AHBSC_FLASH03_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLASH03_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE7_MASK) /*! @} */ /*! @name ROM_MEM_RULE - ROM Memory Rule */ /*! @{ */ #define AHBSC_ROM_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_ROM_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE0_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE0_MASK) #define AHBSC_ROM_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_ROM_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE1_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE1_MASK) #define AHBSC_ROM_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_ROM_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE2_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE2_MASK) #define AHBSC_ROM_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_ROM_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE3_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE3_MASK) #define AHBSC_ROM_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_ROM_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE4_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE4_MASK) #define AHBSC_ROM_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_ROM_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE5_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE5_MASK) #define AHBSC_ROM_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_ROM_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE6_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE6_MASK) #define AHBSC_ROM_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_ROM_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE7_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_ROM_MEM_RULE */ #define AHBSC_ROM_MEM_RULE_COUNT (4U) /*! @name RAMX_MEM_RULE0_RAMX_MEM_RULE - RAMX Memory Rule */ /*! @{ */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE */ #define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_COUNT (3U) /*! @name RAMA_MEM_RULE - RAMA Memory Rule 0 */ /*! @{ */ #define AHBSC_RAMA_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAMA_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMA_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE0_MASK) #define AHBSC_RAMA_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAMA_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMA_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE1_MASK) #define AHBSC_RAMA_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAMA_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMA_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE2_MASK) #define AHBSC_RAMA_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAMA_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMA_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE3_MASK) #define AHBSC_RAMA_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAMA_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMA_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE4_MASK) #define AHBSC_RAMA_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAMA_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMA_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE5_MASK) #define AHBSC_RAMA_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAMA_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMA_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE6_MASK) #define AHBSC_RAMA_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAMA_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMA_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE7_MASK) /*! @} */ /*! @name RAMB_MEM_RULE - RAMB Memory Rule */ /*! @{ */ #define AHBSC_RAMB_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAMB_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMB_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE0_MASK) #define AHBSC_RAMB_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAMB_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMB_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE1_MASK) #define AHBSC_RAMB_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAMB_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMB_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE2_MASK) #define AHBSC_RAMB_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAMB_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMB_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE3_MASK) #define AHBSC_RAMB_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAMB_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMB_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE4_MASK) #define AHBSC_RAMB_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAMB_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMB_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE5_MASK) #define AHBSC_RAMB_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAMB_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMB_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE6_MASK) #define AHBSC_RAMB_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAMB_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMB_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE7_MASK) /*! @} */ /*! @name RAMC_MEM_RULE - RAMC Memory Rule */ /*! @{ */ #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAMC_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMC_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK) #define AHBSC_RAMC_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAMC_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMC_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE1_MASK) #define AHBSC_RAMC_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAMC_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMC_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE2_MASK) #define AHBSC_RAMC_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAMC_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMC_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE3_MASK) #define AHBSC_RAMC_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAMC_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMC_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE4_MASK) #define AHBSC_RAMC_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAMC_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMC_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE5_MASK) #define AHBSC_RAMC_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAMC_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMC_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE6_MASK) #define AHBSC_RAMC_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAMC_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMC_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_RAMC_MEM_RULE */ #define AHBSC_RAMC_MEM_RULE_COUNT (2U) /*! @name RAMD_MEM_RULE - RAMD Memory Rule */ /*! @{ */ #define AHBSC_RAMD_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAMD_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMD_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE0_MASK) #define AHBSC_RAMD_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAMD_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMD_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE1_MASK) #define AHBSC_RAMD_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAMD_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMD_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE2_MASK) #define AHBSC_RAMD_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAMD_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMD_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE3_MASK) #define AHBSC_RAMD_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAMD_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMD_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE4_MASK) #define AHBSC_RAMD_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAMD_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMD_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE5_MASK) #define AHBSC_RAMD_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAMD_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMD_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE6_MASK) #define AHBSC_RAMD_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAMD_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMD_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_RAMD_MEM_RULE */ #define AHBSC_RAMD_MEM_RULE_COUNT (2U) /*! @name RAME_MEM_RULE - RAME Memory Rule */ /*! @{ */ #define AHBSC_RAME_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAME_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAME_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE0_MASK) #define AHBSC_RAME_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAME_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAME_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE1_MASK) #define AHBSC_RAME_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAME_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAME_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE2_MASK) #define AHBSC_RAME_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAME_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAME_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE3_MASK) #define AHBSC_RAME_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAME_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAME_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE4_MASK) #define AHBSC_RAME_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAME_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAME_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE5_MASK) #define AHBSC_RAME_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAME_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAME_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE6_MASK) #define AHBSC_RAME_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAME_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAME_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_RAME_MEM_RULE */ #define AHBSC_RAME_MEM_RULE_COUNT (2U) /*! @name RAMF_MEM_RULE - RAMF Memory Rule */ /*! @{ */ #define AHBSC_RAMF_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAMF_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMF_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE0_MASK) #define AHBSC_RAMF_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAMF_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMF_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE1_MASK) #define AHBSC_RAMF_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAMF_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMF_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE2_MASK) #define AHBSC_RAMF_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAMF_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMF_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE3_MASK) #define AHBSC_RAMF_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAMF_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMF_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE4_MASK) #define AHBSC_RAMF_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAMF_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMF_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE5_MASK) #define AHBSC_RAMF_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAMF_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMF_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE6_MASK) #define AHBSC_RAMF_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAMF_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMF_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMF_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMF_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_RAMF_MEM_RULE */ #define AHBSC_RAMF_MEM_RULE_COUNT (2U) /*! @name RAMG_MEM_RULE - RAMG Memory Rule */ /*! @{ */ #define AHBSC_RAMG_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAMG_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMG_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE0_MASK) #define AHBSC_RAMG_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAMG_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMG_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE1_MASK) #define AHBSC_RAMG_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAMG_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMG_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE2_MASK) #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAMG_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMG_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK) #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAMG_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMG_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK) #define AHBSC_RAMG_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAMG_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMG_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE5_MASK) #define AHBSC_RAMG_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAMG_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMG_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE6_MASK) #define AHBSC_RAMG_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAMG_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMG_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_RAMG_MEM_RULE */ #define AHBSC_RAMG_MEM_RULE_COUNT (2U) /*! @name RAMH_MEM_RULE - RAMH Memory Rule */ /*! @{ */ #define AHBSC_RAMH_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_RAMH_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE0_MASK) #define AHBSC_RAMH_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_RAMH_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE1_MASK) #define AHBSC_RAMH_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_RAMH_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE2_MASK) #define AHBSC_RAMH_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_RAMH_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE3_MASK) #define AHBSC_RAMH_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_RAMH_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE4_MASK) #define AHBSC_RAMH_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_RAMH_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE5_MASK) #define AHBSC_RAMH_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_RAMH_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE6_MASK) #define AHBSC_RAMH_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_RAMH_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_RAMH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMH_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMH_MEM_RULE_RULE7_MASK) /*! @} */ /*! @name APB_PERIPHERAL_GROUP0_MEM_RULE0 - APB Bridge Group 0 Memory Rule 0 */ /*! @{ */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK (0x3U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT (0U) /*! SYSCON - SYSCON * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U) /*! PINT0 - PINT0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK (0x3000000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT (24U) /*! INPUTMUX - INPUTMUX * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK) /*! @} */ /*! @name APB_PERIPHERAL_GROUP0_MEM_RULE1 - APB Bridge Group 0 Memory Rule 1 */ /*! @{ */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK (0x30000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT (16U) /*! CTIMER0 - CTIMER0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK (0x300000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT (20U) /*! CTIMER1 - CTIMER1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK (0x3000000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT (24U) /*! CTIMER2 - CTIMER2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK (0x30000000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT (28U) /*! CTIMER3 - CTIMER3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK) /*! @} */ /*! @name APB_PERIPHERAL_GROUP0_MEM_RULE2 - APB Bridge Group 0 Rule 2 */ /*! @{ */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK (0x3U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT (0U) /*! CTIMER4 - CTIMER4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK (0x30U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT (4U) /*! FREQME0 - FREQME0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK (0x300U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT (8U) /*! UTCIK0 - UTCIK0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK (0x3000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT (12U) /*! MRT0 - MRT0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK (0x30000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT (16U) /*! OSTIMER0 - OSTIMER0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK (0x3000000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT (24U) /*! WWDT0 - WWDT0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK (0x30000000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT (28U) /*! WWDT1 - WWDT1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK) /*! @} */ /*! @name APB_PERIPHERAL_GROUP0_MEM_RULE3 - APB Bridge Group 0 Memory Rule 3 */ /*! @{ */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK (0x3000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT (12U) /*! CACHE64_POLSEL0 - CACHE64_POLSEL0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK) /*! @} */ /*! @name APB_PERIPHERAL_GROUP1_MEM_RULE0 - APB Bridge Group 1 Memory Rule 0 */ /*! @{ */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK (0x30U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT (4U) /*! I3C0 - I3C0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK (0x300U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT (8U) /*! I3C1 - I3C1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK (0x300000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT (20U) /*! GDET - GDET * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK (0x3000000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT (24U) /*! ITRC - ITRC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK) /*! @} */ /*! @name APB_PERIPHERAL_GROUP1_MEM_RULE1 - APB Bridge Group 1 Memory Rule 1 */ /*! @{ */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK (0x3000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT (12U) /*! PKC - PKC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK (0x30000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT (16U) /*! PUF_ALIAS0 - PUF_ALIAS0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK (0x300000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT (20U) /*! PUF_ALIAS1 - PUF_ALIAS1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK (0x3000000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT (24U) /*! PUF_ALIAS2 - PUF_ALIAS2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK (0x30000000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT (28U) /*! PUF_ALIAS3 - PUF_ALIAS3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK) /*! @} */ /*! @name APB_PERIPHERAL_GROUP1_MEM_RULE2 - APB Bridge Group 1 Memory Rule 2 */ /*! @{ */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3_MASK (0x30U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3_SHIFT (4U) /*! SM3 - SM3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SM3_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK (0x300U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT (8U) /*! COOLFLUX - COOLFLUX * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK (0x3000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT (12U) /*! SMARTDMA - SmartDMA * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK (0x30000U) #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT (16U) /*! PLU - PLU * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP0_MEM_RULE0 - AIPS Bridge Group 0 Memory Rule 0 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT (0U) /*! GPIO5_ALIAS0 - GPIO5_ALIAS0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT (4U) /*! GPIO5_ALIAS1 - GPIO5_ALIAS2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT (8U) /*! PORT5 - PORT5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT (12U) /*! FMU0 - FMU0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT (16U) /*! SCG0 - SCG0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT (20U) /*! SPC0 - SPC0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT (24U) /*! WUU0 - WUU0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0_SHIFT (28U) /*! TRO0 - TRO0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_TRO0_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP0_MEM_RULE1 - AIPS Bridge Group 0 Memory Rule 1 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT (8U) /*! LPTMR0 - LPTMR0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT (12U) /*! LPTMR1 - LPTMR1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT (16U) /*! RTC - RTC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT (24U) /*! FMU_TEST - FMU_TEST * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP0_MEM_RULE2 - AIPS Bridge Group 0 Memory Rule 2 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT (0U) /*! TSI - TSI * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT (4U) /*! CMP0 - CMP0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT (8U) /*! CMP1 - CMP1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT (12U) /*! CMP2 - CMP2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT (16U) /*! ELS - ELS * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT (20U) /*! ELS_ALIAS1 - ELS_ALIAS1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT (24U) /*! ELS_ALIAS2 - ELS_ALIAS2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT (28U) /*! ELS_ALIAS3 - ELS_ALIAS3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP0_MEM_RULE3 - AIPS Bridge Group 0 Memory Rule 3 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT (0U) /*! DIGTMP - DIGTMP * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT (4U) /*! VBAT - VBAT * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT (8U) /*! TRNG - TRNG * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT (12U) /*! EIM0 - EIM0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT (16U) /*! ERM0 - ERM0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT (20U) /*! INTM0 - INTM0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK) /*! @} */ /*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0 - AHB Peripheral 0 Slave Port 12 Slave Rule 0 */ /*! @{ */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK (0x30U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT (4U) /*! eDMA0_CH15 - eDMA0_CH15 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK (0x300U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT (8U) /*! SCT0 - SCT0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK (0x3000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT (12U) /*! LP_FLEXCOMM0 - LP_FLEXCOMM0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK (0x30000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT (16U) /*! LP_FLEXCOMM1 - LP_FLEXCOMM1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK (0x300000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT (20U) /*! LP_FLEXCOMM2 - LP_FLEXCOMM2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK (0x3000000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT (24U) /*! LP_FLEXCOMM3 - LP_FLEXCOMM3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK (0x30000000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT (28U) /*! GPIO0_ALIAS0 - GPIO0_ALIAS0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK) /*! @} */ /*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1 - AHB Peripheral 0 Slave Port 12 Slave Rule 1 */ /*! @{ */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK (0x3U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT (0U) /*! GPIO0_ALIAS1 - GPIO0_ALIAS1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK (0x30U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT (4U) /*! GPIO1_ALIAS0 - GPIO1_ALIAS0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK (0x300U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT (8U) /*! GPIO1_ALIAS1 - GPIO1_ALIAS1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK (0x3000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT (12U) /*! GPIO2_ALIAS0 - GPIO2_ALIAS0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK (0x30000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT (16U) /*! GPIO2_ALIAS1 - GPIO2_ALIAS1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK (0x300000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT (20U) /*! GPIO3_ALIAS0 - GPIO3_ALIAS0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK (0x3000000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT (24U) /*! GPIO3_ALIAS1 - GPIO3_ALIAS1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK (0x30000000U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT (28U) /*! GPIO4_ALIAS0 - GPIO4_ALIAS0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK) /*! @} */ /*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2 - AHB Peripheral 0 Slave Port 12 Slave Rule 2 */ /*! @{ */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK (0x3U) #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT (0U) /*! GPIO4_ALIAS1 - GPIO4_ALIAS1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP1_MEM_RULE0 - AIPS Bridge Group 1 Rule 0 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT (0U) /*! eDMA0_MP - eDMA0_MP * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT (4U) /*! eDMA0_CH0 - eDMA0_CH0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT (8U) /*! eDMA0_CH1 - eDMA0_CH1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT (12U) /*! eDMA0_CH2 - eDMA0_CH2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT (16U) /*! eDMA0_CH3 - FLEXSPI0 Registers * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT (20U) /*! eDMA0_CH4 - eDMA0_CH4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT (24U) /*! eDMA0_CH5 - eDMA0_CH5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT (28U) /*! eDMA0_CH6 - eDMA0_CH6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP1_MEM_RULE1 - AIPS Bridge Group 1 Rule 1 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT (0U) /*! eDMA0_CH7 - eDMA0_CH7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT (4U) /*! eDMA0_CH8 - eDMA0_CH8 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT (8U) /*! eDMA0_CH9 - eDMA0_CH9 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT (12U) /*! eDMA0_CH10 - eDMA0_CH10 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT (16U) /*! eDMA0_CH11 - FLEXSPI0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT (20U) /*! eDMA0_CH12 - eDMA0_CH12 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT (24U) /*! eDMA0_CH13 - eDMA0_CH13 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT (28U) /*! eDMA0_CH14 - eDMA0_CH14 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK) /*! @} */ /*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0 - AHB Peripheral 1 Slave Port 13 Slave Rule 0 */ /*! @{ */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK (0x30U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT (4U) /*! eDMA1_CH15 - eDMA1_CH15 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK (0x300U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT (8U) /*! SEMA42 - SEMA42 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK (0x3000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT (12U) /*! MAILBOX - MAILBOX * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK (0x30000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT (16U) /*! PKC_RAM - PKC_RAM * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK (0x300000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT (20U) /*! FLEXCOMM4 - FLEXCOMM4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK (0x3000000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT (24U) /*! FLEXCOMM5 - FLEXCOMM5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK (0x30000000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT (28U) /*! FLEXCOMM6 - FLEXCOMM6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK) /*! @} */ /*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1 - AHB Peripheral 1 Slave Port 13 Slave Rule 1 */ /*! @{ */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK (0x3U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT (0U) /*! FLEXCOMM7 - FLEXCOMM7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK (0x30U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT (4U) /*! FLEXCOMM8 - FLEXCOMM8 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK (0x300U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT (8U) /*! FLEXCOMM9 - FLEXCOMM9 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK (0x3000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT (12U) /*! USB_FS_OTG_RAM - USB FS OTG RAM * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK (0x30000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT (16U) /*! CDOG0 - CDOG0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK (0x300000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT (20U) /*! CDOG1 - CDOG1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK (0x3000000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT (24U) /*! DEBUG_MAILBOX - DEBUG_MAILBOX * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK (0x30000000U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT (28U) /*! NPU - NPU * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK) /*! @} */ /*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2 - AHB Peripheral 1 Slave Port 13 Slave Rule 2 */ /*! @{ */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD_MASK (0x3U) #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD_SHIFT (0U) /*! POWERQUAD - POWERQUAD * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2_POWERQUAD_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP2_MEM_RULE0 - AIPS Bridge Group 2 Rule 0 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT (0U) /*! eDMA1_MP - eDMA1_MP * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT (4U) /*! eDMA1_CH0 - eDMA1_CH0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT (8U) /*! eDMA1_CH1 - eDMA1_CH1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT (12U) /*! eDMA1_CH2 - eDMA1_CH2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT (16U) /*! eDMA1_CH3 - eDMA1_CH3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT (20U) /*! eDMA1_CH4 - eDMA1_CH4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT (24U) /*! eDMA1_CH5 - eDMA1_CH5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT (28U) /*! eDMA1_CH6 - eDMA1_CH6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP2_MEM_RULE1 - AIPS Bridge Group 2 Memory Rule 1 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT (0U) /*! eDMA1_CH7 - eDMA1_CH7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8_SHIFT (4U) /*! eDMA1_CH8 - eDMA1_CH8 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH8_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9_SHIFT (8U) /*! eDMA1_CH9 - eDMA1_CH9 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH9_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10_SHIFT (12U) /*! eDMA1_CH10 - eDMA1_CH10 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH10_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11_SHIFT (16U) /*! eDMA1_CH11 - eDMA1_CH11 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH11_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12_SHIFT (20U) /*! eDMA1_CH12 - eDMA1_CH12 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH12_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13_SHIFT (24U) /*! eDMA1_CH13 - eDMA1_CH13 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH13_MASK) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14_SHIFT (28U) /*! eDMA1_CH14 - eDMA1_CH14 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH14_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP3_MEM_RULE0 - AIPS Bridge Group 3 Rule 0 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT (0U) /*! EWM0 - EWM0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT (4U) /*! LPCAC - LPCAC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT (8U) /*! FLEXSPI_CMX - FLEXSPI_CMX * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT (20U) /*! SFA - SFA * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT (28U) /*! MBC - MBC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP3_MEM_RULE1 - AIPS Bridge Group 3 Memory Rule 1 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT (0U) /*! FLEXSPI - FLEXSPI * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT (4U) /*! OTPC - OTPC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT (12U) /*! CRC - CRC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT (16U) /*! NPX - NPX * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT (24U) /*! PWM - PWM * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC_SHIFT (28U) /*! ENC - ENC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_ENC_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP3_MEM_RULE2 - AIPS Bridge Group 3 Rule 2 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT (0U) /*! PWM1 - PWM1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1_SHIFT (4U) /*! ENC1 - ENC1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_ENC1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT (8U) /*! EVTG - EVTG * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT (16U) /*! CAN0_RULE0 - CAN0 RULE0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT (20U) /*! CAN0_RULE1 - CAN0 RULE1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT (24U) /*! CAN0_RULE2 - CAN0 RULE2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT (28U) /*! CAN0_RULE3 - CAN0 RULE3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP3_MEM_RULE3 - AIPS Bridge Group 3 Rule 3 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT (0U) /*! CAN1_RULE0 - CAN1 RULE0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT (4U) /*! CAN1_RULE1 - CAN1 RULE1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT (8U) /*! CAN1_RULE2 - CAN1 RULE2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT (12U) /*! CAN1_RULE3 - CAN1 RULE3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT (16U) /*! USBDCD - USBDCD * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT (20U) /*! USBFS - USBFS * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP4_MEM_RULE0 - AIPS Bridge Group 4 Rule 0 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK (0xFU) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT (0U) /*! ENET - ENET * 0b0000..Non-secure and non-privilege user access allowed * 0b0001..Non-secure and privilege access allowed * 0b0010..Secure and non-privilege user access allowed * 0b0011..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT (12U) /*! EMVSIM0 - EMVSIM0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT (16U) /*! EMVSIM1 - EMVSIM1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT (20U) /*! FLEXIO - FLEXIO * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT (24U) /*! SAI0 - SAI0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT (28U) /*! SAI1 - SAI1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP4_MEM_RULE1 - AIPS Bridge Group 4 Rule 1 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT (0U) /*! SINC0 - SINC0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT (4U) /*! uSDHC0 - uSDHC0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT (8U) /*! USBHSPHY - USBHSPHY * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT (12U) /*! USBHS - USBHS * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT (16U) /*! MICD - MICD * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT (20U) /*! ADC0 - ADC0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT (24U) /*! ADC1 - ADC1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT (28U) /*! DAC0 - DAC0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP4_MEM_RULE2 - AIPS Bridge Group 4 Rule 2 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT (0U) /*! OPAMP0 - OPAMP0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT (4U) /*! VREF - VREF * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT (8U) /*! DAC - DAC * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK (0x3000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT (12U) /*! OPAMP1 - OPAMP1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK (0x30000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT (16U) /*! HPDAC0 - HPDAC0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK (0x300000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT (20U) /*! OPAMP2 - OPAMP2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT (24U) /*! PORT0 - PORT0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT (28U) /*! PORT1 - PORT1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK) /*! @} */ /*! @name AIPS_BRIDGE_GROUP4_MEM_RULE3 - AIPS Bridge Group 4 Rule 3 */ /*! @{ */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK (0x3U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT (0U) /*! PORT2 - PORT2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK (0x30U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT (4U) /*! PORT3 - PORT3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK (0x300U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT (8U) /*! PORT4 - PORT4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK (0x3000000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT (24U) /*! MTR0 - MTR0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK (0x30000000U) #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT (28U) /*! ATX0 - ATX0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK) /*! @} */ /*! @name AHB_SECURE_CTRL_PERIPHERAL_RULE0 - AHB Secure Control Peripheral Rule 0 */ /*! @{ */ #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK (0x3U) #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK) #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK (0x30U) #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK) #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK (0x300U) #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK) #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK (0x3000U) #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK) /*! @} */ /*! @name FLEXSPI0_REGION0_MEM_RULE - FLEXSPI0 Region 0 Memory Rule */ /*! @{ */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_FLEXSPI0_REGION0_MEM_RULE */ #define AHBSC_FLEXSPI0_REGION0_MEM_RULE_COUNT (4U) /*! @name FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 - FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 6 Memory Rule 0 */ /*! @{ */ #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK (0x3U) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK (0x30U) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK (0x300U) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK (0x3000U) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_MASK (0x30000U) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_MASK) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_MASK (0x300000U) #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_SHIFT)) & AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_MASK) /*! @} */ /* The count of AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 */ #define AHBSC_FLEXSPI0_REGION1_6_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_COUNT (6U) /*! @name FLEXSPI0_REGION7_MEM_RULE - FLEXSPI0 Region 7 Memory Rule */ /*! @{ */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0_MASK (0x3U) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE0_MASK) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1_MASK (0x30U) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE1_MASK) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2_MASK (0x300U) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE2_MASK) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3_MASK (0x3000U) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE3_MASK) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4_MASK (0x30000U) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE4_MASK) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5_MASK (0x300000U) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE5_MASK) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6_MASK (0x3000000U) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - Rule 6 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE6_MASK) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7_MASK (0x30000000U) #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - Rule 7 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLEXSPI0_REGION7_MEM_RULE_RULE7_MASK) /*! @} */ /* The count of AHBSC_FLEXSPI0_REGION7_MEM_RULE */ #define AHBSC_FLEXSPI0_REGION7_MEM_RULE_COUNT (4U) /*! @name FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 - FLEXSPI0 Region 8 Memory Rule 0..FLEXSPI0 Region 13 Memory Rule 0 */ /*! @{ */ #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK (0x3U) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT (0U) /*! RULE0 - Rule 0 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK (0x30U) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT (4U) /*! RULE1 - Rule 1 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK (0x300U) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT (8U) /*! RULE2 - Rule 2 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK (0x3000U) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT (12U) /*! RULE3 - Rule 3 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_MASK (0x30000U) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_SHIFT (16U) /*! RULE4 - Rule 4 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE4_MASK) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_MASK (0x300000U) #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_SHIFT (20U) /*! RULE5 - Rule 5 * 0b00..Non-secure and non-privilege user access allowed * 0b01..Non-secure and privilege access allowed * 0b10..Secure and non-privilege user access allowed * 0b11..Secure and privilege user access allowed */ #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_SHIFT)) & AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE5_MASK) /*! @} */ /* The count of AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 */ #define AHBSC_FLEXSPI0_REGION8_13_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_COUNT (6U) /*! @name SEC_VIO_ADDRN_SEC_VIO_ADDR - Security Violation Address */ /*! @{ */ #define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) #define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) /*! SEC_VIO_ADDR - Security violation address for AHB layer a reset value 0 */ #define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) /*! @} */ /* The count of AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR */ #define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_COUNT (32U) /*! @name SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */ /*! @{ */ #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) /*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator * 0b0..Read access * 0b1..Write access */ #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) /*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access * 0b0..Code * 0b1..Data */ #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) /*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level */ #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0x1F00U) #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) /*! SEC_VIO_INFO_MASTER - Security violation master number * 0b00000..M33 Code * 0b00001..M33 System * 0b00010..CPU1 (Mirco-CM33) Code * 0b00011..SMARTDMA Instruction * 0b00100..CPU1 (Mirco-CM33) system * 0b00101..SMARTDMA Data * 0b00110..eDMA0 * 0b00111..eDMA1 * 0b01000..PKC * 0b01001..ELS S50 * 0b01010..PKC M0 * 0b01011..NPU Operands * 0b01100..DSP Instruction * 0b01101..DSPX * 0b01110..DSPY * 0b10000..NPU Data * 0b10001..USB FS * 0b10010..Ethernet * 0b10011..USB HS * 0b10100..uSDHC */ #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) /*! @} */ /* The count of AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO */ #define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_COUNT (32U) /*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */ /*! @{ */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) /*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) /*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) /*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) /*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) /*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) /*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) /*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) /*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) /*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) /*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) /*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) /*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U) /*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U) /*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U) /*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U) /*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U) /*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U) /*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U) #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U) /*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18 * 0b0..Not valid * 0b1..Valid */ #define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK) /*! @} */ /*! @name SEC_GPIO_MASKN_SEC_GPIO_MASK - GPIO Mask for Port 0..GPIO Mask for Port 1 */ /*! @{ */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK (0x1U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT (0U) /*! PIO0_PIN0_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK (0x1U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT (0U) /*! PIO1_PIN0_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK (0x2U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT (1U) /*! PIO0_PIN1_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK (0x2U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT (1U) /*! PIO1_PIN1_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK (0x4U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT (2U) /*! PIO0_PIN2_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK (0x4U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT (2U) /*! PIO1_PIN2_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK (0x8U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT (3U) /*! PIO0_PIN3_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK (0x8U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT (3U) /*! PIO1_PIN3_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK (0x10U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT (4U) /*! PIO0_PIN4_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK (0x10U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT (4U) /*! PIO1_PIN4_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK (0x20U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT (5U) /*! PIO0_PIN5_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK (0x20U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT (5U) /*! PIO1_PIN5_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK (0x40U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT (6U) /*! PIO0_PIN6_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK (0x40U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT (6U) /*! PIO1_PIN6_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK (0x80U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT (7U) /*! PIO0_PIN7_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK (0x80U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT (7U) /*! PIO1_PIN7_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK (0x100U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT (8U) /*! PIO0_PIN8_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK (0x100U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT (8U) /*! PIO1_PIN8_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK (0x200U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT (9U) /*! PIO0_PIN9_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK (0x200U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT (9U) /*! PIO1_PIN9_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK (0x400U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT (10U) /*! PIO0_PIN10_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK (0x400U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT (10U) /*! PIO1_PIN10_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK (0x800U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT (11U) /*! PIO0_PIN11_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK (0x800U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT (11U) /*! PIO1_PIN11_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK (0x1000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT (12U) /*! PIO0_PIN12_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK (0x1000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT (12U) /*! PIO1_PIN12_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK (0x2000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT (13U) /*! PIO0_PIN13_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK (0x2000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT (13U) /*! PIO1_PIN13_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK (0x4000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT (14U) /*! PIO0_PIN14_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK (0x4000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT (14U) /*! PIO1_PIN14_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK (0x8000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT (15U) /*! PIO0_PIN15_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK (0x8000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT (15U) /*! PIO1_PIN15_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK (0x10000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT (16U) /*! PIO0_PIN16_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK (0x10000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT (16U) /*! PIO1_PIN16_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK (0x20000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT (17U) /*! PIO0_PIN17_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK (0x20000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT (17U) /*! PIO1_PIN17_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK (0x40000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT (18U) /*! PIO0_PIN18_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK (0x40000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT (18U) /*! PIO1_PIN18_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK (0x80000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT (19U) /*! PIO0_PIN19_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK (0x80000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT (19U) /*! PIO1_PIN19_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK (0x100000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT (20U) /*! PIO0_PIN20_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK (0x100000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT (20U) /*! PIO1_PIN20_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK (0x200000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT (21U) /*! PIO0_PIN21_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK (0x200000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT (21U) /*! PIO1_PIN21_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK (0x400000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT (22U) /*! PIO0_PIN22_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK (0x400000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT (22U) /*! PIO1_PIN22_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK (0x800000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT (23U) /*! PIO0_PIN23_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK (0x800000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT (23U) /*! PIO1_PIN23_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT (24U) /*! PIO0_PIN24_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT (24U) /*! PIO1_PIN24_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT (25U) /*! PIO0_PIN25_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT (25U) /*! PIO1_PIN25_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT (26U) /*! PIO0_PIN26_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT (26U) /*! PIO1_PIN26_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT (27U) /*! PIO0_PIN27_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT (27U) /*! PIO1_PIN27_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT (28U) /*! PIO0_PIN28_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT (28U) /*! PIO1_PIN28_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT (29U) /*! PIO0_PIN29_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT (29U) /*! PIO1_PIN29_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT (30U) /*! PIO0_PIN30_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT (30U) /*! PIO1_PIN30_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT (31U) /*! PIO0_PIN31_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT (31U) /*! PIO1_PIN31_SEC_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK) /*! @} */ /* The count of AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK */ #define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_COUNT (2U) /*! @name SEC_CPU1_INT_MASK0 - Secure Interrupt Mask 0 for CPU1 */ /*! @{ */ #define AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK_MASK (0x1U) #define AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK_SHIFT (0U) /*! INT0_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT0_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK_MASK (0x2U) #define AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK_SHIFT (1U) /*! INT1_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT1_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK_MASK (0x4U) #define AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK_SHIFT (2U) /*! INT2_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT2_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK_MASK (0x8U) #define AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK_SHIFT (3U) /*! INT3_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT3_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK_MASK (0x10U) #define AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK_SHIFT (4U) /*! INT4_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT4_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK_MASK (0x20U) #define AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK_SHIFT (5U) /*! INT5_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT5_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK_MASK (0x40U) #define AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK_SHIFT (6U) /*! INT6_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT6_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK_MASK (0x80U) #define AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK_SHIFT (7U) /*! INT7_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT7_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK_MASK (0x100U) #define AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK_SHIFT (8U) /*! INT8_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT8_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK_MASK (0x200U) #define AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK_SHIFT (9U) /*! INT9_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT9_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK_MASK (0x400U) #define AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK_SHIFT (10U) /*! INT10_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT10_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK_MASK (0x800U) #define AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK_SHIFT (11U) /*! INT11_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT11_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK_MASK (0x1000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK_SHIFT (12U) /*! INT12_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT12_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK_MASK (0x2000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK_SHIFT (13U) /*! INT13_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT13_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK_MASK (0x4000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK_SHIFT (14U) /*! INT14_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT14_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK_MASK (0x8000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK_SHIFT (15U) /*! INT15_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT15_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK_MASK (0x10000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK_SHIFT (16U) /*! INT16_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT16_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK_MASK (0x20000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK_SHIFT (17U) /*! INT17_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT17_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK_MASK (0x40000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK_SHIFT (18U) /*! INT18_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT18_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK_MASK (0x80000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK_SHIFT (19U) /*! INT19_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT19_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK_MASK (0x100000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK_SHIFT (20U) /*! INT20_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT20_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK_MASK (0x200000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK_SHIFT (21U) /*! INT21_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT21_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK_MASK (0x400000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK_SHIFT (22U) /*! INT22_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT22_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK_MASK (0x800000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK_SHIFT (23U) /*! INT23_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT23_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK_MASK (0x1000000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK_SHIFT (24U) /*! INT24_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT24_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK_MASK (0x2000000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK_SHIFT (25U) /*! INT25_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT25_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK_MASK (0x4000000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK_SHIFT (26U) /*! INT26_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT26_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK_MASK (0x8000000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK_SHIFT (27U) /*! INT27_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT27_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK_MASK (0x10000000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK_SHIFT (28U) /*! INT28_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT28_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK_MASK (0x20000000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK_SHIFT (29U) /*! INT29_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT29_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK_MASK (0x40000000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK_SHIFT (30U) /*! INT30_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT30_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK_MASK (0x80000000U) #define AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK_SHIFT (31U) /*! INT31_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK0_INT31_MASK_MASK) /*! @} */ /*! @name SEC_CPU1_INT_MASK1 - Secure Interrupt Mask 1 for CPU1 */ /*! @{ */ #define AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK_MASK (0x1U) #define AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK_SHIFT (0U) /*! INT32_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT32_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK_MASK (0x2U) #define AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK_SHIFT (1U) /*! INT33_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT33_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK_MASK (0x4U) #define AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK_SHIFT (2U) /*! INT34_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT34_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK_MASK (0x8U) #define AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK_SHIFT (3U) /*! INT35_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT35_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK_MASK (0x10U) #define AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK_SHIFT (4U) /*! INT36_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT36_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK_MASK (0x20U) #define AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK_SHIFT (5U) /*! INT37_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT37_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK_MASK (0x40U) #define AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK_SHIFT (6U) /*! INT38_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT38_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK_MASK (0x80U) #define AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK_SHIFT (7U) /*! INT39_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT39_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK_MASK (0x100U) #define AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK_SHIFT (8U) /*! INT40_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT40_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK_MASK (0x200U) #define AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK_SHIFT (9U) /*! INT41_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT41_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK_MASK (0x400U) #define AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK_SHIFT (10U) /*! INT42_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT42_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK_MASK (0x800U) #define AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK_SHIFT (11U) /*! INT43_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT43_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK_MASK (0x1000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK_SHIFT (12U) /*! INT44_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT44_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK_MASK (0x2000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK_SHIFT (13U) /*! INT45_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT45_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK_MASK (0x4000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK_SHIFT (14U) /*! INT46_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT46_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK_MASK (0x8000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK_SHIFT (15U) /*! INT47_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT47_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK_MASK (0x10000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK_SHIFT (16U) /*! INT48_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT48_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK_MASK (0x20000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK_SHIFT (17U) /*! INT49_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT49_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK_MASK (0x40000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK_SHIFT (18U) /*! INT50_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT50_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK_MASK (0x80000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK_SHIFT (19U) /*! INT51_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT51_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK_MASK (0x100000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK_SHIFT (20U) /*! INT52_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT52_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK_MASK (0x200000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK_SHIFT (21U) /*! INT53_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT53_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK_MASK (0x400000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK_SHIFT (22U) /*! INT54_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT54_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK_MASK (0x800000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK_SHIFT (23U) /*! INT55_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT55_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK_MASK (0x1000000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK_SHIFT (24U) /*! INT56_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT56_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK_MASK (0x2000000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK_SHIFT (25U) /*! INT57_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT57_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK_MASK (0x4000000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK_SHIFT (26U) /*! INT58_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT58_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK_MASK (0x8000000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK_SHIFT (27U) /*! INT59_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT59_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK_MASK (0x10000000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK_SHIFT (28U) /*! INT60_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT60_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK_MASK (0x20000000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK_SHIFT (29U) /*! INT61_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT61_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK_MASK (0x40000000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK_SHIFT (30U) /*! INT62_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT62_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK_MASK (0x80000000U) #define AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK_SHIFT (31U) /*! INT63_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK1_INT63_MASK_MASK) /*! @} */ /*! @name SEC_CPU1_INT_MASK2 - Secure Interrupt Mask 2 for CPU1 */ /*! @{ */ #define AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK_MASK (0x1U) #define AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK_SHIFT (0U) /*! INT64_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT64_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK_MASK (0x2U) #define AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK_SHIFT (1U) /*! INT65_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT65_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK_MASK (0x4U) #define AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK_SHIFT (2U) /*! INT66_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT66_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK_MASK (0x8U) #define AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK_SHIFT (3U) /*! INT67_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT67_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK_MASK (0x10U) #define AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK_SHIFT (4U) /*! INT68_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT68_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK_MASK (0x20U) #define AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK_SHIFT (5U) /*! INT69_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT69_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK_MASK (0x40U) #define AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK_SHIFT (6U) /*! INT70_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT70_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK_MASK (0x80U) #define AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK_SHIFT (7U) /*! INT71_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT71_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK_MASK (0x100U) #define AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK_SHIFT (8U) /*! INT72_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT72_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK_MASK (0x200U) #define AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK_SHIFT (9U) /*! INT73_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT73_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK_MASK (0x400U) #define AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK_SHIFT (10U) /*! INT74_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT74_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK_MASK (0x800U) #define AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK_SHIFT (11U) /*! INT75_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT75_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK_MASK (0x1000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK_SHIFT (12U) /*! INT76_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT76_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK_MASK (0x2000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK_SHIFT (13U) /*! INT77_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT77_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK_MASK (0x4000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK_SHIFT (14U) /*! INT78_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT78_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK_MASK (0x8000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK_SHIFT (15U) /*! INT79_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT79_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK_MASK (0x10000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK_SHIFT (16U) /*! INT80_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT80_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK_MASK (0x20000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK_SHIFT (17U) /*! INT81_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT81_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK_MASK (0x40000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK_SHIFT (18U) /*! INT82_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT82_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK_MASK (0x80000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK_SHIFT (19U) /*! INT83_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT83_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK_MASK (0x100000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK_SHIFT (20U) /*! INT84_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT84_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK_MASK (0x200000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK_SHIFT (21U) /*! INT85_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT85_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK_MASK (0x400000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK_SHIFT (22U) /*! INT86_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT86_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK_MASK (0x800000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK_SHIFT (23U) /*! INT87_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT87_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK_MASK (0x1000000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK_SHIFT (24U) /*! INT88_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT88_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK_MASK (0x2000000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK_SHIFT (25U) /*! INT89_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT89_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK_MASK (0x4000000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK_SHIFT (26U) /*! INT90_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT90_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK_MASK (0x8000000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK_SHIFT (27U) /*! INT91_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT91_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK_MASK (0x10000000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK_SHIFT (28U) /*! INT92_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT92_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK_MASK (0x20000000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK_SHIFT (29U) /*! INT93_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT93_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK_MASK (0x40000000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK_SHIFT (30U) /*! INT94_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT94_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK_MASK (0x80000000U) #define AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK_SHIFT (31U) /*! INT95_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK2_INT95_MASK_MASK) /*! @} */ /*! @name SEC_CPU1_INT_MASK3 - Secure Interrupt Mask 3 for CPU1 */ /*! @{ */ #define AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK_MASK (0x1U) #define AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK_SHIFT (0U) /*! INT96_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT96_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK_MASK (0x2U) #define AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK_SHIFT (1U) /*! INT97_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT97_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK_MASK (0x4U) #define AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK_SHIFT (2U) /*! INT98_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT98_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK_MASK (0x8U) #define AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK_SHIFT (3U) /*! INT99_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT99_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK_MASK (0x10U) #define AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK_SHIFT (4U) /*! INT100_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT100_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK_MASK (0x20U) #define AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK_SHIFT (5U) /*! INT101_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT101_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK_MASK (0x40U) #define AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK_SHIFT (6U) /*! INT102_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT102_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK_MASK (0x80U) #define AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK_SHIFT (7U) /*! INT103_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT103_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK_MASK (0x100U) #define AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK_SHIFT (8U) /*! INT104_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT104_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK_MASK (0x200U) #define AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK_SHIFT (9U) /*! INT105_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT105_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK_MASK (0x400U) #define AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK_SHIFT (10U) /*! INT106_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT106_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK_MASK (0x800U) #define AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK_SHIFT (11U) /*! INT107_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT107_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK_MASK (0x1000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK_SHIFT (12U) /*! INT108_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT108_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK_MASK (0x2000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK_SHIFT (13U) /*! INT109_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT109_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK_MASK (0x4000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK_SHIFT (14U) /*! INT110_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT110_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK_MASK (0x8000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK_SHIFT (15U) /*! INT111_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT111_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK_MASK (0x10000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK_SHIFT (16U) /*! INT112_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT112_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK_MASK (0x20000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK_SHIFT (17U) /*! INT113_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT113_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK_MASK (0x40000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK_SHIFT (18U) /*! INT114_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT114_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK_MASK (0x80000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK_SHIFT (19U) /*! INT115_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT115_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK_MASK (0x100000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK_SHIFT (20U) /*! INT116_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT116_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK_MASK (0x200000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK_SHIFT (21U) /*! INT117_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT117_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK_MASK (0x400000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK_SHIFT (22U) /*! INT118_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT118_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK_MASK (0x800000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK_SHIFT (23U) /*! INT119_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT119_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK_MASK (0x1000000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK_SHIFT (24U) /*! INT120_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT120_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK_MASK (0x2000000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK_SHIFT (25U) /*! INT121_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT121_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK_MASK (0x4000000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK_SHIFT (26U) /*! INT122_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT122_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK_MASK (0x8000000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK_SHIFT (27U) /*! INT123_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT123_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK_MASK (0x10000000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK_SHIFT (28U) /*! INT124_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT124_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK_MASK (0x20000000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK_SHIFT (29U) /*! INT125_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT125_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK_MASK (0x40000000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK_SHIFT (30U) /*! INT126_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT126_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK_MASK (0x80000000U) #define AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK_SHIFT (31U) /*! INT127_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK3_INT127_MASK_MASK) /*! @} */ /*! @name SEC_CPU1_INT_MASK4 - Secure Interrupt Mask 4 for CPU1 */ /*! @{ */ #define AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK_MASK (0x1U) #define AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK_SHIFT (0U) /*! INT128_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT128_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK_MASK (0x2U) #define AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK_SHIFT (1U) /*! INT129_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT129_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK_MASK (0x4U) #define AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK_SHIFT (2U) /*! INT130_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT130_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK_MASK (0x8U) #define AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK_SHIFT (3U) /*! INT131_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT131_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK_MASK (0x10U) #define AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK_SHIFT (4U) /*! INT132_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT132_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK_MASK (0x20U) #define AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK_SHIFT (5U) /*! INT133_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT133_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK_MASK (0x40U) #define AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK_SHIFT (6U) /*! INT134_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT134_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK_MASK (0x80U) #define AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK_SHIFT (7U) /*! INT135_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT135_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK_MASK (0x100U) #define AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK_SHIFT (8U) /*! INT136_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT136_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK_MASK (0x200U) #define AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK_SHIFT (9U) /*! INT137_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT137_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK_MASK (0x400U) #define AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK_SHIFT (10U) /*! INT138_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT138_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK_MASK (0x800U) #define AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK_SHIFT (11U) /*! INT139_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT139_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK_MASK (0x1000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK_SHIFT (12U) /*! INT140_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT140_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK_MASK (0x2000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK_SHIFT (13U) /*! INT141_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT141_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK_MASK (0x4000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK_SHIFT (14U) /*! INT142_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT142_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK_MASK (0x8000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK_SHIFT (15U) /*! INT143_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT143_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK_MASK (0x10000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK_SHIFT (16U) /*! INT144_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT144_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK_MASK (0x20000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK_SHIFT (17U) /*! INT145_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT145_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK_MASK (0x40000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK_SHIFT (18U) /*! INT146_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT146_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK_MASK (0x80000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK_SHIFT (19U) /*! INT147_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT147_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK_MASK (0x100000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK_SHIFT (20U) /*! INT148_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT148_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK_MASK (0x200000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK_SHIFT (21U) /*! INT149_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT149_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK_MASK (0x400000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK_SHIFT (22U) /*! INT150_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT150_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK_MASK (0x800000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK_SHIFT (23U) /*! INT151_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT151_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK_MASK (0x1000000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK_SHIFT (24U) /*! INT152_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT152_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK_MASK (0x2000000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK_SHIFT (25U) /*! INT153_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT153_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK_MASK (0x4000000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK_SHIFT (26U) /*! INT154_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT154_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK_MASK (0x8000000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK_SHIFT (27U) /*! INT155_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT155_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK_MASK (0x10000000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK_SHIFT (28U) /*! INT156_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT156_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK_MASK (0x20000000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK_SHIFT (29U) /*! INT157_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT157_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK_MASK (0x40000000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK_SHIFT (30U) /*! INT158_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT158_MASK_MASK) #define AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK_MASK (0x80000000U) #define AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK_SHIFT (31U) /*! INT159_MASK - Mask bit * 0b0..Masked * 0b1..Not masked */ #define AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK_SHIFT)) & AHBSC_SEC_CPU1_INT_MASK4_INT159_MASK_MASK) /*! @} */ /*! @name SEC_GP_REG_LOCK - Secure Mask Lock */ /*! @{ */ #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) /*! SEC_GPIO_MASK0_LOCK - Secure GPIO _MASK0 Lock * 0b00..Reserved * 0b01..SEC_GPIO_MASK0 cannot be written * 0b10..SEC_GPIO_MASK0 can be written * 0b11..Reserved */ #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK) #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) /*! SEC_GPIO_MASK1_LOCK - Secure GPIO _MASK1 Lock * 0b00..Reserved * 0b01..SEC_GPIO_MASK1 cannot be written * 0b10..SEC_GPIO_MASK1 can be written * 0b11..Reserved */ #define AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x3000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (12U) /*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU1_INT_MASK0 Lock * 0b00..Reserved * 0b01..SEC_GPIO_MASK0 cannot be written * 0b10..SEC_GPIO_MASK0 can be written * 0b11..Reserved */ #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (14U) /*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU1_INT_MASK1 Lock * 0b00..Reserved * 0b01..SEC_GPIO_MASK1 cannot be written * 0b10..SEC_GPIO_MASK1 can be written * 0b11..Reserved */ #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK_MASK (0x30000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK_SHIFT (16U) /*! SEC_CPU1_INT_MASK2_LOCK - SEC_CPU1_INT_MASK2 Lock * 0b00..Reserved * 0b01..SEC_CPU1_INT_MASK2 cannot be written * 0b10..SEC_CPU1_INT_MASK2 can be written * 0b11..Reserved */ #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK2_LOCK_MASK) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK_MASK (0xC0000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK_SHIFT (18U) /*! SEC_CPU1_INT_MASK3_LOCK - SEC_CPU1_INT_MASK3 Lock * 0b00..Reserved * 0b01..SEC_CPU1_INT_MASK3 cannot be written * 0b10..SEC_CPU1_INT_MASK3 can be written * 0b11..Reserved */ #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK3_LOCK_MASK) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK_MASK (0x300000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK_SHIFT (20U) /*! SEC_CPU1_INT_MASK4_LOCK - SEC_CPU1_INT_MASK4 Lock * 0b00..Reserved * 0b01..SEC_CPU1_INT_MASK4 cannot be written * 0b10..SEC_CPU1_INT_MASK4 can be written * 0b11..Reserved */ #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK_SHIFT)) & AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK4_LOCK_MASK) /*! @} */ /*! @name MASTER_SEC_LEVEL - Master Secure Level */ /*! @{ */ #define AHBSC_MASTER_SEC_LEVEL_CPU1_MASK (0xCU) #define AHBSC_MASTER_SEC_LEVEL_CPU1_SHIFT (2U) /*! CPU1 - CPU1 * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_CPU1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_CPU1_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_CPU1_MASK) #define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK (0x30U) #define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT (4U) /*! SMARTDMA - SMARTDMA Data * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK) #define AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK (0xC0U) #define AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT (6U) /*! eDMA0 - eDMA0 * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_EDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK) #define AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK (0x300U) #define AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT (8U) /*! eDMA1 - eDMA1 * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK) #define AHBSC_MASTER_SEC_LEVEL_PKC_MASK (0xC00U) #define AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT (10U) /*! PKC - PKC * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_PKC_MASK) #define AHBSC_MASTER_SEC_LEVEL_PQ_MASK (0xC000U) #define AHBSC_MASTER_SEC_LEVEL_PQ_SHIFT (14U) /*! PQ - PowerQuad * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_PQ_MASK) #define AHBSC_MASTER_SEC_LEVEL_NPUO_MASK (0x30000U) #define AHBSC_MASTER_SEC_LEVEL_NPUO_SHIFT (16U) /*! NPUO - NPU Operands * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_NPUO(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_NPUO_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_NPUO_MASK) #define AHBSC_MASTER_SEC_LEVEL_COOLFLUXI_MASK (0xC0000U) #define AHBSC_MASTER_SEC_LEVEL_COOLFLUXI_SHIFT (18U) /*! COOLFLUXI - Coolflux Instruction * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_COOLFLUXI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_COOLFLUXI_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_COOLFLUXI_MASK) #define AHBSC_MASTER_SEC_LEVEL_USB_FS_MASK (0xC00000U) #define AHBSC_MASTER_SEC_LEVEL_USB_FS_SHIFT (22U) /*! USB_FS - USB_FS * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USB_FS_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USB_FS_MASK) #define AHBSC_MASTER_SEC_LEVEL_ETHERNET_MASK (0x3000000U) #define AHBSC_MASTER_SEC_LEVEL_ETHERNET_SHIFT (24U) /*! ETHERNET - Ethernet * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_ETHERNET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_ETHERNET_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_ETHERNET_MASK) #define AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK (0xC000000U) #define AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT (26U) /*! USB_HS - USB HS * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK) #define AHBSC_MASTER_SEC_LEVEL_USDHC_MASK (0x30000000U) #define AHBSC_MASTER_SEC_LEVEL_USDHC_SHIFT (28U) /*! USDHC - uSDHC * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define AHBSC_MASTER_SEC_LEVEL_USDHC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USDHC_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USDHC_MASK) #define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) #define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) /*! MASTER_SEC_LEVEL_LOCK - Master SEC Level Lock * 0b00..Reserved * 0b01..MASTER_SEC_LEVEL_LOCK cannot be written * 0b10..MASTER_SEC_LEVEL_LOCK can be written * 0b11..Reserved */ #define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) /*! @} */ /*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */ /*! @{ */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1_MASK (0xCU) #define AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1_SHIFT (2U) /*! CPU1 - CPU1 * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_CPU1_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK (0x30U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT (4U) /*! SMARTDMA - SMARTDMA Data * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK (0xC0U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT (6U) /*! eDMA0 - eDMA0 * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK (0x300U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT (8U) /*! eDMA1 - eDMA1 * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK (0xC00U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT (10U) /*! PKC - PKC * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC000U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (14U) /*! PQ - PowerQuad * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_PQ_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO_MASK (0x30000U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO_SHIFT (16U) /*! NPUO - NPU Operands * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_NPUO_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI_MASK (0xC0000U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI_SHIFT (18U) /*! COOLFLUXI - Coolflux Instruction * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_COOLFLUXI_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS_MASK (0xC00000U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS_SHIFT (22U) /*! USB_FS - USB_FS * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USB_FS_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET_MASK (0x3000000U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET_SHIFT (24U) /*! ETHERNET - Ethernet * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_ETHERNET_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK (0xC000000U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT (26U) /*! USB_HS - USB HS * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC_MASK (0x30000000U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC_SHIFT (28U) /*! USDHC - uSDHC * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USDHC_MASK) #define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) #define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) /*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master SEC Level Antipol Lock * 0b00..Reserved * 0b01..MASTER_SEC_LEVEL_LOCK cannot be written * 0b10..MASTER_SEC_LEVEL_LOCK can be written * 0b11..Reserved */ #define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) /*! @} */ /*! @name CPU0_LOCK_REG - Miscellaneous CPU0 Control Signals */ /*! @{ */ #define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) #define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) /*! LOCK_NS_VTOR - LOCK_NS_VTOR * 0b00..Reserved * 0b01..CM33 (CPU0) LOCKNSVTOR is 1 * 0b10..CM33 (CPU0) LOCKNSVTOR is 0 * 0b11..Reserved */ #define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) #define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) #define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) /*! LOCK_NS_MPU - LOCK_NS_MPU * 0b00..Reserved * 0b01..CM33 (CPU0) LOCK_NS_MPU is 1 * 0b10..CM33 (CPU0) LOCK_NS_MPU is 0 * 0b11..Reserved */ #define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) #define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) #define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) /*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR * 0b00..Reserved * 0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1 * 0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0 * 0b11..Reserved */ #define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) #define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) #define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) /*! LOCK_S_MPU - LOCK_S_MPU * 0b00..Reserved * 0b01..CM33 (CPU0) LOCK_S_MPU is 1 * 0b10..CM33 (CPU0) LOCK_S_MPU is 0 * 0b11..Reserved */ #define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK) #define AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) #define AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) /*! LOCK_SAU - LOCK_SAU * 0b00..Reserved * 0b01..CM33 (CPU0) LOCK_SAU is 1 * 0b10..CM33 (CPU0) LOCK_SAU is 0 * 0b11..Reserved */ #define AHBSC_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK) #define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) #define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) /*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG_LOCK * 0b00..Reserved * 0b01..CM33_LOCK_REG_LOCK is 1 * 0b10..CM33_LOCK_REG_LOCK is 0 * 0b11..Reserved */ #define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) /*! @} */ /*! @name CPU1_LOCK_REG - Miscellaneous CPU1 Control Signals */ /*! @{ */ #define AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) #define AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) /*! LOCK_NS_VTOR - LOCK_NS_VTOR * 0b00..Reserved * 0b01..CM33 (CPU0) LOCKNSVTOR is 1 * 0b10..CM33 (CPU0) LOCKNSVTOR is 0 * 0b11..Reserved */ #define AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) #define AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) #define AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) /*! LOCK_NS_MPU - LOCK_NS_MPU * 0b00..Reserved * 0b01..CM33 (CPU0) LOCK_NS_MPU is 1 * 0b10..CM33 (CPU0) LOCK_NS_MPU is 0 * 0b11..Reserved */ #define AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) /*! @} */ /*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */ /*! @{ */ #define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) #define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) /*! WRITE_LOCK - Write Lock * 0b00..Reserved * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) #define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) #define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) /*! ENABLE_SECURE_CHECKING - Enable Secure Checking * 0b00..Reserved * 0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not * meet the security rule of the slave or memory to be accessed. * 0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security * rule of the slave or memory, it will not be detected as a violation. * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) #define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) #define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) /*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking * 0b00..Reserved * 0b01..Enables the privilege checking of secure mode access. * 0b10..Disables the privilege checking of secure mode access. * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) #define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) #define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) /*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking * 0b00..Reserved * 0b01..Enables the privilege checking of non-secure mode access. * 0b10..Disables the privilege checking of non-secure mode access. * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) #define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) #define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) /*! DISABLE_VIOLATION_ABORT - Disable Violation Abort * 0b00..Reserved * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq * (interrupt request) will still be asserted and serviced by ISR. * 0b10..The violation detected by the secure checker will cause an abort. * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U) #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U) /*! DISABLE_STRICT_MODE - Disable Strict Mode * 0b00..Reserved * 0b01..Master can access memories and peripherals at the same level or below that level. * 0b10..Master can access memories and peripherals at same level only * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK) #define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) #define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) /*! IDAU_ALL_NS - IDAU All Non-Secure * 0b00..Reserved * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. * 0b10..IDAU is enabled (restrictive mode) * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) /*! @} */ /*! @name MISC_CTRL_REG - Secure Control */ /*! @{ */ #define AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) #define AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) /*! WRITE_LOCK - Write Lock * 0b00..Reserved * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed * 0b11..Reserved */ #define AHBSC_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK) #define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) #define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) /*! ENABLE_SECURE_CHECKING - Enable Secure Checking * 0b00..Reserved * 0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not * meet the security rule of the slave or memory to be accessed. * 0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security * rule of the slave or memory, it will not be detected as a violation. * 0b11..Reserved */ #define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) #define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) #define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) /*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking * 0b00..Reserved * 0b01..Enables privilege checking of secure mode access. * 0b10..Disables privilege checking of secure mode access. * 0b11..Reserved */ #define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) #define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) #define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) /*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking * 0b00..Reserved * 0b01..Enables privilege checking of non-secure mode access. * 0b10..Disables privilege checking of non-secure mode access is disabled. * 0b11..Reserved */ #define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) #define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) #define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) /*! DISABLE_VIOLATION_ABORT - Disable Violation Abort * 0b00..Reserved * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq * (interrupt request) will still be asserted and serviced by ISR. * 0b10..The violation detected by the secure checker will cause an abort. * 0b11..Reserved */ #define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) #define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U) #define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U) /*! DISABLE_STRICT_MODE - Disable Strict Mode * 0b00..Reserved * 0b01..Master strict mode is on and can access memories and peripherals at the same level or below that level * 0b10..Master strict mode is disabled and can access memories and peripherals at same level only * 0b11..Reserved */ #define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK) #define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) #define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) /*! IDAU_ALL_NS - IDAU All Non-Secure * 0b00..Reserved * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. * 0b10..IDAU is enabled (restrictive mode) * 0b11..Reserved */ #define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK) /*! @} */ /*! * @} */ /* end of group AHBSC_Register_Masks */ /* AHBSC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral AHBSC base address */ #define AHBSC_BASE (0x50120000u) /** Peripheral AHBSC base address */ #define AHBSC_BASE_NS (0x40120000u) /** Peripheral AHBSC base pointer */ #define AHBSC ((AHBSC_Type *)AHBSC_BASE) /** Peripheral AHBSC base pointer */ #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) /** Peripheral AHBSC_ALIAS1 base address */ #define AHBSC_ALIAS1_BASE (0x50121000u) /** Peripheral AHBSC_ALIAS1 base address */ #define AHBSC_ALIAS1_BASE_NS (0x40121000u) /** Peripheral AHBSC_ALIAS1 base pointer */ #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) /** Peripheral AHBSC_ALIAS1 base pointer */ #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) /** Peripheral AHBSC_ALIAS2 base address */ #define AHBSC_ALIAS2_BASE (0x50122000u) /** Peripheral AHBSC_ALIAS2 base address */ #define AHBSC_ALIAS2_BASE_NS (0x40122000u) /** Peripheral AHBSC_ALIAS2 base pointer */ #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) /** Peripheral AHBSC_ALIAS2 base pointer */ #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) /** Peripheral AHBSC_ALIAS3 base address */ #define AHBSC_ALIAS3_BASE (0x50123000u) /** Peripheral AHBSC_ALIAS3 base address */ #define AHBSC_ALIAS3_BASE_NS (0x40123000u) /** Peripheral AHBSC_ALIAS3 base pointer */ #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) /** Peripheral AHBSC_ALIAS3 base pointer */ #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) /** Array initializer of AHBSC peripheral base addresses */ #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } /** Array initializer of AHBSC peripheral base pointers */ #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } /** Array initializer of AHBSC peripheral base addresses */ #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } /** Array initializer of AHBSC peripheral base pointers */ #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } #else /** Peripheral AHBSC base address */ #define AHBSC_BASE (0x40120000u) /** Peripheral AHBSC base pointer */ #define AHBSC ((AHBSC_Type *)AHBSC_BASE) /** Peripheral AHBSC_ALIAS1 base address */ #define AHBSC_ALIAS1_BASE (0x40121000u) /** Peripheral AHBSC_ALIAS1 base pointer */ #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) /** Peripheral AHBSC_ALIAS2 base address */ #define AHBSC_ALIAS2_BASE (0x40122000u) /** Peripheral AHBSC_ALIAS2 base pointer */ #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) /** Peripheral AHBSC_ALIAS3 base address */ #define AHBSC_ALIAS3_BASE (0x40123000u) /** Peripheral AHBSC_ALIAS3 base pointer */ #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) /** Array initializer of AHBSC peripheral base addresses */ #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } /** Array initializer of AHBSC peripheral base pointers */ #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } #endif /*! * @} */ /* end of group AHBSC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BSP32 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BSP32_Peripheral_Access_Layer BSP32 Peripheral Access Layer * @{ */ /** BSP32 - Register Layout Typedef */ typedef struct { __IO uint32_t OFFSET_PMEM; /**< Offset address register for program memory, offset: 0x0 */ __IO uint32_t OFFSET_XMEM; /**< Offset address register for X-data memory, offset: 0x4 */ __IO uint32_t OFFSET_YMEM; /**< Offset address register for Y-data memory, offset: 0x8 */ __IO uint32_t OFFSET_MAILBOX; /**< Offset address register for mailbox peripheral, offset: 0xC */ __O uint32_t INTERRUPTS_EXTERNAL; /**< External interrupt register, offset: 0x10 */ __IO uint32_t INTERRUPTS_STATUS; /**< Interrupt status register, offset: 0x14 */ __IO uint32_t CF_GATING_OVERRIDE; /**< CoolFlux BSP32 gating override, offset: 0x18 */ __IO uint32_t IVT_OFFSET; /**< CoolFlux BSP32 IVT offset register, offset: 0x1C */ __I uint32_t SLEEP_MODE; /**< CoolFlux BSP32 sleep mode register, offset: 0x20 */ __IO uint32_t IVT0; /**< CoolFlux BSP32 IVT register 0 content, offset: 0x24 */ __IO uint32_t IVT1; /**< CoolFlux BSP32 IVT register 1 content, offset: 0x28 */ __IO uint32_t IVT2; /**< CoolFlux BSP32 IVT register 2 content, offset: 0x2C */ __IO uint32_t IVT3; /**< CoolFlux BSP32 IVT register 3 content, offset: 0x30 */ __IO uint32_t IVT_DISABLE; /**< CoolFlux BSP32 IVT disable register, offset: 0x34 */ } BSP32_Type; /* ---------------------------------------------------------------------------- -- BSP32 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BSP32_Register_Masks BSP32 Register Masks * @{ */ /*! @name OFFSET_PMEM - Offset address register for program memory */ /*! @{ */ #define BSP32_OFFSET_PMEM_VAL_MASK (0x3FU) #define BSP32_OFFSET_PMEM_VAL_SHIFT (0U) /*! val - Offset address register for program memory */ #define BSP32_OFFSET_PMEM_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_OFFSET_PMEM_VAL_SHIFT)) & BSP32_OFFSET_PMEM_VAL_MASK) /*! @} */ /*! @name OFFSET_XMEM - Offset address register for X-data memory */ /*! @{ */ #define BSP32_OFFSET_XMEM_VAL_MASK (0xFFU) #define BSP32_OFFSET_XMEM_VAL_SHIFT (0U) /*! val - Offset address register for X-data memory */ #define BSP32_OFFSET_XMEM_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_OFFSET_XMEM_VAL_SHIFT)) & BSP32_OFFSET_XMEM_VAL_MASK) /*! @} */ /*! @name OFFSET_YMEM - Offset address register for Y-data memory */ /*! @{ */ #define BSP32_OFFSET_YMEM_VAL_MASK (0xFFU) #define BSP32_OFFSET_YMEM_VAL_SHIFT (0U) /*! val - Offset address register for Y-data memory */ #define BSP32_OFFSET_YMEM_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_OFFSET_YMEM_VAL_SHIFT)) & BSP32_OFFSET_YMEM_VAL_MASK) /*! @} */ /*! @name OFFSET_MAILBOX - Offset address register for mailbox peripheral */ /*! @{ */ #define BSP32_OFFSET_MAILBOX_VAL_MASK (0xFFFFFFU) #define BSP32_OFFSET_MAILBOX_VAL_SHIFT (0U) /*! val - Offset address register for mailbox peripheral */ #define BSP32_OFFSET_MAILBOX_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_OFFSET_MAILBOX_VAL_SHIFT)) & BSP32_OFFSET_MAILBOX_VAL_MASK) /*! @} */ /*! @name INTERRUPTS_EXTERNAL - External interrupt register */ /*! @{ */ #define BSP32_INTERRUPTS_EXTERNAL_VAL_MASK (0xFFFFFFFFU) #define BSP32_INTERRUPTS_EXTERNAL_VAL_SHIFT (0U) /*! val - External interrupt register */ #define BSP32_INTERRUPTS_EXTERNAL_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_INTERRUPTS_EXTERNAL_VAL_SHIFT)) & BSP32_INTERRUPTS_EXTERNAL_VAL_MASK) /*! @} */ /*! @name INTERRUPTS_STATUS - Interrupt status register */ /*! @{ */ #define BSP32_INTERRUPTS_STATUS_VAL_MASK (0x1U) #define BSP32_INTERRUPTS_STATUS_VAL_SHIFT (0U) /*! val - Interrupt status register */ #define BSP32_INTERRUPTS_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_INTERRUPTS_STATUS_VAL_SHIFT)) & BSP32_INTERRUPTS_STATUS_VAL_MASK) /*! @} */ /*! @name CF_GATING_OVERRIDE - CoolFlux BSP32 gating override */ /*! @{ */ #define BSP32_CF_GATING_OVERRIDE_VAL_MASK (0x1U) #define BSP32_CF_GATING_OVERRIDE_VAL_SHIFT (0U) /*! val - CoolFlux BSP32 gating override */ #define BSP32_CF_GATING_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_CF_GATING_OVERRIDE_VAL_SHIFT)) & BSP32_CF_GATING_OVERRIDE_VAL_MASK) /*! @} */ /*! @name IVT_OFFSET - CoolFlux BSP32 IVT offset register */ /*! @{ */ #define BSP32_IVT_OFFSET_VAL_MASK (0xFFFFFFU) #define BSP32_IVT_OFFSET_VAL_SHIFT (0U) /*! val - CoolFlux BSP32 IVT offset register */ #define BSP32_IVT_OFFSET_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_IVT_OFFSET_VAL_SHIFT)) & BSP32_IVT_OFFSET_VAL_MASK) /*! @} */ /*! @name SLEEP_MODE - CoolFlux BSP32 sleep mode register */ /*! @{ */ #define BSP32_SLEEP_MODE_VAL_MASK (0x1U) #define BSP32_SLEEP_MODE_VAL_SHIFT (0U) /*! val - CoolFlux BSP32 sleep mode register */ #define BSP32_SLEEP_MODE_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_SLEEP_MODE_VAL_SHIFT)) & BSP32_SLEEP_MODE_VAL_MASK) /*! @} */ /*! @name IVT0 - CoolFlux BSP32 IVT register 0 content */ /*! @{ */ #define BSP32_IVT0_VAL_MASK (0xFFFFFFU) #define BSP32_IVT0_VAL_SHIFT (0U) /*! val - CoolFlux BSP32 IVT register 0 content */ #define BSP32_IVT0_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_IVT0_VAL_SHIFT)) & BSP32_IVT0_VAL_MASK) /*! @} */ /*! @name IVT1 - CoolFlux BSP32 IVT register 1 content */ /*! @{ */ #define BSP32_IVT1_VAL_MASK (0xFFFFFFU) #define BSP32_IVT1_VAL_SHIFT (0U) /*! val - CoolFlux BSP32 IVT register 1 content */ #define BSP32_IVT1_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_IVT1_VAL_SHIFT)) & BSP32_IVT1_VAL_MASK) /*! @} */ /*! @name IVT2 - CoolFlux BSP32 IVT register 2 content */ /*! @{ */ #define BSP32_IVT2_VAL_MASK (0xFFFFFFU) #define BSP32_IVT2_VAL_SHIFT (0U) /*! val - CoolFlux BSP32 IVT register 2 content */ #define BSP32_IVT2_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_IVT2_VAL_SHIFT)) & BSP32_IVT2_VAL_MASK) /*! @} */ /*! @name IVT3 - CoolFlux BSP32 IVT register 3 content */ /*! @{ */ #define BSP32_IVT3_VAL_MASK (0xFFFFFFU) #define BSP32_IVT3_VAL_SHIFT (0U) /*! val - CoolFlux BSP32 IVT register 3 content */ #define BSP32_IVT3_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_IVT3_VAL_SHIFT)) & BSP32_IVT3_VAL_MASK) /*! @} */ /*! @name IVT_DISABLE - CoolFlux BSP32 IVT disable register */ /*! @{ */ #define BSP32_IVT_DISABLE_VAL_MASK (0x1U) #define BSP32_IVT_DISABLE_VAL_SHIFT (0U) /*! val - CoolFlux BSP32 IVT disable register */ #define BSP32_IVT_DISABLE_VAL(x) (((uint32_t)(((uint32_t)(x)) << BSP32_IVT_DISABLE_VAL_SHIFT)) & BSP32_IVT_DISABLE_VAL_MASK) /*! @} */ /*! * @} */ /* end of group BSP32_Register_Masks */ /* BSP32 - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral BSP32_0 base address */ #define BSP32_0_BASE (0x50032000u) /** Peripheral BSP32_0 base address */ #define BSP32_0_BASE_NS (0x40032000u) /** Peripheral BSP32_0 base pointer */ #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) /** Peripheral BSP32_0 base pointer */ #define BSP32_0_NS ((BSP32_Type *)BSP32_0_BASE_NS) /** Array initializer of BSP32 peripheral base addresses */ #define BSP32_BASE_ADDRS { BSP32_0_BASE } /** Array initializer of BSP32 peripheral base pointers */ #define BSP32_BASE_PTRS { BSP32_0 } /** Array initializer of BSP32 peripheral base addresses */ #define BSP32_BASE_ADDRS_NS { BSP32_0_BASE_NS } /** Array initializer of BSP32 peripheral base pointers */ #define BSP32_BASE_PTRS_NS { BSP32_0_NS } #else /** Peripheral BSP32_0 base address */ #define BSP32_0_BASE (0x40032000u) /** Peripheral BSP32_0 base pointer */ #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) /** Array initializer of BSP32 peripheral base addresses */ #define BSP32_BASE_ADDRS { BSP32_0_BASE } /** Array initializer of BSP32 peripheral base pointers */ #define BSP32_BASE_PTRS { BSP32_0 } #endif /*! * @} */ /* end of group BSP32_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CACHE64_CTRL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer * @{ */ /** CACHE64_CTRL - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[2048]; __IO uint32_t CCR; /**< Cache Control, offset: 0x800 */ __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ __IO uint32_t CSAR; /**< Cache Search Address, offset: 0x808 */ __IO uint32_t CCVR; /**< Cache Read/Write Value, offset: 0x80C */ } CACHE64_CTRL_Type; /* ---------------------------------------------------------------------------- -- CACHE64_CTRL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks * @{ */ /*! @name CCR - Cache Control */ /*! @{ */ #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) #define CACHE64_CTRL_CCR_ENCACHE_SHIFT (0U) /*! ENCACHE - Cache Enable * 0b0..Disables * 0b1..Enables */ #define CACHE64_CTRL_CCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK) #define CACHE64_CTRL_CCR_ENWRBUF_MASK (0x2U) #define CACHE64_CTRL_CCR_ENWRBUF_SHIFT (1U) /*! ENWRBUF - Enable Write Buffer * 0b0..Disables * 0b1..Enables */ #define CACHE64_CTRL_CCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK) #define CACHE64_CTRL_CCR_FRCWT_MASK (0x4U) #define CACHE64_CTRL_CCR_FRCWT_SHIFT (2U) /*! FRCWT - Force Write Through Mode * 0b0..Does not force * 0b1..Force */ #define CACHE64_CTRL_CCR_FRCWT(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCWT_SHIFT)) & CACHE64_CTRL_CCR_FRCWT_MASK) #define CACHE64_CTRL_CCR_FRCNOALLC_MASK (0x8U) #define CACHE64_CTRL_CCR_FRCNOALLC_SHIFT (3U) /*! FRCNOALLC - Forces No Allocation On Cache Misses * 0b0..Allocation on cache misses * 0b1..Forces no allocation on cache misses (FRCWT must be asserted) */ #define CACHE64_CTRL_CCR_FRCNOALLC(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCNOALLC_SHIFT)) & CACHE64_CTRL_CCR_FRCNOALLC_MASK) #define CACHE64_CTRL_CCR_INVW0_MASK (0x1000000U) #define CACHE64_CTRL_CCR_INVW0_SHIFT (24U) /*! INVW0 - Invalidate Way 0 * 0b0..No operation * 0b1..Invalidates all lines in way 0 */ #define CACHE64_CTRL_CCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK) #define CACHE64_CTRL_CCR_PUSHW0_MASK (0x2000000U) #define CACHE64_CTRL_CCR_PUSHW0_SHIFT (25U) /*! PUSHW0 - Push Way 0 * 0b0..No operation * 0b1..Push all modified lines in way 0 */ #define CACHE64_CTRL_CCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK) #define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U) #define CACHE64_CTRL_CCR_INVW1_SHIFT (26U) /*! INVW1 - Invalidate Way 1 * 0b0..No operation * 0b1..Invalidates all lines in way 1 */ #define CACHE64_CTRL_CCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK) #define CACHE64_CTRL_CCR_PUSHW1_MASK (0x8000000U) #define CACHE64_CTRL_CCR_PUSHW1_SHIFT (27U) /*! PUSHW1 - Push Way 1 * 0b0..No operation * 0b1..Push all modified lines in way 1 */ #define CACHE64_CTRL_CCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK) #define CACHE64_CTRL_CCR_GO_MASK (0x80000000U) #define CACHE64_CTRL_CCR_GO_SHIFT (31U) /*! GO - Initiate Cache Command * 0b0..Write: no effect; Read: no cache command active * 0b1..Write: initiates cache command; Read: cache command active */ #define CACHE64_CTRL_CCR_GO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK) /*! @} */ /*! @name CLCR - Cache Line Control */ /*! @{ */ #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) #define CACHE64_CTRL_CLCR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect; Read: no line command active * 0b1..Write: initiate line command; Read: line command active */ #define CACHE64_CTRL_CLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK) #define CACHE64_CTRL_CLCR_CACHEADDR_MASK (0x1FFCU) #define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT (2U) /*! CACHEADDR - Cache Address */ #define CACHE64_CTRL_CLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK) #define CACHE64_CTRL_CLCR_WSEL_MASK (0x4000U) #define CACHE64_CTRL_CLCR_WSEL_SHIFT (14U) /*! WSEL - Way Select * 0b0..Way 0 * 0b1..Way 1 */ #define CACHE64_CTRL_CLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK) #define CACHE64_CTRL_CLCR_TDSEL_MASK (0x10000U) #define CACHE64_CTRL_CLCR_TDSEL_SHIFT (16U) /*! TDSEL - Tag Or Data Select * 0b0..Data * 0b1..Tag */ #define CACHE64_CTRL_CLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK) #define CACHE64_CTRL_CLCR_LCIVB_MASK (0x100000U) #define CACHE64_CTRL_CLCR_LCIVB_SHIFT (20U) /*! LCIVB - Line Command Initial Valid Bit * 0b0..Initial state 0 * 0b1..Initial state 1 */ #define CACHE64_CTRL_CLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK) #define CACHE64_CTRL_CLCR_LCIMB_MASK (0x200000U) #define CACHE64_CTRL_CLCR_LCIMB_SHIFT (21U) /*! LCIMB - Line Command Initial Modified Bit * 0b0..Initial state 0 * 0b1..Initial state 1 */ #define CACHE64_CTRL_CLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK) #define CACHE64_CTRL_CLCR_LCWAY_MASK (0x400000U) #define CACHE64_CTRL_CLCR_LCWAY_SHIFT (22U) /*! LCWAY - Line Command Way * 0b0..Way 0 * 0b1..Way 1 */ #define CACHE64_CTRL_CLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK) #define CACHE64_CTRL_CLCR_LCMD_MASK (0x3000000U) #define CACHE64_CTRL_CLCR_LCMD_SHIFT (24U) /*! LCMD - Line Command * 0b00..Search and read or write * 0b01..Invalidate * 0b10..Push * 0b11..Clear */ #define CACHE64_CTRL_CLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK) #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) #define CACHE64_CTRL_CLCR_LADSEL_SHIFT (26U) /*! LADSEL - Line Address Select * 0b0..Cache * 0b1..Physical */ #define CACHE64_CTRL_CLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK) #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) #define CACHE64_CTRL_CLCR_LACC_SHIFT (27U) /*! LACC - Line Access Type * 0b0..Read * 0b1..Write */ #define CACHE64_CTRL_CLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK) /*! @} */ /*! @name CSAR - Cache Search Address */ /*! @{ */ #define CACHE64_CTRL_CSAR_LGO_MASK (0x1U) #define CACHE64_CTRL_CSAR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect; Read: no line command active * 0b1..Write: initiate line command; Read: line command active */ #define CACHE64_CTRL_CSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK) #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) #define CACHE64_CTRL_CSAR_PHYADDR_SHIFT (1U) /*! PHYADDR - Physical Address */ #define CACHE64_CTRL_CSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR_MASK) /*! @} */ /*! @name CCVR - Cache Read/Write Value */ /*! @{ */ #define CACHE64_CTRL_CCVR_DATA_MASK (0xFFFFFFFFU) #define CACHE64_CTRL_CCVR_DATA_SHIFT (0U) /*! DATA - Cache Read/Write Data */ #define CACHE64_CTRL_CCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group CACHE64_CTRL_Register_Masks */ /* CACHE64_CTRL - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CACHE64_CTRL0 base address */ #define CACHE64_CTRL0_BASE (0x5001B000u) /** Peripheral CACHE64_CTRL0 base address */ #define CACHE64_CTRL0_BASE_NS (0x4001B000u) /** Peripheral CACHE64_CTRL0 base pointer */ #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) /** Peripheral CACHE64_CTRL0 base pointer */ #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) /** Array initializer of CACHE64_CTRL peripheral base addresses */ #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } /** Array initializer of CACHE64_CTRL peripheral base pointers */ #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } /** Array initializer of CACHE64_CTRL peripheral base addresses */ #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } /** Array initializer of CACHE64_CTRL peripheral base pointers */ #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } #else /** Peripheral CACHE64_CTRL0 base address */ #define CACHE64_CTRL0_BASE (0x4001B000u) /** Peripheral CACHE64_CTRL0 base pointer */ #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) /** Array initializer of CACHE64_CTRL peripheral base addresses */ #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } /** Array initializer of CACHE64_CTRL peripheral base pointers */ #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } #endif /** CACHE64_CTRL physical memory base alias count */ #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** CACHE64_CTRL physical memory base address */ #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } /** CACHE64_CTRL physical memory size */ #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } /** CACHE64_CTRL physical memory base address */ #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } /** CACHE64_CTRL physical memory size */ #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } #else /** CACHE64_CTRL physical memory base address */ #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } /** CACHE64_CTRL physical memory size */ #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } #endif /* Backward compatibility */ /*! * @} */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CACHE64_POLSEL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer * @{ */ /** CACHE64_POLSEL - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[20]; __IO uint32_t REG0_TOP; /**< Region 0 Top Boundary, offset: 0x14 */ __IO uint32_t REG1_TOP; /**< Region 1 Top Boundary, offset: 0x18 */ __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ } CACHE64_POLSEL_Type; /* ---------------------------------------------------------------------------- -- CACHE64_POLSEL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks * @{ */ /*! @name REG0_TOP - Region 0 Top Boundary */ /*! @{ */ #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK (0x1FFFFC00U) #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) /*! REG0_TOP - Upper Limit Of Region 0 */ #define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK) /*! @} */ /*! @name REG1_TOP - Region 1 Top Boundary */ /*! @{ */ #define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK (0x1FFFFC00U) #define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT (10U) /*! REG1_TOP - Upper Limit Of Region 1 */ #define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK) /*! @} */ /*! @name POLSEL - Policy Select */ /*! @{ */ #define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK (0x3U) #define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT (0U) /*! REG0_POLICY - Policy Select For Region 0 * 0b00..Noncacheable * 0b01..Write-through * 0b10..Write-back * 0b11..Invalid */ #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK) #define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK (0xCU) #define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT (2U) /*! REG1_POLICY - Policy Select For Region 1 * 0b00..Noncacheable * 0b01..Write-through * 0b10..Write-back * 0b11..Invalid */ #define CACHE64_POLSEL_POLSEL_REG1_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK) #define CACHE64_POLSEL_POLSEL_REG2_POLICY_MASK (0x30U) #define CACHE64_POLSEL_POLSEL_REG2_POLICY_SHIFT (4U) /*! REG2_POLICY - Policy Select For Region 2 * 0b00..Noncacheable * 0b01..Write-through * 0b10..Write-back * 0b11..Invalid */ #define CACHE64_POLSEL_POLSEL_REG2_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG2_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG2_POLICY_MASK) /*! @} */ /*! * @} */ /* end of group CACHE64_POLSEL_Register_Masks */ /* CACHE64_POLSEL - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CACHE64_POLSEL0 base address */ #define CACHE64_POLSEL0_BASE (0x5001B000u) /** Peripheral CACHE64_POLSEL0 base address */ #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) /** Peripheral CACHE64_POLSEL0 base pointer */ #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) /** Peripheral CACHE64_POLSEL0 base pointer */ #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) /** Array initializer of CACHE64_POLSEL peripheral base addresses */ #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } /** Array initializer of CACHE64_POLSEL peripheral base pointers */ #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } /** Array initializer of CACHE64_POLSEL peripheral base addresses */ #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } /** Array initializer of CACHE64_POLSEL peripheral base pointers */ #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } #else /** Peripheral CACHE64_POLSEL0 base address */ #define CACHE64_POLSEL0_BASE (0x4001B000u) /** Peripheral CACHE64_POLSEL0 base pointer */ #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) /** Array initializer of CACHE64_POLSEL peripheral base addresses */ #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } /** Array initializer of CACHE64_POLSEL peripheral base pointers */ #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } #endif /*! * @} */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAN Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer * @{ */ /** CAN - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ uint8_t RESERVED_1[4]; __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ uint8_t RESERVED_2[4]; __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ uint8_t RESERVED_3[8]; __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ uint8_t RESERVED_4[44]; union { /* offset: 0x80 */ struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ } MB_8B[32]; struct { /* offset: 0x80, array step: 0x18 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */ __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ } MB_16B[21]; struct { /* offset: 0x80, array step: 0x28 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */ __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ } MB_32B[12]; struct { /* offset: 0x80, array step: 0x48 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */ __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ } MB_64B[7]; struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[32]; }; uint8_t RESERVED_5[1536]; __IO uint32_t RXIMR[32]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_6[512]; __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ uint8_t RESERVED_7[24]; struct { /* offset: 0xB40, array step: 0x10 */ __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ } WMB[4]; uint8_t RESERVED_8[112]; __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ uint8_t RESERVED_9[9192]; __IO uint32_t ERFFEL[32]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ } CAN_Type; /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /*! @name MCR - Module Configuration */ /*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) /*! MAXMB - Number of the Last Message Buffer */ #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) /*! IDAM - ID Acceptance Mode * 0b00..Format A: One full ID (standard and extended) per ID filter table element. * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. * 0b11..Format D: All frames rejected. */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) #define CAN_MCR_FDEN_MASK (0x800U) #define CAN_MCR_FDEN_SHIFT (11U) /*! FDEN - CAN FD Operation Enable * 0b1..Enable * 0b0..Disable */ #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) /*! AEN - Abort Enable * 0b0..Disabled * 0b1..Enabled */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) /*! LPRIOEN - Local Priority Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_PNET_EN_MASK (0x4000U) #define CAN_MCR_PNET_EN_SHIFT (14U) /*! PNET_EN - Pretended Networking Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) #define CAN_MCR_DMA_MASK (0x8000U) #define CAN_MCR_DMA_SHIFT (15U) /*! DMA - DMA Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) /*! IRMQ - Individual RX Masking and Queue Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) /*! SRXDIS - Self-Reception Disable * 0b0..Enable * 0b1..Disable */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) /*! WAKSRC - Wake-Up Source * 0b0..No filter applied * 0b1..Filter applied */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge * 0b0..Not in a low-power mode * 0b1..In a low-power mode */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) /*! WRNEN - Warning Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) /*! SLFWAK - Self Wake-up * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) /*! FRZACK - Freeze Mode Acknowledge * 0b0..Not in Freeze mode, prescaler running. * 0b1..In Freeze mode, prescaler stopped. */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) /*! SOFTRST - Soft Reset * 0b0..No reset * 0b1..Soft reset affects reset registers */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) /*! WAKMSK - Wake-up Interrupt Mask * 0b0..Disabled * 0b1..Enabled */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. * 0b1..FlexCAN is in Disable mode, Stop mode, or Freeze mode. */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) /*! HALT - Halt FlexCAN * 0b0..No request * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) /*! RFEN - Legacy RX FIFO Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) /*! FRZ - Freeze Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) /*! MDIS - Module Disable * 0b0..Enable * 0b1..Disable */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) /*! @} */ /*! @name CTRL1 - Control 1 */ /*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) /*! PROPSEG - Propagation Segment */ #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) /*! LOM - Listen-Only Mode * 0b0..Listen-Only mode is deactivated. * 0b1..FlexCAN module operates in Listen-Only mode. */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) /*! LBUF - Lowest Buffer Transmitted First * 0b0..Buffer with highest priority is transmitted first. * 0b1..Lowest number buffer is transmitted first. */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery * 0b0..Enabled * 0b1..Disabled */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) /*! SMP - CAN Bit Sampling * 0b0..One sample is used to determine the bit value. * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two * preceding samples. A majority rule is used. */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) /*! RWRNMSK - RX Warning Interrupt Mask * 0b0..Disabled * 0b1..Enabled */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) /*! TWRNMSK - TX Warning Interrupt Mask * 0b0..Disabled * 0b1..Enabled */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) /*! LPB - Loopback Mode * 0b0..Disabled * 0b1..Enabled */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) /*! ERRMSK - Error Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) /*! BOFFMSK - Bus Off Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) /*! PSEG2 - Phase Segment 2 */ #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) #define CAN_CTRL1_PSEG1_MASK (0x380000U) #define CAN_CTRL1_PSEG1_SHIFT (19U) /*! PSEG1 - Phase Segment 1 */ #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) #define CAN_CTRL1_RJW_MASK (0xC00000U) #define CAN_CTRL1_RJW_SHIFT (22U) /*! RJW - Resync Jump Width */ #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) /*! PRESDIV - Prescaler Division Factor */ #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) /*! @} */ /*! @name TIMER - Free-Running Timer */ /*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) /*! TIMER - Timer Value */ #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) /*! @} */ /*! @name RXMGMASK - RX Message Buffers Global Mask */ /*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) /*! MG - Global Mask for RX Message Buffers */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @} */ /*! @name RX14MASK - Receive 14 Mask */ /*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) /*! RX14M - RX Buffer 14 Mask Bits */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @} */ /*! @name RX15MASK - Receive 15 Mask */ /*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) /*! RX15M - RX Buffer 15 Mask Bits */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @} */ /*! @name ECR - Error Counter */ /*! @{ */ #define CAN_ECR_TXERRCNT_MASK (0xFFU) #define CAN_ECR_TXERRCNT_SHIFT (0U) /*! TXERRCNT - Transmit Error Counter */ #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) #define CAN_ECR_RXERRCNT_MASK (0xFF00U) #define CAN_ECR_RXERRCNT_SHIFT (8U) /*! RXERRCNT - Receive Error Counter */ #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) /*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) /*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) /*! @} */ /*! @name ESR1 - Error and Status 1 */ /*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) /*! WAKINT - Wake-up Interrupt Flag * 0b0..No such occurrence. * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) /*! ERRINT - Error Interrupt Flag * 0b0..No such occurrence. * 0b1..Indicates setting of any error flag in the Error and Status register. */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) /*! BOFFINT - Bus Off Interrupt Flag * 0b0..No such occurrence. * 0b1..FlexCAN module entered Bus Off state. */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) /*! RX - FlexCAN in Reception Flag * 0b0..Not receiving * 0b1..Receiving */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) /*! FLTCONF - Fault Confinement State * 0b00..Error Active * 0b01..Error Passive * 0b1x..Bus Off */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) /*! TX - FlexCAN In Transmission * 0b0..Not transmitting * 0b1..Transmitting */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) /*! IDLE - Idle * 0b0..Not IDLE * 0b1..IDLE */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) /*! RXWRN - RX Error Warning Flag * 0b0..No such occurrence. * 0b1..RXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) /*! TXWRN - TX Error Warning Flag * 0b0..No such occurrence. * 0b1..TXERRCNT is 96 or greater. */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) /*! STFERR - Stuffing Error Flag * 0b0..No error * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) /*! FRMERR - Form Error Flag * 0b0..No error * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) /*! CRCERR - Cyclic Redundancy Check Error Flag * 0b0..No error * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) /*! ACKERR - Acknowledge Error Flag * 0b0..No error * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) /*! BIT0ERR - Bit0 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) /*! BIT1ERR - Bit1 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) /*! RWRNINT - RX Warning Interrupt Flag * 0b0..No such occurrence * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) /*! TWRNINT - TX Warning Interrupt Flag * 0b0..No such occurrence * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) /*! SYNCH - CAN Synchronization Status Flag * 0b0..Not synchronized * 0b1..Synchronized */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) /*! BOFFDONEINT - Bus Off Done Interrupt Flag * 0b0..No such occurrence * 0b1..FlexCAN module has completed Bus Off process. */ #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) /*! ERRINT_FAST - Fast Error Interrupt Flag * 0b0..No such occurrence. * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. */ #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) #define CAN_ESR1_ERROVR_MASK (0x200000U) #define CAN_ESR1_ERROVR_SHIFT (21U) /*! ERROVR - Error Overrun Flag * 0b0..No overrun * 0b1..Overrun */ #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) /*! STFERR_FAST - Fast Stuffing Error Flag * 0b0..No such occurrence. * 0b1..A stuffing error occurred since last read of this register. */ #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) /*! FRMERR_FAST - Fast Form Error Flag * 0b0..No such occurrence. * 0b1..A form error occurred since last read of this register. */ #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) /*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) /*! BIT0ERR_FAST - Fast Bit0 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit transmitted as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) /*! BIT1ERR_FAST - Fast Bit1 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit transmitted as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) /*! @} */ /*! @name IMASK1 - Interrupt Masks 1 */ /*! @{ */ #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUF31TO0M_SHIFT (0U) /*! BUF31TO0M - Buffer MBi Mask */ #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) /*! @} */ /*! @name IFLAG1 - Interrupt Flags 1 */ /*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) /*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit * 0b0..MB0 has no occurrence of successfully completed transmission or reception. * 0b1..MB0 has successfully completed transmission or reception. */ #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) /*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) /*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO * 0b0..No occurrence of completed transmission or reception, or no frames available * 0b1..MB5 completed transmission or reception, or frames available */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) /*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. * 0b1..MB6 completed transmission or reception, or FIFO almost full. */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) /*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. * 0b1..MB7 completed transmission or reception, or FIFO overflow. */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) /*! BUF31TO8I - Buffer MBi Interrupt */ #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @} */ /*! @name CTRL2 - Control 2 */ /*! @{ */ #define CAN_CTRL2_EDFLTDIS_MASK (0x800U) #define CAN_CTRL2_EDFLTDIS_SHIFT (11U) /*! EDFLTDIS - Edge Filter Disable * 0b0..Enabled * 0b1..Disabled */ #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) /*! ISOCANFDEN - ISO CAN FD Enable * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) #define CAN_CTRL2_BTE_MASK (0x2000U) #define CAN_CTRL2_BTE_SHIFT (13U) /*! BTE - Bit Timing Expansion Enable * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) #define CAN_CTRL2_PREXCEN_MASK (0x4000U) #define CAN_CTRL2_PREXCEN_SHIFT (14U) /*! PREXCEN - Protocol Exception Enable * 0b0..Disabled * 0b1..Enabled */ #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) /*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) /*! RRS - Remote Request Storing * 0b0..Generated * 0b1..Stored */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) /*! MRP - Message Buffers Reception Priority * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) /*! TASD - Transmission Arbitration Start Delay */ #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) #define CAN_CTRL2_RFFN_MASK (0xF000000U) #define CAN_CTRL2_RFFN_SHIFT (24U) /*! RFFN - Number of Legacy Receive FIFO Filters */ #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) /*! BOFFDONEMSK - Bus Off Done Interrupt Mask * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) /*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) /*! @} */ /*! @name ESR2 - Error and Status 2 */ /*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) /*! IMB - Inactive Message Buffer * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. * 0b1..At least one message buffer is inactive. */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) /*! VPS - Valid Priority Status * 0b0..Invalid * 0b1..Valid */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) /*! LPTM - Lowest Priority TX Message Buffer */ #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) /*! @} */ /*! @name CRCR - Cyclic Redundancy Check */ /*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) /*! TXCRC - Transmitted CRC value */ #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) /*! MBCRC - CRC Message Buffer */ #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) /*! @} */ /*! @name RXFGMASK - Legacy RX FIFO Global Mask */ /*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) /*! FGM - Legacy RX FIFO Global Mask Bits */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @} */ /*! @name RXFIR - Legacy RX FIFO Information */ /*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) /*! IDHIT - Identifier Acceptance Filter Hit Indicator */ #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) /*! @} */ /*! @name CBT - CAN Bit Timing */ /*! @{ */ #define CAN_CBT_EPSEG2_MASK (0x1FU) #define CAN_CBT_EPSEG2_SHIFT (0U) /*! EPSEG2 - Extended Phase Segment 2 */ #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) #define CAN_CBT_EPSEG1_MASK (0x3E0U) #define CAN_CBT_EPSEG1_SHIFT (5U) /*! EPSEG1 - Extended Phase Segment 1 */ #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) #define CAN_CBT_EPROPSEG_MASK (0xFC00U) #define CAN_CBT_EPROPSEG_SHIFT (10U) /*! EPROPSEG - Extended Propagation Segment */ #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) #define CAN_CBT_ERJW_MASK (0x1F0000U) #define CAN_CBT_ERJW_SHIFT (16U) /*! ERJW - Extended Resync Jump Width */ #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) #define CAN_CBT_EPRESDIV_SHIFT (21U) /*! EPRESDIV - Extended Prescaler Division Factor */ #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) #define CAN_CBT_BTF_MASK (0x80000000U) #define CAN_CBT_BTF_SHIFT (31U) /*! BTF - Bit Timing Format Enable * 0b0..Disable * 0b1..Enable */ #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) /*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT_MB8B (32U) /* The count of CAN_ID */ #define CAN_ID_COUNT_MB8B (32U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB8B (32U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB8B2 (2U) /* The count of CAN_CS */ #define CAN_CS_COUNT_MB16B (21U) /* The count of CAN_ID */ #define CAN_ID_COUNT_MB16B (21U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB16B (21U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB16B2 (4U) /* The count of CAN_CS */ #define CAN_CS_COUNT_MB32B (12U) /* The count of CAN_ID */ #define CAN_ID_COUNT_MB32B (12U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB32B (12U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB32B2 (8U) /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ /*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field * appears on the CAN bus. */ #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) #define CAN_CS_DLC_MASK (0xF0000U) #define CAN_CS_DLC_SHIFT (16U) /*! DLC - Length of the data to be stored/transmitted. */ #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) #define CAN_CS_RTR_MASK (0x100000U) #define CAN_CS_RTR_SHIFT (20U) /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) #define CAN_CS_IDE_MASK (0x200000U) #define CAN_CS_IDE_SHIFT (21U) /*! IDE - ID Extended. One/zero for extended/standard format frame. */ #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) #define CAN_CS_SRR_MASK (0x400000U) #define CAN_CS_SRR_SHIFT (22U) /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by * the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) #define CAN_CS_ESI_MASK (0x20000000U) #define CAN_CS_ESI_SHIFT (29U) /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) #define CAN_CS_BRS_MASK (0x40000000U) #define CAN_CS_BRS_SHIFT (30U) /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) #define CAN_CS_EDL_MASK (0x80000000U) #define CAN_CS_EDL_SHIFT (31U) /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ #define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) /*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT_MB64B (7U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ /*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) /*! EXT - Contains extended (LOW word) identifier of message buffer. */ #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) #define CAN_ID_STD_MASK (0x1FFC0000U) #define CAN_ID_STD_SHIFT (18U) /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular * ID to define the transmission priority. */ #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) /*! @} */ /* The count of CAN_ID */ #define CAN_ID_COUNT_MB64B (7U) /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ /*! @{ */ #define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_3_SHIFT (0U) /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) #define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_7_SHIFT (0U) /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) #define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_11_SHIFT (0U) /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) #define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_15_SHIFT (0U) /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) #define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_19_SHIFT (0U) /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) #define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_23_SHIFT (0U) /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) #define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_27_SHIFT (0U) /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) #define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_31_SHIFT (0U) /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) #define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_35_SHIFT (0U) /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) #define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_39_SHIFT (0U) /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) #define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_43_SHIFT (0U) /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) #define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_47_SHIFT (0U) /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) #define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_51_SHIFT (0U) /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) #define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_55_SHIFT (0U) /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) #define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_59_SHIFT (0U) /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) #define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_63_SHIFT (0U) /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) #define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_2_SHIFT (8U) /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) #define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_6_SHIFT (8U) /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) #define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_10_SHIFT (8U) /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) #define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_14_SHIFT (8U) /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) #define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_18_SHIFT (8U) /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) #define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_22_SHIFT (8U) /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) #define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_26_SHIFT (8U) /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) #define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_30_SHIFT (8U) /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) #define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_34_SHIFT (8U) /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) #define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_38_SHIFT (8U) /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) #define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_42_SHIFT (8U) /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) #define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_46_SHIFT (8U) /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) #define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_50_SHIFT (8U) /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) #define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_54_SHIFT (8U) /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) #define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_58_SHIFT (8U) /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) #define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_62_SHIFT (8U) /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) #define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_1_SHIFT (16U) /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) #define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_5_SHIFT (16U) /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) #define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_9_SHIFT (16U) /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) #define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_13_SHIFT (16U) /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) #define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_17_SHIFT (16U) /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) #define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_21_SHIFT (16U) /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) #define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_25_SHIFT (16U) /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) #define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_29_SHIFT (16U) /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) #define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_33_SHIFT (16U) /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) #define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_37_SHIFT (16U) /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) #define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_41_SHIFT (16U) /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) #define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_45_SHIFT (16U) /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) #define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_49_SHIFT (16U) /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) #define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_53_SHIFT (16U) /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) #define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_57_SHIFT (16U) /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) #define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_61_SHIFT (16U) /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) #define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_0_SHIFT (24U) /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) #define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_4_SHIFT (24U) /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) #define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_8_SHIFT (24U) /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) #define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_12_SHIFT (24U) /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) #define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_16_SHIFT (24U) /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) #define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_20_SHIFT (24U) /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) #define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_24_SHIFT (24U) /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) #define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_28_SHIFT (24U) /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) #define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_32_SHIFT (24U) /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) #define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_36_SHIFT (24U) /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) #define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_40_SHIFT (24U) /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) #define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_44_SHIFT (24U) /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) #define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_48_SHIFT (24U) /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) #define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_52_SHIFT (24U) /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) #define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_56_SHIFT (24U) /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) #define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_60_SHIFT (24U) /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) /*! @} */ /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB64B (7U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB64B2 (16U) /* The count of CAN_CS */ #define CAN_CS_COUNT (32U) /* The count of CAN_ID */ #define CAN_ID_COUNT (32U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ /*! @{ */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) /*! @} */ /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (32U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ /*! @{ */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) /*! @} */ /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (32U) /*! @name RXIMR - Receive Individual Mask */ /*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) /*! MI - Individual Mask Bits */ #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) /*! @} */ /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (32U) /*! @name CTRL1_PN - Pretended Networking Control 1 */ /*! @{ */ #define CAN_CTRL1_PN_FCS_MASK (0x3U) #define CAN_CTRL1_PN_FCS_SHIFT (0U) /*! FCS - Filtering Combination Selection * 0b00..Message ID filtering only * 0b01..Message ID filtering and payload filtering * 0b10..Message ID filtering occurring a specified number of times * 0b11..Message ID filtering and payload filtering a specified number of times */ #define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) #define CAN_CTRL1_PN_IDFS_MASK (0xCU) #define CAN_CTRL1_PN_IDFS_SHIFT (2U) /*! IDFS - ID Filtering Selection * 0b00..Match ID contents to an exact target value * 0b01..Match an ID value greater than or equal to a specified target value * 0b10..Match an ID value smaller than or equal to a specified target value * 0b11..Match an ID value within a range of values, inclusive */ #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) #define CAN_CTRL1_PN_PLFS_MASK (0x30U) #define CAN_CTRL1_PN_PLFS_SHIFT (4U) /*! PLFS - Payload Filtering Selection * 0b00..Match payload contents to an exact target value * 0b01..Match a payload value greater than or equal to a specified target value * 0b10..Match a payload value smaller than or equal to a specified target value * 0b11..Match upon a payload value within a range of values, inclusive */ #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) #define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) #define CAN_CTRL1_PN_NMATCH_SHIFT (8U) /*! NMATCH - Number of Messages Matching the Same Filtering Criteria * 0b00000001..Once * 0b00000010..Twice * 0b11111111..255 times */ #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) #define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) #define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) /*! WUMF_MSK - Wake-up by Matching Flag Mask * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) #define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) #define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) /*! WTOF_MSK - Wake-up by Timeout Flag Mask * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) /*! @} */ /*! @name CTRL2_PN - Pretended Networking Control 2 */ /*! @{ */ #define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) #define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) /*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */ #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) /*! @} */ /*! @name WU_MTC - Pretended Networking Wake-Up Match */ /*! @{ */ #define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) #define CAN_WU_MTC_MCOUNTER_SHIFT (8U) /*! MCOUNTER - Number of Matches in Pretended Networking */ #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) #define CAN_WU_MTC_WUMF_MASK (0x10000U) #define CAN_WU_MTC_WUMF_SHIFT (16U) /*! WUMF - Wake-up by Match Flag * 0b0..No event detected * 0b1..Event detected */ #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) #define CAN_WU_MTC_WTOF_MASK (0x20000U) #define CAN_WU_MTC_WTOF_SHIFT (17U) /*! WTOF - Wake-up by Timeout Flag Bit * 0b0..No event detected * 0b1..Event detected */ #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) /*! @} */ /*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ /*! @{ */ #define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) #define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) /*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */ #define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) #define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) #define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) /*! FLT_RTR - Remote Transmission Request Filter * 0b0..Reject remote frame (accept data frame) * 0b1..Accept remote frame */ #define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) #define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) #define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) /*! FLT_IDE - ID Extended Filter * 0b0..Standard * 0b1..Extended */ #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) /*! @} */ /*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ /*! @{ */ #define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) #define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) /*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */ #define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) #define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) #define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) /*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */ #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) /*! @} */ /*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ /*! @{ */ #define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) #define CAN_PL1_LO_Data_byte_3_SHIFT (0U) /*! Data_byte_3 - Data byte 3 */ #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) #define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) #define CAN_PL1_LO_Data_byte_2_SHIFT (8U) /*! Data_byte_2 - Data byte 2 */ #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) #define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) #define CAN_PL1_LO_Data_byte_1_SHIFT (16U) /*! Data_byte_1 - Data byte 1 */ #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) #define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) #define CAN_PL1_LO_Data_byte_0_SHIFT (24U) /*! Data_byte_0 - Data byte 0 */ #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) /*! @} */ /*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ /*! @{ */ #define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) #define CAN_PL1_HI_Data_byte_7_SHIFT (0U) /*! Data_byte_7 - Data byte 7 */ #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) #define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) #define CAN_PL1_HI_Data_byte_6_SHIFT (8U) /*! Data_byte_6 - Data byte 6 */ #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) #define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) #define CAN_PL1_HI_Data_byte_5_SHIFT (16U) /*! Data_byte_5 - Data byte 5 */ #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) #define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) #define CAN_PL1_HI_Data_byte_4_SHIFT (24U) /*! Data_byte_4 - Data byte 4 */ #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) /*! @} */ /*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ /*! @{ */ #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) /*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) /*! RTR_MSK - Remote Transmission Request Mask * 0b0..The corresponding bit in the filter is "don't care." * 0b1..The corresponding bit in the filter is checked. */ #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) /*! IDE_MSK - ID Extended Mask * 0b0..The corresponding bit in the filter is "don't care." * 0b1..The corresponding bit in the filter is checked. */ #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) /*! @} */ /*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ /*! @{ */ #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) /*! Data_byte_3 - Data Byte 3 */ #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) /*! Data_byte_2 - Data Byte 2 */ #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) /*! Data_byte_1 - Data Byte 1 */ #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) /*! Data_byte_0 - Data Byte 0 */ #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) /*! @} */ /*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ /*! @{ */ #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) /*! Data_byte_7 - Data Byte 7 */ #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) /*! Data_byte_6 - Data Byte 6 */ #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) /*! Data_byte_5 - Data Byte 5 */ #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) /*! Data_byte_4 - Data Byte 4 */ #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) /*! @} */ /*! @name WMB_CS - Wake-Up Message Buffer */ /*! @{ */ #define CAN_WMB_CS_DLC_MASK (0xF0000U) #define CAN_WMB_CS_DLC_SHIFT (16U) /*! DLC - Length of Data in Bytes */ #define CAN_WMB_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK) #define CAN_WMB_CS_RTR_MASK (0x100000U) #define CAN_WMB_CS_RTR_SHIFT (20U) /*! RTR - Remote Transmission Request * 0b0..Data * 0b1..Remote */ #define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) #define CAN_WMB_CS_IDE_MASK (0x200000U) #define CAN_WMB_CS_IDE_SHIFT (21U) /*! IDE - ID Extended Bit * 0b0..Standard * 0b1..Extended */ #define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) #define CAN_WMB_CS_SRR_MASK (0x400000U) #define CAN_WMB_CS_SRR_SHIFT (22U) /*! SRR - Substitute Remote Request * 0b0..Dominant * 0b1..Recessive */ #define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) /*! @} */ /* The count of CAN_WMB_CS */ #define CAN_WMB_CS_COUNT (4U) /*! @name WMB_ID - Wake-Up Message Buffer for ID */ /*! @{ */ #define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) #define CAN_WMB_ID_ID_SHIFT (0U) /*! ID - Received ID in Pretended Networking Mode */ #define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) /*! @} */ /* The count of CAN_WMB_ID */ #define CAN_WMB_ID_COUNT (4U) /*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ /*! @{ */ #define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) #define CAN_WMB_D03_Data_byte_3_SHIFT (0U) /*! Data_byte_3 - Data Byte 3 */ #define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) #define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) #define CAN_WMB_D03_Data_byte_2_SHIFT (8U) /*! Data_byte_2 - Data Byte 2 */ #define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) #define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) #define CAN_WMB_D03_Data_byte_1_SHIFT (16U) /*! Data_byte_1 - Data Byte 1 */ #define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) #define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) #define CAN_WMB_D03_Data_byte_0_SHIFT (24U) /*! Data_byte_0 - Data Byte 0 */ #define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) /*! @} */ /* The count of CAN_WMB_D03 */ #define CAN_WMB_D03_COUNT (4U) /*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ /*! @{ */ #define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) #define CAN_WMB_D47_Data_byte_7_SHIFT (0U) /*! Data_byte_7 - Data Byte 7 */ #define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) #define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) #define CAN_WMB_D47_Data_byte_6_SHIFT (8U) /*! Data_byte_6 - Data Byte 6 */ #define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) #define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) #define CAN_WMB_D47_Data_byte_5_SHIFT (16U) /*! Data_byte_5 - Data Byte 5 */ #define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) #define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) #define CAN_WMB_D47_Data_byte_4_SHIFT (24U) /*! Data_byte_4 - Data Byte 4 */ #define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) /*! @} */ /* The count of CAN_WMB_D47 */ #define CAN_WMB_D47_COUNT (4U) /*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ /*! @{ */ #define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) #define CAN_EPRS_ENPRESDIV_SHIFT (0U) /*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ #define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) #define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) #define CAN_EPRS_EDPRESDIV_SHIFT (16U) /*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ #define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) /*! @} */ /*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ /*! @{ */ #define CAN_ENCBT_NTSEG1_MASK (0xFFU) #define CAN_ENCBT_NTSEG1_SHIFT (0U) /*! NTSEG1 - Nominal Time Segment 1 */ #define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) #define CAN_ENCBT_NTSEG2_MASK (0x7F000U) #define CAN_ENCBT_NTSEG2_SHIFT (12U) /*! NTSEG2 - Nominal Time Segment 2 */ #define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) #define CAN_ENCBT_NRJW_MASK (0x1FC00000U) #define CAN_ENCBT_NRJW_SHIFT (22U) /*! NRJW - Nominal Resynchronization Jump Width */ #define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) /*! @} */ /*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ /*! @{ */ #define CAN_EDCBT_DTSEG1_MASK (0x1FU) #define CAN_EDCBT_DTSEG1_SHIFT (0U) /*! DTSEG1 - Data Phase Segment 1 */ #define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) #define CAN_EDCBT_DTSEG2_MASK (0xF000U) #define CAN_EDCBT_DTSEG2_SHIFT (12U) /*! DTSEG2 - Data Phase Time Segment 2 */ #define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) #define CAN_EDCBT_DRJW_MASK (0x3C00000U) #define CAN_EDCBT_DRJW_SHIFT (22U) /*! DRJW - Data Phase Resynchronization Jump Width */ #define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) /*! @} */ /*! @name ETDC - Enhanced Transceiver Delay Compensation */ /*! @{ */ #define CAN_ETDC_ETDCVAL_MASK (0xFFU) #define CAN_ETDC_ETDCVAL_SHIFT (0U) /*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ #define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) #define CAN_ETDC_ETDCFAIL_MASK (0x8000U) #define CAN_ETDC_ETDCFAIL_SHIFT (15U) /*! ETDCFAIL - Transceiver Delay Compensation Fail * 0b0..In range * 0b1..Out of range */ #define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) #define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) #define CAN_ETDC_ETDCOFF_SHIFT (16U) /*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ #define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) #define CAN_ETDC_TDMDIS_MASK (0x40000000U) #define CAN_ETDC_TDMDIS_SHIFT (30U) /*! TDMDIS - Transceiver Delay Measurement Disable * 0b0..Enable * 0b1..Disable */ #define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) #define CAN_ETDC_ETDCEN_MASK (0x80000000U) #define CAN_ETDC_ETDCEN_SHIFT (31U) /*! ETDCEN - Transceiver Delay Compensation Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) /*! @} */ /*! @name FDCTRL - CAN FD Control */ /*! @{ */ #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) #define CAN_FDCTRL_TDCVAL_SHIFT (0U) /*! TDCVAL - Transceiver Delay Compensation Value */ #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) #define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) #define CAN_FDCTRL_TDCOFF_SHIFT (8U) /*! TDCOFF - Transceiver Delay Compensation Offset */ #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) /*! TDCFAIL - Transceiver Delay Compensation Fail * 0b0..In range * 0b1..Out of range */ #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) #define CAN_FDCTRL_TDCEN_MASK (0x8000U) #define CAN_FDCTRL_TDCEN_SHIFT (15U) /*! TDCEN - Transceiver Delay Compensation Enable * 0b0..Disable * 0b1..Enable */ #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) #define CAN_FDCTRL_MBDSR0_SHIFT (16U) /*! MBDSR0 - Message Buffer Data Size for Region 0 * 0b00..8 bytes * 0b01..16 bytes * 0b10..32 bytes * 0b11..64 bytes */ #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) #define CAN_FDCTRL_FDRATE_SHIFT (31U) /*! FDRATE - Bit Rate Switch Enable * 0b0..Disable * 0b1..Enable */ #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) /*! @} */ /*! @name FDCBT - CAN FD Bit Timing */ /*! @{ */ #define CAN_FDCBT_FPSEG2_MASK (0x7U) #define CAN_FDCBT_FPSEG2_SHIFT (0U) /*! FPSEG2 - Fast Phase Segment 2 */ #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) #define CAN_FDCBT_FPSEG1_MASK (0xE0U) #define CAN_FDCBT_FPSEG1_SHIFT (5U) /*! FPSEG1 - Fast Phase Segment 1 */ #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) #define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) #define CAN_FDCBT_FPROPSEG_SHIFT (10U) /*! FPROPSEG - Fast Propagation Segment */ #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) #define CAN_FDCBT_FRJW_MASK (0x70000U) #define CAN_FDCBT_FRJW_SHIFT (16U) /*! FRJW - Fast Resync Jump Width */ #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) #define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) #define CAN_FDCBT_FPRESDIV_SHIFT (20U) /*! FPRESDIV - Fast Prescaler Division Factor */ #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) /*! @} */ /*! @name FDCRC - CAN FD CRC */ /*! @{ */ #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) #define CAN_FDCRC_FD_TXCRC_SHIFT (0U) /*! FD_TXCRC - Extended Transmitted CRC value */ #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) /*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) /*! @} */ /*! @name ERFCR - Enhanced RX FIFO Control */ /*! @{ */ #define CAN_ERFCR_ERFWM_MASK (0x1FU) #define CAN_ERFCR_ERFWM_SHIFT (0U) /*! ERFWM - Enhanced RX FIFO Watermark */ #define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) #define CAN_ERFCR_NFE_MASK (0x3F00U) #define CAN_ERFCR_NFE_SHIFT (8U) /*! NFE - Number of Enhanced RX FIFO Filter Elements */ #define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) #define CAN_ERFCR_NEXIF_MASK (0x7F0000U) #define CAN_ERFCR_NEXIF_SHIFT (16U) /*! NEXIF - Number of Extended ID Filter Elements */ #define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) #define CAN_ERFCR_DMALW_MASK (0x7C000000U) #define CAN_ERFCR_DMALW_SHIFT (26U) /*! DMALW - DMA Last Word */ #define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) #define CAN_ERFCR_ERFEN_MASK (0x80000000U) #define CAN_ERFCR_ERFEN_SHIFT (31U) /*! ERFEN - Enhanced RX FIFO enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) /*! @} */ /*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ /*! @{ */ #define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) #define CAN_ERFIER_ERFDAIE_SHIFT (28U) /*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) #define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) #define CAN_ERFIER_ERFWMIIE_SHIFT (29U) /*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) #define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) #define CAN_ERFIER_ERFOVFIE_SHIFT (30U) /*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) #define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) #define CAN_ERFIER_ERFUFWIE_SHIFT (31U) /*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) /*! @} */ /*! @name ERFSR - Enhanced RX FIFO Status */ /*! @{ */ #define CAN_ERFSR_ERFEL_MASK (0x3FU) #define CAN_ERFSR_ERFEL_SHIFT (0U) /*! ERFEL - Enhanced RX FIFO Elements */ #define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) #define CAN_ERFSR_ERFF_MASK (0x10000U) #define CAN_ERFSR_ERFF_SHIFT (16U) /*! ERFF - Enhanced RX FIFO Full Flag * 0b0..Not full * 0b1..Full */ #define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) #define CAN_ERFSR_ERFE_MASK (0x20000U) #define CAN_ERFSR_ERFE_SHIFT (17U) /*! ERFE - Enhanced RX FIFO Empty Flag * 0b0..Not empty * 0b1..Empty */ #define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) #define CAN_ERFSR_ERFCLR_MASK (0x8000000U) #define CAN_ERFSR_ERFCLR_SHIFT (27U) /*! ERFCLR - Enhanced RX FIFO Clear * 0b0..No effect * 0b1..Clear enhanced RX FIFO content */ #define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) #define CAN_ERFSR_ERFDA_MASK (0x10000000U) #define CAN_ERFSR_ERFDA_SHIFT (28U) /*! ERFDA - Enhanced RX FIFO Data Available Flag * 0b0..No such occurrence * 0b1..At least one message stored in Enhanced RX FIFO */ #define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) #define CAN_ERFSR_ERFWMI_SHIFT (29U) /*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag * 0b0..No such occurrence * 0b1..Number of messages in FIFO is greater than the watermark */ #define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) #define CAN_ERFSR_ERFOVF_MASK (0x40000000U) #define CAN_ERFSR_ERFOVF_SHIFT (30U) /*! ERFOVF - Enhanced RX FIFO Overflow Flag * 0b0..No such occurrence * 0b1..Overflow */ #define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) #define CAN_ERFSR_ERFUFW_MASK (0x80000000U) #define CAN_ERFSR_ERFUFW_SHIFT (31U) /*! ERFUFW - Enhanced RX FIFO Underflow Flag * 0b0..No such occurrence * 0b1..Underflow */ #define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) /*! @} */ /*! @name ERFFEL - Enhanced RX FIFO Filter Element */ /*! @{ */ #define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) #define CAN_ERFFEL_FEL_SHIFT (0U) /*! FEL - Filter Element Bits */ #define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) /*! @} */ /* The count of CAN_ERFFEL */ #define CAN_ERFFEL_COUNT (32U) /*! * @} */ /* end of group CAN_Register_Masks */ /* CAN - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CAN0 base address */ #define CAN0_BASE (0x500D4000u) /** Peripheral CAN0 base address */ #define CAN0_BASE_NS (0x400D4000u) /** Peripheral CAN0 base pointer */ #define CAN0 ((CAN_Type *)CAN0_BASE) /** Peripheral CAN0 base pointer */ #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) /** Peripheral CAN1 base address */ #define CAN1_BASE (0x500D8000u) /** Peripheral CAN1 base address */ #define CAN1_BASE_NS (0x400D8000u) /** Peripheral CAN1 base pointer */ #define CAN1 ((CAN_Type *)CAN1_BASE) /** Peripheral CAN1 base pointer */ #define CAN1_NS ((CAN_Type *)CAN1_BASE_NS) /** Array initializer of CAN peripheral base addresses */ #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } /** Array initializer of CAN peripheral base pointers */ #define CAN_BASE_PTRS { CAN0, CAN1 } /** Array initializer of CAN peripheral base addresses */ #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS, CAN1_BASE_NS } /** Array initializer of CAN peripheral base pointers */ #define CAN_BASE_PTRS_NS { CAN0_NS, CAN1_NS } #else /** Peripheral CAN0 base address */ #define CAN0_BASE (0x400D4000u) /** Peripheral CAN0 base pointer */ #define CAN0 ((CAN_Type *)CAN0_BASE) /** Peripheral CAN1 base address */ #define CAN1_BASE (0x400D8000u) /** Peripheral CAN1 base pointer */ #define CAN1 ((CAN_Type *)CAN1_BASE) /** Array initializer of CAN peripheral base addresses */ #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } /** Array initializer of CAN peripheral base pointers */ #define CAN_BASE_PTRS { CAN0, CAN1 } #endif /** Interrupt vectors for the CAN peripheral type */ #define CAN_Rx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } #define CAN_Tx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } #define CAN_Wake_Up_IRQS { CAN0_IRQn, CAN1_IRQn } #define CAN_Error_IRQS { CAN0_IRQn, CAN1_IRQn } #define CAN_Bus_Off_IRQS { CAN0_IRQn, CAN1_IRQn } #define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn, CAN1_IRQn } /*! * @} */ /* end of group CAN_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer * @{ */ /** CDOG - Register Layout Typedef */ typedef struct { __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ __IO uint32_t RELOAD; /**< Instruction Timer Reload Register, offset: 0x4 */ __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer Register, offset: 0x8 */ uint8_t RESERVED_0[4]; __I uint32_t STATUS; /**< Status 1 Register, offset: 0x10 */ __I uint32_t STATUS2; /**< Status 2 Register, offset: 0x14 */ __IO uint32_t FLAGS; /**< Flags Register, offset: 0x18 */ __IO uint32_t PERSISTENT; /**< Persistent Data Storage Register, offset: 0x1C */ __O uint32_t START; /**< START Command Register, offset: 0x20 */ __O uint32_t STOP; /**< STOP Command Register, offset: 0x24 */ __O uint32_t RESTART; /**< RESTART Command Register, offset: 0x28 */ __O uint32_t ADD; /**< ADD Command Register, offset: 0x2C */ __O uint32_t ADD1; /**< ADD1 Command Register, offset: 0x30 */ __O uint32_t ADD16; /**< ADD16 Command Register, offset: 0x34 */ __O uint32_t ADD256; /**< ADD256 Command Register, offset: 0x38 */ __O uint32_t SUB; /**< SUB Command Register, offset: 0x3C */ __O uint32_t SUB1; /**< SUB1 Command Register, offset: 0x40 */ __O uint32_t SUB16; /**< SUB16 Command Register, offset: 0x44 */ __O uint32_t SUB256; /**< SUB256 Command Register, offset: 0x48 */ __O uint32_t ASSERT16; /**< ASSERT16 Command Register, offset: 0x4C */ } CDOG_Type; /* ---------------------------------------------------------------------------- -- CDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CDOG_Register_Masks CDOG Register Masks * @{ */ /*! @name CONTROL - Control Register */ /*! @{ */ #define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) #define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) /*! LOCK_CTRL - Lock control * 0b01..Locked * 0b10..Unlocked */ #define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) #define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) #define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) /*! TIMEOUT_CTRL - TIMEOUT fault control * 0b100..Disable both reset and interrupt * 0b001..Enable reset * 0b010..Enable interrupt */ #define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) #define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) #define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) /*! MISCOMPARE_CTRL - MISCOMPARE fault control * 0b100..Disable both reset and interrupt * 0b001..Enable reset * 0b010..Enable interrupt */ #define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) #define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) #define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) /*! SEQUENCE_CTRL - SEQUENCE fault control * 0b001..Enable reset * 0b010..Enable interrupt * 0b100..Disable both reset and interrupt */ #define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) #define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) #define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) /*! STATE_CTRL - STATE fault control * 0b001..Enable reset * 0b010..Enable interrupt * 0b100..Disable both reset and interrupt */ #define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) #define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) #define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) /*! ADDRESS_CTRL - ADDRESS fault control * 0b001..Enable reset * 0b010..Enable interrupt * 0b100..Disable both reset and interrupt */ #define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) #define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) #define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) /*! IRQ_PAUSE - IRQ pause control * 0b01..Keep the timer running * 0b10..Stop the timer */ #define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) #define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) #define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) /*! DEBUG_HALT_CTRL - DEBUG_HALT control * 0b01..Keep the timer running * 0b10..Stop the timer */ #define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) /*! @} */ /*! @name RELOAD - Instruction Timer Reload Register */ /*! @{ */ #define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) #define CDOG_RELOAD_RLOAD_SHIFT (0U) /*! RLOAD - Instruction Timer reload value */ #define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) /*! @} */ /*! @name INSTRUCTION_TIMER - Instruction Timer Register */ /*! @{ */ #define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) #define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) /*! INSTIM - Current value of the Instruction Timer */ #define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) /*! @} */ /*! @name STATUS - Status 1 Register */ /*! @{ */ #define CDOG_STATUS_NUMTOF_MASK (0xFFU) #define CDOG_STATUS_NUMTOF_SHIFT (0U) /*! NUMTOF - Number of TIMEOUT faults since the last POR */ #define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) #define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) #define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) /*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */ #define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) #define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) #define CDOG_STATUS_NUMILSEQF_SHIFT (16U) /*! NUMILSEQF - Number of SEQUENCE faults since the last POR */ #define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) #define CDOG_STATUS_CURST_MASK (0xF0000000U) #define CDOG_STATUS_CURST_SHIFT (28U) /*! CURST - Current State */ #define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) /*! @} */ /*! @name STATUS2 - Status 2 Register */ /*! @{ */ #define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) #define CDOG_STATUS2_NUMCNTF_SHIFT (0U) /*! NUMCNTF - Number of CONTROL faults since the last POR */ #define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) #define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) #define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) /*! NUMILLSTF - Number of STATE faults since the last POR */ #define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) #define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) #define CDOG_STATUS2_NUMILLA_SHIFT (16U) /*! NUMILLA - Number of ADDRESS faults since the last POR */ #define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) /*! @} */ /*! @name FLAGS - Flags Register */ /*! @{ */ #define CDOG_FLAGS_TO_FLAG_MASK (0x1U) #define CDOG_FLAGS_TO_FLAG_SHIFT (0U) /*! TO_FLAG - TIMEOUT fault flag * 0b0..A TIMEOUT fault has not occurred * 0b1..A TIMEOUT fault has occurred */ #define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) #define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) #define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) /*! MISCOM_FLAG - MISCOMPARE fault flag * 0b0..A MISCOMPARE fault has not occurred * 0b1..A MISCOMPARE fault has occurred */ #define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) #define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) #define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) /*! SEQ_FLAG - SEQUENCE fault flag * 0b0..A SEQUENCE fault has not occurred * 0b1..A SEQUENCE fault has occurred */ #define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) #define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) #define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) /*! CNT_FLAG - CONTROL fault flag * 0b0..A CONTROL fault has not occurred * 0b1..A CONTROL fault has occurred */ #define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) #define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) #define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) /*! STATE_FLAG - STATE fault flag * 0b0..A STATE fault has not occurred * 0b1..A STATE fault has occurred */ #define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) #define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) #define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) /*! ADDR_FLAG - ADDRESS fault flag * 0b0..An ADDRESS fault has not occurred * 0b1..An ADDRESS fault has occurred */ #define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) #define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) #define CDOG_FLAGS_POR_FLAG_SHIFT (16U) /*! POR_FLAG - Power-on reset flag * 0b0..A Power-on reset event has not occurred * 0b1..A Power-on reset event has occurred */ #define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) /*! @} */ /*! @name PERSISTENT - Persistent Data Storage Register */ /*! @{ */ #define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) #define CDOG_PERSISTENT_PERSIS_SHIFT (0U) /*! PERSIS - Persistent Storage */ #define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) /*! @} */ /*! @name START - START Command Register */ /*! @{ */ #define CDOG_START_STRT_MASK (0xFFFFFFFFU) #define CDOG_START_STRT_SHIFT (0U) /*! STRT - Start command */ #define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) /*! @} */ /*! @name STOP - STOP Command Register */ /*! @{ */ #define CDOG_STOP_STP_MASK (0xFFFFFFFFU) #define CDOG_STOP_STP_SHIFT (0U) /*! STP - Stop command */ #define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) /*! @} */ /*! @name RESTART - RESTART Command Register */ /*! @{ */ #define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) #define CDOG_RESTART_RSTRT_SHIFT (0U) /*! RSTRT - Restart command */ #define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) /*! @} */ /*! @name ADD - ADD Command Register */ /*! @{ */ #define CDOG_ADD_AD_MASK (0xFFFFFFFFU) #define CDOG_ADD_AD_SHIFT (0U) /*! AD - ADD Write Value */ #define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) /*! @} */ /*! @name ADD1 - ADD1 Command Register */ /*! @{ */ #define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) #define CDOG_ADD1_AD1_SHIFT (0U) /*! AD1 - ADD 1 */ #define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) /*! @} */ /*! @name ADD16 - ADD16 Command Register */ /*! @{ */ #define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) #define CDOG_ADD16_AD16_SHIFT (0U) /*! AD16 - ADD 16 */ #define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) /*! @} */ /*! @name ADD256 - ADD256 Command Register */ /*! @{ */ #define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) #define CDOG_ADD256_AD256_SHIFT (0U) /*! AD256 - ADD 256 */ #define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) /*! @} */ /*! @name SUB - SUB Command Register */ /*! @{ */ #define CDOG_SUB_SB_MASK (0xFFFFFFFFU) #define CDOG_SUB_SB_SHIFT (0U) /*! SB - Subtract Write Value */ #define CDOG_SUB_SB(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK) /*! @} */ /*! @name SUB1 - SUB1 Command Register */ /*! @{ */ #define CDOG_SUB1_SB1_MASK (0xFFFFFFFFU) #define CDOG_SUB1_SB1_SHIFT (0U) /*! SB1 - Subtract 1 */ #define CDOG_SUB1_SB1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK) /*! @} */ /*! @name SUB16 - SUB16 Command Register */ /*! @{ */ #define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) #define CDOG_SUB16_SB16_SHIFT (0U) /*! SB16 - Subtract 16 */ #define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) /*! @} */ /*! @name SUB256 - SUB256 Command Register */ /*! @{ */ #define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) #define CDOG_SUB256_SB256_SHIFT (0U) /*! SB256 - Subtract 256 */ #define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) /*! @} */ /*! @name ASSERT16 - ASSERT16 Command Register */ /*! @{ */ #define CDOG_ASSERT16_AST16_MASK (0xFFFFFFFFU) #define CDOG_ASSERT16_AST16_SHIFT (0U) /*! AST16 - ASSERT16 Command */ #define CDOG_ASSERT16_AST16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK) /*! @} */ /*! * @} */ /* end of group CDOG_Register_Masks */ /* CDOG - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CDOG0 base address */ #define CDOG0_BASE (0x500BB000u) /** Peripheral CDOG0 base address */ #define CDOG0_BASE_NS (0x400BB000u) /** Peripheral CDOG0 base pointer */ #define CDOG0 ((CDOG_Type *)CDOG0_BASE) /** Peripheral CDOG0 base pointer */ #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) /** Peripheral CDOG1 base address */ #define CDOG1_BASE (0x500BC000u) /** Peripheral CDOG1 base address */ #define CDOG1_BASE_NS (0x400BC000u) /** Peripheral CDOG1 base pointer */ #define CDOG1 ((CDOG_Type *)CDOG1_BASE) /** Peripheral CDOG1 base pointer */ #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) /** Array initializer of CDOG peripheral base addresses */ #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } /** Array initializer of CDOG peripheral base pointers */ #define CDOG_BASE_PTRS { CDOG0, CDOG1 } /** Array initializer of CDOG peripheral base addresses */ #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } /** Array initializer of CDOG peripheral base pointers */ #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } #else /** Peripheral CDOG0 base address */ #define CDOG0_BASE (0x400BB000u) /** Peripheral CDOG0 base pointer */ #define CDOG0 ((CDOG_Type *)CDOG0_BASE) /** Peripheral CDOG1 base address */ #define CDOG1_BASE (0x400BC000u) /** Peripheral CDOG1 base pointer */ #define CDOG1 ((CDOG_Type *)CDOG1_BASE) /** Array initializer of CDOG peripheral base addresses */ #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } /** Array initializer of CDOG peripheral base pointers */ #define CDOG_BASE_PTRS { CDOG0, CDOG1 } #endif /** Interrupt vectors for the CDOG peripheral type */ #define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } /*! * @} */ /* end of group CDOG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer * @{ */ /** CMC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t CKCTRL; /**< Clock Control, offset: 0x10 */ __IO uint32_t CKSTAT; /**< Clock Status, offset: 0x14 */ __IO uint32_t PMPROT; /**< Power Mode Protection, offset: 0x18 */ __O uint32_t GPMCTRL; /**< Global Power Mode Control, offset: 0x1C */ __IO uint32_t PMCTRL[2]; /**< Power Mode Control, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[88]; __I uint32_t SRS; /**< System Reset Status, offset: 0x80 */ __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x84 */ __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x88 */ __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x8C */ __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x90 */ uint8_t RESERVED_2[8]; __I uint32_t RSTCNT; /**< Reset Count Register, offset: 0x9C */ __IO uint32_t MR[1]; /**< Mode, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_3[12]; __IO uint32_t FM[1]; /**< Force Mode, array offset: 0xB0, array step: 0x4 */ uint8_t RESERVED_4[12]; __IO uint32_t SRAMDIS[1]; /**< SRAM Disable, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[12]; __IO uint32_t SRAMRET[1]; /**< SRAM Retention, array offset: 0xD0, array step: 0x4 */ uint8_t RESERVED_6[12]; __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ uint8_t RESERVED_7[28]; __IO uint32_t BSR; /**< BootROM Status Register, offset: 0x100 */ uint8_t RESERVED_8[8]; __IO uint32_t BLR; /**< BootROM Lock Register, offset: 0x10C */ __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ uint8_t RESERVED_9[12]; __IO uint32_t DBGCTL; /**< Debug Control, offset: 0x120 */ } CMC_Type; /* ---------------------------------------------------------------------------- -- CMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMC_Register_Masks CMC Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define CMC_VERID_FEATURE_MASK (0xFFFFU) #define CMC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number */ #define CMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK) #define CMC_VERID_MINOR_MASK (0xFF0000U) #define CMC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define CMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK) #define CMC_VERID_MAJOR_MASK (0xFF000000U) #define CMC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define CMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK) /*! @} */ /*! @name CKCTRL - Clock Control */ /*! @{ */ #define CMC_CKCTRL_CKMODE_MASK (0xFU) #define CMC_CKCTRL_CKMODE_SHIFT (0U) /*! CKMODE - Clocking Mode * 0b0000..No clock gating * 0b0001..Core clock is gated * 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode. */ #define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) #define CMC_CKCTRL_LOCK_MASK (0x80000000U) #define CMC_CKCTRL_LOCK_SHIFT (31U) /*! LOCK - Lock * 0b0..Allowed * 0b1..Blocked */ #define CMC_CKCTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK) /*! @} */ /*! @name CKSTAT - Clock Status */ /*! @{ */ #define CMC_CKSTAT_CKMODE_MASK (0xFU) #define CMC_CKSTAT_CKMODE_SHIFT (0U) /*! CKMODE - Low Power Status * 0b0000..Core clock not gated * 0b0001..Core clock was gated * 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode * *.. */ #define CMC_CKSTAT_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK) #define CMC_CKSTAT_WAKEUP_MASK (0xFF00U) #define CMC_CKSTAT_WAKEUP_SHIFT (8U) /*! WAKEUP - Wake-up Source */ #define CMC_CKSTAT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK) #define CMC_CKSTAT_VALID_MASK (0x80000000U) #define CMC_CKSTAT_VALID_SHIFT (31U) /*! VALID - Clock Status Valid * 0b0..Core clock not gated * 0b1..Core clock was gated due to Low-Power mode entry */ #define CMC_CKSTAT_VALID(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK) /*! @} */ /*! @name PMPROT - Power Mode Protection */ /*! @{ */ #define CMC_PMPROT_LPMODE_MASK (0xFU) #define CMC_PMPROT_LPMODE_SHIFT (0U) /*! LPMODE - Low-Power Mode * 0b0000..Not allowed * 0b0001..Allowed * 0b0010..Allowed * 0b0011..Allowed * 0b0100..Allowed * 0b0101..Allowed * 0b0110..Allowed * 0b0111..Allowed * 0b1000..Allowed * 0b1001..Allowed * 0b1010..Allowed * 0b1011..Allowed * 0b1100..Allowed * 0b1101..Allowed * 0b1110..Allowed * 0b1111..Allowed */ #define CMC_PMPROT_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK) #define CMC_PMPROT_LOCK_MASK (0x80000000U) #define CMC_PMPROT_LOCK_SHIFT (31U) /*! LOCK - Lock Register * 0b0..Allowed * 0b1..Blocked */ #define CMC_PMPROT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK) /*! @} */ /*! @name GPMCTRL - Global Power Mode Control */ /*! @{ */ #define CMC_GPMCTRL_LPMODE_MASK (0xFU) #define CMC_GPMCTRL_LPMODE_SHIFT (0U) /*! LPMODE - Low-Power Mode */ #define CMC_GPMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK) /*! @} */ /*! @name PMCTRL - Power Mode Control */ /*! @{ */ #define CMC_PMCTRL_LPMODE_MASK (0xFU) #define CMC_PMCTRL_LPMODE_SHIFT (0U) /*! LPMODE - Low-Power Mode * 0b0000..Active/Sleep * 0b0001..Deep Sleep * 0b0011..Power Down * 0b0111..Reserved * 0b1111..Deep-Power Down */ #define CMC_PMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK) /*! @} */ /* The count of CMC_PMCTRL */ #define CMC_PMCTRL_COUNT (2U) /*! @name SRS - System Reset Status */ /*! @{ */ #define CMC_SRS_WAKEUP_MASK (0x1U) #define CMC_SRS_WAKEUP_SHIFT (0U) /*! WAKEUP - Wake-up Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK) #define CMC_SRS_POR_MASK (0x2U) #define CMC_SRS_POR_SHIFT (1U) /*! POR - Power-on Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK) #define CMC_SRS_VD_MASK (0x4U) #define CMC_SRS_VD_SHIFT (2U) /*! VD - Voltage Detect Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK) #define CMC_SRS_WARM_MASK (0x10U) #define CMC_SRS_WARM_SHIFT (4U) /*! WARM - Warm Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK) #define CMC_SRS_FATAL_MASK (0x20U) #define CMC_SRS_FATAL_SHIFT (5U) /*! FATAL - Fatal Reset * 0b0..Reset was not generated * 0b1..Reset was generated */ #define CMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK) #define CMC_SRS_PIN_MASK (0x100U) #define CMC_SRS_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Reset was not generated * 0b1..Reset was generated */ #define CMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK) #define CMC_SRS_DAP_MASK (0x200U) #define CMC_SRS_DAP_SHIFT (9U) /*! DAP - Debug Access Port Reset * 0b0..Reset was not generated * 0b1..Reset was generated */ #define CMC_SRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK) #define CMC_SRS_RSTACK_MASK (0x400U) #define CMC_SRS_RSTACK_SHIFT (10U) /*! RSTACK - Reset Timeout * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK) #define CMC_SRS_LPACK_MASK (0x800U) #define CMC_SRS_LPACK_SHIFT (11U) /*! LPACK - Low Power Acknowledge Timeout Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK) #define CMC_SRS_SCG_MASK (0x1000U) #define CMC_SRS_SCG_SHIFT (12U) /*! SCG - System Clock Generation Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK) #define CMC_SRS_WWDT0_MASK (0x2000U) #define CMC_SRS_WWDT0_SHIFT (13U) /*! WWDT0 - Windowed Watchdog 0 Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK) #define CMC_SRS_SW_MASK (0x4000U) #define CMC_SRS_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK) #define CMC_SRS_LOCKUP_MASK (0x8000U) #define CMC_SRS_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK) #define CMC_SRS_CPU1_MASK (0x10000U) #define CMC_SRS_CPU1_SHIFT (16U) /*! CPU1 - CPU1 System Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CPU1_SHIFT)) & CMC_SRS_CPU1_MASK) #define CMC_SRS_VBAT_MASK (0x1000000U) #define CMC_SRS_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VBAT_SHIFT)) & CMC_SRS_VBAT_MASK) #define CMC_SRS_WWDT1_MASK (0x2000000U) #define CMC_SRS_WWDT1_SHIFT (25U) /*! WWDT1 - Windowed Watchdog 1 Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SRS_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT1_SHIFT)) & CMC_SRS_WWDT1_MASK) #define CMC_SRS_CDOG0_MASK (0x4000000U) #define CMC_SRS_CDOG0_SHIFT (26U) /*! CDOG0 - Code Watchdog 0 Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK) #define CMC_SRS_CDOG1_MASK (0x8000000U) #define CMC_SRS_CDOG1_SHIFT (27U) /*! CDOG1 - Code Watchdog 1 Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG1_SHIFT)) & CMC_SRS_CDOG1_MASK) #define CMC_SRS_JTAG_MASK (0x10000000U) #define CMC_SRS_JTAG_SHIFT (28U) /*! JTAG - JTAG System Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK) #define CMC_SRS_SECVIO_MASK (0x40000000U) #define CMC_SRS_SECVIO_SHIFT (30U) /*! SECVIO - Security Violation Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SECVIO_SHIFT)) & CMC_SRS_SECVIO_MASK) #define CMC_SRS_TAMPER_MASK (0x80000000U) #define CMC_SRS_TAMPER_SHIFT (31U) /*! TAMPER - Tamper Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_TAMPER_SHIFT)) & CMC_SRS_TAMPER_MASK) /*! @} */ /*! @name RPC - Reset Pin Control */ /*! @{ */ #define CMC_RPC_FILTCFG_MASK (0x1FU) #define CMC_RPC_FILTCFG_SHIFT (0U) /*! FILTCFG - Reset Filter Configuration */ #define CMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK) #define CMC_RPC_FILTEN_MASK (0x100U) #define CMC_RPC_FILTEN_SHIFT (8U) /*! FILTEN - Filter Enable * 0b0..Disables * 0b1..Enables */ #define CMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK) #define CMC_RPC_LPFEN_MASK (0x200U) #define CMC_RPC_LPFEN_SHIFT (9U) /*! LPFEN - Low-Power Filter Enable * 0b0..Disables * 0b1..Enables */ #define CMC_RPC_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK) /*! @} */ /*! @name SSRS - Sticky System Reset Status */ /*! @{ */ #define CMC_SSRS_WAKEUP_MASK (0x1U) #define CMC_SSRS_WAKEUP_SHIFT (0U) /*! WAKEUP - Wake-up Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK) #define CMC_SSRS_POR_MASK (0x2U) #define CMC_SSRS_POR_SHIFT (1U) /*! POR - Power-on Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK) #define CMC_SSRS_VD_MASK (0x4U) #define CMC_SSRS_VD_SHIFT (2U) /*! VD - Voltage Detect Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK) #define CMC_SSRS_WARM_MASK (0x10U) #define CMC_SSRS_WARM_SHIFT (4U) /*! WARM - Warm Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK) #define CMC_SSRS_FATAL_MASK (0x20U) #define CMC_SSRS_FATAL_SHIFT (5U) /*! FATAL - Fatal Reset * 0b0..Reset was not generated * 0b1..Reset was generated */ #define CMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK) #define CMC_SSRS_PIN_MASK (0x100U) #define CMC_SSRS_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK) #define CMC_SSRS_DAP_MASK (0x200U) #define CMC_SSRS_DAP_SHIFT (9U) /*! DAP - DAP Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK) #define CMC_SSRS_RSTACK_MASK (0x400U) #define CMC_SSRS_RSTACK_SHIFT (10U) /*! RSTACK - Reset Timeout * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK) #define CMC_SSRS_LPACK_MASK (0x800U) #define CMC_SSRS_LPACK_SHIFT (11U) /*! LPACK - Low Power Acknowledge Timeout Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK) #define CMC_SSRS_SCG_MASK (0x1000U) #define CMC_SSRS_SCG_SHIFT (12U) /*! SCG - System Clock Generation Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK) #define CMC_SSRS_WWDT0_MASK (0x2000U) #define CMC_SSRS_WWDT0_SHIFT (13U) /*! WWDT0 - Windowed Watchdog 0 Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SSRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK) #define CMC_SSRS_SW_MASK (0x4000U) #define CMC_SSRS_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK) #define CMC_SSRS_LOCKUP_MASK (0x8000U) #define CMC_SSRS_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK) #define CMC_SSRS_CPU1_MASK (0x10000U) #define CMC_SSRS_CPU1_SHIFT (16U) /*! CPU1 - CPU1 Reset * 0b0..Reset not generated from CPU1 reset source. * 0b1..Reset generated from CPU1 reset source. */ #define CMC_SSRS_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CPU1_SHIFT)) & CMC_SSRS_CPU1_MASK) #define CMC_SSRS_VBAT_MASK (0x1000000U) #define CMC_SSRS_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VBAT_SHIFT)) & CMC_SSRS_VBAT_MASK) #define CMC_SSRS_WWDT1_MASK (0x2000000U) #define CMC_SSRS_WWDT1_SHIFT (25U) /*! WWDT1 - Windowed Watchdog 1 Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SSRS_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT1_SHIFT)) & CMC_SSRS_WWDT1_MASK) #define CMC_SSRS_CDOG0_MASK (0x4000000U) #define CMC_SSRS_CDOG0_SHIFT (26U) /*! CDOG0 - Code Watchdog 0 Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SSRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK) #define CMC_SSRS_CDOG1_MASK (0x8000000U) #define CMC_SSRS_CDOG1_SHIFT (27U) /*! CDOG1 - Code Watchdog 1 Reset * 0b0..Reset is not generated * 0b1..Reset is generated */ #define CMC_SSRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG1_SHIFT)) & CMC_SSRS_CDOG1_MASK) #define CMC_SSRS_JTAG_MASK (0x10000000U) #define CMC_SSRS_JTAG_SHIFT (28U) /*! JTAG - JTAG System Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK) #define CMC_SSRS_SECVIO_MASK (0x40000000U) #define CMC_SSRS_SECVIO_SHIFT (30U) /*! SECVIO - Security Violation Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SECVIO_SHIFT)) & CMC_SSRS_SECVIO_MASK) #define CMC_SSRS_TAMPER_MASK (0x80000000U) #define CMC_SSRS_TAMPER_SHIFT (31U) /*! TAMPER - Tamper Reset * 0b0..Reset not generated * 0b1..Reset generated */ #define CMC_SSRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_TAMPER_SHIFT)) & CMC_SSRS_TAMPER_MASK) /*! @} */ /*! @name SRIE - System Reset Interrupt Enable */ /*! @{ */ #define CMC_SRIE_PIN_MASK (0x100U) #define CMC_SRIE_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK) #define CMC_SRIE_DAP_MASK (0x200U) #define CMC_SRIE_DAP_SHIFT (9U) /*! DAP - DAP Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK) #define CMC_SRIE_LPACK_MASK (0x800U) #define CMC_SRIE_LPACK_SHIFT (11U) /*! LPACK - Low Power Acknowledge Timeout Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK) #define CMC_SRIE_SCG_MASK (0x1000U) #define CMC_SRIE_SCG_SHIFT (12U) /*! SCG - System Clock Generation Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK) #define CMC_SRIE_WWDT0_MASK (0x2000U) #define CMC_SRIE_WWDT0_SHIFT (13U) /*! WWDT0 - Windowed Watchdog 0 Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK) #define CMC_SRIE_SW_MASK (0x4000U) #define CMC_SRIE_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK) #define CMC_SRIE_LOCKUP_MASK (0x8000U) #define CMC_SRIE_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK) #define CMC_SRIE_CPU1_MASK (0x10000U) #define CMC_SRIE_CPU1_SHIFT (16U) /*! CPU1 - CPU1 Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CPU1_SHIFT)) & CMC_SRIE_CPU1_MASK) #define CMC_SRIE_VBAT_MASK (0x1000000U) #define CMC_SRIE_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_VBAT_SHIFT)) & CMC_SRIE_VBAT_MASK) #define CMC_SRIE_WWDT1_MASK (0x2000000U) #define CMC_SRIE_WWDT1_SHIFT (25U) /*! WWDT1 - Windowed Watchdog 1 Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT1_SHIFT)) & CMC_SRIE_WWDT1_MASK) #define CMC_SRIE_CDOG0_MASK (0x4000000U) #define CMC_SRIE_CDOG0_SHIFT (26U) /*! CDOG0 - Code Watchdog 0 Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK) #define CMC_SRIE_CDOG1_MASK (0x8000000U) #define CMC_SRIE_CDOG1_SHIFT (27U) /*! CDOG1 - Code Watchdog 1 Reset * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CMC_SRIE_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG1_SHIFT)) & CMC_SRIE_CDOG1_MASK) /*! @} */ /*! @name SRIF - System Reset Interrupt Flag */ /*! @{ */ #define CMC_SRIF_PIN_MASK (0x100U) #define CMC_SRIF_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK) #define CMC_SRIF_DAP_MASK (0x200U) #define CMC_SRIF_DAP_SHIFT (9U) /*! DAP - DAP Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK) #define CMC_SRIF_LPACK_MASK (0x800U) #define CMC_SRIF_LPACK_SHIFT (11U) /*! LPACK - Low Power Acknowledge Timeout Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK) #define CMC_SRIF_WWDT0_MASK (0x2000U) #define CMC_SRIF_WWDT0_SHIFT (13U) /*! WWDT0 - Windowed Watchdog 0 Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK) #define CMC_SRIF_SW_MASK (0x4000U) #define CMC_SRIF_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK) #define CMC_SRIF_LOCKUP_MASK (0x8000U) #define CMC_SRIF_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK) #define CMC_SRIF_CPU1_MASK (0x10000U) #define CMC_SRIF_CPU1_SHIFT (16U) /*! CPU1 - CPU1 Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CPU1_SHIFT)) & CMC_SRIF_CPU1_MASK) #define CMC_SRIF_VBAT_MASK (0x1000000U) #define CMC_SRIF_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_VBAT_SHIFT)) & CMC_SRIF_VBAT_MASK) #define CMC_SRIF_WWDT1_MASK (0x2000000U) #define CMC_SRIF_WWDT1_SHIFT (25U) /*! WWDT1 - Windowed Watchdog 1 Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT1_SHIFT)) & CMC_SRIF_WWDT1_MASK) #define CMC_SRIF_CDOG0_MASK (0x4000000U) #define CMC_SRIF_CDOG0_SHIFT (26U) /*! CDOG0 - Code Watchdog 0 Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK) #define CMC_SRIF_CDOG1_MASK (0x8000000U) #define CMC_SRIF_CDOG1_SHIFT (27U) /*! CDOG1 - Code Watchdog 1 Reset * 0b0..Reset source not pending * 0b1..Reset source pending */ #define CMC_SRIF_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG1_SHIFT)) & CMC_SRIF_CDOG1_MASK) /*! @} */ /*! @name RSTCNT - Reset Count Register */ /*! @{ */ #define CMC_RSTCNT_COUNT_MASK (0xFFU) #define CMC_RSTCNT_COUNT_SHIFT (0U) /*! COUNT - Count */ #define CMC_RSTCNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CMC_RSTCNT_COUNT_SHIFT)) & CMC_RSTCNT_COUNT_MASK) /*! @} */ /*! @name MR - Mode */ /*! @{ */ #define CMC_MR_ISPMODE_n_MASK (0x1U) #define CMC_MR_ISPMODE_n_SHIFT (0U) /*! ISPMODE_n - In System Programming Mode */ #define CMC_MR_ISPMODE_n(x) (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK) /*! @} */ /* The count of CMC_MR */ #define CMC_MR_COUNT (1U) /*! @name FM - Force Mode */ /*! @{ */ #define CMC_FM_FORCECFG_MASK (0x1U) #define CMC_FM_FORCECFG_SHIFT (0U) /*! FORCECFG - Boot Configuration * 0b0..No effect * 0b1..Asserts */ #define CMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK) /*! @} */ /* The count of CMC_FM */ #define CMC_FM_COUNT (1U) /*! @name SRAMDIS - SRAM Disable */ /*! @{ */ #define CMC_SRAMDIS_DIS0_MASK (0x1U) #define CMC_SRAMDIS_DIS0_SHIFT (0U) /*! DIS0 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS0_SHIFT)) & CMC_SRAMDIS_DIS0_MASK) #define CMC_SRAMDIS_DIS1_MASK (0x2U) #define CMC_SRAMDIS_DIS1_SHIFT (1U) /*! DIS1 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS1_SHIFT)) & CMC_SRAMDIS_DIS1_MASK) #define CMC_SRAMDIS_DIS2_MASK (0x4U) #define CMC_SRAMDIS_DIS2_SHIFT (2U) /*! DIS2 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS2_SHIFT)) & CMC_SRAMDIS_DIS2_MASK) #define CMC_SRAMDIS_DIS3_MASK (0x8U) #define CMC_SRAMDIS_DIS3_SHIFT (3U) /*! DIS3 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS3_SHIFT)) & CMC_SRAMDIS_DIS3_MASK) #define CMC_SRAMDIS_DIS4_MASK (0x10U) #define CMC_SRAMDIS_DIS4_SHIFT (4U) /*! DIS4 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS4_SHIFT)) & CMC_SRAMDIS_DIS4_MASK) #define CMC_SRAMDIS_DIS5_MASK (0x20U) #define CMC_SRAMDIS_DIS5_SHIFT (5U) /*! DIS5 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS5_SHIFT)) & CMC_SRAMDIS_DIS5_MASK) #define CMC_SRAMDIS_DIS6_MASK (0x40U) #define CMC_SRAMDIS_DIS6_SHIFT (6U) /*! DIS6 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS6_SHIFT)) & CMC_SRAMDIS_DIS6_MASK) #define CMC_SRAMDIS_DIS7_MASK (0x80U) #define CMC_SRAMDIS_DIS7_SHIFT (7U) /*! DIS7 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS7_SHIFT)) & CMC_SRAMDIS_DIS7_MASK) #define CMC_SRAMDIS_DIS8_MASK (0x100U) #define CMC_SRAMDIS_DIS8_SHIFT (8U) /*! DIS8 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS8_SHIFT)) & CMC_SRAMDIS_DIS8_MASK) #define CMC_SRAMDIS_DIS9_MASK (0x200U) #define CMC_SRAMDIS_DIS9_SHIFT (9U) /*! DIS9 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS9_SHIFT)) & CMC_SRAMDIS_DIS9_MASK) #define CMC_SRAMDIS_DIS10_MASK (0x400U) #define CMC_SRAMDIS_DIS10_SHIFT (10U) /*! DIS10 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS10_SHIFT)) & CMC_SRAMDIS_DIS10_MASK) #define CMC_SRAMDIS_DIS11_MASK (0x800U) #define CMC_SRAMDIS_DIS11_SHIFT (11U) /*! DIS11 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS11_SHIFT)) & CMC_SRAMDIS_DIS11_MASK) #define CMC_SRAMDIS_DIS12_MASK (0x1000U) #define CMC_SRAMDIS_DIS12_SHIFT (12U) /*! DIS12 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS12_SHIFT)) & CMC_SRAMDIS_DIS12_MASK) #define CMC_SRAMDIS_DIS13_MASK (0x2000U) #define CMC_SRAMDIS_DIS13_SHIFT (13U) /*! DIS13 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS13_SHIFT)) & CMC_SRAMDIS_DIS13_MASK) #define CMC_SRAMDIS_DIS14_MASK (0x4000U) #define CMC_SRAMDIS_DIS14_SHIFT (14U) /*! DIS14 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS14_SHIFT)) & CMC_SRAMDIS_DIS14_MASK) #define CMC_SRAMDIS_DIS15_MASK (0x8000U) #define CMC_SRAMDIS_DIS15_SHIFT (15U) /*! DIS15 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS15_SHIFT)) & CMC_SRAMDIS_DIS15_MASK) #define CMC_SRAMDIS_DIS16_MASK (0x10000U) #define CMC_SRAMDIS_DIS16_SHIFT (16U) /*! DIS16 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS16_SHIFT)) & CMC_SRAMDIS_DIS16_MASK) #define CMC_SRAMDIS_DIS17_MASK (0x20000U) #define CMC_SRAMDIS_DIS17_SHIFT (17U) /*! DIS17 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS17_SHIFT)) & CMC_SRAMDIS_DIS17_MASK) #define CMC_SRAMDIS_DIS18_MASK (0x40000U) #define CMC_SRAMDIS_DIS18_SHIFT (18U) /*! DIS18 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS18_SHIFT)) & CMC_SRAMDIS_DIS18_MASK) #define CMC_SRAMDIS_DIS19_MASK (0x80000U) #define CMC_SRAMDIS_DIS19_SHIFT (19U) /*! DIS19 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS19_SHIFT)) & CMC_SRAMDIS_DIS19_MASK) #define CMC_SRAMDIS_DIS20_MASK (0x100000U) #define CMC_SRAMDIS_DIS20_SHIFT (20U) /*! DIS20 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS20_SHIFT)) & CMC_SRAMDIS_DIS20_MASK) #define CMC_SRAMDIS_DIS21_MASK (0x200000U) #define CMC_SRAMDIS_DIS21_SHIFT (21U) /*! DIS21 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS21_SHIFT)) & CMC_SRAMDIS_DIS21_MASK) #define CMC_SRAMDIS_DIS22_MASK (0x400000U) #define CMC_SRAMDIS_DIS22_SHIFT (22U) /*! DIS22 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS22_SHIFT)) & CMC_SRAMDIS_DIS22_MASK) #define CMC_SRAMDIS_DIS23_MASK (0x800000U) #define CMC_SRAMDIS_DIS23_SHIFT (23U) /*! DIS23 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS23_SHIFT)) & CMC_SRAMDIS_DIS23_MASK) #define CMC_SRAMDIS_DIS24_MASK (0x1000000U) #define CMC_SRAMDIS_DIS24_SHIFT (24U) /*! DIS24 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS24_SHIFT)) & CMC_SRAMDIS_DIS24_MASK) #define CMC_SRAMDIS_DIS25_MASK (0x2000000U) #define CMC_SRAMDIS_DIS25_SHIFT (25U) /*! DIS25 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS25_SHIFT)) & CMC_SRAMDIS_DIS25_MASK) #define CMC_SRAMDIS_DIS26_MASK (0x4000000U) #define CMC_SRAMDIS_DIS26_SHIFT (26U) /*! DIS26 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS26_SHIFT)) & CMC_SRAMDIS_DIS26_MASK) #define CMC_SRAMDIS_DIS27_MASK (0x8000000U) #define CMC_SRAMDIS_DIS27_SHIFT (27U) /*! DIS27 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS27_SHIFT)) & CMC_SRAMDIS_DIS27_MASK) #define CMC_SRAMDIS_DIS28_MASK (0x10000000U) #define CMC_SRAMDIS_DIS28_SHIFT (28U) /*! DIS28 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS28_SHIFT)) & CMC_SRAMDIS_DIS28_MASK) #define CMC_SRAMDIS_DIS29_MASK (0x20000000U) #define CMC_SRAMDIS_DIS29_SHIFT (29U) /*! DIS29 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS29_SHIFT)) & CMC_SRAMDIS_DIS29_MASK) #define CMC_SRAMDIS_DIS30_MASK (0x40000000U) #define CMC_SRAMDIS_DIS30_SHIFT (30U) /*! DIS30 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS30_SHIFT)) & CMC_SRAMDIS_DIS30_MASK) #define CMC_SRAMDIS_DIS31_MASK (0x80000000U) #define CMC_SRAMDIS_DIS31_SHIFT (31U) /*! DIS31 - SRAM Disable * 0b0..Enables * 0b1..Disables */ #define CMC_SRAMDIS_DIS31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS31_SHIFT)) & CMC_SRAMDIS_DIS31_MASK) /*! @} */ /* The count of CMC_SRAMDIS */ #define CMC_SRAMDIS_COUNT (1U) /*! @name SRAMRET - SRAM Retention */ /*! @{ */ #define CMC_SRAMRET_RET0_MASK (0x1U) #define CMC_SRAMRET_RET0_SHIFT (0U) /*! RET0 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET0_SHIFT)) & CMC_SRAMRET_RET0_MASK) #define CMC_SRAMRET_RET1_MASK (0x2U) #define CMC_SRAMRET_RET1_SHIFT (1U) /*! RET1 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET1_SHIFT)) & CMC_SRAMRET_RET1_MASK) #define CMC_SRAMRET_RET2_MASK (0x4U) #define CMC_SRAMRET_RET2_SHIFT (2U) /*! RET2 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET2_SHIFT)) & CMC_SRAMRET_RET2_MASK) #define CMC_SRAMRET_RET3_MASK (0x8U) #define CMC_SRAMRET_RET3_SHIFT (3U) /*! RET3 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET3_SHIFT)) & CMC_SRAMRET_RET3_MASK) #define CMC_SRAMRET_RET4_MASK (0x10U) #define CMC_SRAMRET_RET4_SHIFT (4U) /*! RET4 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET4_SHIFT)) & CMC_SRAMRET_RET4_MASK) #define CMC_SRAMRET_RET5_MASK (0x20U) #define CMC_SRAMRET_RET5_SHIFT (5U) /*! RET5 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET5_SHIFT)) & CMC_SRAMRET_RET5_MASK) #define CMC_SRAMRET_RET6_MASK (0x40U) #define CMC_SRAMRET_RET6_SHIFT (6U) /*! RET6 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET6_SHIFT)) & CMC_SRAMRET_RET6_MASK) #define CMC_SRAMRET_RET7_MASK (0x80U) #define CMC_SRAMRET_RET7_SHIFT (7U) /*! RET7 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET7_SHIFT)) & CMC_SRAMRET_RET7_MASK) #define CMC_SRAMRET_RET8_MASK (0x100U) #define CMC_SRAMRET_RET8_SHIFT (8U) /*! RET8 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET8_SHIFT)) & CMC_SRAMRET_RET8_MASK) #define CMC_SRAMRET_RET9_MASK (0x200U) #define CMC_SRAMRET_RET9_SHIFT (9U) /*! RET9 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET9_SHIFT)) & CMC_SRAMRET_RET9_MASK) #define CMC_SRAMRET_RET10_MASK (0x400U) #define CMC_SRAMRET_RET10_SHIFT (10U) /*! RET10 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET10_SHIFT)) & CMC_SRAMRET_RET10_MASK) #define CMC_SRAMRET_RET11_MASK (0x800U) #define CMC_SRAMRET_RET11_SHIFT (11U) /*! RET11 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET11_SHIFT)) & CMC_SRAMRET_RET11_MASK) #define CMC_SRAMRET_RET12_MASK (0x1000U) #define CMC_SRAMRET_RET12_SHIFT (12U) /*! RET12 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET12_SHIFT)) & CMC_SRAMRET_RET12_MASK) #define CMC_SRAMRET_RET13_MASK (0x2000U) #define CMC_SRAMRET_RET13_SHIFT (13U) /*! RET13 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET13_SHIFT)) & CMC_SRAMRET_RET13_MASK) #define CMC_SRAMRET_RET14_MASK (0x4000U) #define CMC_SRAMRET_RET14_SHIFT (14U) /*! RET14 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET14_SHIFT)) & CMC_SRAMRET_RET14_MASK) #define CMC_SRAMRET_RET15_MASK (0x8000U) #define CMC_SRAMRET_RET15_SHIFT (15U) /*! RET15 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET15_SHIFT)) & CMC_SRAMRET_RET15_MASK) #define CMC_SRAMRET_RET16_MASK (0x10000U) #define CMC_SRAMRET_RET16_SHIFT (16U) /*! RET16 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET16_SHIFT)) & CMC_SRAMRET_RET16_MASK) #define CMC_SRAMRET_RET17_MASK (0x20000U) #define CMC_SRAMRET_RET17_SHIFT (17U) /*! RET17 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET17_SHIFT)) & CMC_SRAMRET_RET17_MASK) #define CMC_SRAMRET_RET18_MASK (0x40000U) #define CMC_SRAMRET_RET18_SHIFT (18U) /*! RET18 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET18_SHIFT)) & CMC_SRAMRET_RET18_MASK) #define CMC_SRAMRET_RET19_MASK (0x80000U) #define CMC_SRAMRET_RET19_SHIFT (19U) /*! RET19 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET19_SHIFT)) & CMC_SRAMRET_RET19_MASK) #define CMC_SRAMRET_RET20_MASK (0x100000U) #define CMC_SRAMRET_RET20_SHIFT (20U) /*! RET20 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET20_SHIFT)) & CMC_SRAMRET_RET20_MASK) #define CMC_SRAMRET_RET21_MASK (0x200000U) #define CMC_SRAMRET_RET21_SHIFT (21U) /*! RET21 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET21_SHIFT)) & CMC_SRAMRET_RET21_MASK) #define CMC_SRAMRET_RET22_MASK (0x400000U) #define CMC_SRAMRET_RET22_SHIFT (22U) /*! RET22 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET22_SHIFT)) & CMC_SRAMRET_RET22_MASK) #define CMC_SRAMRET_RET23_MASK (0x800000U) #define CMC_SRAMRET_RET23_SHIFT (23U) /*! RET23 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET23_SHIFT)) & CMC_SRAMRET_RET23_MASK) #define CMC_SRAMRET_RET24_MASK (0x1000000U) #define CMC_SRAMRET_RET24_SHIFT (24U) /*! RET24 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET24_SHIFT)) & CMC_SRAMRET_RET24_MASK) #define CMC_SRAMRET_RET25_MASK (0x2000000U) #define CMC_SRAMRET_RET25_SHIFT (25U) /*! RET25 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET25_SHIFT)) & CMC_SRAMRET_RET25_MASK) #define CMC_SRAMRET_RET26_MASK (0x4000000U) #define CMC_SRAMRET_RET26_SHIFT (26U) /*! RET26 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET26_SHIFT)) & CMC_SRAMRET_RET26_MASK) #define CMC_SRAMRET_RET27_MASK (0x8000000U) #define CMC_SRAMRET_RET27_SHIFT (27U) /*! RET27 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET27_SHIFT)) & CMC_SRAMRET_RET27_MASK) #define CMC_SRAMRET_RET28_MASK (0x10000000U) #define CMC_SRAMRET_RET28_SHIFT (28U) /*! RET28 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET28_SHIFT)) & CMC_SRAMRET_RET28_MASK) #define CMC_SRAMRET_RET29_MASK (0x20000000U) #define CMC_SRAMRET_RET29_SHIFT (29U) /*! RET29 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET29_SHIFT)) & CMC_SRAMRET_RET29_MASK) #define CMC_SRAMRET_RET30_MASK (0x40000000U) #define CMC_SRAMRET_RET30_SHIFT (30U) /*! RET30 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET30_SHIFT)) & CMC_SRAMRET_RET30_MASK) #define CMC_SRAMRET_RET31_MASK (0x80000000U) #define CMC_SRAMRET_RET31_SHIFT (31U) /*! RET31 - SRAM Retention * 0b0..Retains * 0b1..Powers off */ #define CMC_SRAMRET_RET31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET31_SHIFT)) & CMC_SRAMRET_RET31_MASK) /*! @} */ /* The count of CMC_SRAMRET */ #define CMC_SRAMRET_COUNT (1U) /*! @name FLASHCR - Flash Control */ /*! @{ */ #define CMC_FLASHCR_FLASHDIS_MASK (0x1U) #define CMC_FLASHCR_FLASHDIS_SHIFT (0U) /*! FLASHDIS - Flash Disable * 0b0..No effect * 0b1..Flash memory is disabled */ #define CMC_FLASHCR_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK) #define CMC_FLASHCR_FLASHDOZE_MASK (0x2U) #define CMC_FLASHCR_FLASHDOZE_SHIFT (1U) /*! FLASHDOZE - Flash Doze * 0b0..No effect * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) */ #define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) /*! @} */ /*! @name BSR - BootROM Status Register */ /*! @{ */ #define CMC_BSR_STAT_MASK (0xFFFFFFFFU) #define CMC_BSR_STAT_SHIFT (0U) /*! STAT - Provides status information written by the BootROM. */ #define CMC_BSR_STAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_BSR_STAT_SHIFT)) & CMC_BSR_STAT_MASK) /*! @} */ /*! @name BLR - BootROM Lock Register */ /*! @{ */ #define CMC_BLR_LOCK_MASK (0x7U) #define CMC_BLR_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b010..BootROM Status and Lock Registers can be written * 0b101..BootROM Status and Lock Registers cannot be written */ #define CMC_BLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_BLR_LOCK_SHIFT)) & CMC_BLR_LOCK_MASK) /*! @} */ /*! @name CORECTL - Core Control */ /*! @{ */ #define CMC_CORECTL_NPIE_MASK (0x1U) #define CMC_CORECTL_NPIE_SHIFT (0U) /*! NPIE - Non-maskable Pin Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define CMC_CORECTL_NPIE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK) /*! @} */ /*! @name DBGCTL - Debug Control */ /*! @{ */ #define CMC_DBGCTL_SOD_MASK (0x1U) #define CMC_DBGCTL_SOD_SHIFT (0U) /*! SOD - Sleep Or Debug * 0b0..Remains enabled * 0b1..Disabled */ #define CMC_DBGCTL_SOD(x) (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK) /*! @} */ /*! * @} */ /* end of group CMC_Register_Masks */ /* CMC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CMC0 base address */ #define CMC0_BASE (0x50048000u) /** Peripheral CMC0 base address */ #define CMC0_BASE_NS (0x40048000u) /** Peripheral CMC0 base pointer */ #define CMC0 ((CMC_Type *)CMC0_BASE) /** Peripheral CMC0 base pointer */ #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) /** Array initializer of CMC peripheral base addresses */ #define CMC_BASE_ADDRS { CMC0_BASE } /** Array initializer of CMC peripheral base pointers */ #define CMC_BASE_PTRS { CMC0 } /** Array initializer of CMC peripheral base addresses */ #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } /** Array initializer of CMC peripheral base pointers */ #define CMC_BASE_PTRS_NS { CMC0_NS } #else /** Peripheral CMC0 base address */ #define CMC0_BASE (0x40048000u) /** Peripheral CMC0 base pointer */ #define CMC0 ((CMC_Type *)CMC0_BASE) /** Array initializer of CMC peripheral base addresses */ #define CMC_BASE_ADDRS { CMC0_BASE } /** Array initializer of CMC peripheral base pointers */ #define CMC_BASE_PTRS { CMC0 } #endif /* Backward compatibility for CMC */ #define CMC_SRAMDIS_DIS_MASK (0xFFFFFFFFU) #define CMC_SRAMDIS_DIS_SHIFT (0U) /*! DIS - SRAM Disable */ #define CMC_SRAMDIS_DIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK) #define CMC_SRAMRET_RET_MASK (0xFFFFFFFFU) #define CMC_SRAMRET_RET_SHIFT (0U) /*! RET - SRAM Retention */ #define CMC_SRAMRET_RET(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK) /*! * @} */ /* end of group CMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer * @{ */ /** CRC - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ struct { /* offset: 0x0 */ __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ } ACCESS8BIT; struct { /* offset: 0x0 */ __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ } ACCESS16BIT; __IO uint32_t DATA; /**< Data, offset: 0x0 */ }; union { /* offset: 0x4 */ struct { /* offset: 0x4 */ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ } GPOLY_ACCESS8BIT; struct { /* offset: 0x4 */ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ } GPOLY_ACCESS16BIT; __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ }; union { /* offset: 0x8 */ struct { /* offset: 0x8 */ uint8_t RESERVED_0[3]; __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ } CTRL_ACCESS8BIT; __IO uint32_t CTRL; /**< Control, offset: 0x8 */ }; } CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Register_Masks CRC Register Masks * @{ */ /*! @name DATALL - CRC_DATALL register */ /*! @{ */ #define CRC_DATALL_DATALL_MASK (0xFFU) #define CRC_DATALL_DATALL_SHIFT (0U) #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) /*! @} */ /*! @name DATALU - CRC_DATALU register */ /*! @{ */ #define CRC_DATALU_DATALU_MASK (0xFFU) #define CRC_DATALU_DATALU_SHIFT (0U) #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) /*! @} */ /*! @name DATAHL - CRC_DATAHL register */ /*! @{ */ #define CRC_DATAHL_DATAHL_MASK (0xFFU) #define CRC_DATAHL_DATAHL_SHIFT (0U) #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) /*! @} */ /*! @name DATAHU - CRC_DATAHU register */ /*! @{ */ #define CRC_DATAHU_DATAHU_MASK (0xFFU) #define CRC_DATAHU_DATAHU_SHIFT (0U) #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) /*! @} */ /*! @name DATAL - CRC_DATAL register */ /*! @{ */ #define CRC_DATAL_DATAL_MASK (0xFFFFU) #define CRC_DATAL_DATAL_SHIFT (0U) #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) /*! @} */ /*! @name DATAH - CRC_DATAH register */ /*! @{ */ #define CRC_DATAH_DATAH_MASK (0xFFFFU) #define CRC_DATAH_DATAH_SHIFT (0U) #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) /*! @} */ /*! @name DATA - Data */ /*! @{ */ #define CRC_DATA_LL_MASK (0xFFU) #define CRC_DATA_LL_SHIFT (0U) /*! LL - Lower Part of Low Byte */ #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) #define CRC_DATA_LU_MASK (0xFF00U) #define CRC_DATA_LU_SHIFT (8U) /*! LU - Upper Part of Low Byte */ #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) #define CRC_DATA_HL_MASK (0xFF0000U) #define CRC_DATA_HL_SHIFT (16U) /*! HL - Lower Part of High Byte */ #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) #define CRC_DATA_HU_MASK (0xFF000000U) #define CRC_DATA_HU_SHIFT (24U) /*! HU - Upper Part of High Byte */ #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) /*! @} */ /*! @name GPOLYLL - CRC_GPOLYLL register */ /*! @{ */ #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) /*! @} */ /*! @name GPOLYLU - CRC_GPOLYLU register */ /*! @{ */ #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) /*! @} */ /*! @name GPOLYHL - CRC_GPOLYHL register */ /*! @{ */ #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) /*! @} */ /*! @name GPOLYHU - CRC_GPOLYHU register */ /*! @{ */ #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) /*! @} */ /*! @name GPOLYL - CRC_GPOLYL register */ /*! @{ */ #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) #define CRC_GPOLYL_GPOLYL_SHIFT (0U) #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) /*! @} */ /*! @name GPOLYH - CRC_GPOLYH register */ /*! @{ */ #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) #define CRC_GPOLYH_GPOLYH_SHIFT (0U) #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) /*! @} */ /*! @name GPOLY - Polynomial */ /*! @{ */ #define CRC_GPOLY_LOW_MASK (0xFFFFU) #define CRC_GPOLY_LOW_SHIFT (0U) /*! LOW - Low Half-Word */ #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) #define CRC_GPOLY_HIGH_SHIFT (16U) /*! HIGH - High Half-Word */ #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) /*! @} */ /*! @name CTRLHU - CRC_CTRLHU register */ /*! @{ */ #define CRC_CTRLHU_TCRC_MASK (0x1U) #define CRC_CTRLHU_TCRC_SHIFT (0U) /*! TCRC - TCRC * 0b0..16 bits * 0b1..32 bits */ #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) #define CRC_CTRLHU_WAS_MASK (0x2U) #define CRC_CTRLHU_WAS_SHIFT (1U) /*! WAS - Write as Seed * 0b0..Data values * 0b1..Seed values */ #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) #define CRC_CTRLHU_FXOR_MASK (0x4U) #define CRC_CTRLHU_FXOR_SHIFT (2U) /*! FXOR - Complement Read of CRC Data Register * 0b0..Disables XOR on reading data. * 0b1..Inverts or complements the read value of the CRC Data. */ #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) #define CRC_CTRLHU_TOTR_MASK (0x30U) #define CRC_CTRLHU_TOTR_SHIFT (4U) /*! TOTR - Transpose Type for Read * 0b00..No transposition * 0b01..Bits in bytes are transposed, but bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) #define CRC_CTRLHU_TOT_MASK (0xC0U) #define CRC_CTRLHU_TOT_SHIFT (6U) /*! TOT - Transpose Type for Write * 0b00..No transposition * 0b01..Bits in bytes are transposed, but bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) /*! @} */ /*! @name CTRL - Control */ /*! @{ */ #define CRC_CTRL_TCRC_MASK (0x1000000U) #define CRC_CTRL_TCRC_SHIFT (24U) /*! TCRC - TCRC * 0b0..16 bits * 0b1..32 bits */ #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) #define CRC_CTRL_WAS_MASK (0x2000000U) #define CRC_CTRL_WAS_SHIFT (25U) /*! WAS - Write as Seed * 0b0..Data values * 0b1..Seed values */ #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) #define CRC_CTRL_FXOR_MASK (0x4000000U) #define CRC_CTRL_FXOR_SHIFT (26U) /*! FXOR - Complement Read of CRC Data Register * 0b0..Disables XOR on reading data. * 0b1..Inverts or complements the read value of the CRC Data. */ #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) #define CRC_CTRL_TOTR_MASK (0x30000000U) #define CRC_CTRL_TOTR_SHIFT (28U) /*! TOTR - Transpose Type for Read * 0b00..No transposition * 0b01..Bits in bytes are transposed, but bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) #define CRC_CTRL_TOT_MASK (0xC0000000U) #define CRC_CTRL_TOT_SHIFT (30U) /*! TOT - Transpose Type for Write * 0b00..No transposition * 0b01..Bits in bytes are transposed, but bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) /*! @} */ /*! * @} */ /* end of group CRC_Register_Masks */ /* CRC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CRC0 base address */ #define CRC0_BASE (0x500CB000u) /** Peripheral CRC0 base address */ #define CRC0_BASE_NS (0x400CB000u) /** Peripheral CRC0 base pointer */ #define CRC0 ((CRC_Type *)CRC0_BASE) /** Peripheral CRC0 base pointer */ #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) /** Array initializer of CRC peripheral base addresses */ #define CRC_BASE_ADDRS { CRC0_BASE } /** Array initializer of CRC peripheral base pointers */ #define CRC_BASE_PTRS { CRC0 } /** Array initializer of CRC peripheral base addresses */ #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } /** Array initializer of CRC peripheral base pointers */ #define CRC_BASE_PTRS_NS { CRC0_NS } #else /** Peripheral CRC0 base address */ #define CRC0_BASE (0x400CB000u) /** Peripheral CRC0 base pointer */ #define CRC0 ((CRC_Type *)CRC0_BASE) /** Array initializer of CRC peripheral base addresses */ #define CRC_BASE_ADDRS { CRC0_BASE } /** Array initializer of CRC peripheral base pointers */ #define CRC_BASE_PTRS { CRC0 } #endif /*! * @} */ /* end of group CRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CTIMER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer * @{ */ /** CTIMER - Register Layout Typedef */ typedef struct { __IO uint32_t IR; /**< Interrupt, offset: 0x0 */ __IO uint32_t TCR; /**< Timer Control, offset: 0x4 */ __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ __IO uint32_t PR; /**< Prescale, offset: 0xC */ __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ __IO uint32_t MCR; /**< Match Control, offset: 0x14 */ __IO uint32_t MR[4]; /**< Match, array offset: 0x18, array step: 0x4 */ __IO uint32_t CCR; /**< Capture Control, offset: 0x28 */ __I uint32_t CR[4]; /**< Capture, array offset: 0x2C, array step: 0x4 */ __IO uint32_t EMR; /**< External Match, offset: 0x3C */ uint8_t RESERVED_0[48]; __IO uint32_t CTCR; /**< Count Control, offset: 0x70 */ __IO uint32_t PWMC; /**< PWM Control, offset: 0x74 */ __IO uint32_t MSR[4]; /**< Match Shadow, array offset: 0x78, array step: 0x4 */ } CTIMER_Type; /* ---------------------------------------------------------------------------- -- CTIMER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CTIMER_Register_Masks CTIMER Register Masks * @{ */ /*! @name IR - Interrupt */ /*! @{ */ #define CTIMER_IR_MR0INT_MASK (0x1U) #define CTIMER_IR_MR0INT_SHIFT (0U) /*! MR0INT - Interrupt Flag for Match Channel 0 Event */ #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) #define CTIMER_IR_MR1INT_MASK (0x2U) #define CTIMER_IR_MR1INT_SHIFT (1U) /*! MR1INT - Interrupt Flag for Match Channel 1 Event */ #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) #define CTIMER_IR_MR2INT_MASK (0x4U) #define CTIMER_IR_MR2INT_SHIFT (2U) /*! MR2INT - Interrupt Flag for Match Channel 2 Event */ #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) #define CTIMER_IR_MR3INT_MASK (0x8U) #define CTIMER_IR_MR3INT_SHIFT (3U) /*! MR3INT - Interrupt Flag for Match Channel 3 Event */ #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) #define CTIMER_IR_CR0INT_MASK (0x10U) #define CTIMER_IR_CR0INT_SHIFT (4U) /*! CR0INT - Interrupt Flag for Capture Channel 0 Event */ #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) #define CTIMER_IR_CR1INT_MASK (0x20U) #define CTIMER_IR_CR1INT_SHIFT (5U) /*! CR1INT - Interrupt Flag for Capture Channel 1 Event */ #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) #define CTIMER_IR_CR2INT_MASK (0x40U) #define CTIMER_IR_CR2INT_SHIFT (6U) /*! CR2INT - Interrupt Flag for Capture Channel 2 Event */ #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) #define CTIMER_IR_CR3INT_MASK (0x80U) #define CTIMER_IR_CR3INT_SHIFT (7U) /*! CR3INT - Interrupt Flag for Capture Channel 3 Event */ #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) /*! @} */ /*! @name TCR - Timer Control */ /*! @{ */ #define CTIMER_TCR_CEN_MASK (0x1U) #define CTIMER_TCR_CEN_SHIFT (0U) /*! CEN - Counter Enable * 0b0..Disable * 0b1..Enable */ #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) #define CTIMER_TCR_CRST_MASK (0x2U) #define CTIMER_TCR_CRST_SHIFT (1U) /*! CRST - Counter Reset Enable * 0b0..Disable * 0b1..Enable */ #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) #define CTIMER_TCR_AGCEN_MASK (0x10U) #define CTIMER_TCR_AGCEN_SHIFT (4U) /*! AGCEN - Allow Global Count Enable * 0b0..Disable * 0b1..Enable */ #define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) #define CTIMER_TCR_ATCEN_MASK (0x20U) #define CTIMER_TCR_ATCEN_SHIFT (5U) /*! ATCEN - Allow Trigger Count Enable * 0b0..Disable * 0b1..Enable */ #define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) /*! @} */ /*! @name TC - Timer Counter */ /*! @{ */ #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) #define CTIMER_TC_TCVAL_SHIFT (0U) /*! TCVAL - Timer Counter Value */ #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) /*! @} */ /*! @name PR - Prescale */ /*! @{ */ #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) #define CTIMER_PR_PRVAL_SHIFT (0U) /*! PRVAL - Prescale Reload Value */ #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) /*! @} */ /*! @name PC - Prescale Counter */ /*! @{ */ #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) #define CTIMER_PC_PCVAL_SHIFT (0U) /*! PCVAL - Prescale Counter Value */ #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) /*! @} */ /*! @name MCR - Match Control */ /*! @{ */ #define CTIMER_MCR_MR0I_MASK (0x1U) #define CTIMER_MCR_MR0I_SHIFT (0U) /*! MR0I - Interrupt on MR0 * 0b0..Does not generate * 0b1..Generates */ #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) #define CTIMER_MCR_MR0R_MASK (0x2U) #define CTIMER_MCR_MR0R_SHIFT (1U) /*! MR0R - Reset on MR0 * 0b0..Does not reset * 0b1..Resets */ #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) #define CTIMER_MCR_MR0S_MASK (0x4U) #define CTIMER_MCR_MR0S_SHIFT (2U) /*! MR0S - Stop on MR0 * 0b0..Does not stop * 0b1..Stops */ #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) #define CTIMER_MCR_MR1I_MASK (0x8U) #define CTIMER_MCR_MR1I_SHIFT (3U) /*! MR1I - Interrupt on MR1 * 0b0..Does not generate * 0b1..Generates */ #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) #define CTIMER_MCR_MR1R_MASK (0x10U) #define CTIMER_MCR_MR1R_SHIFT (4U) /*! MR1R - Reset on MR1 * 0b0..Does not reset * 0b1..Resets */ #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) #define CTIMER_MCR_MR1S_MASK (0x20U) #define CTIMER_MCR_MR1S_SHIFT (5U) /*! MR1S - Stop on MR1 * 0b0..Does not stop * 0b1..Stops */ #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) #define CTIMER_MCR_MR2I_MASK (0x40U) #define CTIMER_MCR_MR2I_SHIFT (6U) /*! MR2I - Interrupt on MR2 * 0b0..Does not generate * 0b1..Generates */ #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) #define CTIMER_MCR_MR2R_MASK (0x80U) #define CTIMER_MCR_MR2R_SHIFT (7U) /*! MR2R - Reset on MR2 * 0b0..Does not reset * 0b1..Resets */ #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) #define CTIMER_MCR_MR2S_MASK (0x100U) #define CTIMER_MCR_MR2S_SHIFT (8U) /*! MR2S - Stop on MR2 * 0b0..Does not stop * 0b1..Stops */ #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) #define CTIMER_MCR_MR3I_MASK (0x200U) #define CTIMER_MCR_MR3I_SHIFT (9U) /*! MR3I - Interrupt on MR3 * 0b0..Does not generate * 0b1..Generates */ #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) #define CTIMER_MCR_MR3R_MASK (0x400U) #define CTIMER_MCR_MR3R_SHIFT (10U) /*! MR3R - Reset on MR3 * 0b0..Does not reset * 0b1..Resets */ #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) #define CTIMER_MCR_MR3S_MASK (0x800U) #define CTIMER_MCR_MR3S_SHIFT (11U) /*! MR3S - Stop on MR3 * 0b0..Does not stop * 0b1..Stops */ #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) #define CTIMER_MCR_MR0RL_MASK (0x1000000U) #define CTIMER_MCR_MR0RL_SHIFT (24U) /*! MR0RL - Reload MR * 0b0..Does not reload * 0b1..Reloads */ #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) #define CTIMER_MCR_MR1RL_MASK (0x2000000U) #define CTIMER_MCR_MR1RL_SHIFT (25U) /*! MR1RL - Reload MR * 0b0..Does not reload * 0b1..Reloads */ #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) #define CTIMER_MCR_MR2RL_MASK (0x4000000U) #define CTIMER_MCR_MR2RL_SHIFT (26U) /*! MR2RL - Reload MR * 0b0..Does not reload * 0b1..Reloads */ #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) #define CTIMER_MCR_MR3RL_MASK (0x8000000U) #define CTIMER_MCR_MR3RL_SHIFT (27U) /*! MR3RL - Reload MR * 0b0..Does not reload * 0b1..Reloads */ #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) /*! @} */ /*! @name MR - Match */ /*! @{ */ #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) #define CTIMER_MR_MATCH_SHIFT (0U) /*! MATCH - Timer Counter Match Value */ #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) /*! @} */ /* The count of CTIMER_MR */ #define CTIMER_MR_COUNT (4U) /*! @name CCR - Capture Control */ /*! @{ */ #define CTIMER_CCR_CAP0RE_MASK (0x1U) #define CTIMER_CCR_CAP0RE_SHIFT (0U) /*! CAP0RE - Rising Edge of Capture Channel 0 * 0b0..Does not load * 0b1..Loads */ #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) #define CTIMER_CCR_CAP0FE_MASK (0x2U) #define CTIMER_CCR_CAP0FE_SHIFT (1U) /*! CAP0FE - Falling Edge of Capture Channel 0 * 0b0..Does not load * 0b1..Loads */ #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) #define CTIMER_CCR_CAP0I_MASK (0x4U) #define CTIMER_CCR_CAP0I_SHIFT (2U) /*! CAP0I - Generate Interrupt on Channel 0 Capture Event * 0b0..Does not generate * 0b1..Generates */ #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) #define CTIMER_CCR_CAP1RE_MASK (0x8U) #define CTIMER_CCR_CAP1RE_SHIFT (3U) /*! CAP1RE - Rising Edge of Capture Channel 1 * 0b0..Does not load * 0b1..Loads */ #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) #define CTIMER_CCR_CAP1FE_MASK (0x10U) #define CTIMER_CCR_CAP1FE_SHIFT (4U) /*! CAP1FE - Falling Edge of Capture Channel 1 * 0b0..Does not load * 0b1..Loads */ #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) #define CTIMER_CCR_CAP1I_MASK (0x20U) #define CTIMER_CCR_CAP1I_SHIFT (5U) /*! CAP1I - Generate Interrupt on Channel 1 Capture Event * 0b0..Does not generates * 0b1..Generates */ #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) #define CTIMER_CCR_CAP2RE_MASK (0x40U) #define CTIMER_CCR_CAP2RE_SHIFT (6U) /*! CAP2RE - Rising Edge of Capture Channel 2 * 0b0..Does not load * 0b1..Loads */ #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) #define CTIMER_CCR_CAP2FE_MASK (0x80U) #define CTIMER_CCR_CAP2FE_SHIFT (7U) /*! CAP2FE - Falling Edge of Capture Channel 2 * 0b0..Does not load * 0b1..Loads */ #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) #define CTIMER_CCR_CAP2I_MASK (0x100U) #define CTIMER_CCR_CAP2I_SHIFT (8U) /*! CAP2I - Generate Interrupt on Channel 2 Capture Event * 0b0..Does not generate * 0b1..Generates */ #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) #define CTIMER_CCR_CAP3RE_MASK (0x200U) #define CTIMER_CCR_CAP3RE_SHIFT (9U) /*! CAP3RE - Rising Edge of Capture Channel 3 * 0b0..Does not load * 0b1..Loads */ #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) #define CTIMER_CCR_CAP3FE_MASK (0x400U) #define CTIMER_CCR_CAP3FE_SHIFT (10U) /*! CAP3FE - Falling Edge of Capture Channel 3 * 0b0..Does not load * 0b1..Loads */ #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) #define CTIMER_CCR_CAP3I_MASK (0x800U) #define CTIMER_CCR_CAP3I_SHIFT (11U) /*! CAP3I - Generate Interrupt on Channel 3 Capture Event * 0b0..Does not generate * 0b1..Generates */ #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) /*! @} */ /*! @name CR - Capture */ /*! @{ */ #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) #define CTIMER_CR_CAP_SHIFT (0U) /*! CAP - Timer Counter Capture Value */ #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) /*! @} */ /* The count of CTIMER_CR */ #define CTIMER_CR_COUNT (4U) /*! @name EMR - External Match */ /*! @{ */ #define CTIMER_EMR_EM0_MASK (0x1U) #define CTIMER_EMR_EM0_SHIFT (0U) /*! EM0 - External Match 0 * 0b0..Low * 0b1..High */ #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) #define CTIMER_EMR_EM1_MASK (0x2U) #define CTIMER_EMR_EM1_SHIFT (1U) /*! EM1 - External Match 1 * 0b0..Low * 0b1..High */ #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) #define CTIMER_EMR_EM2_MASK (0x4U) #define CTIMER_EMR_EM2_SHIFT (2U) /*! EM2 - External Match 2 * 0b0..Low * 0b1..High */ #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) #define CTIMER_EMR_EM3_MASK (0x8U) #define CTIMER_EMR_EM3_SHIFT (3U) /*! EM3 - External Match 3 * 0b0..Low * 0b1..High */ #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) #define CTIMER_EMR_EMC0_MASK (0x30U) #define CTIMER_EMR_EMC0_SHIFT (4U) /*! EMC0 - External Match Control 0 * 0b00..Does nothing * 0b01..Goes low * 0b10..Goes high * 0b11..Toggles */ #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) #define CTIMER_EMR_EMC1_MASK (0xC0U) #define CTIMER_EMR_EMC1_SHIFT (6U) /*! EMC1 - External Match Control 1 * 0b00..Does nothing * 0b01..Goes low * 0b10..Goes high * 0b11..Toggles */ #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) #define CTIMER_EMR_EMC2_MASK (0x300U) #define CTIMER_EMR_EMC2_SHIFT (8U) /*! EMC2 - External Match Control 2 * 0b00..Does nothing * 0b01..Goes low * 0b10..Goes high * 0b11..Toggles */ #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) #define CTIMER_EMR_EMC3_MASK (0xC00U) #define CTIMER_EMR_EMC3_SHIFT (10U) /*! EMC3 - External Match Control 3 * 0b00..Does nothing * 0b01..Goes low * 0b10..Goes high * 0b11..Toggles */ #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) /*! @} */ /*! @name CTCR - Count Control */ /*! @{ */ #define CTIMER_CTCR_CTMODE_MASK (0x3U) #define CTIMER_CTCR_CTMODE_SHIFT (0U) /*! CTMODE - Counter Timer Mode * 0b00..Timer mode * 0b01..Counter mode rising edge * 0b10..Counter mode falling edge * 0b11..Counter mode dual edge */ #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) #define CTIMER_CTCR_CINSEL_MASK (0xCU) #define CTIMER_CTCR_CINSEL_SHIFT (2U) /*! CINSEL - Count Input Select * 0b00..Channel 0, CAPn[0] for CTIMERn * 0b01..Channel 1, CAPn[1] for CTIMERn * 0b10..Channel 2, CAPn[2] for CTIMERn * 0b11..Channel 3, CAPn[3] for CTIMERn */ #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) #define CTIMER_CTCR_ENCC_MASK (0x10U) #define CTIMER_CTCR_ENCC_SHIFT (4U) /*! ENCC - Capture Channel Enable */ #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) #define CTIMER_CTCR_SELCC_MASK (0xE0U) #define CTIMER_CTCR_SELCC_SHIFT (5U) /*! SELCC - Edge Select * 0b000..Capture channel 0 rising edge * 0b001..Capture channel 0 falling edge * 0b010..Capture channel 1 rising edge * 0b011..Capture channel 1 falling edge * 0b100..Capture channel 2 rising edge * 0b101..Capture channel 2 falling edge */ #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) /*! @} */ /*! @name PWMC - PWM Control */ /*! @{ */ #define CTIMER_PWMC_PWMEN0_MASK (0x1U) #define CTIMER_PWMC_PWMEN0_SHIFT (0U) /*! PWMEN0 - PWM Mode Enable for Channel 0 * 0b0..Disable * 0b1..Enable */ #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) #define CTIMER_PWMC_PWMEN1_MASK (0x2U) #define CTIMER_PWMC_PWMEN1_SHIFT (1U) /*! PWMEN1 - PWM Mode Enable for Channel 1 * 0b0..Disable * 0b1..Enable */ #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) #define CTIMER_PWMC_PWMEN2_MASK (0x4U) #define CTIMER_PWMC_PWMEN2_SHIFT (2U) /*! PWMEN2 - PWM Mode Enable for Channel 2 * 0b0..Disable * 0b1..Enable */ #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) #define CTIMER_PWMC_PWMEN3_MASK (0x8U) #define CTIMER_PWMC_PWMEN3_SHIFT (3U) /*! PWMEN3 - PWM Mode Enable for Channel 3 * 0b0..Disable * 0b1..Enable */ #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) /*! @} */ /*! @name MSR - Match Shadow */ /*! @{ */ #define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) #define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) /*! MATCH_SHADOW - Timer Counter Match Shadow Value */ #define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) /*! @} */ /* The count of CTIMER_MSR */ #define CTIMER_MSR_COUNT (4U) /*! * @} */ /* end of group CTIMER_Register_Masks */ /* CTIMER - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CTIMER0 base address */ #define CTIMER0_BASE (0x5000C000u) /** Peripheral CTIMER0 base address */ #define CTIMER0_BASE_NS (0x4000C000u) /** Peripheral CTIMER0 base pointer */ #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) /** Peripheral CTIMER0 base pointer */ #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) /** Peripheral CTIMER1 base address */ #define CTIMER1_BASE (0x5000D000u) /** Peripheral CTIMER1 base address */ #define CTIMER1_BASE_NS (0x4000D000u) /** Peripheral CTIMER1 base pointer */ #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) /** Peripheral CTIMER1 base pointer */ #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) /** Peripheral CTIMER2 base address */ #define CTIMER2_BASE (0x5000E000u) /** Peripheral CTIMER2 base address */ #define CTIMER2_BASE_NS (0x4000E000u) /** Peripheral CTIMER2 base pointer */ #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) /** Peripheral CTIMER2 base pointer */ #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) /** Peripheral CTIMER3 base address */ #define CTIMER3_BASE (0x5000F000u) /** Peripheral CTIMER3 base address */ #define CTIMER3_BASE_NS (0x4000F000u) /** Peripheral CTIMER3 base pointer */ #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) /** Peripheral CTIMER3 base pointer */ #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) /** Peripheral CTIMER4 base address */ #define CTIMER4_BASE (0x50010000u) /** Peripheral CTIMER4 base address */ #define CTIMER4_BASE_NS (0x40010000u) /** Peripheral CTIMER4 base pointer */ #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) /** Peripheral CTIMER4 base pointer */ #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) /** Array initializer of CTIMER peripheral base addresses */ #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } /** Array initializer of CTIMER peripheral base pointers */ #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } /** Array initializer of CTIMER peripheral base addresses */ #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } /** Array initializer of CTIMER peripheral base pointers */ #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } #else /** Peripheral CTIMER0 base address */ #define CTIMER0_BASE (0x4000C000u) /** Peripheral CTIMER0 base pointer */ #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) /** Peripheral CTIMER1 base address */ #define CTIMER1_BASE (0x4000D000u) /** Peripheral CTIMER1 base pointer */ #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) /** Peripheral CTIMER2 base address */ #define CTIMER2_BASE (0x4000E000u) /** Peripheral CTIMER2 base pointer */ #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) /** Peripheral CTIMER3 base address */ #define CTIMER3_BASE (0x4000F000u) /** Peripheral CTIMER3 base pointer */ #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) /** Peripheral CTIMER4 base address */ #define CTIMER4_BASE (0x40010000u) /** Peripheral CTIMER4 base pointer */ #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) /** Array initializer of CTIMER peripheral base addresses */ #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } /** Array initializer of CTIMER peripheral base pointers */ #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } #endif /** Interrupt vectors for the CTIMER peripheral type */ #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } /*! * @} */ /* end of group CTIMER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DIGTMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DIGTMP_Peripheral_Access_Layer DIGTMP Peripheral Access Layer * @{ */ /** DIGTMP - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[16]; __IO uint32_t CR; /**< Control, offset: 0x10 */ __IO uint32_t SR; /**< Status, offset: 0x14 */ __IO uint32_t LR; /**< Lock, offset: 0x18 */ __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ __IO uint32_t TSR; /**< Tamper Seconds, offset: 0x20 */ __IO uint32_t TER; /**< Tamper Enable, offset: 0x24 */ __IO uint32_t PDR; /**< Pin Direction, offset: 0x28 */ __IO uint32_t PPR; /**< Pin Polarity, offset: 0x2C */ __IO uint32_t ATR[2]; /**< Active Tamper, array offset: 0x30, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PGFR[8]; /**< Pin Glitch Filter, array offset: 0x40, array step: 0x4 */ } DIGTMP_Type; /* ---------------------------------------------------------------------------- -- DIGTMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DIGTMP_Register_Masks DIGTMP Register Masks * @{ */ /*! @name CR - Control */ /*! @{ */ #define DIGTMP_CR_SWR_MASK (0x1U) #define DIGTMP_CR_SWR_SHIFT (0U) /*! SWR - Software Reset * 0b0..No effect * 0b1..Perform a software reset */ #define DIGTMP_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_SWR_SHIFT)) & DIGTMP_CR_SWR_MASK) #define DIGTMP_CR_DEN_MASK (0x2U) #define DIGTMP_CR_DEN_SHIFT (1U) /*! DEN - Digital Tamper Enable * 0b0..Disables TDET clock and prescaler * 0b1..Enables TDET clock and prescaler */ #define DIGTMP_CR_DEN(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DEN_SHIFT)) & DIGTMP_CR_DEN_MASK) #define DIGTMP_CR_TFSR_MASK (0x4U) #define DIGTMP_CR_TFSR_SHIFT (2U) /*! TFSR - Tamper Force System Reset * 0b0..Do not force chip reset * 0b1..Force chip reset */ #define DIGTMP_CR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_TFSR_SHIFT)) & DIGTMP_CR_TFSR_MASK) #define DIGTMP_CR_UM_MASK (0x8U) #define DIGTMP_CR_UM_SHIFT (3U) /*! UM - Update Mode * 0b0..No effect * 0b1..Allows the clearing of interrupts */ #define DIGTMP_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_UM_SHIFT)) & DIGTMP_CR_UM_MASK) #define DIGTMP_CR_ATCS0_MASK (0x10U) #define DIGTMP_CR_ATCS0_SHIFT (4U) /*! ATCS0 - Active Tamper Clock Source * 0b0..1 Hz prescaler clock * 0b1..64 Hz prescaler clock */ #define DIGTMP_CR_ATCS0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS0_SHIFT)) & DIGTMP_CR_ATCS0_MASK) #define DIGTMP_CR_ATCS1_MASK (0x20U) #define DIGTMP_CR_ATCS1_SHIFT (5U) /*! ATCS1 - Active Tamper Clock Source * 0b0..1 Hz prescaler clock * 0b1..64 Hz prescaler clock */ #define DIGTMP_CR_ATCS1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS1_SHIFT)) & DIGTMP_CR_ATCS1_MASK) #define DIGTMP_CR_DISTAM_MASK (0x100U) #define DIGTMP_CR_DISTAM_SHIFT (8U) /*! DISTAM - Disable Prescaler On Tamper * 0b0..No effect * 0b1..Automatically disables the prescaler after tamper detection */ #define DIGTMP_CR_DISTAM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DISTAM_SHIFT)) & DIGTMP_CR_DISTAM_MASK) #define DIGTMP_CR_DPR_MASK (0xFFFE0000U) #define DIGTMP_CR_DPR_SHIFT (17U) /*! DPR - Digital Tamper Prescaler */ #define DIGTMP_CR_DPR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DPR_SHIFT)) & DIGTMP_CR_DPR_MASK) /*! @} */ /*! @name SR - Status */ /*! @{ */ #define DIGTMP_SR_DTF_MASK (0x1U) #define DIGTMP_SR_DTF_SHIFT (0U) /*! DTF - Digital Tamper Flag * 0b0..TDET tampering not detected * 0b1..TDET tampering detected */ #define DIGTMP_SR_DTF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_DTF_SHIFT)) & DIGTMP_SR_DTF_MASK) #define DIGTMP_SR_TAF_MASK (0x2U) #define DIGTMP_SR_TAF_SHIFT (1U) /*! TAF - Tamper Acknowledge Flag * 0b0..Digital Tamper Flag (SR[DTF]) is clear or chip reset has not occurred after Digital Tamper Flag (SR[DTF]) was set. * 0b1..Chip reset has occurred after Digital Tamper Flag (SR[DTF]) was set. */ #define DIGTMP_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TAF_SHIFT)) & DIGTMP_SR_TAF_MASK) #define DIGTMP_SR_TIF0_MASK (0x4U) #define DIGTMP_SR_TIF0_SHIFT (2U) /*! TIF0 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF0_SHIFT)) & DIGTMP_SR_TIF0_MASK) #define DIGTMP_SR_TIF1_MASK (0x8U) #define DIGTMP_SR_TIF1_SHIFT (3U) /*! TIF1 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF1_SHIFT)) & DIGTMP_SR_TIF1_MASK) #define DIGTMP_SR_TIF2_MASK (0x10U) #define DIGTMP_SR_TIF2_SHIFT (4U) /*! TIF2 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF2_SHIFT)) & DIGTMP_SR_TIF2_MASK) #define DIGTMP_SR_TIF3_MASK (0x20U) #define DIGTMP_SR_TIF3_SHIFT (5U) /*! TIF3 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF3_SHIFT)) & DIGTMP_SR_TIF3_MASK) #define DIGTMP_SR_TIF4_MASK (0x40U) #define DIGTMP_SR_TIF4_SHIFT (6U) /*! TIF4 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF4_SHIFT)) & DIGTMP_SR_TIF4_MASK) #define DIGTMP_SR_TIF5_MASK (0x80U) #define DIGTMP_SR_TIF5_SHIFT (7U) /*! TIF5 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF5_SHIFT)) & DIGTMP_SR_TIF5_MASK) #define DIGTMP_SR_TIF6_MASK (0x100U) #define DIGTMP_SR_TIF6_SHIFT (8U) /*! TIF6 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF6_SHIFT)) & DIGTMP_SR_TIF6_MASK) #define DIGTMP_SR_TIF7_MASK (0x200U) #define DIGTMP_SR_TIF7_SHIFT (9U) /*! TIF7 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF7_SHIFT)) & DIGTMP_SR_TIF7_MASK) #define DIGTMP_SR_TIF8_MASK (0x400U) #define DIGTMP_SR_TIF8_SHIFT (10U) /*! TIF8 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF8_SHIFT)) & DIGTMP_SR_TIF8_MASK) #define DIGTMP_SR_TIF9_MASK (0x800U) #define DIGTMP_SR_TIF9_SHIFT (11U) /*! TIF9 - Tamper Input n Flag * 0b0..On-chip tamper not detected * 0b1..On-chip tamper detected */ #define DIGTMP_SR_TIF9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF9_SHIFT)) & DIGTMP_SR_TIF9_MASK) #define DIGTMP_SR_TPF0_MASK (0x10000U) #define DIGTMP_SR_TPF0_SHIFT (16U) /*! TPF0 - Tamper Pin n Flag * 0b0..Pin tamper not detected * 0b1..Pin tamper detected */ #define DIGTMP_SR_TPF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF0_SHIFT)) & DIGTMP_SR_TPF0_MASK) #define DIGTMP_SR_TPF1_MASK (0x20000U) #define DIGTMP_SR_TPF1_SHIFT (17U) /*! TPF1 - Tamper Pin n Flag * 0b0..Pin tamper not detected * 0b1..Pin tamper detected */ #define DIGTMP_SR_TPF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF1_SHIFT)) & DIGTMP_SR_TPF1_MASK) #define DIGTMP_SR_TPF2_MASK (0x40000U) #define DIGTMP_SR_TPF2_SHIFT (18U) /*! TPF2 - Tamper Pin n Flag * 0b0..Pin tamper not detected * 0b1..Pin tamper detected */ #define DIGTMP_SR_TPF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF2_SHIFT)) & DIGTMP_SR_TPF2_MASK) #define DIGTMP_SR_TPF3_MASK (0x80000U) #define DIGTMP_SR_TPF3_SHIFT (19U) /*! TPF3 - Tamper Pin n Flag * 0b0..Pin tamper not detected * 0b1..Pin tamper detected */ #define DIGTMP_SR_TPF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF3_SHIFT)) & DIGTMP_SR_TPF3_MASK) #define DIGTMP_SR_TPF4_MASK (0x100000U) #define DIGTMP_SR_TPF4_SHIFT (20U) /*! TPF4 - Tamper Pin n Flag * 0b0..Pin tamper not detected * 0b1..Pin tamper detected */ #define DIGTMP_SR_TPF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF4_SHIFT)) & DIGTMP_SR_TPF4_MASK) #define DIGTMP_SR_TPF5_MASK (0x200000U) #define DIGTMP_SR_TPF5_SHIFT (21U) /*! TPF5 - Tamper Pin n Flag * 0b0..Pin tamper not detected * 0b1..Pin tamper detected */ #define DIGTMP_SR_TPF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF5_SHIFT)) & DIGTMP_SR_TPF5_MASK) #define DIGTMP_SR_TPF6_MASK (0x400000U) #define DIGTMP_SR_TPF6_SHIFT (22U) /*! TPF6 - Tamper Pin n Flag * 0b0..Pin tamper not detected * 0b1..Pin tamper detected */ #define DIGTMP_SR_TPF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF6_SHIFT)) & DIGTMP_SR_TPF6_MASK) #define DIGTMP_SR_TPF7_MASK (0x800000U) #define DIGTMP_SR_TPF7_SHIFT (23U) /*! TPF7 - Tamper Pin n Flag * 0b0..Pin tamper not detected * 0b1..Pin tamper detected */ #define DIGTMP_SR_TPF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF7_SHIFT)) & DIGTMP_SR_TPF7_MASK) /*! @} */ /*! @name LR - Lock */ /*! @{ */ #define DIGTMP_LR_CRL_MASK (0x10U) #define DIGTMP_LR_CRL_SHIFT (4U) /*! CRL - Control Register Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_CRL_SHIFT)) & DIGTMP_LR_CRL_MASK) #define DIGTMP_LR_SRL_MASK (0x20U) #define DIGTMP_LR_SRL_SHIFT (5U) /*! SRL - Status Register Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_SRL_SHIFT)) & DIGTMP_LR_SRL_MASK) #define DIGTMP_LR_LRL_MASK (0x40U) #define DIGTMP_LR_LRL_SHIFT (6U) /*! LRL - Lock Register Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_LRL_SHIFT)) & DIGTMP_LR_LRL_MASK) #define DIGTMP_LR_IEL_MASK (0x80U) #define DIGTMP_LR_IEL_SHIFT (7U) /*! IEL - Interrupt Enable Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_IEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_IEL_SHIFT)) & DIGTMP_LR_IEL_MASK) #define DIGTMP_LR_TSL_MASK (0x100U) #define DIGTMP_LR_TSL_SHIFT (8U) /*! TSL - Tamper Seconds Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_TSL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TSL_SHIFT)) & DIGTMP_LR_TSL_MASK) #define DIGTMP_LR_TEL_MASK (0x200U) #define DIGTMP_LR_TEL_SHIFT (9U) /*! TEL - Tamper Enable Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_TEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TEL_SHIFT)) & DIGTMP_LR_TEL_MASK) #define DIGTMP_LR_PDL_MASK (0x400U) #define DIGTMP_LR_PDL_SHIFT (10U) /*! PDL - Pin Direction Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_PDL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PDL_SHIFT)) & DIGTMP_LR_PDL_MASK) #define DIGTMP_LR_PPL_MASK (0x800U) #define DIGTMP_LR_PPL_SHIFT (11U) /*! PPL - Pin Polarity Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_PPL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PPL_SHIFT)) & DIGTMP_LR_PPL_MASK) #define DIGTMP_LR_ATL0_MASK (0x1000U) #define DIGTMP_LR_ATL0_SHIFT (12U) /*! ATL0 - Active Tamper Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_ATL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL0_SHIFT)) & DIGTMP_LR_ATL0_MASK) #define DIGTMP_LR_ATL1_MASK (0x2000U) #define DIGTMP_LR_ATL1_SHIFT (13U) /*! ATL1 - Active Tamper Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_ATL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL1_SHIFT)) & DIGTMP_LR_ATL1_MASK) #define DIGTMP_LR_GFL0_MASK (0x10000U) #define DIGTMP_LR_GFL0_SHIFT (16U) /*! GFL0 - Glitch Filter Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_GFL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL0_SHIFT)) & DIGTMP_LR_GFL0_MASK) #define DIGTMP_LR_GFL1_MASK (0x20000U) #define DIGTMP_LR_GFL1_SHIFT (17U) /*! GFL1 - Glitch Filter Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_GFL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL1_SHIFT)) & DIGTMP_LR_GFL1_MASK) #define DIGTMP_LR_GFL2_MASK (0x40000U) #define DIGTMP_LR_GFL2_SHIFT (18U) /*! GFL2 - Glitch Filter Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_GFL2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL2_SHIFT)) & DIGTMP_LR_GFL2_MASK) #define DIGTMP_LR_GFL3_MASK (0x80000U) #define DIGTMP_LR_GFL3_SHIFT (19U) /*! GFL3 - Glitch Filter Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_GFL3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL3_SHIFT)) & DIGTMP_LR_GFL3_MASK) #define DIGTMP_LR_GFL4_MASK (0x100000U) #define DIGTMP_LR_GFL4_SHIFT (20U) /*! GFL4 - Glitch Filter Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_GFL4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL4_SHIFT)) & DIGTMP_LR_GFL4_MASK) #define DIGTMP_LR_GFL5_MASK (0x200000U) #define DIGTMP_LR_GFL5_SHIFT (21U) /*! GFL5 - Glitch Filter Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_GFL5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL5_SHIFT)) & DIGTMP_LR_GFL5_MASK) #define DIGTMP_LR_GFL6_MASK (0x400000U) #define DIGTMP_LR_GFL6_SHIFT (22U) /*! GFL6 - Glitch Filter Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_GFL6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL6_SHIFT)) & DIGTMP_LR_GFL6_MASK) #define DIGTMP_LR_GFL7_MASK (0x800000U) #define DIGTMP_LR_GFL7_SHIFT (23U) /*! GFL7 - Glitch Filter Lock * 0b0..Locked and writes are ignored * 0b1..Not locked and writes complete as normal */ #define DIGTMP_LR_GFL7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL7_SHIFT)) & DIGTMP_LR_GFL7_MASK) /*! @} */ /*! @name IER - Interrupt Enable */ /*! @{ */ #define DIGTMP_IER_DTIE_MASK (0x1U) #define DIGTMP_IER_DTIE_SHIFT (0U) /*! DTIE - Digital Tamper Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_DTIE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_DTIE_SHIFT)) & DIGTMP_IER_DTIE_MASK) #define DIGTMP_IER_TIIE0_MASK (0x4U) #define DIGTMP_IER_TIIE0_SHIFT (2U) /*! TIIE0 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE0_SHIFT)) & DIGTMP_IER_TIIE0_MASK) #define DIGTMP_IER_TIIE1_MASK (0x8U) #define DIGTMP_IER_TIIE1_SHIFT (3U) /*! TIIE1 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE1_SHIFT)) & DIGTMP_IER_TIIE1_MASK) #define DIGTMP_IER_TIIE2_MASK (0x10U) #define DIGTMP_IER_TIIE2_SHIFT (4U) /*! TIIE2 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE2_SHIFT)) & DIGTMP_IER_TIIE2_MASK) #define DIGTMP_IER_TIIE3_MASK (0x20U) #define DIGTMP_IER_TIIE3_SHIFT (5U) /*! TIIE3 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE3_SHIFT)) & DIGTMP_IER_TIIE3_MASK) #define DIGTMP_IER_TIIE4_MASK (0x40U) #define DIGTMP_IER_TIIE4_SHIFT (6U) /*! TIIE4 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE4_SHIFT)) & DIGTMP_IER_TIIE4_MASK) #define DIGTMP_IER_TIIE5_MASK (0x80U) #define DIGTMP_IER_TIIE5_SHIFT (7U) /*! TIIE5 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE5_SHIFT)) & DIGTMP_IER_TIIE5_MASK) #define DIGTMP_IER_TIIE6_MASK (0x100U) #define DIGTMP_IER_TIIE6_SHIFT (8U) /*! TIIE6 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE6_SHIFT)) & DIGTMP_IER_TIIE6_MASK) #define DIGTMP_IER_TIIE7_MASK (0x200U) #define DIGTMP_IER_TIIE7_SHIFT (9U) /*! TIIE7 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE7_SHIFT)) & DIGTMP_IER_TIIE7_MASK) #define DIGTMP_IER_TIIE8_MASK (0x400U) #define DIGTMP_IER_TIIE8_SHIFT (10U) /*! TIIE8 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE8_SHIFT)) & DIGTMP_IER_TIIE8_MASK) #define DIGTMP_IER_TIIE9_MASK (0x800U) #define DIGTMP_IER_TIIE9_SHIFT (11U) /*! TIIE9 - Tamper Input n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TIIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE9_SHIFT)) & DIGTMP_IER_TIIE9_MASK) #define DIGTMP_IER_TPIE0_MASK (0x10000U) #define DIGTMP_IER_TPIE0_SHIFT (16U) /*! TPIE0 - Tamper Pin n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TPIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE0_SHIFT)) & DIGTMP_IER_TPIE0_MASK) #define DIGTMP_IER_TPIE1_MASK (0x20000U) #define DIGTMP_IER_TPIE1_SHIFT (17U) /*! TPIE1 - Tamper Pin n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TPIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE1_SHIFT)) & DIGTMP_IER_TPIE1_MASK) #define DIGTMP_IER_TPIE2_MASK (0x40000U) #define DIGTMP_IER_TPIE2_SHIFT (18U) /*! TPIE2 - Tamper Pin n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TPIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE2_SHIFT)) & DIGTMP_IER_TPIE2_MASK) #define DIGTMP_IER_TPIE3_MASK (0x80000U) #define DIGTMP_IER_TPIE3_SHIFT (19U) /*! TPIE3 - Tamper Pin n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TPIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE3_SHIFT)) & DIGTMP_IER_TPIE3_MASK) #define DIGTMP_IER_TPIE4_MASK (0x100000U) #define DIGTMP_IER_TPIE4_SHIFT (20U) /*! TPIE4 - Tamper Pin n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TPIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE4_SHIFT)) & DIGTMP_IER_TPIE4_MASK) #define DIGTMP_IER_TPIE5_MASK (0x200000U) #define DIGTMP_IER_TPIE5_SHIFT (21U) /*! TPIE5 - Tamper Pin n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TPIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE5_SHIFT)) & DIGTMP_IER_TPIE5_MASK) #define DIGTMP_IER_TPIE6_MASK (0x400000U) #define DIGTMP_IER_TPIE6_SHIFT (22U) /*! TPIE6 - Tamper Pin n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TPIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE6_SHIFT)) & DIGTMP_IER_TPIE6_MASK) #define DIGTMP_IER_TPIE7_MASK (0x800000U) #define DIGTMP_IER_TPIE7_SHIFT (23U) /*! TPIE7 - Tamper Pin n Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_IER_TPIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE7_SHIFT)) & DIGTMP_IER_TPIE7_MASK) /*! @} */ /*! @name TSR - Tamper Seconds */ /*! @{ */ #define DIGTMP_TSR_TTS_MASK (0xFFFFFFFFU) #define DIGTMP_TSR_TTS_SHIFT (0U) /*! TTS - Tamper Time Seconds */ #define DIGTMP_TSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TSR_TTS_SHIFT)) & DIGTMP_TSR_TTS_MASK) /*! @} */ /*! @name TER - Tamper Enable */ /*! @{ */ #define DIGTMP_TER_TIE0_MASK (0x4U) #define DIGTMP_TER_TIE0_SHIFT (2U) /*! TIE0 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE0_SHIFT)) & DIGTMP_TER_TIE0_MASK) #define DIGTMP_TER_TIE1_MASK (0x8U) #define DIGTMP_TER_TIE1_SHIFT (3U) /*! TIE1 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE1_SHIFT)) & DIGTMP_TER_TIE1_MASK) #define DIGTMP_TER_TIE2_MASK (0x10U) #define DIGTMP_TER_TIE2_SHIFT (4U) /*! TIE2 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE2_SHIFT)) & DIGTMP_TER_TIE2_MASK) #define DIGTMP_TER_TIE3_MASK (0x20U) #define DIGTMP_TER_TIE3_SHIFT (5U) /*! TIE3 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE3_SHIFT)) & DIGTMP_TER_TIE3_MASK) #define DIGTMP_TER_TIE4_MASK (0x40U) #define DIGTMP_TER_TIE4_SHIFT (6U) /*! TIE4 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE4_SHIFT)) & DIGTMP_TER_TIE4_MASK) #define DIGTMP_TER_TIE5_MASK (0x80U) #define DIGTMP_TER_TIE5_SHIFT (7U) /*! TIE5 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE5_SHIFT)) & DIGTMP_TER_TIE5_MASK) #define DIGTMP_TER_TIE6_MASK (0x100U) #define DIGTMP_TER_TIE6_SHIFT (8U) /*! TIE6 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE6_SHIFT)) & DIGTMP_TER_TIE6_MASK) #define DIGTMP_TER_TIE7_MASK (0x200U) #define DIGTMP_TER_TIE7_SHIFT (9U) /*! TIE7 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE7_SHIFT)) & DIGTMP_TER_TIE7_MASK) #define DIGTMP_TER_TIE8_MASK (0x400U) #define DIGTMP_TER_TIE8_SHIFT (10U) /*! TIE8 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE8_SHIFT)) & DIGTMP_TER_TIE8_MASK) #define DIGTMP_TER_TIE9_MASK (0x800U) #define DIGTMP_TER_TIE9_SHIFT (11U) /*! TIE9 - Tamper Input Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE9_SHIFT)) & DIGTMP_TER_TIE9_MASK) #define DIGTMP_TER_TPE0_MASK (0x10000U) #define DIGTMP_TER_TPE0_SHIFT (16U) /*! TPE0 - Tamper Pin Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TPE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE0_SHIFT)) & DIGTMP_TER_TPE0_MASK) #define DIGTMP_TER_TPE1_MASK (0x20000U) #define DIGTMP_TER_TPE1_SHIFT (17U) /*! TPE1 - Tamper Pin Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TPE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE1_SHIFT)) & DIGTMP_TER_TPE1_MASK) #define DIGTMP_TER_TPE2_MASK (0x40000U) #define DIGTMP_TER_TPE2_SHIFT (18U) /*! TPE2 - Tamper Pin Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TPE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE2_SHIFT)) & DIGTMP_TER_TPE2_MASK) #define DIGTMP_TER_TPE3_MASK (0x80000U) #define DIGTMP_TER_TPE3_SHIFT (19U) /*! TPE3 - Tamper Pin Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TPE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE3_SHIFT)) & DIGTMP_TER_TPE3_MASK) #define DIGTMP_TER_TPE4_MASK (0x100000U) #define DIGTMP_TER_TPE4_SHIFT (20U) /*! TPE4 - Tamper Pin Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TPE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE4_SHIFT)) & DIGTMP_TER_TPE4_MASK) #define DIGTMP_TER_TPE5_MASK (0x200000U) #define DIGTMP_TER_TPE5_SHIFT (21U) /*! TPE5 - Tamper Pin Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TPE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE5_SHIFT)) & DIGTMP_TER_TPE5_MASK) #define DIGTMP_TER_TPE6_MASK (0x400000U) #define DIGTMP_TER_TPE6_SHIFT (22U) /*! TPE6 - Tamper Pin Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TPE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE6_SHIFT)) & DIGTMP_TER_TPE6_MASK) #define DIGTMP_TER_TPE7_MASK (0x800000U) #define DIGTMP_TER_TPE7_SHIFT (23U) /*! TPE7 - Tamper Pin Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_TER_TPE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE7_SHIFT)) & DIGTMP_TER_TPE7_MASK) /*! @} */ /*! @name PDR - Pin Direction */ /*! @{ */ #define DIGTMP_PDR_TPD0_MASK (0x1U) #define DIGTMP_PDR_TPD0_SHIFT (0U) /*! TPD0 - Tamper Pin Direction * 0b0..Input * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) */ #define DIGTMP_PDR_TPD0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD0_SHIFT)) & DIGTMP_PDR_TPD0_MASK) #define DIGTMP_PDR_TPD1_MASK (0x2U) #define DIGTMP_PDR_TPD1_SHIFT (1U) /*! TPD1 - Tamper Pin Direction * 0b0..Input * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) */ #define DIGTMP_PDR_TPD1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD1_SHIFT)) & DIGTMP_PDR_TPD1_MASK) #define DIGTMP_PDR_TPD2_MASK (0x4U) #define DIGTMP_PDR_TPD2_SHIFT (2U) /*! TPD2 - Tamper Pin Direction * 0b0..Input * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) */ #define DIGTMP_PDR_TPD2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD2_SHIFT)) & DIGTMP_PDR_TPD2_MASK) #define DIGTMP_PDR_TPD3_MASK (0x8U) #define DIGTMP_PDR_TPD3_SHIFT (3U) /*! TPD3 - Tamper Pin Direction * 0b0..Input * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) */ #define DIGTMP_PDR_TPD3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD3_SHIFT)) & DIGTMP_PDR_TPD3_MASK) #define DIGTMP_PDR_TPD4_MASK (0x10U) #define DIGTMP_PDR_TPD4_SHIFT (4U) /*! TPD4 - Tamper Pin Direction * 0b0..Input * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) */ #define DIGTMP_PDR_TPD4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD4_SHIFT)) & DIGTMP_PDR_TPD4_MASK) #define DIGTMP_PDR_TPD5_MASK (0x20U) #define DIGTMP_PDR_TPD5_SHIFT (5U) /*! TPD5 - Tamper Pin Direction * 0b0..Input * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) */ #define DIGTMP_PDR_TPD5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD5_SHIFT)) & DIGTMP_PDR_TPD5_MASK) #define DIGTMP_PDR_TPD6_MASK (0x40U) #define DIGTMP_PDR_TPD6_SHIFT (6U) /*! TPD6 - Tamper Pin Direction * 0b0..Input * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) */ #define DIGTMP_PDR_TPD6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD6_SHIFT)) & DIGTMP_PDR_TPD6_MASK) #define DIGTMP_PDR_TPD7_MASK (0x80U) #define DIGTMP_PDR_TPD7_SHIFT (7U) /*! TPD7 - Tamper Pin Direction * 0b0..Input * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) */ #define DIGTMP_PDR_TPD7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD7_SHIFT)) & DIGTMP_PDR_TPD7_MASK) #define DIGTMP_PDR_TPOD0_MASK (0x10000U) #define DIGTMP_PDR_TPOD0_SHIFT (16U) /*! TPOD0 - Tamper Pin Output Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PDR_TPOD0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD0_SHIFT)) & DIGTMP_PDR_TPOD0_MASK) #define DIGTMP_PDR_TPOD1_MASK (0x20000U) #define DIGTMP_PDR_TPOD1_SHIFT (17U) /*! TPOD1 - Tamper Pin Output Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PDR_TPOD1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD1_SHIFT)) & DIGTMP_PDR_TPOD1_MASK) #define DIGTMP_PDR_TPOD2_MASK (0x40000U) #define DIGTMP_PDR_TPOD2_SHIFT (18U) /*! TPOD2 - Tamper Pin Output Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PDR_TPOD2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD2_SHIFT)) & DIGTMP_PDR_TPOD2_MASK) #define DIGTMP_PDR_TPOD3_MASK (0x80000U) #define DIGTMP_PDR_TPOD3_SHIFT (19U) /*! TPOD3 - Tamper Pin Output Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PDR_TPOD3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD3_SHIFT)) & DIGTMP_PDR_TPOD3_MASK) #define DIGTMP_PDR_TPOD4_MASK (0x100000U) #define DIGTMP_PDR_TPOD4_SHIFT (20U) /*! TPOD4 - Tamper Pin Output Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PDR_TPOD4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD4_SHIFT)) & DIGTMP_PDR_TPOD4_MASK) #define DIGTMP_PDR_TPOD5_MASK (0x200000U) #define DIGTMP_PDR_TPOD5_SHIFT (21U) /*! TPOD5 - Tamper Pin Output Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PDR_TPOD5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD5_SHIFT)) & DIGTMP_PDR_TPOD5_MASK) #define DIGTMP_PDR_TPOD6_MASK (0x400000U) #define DIGTMP_PDR_TPOD6_SHIFT (22U) /*! TPOD6 - Tamper Pin Output Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PDR_TPOD6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD6_SHIFT)) & DIGTMP_PDR_TPOD6_MASK) #define DIGTMP_PDR_TPOD7_MASK (0x800000U) #define DIGTMP_PDR_TPOD7_SHIFT (23U) /*! TPOD7 - Tamper Pin Output Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PDR_TPOD7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD7_SHIFT)) & DIGTMP_PDR_TPOD7_MASK) /*! @} */ /*! @name PPR - Pin Polarity */ /*! @{ */ #define DIGTMP_PPR_TPP0_MASK (0x1U) #define DIGTMP_PPR_TPP0_SHIFT (0U) /*! TPP0 - Tamper Pin n Polarity * 0b0..Not inverted * 0b1..Inverted */ #define DIGTMP_PPR_TPP0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP0_SHIFT)) & DIGTMP_PPR_TPP0_MASK) #define DIGTMP_PPR_TPP1_MASK (0x2U) #define DIGTMP_PPR_TPP1_SHIFT (1U) /*! TPP1 - Tamper Pin n Polarity * 0b0..Not inverted * 0b1..Inverted */ #define DIGTMP_PPR_TPP1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP1_SHIFT)) & DIGTMP_PPR_TPP1_MASK) #define DIGTMP_PPR_TPP2_MASK (0x4U) #define DIGTMP_PPR_TPP2_SHIFT (2U) /*! TPP2 - Tamper Pin n Polarity * 0b0..Not inverted * 0b1..Inverted */ #define DIGTMP_PPR_TPP2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP2_SHIFT)) & DIGTMP_PPR_TPP2_MASK) #define DIGTMP_PPR_TPP3_MASK (0x8U) #define DIGTMP_PPR_TPP3_SHIFT (3U) /*! TPP3 - Tamper Pin n Polarity * 0b0..Not inverted * 0b1..Inverted */ #define DIGTMP_PPR_TPP3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP3_SHIFT)) & DIGTMP_PPR_TPP3_MASK) #define DIGTMP_PPR_TPP4_MASK (0x10U) #define DIGTMP_PPR_TPP4_SHIFT (4U) /*! TPP4 - Tamper Pin n Polarity * 0b0..Not inverted * 0b1..Inverted */ #define DIGTMP_PPR_TPP4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK) #define DIGTMP_PPR_TPP5_MASK (0x20U) #define DIGTMP_PPR_TPP5_SHIFT (5U) /*! TPP5 - Tamper Pin n Polarity * 0b0..Not inverted * 0b1..Inverted */ #define DIGTMP_PPR_TPP5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP5_SHIFT)) & DIGTMP_PPR_TPP5_MASK) #define DIGTMP_PPR_TPP6_MASK (0x40U) #define DIGTMP_PPR_TPP6_SHIFT (6U) /*! TPP6 - Tamper Pin n Polarity * 0b0..Not inverted * 0b1..Inverted */ #define DIGTMP_PPR_TPP6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP6_SHIFT)) & DIGTMP_PPR_TPP6_MASK) #define DIGTMP_PPR_TPP7_MASK (0x80U) #define DIGTMP_PPR_TPP7_SHIFT (7U) /*! TPP7 - Tamper Pin n Polarity * 0b0..Not inverted * 0b1..Inverted */ #define DIGTMP_PPR_TPP7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP7_SHIFT)) & DIGTMP_PPR_TPP7_MASK) #define DIGTMP_PPR_TPID0_MASK (0x10000U) #define DIGTMP_PPR_TPID0_SHIFT (16U) /*! TPID0 - Tamper Pin n Input Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PPR_TPID0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID0_SHIFT)) & DIGTMP_PPR_TPID0_MASK) #define DIGTMP_PPR_TPID1_MASK (0x20000U) #define DIGTMP_PPR_TPID1_SHIFT (17U) /*! TPID1 - Tamper Pin n Input Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PPR_TPID1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID1_SHIFT)) & DIGTMP_PPR_TPID1_MASK) #define DIGTMP_PPR_TPID2_MASK (0x40000U) #define DIGTMP_PPR_TPID2_SHIFT (18U) /*! TPID2 - Tamper Pin n Input Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PPR_TPID2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID2_SHIFT)) & DIGTMP_PPR_TPID2_MASK) #define DIGTMP_PPR_TPID3_MASK (0x80000U) #define DIGTMP_PPR_TPID3_SHIFT (19U) /*! TPID3 - Tamper Pin n Input Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PPR_TPID3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID3_SHIFT)) & DIGTMP_PPR_TPID3_MASK) #define DIGTMP_PPR_TPID4_MASK (0x100000U) #define DIGTMP_PPR_TPID4_SHIFT (20U) /*! TPID4 - Tamper Pin n Input Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PPR_TPID4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID4_SHIFT)) & DIGTMP_PPR_TPID4_MASK) #define DIGTMP_PPR_TPID5_MASK (0x200000U) #define DIGTMP_PPR_TPID5_SHIFT (21U) /*! TPID5 - Tamper Pin n Input Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PPR_TPID5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID5_SHIFT)) & DIGTMP_PPR_TPID5_MASK) #define DIGTMP_PPR_TPID6_MASK (0x400000U) #define DIGTMP_PPR_TPID6_SHIFT (22U) /*! TPID6 - Tamper Pin n Input Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PPR_TPID6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID6_SHIFT)) & DIGTMP_PPR_TPID6_MASK) #define DIGTMP_PPR_TPID7_MASK (0x800000U) #define DIGTMP_PPR_TPID7_SHIFT (23U) /*! TPID7 - Tamper Pin n Input Data * 0b0..Zero * 0b1..One */ #define DIGTMP_PPR_TPID7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID7_SHIFT)) & DIGTMP_PPR_TPID7_MASK) /*! @} */ /*! @name ATR - Active Tamper */ /*! @{ */ #define DIGTMP_ATR_ATSR_MASK (0xFFFFU) #define DIGTMP_ATR_ATSR_SHIFT (0U) /*! ATSR - Active Tamper Shift Register */ #define DIGTMP_ATR_ATSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATSR_SHIFT)) & DIGTMP_ATR_ATSR_MASK) #define DIGTMP_ATR_ATP_MASK (0xFFFF0000U) #define DIGTMP_ATR_ATP_SHIFT (16U) /*! ATP - Active Tamper Polynomial */ #define DIGTMP_ATR_ATP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATP_SHIFT)) & DIGTMP_ATR_ATP_MASK) /*! @} */ /* The count of DIGTMP_ATR */ #define DIGTMP_ATR_COUNT (2U) /*! @name PGFR - Pin Glitch Filter */ /*! @{ */ #define DIGTMP_PGFR_GFW_MASK (0x3FU) #define DIGTMP_PGFR_GFW_SHIFT (0U) /*! GFW - Glitch Filter Width */ #define DIGTMP_PGFR_GFW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFW_SHIFT)) & DIGTMP_PGFR_GFW_MASK) #define DIGTMP_PGFR_GFP_MASK (0x40U) #define DIGTMP_PGFR_GFP_SHIFT (6U) /*! GFP - Glitch Filter Prescaler * 0b0..512 Hz prescaler clock * 0b1..32.768 kHz clock */ #define DIGTMP_PGFR_GFP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFP_SHIFT)) & DIGTMP_PGFR_GFP_MASK) #define DIGTMP_PGFR_GFE_MASK (0x80U) #define DIGTMP_PGFR_GFE_SHIFT (7U) /*! GFE - Glitch Filter Enable * 0b0..Bypasses * 0b1..Enables */ #define DIGTMP_PGFR_GFE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFE_SHIFT)) & DIGTMP_PGFR_GFE_MASK) #define DIGTMP_PGFR_TPSW_MASK (0x300U) #define DIGTMP_PGFR_TPSW_SHIFT (8U) /*! TPSW - Tamper Pin Sample Width * 0b00..Continuous monitoring, pin sampling disabled * 0b01..2 cycles for pull enable and 1 cycle for input buffer enable * 0b10..4 cycles for pull enable and 2 cycles for input buffer enable * 0b11..8 cycles for pull enable and 4 cycles for input buffer enable */ #define DIGTMP_PGFR_TPSW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSW_SHIFT)) & DIGTMP_PGFR_TPSW_MASK) #define DIGTMP_PGFR_TPSF_MASK (0xC00U) #define DIGTMP_PGFR_TPSF_SHIFT (10U) /*! TPSF - Tamper Pin Sample Frequency * 0b00..Every 8 cycles * 0b01..Every 32 cycles * 0b10..Every 128 cycles * 0b11..Every 512 cycles */ #define DIGTMP_PGFR_TPSF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSF_SHIFT)) & DIGTMP_PGFR_TPSF_MASK) #define DIGTMP_PGFR_TPEX_MASK (0x30000U) #define DIGTMP_PGFR_TPEX_SHIFT (16U) /*! TPEX - Tamper Pin Expected * 0b00..Zero/passive tamper * 0b01..Active Tamper 0 output * 0b10..Active Tamper 1 output * 0b11..Active Tamper 0 output XORed with Active Tamper 1 output */ #define DIGTMP_PGFR_TPEX(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPEX_SHIFT)) & DIGTMP_PGFR_TPEX_MASK) #define DIGTMP_PGFR_TPE_MASK (0x1000000U) #define DIGTMP_PGFR_TPE_SHIFT (24U) /*! TPE - Tamper Pull Enable * 0b0..Disables * 0b1..Enables */ #define DIGTMP_PGFR_TPE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPE_SHIFT)) & DIGTMP_PGFR_TPE_MASK) #define DIGTMP_PGFR_TPS_MASK (0x2000000U) #define DIGTMP_PGFR_TPS_SHIFT (25U) /*! TPS - Tamper Pull Select * 0b0..Asserts * 0b1..Negates */ #define DIGTMP_PGFR_TPS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPS_SHIFT)) & DIGTMP_PGFR_TPS_MASK) /*! @} */ /* The count of DIGTMP_PGFR */ #define DIGTMP_PGFR_COUNT (8U) /*! * @} */ /* end of group DIGTMP_Register_Masks */ /* DIGTMP - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral TDET0 base address */ #define TDET0_BASE (0x50058000u) /** Peripheral TDET0 base address */ #define TDET0_BASE_NS (0x40058000u) /** Peripheral TDET0 base pointer */ #define TDET0 ((DIGTMP_Type *)TDET0_BASE) /** Peripheral TDET0 base pointer */ #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) /** Array initializer of DIGTMP peripheral base addresses */ #define DIGTMP_BASE_ADDRS { TDET0_BASE } /** Array initializer of DIGTMP peripheral base pointers */ #define DIGTMP_BASE_PTRS { TDET0 } /** Array initializer of DIGTMP peripheral base addresses */ #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } /** Array initializer of DIGTMP peripheral base pointers */ #define DIGTMP_BASE_PTRS_NS { TDET0_NS } #else /** Peripheral TDET0 base address */ #define TDET0_BASE (0x40058000u) /** Peripheral TDET0 base pointer */ #define TDET0 ((DIGTMP_Type *)TDET0_BASE) /** Array initializer of DIGTMP peripheral base addresses */ #define DIGTMP_BASE_ADDRS { TDET0_BASE } /** Array initializer of DIGTMP peripheral base pointers */ #define DIGTMP_BASE_PTRS { TDET0 } #endif /*! * @} */ /* end of group DIGTMP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DM_Peripheral_Access_Layer DM Peripheral Access Layer * @{ */ /** DM - Register Layout Typedef */ typedef struct { __IO uint32_t CSW; /**< Command and Status Word, offset: 0x0 */ __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ uint8_t RESERVED_0[240]; __I uint32_t ID; /**< Identification, offset: 0xFC */ } DM_Type; /* ---------------------------------------------------------------------------- -- DM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DM_Register_Masks DM Register Masks * @{ */ /*! @name CSW - Command and Status Word */ /*! @{ */ #define DM_CSW_RESYNCH_REQ_MASK (0x1U) #define DM_CSW_RESYNCH_REQ_SHIFT (0U) /*! RESYNCH_REQ - Resynchronization Request * 0b0..No request * 0b1..Request for resynchronization */ #define DM_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_RESYNCH_REQ_SHIFT)) & DM_CSW_RESYNCH_REQ_MASK) #define DM_CSW_REQ_PENDING_MASK (0x2U) #define DM_CSW_REQ_PENDING_SHIFT (1U) /*! REQ_PENDING - Request Pending * 0b0..No request pending * 0b1..Request for resynchronization pending */ #define DM_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_REQ_PENDING_SHIFT)) & DM_CSW_REQ_PENDING_MASK) #define DM_CSW_DBG_OR_ERR_MASK (0x4U) #define DM_CSW_DBG_OR_ERR_SHIFT (2U) /*! DBG_OR_ERR - DBGMB Overrun Error * 0b0..No DBGMB Overrun error * 0b1..DBGMB overrun error. A DBGMB overrun occurred. */ #define DM_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_DBG_OR_ERR_SHIFT)) & DM_CSW_DBG_OR_ERR_MASK) #define DM_CSW_AHB_OR_ERR_MASK (0x8U) #define DM_CSW_AHB_OR_ERR_SHIFT (3U) /*! AHB_OR_ERR - AHB Overrun Error * 0b0..No AHB Overrun Error * 0b1..AHB Overrun Error. An AHB overrun occurred. */ #define DM_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_AHB_OR_ERR_SHIFT)) & DM_CSW_AHB_OR_ERR_MASK) #define DM_CSW_SOFT_RESET_MASK (0x10U) #define DM_CSW_SOFT_RESET_SHIFT (4U) /*! SOFT_RESET - Soft Reset */ #define DM_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_SOFT_RESET_SHIFT)) & DM_CSW_SOFT_RESET_MASK) #define DM_CSW_CHIP_RESET_REQ_MASK (0x20U) #define DM_CSW_CHIP_RESET_REQ_SHIFT (5U) /*! CHIP_RESET_REQ - Chip Reset Request */ #define DM_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_CHIP_RESET_REQ_SHIFT)) & DM_CSW_CHIP_RESET_REQ_MASK) /*! @} */ /*! @name REQUEST - Request Value */ /*! @{ */ #define DM_REQUEST_REQUEST_MASK (0xFFFFFFFFU) #define DM_REQUEST_REQUEST_SHIFT (0U) /*! REQUEST - Request Value */ #define DM_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DM_REQUEST_REQUEST_SHIFT)) & DM_REQUEST_REQUEST_MASK) /*! @} */ /*! @name RETURN - Return Value */ /*! @{ */ #define DM_RETURN_RET_MASK (0xFFFFFFFFU) #define DM_RETURN_RET_SHIFT (0U) /*! RET - Return Value */ #define DM_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DM_RETURN_RET_SHIFT)) & DM_RETURN_RET_MASK) /*! @} */ /*! @name ID - Identification */ /*! @{ */ #define DM_ID_ID_MASK (0xFFFFFFFFU) #define DM_ID_ID_SHIFT (0U) /*! ID - Identification Value */ #define DM_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DM_ID_ID_SHIFT)) & DM_ID_ID_MASK) /*! @} */ /*! * @} */ /* end of group DM_Register_Masks */ /* DM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral DM0 base address */ #define DM0_BASE (0x500BD000u) /** Peripheral DM0 base address */ #define DM0_BASE_NS (0x400BD000u) /** Peripheral DM0 base pointer */ #define DM0 ((DM_Type *)DM0_BASE) /** Peripheral DM0 base pointer */ #define DM0_NS ((DM_Type *)DM0_BASE_NS) /** Array initializer of DM peripheral base addresses */ #define DM_BASE_ADDRS { DM0_BASE } /** Array initializer of DM peripheral base pointers */ #define DM_BASE_PTRS { DM0 } /** Array initializer of DM peripheral base addresses */ #define DM_BASE_ADDRS_NS { DM0_BASE_NS } /** Array initializer of DM peripheral base pointers */ #define DM_BASE_PTRS_NS { DM0_NS } #else /** Peripheral DM0 base address */ #define DM0_BASE (0x400BD000u) /** Peripheral DM0 base pointer */ #define DM0 ((DM_Type *)DM0_BASE) /** Array initializer of DM peripheral base addresses */ #define DM_BASE_ADDRS { DM0_BASE } /** Array initializer of DM peripheral base pointers */ #define DM_BASE_PTRS { DM0 } #endif /*! * @} */ /* end of group DM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer * @{ */ /** DMA - Register Layout Typedef */ typedef struct { __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ uint8_t RESERVED_0[240]; __IO uint32_t CH_GRPRI[16]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_1[3776]; struct { /* offset: 0x1000, array step: 0x1000 */ __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */ __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */ __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */ __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */ __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */ __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */ uint8_t RESERVED_0[8]; __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */ __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */ __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */ union { /* offset: 0x1028, array step: 0x1000 */ __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */ __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */ }; __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */ __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */ __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */ union { /* offset: 0x1036, array step: 0x1000 */ __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */ __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */ }; __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */ __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */ union { /* offset: 0x103E, array step: 0x1000 */ __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */ __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */ }; uint8_t RESERVED_1[4032]; } CH[16]; } DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /*! @name MP_CSR - Management Page Control */ /*! @{ */ #define DMA_MP_CSR_EDBG_MASK (0x2U) #define DMA_MP_CSR_EDBG_SHIFT (1U) /*! EDBG - Enable Debug * 0b0..Debug mode disabled * 0b1..Debug mode is enabled. */ #define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) #define DMA_MP_CSR_ERCA_MASK (0x4U) #define DMA_MP_CSR_ERCA_SHIFT (2U) /*! ERCA - Enable Round Robin Channel Arbitration * 0b0..Round-robin channel arbitration disabled * 0b1..Round-robin channel arbitration enabled */ #define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) #define DMA_MP_CSR_HAE_MASK (0x10U) #define DMA_MP_CSR_HAE_SHIFT (4U) /*! HAE - Halt After Error * 0b0..Normal operation * 0b1..Any error causes the HALT field to be set to 1 */ #define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) #define DMA_MP_CSR_HALT_MASK (0x20U) #define DMA_MP_CSR_HALT_SHIFT (5U) /*! HALT - Halt DMA Operations * 0b0..Normal operation * 0b1..Stall the start of any new channels */ #define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) #define DMA_MP_CSR_GCLC_MASK (0x40U) #define DMA_MP_CSR_GCLC_SHIFT (6U) /*! GCLC - Global Channel Linking Control * 0b0..Channel linking disabled for all channels * 0b1..Channel linking available and controlled by each channel's link settings */ #define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) #define DMA_MP_CSR_GMRC_MASK (0x80U) #define DMA_MP_CSR_GMRC_SHIFT (7U) /*! GMRC - Global Master ID Replication Control * 0b0..Master ID replication disabled for all channels * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting */ #define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) #define DMA_MP_CSR_ECX_MASK (0x100U) #define DMA_MP_CSR_ECX_SHIFT (8U) /*! ECX - Cancel Transfer With Error * 0b0..Normal operation * 0b1..Cancel the remaining data transfer */ #define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) #define DMA_MP_CSR_CX_MASK (0x200U) #define DMA_MP_CSR_CX_SHIFT (9U) /*! CX - Cancel Transfer * 0b0..Normal operation * 0b1..Cancel the remaining data transfer */ #define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) #define DMA_MP_CSR_ACTIVE_ID_MASK (0xF000000U) #define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) /*! ACTIVE_ID - Active Channel ID */ #define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) #define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) #define DMA_MP_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - DMA Active Status * 0b0..eDMA is idle * 0b1..eDMA is executing a channel */ #define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) /*! @} */ /*! @name MP_ES - Management Page Error Status */ /*! @{ */ #define DMA_MP_ES_DBE_MASK (0x1U) #define DMA_MP_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..Last recorded error was a bus error on a destination write */ #define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) #define DMA_MP_ES_SBE_MASK (0x2U) #define DMA_MP_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..Last recorded error was a bus error on a source read */ #define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) #define DMA_MP_ES_SGE_MASK (0x4U) #define DMA_MP_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field */ #define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) #define DMA_MP_ES_NCE_MASK (0x8U) #define DMA_MP_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error */ #define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) #define DMA_MP_ES_DOE_MASK (0x10U) #define DMA_MP_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field */ #define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) #define DMA_MP_ES_DAE_MASK (0x20U) #define DMA_MP_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field */ #define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) #define DMA_MP_ES_SOE_MASK (0x40U) #define DMA_MP_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field */ #define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) #define DMA_MP_ES_SAE_MASK (0x80U) #define DMA_MP_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field */ #define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) #define DMA_MP_ES_ECX_MASK (0x100U) #define DMA_MP_ES_ECX_SHIFT (8U) /*! ECX - Transfer Canceled * 0b0..No canceled transfers * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input */ #define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) #define DMA_MP_ES_ERRCHN_MASK (0xF000000U) #define DMA_MP_ES_ERRCHN_SHIFT (24U) /*! ERRCHN - Error Channel Number or Canceled Channel Number */ #define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) #define DMA_MP_ES_VLD_MASK (0x80000000U) #define DMA_MP_ES_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..No CHn_ES[ERR] fields are set to 1 * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared */ #define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) /*! @} */ /*! @name MP_INT - Management Page Interrupt Request Status */ /*! @{ */ #define DMA_MP_INT_INT_MASK (0xFFFFU) #define DMA_MP_INT_INT_SHIFT (0U) /*! INT - Interrupt Request Status */ #define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) /*! @} */ /*! @name MP_HRS - Management Page Hardware Request Status */ /*! @{ */ #define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) #define DMA_MP_HRS_HRS_SHIFT (0U) /*! HRS - Hardware Request Status */ #define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) /*! @} */ /*! @name CH_GRPRI - Channel Arbitration Group */ /*! @{ */ #define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) #define DMA_CH_GRPRI_GRPRI_SHIFT (0U) /*! GRPRI - Arbitration Group For Channel n */ #define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) /*! @} */ /* The count of DMA_CH_GRPRI */ #define DMA_CH_GRPRI_COUNT (16U) /*! @name CH_CSR - Channel Control and Status */ /*! @{ */ #define DMA_CH_CSR_ERQ_MASK (0x1U) #define DMA_CH_CSR_ERQ_SHIFT (0U) /*! ERQ - Enable DMA Request * 0b0..DMA hardware request signal for corresponding channel disabled * 0b1..DMA hardware request signal for corresponding channel enabled */ #define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) #define DMA_CH_CSR_EARQ_MASK (0x2U) #define DMA_CH_CSR_EARQ_SHIFT (1U) /*! EARQ - Enable Asynchronous DMA Request * 0b0..Disable asynchronous DMA request for the channel * 0b1..Enable asynchronous DMA request for the channel */ #define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) #define DMA_CH_CSR_EEI_MASK (0x4U) #define DMA_CH_CSR_EEI_SHIFT (2U) /*! EEI - Enable Error Interrupt * 0b0..Error signal for corresponding channel does not generate error interrupt * 0b1..Assertion of error signal for corresponding channel generates error interrupt request */ #define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) #define DMA_CH_CSR_EBW_MASK (0x8U) #define DMA_CH_CSR_EBW_SHIFT (3U) /*! EBW - Enable Buffered Writes * 0b0..Buffered writes on system bus disabled * 0b1..Buffered writes on system bus enabled */ #define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK) #define DMA_CH_CSR_DONE_MASK (0x40000000U) #define DMA_CH_CSR_DONE_SHIFT (30U) /*! DONE - Channel Done */ #define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) #define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) #define DMA_CH_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - Channel Active */ #define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) /*! @} */ /* The count of DMA_CH_CSR */ #define DMA_CH_CSR_COUNT (16U) /*! @name CH_ES - Channel Error Status */ /*! @{ */ #define DMA_CH_ES_DBE_MASK (0x1U) #define DMA_CH_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..Last recorded error was bus error on destination write */ #define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) #define DMA_CH_ES_SBE_MASK (0x2U) #define DMA_CH_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..Last recorded error was bus error on source read */ #define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) #define DMA_CH_ES_SGE_MASK (0x4U) #define DMA_CH_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field */ #define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) #define DMA_CH_ES_NCE_MASK (0x8U) #define DMA_CH_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields */ #define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) #define DMA_CH_ES_DOE_MASK (0x10U) #define DMA_CH_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field */ #define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) #define DMA_CH_ES_DAE_MASK (0x20U) #define DMA_CH_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field */ #define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) #define DMA_CH_ES_SOE_MASK (0x40U) #define DMA_CH_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field */ #define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) #define DMA_CH_ES_SAE_MASK (0x80U) #define DMA_CH_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field */ #define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) #define DMA_CH_ES_ERR_MASK (0x80000000U) #define DMA_CH_ES_ERR_SHIFT (31U) /*! ERR - Error In Channel * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) /*! @} */ /* The count of DMA_CH_ES */ #define DMA_CH_ES_COUNT (16U) /*! @name CH_INT - Channel Interrupt Status */ /*! @{ */ #define DMA_CH_INT_INT_MASK (0x1U) #define DMA_CH_INT_INT_SHIFT (0U) /*! INT - Interrupt Request * 0b0..Interrupt request for corresponding channel cleared * 0b1..Interrupt request for corresponding channel active */ #define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) /*! @} */ /* The count of DMA_CH_INT */ #define DMA_CH_INT_COUNT (16U) /*! @name CH_SBR - Channel System Bus */ /*! @{ */ #define DMA_CH_SBR_MID_MASK (0x1FU) #define DMA_CH_SBR_MID_SHIFT (0U) /*! MID - Master ID */ #define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) #define DMA_CH_SBR_SEC_MASK (0x4000U) #define DMA_CH_SBR_SEC_SHIFT (14U) /*! SEC - Security Level * 0b0..Nonsecure protection level for DMA transfers * 0b1..Secure protection level for DMA transfers */ #define DMA_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK) #define DMA_CH_SBR_PAL_MASK (0x8000U) #define DMA_CH_SBR_PAL_SHIFT (15U) /*! PAL - Privileged Access Level * 0b0..User protection level for DMA transfers * 0b1..Privileged protection level for DMA transfers */ #define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) #define DMA_CH_SBR_EMI_MASK (0x10000U) #define DMA_CH_SBR_EMI_SHIFT (16U) /*! EMI - Enable Master ID Replication * 0b0..Master ID replication is disabled * 0b1..Master ID replication is enabled */ #define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) /*! @} */ /* The count of DMA_CH_SBR */ #define DMA_CH_SBR_COUNT (16U) /*! @name CH_PRI - Channel Priority */ /*! @{ */ #define DMA_CH_PRI_APL_MASK (0x7U) #define DMA_CH_PRI_APL_SHIFT (0U) /*! APL - Arbitration Priority Level */ #define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) #define DMA_CH_PRI_DPA_MASK (0x40000000U) #define DMA_CH_PRI_DPA_SHIFT (30U) /*! DPA - Disable Preempt Ability * 0b0..Channel can suspend a lower-priority channel * 0b1..Channel cannot suspend any other channel, regardless of channel priority */ #define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) #define DMA_CH_PRI_ECP_MASK (0x80000000U) #define DMA_CH_PRI_ECP_SHIFT (31U) /*! ECP - Enable Channel Preemption * 0b0..Channel cannot be suspended by a higher-priority channel's service request * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request */ #define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) /*! @} */ /* The count of DMA_CH_PRI */ #define DMA_CH_PRI_COUNT (16U) /*! @name CH_MUX - Channel Multiplexor Configuration */ /*! @{ */ #define DMA_CH_MUX_SRC_MASK (0x7FU) #define DMA_CH_MUX_SRC_SHIFT (0U) /*! SRC - Service Request Source */ #define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK) /*! @} */ /* The count of DMA_CH_MUX */ #define DMA_CH_MUX_COUNT (16U) /*! @name TCD_SADDR - TCD Source Address */ /*! @{ */ #define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_TCD_SADDR_SADDR_SHIFT (0U) /*! SADDR - Source Address */ #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) /*! @} */ /* The count of DMA_TCD_SADDR */ #define DMA_TCD_SADDR_COUNT (16U) /*! @name TCD_SOFF - TCD Signed Source Address Offset */ /*! @{ */ #define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) #define DMA_TCD_SOFF_SOFF_SHIFT (0U) /*! SOFF - Source Address Signed Offset */ #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) /*! @} */ /* The count of DMA_TCD_SOFF */ #define DMA_TCD_SOFF_COUNT (16U) /*! @name TCD_ATTR - TCD Transfer Attributes */ /*! @{ */ #define DMA_TCD_ATTR_DSIZE_MASK (0x7U) #define DMA_TCD_ATTR_DSIZE_SHIFT (0U) /*! DSIZE - Destination Data Transfer Size */ #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) #define DMA_TCD_ATTR_DMOD_MASK (0xF8U) #define DMA_TCD_ATTR_DMOD_SHIFT (3U) /*! DMOD - Destination Address Modulo */ #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) #define DMA_TCD_ATTR_SSIZE_MASK (0x700U) #define DMA_TCD_ATTR_SSIZE_SHIFT (8U) /*! SSIZE - Source Data Transfer Size * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..64-bit * 0b100..16-byte * 0b101..32-byte * 0b110.. * 0b111.. */ #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) #define DMA_TCD_ATTR_SMOD_MASK (0xF800U) #define DMA_TCD_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source Address Modulo * 0b00000..Source address modulo feature disabled * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] */ #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) /*! @} */ /* The count of DMA_TCD_ATTR */ #define DMA_TCD_ATTR_COUNT (16U) /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ /*! @{ */ #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) /*! NBYTES - Number of Bytes To Transfer Per Service Request */ #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..Minor loop offset not applied to DADDR * 0b1..Minor loop offset applied to DADDR */ #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..Minor loop offset not applied to SADDR * 0b1..Minor loop offset applied to SADDR */ #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) /*! @} */ /* The count of DMA_TCD_NBYTES_MLOFFNO */ #define DMA_TCD_NBYTES_MLOFFNO_COUNT (16U) /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ /*! @{ */ #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) /*! NBYTES - Number of Bytes To Transfer Per Service Request */ #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) /*! MLOFF - Minor Loop Offset */ #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..Minor loop offset not applied to DADDR * 0b1..Minor loop offset applied to DADDR */ #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..Minor loop offset not applied to SADDR * 0b1..Minor loop offset applied to SADDR */ #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) /*! @} */ /* The count of DMA_TCD_NBYTES_MLOFFYES */ #define DMA_TCD_NBYTES_MLOFFYES_COUNT (16U) /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ /*! @{ */ #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ #define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) /*! @} */ /* The count of DMA_TCD_SLAST_SDA */ #define DMA_TCD_SLAST_SDA_COUNT (16U) /*! @name TCD_DADDR - TCD Destination Address */ /*! @{ */ #define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_TCD_DADDR_DADDR_SHIFT (0U) /*! DADDR - Destination Address */ #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) /*! @} */ /* The count of DMA_TCD_DADDR */ #define DMA_TCD_DADDR_COUNT (16U) /*! @name TCD_DOFF - TCD Signed Destination Address Offset */ /*! @{ */ #define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) #define DMA_TCD_DOFF_DOFF_SHIFT (0U) /*! DOFF - Destination Address Signed Offset */ #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) /*! @} */ /* The count of DMA_TCD_DOFF */ #define DMA_TCD_DOFF_COUNT (16U) /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ /*! @{ */ #define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) #define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enable Link * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_CITER_ELINKNO */ #define DMA_TCD_CITER_ELINKNO_COUNT (16U) /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ /*! @{ */ #define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x1E00U) #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Minor Loop Link Channel Number */ #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) #define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable Link * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_CITER_ELINKYES */ #define DMA_TCD_CITER_ELINKYES_COUNT (16U) /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ /*! @{ */ #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) /*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ #define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) /*! @} */ /* The count of DMA_TCD_DLAST_SGA */ #define DMA_TCD_DLAST_SGA_COUNT (16U) /*! @name TCD_CSR - TCD Control and Status */ /*! @{ */ #define DMA_TCD_CSR_START_MASK (0x1U) #define DMA_TCD_CSR_START_SHIFT (0U) /*! START - Channel Start * 0b0..Channel not explicitly started * 0b1..Channel explicitly started via a software-initiated service request */ #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) #define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) #define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) /*! INTMAJOR - Enable Interrupt If Major count complete * 0b0..End-of-major loop interrupt disabled * 0b1..End-of-major loop interrupt enabled */ #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) #define DMA_TCD_CSR_INTHALF_MASK (0x4U) #define DMA_TCD_CSR_INTHALF_SHIFT (2U) /*! INTHALF - Enable Interrupt If Major Counter Half-complete * 0b0..Halfway point interrupt disabled * 0b1..Halfway point interrupt enabled */ #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) #define DMA_TCD_CSR_DREQ_MASK (0x8U) #define DMA_TCD_CSR_DREQ_SHIFT (3U) /*! DREQ - Disable Request * 0b0..No operation * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests */ #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) #define DMA_TCD_CSR_ESG_MASK (0x10U) #define DMA_TCD_CSR_ESG_SHIFT (4U) /*! ESG - Enable Scatter/Gather Processing * 0b0..Current channel's TCD is normal format * 0b1..Current channel's TCD specifies scatter/gather format. */ #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) #define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) #define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) /*! MAJORELINK - Enable Link When Major Loop Complete * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) #define DMA_TCD_CSR_EEOP_MASK (0x40U) #define DMA_TCD_CSR_EEOP_SHIFT (6U) /*! EEOP - Enable End-Of-Packet Processing * 0b0..End-of-packet operation disabled * 0b1..End-of-packet hardware input signal enabled */ #define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) #define DMA_TCD_CSR_ESDA_MASK (0x80U) #define DMA_TCD_CSR_ESDA_SHIFT (7U) /*! ESDA - Enable Store Destination Address * 0b0..Ability to store destination address to system memory disabled * 0b1..Ability to store destination address to system memory enabled */ #define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) #define DMA_TCD_CSR_MAJORLINKCH_MASK (0xF00U) #define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) /*! MAJORLINKCH - Major Loop Link Channel Number */ #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) #define DMA_TCD_CSR_BWC_MASK (0xC000U) #define DMA_TCD_CSR_BWC_SHIFT (14U) /*! BWC - Bandwidth Control * 0b00..No eDMA engine stalls * 0b01.. * 0b10..eDMA engine stalls for 4 cycles after each R/W * 0b11..eDMA engine stalls for 8 cycles after each R/W */ #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) /*! @} */ /* The count of DMA_TCD_CSR */ #define DMA_TCD_CSR_COUNT (16U) /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ /*! @{ */ #define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) #define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enables Link * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_BITER_ELINKNO */ #define DMA_TCD_BITER_ELINKNO_COUNT (16U) /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ /*! @{ */ #define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x1E00U) #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Link Channel Number */ #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) #define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable Link * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_BITER_ELINKYES */ #define DMA_TCD_BITER_ELINKYES_COUNT (16U) /*! * @} */ /* end of group DMA_Register_Masks */ /* DMA - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral DMA0 base address */ #define DMA0_BASE (0x50080000u) /** Peripheral DMA0 base address */ #define DMA0_BASE_NS (0x40080000u) /** Peripheral DMA0 base pointer */ #define DMA0 ((DMA_Type *)DMA0_BASE) /** Peripheral DMA0 base pointer */ #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) /** Peripheral DMA1 base address */ #define DMA1_BASE (0x500A0000u) /** Peripheral DMA1 base address */ #define DMA1_BASE_NS (0x400A0000u) /** Peripheral DMA1 base pointer */ #define DMA1 ((DMA_Type *)DMA1_BASE) /** Peripheral DMA1 base pointer */ #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0, DMA1 } /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } #else /** Peripheral DMA0 base address */ #define DMA0_BASE (0x40080000u) /** Peripheral DMA0 base pointer */ #define DMA0 ((DMA_Type *)DMA0_BASE) /** Peripheral DMA1 base address */ #define DMA1_BASE (0x400A0000u) /** Peripheral DMA1 base pointer */ #define DMA1 ((DMA_Type *)DMA1_BASE) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0, DMA1 } #endif /** Interrupt vectors for the DMA peripheral type */ #define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } /*! * @} */ /* end of group DMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer * @{ */ /** EIM - Register Layout Typedef */ typedef struct { __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ uint8_t RESERVED_0[248]; __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ uint8_t RESERVED_1[56]; __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ uint8_t RESERVED_2[56]; __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ uint8_t RESERVED_3[56]; __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */ __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */ uint8_t RESERVED_4[56]; __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */ __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ uint8_t RESERVED_5[56]; __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */ __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ uint8_t RESERVED_6[56]; __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */ __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */ uint8_t RESERVED_7[56]; __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */ __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */ uint8_t RESERVED_8[56]; __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */ __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */ } EIM_Type; /* ---------------------------------------------------------------------------- -- EIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EIM_Register_Masks EIM Register Masks * @{ */ /*! @name EIMCR - Error Injection Module Configuration Register */ /*! @{ */ #define EIM_EIMCR_GEIEN_MASK (0x1U) #define EIM_EIMCR_GEIEN_SHIFT (0U) /*! GEIEN - Global Error Injection Enable * 0b0..Disabled * 0b1..Enabled */ #define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) /*! @} */ /*! @name EICHEN - Error Injection Channel Enable register */ /*! @{ */ #define EIM_EICHEN_EICH8EN_MASK (0x800000U) #define EIM_EICHEN_EICH8EN_SHIFT (23U) /*! EICH8EN - Error Injection Channel 8 Enable * 0b0..Error injection is disabled on Error Injection Channel 8 * 0b1..Error injection is enabled on Error Injection Channel 8 */ #define EIM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH8EN_SHIFT)) & EIM_EICHEN_EICH8EN_MASK) #define EIM_EICHEN_EICH7EN_MASK (0x1000000U) #define EIM_EICHEN_EICH7EN_SHIFT (24U) /*! EICH7EN - Error Injection Channel 7 Enable * 0b0..Error injection is disabled on Error Injection Channel 7 * 0b1..Error injection is enabled on Error Injection Channel 7 */ #define EIM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH7EN_SHIFT)) & EIM_EICHEN_EICH7EN_MASK) #define EIM_EICHEN_EICH6EN_MASK (0x2000000U) #define EIM_EICHEN_EICH6EN_SHIFT (25U) /*! EICH6EN - Error Injection Channel 6 Enable * 0b0..Error injection is disabled on Error Injection Channel 6 * 0b1..Error injection is enabled on Error Injection Channel 6 */ #define EIM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH6EN_SHIFT)) & EIM_EICHEN_EICH6EN_MASK) #define EIM_EICHEN_EICH5EN_MASK (0x4000000U) #define EIM_EICHEN_EICH5EN_SHIFT (26U) /*! EICH5EN - Error Injection Channel 5 Enable * 0b0..Error injection is disabled on Error Injection Channel 5 * 0b1..Error injection is enabled on Error Injection Channel 5 */ #define EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH5EN_SHIFT)) & EIM_EICHEN_EICH5EN_MASK) #define EIM_EICHEN_EICH4EN_MASK (0x8000000U) #define EIM_EICHEN_EICH4EN_SHIFT (27U) /*! EICH4EN - Error Injection Channel 4 Enable * 0b0..Error injection is disabled on Error Injection Channel 4 * 0b1..Error injection is enabled on Error Injection Channel 4 */ #define EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH4EN_SHIFT)) & EIM_EICHEN_EICH4EN_MASK) #define EIM_EICHEN_EICH3EN_MASK (0x10000000U) #define EIM_EICHEN_EICH3EN_SHIFT (28U) /*! EICH3EN - Error Injection Channel 3 Enable * 0b0..Error injection is disabled on Error Injection Channel 3 * 0b1..Error injection is enabled on Error Injection Channel 3 */ #define EIM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH3EN_SHIFT)) & EIM_EICHEN_EICH3EN_MASK) #define EIM_EICHEN_EICH2EN_MASK (0x20000000U) #define EIM_EICHEN_EICH2EN_SHIFT (29U) /*! EICH2EN - Error Injection Channel 2 Enable * 0b0..Error injection is disabled on Error Injection Channel 2 * 0b1..Error injection is enabled on Error Injection Channel 2 */ #define EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH2EN_SHIFT)) & EIM_EICHEN_EICH2EN_MASK) #define EIM_EICHEN_EICH1EN_MASK (0x40000000U) #define EIM_EICHEN_EICH1EN_SHIFT (30U) /*! EICH1EN - Error Injection Channel 1 Enable * 0b0..Error injection is disabled on Error Injection Channel 1 * 0b1..Error injection is enabled on Error Injection Channel 1 */ #define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK) #define EIM_EICHEN_EICH0EN_MASK (0x80000000U) #define EIM_EICHEN_EICH0EN_SHIFT (31U) /*! EICH0EN - Error Injection Channel 0 Enable * 0b0..Error injection is disabled on Error Injection Channel 0 * 0b1..Error injection is enabled on Error Injection Channel 0 */ #define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) /*! @} */ /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ /*! @{ */ #define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ /*! @{ */ #define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ /*! @{ */ #define EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ /*! @{ */ #define EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ /*! @{ */ #define EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ /*! @{ */ #define EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ /*! @{ */ #define EIM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ /*! @{ */ #define EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ /*! @{ */ #define EIM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ /*! @{ */ #define EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ /*! @{ */ #define EIM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ /*! @{ */ #define EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ /*! @{ */ #define EIM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ /*! @{ */ #define EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ /*! @{ */ #define EIM_EICHD7_WORD0_CHKBIT_MASK_MASK (0x80000000U) #define EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (31U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ /*! @{ */ #define EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ /*! @{ */ #define EIM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xF0000000U) #define EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (28U) /*! CHKBIT_MASK - Checkbit Mask */ #define EIM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ /*! @{ */ #define EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define EIM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! * @} */ /* end of group EIM_Register_Masks */ /* EIM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral EIM0 base address */ #define EIM0_BASE (0x5005B000u) /** Peripheral EIM0 base address */ #define EIM0_BASE_NS (0x4005B000u) /** Peripheral EIM0 base pointer */ #define EIM0 ((EIM_Type *)EIM0_BASE) /** Peripheral EIM0 base pointer */ #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) /** Array initializer of EIM peripheral base addresses */ #define EIM_BASE_ADDRS { EIM0_BASE } /** Array initializer of EIM peripheral base pointers */ #define EIM_BASE_PTRS { EIM0 } /** Array initializer of EIM peripheral base addresses */ #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } /** Array initializer of EIM peripheral base pointers */ #define EIM_BASE_PTRS_NS { EIM0_NS } #else /** Peripheral EIM0 base address */ #define EIM0_BASE (0x4005B000u) /** Peripheral EIM0 base pointer */ #define EIM0 ((EIM_Type *)EIM0_BASE) /** Array initializer of EIM peripheral base addresses */ #define EIM_BASE_ADDRS { EIM0_BASE } /** Array initializer of EIM peripheral base pointers */ #define EIM_BASE_PTRS { EIM0 } #endif /*! * @} */ /* end of group EIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EMVSIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer * @{ */ /** EMVSIM - Register Layout Typedef */ typedef struct { __I uint32_t VER_ID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameters, offset: 0x4 */ __IO uint32_t CLKCFG; /**< Clock Configuration, offset: 0x8 */ __IO uint32_t DIVISOR; /**< Baud Rate Divisor, offset: 0xC */ __IO uint32_t CTRL; /**< Control, offset: 0x10 */ __IO uint32_t INT_MASK; /**< Interrupt Mask, offset: 0x14 */ __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ __IO uint32_t TX_THD; /**< Transmitter Threshold, offset: 0x1C */ __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ __IO uint32_t TX_STATUS; /**< Transmitter Status, offset: 0x24 */ __IO uint32_t PCSR; /**< Port Control and Status, offset: 0x28 */ __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */ __O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */ __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value, offset: 0x34 */ __IO uint32_t CWT_VAL; /**< Character Wait Time Value, offset: 0x38 */ __IO uint32_t BWT_VAL; /**< Block Wait Time Value, offset: 0x3C */ __IO uint32_t BGT_VAL; /**< Block Guard Time Value, offset: 0x40 */ __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value, offset: 0x44 */ __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */ } EMVSIM_Type; /* ---------------------------------------------------------------------------- -- EMVSIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks * @{ */ /*! @name VER_ID - Version ID */ /*! @{ */ #define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU) #define EMVSIM_VER_ID_VER_SHIFT (0U) /*! VER - Version ID */ #define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK) /*! @} */ /*! @name PARAM - Parameters */ /*! @{ */ #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU) #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U) /*! RX_FIFO_DEPTH - Receive FIFO Depth */ #define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U) #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U) /*! TX_FIFO_DEPTH - Transmit FIFO Depth */ #define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) /*! @} */ /*! @name CLKCFG - Clock Configuration */ /*! @{ */ #define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU) #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U) /*! CLK_PRSC - Clock Prescaler Value */ #define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK) #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U) #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U) /*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select * 0b00..Disable/reset * 0b01..Card clock * 0b10..Receive clock * 0b11..ETU clock (transmit clock) */ #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U) #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U) /*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select * 0b00..Disable/reset * 0b01..Card clock * 0b10..Receive clock * 0b11..ETU clock (transmit clock) */ #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) /*! @} */ /*! @name DIVISOR - Baud Rate Divisor */ /*! @{ */ #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU) #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U) /*! DIVISOR_VALUE - Divisor (F/D) Value * 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, the minimum value of F/D is 5. * 0b000000101-0b011111111..Divisor value F/D */ #define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) /*! @} */ /*! @name CTRL - Control */ /*! @{ */ #define EMVSIM_CTRL_IC_MASK (0x1U) #define EMVSIM_CTRL_IC_SHIFT (0U) /*! IC - Inverse Convention * 0b0..Direct * 0b1..Inverse */ #define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK) #define EMVSIM_CTRL_ICM_MASK (0x2U) #define EMVSIM_CTRL_ICM_SHIFT (1U) /*! ICM - Initial Character Mode * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK) #define EMVSIM_CTRL_ANACK_MASK (0x4U) #define EMVSIM_CTRL_ANACK_SHIFT (2U) /*! ANACK - Auto NACK Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK) #define EMVSIM_CTRL_ONACK_MASK (0x8U) #define EMVSIM_CTRL_ONACK_SHIFT (3U) /*! ONACK - Overrun NACK Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK) #define EMVSIM_CTRL_FLSH_RX_MASK (0x100U) #define EMVSIM_CTRL_FLSH_RX_SHIFT (8U) /*! FLSH_RX - Flush Receiver * 0b0..Normal * 0b1..Reset */ #define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK) #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) #define EMVSIM_CTRL_FLSH_TX_SHIFT (9U) /*! FLSH_TX - Flush Transmitter * 0b0..Normal * 0b1..Reset */ #define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK) #define EMVSIM_CTRL_SW_RST_MASK (0x400U) #define EMVSIM_CTRL_SW_RST_SHIFT (10U) /*! SW_RST - Software Reset * 0b0..Normal * 0b1..Reset */ #define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK) #define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U) #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U) /*! KILL_CLOCKS - Kill Internal Clocks * 0b0..Enable * 0b1..Disable */ #define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK) #define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U) #define EMVSIM_CTRL_DOZE_EN_SHIFT (12U) /*! DOZE_EN - Doze Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK) #define EMVSIM_CTRL_STOP_EN_MASK (0x2000U) #define EMVSIM_CTRL_STOP_EN_SHIFT (13U) /*! STOP_EN - STOP Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK) #define EMVSIM_CTRL_RCV_EN_MASK (0x10000U) #define EMVSIM_CTRL_RCV_EN_SHIFT (16U) /*! RCV_EN - Receiver Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK) #define EMVSIM_CTRL_XMT_EN_MASK (0x20000U) #define EMVSIM_CTRL_XMT_EN_SHIFT (17U) /*! XMT_EN - Transmitter Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK) #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) #define EMVSIM_CTRL_RCVR_11_SHIFT (18U) /*! RCVR_11 - Receiver 11 ETU Mode Enable * 0b0..12 ETU operation * 0b1..11 ETU operation */ #define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK) #define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U) #define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U) /*! RX_DMA_EN - Receive DMA Enable * 0b0..Not asserted * 0b1..Asserted */ #define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK) #define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U) #define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U) /*! TX_DMA_EN - Transmit DMA Enable * 0b0..Not asserted * 0b1..Asserted */ #define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK) #define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U) #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U) /*! INV_CRC_VAL - Invert CRC Output Value Bits * 0b0..Not inverted * 0b1..Inverted */ #define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK) #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U) #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U) /*! CRC_OUT_FLIP - CRC Output Value Bit Reversal Or Flip Control * 0b0..Not reversed * 0b1..Reversed */ #define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK) #define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U) #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U) /*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal Or Flip Control * 0b0..Not reversed * 0b1..Reversed */ #define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK) #define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U) #define EMVSIM_CTRL_CWT_EN_SHIFT (27U) /*! CWT_EN - CWT Counter Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK) #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) #define EMVSIM_CTRL_LRC_EN_SHIFT (28U) /*! LRC_EN - LRC Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK) #define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U) #define EMVSIM_CTRL_CRC_EN_SHIFT (29U) /*! CRC_EN - CRC Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK) #define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U) #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U) /*! XMT_CRC_LRC - Transmit CRC or LRC Enable * 0b0..Do not transmit * 0b1..Transmit */ #define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK) #define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U) #define EMVSIM_CTRL_BWT_EN_SHIFT (31U) /*! BWT_EN - Block Wait Time Counter Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK) /*! @} */ /*! @name INT_MASK - Interrupt Mask */ /*! @{ */ #define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U) #define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U) /*! RDT_IM - Receive Data Threshold Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK) #define EMVSIM_INT_MASK_TC_IM_MASK (0x2U) #define EMVSIM_INT_MASK_TC_IM_SHIFT (1U) /*! TC_IM - Transmit Complete Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK) #define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U) #define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U) /*! RFO_IM - Receive FIFO Overflow Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK) #define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U) #define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U) /*! ETC_IM - Early Transmit Complete Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK) #define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U) #define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U) /*! TFE_IM - Transmit FIFO Empty Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK) #define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U) #define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U) /*! TNACK_IM - Transmit NACK Threshold Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK) #define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U) #define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U) /*! TFF_IM - Transmit FIFO Full Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK) #define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U) #define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U) /*! TDT_IM - Transmit Data Threshold Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK) #define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U) #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U) /*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK) #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U) /*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK) #define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U) #define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U) /*! RNACK_IM - Receiver NACK Threshold Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK) #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U) #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U) /*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK) #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U) #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U) /*! BGT_ERR_IM - Block Guard Time Error Interrupt * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK) #define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U) #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U) /*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK) #define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U) #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U) /*! RX_DATA_IM - Receive Data Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK) #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) #define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U) /*! PEF_IM - Parity Error Interrupt Mask * 0b0..Enable * 0b1..Masked */ #define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK) /*! @} */ /*! @name RX_THD - Receiver Threshold */ /*! @{ */ #define EMVSIM_RX_THD_RDT_MASK (0xFU) #define EMVSIM_RX_THD_RDT_SHIFT (0U) /*! RDT - Receiver Data Threshold Value */ #define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK) #define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U) #define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U) /*! RNCK_THD - Receiver NACK Threshold Value */ #define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK) /*! @} */ /*! @name TX_THD - Transmitter Threshold */ /*! @{ */ #define EMVSIM_TX_THD_TDT_MASK (0xFU) #define EMVSIM_TX_THD_TDT_SHIFT (0U) /*! TDT - Transmitter Data Threshold Value */ #define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK) #define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U) #define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U) /*! TNCK_THD - Transmitter NACK Threshold Value */ #define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK) /*! @} */ /*! @name RX_STATUS - Receive Status */ /*! @{ */ #define EMVSIM_RX_STATUS_RFO_MASK (0x1U) #define EMVSIM_RX_STATUS_RFO_SHIFT (0U) /*! RFO - Receive FIFO Overflow Flag * 0b0..No overrun error * 0b1..Overrun error */ #define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK) #define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U) #define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U) /*! RX_DATA - Receive Data Interrupt Flag * 0b0..No new byte * 0b1..New byte */ #define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK) #define EMVSIM_RX_STATUS_RDTF_MASK (0x20U) #define EMVSIM_RX_STATUS_RDTF_SHIFT (5U) /*! RDTF - Receive Data Threshold Interrupt Flag * 0b0..Less than threshold * 0b1..Greater than or equal to threshold */ #define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK) #define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U) #define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U) /*! LRC_OK - LRC Check OK Flag * 0b0..No match * 0b1..Match */ #define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK) #define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U) #define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U) /*! CRC_OK - CRC Check OK Flag * 0b0..Current CRC value does not match remainder. * 0b1..Current calculated CRC value matches the expected result. */ #define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK) #define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U) #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U) /*! CWT_ERR - Character Wait Time Error Flag * 0b0..No CWT violation * 0b1..CWT violation */ #define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK) #define EMVSIM_RX_STATUS_RTE_MASK (0x200U) #define EMVSIM_RX_STATUS_RTE_SHIFT (9U) /*! RTE - Received NACK Threshold Error Flag * 0b0..Less than * 0b1..Equal to */ #define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK) #define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U) #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U) /*! BWT_ERR - Block Wait Time Error Flag * 0b0..Not exceeded * 0b1..Exceeded */ #define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK) #define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U) #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U) /*! BGT_ERR - Block Guard Time Error Flag * 0b0..Sufficient * 0b1..Too small */ #define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK) #define EMVSIM_RX_STATUS_PEF_MASK (0x1000U) #define EMVSIM_RX_STATUS_PEF_SHIFT (12U) /*! PEF - Parity Error Flag * 0b0..No error * 0b1..Error */ #define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK) #define EMVSIM_RX_STATUS_FEF_MASK (0x2000U) #define EMVSIM_RX_STATUS_FEF_SHIFT (13U) /*! FEF - Frame Error Flag * 0b0..No error * 0b1..Error */ #define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK) #define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U) #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U) /*! RX_WPTR - Receive FIFO Write Pointer Value */ #define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK) #define EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U) #define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U) /*! RX_CNT - Receive FIFO Byte Count * 0b0000..FIFO empty */ #define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK) /*! @} */ /*! @name TX_STATUS - Transmitter Status */ /*! @{ */ #define EMVSIM_TX_STATUS_TNTE_MASK (0x1U) #define EMVSIM_TX_STATUS_TNTE_SHIFT (0U) /*! TNTE - Transmit NACK Threshold Error Flag * 0b0..Threshold not reached * 0b1..Threshold reached */ #define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK) #define EMVSIM_TX_STATUS_TFE_MASK (0x8U) #define EMVSIM_TX_STATUS_TFE_SHIFT (3U) /*! TFE - Transmit FIFO Empty Flag * 0b0..Not empty * 0b1..Empty */ #define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK) #define EMVSIM_TX_STATUS_ETCF_MASK (0x10U) #define EMVSIM_TX_STATUS_ETCF_SHIFT (4U) /*! ETCF - Early Transmit Complete Flag * 0b0..Pending or incomplete * 0b1..Complete */ #define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK) #define EMVSIM_TX_STATUS_TCF_MASK (0x20U) #define EMVSIM_TX_STATUS_TCF_SHIFT (5U) /*! TCF - Transmit Complete Flag * 0b0..Pending or incomplete * 0b1..Complete */ #define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK) #define EMVSIM_TX_STATUS_TFF_MASK (0x40U) #define EMVSIM_TX_STATUS_TFF_SHIFT (6U) /*! TFF - Transmit FIFO Full Flag * 0b0..Not full * 0b1..Full */ #define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK) #define EMVSIM_TX_STATUS_TDTF_MASK (0x80U) #define EMVSIM_TX_STATUS_TDTF_SHIFT (7U) /*! TDTF - Transmit Data Threshold Flag * 0b0..Threshold exceeded or this field written to 0 * 0b1..Threshold not exceeded */ #define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK) #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U) #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U) /*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag * 0b0..GPCNT0 not reached, or flag cleared * 0b1..GPCNT0 reached */ #define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK) #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U) #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U) /*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag * 0b0..GPCNT1 not reached, or flag cleared * 0b1..GPCNT1 reached */ #define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) #define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U) #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U) /*! TX_RPTR - Transmit FIFO Read Pointer */ #define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK) #define EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U) #define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U) /*! TX_CNT - Transmit FIFO Byte Count * 0b0000..FIFO empty */ #define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK) /*! @} */ /*! @name PCSR - Port Control and Status */ /*! @{ */ #define EMVSIM_PCSR_SAPD_MASK (0x1U) #define EMVSIM_PCSR_SAPD_SHIFT (0U) /*! SAPD - Auto Power Down Enable * 0b0..Disable * 0b1..Enable */ #define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK) #define EMVSIM_PCSR_SVCC_EN_MASK (0x2U) #define EMVSIM_PCSR_SVCC_EN_SHIFT (1U) /*! SVCC_EN - Vcc Enable for Smart Card * 0b0..Disable * 0b1..Enable */ #define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK) #define EMVSIM_PCSR_VCCENP_MASK (0x4U) #define EMVSIM_PCSR_VCCENP_SHIFT (2U) /*! VCCENP - VCC Enable Polarity Control * 0b0..Active high * 0b1..Active low */ #define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK) #define EMVSIM_PCSR_SRST_MASK (0x8U) #define EMVSIM_PCSR_SRST_SHIFT (3U) /*! SRST - Reset Smart Card * 0b0..Assert * 0b1..Deassert */ #define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK) #define EMVSIM_PCSR_SCEN_MASK (0x10U) #define EMVSIM_PCSR_SCEN_SHIFT (4U) /*! SCEN - Clock Enable for Smart Card * 0b0..Disable * 0b1..Enable */ #define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK) #define EMVSIM_PCSR_SCSP_MASK (0x20U) #define EMVSIM_PCSR_SCSP_SHIFT (5U) /*! SCSP - Smart Card Clock Stop Polarity * 0b0..Logic 0 * 0b1..Logic 1 */ #define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK) #define EMVSIM_PCSR_SPD_MASK (0x80U) #define EMVSIM_PCSR_SPD_SHIFT (7U) /*! SPD - Auto Power-Down Control * 0b0..No * 0b1..Yes */ #define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK) #define EMVSIM_PCSR_SPDIM_MASK (0x1000000U) #define EMVSIM_PCSR_SPDIM_SHIFT (24U) /*! SPDIM - Smart Card Presence Detect Interrupt Mask * 0b0..Enable * 0b1..Mask */ #define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK) #define EMVSIM_PCSR_SPDIF_MASK (0x2000000U) #define EMVSIM_PCSR_SPDIF_SHIFT (25U) /*! SPDIF - Smart Card Presence Detect Interrupt Flag * 0b0..No insertion or removal * 0b1..Insertion or removal */ #define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK) #define EMVSIM_PCSR_SPDP_MASK (0x4000000U) #define EMVSIM_PCSR_SPDP_SHIFT (26U) /*! SPDP - Smart Card Presence Detect Pin Status * 0b0..Logic low * 0b1..Logic high */ #define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK) #define EMVSIM_PCSR_SPDES_MASK (0x8000000U) #define EMVSIM_PCSR_SPDES_SHIFT (27U) /*! SPDES - SIM Presence Detect Edge Select * 0b0..Falling edge * 0b1..Rising edge */ #define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK) /*! @} */ /*! @name RX_BUF - Receive Data Read Buffer */ /*! @{ */ #define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU) #define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U) /*! RX_BYTE - Receive Data Byte Read */ #define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK) /*! @} */ /*! @name TX_BUF - Transmit Data Buffer */ /*! @{ */ #define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU) #define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U) /*! TX_BYTE - Transmit Data Byte */ #define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK) /*! @} */ /*! @name TX_GETU - Transmitter Guard ETU Value */ /*! @{ */ #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) #define EMVSIM_TX_GETU_GETU_SHIFT (0U) /*! GETU - Transmitter Guard Time Value in ETU */ #define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK) /*! @} */ /*! @name CWT_VAL - Character Wait Time Value */ /*! @{ */ #define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU) #define EMVSIM_CWT_VAL_CWT_SHIFT (0U) /*! CWT - Character Wait Time Value */ #define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK) /*! @} */ /*! @name BWT_VAL - Block Wait Time Value */ /*! @{ */ #define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU) #define EMVSIM_BWT_VAL_BWT_SHIFT (0U) /*! BWT - Block Wait Time Value */ #define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK) /*! @} */ /*! @name BGT_VAL - Block Guard Time Value */ /*! @{ */ #define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU) #define EMVSIM_BGT_VAL_BGT_SHIFT (0U) /*! BGT - Block Guard Time Value */ #define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK) /*! @} */ /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value */ /*! @{ */ #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU) #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U) /*! GPCNT0 - General Purpose Counter 0 Timeout Value */ #define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK) /*! @} */ /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */ /*! @{ */ #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U) /*! GPCNT1 - General Purpose Counter 1 Timeout Value */ #define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK) /*! @} */ /*! * @} */ /* end of group EMVSIM_Register_Masks */ /* EMVSIM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral EMVSIM0 base address */ #define EMVSIM0_BASE (0x50103000u) /** Peripheral EMVSIM0 base address */ #define EMVSIM0_BASE_NS (0x40103000u) /** Peripheral EMVSIM0 base pointer */ #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) /** Peripheral EMVSIM0 base pointer */ #define EMVSIM0_NS ((EMVSIM_Type *)EMVSIM0_BASE_NS) /** Peripheral EMVSIM1 base address */ #define EMVSIM1_BASE (0x50104000u) /** Peripheral EMVSIM1 base address */ #define EMVSIM1_BASE_NS (0x40104000u) /** Peripheral EMVSIM1 base pointer */ #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) /** Peripheral EMVSIM1 base pointer */ #define EMVSIM1_NS ((EMVSIM_Type *)EMVSIM1_BASE_NS) /** Array initializer of EMVSIM peripheral base addresses */ #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } /** Array initializer of EMVSIM peripheral base pointers */ #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } /** Array initializer of EMVSIM peripheral base addresses */ #define EMVSIM_BASE_ADDRS_NS { EMVSIM0_BASE_NS, EMVSIM1_BASE_NS } /** Array initializer of EMVSIM peripheral base pointers */ #define EMVSIM_BASE_PTRS_NS { EMVSIM0_NS, EMVSIM1_NS } #else /** Peripheral EMVSIM0 base address */ #define EMVSIM0_BASE (0x40103000u) /** Peripheral EMVSIM0 base pointer */ #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) /** Peripheral EMVSIM1 base address */ #define EMVSIM1_BASE (0x40104000u) /** Peripheral EMVSIM1 base pointer */ #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) /** Array initializer of EMVSIM peripheral base addresses */ #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } /** Array initializer of EMVSIM peripheral base pointers */ #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } #endif /** Interrupt vectors for the EMVSIM peripheral type */ #define EMVSIM_IRQS { EMVSIM0_IRQn, EMVSIM1_IRQn } /*! * @} */ /* end of group EMVSIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer * @{ */ /** ENET - Register Layout Typedef */ typedef struct { __IO uint32_t MAC_CONFIGURATION; /**< MAC Configuration, offset: 0x0 */ __IO uint32_t MAC_EXT_CONFIGURATION; /**< MAC Extended Configuration Register, offset: 0x4 */ __IO uint32_t MAC_PACKET_FILTER; /**< MAC Packet Filter, offset: 0x8 */ __IO uint32_t MAC_WATCHDOG_TIMEOUT; /**< Watchdog Timeout, offset: 0xC */ uint8_t RESERVED_0[64]; __IO uint32_t MAC_VLAN_TAG_CTRL; /**< MAC VLAN Tag Control, offset: 0x50 */ uint8_t RESERVED_1[12]; __IO uint32_t MAC_VLAN_INCL; /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */ __IO uint32_t MAC_INNER_VLAN_INCL; /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */ uint8_t RESERVED_2[8]; __IO uint32_t MAC_TX_FLOW_CTRL_Q[1]; /**< MAC Q0 Tx Flow Control, array offset: 0x70, array step: 0x4 */ uint8_t RESERVED_3[28]; __IO uint32_t MAC_RX_FLOW_CTRL; /**< MAC Rx Flow Control, offset: 0x90 */ __IO uint32_t MAC_RXQ_CTRL4; /**< Receive Queue Control 4, offset: 0x94 */ uint8_t RESERVED_4[8]; __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0..Receive Queue Control 2, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_5[4]; __I uint32_t MAC_INTERRUPT_STATUS; /**< Interrupt Status, offset: 0xB0 */ __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ __I uint32_t MAC_RX_TX_STATUS; /**< Receive Transmit Status, offset: 0xB8 */ uint8_t RESERVED_6[4]; __IO uint32_t MAC_PMT_CONTROL_STATUS; /**< PMT Control and Status, offset: 0xC0 */ __IO uint32_t MAC_RWK_PACKET_FILTER; /**< Remote Wakeup Filter, offset: 0xC4 */ uint8_t RESERVED_7[8]; __IO uint32_t MAC_LPI_CONTROL_STATUS; /**< LPI Control and Status, offset: 0xD0 */ __IO uint32_t MAC_LPI_TIMERS_CONTROL; /**< LPI Timers Control, offset: 0xD4 */ __IO uint32_t MAC_LPI_ENTRY_TIMER; /**< Tx LPI Entry Timer Control, offset: 0xD8 */ __IO uint32_t MAC_ONEUS_TIC_COUNTER; /**< One-microsecond Reference Timer, offset: 0xDC */ uint8_t RESERVED_8[48]; __I uint32_t MAC_VERSION; /**< MAC Version, offset: 0x110 */ __I uint32_t MAC_DEBUG; /**< MAC Debug, offset: 0x114 */ uint8_t RESERVED_9[4]; __I uint32_t MAC_HW_FEAT[4]; /**< Hardware Features 0..Hardware Features 3, array offset: 0x11C, array step: 0x4 */ uint8_t RESERVED_10[212]; __IO uint32_t MAC_MDIO_ADDRESS; /**< MDIO Address, offset: 0x200 */ __IO uint32_t MAC_MDIO_DATA; /**< MAC MDIO Data, offset: 0x204 */ uint8_t RESERVED_11[40]; __IO uint32_t MAC_CSR_SW_CTRL; /**< CSR Software Control, offset: 0x230 */ uint8_t RESERVED_12[204]; __IO uint32_t MAC_ADDRESS0_HIGH; /**< MAC Address0 High, offset: 0x300 */ __IO uint32_t MAC_ADDRESS0_LOW; /**< MAC Address0 Low, offset: 0x304 */ uint8_t RESERVED_13[1896]; __IO uint32_t INDIR_ACCESS_CTRL; /**< Indirect Access Control, offset: 0xA70 */ __IO uint32_t INDIR_ACCESS_DATA; /**< Indirect Access Data, offset: 0xA74 */ uint8_t RESERVED_14[136]; __IO uint32_t MAC_TIMESTAMP_CONTROL; /**< Timestamp Control, offset: 0xB00 */ __IO uint32_t MAC_SUB_SECOND_INCREMENT; /**< Subsecond Increment, offset: 0xB04 */ __I uint32_t MAC_SYSTEM_TIME_SECONDS; /**< System Time Seconds, offset: 0xB08 */ __I uint32_t MAC_SYSTEM_TIME_NANOSECONDS; /**< System Time Nanoseconds, offset: 0xB0C */ __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE; /**< System Time Seconds Update, offset: 0xB10 */ __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */ __IO uint32_t MAC_TIMESTAMP_ADDEND; /**< Timestamp Addend, offset: 0xB18 */ uint8_t RESERVED_15[4]; __I uint32_t MAC_TIMESTAMP_STATUS; /**< Timestamp Status, offset: 0xB20 */ uint8_t RESERVED_16[12]; __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */ __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Transmit Timestamp Status Seconds, offset: 0xB34 */ uint8_t RESERVED_17[32]; __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */ __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */ uint8_t RESERVED_18[8]; __I uint32_t MAC_TIMESTAMP_INGRESS_LATENCY; /**< Timestamp Ingress Latency, offset: 0xB68 */ __I uint32_t MAC_TIMESTAMP_EGRESS_LATENCY; /**< Timestamp Egress Latency, offset: 0xB6C */ __IO uint32_t MAC_PPS_CONTROL; /**< PPS Control, offset: 0xB70 */ uint8_t RESERVED_19[12]; __IO uint32_t PPS0_TARGET_TIME_SECONDS; /**< PPS0 Target Time Seconds, offset: 0xB80 */ __IO uint32_t PPS0_TARGET_TIME_NANOSECONDS; /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */ uint8_t RESERVED_20[120]; __IO uint32_t MTL_OPERATION_MODE; /**< MTL Operation Mode, offset: 0xC00 */ uint8_t RESERVED_21[28]; __I uint32_t MTL_INTERRUPT_STATUS; /**< MTL Interrupt Status, offset: 0xC20 */ uint8_t RESERVED_22[12]; __IO uint32_t MTL_RXQ_DMA_MAP0; /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */ uint8_t RESERVED_23[204]; struct { /* offset: 0xD00, array step: 0x40 */ __IO uint32_t MTL_TXQX_OP_MODE; /**< Queue 0 Transmit Operation Mode..Queue 1 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */ __I uint32_t MTL_TXQX_UNDRFLW; /**< Queue 0 Underflow Counter..Queue 1 Underflow Counter, array offset: 0xD04, array step: 0x40 */ __I uint32_t MTL_TXQX_DBG; /**< Queue 0 Transmit Debug..Queue 1 Transmit Debug, array offset: 0xD08, array step: 0x40 */ uint8_t RESERVED_0[4]; __IO uint32_t MTL_TXQX_ETS_CTRL; /**< Queue 1 ETS Control, array offset: 0xD10, array step: 0x40, valid indices: [1] */ __I uint32_t MTL_TXQX_ETS_STAT; /**< Queue 0 ETS Status..Queue 1 ETS Status, array offset: 0xD14, array step: 0x40 */ __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< Queue 0 Quantum or Weights..Queue 1 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */ __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< Queue 1 sendSlopeCredit, array offset: 0xD1C, array step: 0x40, valid indices: [1] */ __IO uint32_t MTL_TXQX_HI_CRDT; /**< Queue 1 hiCredit, array offset: 0xD20, array step: 0x40, valid indices: [1] */ __IO uint32_t MTL_TXQX_LO_CRDT; /**< Queue 1 loCredit, array offset: 0xD24, array step: 0x40, valid indices: [1] */ uint8_t RESERVED_1[4]; __IO uint32_t MTL_QX_INTCTRL_STAT; /**< Queue 0 Interrupt Control Status..Queue 1 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */ __IO uint32_t MTL_RXQX_OP_MODE; /**< Queue 0 Receive Operation Mode..Queue 1 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */ __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< Queue 0 Missed Packet and Overflow Counter..Queue 1 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */ __I uint32_t MTL_RXQX_DBG; /**< Queue 0 Receive Debug..Queue 1 Receive Debug, array offset: 0xD38, array step: 0x40 */ __IO uint32_t MTL_RXQX_CTRL; /**< Queue 0 Receive Control..Queue 1 Receive Control, array offset: 0xD3C, array step: 0x40 */ } MTL_QUEUE[2]; uint8_t RESERVED_24[640]; __IO uint32_t DMA_MODE; /**< DMA Bus Mode, offset: 0x1000 */ __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus Mode, offset: 0x1004 */ __I uint32_t DMA_INTERRUPT_STATUS; /**< DMA Interrupt Status, offset: 0x1008 */ __I uint32_t DMA_DEBUG_STATUS0; /**< DMA Debug Status 0, offset: 0x100C */ uint8_t RESERVED_25[240]; struct { /* offset: 0x1100, array step: 0x80 */ __IO uint32_t DMA_CHX_CTRL; /**< DMA Channel 0 Control..DMA Channel 1 Control, array offset: 0x1100, array step: 0x80 */ __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channel 0 Transmit Control..DMA Channel 1 Transmit Control, array offset: 0x1104, array step: 0x80 */ __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channel 0 Receive Control..DMA Channel 1 Receive Control, array offset: 0x1108, array step: 0x80 */ uint8_t RESERVED_0[8]; __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< Channel 0 Tx Descriptor List Address register..Channel 1 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */ uint8_t RESERVED_1[4]; __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< Channel 0 Rx Descriptor List Address register..Channel 1 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */ __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< Channel 0 Tx Descriptor Tail Pointer..Channel 1 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */ uint8_t RESERVED_2[4]; __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< Channel 0 Rx Descriptor Tail Pointer..Channel 1 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */ __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< Channel 0 Tx Descriptor Ring Length..Channel 1 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */ __IO uint32_t DMA_CHX_RX_CONTROL2; /**< Channeli Receive Control..DMA Channel 1 Receive Control, array offset: 0x1130, array step: 0x80 */ __IO uint32_t DMA_CHX_INT_EN; /**< Channeli Interrupt Enable..Channel 1 Interrupt Enable, array offset: 0x1134, array step: 0x80 */ __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 1 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Channel 0 Slot Function Control and Status..Channel 1 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ uint8_t RESERVED_3[4]; __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channel 0 Current Application Transmit Descriptor..Channel 1 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */ uint8_t RESERVED_4[4]; __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< Channel 0 Current Application Receive Descriptor..Channel 1 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */ uint8_t RESERVED_5[4]; __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< Channel 0 Current Application Transmit Buffer Address..Channel 1 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */ uint8_t RESERVED_6[4]; __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channel 0 Current Application Receive Buffer Address..Channel 1 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */ __IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, array offset: 0x1160, array step: 0x80 */ __I uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channel 0 Missed Frame Counter..Channel 1 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */ uint8_t RESERVED_7[4]; __I uint32_t DMA_CHX_RX_ERI_CNT; /**< Channel 0 Receive ERI Counter..Channel 1 Receive ERI Counter, array offset: 0x116C, array step: 0x80 */ uint8_t RESERVED_8[16]; } DMA_CH[2]; } ENET_Type; /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /*! @name MAC_CONFIGURATION - MAC Configuration */ /*! @{ */ #define ENET_MAC_CONFIGURATION_RE_MASK (0x1U) #define ENET_MAC_CONFIGURATION_RE_SHIFT (0U) /*! RE - Receiver Enable * 0b0..Receiver is disabled * 0b1..Receiver is enabled */ #define ENET_MAC_CONFIGURATION_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_RE_SHIFT)) & ENET_MAC_CONFIGURATION_RE_MASK) #define ENET_MAC_CONFIGURATION_TE_MASK (0x2U) #define ENET_MAC_CONFIGURATION_TE_SHIFT (1U) /*! TE - Transmitter Enable * 0b0..Transmitter is disabled * 0b1..Transmitter is enabled */ #define ENET_MAC_CONFIGURATION_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_TE_SHIFT)) & ENET_MAC_CONFIGURATION_TE_MASK) #define ENET_MAC_CONFIGURATION_PRELEN_MASK (0xCU) #define ENET_MAC_CONFIGURATION_PRELEN_SHIFT (2U) /*! PRELEN - Preamble Length for Transmit packets * 0b10..3 bytes of preamble * 0b01..5 bytes of preamble * 0b00..7 bytes of preamble * 0b11..Reserved */ #define ENET_MAC_CONFIGURATION_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_MAC_CONFIGURATION_PRELEN_MASK) #define ENET_MAC_CONFIGURATION_DC_MASK (0x10U) #define ENET_MAC_CONFIGURATION_DC_SHIFT (4U) /*! DC - Deferral Check * 0b0..Deferral check function is disabled * 0b1..Deferral check function is enabled */ #define ENET_MAC_CONFIGURATION_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DC_SHIFT)) & ENET_MAC_CONFIGURATION_DC_MASK) #define ENET_MAC_CONFIGURATION_BL_MASK (0x60U) #define ENET_MAC_CONFIGURATION_BL_SHIFT (5U) /*! BL - Back-Off Limit * 0b11..k = min(n,1) * 0b00..k = min(n,10) * 0b10..k = min(n,4) * 0b01..k = min(n,8) */ #define ENET_MAC_CONFIGURATION_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_BL_SHIFT)) & ENET_MAC_CONFIGURATION_BL_MASK) #define ENET_MAC_CONFIGURATION_DR_MASK (0x100U) #define ENET_MAC_CONFIGURATION_DR_SHIFT (8U) /*! DR - Disable Retry * 0b1..Disable Retry * 0b0..Enable Retry */ #define ENET_MAC_CONFIGURATION_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DR_SHIFT)) & ENET_MAC_CONFIGURATION_DR_MASK) #define ENET_MAC_CONFIGURATION_DCRS_MASK (0x200U) #define ENET_MAC_CONFIGURATION_DCRS_SHIFT (9U) /*! DCRS - Disable Carrier Sense During Transmission * 0b1..Disable Carrier Sense During Transmission * 0b0..Enable Carrier Sense During Transmission */ #define ENET_MAC_CONFIGURATION_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_MAC_CONFIGURATION_DCRS_MASK) #define ENET_MAC_CONFIGURATION_DO_MASK (0x400U) #define ENET_MAC_CONFIGURATION_DO_SHIFT (10U) /*! DO - Disable Receive Own * 0b1..Disable Receive Own * 0b0..Enable Receive Own */ #define ENET_MAC_CONFIGURATION_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DO_SHIFT)) & ENET_MAC_CONFIGURATION_DO_MASK) #define ENET_MAC_CONFIGURATION_ECRSFD_MASK (0x800U) #define ENET_MAC_CONFIGURATION_ECRSFD_SHIFT (11U) /*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode * 0b0..ECRSFD is disabled * 0b1..ECRSFD is enabled */ #define ENET_MAC_CONFIGURATION_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_MAC_CONFIGURATION_ECRSFD_MASK) #define ENET_MAC_CONFIGURATION_LM_MASK (0x1000U) #define ENET_MAC_CONFIGURATION_LM_SHIFT (12U) /*! LM - Loopback Mode * 0b0..Loopback is disabled * 0b1..Loopback is enabled */ #define ENET_MAC_CONFIGURATION_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_LM_SHIFT)) & ENET_MAC_CONFIGURATION_LM_MASK) #define ENET_MAC_CONFIGURATION_DM_MASK (0x2000U) #define ENET_MAC_CONFIGURATION_DM_SHIFT (13U) /*! DM - Duplex Mode * 0b1..Full-duplex mode * 0b0..Half-duplex mode */ #define ENET_MAC_CONFIGURATION_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_DM_SHIFT)) & ENET_MAC_CONFIGURATION_DM_MASK) #define ENET_MAC_CONFIGURATION_FES_MASK (0x4000U) #define ENET_MAC_CONFIGURATION_FES_SHIFT (14U) /*! FES - Speed * 0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 * 0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0 */ #define ENET_MAC_CONFIGURATION_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_FES_SHIFT)) & ENET_MAC_CONFIGURATION_FES_MASK) #define ENET_MAC_CONFIGURATION_PS_MASK (0x8000U) #define ENET_MAC_CONFIGURATION_PS_SHIFT (15U) /*! PS - Port Select * 0b0..For 1000 or 2500 Mbps operations * 0b1..For 10 or 100 Mbps operations */ #define ENET_MAC_CONFIGURATION_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_PS_SHIFT)) & ENET_MAC_CONFIGURATION_PS_MASK) #define ENET_MAC_CONFIGURATION_JE_MASK (0x10000U) #define ENET_MAC_CONFIGURATION_JE_SHIFT (16U) /*! JE - Jumbo Packet Enable * 0b0..Jumbo packet is disabled * 0b1..Jumbo packet is enabled */ #define ENET_MAC_CONFIGURATION_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_JE_SHIFT)) & ENET_MAC_CONFIGURATION_JE_MASK) #define ENET_MAC_CONFIGURATION_JD_MASK (0x20000U) #define ENET_MAC_CONFIGURATION_JD_SHIFT (17U) /*! JD - Jabber Disable * 0b1..Jabber is disabled * 0b0..Jabber is enabled */ #define ENET_MAC_CONFIGURATION_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_JD_SHIFT)) & ENET_MAC_CONFIGURATION_JD_MASK) #define ENET_MAC_CONFIGURATION_WD_MASK (0x80000U) #define ENET_MAC_CONFIGURATION_WD_SHIFT (19U) /*! WD - Watchdog Disable * 0b1..Watchdog is disabled * 0b0..Watchdog is enabled */ #define ENET_MAC_CONFIGURATION_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_WD_SHIFT)) & ENET_MAC_CONFIGURATION_WD_MASK) #define ENET_MAC_CONFIGURATION_ACS_MASK (0x100000U) #define ENET_MAC_CONFIGURATION_ACS_SHIFT (20U) /*! ACS - Automatic Pad or CRC Stripping * 0b0..Automatic Pad or CRC Stripping is disabled * 0b1..Automatic Pad or CRC Stripping is enabled */ #define ENET_MAC_CONFIGURATION_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_MAC_CONFIGURATION_ACS_MASK) #define ENET_MAC_CONFIGURATION_CST_MASK (0x200000U) #define ENET_MAC_CONFIGURATION_CST_SHIFT (21U) /*! CST - CRC stripping for Type packets * 0b0..CRC stripping for Type packets is disabled * 0b1..CRC stripping for Type packets is enabled */ #define ENET_MAC_CONFIGURATION_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_CST_SHIFT)) & ENET_MAC_CONFIGURATION_CST_MASK) #define ENET_MAC_CONFIGURATION_S2KP_MASK (0x400000U) #define ENET_MAC_CONFIGURATION_S2KP_SHIFT (22U) /*! S2KP - IEEE 802.3as Support for 2K Packets * 0b0..Support upto 2K packet is disabled * 0b1..Support upto 2K packet is Enabled */ #define ENET_MAC_CONFIGURATION_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_MAC_CONFIGURATION_S2KP_MASK) #define ENET_MAC_CONFIGURATION_GPSLCE_MASK (0x800000U) #define ENET_MAC_CONFIGURATION_GPSLCE_SHIFT (23U) /*! GPSLCE - Giant Packet Size Limit Control Enable * 0b0..Giant Packet Size Limit Control is disabled * 0b1..Giant Packet Size Limit Control is enabled */ #define ENET_MAC_CONFIGURATION_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_MAC_CONFIGURATION_GPSLCE_MASK) #define ENET_MAC_CONFIGURATION_IPG_MASK (0x7000000U) #define ENET_MAC_CONFIGURATION_IPG_SHIFT (24U) /*! IPG - Inter-Packet Gap * 0b111..40 bit times IPG * 0b110..48 bit times IPG * 0b101..56 bit times IPG * 0b100..64 bit times IPG * 0b011..72 bit times IPG * 0b010..80 bit times IPG * 0b001..88 bit times IPG * 0b000..96 bit times IPG */ #define ENET_MAC_CONFIGURATION_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_MAC_CONFIGURATION_IPG_MASK) #define ENET_MAC_CONFIGURATION_IPC_MASK (0x8000000U) #define ENET_MAC_CONFIGURATION_IPC_SHIFT (27U) /*! IPC - Checksum Offload * 0b0..IP header/payload checksum checking is disabled * 0b1..IP header/payload checksum checking is enabled */ #define ENET_MAC_CONFIGURATION_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_MAC_CONFIGURATION_IPC_MASK) #define ENET_MAC_CONFIGURATION_SARC_MASK (0x70000000U) #define ENET_MAC_CONFIGURATION_SARC_SHIFT (28U) /*! SARC - Source Address Insertion or Replacement Control * 0b010..Contents of MAC Addr-0 inserted in SA field * 0b011..Contents of MAC Addr-0 replaces SA field * 0b110..Contents of MAC Addr-1 inserted in SA field * 0b111..Contents of MAC Addr-1 replaces SA field * 0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation */ #define ENET_MAC_CONFIGURATION_SARC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_MAC_CONFIGURATION_SARC_MASK) /*! @} */ /*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */ /*! @{ */ #define ENET_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU) #define ENET_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U) /*! GPSL - Giant Packet Size Limit */ #define ENET_MAC_EXT_CONFIGURATION_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_GPSL_MASK) #define ENET_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U) #define ENET_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U) /*! DCRCC - Disable CRC Checking for Received Packets * 0b1..CRC Checking is disabled * 0b0..CRC Checking is enabled */ #define ENET_MAC_EXT_CONFIGURATION_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_DCRCC_MASK) #define ENET_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U) #define ENET_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U) /*! SPEN - Slow Protocol Detection Enable * 0b0..Slow Protocol Detection is disabled * 0b1..Slow Protocol Detection is enabled */ #define ENET_MAC_EXT_CONFIGURATION_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_SPEN_MASK) #define ENET_MAC_EXT_CONFIGURATION_USP_MASK (0x40000U) #define ENET_MAC_EXT_CONFIGURATION_USP_SHIFT (18U) /*! USP - Unicast Slow Protocol Packet Detect * 0b0..Unicast Slow Protocol Packet Detection is disabled * 0b1..Unicast Slow Protocol Packet Detection is enabled */ #define ENET_MAC_EXT_CONFIGURATION_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_USP_MASK) #define ENET_MAC_EXT_CONFIGURATION_PDC_MASK (0x80000U) #define ENET_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U) /*! PDC - Packet Duplication Control * 0b0..Packet Duplication Control is disabled * 0b1..Packet Duplication Control is enabled */ #define ENET_MAC_EXT_CONFIGURATION_PDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_PDC_MASK) #define ENET_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U) #define ENET_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U) /*! EIPGEN - Extended Inter-Packet Gap Enable * 0b0..Extended Inter-Packet Gap is disabled * 0b1..Extended Inter-Packet Gap is enabled */ #define ENET_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_EIPGEN_MASK) #define ENET_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U) #define ENET_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U) /*! EIPG - Extended Inter-Packet Gap */ #define ENET_MAC_EXT_CONFIGURATION_EIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_MAC_EXT_CONFIGURATION_EIPG_MASK) /*! @} */ /*! @name MAC_PACKET_FILTER - MAC Packet Filter */ /*! @{ */ #define ENET_MAC_PACKET_FILTER_PR_MASK (0x1U) #define ENET_MAC_PACKET_FILTER_PR_SHIFT (0U) /*! PR - Promiscuous Mode * 0b0..Promiscuous Mode is disabled * 0b1..Promiscuous Mode is enabled */ #define ENET_MAC_PACKET_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_MAC_PACKET_FILTER_PR_MASK) #define ENET_MAC_PACKET_FILTER_DAIF_MASK (0x8U) #define ENET_MAC_PACKET_FILTER_DAIF_SHIFT (3U) /*! DAIF - DA Inverse Filtering * 0b0..DA Inverse Filtering is disabled * 0b1..DA Inverse Filtering is enabled */ #define ENET_MAC_PACKET_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_MAC_PACKET_FILTER_DAIF_MASK) #define ENET_MAC_PACKET_FILTER_PM_MASK (0x10U) #define ENET_MAC_PACKET_FILTER_PM_SHIFT (4U) /*! PM - Pass All Multicast * 0b0..Pass All Multicast is disabled * 0b1..Pass All Multicast is enabled */ #define ENET_MAC_PACKET_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_MAC_PACKET_FILTER_PM_MASK) #define ENET_MAC_PACKET_FILTER_DBF_MASK (0x20U) #define ENET_MAC_PACKET_FILTER_DBF_SHIFT (5U) /*! DBF - Disable Broadcast Packets * 0b1..Disable Broadcast Packets * 0b0..Enable Broadcast Packets */ #define ENET_MAC_PACKET_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_MAC_PACKET_FILTER_DBF_MASK) #define ENET_MAC_PACKET_FILTER_PCF_MASK (0xC0U) #define ENET_MAC_PACKET_FILTER_PCF_SHIFT (6U) /*! PCF - Pass Control Packets * 0b00..MAC filters all control packets from reaching the application * 0b10..MAC forwards all control packets to the application even if they fail the address filter * 0b11..MAC forwards the control packets that pass the Address filter * 0b01..MAC forwards all control packets except Pause packets to the application even if they fail the address filter */ #define ENET_MAC_PACKET_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_MAC_PACKET_FILTER_PCF_MASK) #define ENET_MAC_PACKET_FILTER_VTFE_MASK (0x10000U) #define ENET_MAC_PACKET_FILTER_VTFE_SHIFT (16U) /*! VTFE - VLAN Tag Filter Enable * 0b0..VLAN Tag Filter is disabled * 0b1..VLAN Tag Filter is enabled */ #define ENET_MAC_PACKET_FILTER_VTFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_MAC_PACKET_FILTER_VTFE_MASK) #define ENET_MAC_PACKET_FILTER_RA_MASK (0x80000000U) #define ENET_MAC_PACKET_FILTER_RA_SHIFT (31U) /*! RA - Receive All * 0b0..Receive All is disabled * 0b1..Receive All is enabled */ #define ENET_MAC_PACKET_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_MAC_PACKET_FILTER_RA_MASK) /*! @} */ /*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */ /*! @{ */ #define ENET_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU) #define ENET_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U) /*! WTO - Watchdog Timeout * 0b1000..10 KB * 0b1001..11 KB * 0b1010..12 KB * 0b1011..13 KB * 0b1100..14 KB * 0b1101..15 KB * 0b1110..16383 Bytes * 0b0000..2 KB * 0b0001..3 KB * 0b0010..4 KB * 0b0011..5 KB * 0b0100..6 KB * 0b0101..7 KB * 0b0110..8 KB * 0b0111..9 KB * 0b1111..Reserved */ #define ENET_MAC_WATCHDOG_TIMEOUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_MAC_WATCHDOG_TIMEOUT_WTO_MASK) #define ENET_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x100U) #define ENET_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U) /*! PWE - Programmable Watchdog Enable * 0b0..Programmable Watchdog is disabled * 0b1..Programmable Watchdog is enabled */ #define ENET_MAC_WATCHDOG_TIMEOUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_MAC_WATCHDOG_TIMEOUT_PWE_MASK) /*! @} */ /*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */ /*! @{ */ #define ENET_MAC_VLAN_TAG_CTRL_VL_MASK (0xFFFFU) #define ENET_MAC_VLAN_TAG_CTRL_VL_SHIFT (0U) /*! VL - VLAN Tag Identifier for Receive Packets */ #define ENET_MAC_VLAN_TAG_CTRL_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_VL_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_VL_MASK) #define ENET_MAC_VLAN_TAG_CTRL_ETV_MASK (0x10000U) #define ENET_MAC_VLAN_TAG_CTRL_ETV_SHIFT (16U) /*! ETV - Enable 12-Bit VLAN Tag Comparison * 0b0..12-bit VLAN Tag Comparison is disabled * 0b1..12-bit VLAN Tag Comparison is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_ETV_MASK) #define ENET_MAC_VLAN_TAG_CTRL_VTIM_MASK (0x20000U) #define ENET_MAC_VLAN_TAG_CTRL_VTIM_SHIFT (17U) /*! VTIM - VLAN Tag Inverse Match Enable * 0b0..VLAN Tag Inverse Match is disabled * 0b1..VLAN Tag Inverse Match is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_VTIM_MASK) #define ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK (0x40000U) #define ENET_MAC_VLAN_TAG_CTRL_ESVL_SHIFT (18U) /*! ESVL - Enable S-VLAN * 0b0..S-VLAN is disabled * 0b1..S-VLAN is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) #define ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK (0x80000U) #define ENET_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT (19U) /*! ERSVLM - Enable Receive S-VLAN Match * 0b0..Receive S-VLAN Match is disabled * 0b1..Receive S-VLAN Match is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK) #define ENET_MAC_VLAN_TAG_CTRL_DOVLTC_MASK (0x100000U) #define ENET_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT (20U) /*! DOVLTC - Disable VLAN Type Check * 0b1..VLAN Type Check is disabled * 0b0..VLAN Type Check is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_DOVLTC_MASK) #define ENET_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x600000U) #define ENET_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21U) /*! EVLS - Enable VLAN Tag Stripping on Receive * 0b11..Always strip * 0b00..Do not strip * 0b10..Strip if VLAN filter fails * 0b01..Strip if VLAN filter passes */ #define ENET_MAC_VLAN_TAG_CTRL_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EVLS_MASK) #define ENET_MAC_VLAN_TAG_CTRL_EVLRXS_MASK (0x1000000U) #define ENET_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT (24U) /*! EVLRXS - Enable VLAN Tag in Rx status * 0b0..VLAN Tag in Rx status is disabled * 0b1..VLAN Tag in Rx status is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EVLRXS_MASK) #define ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK (0x4000000U) #define ENET_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT (26U) /*! EDVLP - Enable Double VLAN Processing * 0b0..Double VLAN Processing is disabled * 0b1..Double VLAN Processing is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK) #define ENET_MAC_VLAN_TAG_CTRL_ERIVLT_MASK (0x8000000U) #define ENET_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT (27U) /*! ERIVLT - Enable Inner VLAN Tag * 0b0..Inner VLAN tag is disabled * 0b1..Inner VLAN tag is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_ERIVLT_MASK) #define ENET_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x30000000U) #define ENET_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28U) /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive * 0b11..Always strip * 0b00..Do not strip * 0b10..Strip if VLAN filter fails * 0b01..Strip if VLAN filter passes */ #define ENET_MAC_VLAN_TAG_CTRL_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EIVLS_MASK) #define ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK (0x80000000U) #define ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U) /*! EIVLRXS - Enable Inner VLAN Tag in Rx Status * 0b0..Inner VLAN Tag in Rx status is disabled * 0b1..Inner VLAN Tag in Rx status is enabled */ #define ENET_MAC_VLAN_TAG_CTRL_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK) /*! @} */ /*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */ /*! @{ */ #define ENET_MAC_VLAN_INCL_VLT_MASK (0xFFFFU) #define ENET_MAC_VLAN_INCL_VLT_SHIFT (0U) /*! VLT - VLAN Tag for Transmit Packets */ #define ENET_MAC_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_MAC_VLAN_INCL_VLT_MASK) #define ENET_MAC_VLAN_INCL_VLC_MASK (0x30000U) #define ENET_MAC_VLAN_INCL_VLC_SHIFT (16U) /*! VLC - VLAN Tag Control in Transmit Packets * 0b01..VLAN tag deletion * 0b10..VLAN tag insertion * 0b00..No VLAN tag deletion, insertion, or replacement * 0b11..VLAN tag replacement */ #define ENET_MAC_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_MAC_VLAN_INCL_VLC_MASK) #define ENET_MAC_VLAN_INCL_VLP_MASK (0x40000U) #define ENET_MAC_VLAN_INCL_VLP_SHIFT (18U) /*! VLP - VLAN Priority Control * 0b0..VLAN Priority Control is disabled * 0b1..VLAN Priority Control is enabled */ #define ENET_MAC_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_MAC_VLAN_INCL_VLP_MASK) #define ENET_MAC_VLAN_INCL_CSVL_MASK (0x80000U) #define ENET_MAC_VLAN_INCL_CSVL_SHIFT (19U) /*! CSVL - C-VLAN or S-VLAN * 0b0..C-VLAN type (0x8100) is inserted or replaced * 0b1..S-VLAN type (0x88A8) is inserted or replaced */ #define ENET_MAC_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_MAC_VLAN_INCL_CSVL_MASK) #define ENET_MAC_VLAN_INCL_VLTI_MASK (0x100000U) #define ENET_MAC_VLAN_INCL_VLTI_SHIFT (20U) /*! VLTI - VLAN Tag Input * 0b0..VLAN Tag Input is disabled * 0b1..VLAN Tag Input is enabled */ #define ENET_MAC_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_MAC_VLAN_INCL_VLTI_MASK) #define ENET_MAC_VLAN_INCL_CBTI_MASK (0x200000U) #define ENET_MAC_VLAN_INCL_CBTI_SHIFT (21U) /*! CBTI - Channel based tag insertion * 0b0..Channel based tag insertion is disabled * 0b1..Channel based tag insertion is enabled */ #define ENET_MAC_VLAN_INCL_CBTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_MAC_VLAN_INCL_CBTI_MASK) #define ENET_MAC_VLAN_INCL_ADDR_MASK (0x1000000U) #define ENET_MAC_VLAN_INCL_ADDR_SHIFT (24U) /*! ADDR - Address */ #define ENET_MAC_VLAN_INCL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_MAC_VLAN_INCL_ADDR_MASK) #define ENET_MAC_VLAN_INCL_RDWR_MASK (0x40000000U) #define ENET_MAC_VLAN_INCL_RDWR_SHIFT (30U) /*! RDWR - Read write control * 0b0..Read operation of indirect access * 0b1..Write operation of indirect access */ #define ENET_MAC_VLAN_INCL_RDWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_MAC_VLAN_INCL_RDWR_MASK) #define ENET_MAC_VLAN_INCL_BUSY_MASK (0x80000000U) #define ENET_MAC_VLAN_INCL_BUSY_SHIFT (31U) /*! BUSY - Busy * 0b1..Busy status detected * 0b0..Busy status not detected */ #define ENET_MAC_VLAN_INCL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_MAC_VLAN_INCL_BUSY_MASK) /*! @} */ /*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */ /*! @{ */ #define ENET_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFFU) #define ENET_MAC_INNER_VLAN_INCL_VLT_SHIFT (0U) /*! VLT - VLAN Tag for Transmit Packets */ #define ENET_MAC_INNER_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_VLT_MASK) #define ENET_MAC_INNER_VLAN_INCL_VLC_MASK (0x30000U) #define ENET_MAC_INNER_VLAN_INCL_VLC_SHIFT (16U) /*! VLC - VLAN Tag Control in Transmit Packets * 0b01..VLAN tag deletion * 0b10..VLAN tag insertion * 0b00..No VLAN tag deletion, insertion, or replacement * 0b11..VLAN tag replacement */ #define ENET_MAC_INNER_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_VLC_MASK) #define ENET_MAC_INNER_VLAN_INCL_VLP_MASK (0x40000U) #define ENET_MAC_INNER_VLAN_INCL_VLP_SHIFT (18U) /*! VLP - VLAN Priority Control * 0b0..VLAN Priority Control is disabled * 0b1..VLAN Priority Control is enabled */ #define ENET_MAC_INNER_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_VLP_MASK) #define ENET_MAC_INNER_VLAN_INCL_CSVL_MASK (0x80000U) #define ENET_MAC_INNER_VLAN_INCL_CSVL_SHIFT (19U) /*! CSVL - C-VLAN or S-VLAN * 0b0..C-VLAN type (0x8100) is inserted * 0b1..S-VLAN type (0x88A8) is inserted */ #define ENET_MAC_INNER_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_CSVL_MASK) #define ENET_MAC_INNER_VLAN_INCL_VLTI_MASK (0x100000U) #define ENET_MAC_INNER_VLAN_INCL_VLTI_SHIFT (20U) /*! VLTI - VLAN Tag Input * 0b0..VLAN Tag Input is disabled * 0b1..VLAN Tag Input is enabled */ #define ENET_MAC_INNER_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_MAC_INNER_VLAN_INCL_VLTI_MASK) /*! @} */ /*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control */ /*! @{ */ #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U) #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U) /*! FCB_BPA - Flow Control Busy or Backpressure Activate * 0b0..Flow Control Busy or Backpressure Activate is disabled * 0b1..Flow Control Busy or Backpressure Activate is enabled */ #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK) #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) /*! TFE - Transmit Flow Control Enable * 0b0..Transmit Flow Control is disabled * 0b1..Transmit Flow Control is enabled */ #define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK) #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) /*! PLT - Pause Low Threshold * 0b011..Pause Time minus 144 Slot Times (PT -144 slot times) * 0b100..Pause Time minus 256 Slot Times (PT -256 slot times) * 0b001..Pause Time minus 28 Slot Times (PT -28 slot times) * 0b010..Pause Time minus 36 Slot Times (PT -36 slot times) * 0b000..Pause Time minus 4 Slot Times (PT -4 slot times) * 0b101..Pause Time minus 512 Slot Times (PT -512 slot times) * 0b110..Reserved */ #define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK) #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) /*! DZPQ - Disable Zero-Quanta Pause * 0b1..Zero-Quanta Pause packet generation is disabled * 0b0..Zero-Quanta Pause packet generation is enabled */ #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) #define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) #define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) /*! PT - Pause Time */ #define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK) /*! @} */ /* The count of ENET_MAC_TX_FLOW_CTRL_Q */ #define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (1U) /*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */ /*! @{ */ #define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) #define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) /*! RFE - Receive Flow Control Enable * 0b0..Receive Flow Control is disabled * 0b1..Receive Flow Control is enabled */ #define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK) #define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) #define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) /*! UP - Unicast Pause Packet Detect * 0b0..Unicast Pause Packet Detect disabled * 0b1..Unicast Pause Packet Detect enabled */ #define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK) /*! @} */ /*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */ /*! @{ */ #define ENET_MAC_RXQ_CTRL4_UFFQE_MASK (0x1U) #define ENET_MAC_RXQ_CTRL4_UFFQE_SHIFT (0U) /*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable. * 0b0..Unicast Address Filter Fail Packets Queuing is disabled * 0b1..Unicast Address Filter Fail Packets Queuing is enabled */ #define ENET_MAC_RXQ_CTRL4_UFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_MAC_RXQ_CTRL4_UFFQE_MASK) #define ENET_MAC_RXQ_CTRL4_UFFQ_MASK (0x2U) #define ENET_MAC_RXQ_CTRL4_UFFQ_SHIFT (1U) /*! UFFQ - Unicast Address Filter Fail Packets Queue. */ #define ENET_MAC_RXQ_CTRL4_UFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_MAC_RXQ_CTRL4_UFFQ_MASK) #define ENET_MAC_RXQ_CTRL4_MFFQE_MASK (0x100U) #define ENET_MAC_RXQ_CTRL4_MFFQE_SHIFT (8U) /*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable. * 0b0..Multicast Address Filter Fail Packets Queuing is disabled * 0b1..Multicast Address Filter Fail Packets Queuing is enabled */ #define ENET_MAC_RXQ_CTRL4_MFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_MAC_RXQ_CTRL4_MFFQE_MASK) #define ENET_MAC_RXQ_CTRL4_MFFQ_MASK (0x200U) #define ENET_MAC_RXQ_CTRL4_MFFQ_SHIFT (9U) /*! MFFQ - Multicast Address Filter Fail Packets Queue. */ #define ENET_MAC_RXQ_CTRL4_MFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_MAC_RXQ_CTRL4_MFFQ_MASK) #define ENET_MAC_RXQ_CTRL4_VFFQE_MASK (0x10000U) #define ENET_MAC_RXQ_CTRL4_VFFQE_SHIFT (16U) /*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable * 0b0..VLAN tag Filter Fail Packets Queuing is disabled * 0b1..VLAN tag Filter Fail Packets Queuing is enabled */ #define ENET_MAC_RXQ_CTRL4_VFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_MAC_RXQ_CTRL4_VFFQE_MASK) #define ENET_MAC_RXQ_CTRL4_VFFQ_MASK (0x20000U) #define ENET_MAC_RXQ_CTRL4_VFFQ_SHIFT (17U) /*! VFFQ - VLAN Tag Filter Fail Packets Queue */ #define ENET_MAC_RXQ_CTRL4_VFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_MAC_RXQ_CTRL4_VFFQ_MASK) /*! @} */ /*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 2 */ /*! @{ */ #define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) #define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) /*! AVCPQ - AV Untagged Control Packets Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 */ #define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK) #define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) #define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) /*! PSRQ0 - Priorities Selected in the Receive Queue 0 */ #define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK) #define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) #define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) /*! RXQ0EN - Receive Queue 0 Enable * 0b00..Queue not enabled * 0b01..Queue enabled for AV * 0b10..Queue enabled for DCB/Generic * 0b11..Reserved */ #define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK) #define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) #define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) /*! RXQ1EN - Receive Queue 1 Enable * 0b00..Queue not enabled * 0b01..Queue enabled for AV * 0b10..Queue enabled for DCB/Generic * 0b11..Reserved */ #define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK) #define ENET_MAC_RXQ_CTRL_PTPQ_MASK (0x70U) #define ENET_MAC_RXQ_CTRL_PTPQ_SHIFT (4U) /*! PTPQ - PTP Packets Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 */ #define ENET_MAC_RXQ_CTRL_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_PTPQ_MASK) #define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) #define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) /*! PSRQ1 - Priorities Selected in the Receive Queue 1 */ #define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK) #define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) #define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U) /*! UPQ - Untagged Packet Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 */ #define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK) #define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) #define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) /*! MCBCQ - Multicast and Broadcast Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 */ #define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK) #define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) #define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) /*! MCBCQEN - Multicast and Broadcast Queue Enable * 0b0..Multicast and Broadcast Queue is disabled * 0b1..Multicast and Broadcast Queue is enabled */ #define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK) #define ENET_MAC_RXQ_CTRL_TACPQE_MASK (0x200000U) #define ENET_MAC_RXQ_CTRL_TACPQE_SHIFT (21U) /*! TACPQE - Tagged AV Control Packets Queuing Enable. * 0b0..Tagged AV Control Packets Queuing is disabled * 0b1..Tagged AV Control Packets Queuing is enabled */ #define ENET_MAC_RXQ_CTRL_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_MAC_RXQ_CTRL_TACPQE_MASK) #define ENET_MAC_RXQ_CTRL_TPQC_MASK (0xC00000U) #define ENET_MAC_RXQ_CTRL_TPQC_SHIFT (22U) /*! TPQC - Tagged PTP over Ethernet Packets Queuing Control. */ #define ENET_MAC_RXQ_CTRL_TPQC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_MAC_RXQ_CTRL_TPQC_MASK) #define ENET_MAC_RXQ_CTRL_OMCBCQ_MASK (0x10000000U) #define ENET_MAC_RXQ_CTRL_OMCBCQ_SHIFT (28U) /*! OMCBCQ - OMCBCQ * 0b0..overriding MCBCQ priority disabled * 0b1..overriding MCBCQ priority enabled */ #define ENET_MAC_RXQ_CTRL_OMCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_OMCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_OMCBCQ_MASK) #define ENET_MAC_RXQ_CTRL_TBRQE_MASK (0x20000000U) #define ENET_MAC_RXQ_CTRL_TBRQE_SHIFT (29U) /*! TBRQE - Type Field Based Rx Queuing Enable */ #define ENET_MAC_RXQ_CTRL_TBRQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_TBRQE_SHIFT)) & ENET_MAC_RXQ_CTRL_TBRQE_MASK) /*! @} */ /* The count of ENET_MAC_RXQ_CTRL */ #define ENET_MAC_RXQ_CTRL_COUNT (3U) /*! @name MAC_INTERRUPT_STATUS - Interrupt Status */ /*! @{ */ #define ENET_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U) #define ENET_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U) /*! PHYIS - PHY Interrupt * 0b1..PHY Interrupt detected * 0b0..PHY Interrupt not detected */ #define ENET_MAC_INTERRUPT_STATUS_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_PHYIS_MASK) #define ENET_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U) #define ENET_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U) /*! PMTIS - PMTIS * 0b1..PMT Interrupt status active * 0b0..PMT Interrupt status not active */ #define ENET_MAC_INTERRUPT_STATUS_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_PMTIS_MASK) #define ENET_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U) #define ENET_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U) /*! LPIIS - LPIIS * 0b1..LPI Interrupt status active * 0b0..LPI Interrupt status not active */ #define ENET_MAC_INTERRUPT_STATUS_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_LPIIS_MASK) #define ENET_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1000U) #define ENET_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U) /*! TSIS - TSIS * 0b1..Timestamp Interrupt status active * 0b0..Timestamp Interrupt status not active */ #define ENET_MAC_INTERRUPT_STATUS_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_TSIS_MASK) #define ENET_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U) #define ENET_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U) /*! TXSTSIS - Transmit Status Interrupt * 0b1..Transmit Interrupt status active * 0b0..Transmit Interrupt status not active */ #define ENET_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_TXSTSIS_MASK) #define ENET_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U) #define ENET_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U) /*! RXSTSIS - Receive Status Interrupt * 0b1..Receive Interrupt status active * 0b0..Receive Interrupt status not active */ #define ENET_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_RXSTSIS_MASK) #define ENET_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U) #define ENET_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U) /*! MDIOIS - MDIO Interrupt Status * 0b1..MDIO Interrupt status active * 0b0..MDIO Interrupt status not active */ #define ENET_MAC_INTERRUPT_STATUS_MDIOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_MAC_INTERRUPT_STATUS_MDIOIS_MASK) /*! @} */ /*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */ /*! @{ */ #define ENET_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U) #define ENET_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U) /*! PHYIE - PHY Interrupt Enable * 0b0..PHY Interrupt is disabled * 0b1..PHY Interrupt is enabled */ #define ENET_MAC_INTERRUPT_ENABLE_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_PHYIE_MASK) #define ENET_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U) #define ENET_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U) /*! PMTIE - PMT Interrupt Enable * 0b0..PMT Interrupt is disabled * 0b1..PMT Interrupt is enabled */ #define ENET_MAC_INTERRUPT_ENABLE_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_PMTIE_MASK) #define ENET_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U) #define ENET_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U) /*! LPIIE - LPI Interrupt Enable * 0b0..LPI Interrupt is disabled * 0b1..LPI Interrupt is enabled */ #define ENET_MAC_INTERRUPT_ENABLE_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_LPIIE_MASK) #define ENET_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1000U) #define ENET_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U) /*! TSIE - Timestamp Interrupt Enable * 0b0..Timestamp Interrupt is disabled * 0b1..Timestamp Interrupt is enabled */ #define ENET_MAC_INTERRUPT_ENABLE_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_TSIE_MASK) #define ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U) #define ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U) /*! TXSTSIE - Transmit Status Interrupt Enable * 0b0..Timestamp Status Interrupt is disabled * 0b1..Timestamp Status Interrupt is enabled */ #define ENET_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK) #define ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U) #define ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U) /*! RXSTSIE - Receive Status Interrupt Enable * 0b0..Receive Status Interrupt is disabled * 0b1..Receive Status Interrupt is enabled */ #define ENET_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK) #define ENET_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U) #define ENET_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U) /*! MDIOIE - MDIO Interrupt Enable * 0b0..MDIO Interrupt is disabled * 0b1..MDIO Interrupt is enabled */ #define ENET_MAC_INTERRUPT_ENABLE_MDIOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_MAC_INTERRUPT_ENABLE_MDIOIE_MASK) /*! @} */ /*! @name MAC_RX_TX_STATUS - Receive Transmit Status */ /*! @{ */ #define ENET_MAC_RX_TX_STATUS_TJT_MASK (0x1U) #define ENET_MAC_RX_TX_STATUS_TJT_SHIFT (0U) /*! TJT - Transmit Jabber Timeout * 0b1..Transmit Jabber Timeout occurred * 0b0..No Transmit Jabber Timeout */ #define ENET_MAC_RX_TX_STATUS_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_MAC_RX_TX_STATUS_TJT_MASK) #define ENET_MAC_RX_TX_STATUS_NCARR_MASK (0x2U) #define ENET_MAC_RX_TX_STATUS_NCARR_SHIFT (1U) /*! NCARR - No Carrier * 0b1..No carrier * 0b0..Carrier is present */ #define ENET_MAC_RX_TX_STATUS_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_MAC_RX_TX_STATUS_NCARR_MASK) #define ENET_MAC_RX_TX_STATUS_LCARR_MASK (0x4U) #define ENET_MAC_RX_TX_STATUS_LCARR_SHIFT (2U) /*! LCARR - Loss of Carrier * 0b1..Loss of carrier * 0b0..Carrier is present */ #define ENET_MAC_RX_TX_STATUS_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_MAC_RX_TX_STATUS_LCARR_MASK) #define ENET_MAC_RX_TX_STATUS_EXDEF_MASK (0x8U) #define ENET_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U) /*! EXDEF - Excessive Deferral * 0b1..Excessive deferral * 0b0..No Excessive deferral */ #define ENET_MAC_RX_TX_STATUS_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_MAC_RX_TX_STATUS_EXDEF_MASK) #define ENET_MAC_RX_TX_STATUS_LCOL_MASK (0x10U) #define ENET_MAC_RX_TX_STATUS_LCOL_SHIFT (4U) /*! LCOL - Late Collision * 0b1..Late collision is sensed * 0b0..No collision */ #define ENET_MAC_RX_TX_STATUS_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_MAC_RX_TX_STATUS_LCOL_MASK) #define ENET_MAC_RX_TX_STATUS_EXCOL_MASK (0x20U) #define ENET_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U) /*! EXCOL - Excessive Collisions * 0b1..Excessive collision is sensed * 0b0..No collision */ #define ENET_MAC_RX_TX_STATUS_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_MAC_RX_TX_STATUS_EXCOL_MASK) #define ENET_MAC_RX_TX_STATUS_RWT_MASK (0x100U) #define ENET_MAC_RX_TX_STATUS_RWT_SHIFT (8U) /*! RWT - Receive Watchdog Timeout * 0b1..Receive watchdog timed out * 0b0..No receive watchdog timeout */ #define ENET_MAC_RX_TX_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_MAC_RX_TX_STATUS_RWT_MASK) /*! @} */ /*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */ /*! @{ */ #define ENET_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U) #define ENET_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U) /*! PWRDWN - Power Down * 0b0..Power down is disabled * 0b1..Power down is enabled */ #define ENET_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK) #define ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U) #define ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U) /*! MGKPKTEN - Magic Packet Enable * 0b0..Magic Packet is disabled * 0b1..Magic Packet is enabled */ #define ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK) #define ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U) #define ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U) /*! RWKPKTEN - Remote Wake-Up Packet Enable * 0b0..Remote wake-up packet is disabled * 0b1..Remote wake-up packet is enabled */ #define ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK) #define ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U) #define ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U) /*! MGKPRCVD - Magic Packet Received * 0b1..Magic packet is received * 0b0..No Magic packet is received */ #define ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK) #define ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U) #define ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U) /*! RWKPRCVD - Remote Wake-Up Packet Received * 0b1..Remote wake-up packet is received * 0b0..Remote wake-up packet is received */ #define ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK) #define ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U) #define ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U) /*! GLBLUCAST - Global Unicast * 0b0..Global unicast is disabled * 0b1..Global unicast is enabled */ #define ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK) #define ENET_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U) #define ENET_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U) /*! RWKPFE - Remote Wake-up Packet Forwarding Enable * 0b0..Remote Wake-up Packet Forwarding is disabled * 0b1..Remote Wake-up Packet Forwarding is enabled */ #define ENET_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK) #define ENET_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U) #define ENET_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U) /*! RWKPTR - Remote Wake-up FIFO Pointer */ #define ENET_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK) #define ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U) #define ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U) /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset * 0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset * 0b1..Remote Wake-Up Packet Filter Register Pointer is Reset */ #define ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK) /*! @} */ /*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */ /*! @{ */ #define ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU) #define ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U) /*! WKUPFRMFTR - RWK Packet Filter */ #define ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK) /*! @} */ /*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */ /*! @{ */ #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U) #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U) /*! TLPIEN - Transmit LPI Entry * 0b1..Transmit LPI entry detected * 0b0..Transmit LPI entry not detected */ #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U) #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U) /*! TLPIEX - Transmit LPI Exit * 0b1..Transmit LPI exit detected * 0b0..Transmit LPI exit not detected */ #define ENET_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U) #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U) /*! RLPIEN - Receive LPI Entry * 0b1..Receive LPI entry detected * 0b0..Receive LPI entry not detected */ #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U) #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U) /*! RLPIEX - Receive LPI Exit * 0b1..Receive LPI exit detected * 0b0..Receive LPI exit not detected */ #define ENET_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U) #define ENET_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U) /*! TLPIST - Transmit LPI State * 0b1..Transmit LPI state detected * 0b0..Transmit LPI state not detected */ #define ENET_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_TLPIST_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U) #define ENET_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U) /*! RLPIST - Receive LPI State * 0b1..Receive LPI state detected * 0b0..Receive LPI state not detected */ #define ENET_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_RLPIST_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U) #define ENET_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U) /*! LPIEN - LPI Enable * 0b0..LPI state is disabled * 0b1..LPI state is enabled */ #define ENET_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_LPIEN_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U) #define ENET_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U) /*! PLS - PHY Link Status * 0b0..link is down * 0b1..link is okay (UP) */ #define ENET_MAC_LPI_CONTROL_STATUS_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_PLS_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U) #define ENET_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U) /*! LPITXA - LPI Tx Automate * 0b0..LPI Tx Automate is disabled * 0b1..LPI Tx Automate is enabled */ #define ENET_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_LPITXA_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U) #define ENET_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U) /*! LPIATE - LPI Timer Enable * 0b0..LPI Timer is disabled * 0b1..LPI Timer is enabled */ #define ENET_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_LPIATE_MASK) #define ENET_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U) #define ENET_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U) /*! LPITCSE - LPI Tx Clock Stop Enable * 0b0..LPI Tx Clock Stop is disabled * 0b1..LPI Tx Clock Stop is enabled */ #define ENET_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK) /*! @} */ /*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */ /*! @{ */ #define ENET_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU) #define ENET_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U) /*! TWT - LPI TW Timer */ #define ENET_MAC_LPI_TIMERS_CONTROL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_MAC_LPI_TIMERS_CONTROL_TWT_MASK) #define ENET_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U) #define ENET_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U) /*! LST - LPI LS Timer */ #define ENET_MAC_LPI_TIMERS_CONTROL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_MAC_LPI_TIMERS_CONTROL_LST_MASK) /*! @} */ /*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */ /*! @{ */ #define ENET_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0xFFFF8U) #define ENET_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U) /*! LPIET - LPI Entry Timer */ #define ENET_MAC_LPI_ENTRY_TIMER_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_MAC_LPI_ENTRY_TIMER_LPIET_MASK) /*! @} */ /*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */ /*! @{ */ #define ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU) #define ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U) /*! TIC_1US_CNTR - 1US TIC Counter */ #define ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK) /*! @} */ /*! @name MAC_VERSION - MAC Version */ /*! @{ */ #define ENET_MAC_VERSION_SNPSVER_MASK (0xFFU) #define ENET_MAC_VERSION_SNPSVER_SHIFT (0U) /*! SNPSVER - Synopsys-defined Version */ #define ENET_MAC_VERSION_SNPSVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPSVER_SHIFT)) & ENET_MAC_VERSION_SNPSVER_MASK) #define ENET_MAC_VERSION_USERVER_MASK (0xFF00U) #define ENET_MAC_VERSION_USERVER_SHIFT (8U) /*! USERVER - User-defined Version */ #define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK) /*! @} */ /*! @name MAC_DEBUG - MAC Debug */ /*! @{ */ #define ENET_MAC_DEBUG_RPESTS_MASK (0x1U) #define ENET_MAC_DEBUG_RPESTS_SHIFT (0U) /*! RPESTS - MAC GMII or MII Receive Protocol Engine Status * 0b1..MAC GMII or MII Receive Protocol Engine Status detected * 0b0..MAC GMII or MII Receive Protocol Engine Status not detected */ #define ENET_MAC_DEBUG_RPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DEBUG_RPESTS_SHIFT)) & ENET_MAC_DEBUG_RPESTS_MASK) #define ENET_MAC_DEBUG_RFCFCSTS_MASK (0x6U) #define ENET_MAC_DEBUG_RFCFCSTS_SHIFT (1U) /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status */ #define ENET_MAC_DEBUG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_MAC_DEBUG_RFCFCSTS_MASK) #define ENET_MAC_DEBUG_TPESTS_MASK (0x10000U) #define ENET_MAC_DEBUG_TPESTS_SHIFT (16U) /*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status * 0b1..MAC GMII or MII Transmit Protocol Engine Status detected * 0b0..MAC GMII or MII Transmit Protocol Engine Status not detected */ #define ENET_MAC_DEBUG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DEBUG_TPESTS_SHIFT)) & ENET_MAC_DEBUG_TPESTS_MASK) #define ENET_MAC_DEBUG_TFCSTS_MASK (0x60000U) #define ENET_MAC_DEBUG_TFCSTS_SHIFT (17U) /*! TFCSTS - MAC Transmit Packet Controller Status * 0b10..Generating and transmitting a Pause control packet (in full-duplex mode) * 0b00..Idle state * 0b11..Transferring input packet for transmission * 0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over */ #define ENET_MAC_DEBUG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_MAC_DEBUG_TFCSTS_MASK) /*! @} */ /*! @name MAC_HW_FEAT - Hardware Features 0..Hardware Features 3 */ /*! @{ */ #define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U) #define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U) /*! MIISEL - 10 or 100 Mbps Support * 0b1..10 or 100 Mbps support * 0b0..No 10 or 100 Mbps support */ #define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK) #define ENET_MAC_HW_FEAT_NRVF_MASK (0x7U) #define ENET_MAC_HW_FEAT_NRVF_SHIFT (0U) /*! NRVF - Number of Extended VLAN Tag Filters Enabled * 0b011..16 Extended Rx VLAN Filters * 0b100..24 Extended Rx VLAN Filters * 0b101..32 Extended Rx VLAN Filters * 0b001..4 Extended Rx VLAN Filters * 0b010..8 Extended Rx VLAN Filters * 0b000..No Extended Rx VLAN Filters * 0b110..Reserved */ #define ENET_MAC_HW_FEAT_NRVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_MAC_HW_FEAT_NRVF_MASK) #define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) #define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - MTL Receive FIFO Size * 0b00011..1024 bytes * 0b00000..128 bytes * 0b01010..128 KB * 0b00111..16384 bytes * 0b00100..2048 bytes * 0b00001..256 bytes * 0b01011..256 KB * 0b01000..32 KB * 0b00101..4096 bytes * 0b00010..512 bytes * 0b01001..64 KB * 0b00110..8192 bytes * 0b01100..Reserved */ #define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK) #define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU) #define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U) /*! RXQCNT - Number of MTL Receive Queues * 0b0000..1 MTL Rx Queue * 0b0001..2 MTL Rx Queues * 0b0010..3 MTL Rx Queues * 0b0011..4 MTL Rx Queues * 0b0100..5 MTL Rx Queues * 0b0101..6 MTL Rx Queues * 0b0110..7 MTL Rx Queues * 0b0111..8 MTL Rx Queues */ #define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK) #define ENET_MAC_HW_FEAT_GMIISEL_MASK (0x2U) #define ENET_MAC_HW_FEAT_GMIISEL_SHIFT (1U) /*! GMIISEL - 1000 Mbps Support * 0b1..1000 Mbps support * 0b0..No 1000 Mbps support */ #define ENET_MAC_HW_FEAT_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_MAC_HW_FEAT_GMIISEL_MASK) #define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U) #define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U) /*! HDSEL - Half-duplex Support * 0b1..Half-duplex support * 0b0..No Half-duplex support */ #define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK) #define ENET_MAC_HW_FEAT_PCSSEL_MASK (0x8U) #define ENET_MAC_HW_FEAT_PCSSEL_SHIFT (3U) /*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) * 0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface) * 0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface) */ #define ENET_MAC_HW_FEAT_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_MAC_HW_FEAT_PCSSEL_MASK) #define ENET_MAC_HW_FEAT_CBTISEL_MASK (0x10U) #define ENET_MAC_HW_FEAT_CBTISEL_SHIFT (4U) /*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable * 0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected * 0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected */ #define ENET_MAC_HW_FEAT_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_MAC_HW_FEAT_CBTISEL_MASK) #define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U) #define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U) /*! VLHASH - VLAN Hash Filter Selected * 0b1..VLAN Hash Filter selected * 0b0..VLAN Hash Filter not selected */ #define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK) #define ENET_MAC_HW_FEAT_DVLAN_MASK (0x20U) #define ENET_MAC_HW_FEAT_DVLAN_SHIFT (5U) /*! DVLAN - Double VLAN Tag Processing Selected * 0b1..Double VLAN option is selected * 0b0..Double VLAN option is not selected */ #define ENET_MAC_HW_FEAT_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_MAC_HW_FEAT_DVLAN_MASK) #define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U) #define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U) /*! SMASEL - SMA (MDIO) Interface * 0b1..SMA (MDIO) Interface selected * 0b0..SMA (MDIO) Interface not selected */ #define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK) #define ENET_MAC_HW_FEAT_SPRAM_MASK (0x20U) #define ENET_MAC_HW_FEAT_SPRAM_SHIFT (5U) /*! SPRAM - Single Port RAM Enable * 0b1..Single Port RAM feature is selected * 0b0..Single Port RAM feature is not selected */ #define ENET_MAC_HW_FEAT_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_MAC_HW_FEAT_SPRAM_MASK) #define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U) #define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U) /*! RWKSEL - PMT Remote Wake-up Packet Enable * 0b1..PMT Remote Wake-up Packet Enable option is selected * 0b0..PMT Remote Wake-up Packet Enable option is not selected */ #define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK) #define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) #define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) /*! TXFIFOSIZE - MTL Transmit FIFO Size * 0b00011..1024 bytes * 0b00000..128 bytes * 0b01010..128 KB * 0b00111..16384 bytes * 0b00100..2048 bytes * 0b00001..256 bytes * 0b01000..32 KB * 0b00101..4096 bytes * 0b00010..512 bytes * 0b01001..64 KB * 0b00110..8192 bytes * 0b01011..Reserved */ #define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK) #define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) #define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U) /*! TXQCNT - Number of MTL Transmit Queues * 0b0000..1 MTL Tx Queue * 0b0001..2 MTL Tx Queues * 0b0010..3 MTL Tx Queues * 0b0011..4 MTL Tx Queues * 0b0100..5 MTL Tx Queues * 0b0101..6 MTL Tx Queues * 0b0110..7 MTL Tx Queues * 0b0111..8 MTL Tx Queues */ #define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK) #define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U) #define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U) /*! MGKSEL - PMT Magic Packet Enable * 0b1..PMT Magic Packet Enable option is selected * 0b0..PMT Magic Packet Enable option is not selected */ #define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK) #define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U) #define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U) /*! MMCSEL - RMON Module Enable * 0b1..RMON Module Enable option is selected * 0b0..RMON Module Enable option is not selected */ #define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK) #define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) #define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) /*! ARPOFFSEL - ARP Offload Enabled * 0b1..ARP Offload Enable option is selected * 0b0..ARP Offload Enable option is not selected */ #define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK) #define ENET_MAC_HW_FEAT_PDUPSEL_MASK (0x200U) #define ENET_MAC_HW_FEAT_PDUPSEL_SHIFT (9U) /*! PDUPSEL - Broadcast/Multicast Packet Duplication * 0b1..Broadcast/Multicast Packet Duplication feature is selected * 0b0..Broadcast/Multicast Packet Duplication feature is not selected */ #define ENET_MAC_HW_FEAT_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_MAC_HW_FEAT_PDUPSEL_MASK) #define ENET_MAC_HW_FEAT_FRPSEL_MASK (0x400U) #define ENET_MAC_HW_FEAT_FRPSEL_SHIFT (10U) /*! FRPSEL - Flexible Receive Parser Selected * 0b1..Flexible Receive Parser feature is selected * 0b0..Flexible Receive Parser feature is not selected */ #define ENET_MAC_HW_FEAT_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_MAC_HW_FEAT_FRPSEL_MASK) #define ENET_MAC_HW_FEAT_FRPBS_MASK (0x1800U) #define ENET_MAC_HW_FEAT_FRPBS_SHIFT (11U) /*! FRPBS - Flexible Receive Parser Buffer size * 0b01..128 Bytes * 0b10..256 Bytes * 0b00..64 Bytes * 0b11..Reserved */ #define ENET_MAC_HW_FEAT_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_MAC_HW_FEAT_FRPBS_MASK) #define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U) #define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U) /*! OSTEN - One-Step Timestamping Enable * 0b1..One-Step Timestamping feature is selected * 0b0..One-Step Timestamping feature is not selected */ #define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK) #define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U) #define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U) /*! PTOEN - PTP Offload Enable * 0b1..PTP Offload feature is selected * 0b0..PTP Offload feature is not selected */ #define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK) #define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) #define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) /*! RXCHCNT - Number of DMA Receive Channels * 0b0000..1 MTL Rx Channel * 0b0001..2 MTL Rx Channels * 0b0010..3 MTL Rx Channels * 0b0011..4 MTL Rx Channels * 0b0100..5 MTL Rx Channels * 0b0101..6 MTL Rx Channels * 0b0110..7 MTL Rx Channels * 0b0111..8 MTL Rx Channels */ #define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK) #define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U) #define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U) /*! TSSEL - IEEE 1588-2008 Timestamp Enabled * 0b1..IEEE 1588-2008 Timestamp Enable option is selected * 0b0..IEEE 1588-2008 Timestamp Enable option is not selected */ #define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK) #define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) #define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) /*! ADVTHWORD - IEEE 1588 High Word Register Enable * 0b1..IEEE 1588 High Word Register option is selected * 0b0..IEEE 1588 High Word Register option is not selected */ #define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK) #define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U) #define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U) /*! EEESEL - Energy Efficient Ethernet Enabled * 0b1..Energy Efficient Ethernet Enable option is selected * 0b0..Energy Efficient Ethernet Enable option is not selected */ #define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK) #define ENET_MAC_HW_FEAT_FRPES_MASK (0x6000U) #define ENET_MAC_HW_FEAT_FRPES_SHIFT (13U) /*! FRPES - Flexible Receive Parser Table Entries size * 0b01..128 Entries * 0b10..256 Entries * 0b00..64 Entries * 0b11..Reserved */ #define ENET_MAC_HW_FEAT_FRPES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_MAC_HW_FEAT_FRPES_MASK) #define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U) #define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U) /*! ADDR64 - Address Width. * 0b00..32 * 0b01..40 * 0b10..48 * 0b11..Reserved */ #define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK) #define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) #define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) /*! TXCOESEL - Transmit Checksum Offload Enabled * 0b1..Transmit Checksum Offload Enable option is selected * 0b0..Transmit Checksum Offload Enable option is not selected */ #define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK) #define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U) #define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U) /*! DCBEN - DCB Feature Enable * 0b1..DCB Feature is selected * 0b0..DCB Feature is not selected */ #define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK) #define ENET_MAC_HW_FEAT_ESTSEL_MASK (0x10000U) #define ENET_MAC_HW_FEAT_ESTSEL_SHIFT (16U) /*! ESTSEL - Enhancements to Scheduled Traffic Enable * 0b1..Enable Enhancements to Scheduling Traffic feature is selected * 0b0..Enable Enhancements to Scheduling Traffic feature is not selected */ #define ENET_MAC_HW_FEAT_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_MAC_HW_FEAT_ESTSEL_MASK) #define ENET_MAC_HW_FEAT_RDCSZ_MASK (0x30000U) #define ENET_MAC_HW_FEAT_RDCSZ_SHIFT (16U) /*! RDCSZ - Rx DMA Descriptor Cache Size in terms of 16 bytes descriptors: */ #define ENET_MAC_HW_FEAT_RDCSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RDCSZ_SHIFT)) & ENET_MAC_HW_FEAT_RDCSZ_MASK) #define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) #define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) /*! RXCOESEL - Receive Checksum Offload Enabled * 0b1..Receive Checksum Offload Enable option is selected * 0b0..Receive Checksum Offload Enable option is not selected */ #define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK) #define ENET_MAC_HW_FEAT_ESTDEP_MASK (0xE0000U) #define ENET_MAC_HW_FEAT_ESTDEP_SHIFT (17U) /*! ESTDEP - Depth of the Gate Control List * 0b101..1024 * 0b010..128 * 0b011..256 * 0b100..512 * 0b001..64 * 0b000..No Depth configured * 0b110..Reserved */ #define ENET_MAC_HW_FEAT_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_MAC_HW_FEAT_ESTDEP_MASK) #define ENET_MAC_HW_FEAT_SPHEN_MASK (0x20000U) #define ENET_MAC_HW_FEAT_SPHEN_SHIFT (17U) /*! SPHEN - Split Header Feature Enable * 0b1..Split Header Feature is selected * 0b0..Split Header Feature is not selected */ #define ENET_MAC_HW_FEAT_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_MAC_HW_FEAT_SPHEN_MASK) #define ENET_MAC_HW_FEAT_ADDMACADRSEL_MASK (0x7C0000U) #define ENET_MAC_HW_FEAT_ADDMACADRSEL_SHIFT (18U) /*! ADDMACADRSEL - MAC Addresses 1-31 Selected */ #define ENET_MAC_HW_FEAT_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_MAC_HW_FEAT_ADDMACADRSEL_MASK) #define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U) #define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U) /*! TSOEN - TCP Segmentation Offload Enable * 0b1..TCP Segmentation Offload Feature is selected * 0b0..TCP Segmentation Offload Feature is not selected */ #define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK) #define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) #define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) /*! TXCHCNT - Number of DMA Transmit Channels * 0b0000..1 MTL Tx Channel * 0b0001..2 MTL Tx Channels * 0b0010..3 MTL Tx Channels * 0b0011..4 MTL Tx Channels * 0b0100..5 MTL Tx Channels * 0b0101..6 MTL Tx Channels * 0b0110..7 MTL Tx Channels * 0b0111..8 MTL Tx Channels */ #define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK) #define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) #define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) /*! DBGMEMA - DMA Debug Registers Enable * 0b1..DMA Debug Registers option is selected * 0b0..DMA Debug Registers option is not selected */ #define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK) #define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U) #define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U) /*! AVSEL - AV Feature Enable * 0b1..AV Feature is selected * 0b0..AV Feature is not selected */ #define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK) #define ENET_MAC_HW_FEAT_ESTWID_MASK (0x300000U) #define ENET_MAC_HW_FEAT_ESTWID_SHIFT (20U) /*! ESTWID - Width of the Time Interval field in the Gate Control List * 0b00..Width not configured * 0b01..16 * 0b10..20 * 0b11..24 */ #define ENET_MAC_HW_FEAT_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_MAC_HW_FEAT_ESTWID_MASK) #define ENET_MAC_HW_FEAT_RAVSEL_MASK (0x200000U) #define ENET_MAC_HW_FEAT_RAVSEL_SHIFT (21U) /*! RAVSEL - Rx Side Only AV Feature Enable * 0b1..Rx Side Only AV Feature is selected * 0b0..Rx Side Only AV Feature is not selected */ #define ENET_MAC_HW_FEAT_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_MAC_HW_FEAT_RAVSEL_MASK) #define ENET_MAC_HW_FEAT_TDCSZ_MASK (0xC00000U) #define ENET_MAC_HW_FEAT_TDCSZ_SHIFT (22U) /*! TDCSZ - Tx DMA Descriptor Cache Size in terms of 16 bytes descriptors: */ #define ENET_MAC_HW_FEAT_TDCSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TDCSZ_SHIFT)) & ENET_MAC_HW_FEAT_TDCSZ_MASK) #define ENET_MAC_HW_FEAT_MACADR32SEL_MASK (0x800000U) #define ENET_MAC_HW_FEAT_MACADR32SEL_SHIFT (23U) /*! MACADR32SEL - MAC Addresses 32-63 Selected * 0b1..MAC Addresses 32-63 Select option is selected * 0b0..MAC Addresses 32-63 Select option is not selected */ #define ENET_MAC_HW_FEAT_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_MAC_HW_FEAT_MACADR32SEL_MASK) #define ENET_MAC_HW_FEAT_POUOST_MASK (0x800000U) #define ENET_MAC_HW_FEAT_POUOST_SHIFT (23U) /*! POUOST - One Step for PTP over UDP/IP Feature Enable * 0b1..One Step for PTP over UDP/IP Feature is selected * 0b0..One Step for PTP over UDP/IP Feature is not selected */ #define ENET_MAC_HW_FEAT_POUOST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_MAC_HW_FEAT_POUOST_MASK) #define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) #define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) /*! HASHTBLSZ - Hash Table Size * 0b10..128 * 0b11..256 * 0b01..64 * 0b00..No hash table */ #define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK) #define ENET_MAC_HW_FEAT_MACADR64SEL_MASK (0x1000000U) #define ENET_MAC_HW_FEAT_MACADR64SEL_SHIFT (24U) /*! MACADR64SEL - MAC Addresses 64-127 Selected * 0b1..MAC Addresses 64-127 Select option is selected * 0b0..MAC Addresses 64-127 Select option is not selected */ #define ENET_MAC_HW_FEAT_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_MAC_HW_FEAT_MACADR64SEL_MASK) #define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) #define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) /*! PPSOUTNUM - Number of PPS Outputs * 0b001..1 PPS output * 0b010..2 PPS output * 0b011..3 PPS output * 0b100..4 PPS output * 0b000..No PPS output * 0b101..Reserved */ #define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK) #define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) #define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) /*! TSSTSSEL - Timestamp System Time Source * 0b10..Both * 0b01..External * 0b00..Internal * 0b11..Reserved */ #define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK) #define ENET_MAC_HW_FEAT_FPESEL_MASK (0x4000000U) #define ENET_MAC_HW_FEAT_FPESEL_SHIFT (26U) /*! FPESEL - Frame Preemption Enable * 0b1..Frame Preemption Enable feature is selected * 0b0..Frame Preemption Enable feature is not selected */ #define ENET_MAC_HW_FEAT_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_MAC_HW_FEAT_FPESEL_MASK) #define ENET_MAC_HW_FEAT_L3L4FNUM_MASK (0x78000000U) #define ENET_MAC_HW_FEAT_L3L4FNUM_SHIFT (27U) /*! L3L4FNUM - Total number of L3 or L4 Filters * 0b0001..1 L3 or L4 Filter * 0b0010..2 L3 or L4 Filters * 0b0011..3 L3 or L4 Filters * 0b0100..4 L3 or L4 Filters * 0b0101..5 L3 or L4 Filters * 0b0110..6 L3 or L4 Filters * 0b0111..7 L3 or L4 Filters * 0b1000..8 L3 or L4 Filters * 0b0000..No L3 or L4 Filter */ #define ENET_MAC_HW_FEAT_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_MAC_HW_FEAT_L3L4FNUM_MASK) #define ENET_MAC_HW_FEAT_SAVLANINS_MASK (0x8000000U) #define ENET_MAC_HW_FEAT_SAVLANINS_SHIFT (27U) /*! SAVLANINS - Source Address or VLAN Insertion Enable * 0b1..Source Address or VLAN Insertion Enable option is selected * 0b0..Source Address or VLAN Insertion Enable option is not selected */ #define ENET_MAC_HW_FEAT_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_MAC_HW_FEAT_SAVLANINS_MASK) #define ENET_MAC_HW_FEAT_TBSSEL_MASK (0x8000000U) #define ENET_MAC_HW_FEAT_TBSSEL_SHIFT (27U) /*! TBSSEL - Time Based Scheduling Enable * 0b1..Time Based Scheduling Enable feature is selected * 0b0..Time Based Scheduling Enable feature is not selected */ #define ENET_MAC_HW_FEAT_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TBSSEL_MASK) #define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) #define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) /*! ACTPHYSEL - Active PHY Selected * 0b000..GMII or MII * 0b111..RevMII * 0b001..RGMII * 0b100..RMII * 0b101..RTBI * 0b010..SGMII * 0b110..SMII * 0b011..TBI */ #define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK) #define ENET_MAC_HW_FEAT_ASP_MASK (0x30000000U) #define ENET_MAC_HW_FEAT_ASP_SHIFT (28U) /*! ASP - Automotive Safety Package * 0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature * 0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature * 0b01..Only "ECC protection for external memory" feature is selected * 0b00..No Safety features selected */ #define ENET_MAC_HW_FEAT_ASP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ASP_SHIFT)) & ENET_MAC_HW_FEAT_ASP_MASK) #define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) #define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs * 0b001..1 auxiliary input * 0b010..2 auxiliary input * 0b011..3 auxiliary input * 0b100..4 auxiliary input * 0b000..No auxiliary input * 0b101..Reserved */ #define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK) /*! @} */ /* The count of ENET_MAC_HW_FEAT */ #define ENET_MAC_HW_FEAT_COUNT (4U) /*! @name MAC_MDIO_ADDRESS - MDIO Address */ /*! @{ */ #define ENET_MAC_MDIO_ADDRESS_GB_MASK (0x1U) #define ENET_MAC_MDIO_ADDRESS_GB_SHIFT (0U) /*! GB - GMII Busy * 0b0..GMII Busy is disabled * 0b1..GMII Busy is enabled */ #define ENET_MAC_MDIO_ADDRESS_GB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_MAC_MDIO_ADDRESS_GB_MASK) #define ENET_MAC_MDIO_ADDRESS_C45E_MASK (0x2U) #define ENET_MAC_MDIO_ADDRESS_C45E_SHIFT (1U) /*! C45E - Clause 45 PHY Enable * 0b0..Clause 45 PHY is disabled * 0b1..Clause 45 PHY is enabled */ #define ENET_MAC_MDIO_ADDRESS_C45E(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_MAC_MDIO_ADDRESS_C45E_MASK) #define ENET_MAC_MDIO_ADDRESS_GOC_0_MASK (0x4U) #define ENET_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U) /*! GOC_0 - GMII Operation Command 0 * 0b0..GMII Operation Command 0 is disabled * 0b1..GMII Operation Command 0 is enabled */ #define ENET_MAC_MDIO_ADDRESS_GOC_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_MAC_MDIO_ADDRESS_GOC_0_MASK) #define ENET_MAC_MDIO_ADDRESS_GOC_1_MASK (0x8U) #define ENET_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U) /*! GOC_1 - GMII Operation Command 1 * 0b0..GMII Operation Command 1 is disabled * 0b1..GMII Operation Command 1 is enabled */ #define ENET_MAC_MDIO_ADDRESS_GOC_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_MAC_MDIO_ADDRESS_GOC_1_MASK) #define ENET_MAC_MDIO_ADDRESS_SKAP_MASK (0x10U) #define ENET_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U) /*! SKAP - Skip Address Packet * 0b0..Skip Address Packet is disabled * 0b1..Skip Address Packet is enabled */ #define ENET_MAC_MDIO_ADDRESS_SKAP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_MAC_MDIO_ADDRESS_SKAP_MASK) #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) #define ENET_MAC_MDIO_ADDRESS_CR_SHIFT (8U) /*! CR - CR */ #define ENET_MAC_MDIO_ADDRESS_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK) #define ENET_MAC_MDIO_ADDRESS_NTC_MASK (0x7000U) #define ENET_MAC_MDIO_ADDRESS_NTC_SHIFT (12U) /*! NTC - NTC */ #define ENET_MAC_MDIO_ADDRESS_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_MAC_MDIO_ADDRESS_NTC_MASK) #define ENET_MAC_MDIO_ADDRESS_RDA_MASK (0x1F0000U) #define ENET_MAC_MDIO_ADDRESS_RDA_SHIFT (16U) /*! RDA - Register/Device Address */ #define ENET_MAC_MDIO_ADDRESS_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_MAC_MDIO_ADDRESS_RDA_MASK) #define ENET_MAC_MDIO_ADDRESS_PA_MASK (0x3E00000U) #define ENET_MAC_MDIO_ADDRESS_PA_SHIFT (21U) /*! PA - Physical Layer Address */ #define ENET_MAC_MDIO_ADDRESS_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_MAC_MDIO_ADDRESS_PA_MASK) #define ENET_MAC_MDIO_ADDRESS_BTB_MASK (0x4000000U) #define ENET_MAC_MDIO_ADDRESS_BTB_SHIFT (26U) /*! BTB - Back to Back transactions * 0b0..Back to Back transactions disabled * 0b1..Back to Back transactions enabled */ #define ENET_MAC_MDIO_ADDRESS_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_MAC_MDIO_ADDRESS_BTB_MASK) #define ENET_MAC_MDIO_ADDRESS_PSE_MASK (0x8000000U) #define ENET_MAC_MDIO_ADDRESS_PSE_SHIFT (27U) /*! PSE - Preamble Suppression Enable * 0b0..Preamble Suppression disabled * 0b1..Preamble Suppression enabled */ #define ENET_MAC_MDIO_ADDRESS_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_MAC_MDIO_ADDRESS_PSE_MASK) /*! @} */ /*! @name MAC_MDIO_DATA - MAC MDIO Data */ /*! @{ */ #define ENET_MAC_MDIO_DATA_GD_MASK (0xFFFFU) #define ENET_MAC_MDIO_DATA_GD_SHIFT (0U) /*! GD - GMII Data */ #define ENET_MAC_MDIO_DATA_GD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_GD_SHIFT)) & ENET_MAC_MDIO_DATA_GD_MASK) #define ENET_MAC_MDIO_DATA_RA_MASK (0xFFFF0000U) #define ENET_MAC_MDIO_DATA_RA_SHIFT (16U) /*! RA - Register Address */ #define ENET_MAC_MDIO_DATA_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_RA_SHIFT)) & ENET_MAC_MDIO_DATA_RA_MASK) /*! @} */ /*! @name MAC_CSR_SW_CTRL - CSR Software Control */ /*! @{ */ #define ENET_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U) #define ENET_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U) /*! RCWE - Register Clear on Write 1 Enable * 0b0..Register Clear on Write 1 is disabled * 0b1..Register Clear on Write 1 is enabled */ #define ENET_MAC_CSR_SW_CTRL_RCWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_MAC_CSR_SW_CTRL_RCWE_MASK) /*! @} */ /*! @name MAC_ADDRESS0_HIGH - MAC Address0 High */ /*! @{ */ #define ENET_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFFU) #define ENET_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0U) /*! ADDRHI - MAC Address0[47:32] */ #define ENET_MAC_ADDRESS0_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT)) & ENET_MAC_ADDRESS0_HIGH_ADDRHI_MASK) #define ENET_MAC_ADDRESS0_HIGH_DCS_MASK (0x30000U) #define ENET_MAC_ADDRESS0_HIGH_DCS_SHIFT (16U) /*! DCS - DMA Channel Select */ #define ENET_MAC_ADDRESS0_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDRESS0_HIGH_DCS_SHIFT)) & ENET_MAC_ADDRESS0_HIGH_DCS_MASK) #define ENET_MAC_ADDRESS0_HIGH_AE_MASK (0x80000000U) #define ENET_MAC_ADDRESS0_HIGH_AE_SHIFT (31U) /*! AE - Address Enable * 0b0..INVALID : This bit must be always set to 1 * 0b1..This bit is always set to 1 */ #define ENET_MAC_ADDRESS0_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDRESS0_HIGH_AE_SHIFT)) & ENET_MAC_ADDRESS0_HIGH_AE_MASK) /*! @} */ /*! @name MAC_ADDRESS0_LOW - MAC Address0 Low */ /*! @{ */ #define ENET_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFFU) #define ENET_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0U) /*! ADDRLO - MAC Address0[31:0] */ #define ENET_MAC_ADDRESS0_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDRESS0_LOW_ADDRLO_SHIFT)) & ENET_MAC_ADDRESS0_LOW_ADDRLO_MASK) /*! @} */ /*! @name INDIR_ACCESS_CTRL - Indirect Access Control */ /*! @{ */ #define ENET_INDIR_ACCESS_CTRL_OB_MASK (0x1U) #define ENET_INDIR_ACCESS_CTRL_OB_SHIFT (0U) /*! OB - Operation Busy. */ #define ENET_INDIR_ACCESS_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_OB_SHIFT)) & ENET_INDIR_ACCESS_CTRL_OB_MASK) #define ENET_INDIR_ACCESS_CTRL_COM_MASK (0x2U) #define ENET_INDIR_ACCESS_CTRL_COM_SHIFT (1U) /*! COM - Command type * 0b1..Read operation * 0b0..Write operation */ #define ENET_INDIR_ACCESS_CTRL_COM(x) (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_COM_SHIFT)) & ENET_INDIR_ACCESS_CTRL_COM_MASK) #define ENET_INDIR_ACCESS_CTRL_AUTO_MASK (0x20U) #define ENET_INDIR_ACCESS_CTRL_AUTO_SHIFT (5U) /*! AUTO - Auto increment */ #define ENET_INDIR_ACCESS_CTRL_AUTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_AUTO_SHIFT)) & ENET_INDIR_ACCESS_CTRL_AUTO_MASK) #define ENET_INDIR_ACCESS_CTRL_AOFF_MASK (0xFF00U) #define ENET_INDIR_ACCESS_CTRL_AOFF_SHIFT (8U) /*! AOFF - Address Offset */ #define ENET_INDIR_ACCESS_CTRL_AOFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_AOFF_SHIFT)) & ENET_INDIR_ACCESS_CTRL_AOFF_MASK) #define ENET_INDIR_ACCESS_CTRL_MSEL_MASK (0xF0000U) #define ENET_INDIR_ACCESS_CTRL_MSEL_SHIFT (16U) /*! MSEL - Mode Select */ #define ENET_INDIR_ACCESS_CTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_CTRL_MSEL_SHIFT)) & ENET_INDIR_ACCESS_CTRL_MSEL_MASK) /*! @} */ /*! @name INDIR_ACCESS_DATA - Indirect Access Data */ /*! @{ */ #define ENET_INDIR_ACCESS_DATA_DATA_MASK (0xFFFFFFFFU) #define ENET_INDIR_ACCESS_DATA_DATA_SHIFT (0U) /*! DATA - This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl */ #define ENET_INDIR_ACCESS_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_INDIR_ACCESS_DATA_DATA_SHIFT)) & ENET_INDIR_ACCESS_DATA_DATA_MASK) /*! @} */ /*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */ /*! @{ */ #define ENET_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U) #define ENET_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U) /*! TSENA - Enable Timestamp * 0b0..Timestamp is disabled * 0b1..Timestamp is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSENA_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U) #define ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U) /*! TSCFUPDT - Fine or Coarse Timestamp Update * 0b0..Coarse method is used to update system timestamp * 0b1..Fine method is used to update system timestamp */ #define ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U) #define ENET_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U) /*! TSINIT - Initialize Timestamp * 0b0..Timestamp is not initialized * 0b1..Timestamp is initialized */ #define ENET_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U) #define ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U) /*! TSUPDT - Update Timestamp * 0b0..Timestamp is not updated * 0b1..Timestamp is updated */ #define ENET_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSTRIG_MASK (0x10U) #define ENET_MAC_TIMESTAMP_CONTROL_TSTRIG_SHIFT (4U) /*! TSTRIG - Enable Timestamp Interrupt Trigger * 0b0..Timestamp Interrupt Trigger is not enabled * 0b1..Timestamp Interrupt Trigger is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSTRIG_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U) #define ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U) /*! TSADDREG - Update Addend Register * 0b0..Addend Register is not updated * 0b1..Addend Register is updated */ #define ENET_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U) #define ENET_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U) /*! TSENALL - Enable Timestamp for All Packets * 0b0..Timestamp for All Packets disabled * 0b1..Timestamp for All Packets enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSENALL_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U) #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U) /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control * 0b0..Timestamp Digital Rollover Control is disabled and Binary Rollover Control is enabled * 0b1..Timestamp Digital Rollover Control is enabled and Binary Rollover Control is disabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U) #define ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U) /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format * 0b0..PTP Packet Processing for Version 2 Format is disabled * 0b1..PTP Packet Processing for Version 2 Format is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U) #define ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U) /*! TSIPENA - Enable Processing of PTP over Ethernet Packets * 0b0..Processing of PTP over Ethernet Packets is disabled * 0b1..Processing of PTP over Ethernet Packets is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U) #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U) /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP * 0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled * 0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U) #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U) /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP * 0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled * 0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U) #define ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U) /*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages * 0b0..Timestamp Snapshot for Event Messages is disabled * 0b1..Timestamp Snapshot for Event Messages is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U) #define ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U) /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master * 0b0..Snapshot for Messages Relevant to Master is disabled * 0b1..Snapshot for Messages Relevant to Master is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U) #define ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U) /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots */ #define ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U) #define ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U) /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering * 0b0..MAC Address for PTP Packet Filtering is disabled * 0b1..MAC Address for PTP Packet Filtering is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U) #define ENET_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U) /*! ESTI - External System Time Input * 0b0..External System Time Input is disabled * 0b1..External System Time Input is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_ESTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_ESTI_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U) #define ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U) /*! TXTSSTSM - Transmit Timestamp Status Mode * 0b0..Transmit Timestamp Status Mode is disabled * 0b1..Transmit Timestamp Status Mode is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK) #define ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U) #define ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U) /*! AV8021ASMEN - AV 802. * 0b0..AV 802.1AS Mode is disabled * 0b1..AV 802.1AS Mode is enabled */ #define ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK) /*! @} */ /*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */ /*! @{ */ #define ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF0000U) #define ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (16U) /*! SNSINC - Sub-nanosecond Increment Value */ #define ENET_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) /*! @} */ /*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */ /*! @{ */ #define ENET_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU) #define ENET_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U) /*! TSS - Timestamp Second */ #define ENET_MAC_SYSTEM_TIME_SECONDS_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_MAC_SYSTEM_TIME_SECONDS_TSS_MASK) /*! @} */ /*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */ /*! @{ */ #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU) #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U) /*! TSSS - Timestamp Sub Seconds */ #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK) /*! @} */ /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */ /*! @{ */ #define ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU) #define ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U) /*! TSS - Timestamp Seconds */ #define ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK) /*! @} */ /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */ /*! @{ */ #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU) #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U) /*! TSSS - Timestamp Sub Seconds */ #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U) #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U) /*! ADDSUB - Add or Subtract Time * 0b0..Add time * 0b1..Subtract time */ #define ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK) /*! @} */ /*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */ /*! @{ */ #define ENET_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) #define ENET_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U) /*! TSAR - Timestamp Addend Register */ #define ENET_MAC_TIMESTAMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_TIMESTAMP_ADDEND_TSAR_MASK) /*! @} */ /*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */ /*! @{ */ #define ENET_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U) #define ENET_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U) /*! TSSOVF - Timestamp Seconds Overflow * 0b1..Timestamp Seconds Overflow status detected * 0b0..Timestamp Seconds Overflow status not detected */ #define ENET_MAC_TIMESTAMP_STATUS_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_MAC_TIMESTAMP_STATUS_TSSOVF_MASK) #define ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U) #define ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U) /*! TSTARGT0 - Timestamp Target Time Reached * 0b1..Timestamp Target Time Reached status detected * 0b0..Timestamp Target Time Reached status not detected */ #define ENET_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK) #define ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U) #define ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U) /*! TSTRGTERR0 - Timestamp Target Time Error * 0b1..Timestamp Target Time Error status detected * 0b0..Timestamp Target Time Error status not detected */ #define ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK) #define ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U) #define ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U) /*! TXTSSIS - Tx Timestamp Status Interrupt Status * 0b1..Tx Timestamp Status Interrupt status detected * 0b0..Tx Timestamp Status Interrupt status not detected */ #define ENET_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK) /*! @} */ /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */ /*! @{ */ #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU) #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U) /*! TXTSSLO - Transmit Timestamp Status Low */ #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK) #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U) #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U) /*! TXTSSMIS - TXTSSMIS * 0b1..Transmit Timestamp Status Missed status detected * 0b0..Transmit Timestamp Status Missed status not detected */ #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK) /*! @} */ /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */ /*! @{ */ #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU) #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U) /*! TXTSSHI - Transmit Timestamp Status High */ #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK) /*! @} */ /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */ /*! @{ */ #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) /*! TSIC - Timestamp Ingress Correction */ #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) /*! @} */ /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */ /*! @{ */ #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) /*! TSEC - Timestamp Egress Correction */ #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) /*! @} */ /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */ /*! @{ */ #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U) #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U) /*! ITLSNS - ITLSNS */ #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U) #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U) /*! ITLNS - ITLNS */ #define ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK) /*! @} */ /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */ /*! @{ */ #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U) #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U) /*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds */ #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U) #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U) /*! ETLNS - Egress Timestamp Latency, in nanoseconds */ #define ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK) /*! @} */ /*! @name MAC_PPS_CONTROL - PPS Control */ /*! @{ */ #define ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU) #define ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U) /*! PPSCTRL_PPSCMD - PPS Output Frequency Control */ #define ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) /*! @} */ /*! @name PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */ /*! @{ */ #define ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU) #define ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U) /*! TSTRH0 - PPS Target Time Seconds Register */ #define ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK) /*! @} */ /*! @name PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */ /*! @{ */ #define ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU) #define ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U) /*! TTSL0 - Target Time Low for PPS Register */ #define ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK) /*! @} */ /*! @name MTL_OPERATION_MODE - MTL Operation Mode */ /*! @{ */ #define ENET_MTL_OPERATION_MODE_DTXSTS_MASK (0x2U) #define ENET_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U) /*! DTXSTS - Drop Transmit Status * 0b0..Drop Transmit Status is disabled * 0b1..Drop Transmit Status is enabled */ #define ENET_MTL_OPERATION_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_MTL_OPERATION_MODE_DTXSTS_MASK) #define ENET_MTL_OPERATION_MODE_RAA_MASK (0x4U) #define ENET_MTL_OPERATION_MODE_RAA_SHIFT (2U) /*! RAA - Receive Arbitration Algorithm * 0b0..Strict priority (SP) * 0b1..Weighted Strict Priority (WSP) */ #define ENET_MTL_OPERATION_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_MTL_OPERATION_MODE_RAA_MASK) #define ENET_MTL_OPERATION_MODE_SCHALG_MASK (0x60U) #define ENET_MTL_OPERATION_MODE_SCHALG_SHIFT (5U) /*! SCHALG - Tx Scheduling Algorithm * 0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved * 0b11..Strict priority algorithm * 0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved * 0b00..WRR algorithm */ #define ENET_MTL_OPERATION_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_MTL_OPERATION_MODE_SCHALG_MASK) #define ENET_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U) #define ENET_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U) /*! CNTPRST - Counters Preset * 0b0..Counters Preset is disabled * 0b1..Counters Preset is enabled */ #define ENET_MTL_OPERATION_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_MTL_OPERATION_MODE_CNTPRST_MASK) #define ENET_MTL_OPERATION_MODE_CNTCLR_MASK (0x200U) #define ENET_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U) /*! CNTCLR - Counters Reset * 0b0..Counters are not reset * 0b1..All counters are reset */ #define ENET_MTL_OPERATION_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_MTL_OPERATION_MODE_CNTCLR_MASK) /*! @} */ /*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */ /*! @{ */ #define ENET_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U) #define ENET_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U) /*! Q0IS - Queue 0 Interrupt status * 0b1..Queue 0 Interrupt status detected * 0b0..Queue 0 Interrupt status not detected */ #define ENET_MTL_INTERRUPT_STATUS_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_MTL_INTERRUPT_STATUS_Q0IS_MASK) #define ENET_MTL_INTERRUPT_STATUS_Q1IS_MASK (0x2U) #define ENET_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U) /*! Q1IS - Queue 1 Interrupt status * 0b1..Queue 1 Interrupt status detected * 0b0..Queue 1 Interrupt status not detected */ #define ENET_MTL_INTERRUPT_STATUS_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_MTL_INTERRUPT_STATUS_Q1IS_MASK) /*! @} */ /*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */ /*! @{ */ #define ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK (0x1U) #define ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U) /*! Q0MDMACH - Queue 0 Mapped to DMA Channel */ #define ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK) #define ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK (0x10U) #define ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U) /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection * 0b0..Queue 0 disabled for DA-based DMA Channel Selection * 0b1..Queue 0 enabled for DA-based DMA Channel Selection */ #define ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK) #define ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK (0x100U) #define ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U) /*! Q1MDMACH - Queue 1 Mapped to DMA Channel */ #define ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK) #define ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK (0x1000U) #define ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U) /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection * 0b0..Queue 1 disabled for DA-based DMA Channel Selection * 0b1..Queue 1 enabled for DA-based DMA Channel Selection */ #define ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK) /*! @} */ /*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 1 Transmit Operation Mode */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) /*! FTQ - Flush Transmit Queue * 0b0..Flush Transmit Queue is disabled * 0b1..Flush Transmit Queue is enabled */ #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) /*! TSF - Transmit Store and Forward * 0b0..Transmit Store and Forward is disabled * 0b1..Transmit Store and Forward is enabled */ #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) /*! TXQEN - Transmit Queue Enable * 0b00..Not enabled * 0b10..Enabled * 0b01..Enable in AV mode (Reserved in non-AV) * 0b11..Reserved */ #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) /*! TTC - Transmit Threshold Control * 0b011..128 * 0b100..192 * 0b101..256 * 0b000..32 * 0b110..384 * 0b111..512 * 0b001..64 * 0b010..96 */ #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U) #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) /*! TQS - Transmit Queue Size */ #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */ #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U) /*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 1 Underflow Counter */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) /*! UFFRMCNT - Underflow Packet Counter */ #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter * 0b1..Overflow detected for Underflow Packet Counter * 0b0..Overflow not detected for Underflow Packet Counter */ #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */ #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U) /*! @name MTL_QUEUE_MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 1 Transmit Debug */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) /*! TXQPAUSED - Transmit Queue in Pause * 0b1..Transmit Queue in Pause status is detected * 0b0..Transmit Queue in Pause status is not detected */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) /*! TRCSTS - MTL Tx Queue Read Controller Status * 0b11..Flushing the Tx queue because of the Packet Abort request from the MAC * 0b00..Idle state * 0b01..Read state (transferring data to the MAC transmitter) * 0b10..Waiting for pending Tx Status from the MAC transmitter */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) /*! TWCSTS - MTL Tx Queue Write Controller Status * 0b1..MTL Tx Queue Write Controller status is detected * 0b0..MTL Tx Queue Write Controller status is not detected */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) /*! TXQSTS - MTL Tx Queue Not Empty Status * 0b1..MTL Tx Queue Not Empty status is detected * 0b0..MTL Tx Queue Not Empty status is not detected */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) /*! TXSTSFSTS - MTL Tx Status FIFO Full Status * 0b1..MTL Tx Status FIFO Full status is detected * 0b0..MTL Tx Status FIFO Full status is not detected */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U) /*! PTXQ - Number of Packets in the Transmit Queue */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF_MASK (0x700000U) #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF_SHIFT (20U) /*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STXSTSF_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */ #define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U) /*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - Queue 1 ETS Control */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) /*! AVALG - AV Algorithm * 0b0..CBS Algorithm is disabled * 0b1..CBS Algorithm is enabled */ #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) /*! CC - Credit Control * 0b0..Credit Control is disabled * 0b1..Credit Control is enabled */ #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK) #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) /*! SLC - Slot Count * 0b100..16 slots * 0b000..1 slot * 0b001..2 slots * 0b010..4 slots * 0b011..8 slots * 0b101..Reserved */ #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */ #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U) /*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 1 ETS Status */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) /*! ABS - Average Bits per Slot */ #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */ #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U) /*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 1 idleSlopeCredit, Quantum or Weights */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) /*! ISCQW - idleSlopeCredit, Quantum or Weights */ #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */ #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U) /*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) /*! SSC - sendSlopeCredit Value */ #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */ #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U) /*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - Queue 1 hiCredit */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) /*! HC - hiCredit Value */ #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */ #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U) /*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - Queue 1 loCredit */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) /*! LC - loCredit Value */ #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */ #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U) /*! @name MTL_QUEUE_MTL_QX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 1 Interrupt Control Status */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) /*! TXUNFIS - Transmit Queue Underflow Interrupt Status * 0b1..Transmit Queue Underflow Interrupt Status detected * 0b0..Transmit Queue Underflow Interrupt Status not detected */ #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUNFIS_MASK) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS_MASK (0x2U) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS_SHIFT (1U) /*! ABPSIS - Average Bits Per Slot Interrupt Status * 0b1..Average Bits Per Slot Interrupt Status detected * 0b0..Average Bits Per Slot Interrupt Status not detected */ #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIS_MASK) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE_MASK (0x100U) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE_SHIFT (8U) /*! TXUIE - Transmit Queue Underflow Interrupt Enable * 0b0..Transmit Queue Underflow Interrupt Status is disabled * 0b1..Transmit Queue Underflow Interrupt Status is enabled */ #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_TXUIE_MASK) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE_MASK (0x200U) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE_SHIFT (9U) /*! ABPSIE - Average Bits Per Slot Interrupt Enable * 0b0..Average Bits Per Slot Interrupt is disabled * 0b1..Average Bits Per Slot Interrupt is enabled */ #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_ABPSIE_MASK) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) /*! RXOVFIS - Receive Queue Overflow Interrupt Status * 0b1..Receive Queue Overflow Interrupt Status detected * 0b0..Receive Queue Overflow Interrupt Status not detected */ #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOVFIS_MASK) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE_SHIFT (24U) /*! RXOIE - Receive Queue Overflow Interrupt Enable * 0b0..Receive Queue Overflow Interrupt is disabled * 0b1..Receive Queue Overflow Interrupt is enabled */ #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_RXOIE_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT */ #define ENET_MTL_QUEUE_MTL_QX_INTCTRL_STAT_COUNT (2U) /*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 1 Receive Operation Mode */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) /*! RTC - Receive Queue Threshold Control * 0b11..128 * 0b01..32 * 0b00..64 * 0b10..96 */ #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) /*! FUP - Forward Undersized Good Packets * 0b0..Forward Undersized Good Packets is disabled * 0b1..Forward Undersized Good Packets is enabled */ #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) /*! FEP - Forward Error Packets * 0b0..Forward Error Packets is disabled * 0b1..Forward Error Packets is enabled */ #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) /*! RSF - Receive Queue Store and Forward * 0b0..Receive Queue Store and Forward is disabled * 0b1..Receive Queue Store and Forward is enabled */ #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets * 0b1..Dropping of TCP/IP Checksum Error Packets is disabled * 0b0..Dropping of TCP/IP Checksum Error Packets is enabled */ #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U) #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) /*! RQS - Receive Queue Size */ #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */ #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U) /*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 1 Missed Packet and Overflow Counter */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) /*! OVFPKTCNT - Overflow Packet Counter */ #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) /*! OVFCNTOVF - Overflow Counter Overflow Bit * 0b1..Overflow Counter overflow detected * 0b0..Overflow Counter overflow not detected */ #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U) #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U) /*! MISPKTCNT - Missed Packet Counter */ #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U) #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U) /*! MISCNTOVF - Missed Packet Counter Overflow Bit * 0b1..Missed Packet Counter overflow detected * 0b0..Missed Packet Counter overflow not detected */ #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */ #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U) /*! @name MTL_QUEUE_MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 1 Receive Debug */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) /*! RWCSTS - MTL Rx Queue Write Controller Active Status * 0b1..MTL Rx Queue Write Controller Active Status detected * 0b0..MTL Rx Queue Write Controller Active Status not detected */ #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) /*! RRCSTS - MTL Rx Queue Read Controller State * 0b11..Flushing the packet data and status * 0b00..Idle state * 0b01..Reading packet data * 0b10..Reading packet status (or timestamp) */ #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) /*! RXQSTS - MTL Rx Queue Fill-Level Status * 0b10..Rx Queue fill-level above flow-control activate threshold * 0b01..Rx Queue fill-level below flow-control deactivate threshold * 0b00..Rx Queue empty * 0b11..Rx Queue full */ #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U) /*! PRXQ - Number of Packets in Receive Queue */ #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */ #define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U) /*! @name MTL_QUEUE_MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 1 Receive Control */ /*! @{ */ #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) /*! RXQ_WEGT - Receive Queue Weight */ #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK) #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration * 0b0..Receive Queue Packet Arbitration is disabled * 0b1..Receive Queue Packet Arbitration is enabled */ #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK) /*! @} */ /* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */ #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U) /*! @name DMA_MODE - DMA Bus Mode */ /*! @{ */ #define ENET_DMA_MODE_SWR_MASK (0x1U) #define ENET_DMA_MODE_SWR_SHIFT (0U) /*! SWR - Software Reset * 0b0..Software Reset is disabled * 0b1..Software Reset is enabled */ #define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK) #define ENET_DMA_MODE_DA_MASK (0x2U) #define ENET_DMA_MODE_DA_SHIFT (1U) /*! DA - DMA Tx or Rx Arbitration Scheme * 0b1..Fixed Priority * 0b0..Weighted Round-Robin with Rx:Tx or Tx:Rx */ #define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK) #define ENET_DMA_MODE_TAA_MASK (0x1CU) #define ENET_DMA_MODE_TAA_SHIFT (2U) /*! TAA - Transmit Arbitration Algorithm * 0b000..Fixed priority * 0b011..Reserved (for 3'b011 to 3'b111) * 0b010..Weighted Round-Robin (WRR) * 0b001..Weighted Strict Priority (WSP) */ #define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK) #define ENET_DMA_MODE_TXPR_MASK (0x800U) #define ENET_DMA_MODE_TXPR_SHIFT (11U) /*! TXPR - Transmit Priority * 0b0..Transmit Priority is disabled * 0b1..Transmit Priority is enabled */ #define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK) #define ENET_DMA_MODE_PR_MASK (0x7000U) #define ENET_DMA_MODE_PR_SHIFT (12U) /*! PR - Priority Ratio * 0b000..The priority ratio is 1:1 * 0b001..The priority ratio is 2:1 * 0b010..The priority ratio is 3:1 * 0b011..The priority ratio is 4:1 * 0b100..The priority ratio is 5:1 * 0b101..The priority ratio is 6:1 * 0b110..The priority ratio is 7:1 * 0b111..The priority ratio is 8:1 */ #define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK) /*! @} */ /*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */ /*! @{ */ #define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U) #define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U) /*! FB - Fixed Burst Length * 0b0..Fixed Burst Length is disabled * 0b1..Fixed Burst Length is enabled */ #define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK) #define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) #define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U) /*! AAL - Address-Aligned Beats * 0b0..Address-Aligned Beats is disabled * 0b1..Address-Aligned Beats is enabled */ #define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK) #define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U) #define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U) /*! MB - Mixed Burst * 0b0..Mixed Burst is disabled * 0b1..Mixed Burst is enabled */ #define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK) #define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U) #define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U) /*! RB - Rebuild INCRx Burst * 0b0..Rebuild INCRx Burst is disabled * 0b1..Rebuild INCRx Burst is enabled */ #define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK) /*! @} */ /*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */ /*! @{ */ #define ENET_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U) #define ENET_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) /*! DC0IS - DMA Channel 0 Interrupt Status * 0b1..DMA Channel 0 Interrupt Status detected * 0b0..DMA Channel 0 Interrupt Status not detected */ #define ENET_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_DMA_INTERRUPT_STATUS_DC0IS_MASK) #define ENET_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U) #define ENET_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U) /*! DC1IS - DMA Channel 1 Interrupt Status * 0b1..DMA Channel 1 Interrupt Status detected * 0b0..DMA Channel 1 Interrupt Status not detected */ #define ENET_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_DMA_INTERRUPT_STATUS_DC1IS_MASK) #define ENET_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U) #define ENET_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) /*! MTLIS - MTL Interrupt Status * 0b1..MTL Interrupt Status detected * 0b0..MTL Interrupt Status not detected */ #define ENET_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_DMA_INTERRUPT_STATUS_MTLIS_MASK) #define ENET_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U) #define ENET_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) /*! MACIS - MAC Interrupt Status * 0b1..MAC Interrupt Status detected * 0b0..MAC Interrupt Status not detected */ #define ENET_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_DMA_INTERRUPT_STATUS_MACIS_MASK) /*! @} */ /*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */ /*! @{ */ #define ENET_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U) #define ENET_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) /*! AXWHSTS - AHB Master Status * 0b1..AXI Master Write Channel or AHB Master Status detected * 0b0..AXI Master Write Channel or AHB Master Status not detected */ #define ENET_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_DMA_DEBUG_STATUS0_AXWHSTS_MASK) #define ENET_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U) #define ENET_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) /*! RPS0 - DMA Channel 0 Receive Process State * 0b0010..Reserved for future use * 0b0101..Running (Closing the Rx Descriptor) * 0b0001..Running (Fetching Rx Transfer Descriptor) * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) * 0b0011..Running (Waiting for Rx packet) * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0100..Suspended (Rx Descriptor Unavailable) * 0b0110..Timestamp write state */ #define ENET_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_DMA_DEBUG_STATUS0_RPS0_MASK) #define ENET_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U) #define ENET_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) /*! TPS0 - DMA Channel 0 Transmit Process State * 0b0101..Reserved for future use * 0b0111..Running (Closing Tx Descriptor) * 0b0001..Running (Fetching Tx Transfer Descriptor) * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0010..Running (Waiting for status) * 0b0000..Stopped (Reset or Stop Transmit Command issued) * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) * 0b0100..Timestamp write state */ #define ENET_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_DMA_DEBUG_STATUS0_TPS0_MASK) #define ENET_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U) #define ENET_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U) /*! RPS1 - DMA Channel 1 Receive Process State * 0b0010..Reserved for future use * 0b0101..Running (Closing the Rx Descriptor) * 0b0001..Running (Fetching Rx Transfer Descriptor) * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) * 0b0011..Running (Waiting for Rx packet) * 0b0000..Stopped (Reset or Stop Receive Command issued) * 0b0100..Suspended (Rx Descriptor Unavailable) * 0b0110..Timestamp write state */ #define ENET_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_DMA_DEBUG_STATUS0_RPS1_MASK) #define ENET_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U) #define ENET_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U) /*! TPS1 - DMA Channel 1 Transmit Process State * 0b0101..Reserved for future use * 0b0111..Running (Closing Tx Descriptor) * 0b0001..Running (Fetching Tx Transfer Descriptor) * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) * 0b0010..Running (Waiting for status) * 0b0000..Stopped (Reset or Stop Transmit Command issued) * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) * 0b0100..Timestamp write state */ #define ENET_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_DMA_DEBUG_STATUS0_TPS1_MASK) /*! @} */ /*! @name DMA_CH_DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 1 Control */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U) /*! PBLx8 - 8xPBL mode * 0b0..8xPBL mode is disabled * 0b1..8xPBL mode is enabled */ #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK) #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U) /*! DSL - Descriptor Skip Length */ #define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_CTRL */ #define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U) /*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 1 Transmit Control */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U) /*! ST - Start or Stop Transmission Command * 0b1..Start Transmission Command * 0b0..Stop Transmission Command */ #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U) /*! TCW - Transmit Channel Weight */ #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) /*! OSF - Operate on Second Packet * 0b0..Operate on Second Packet disabled * 0b1..Operate on Second Packet enabled */ #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) /*! TxPBL - Transmit Programmable Burst Length */ #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC_MASK (0x400000U) #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC_SHIFT (22U) /*! ETIC - Early Transmit Interrupt Control * 0b0..Early Transmit Interrupt is disabled * 0b1..Early Transmit Interrupt is enabled */ #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ETIC_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */ #define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U) /*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 1 Receive Control */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U) /*! SR - Start or Stop Receive * 0b1..Start Receive * 0b0..Stop Receive */ #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0_MASK (0x6U) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0_SHIFT (1U) /*! RBSZ_X_0 - Receive Buffer size Low */ #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_X_0_MASK) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y_MASK (0x7FF8U) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y_SHIFT (3U) /*! RBSZ_13_Y - Receive Buffer size High */ #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y_MASK) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) /*! RxPBL - Receive Programmable Burst Length */ #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC_MASK (0x400000U) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC_SHIFT (22U) /*! ERIC - Early Receive Interrupt Control * 0b0..Early Receive Interrupt is disabled * 0b1..Early Receive Interrupt is enabled */ #define ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_ERIC_MASK) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) /*! RPF - Rx Packet Flush. * 0b0..Rx Packet Flush is disabled * 0b1..Rx Packet Flush is enabled */ #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */ #define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U) /*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 1 Tx Descriptor List Address */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFFCU) #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (2U) /*! TDESLA - Start of Transmit List */ #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */ #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U) /*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 1 Rx Descriptor List Address */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFFCU) #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (2U) /*! RDESLA - Start of Receive List */ #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */ #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U) /*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 1 Tx Descriptor Tail Pointer */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU) #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U) /*! TDTP - Transmit Descriptor Tail Pointer */ #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */ #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U) /*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 1 Rx Descriptor Tail Pointer */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU) #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U) /*! RDTP - Receive Descriptor Tail Pointer */ #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */ #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U) /*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 1 Tx Descriptor Ring Length */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) /*! TDRL - Transmit Descriptor Ring Length */ #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */ #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U) /*! @name DMA_CH_DMA_CHX_RX_CONTROL2 - Channeli Receive Control..DMA Channel 1 Receive Control */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_MASK (0x3FFU) #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_SHIFT (0U) /*! RDRL - Receive Descriptor Ring Length */ #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_MASK) #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS_MASK (0xFF0000U) #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS_SHIFT (16U) /*! ARBS - Alternate Receive Buffer Size */ #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CONTROL2_ARBS_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_RX_CONTROL2 */ #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_COUNT (2U) /*! @name DMA_CH_DMA_CHX_INT_EN - Channeli Interrupt Enable..Channel 1 Interrupt Enable */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U) #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U) /*! TIE - Transmit Interrupt Enable * 0b0..Transmit Interrupt is disabled * 0b1..Transmit Interrupt is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_TXSE_MASK (0x2U) #define ENET_DMA_CH_DMA_CHX_INT_EN_TXSE_SHIFT (1U) /*! TXSE - Transmit Stopped Enable * 0b0..Transmit Stopped is disabled * 0b1..Transmit Stopped is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_TXSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TXSE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U) #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U) /*! TBUE - Transmit Buffer Unavailable Enable * 0b0..Transmit Buffer Unavailable is disabled * 0b1..Transmit Buffer Unavailable is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U) #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U) /*! RIE - Receive Interrupt Enable * 0b0..Receive Interrupt is disabled * 0b1..Receive Interrupt is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U) #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U) /*! RBUE - Receive Buffer Unavailable Enable * 0b0..Receive Buffer Unavailable is disabled * 0b1..Receive Buffer Unavailable is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U) #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U) /*! RSE - Receive Stopped Enable * 0b0..Receive Stopped is disabled * 0b1..Receive Stopped is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U) #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U) /*! RWTE - Receive Watchdog Timeout Enable * 0b0..Receive Watchdog Timeout is disabled * 0b1..Receive Watchdog Timeout is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U) #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U) /*! ETIE - Early Transmit Interrupt Enable * 0b0..Early Transmit Interrupt is disabled * 0b1..Early Transmit Interrupt is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U) #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U) /*! ERIE - Early Receive Interrupt Enable * 0b0..Early Receive Interrupt is disabled * 0b1..Early Receive Interrupt is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U) /*! FBEE - Fatal Bus Error Enable * 0b0..Fatal Bus Error is disabled * 0b1..Fatal Bus Error is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_CDEE_MASK (0x2000U) #define ENET_DMA_CH_DMA_CHX_INT_EN_CDEE_SHIFT (13U) /*! CDEE - Context Descriptor Error Enable * 0b0..Context Descriptor Error is disabled * 0b1..Context Descriptor Error is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_CDEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_CDEE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U) #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U) /*! AIE - Abnormal Interrupt Summary Enable * 0b0..Abnormal Interrupt Summary is disabled * 0b1..Abnormal Interrupt Summary is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK) #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U) #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U) /*! NIE - Normal Interrupt Summary Enable * 0b0..Normal Interrupt Summary is disabled * 0b1..Normal Interrupt Summary is enabled */ #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_INT_EN */ #define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U) /*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 1 Receive Interrupt Watchdog Timer */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU) #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U) /*! RWT - Receive Interrupt Watchdog Timer Count */ #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWT_MASK) #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U) #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U) /*! RWTU - Receive Interrupt Watchdog Timer Count Units */ #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */ #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U) /*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 1 Slot Function Control and Status */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) /*! ESC - Enable Slot Comparison * 0b0..Slot Comparison is disabled * 0b1..Slot Comparison is enabled */ #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) /*! ASC - Advance Slot Check * 0b0..Advance Slot Check is disabled * 0b1..Advance Slot Check is enabled */ #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U) #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U) /*! SIV - Slot Interval Value */ #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK) #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) /*! RSN - Reference Slot Number */ #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */ #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U) /*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 1 Current Application Transmit Descriptor */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U) /*! CURTDESAPTR - Application Transmit Descriptor Address Pointer */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U) /*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 1 Current Application Receive Descriptor */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U) /*! CURRDESAPTR - Application Receive Descriptor Address Pointer */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U) /*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 1 Current Application Transmit Buffer Address */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU) #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U) /*! CURTBUFAPTR - Application Transmit Buffer Address Pointer */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U) /*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 1 Current Application Receive Buffer Address */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU) #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U) /*! CURRBUFAPTR - Application Receive Buffer Address Pointer */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */ #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U) /*! @name DMA_CH_DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 1 Status */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U) #define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U) /*! TI - Transmit Interrupt * 0b1..Transmit Interrupt status detected * 0b0..Transmit Interrupt status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U) #define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U) /*! TPS - Transmit Process Stopped * 0b1..Transmit Process Stopped status detected * 0b0..Transmit Process Stopped status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U) #define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U) /*! TBU - Transmit Buffer Unavailable * 0b1..Transmit Buffer Unavailable status detected * 0b0..Transmit Buffer Unavailable status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U) #define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U) /*! RI - Receive Interrupt * 0b1..Receive Interrupt status detected * 0b0..Receive Interrupt status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U) #define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U) /*! RBU - Receive Buffer Unavailable * 0b1..Receive Buffer Unavailable status detected * 0b0..Receive Buffer Unavailable status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U) #define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U) /*! RPS - Receive Process Stopped * 0b1..Receive Process Stopped status detected * 0b0..Receive Process Stopped status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U) #define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U) /*! RWT - Receive Watchdog Timeout * 0b1..Receive Watchdog Timeout status detected * 0b0..Receive Watchdog Timeout status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U) #define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U) /*! ETI - Early Transmit Interrupt * 0b1..Early Transmit Interrupt status detected * 0b0..Early Transmit Interrupt status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U) #define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U) /*! ERI - Early Receive Interrupt * 0b1..Early Receive Interrupt status detected * 0b0..Early Receive Interrupt status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U) #define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U) /*! FBE - Fatal Bus Error * 0b1..Fatal Bus Error status detected * 0b0..Fatal Bus Error status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_CDE_MASK (0x2000U) #define ENET_DMA_CH_DMA_CHX_STAT_CDE_SHIFT (13U) /*! CDE - Context Descriptor Error * 0b1..Context Descriptor Error status detected * 0b0..Context Descriptor Error status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_CDE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_CDE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_CDE_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U) #define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U) /*! AIS - Abnormal Interrupt Summary * 0b1..Abnormal Interrupt Summary status detected * 0b0..Abnormal Interrupt Summary status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U) #define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U) /*! NIS - Normal Interrupt Summary * 0b1..Normal Interrupt Summary status detected * 0b0..Normal Interrupt Summary status not detected */ #define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_TEB_MASK (0x70000U) #define ENET_DMA_CH_DMA_CHX_STAT_TEB_SHIFT (16U) /*! TEB - Tx DMA Error Bits */ #define ENET_DMA_CH_DMA_CHX_STAT_TEB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TEB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TEB_MASK) #define ENET_DMA_CH_DMA_CHX_STAT_REB_MASK (0x380000U) #define ENET_DMA_CH_DMA_CHX_STAT_REB_SHIFT (19U) /*! REB - Rx DMA Error Bits */ #define ENET_DMA_CH_DMA_CHX_STAT_REB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_REB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_REB_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_STAT */ #define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U) /*! @name DMA_CH_DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 1 Missed Frame Counter */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU) #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U) /*! MFC - Dropped Packet Counters */ #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK) #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U) #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U) /*! MFCO - Overflow status of the MFC Counter * 0b1..Miss Frame Counter overflow occurred * 0b0..Miss Frame Counter overflow not occurred */ #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT */ #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_COUNT (2U) /*! @name DMA_CH_DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 1 Receive ERI Counter */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT_MASK (0xFFFU) #define ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT (0U) /*! ECNT - ERI Counter */ #define ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_ECNT_MASK) /*! @} */ /* The count of ENET_DMA_CH_DMA_CHX_RX_ERI_CNT */ #define ENET_DMA_CH_DMA_CHX_RX_ERI_CNT_COUNT (2U) /*! * @} */ /* end of group ENET_Register_Masks */ /* ENET - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral ENET0 base address */ #define ENET0_BASE (0x50100000u) /** Peripheral ENET0 base address */ #define ENET0_BASE_NS (0x40100000u) /** Peripheral ENET0 base pointer */ #define ENET0 ((ENET_Type *)ENET0_BASE) /** Peripheral ENET0 base pointer */ #define ENET0_NS ((ENET_Type *)ENET0_BASE_NS) /** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS { ENET0_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET0 } /** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS_NS { ENET0_BASE_NS } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS_NS { ENET0_NS } #else /** Peripheral ENET0 base address */ #define ENET0_BASE (0x40100000u) /** Peripheral ENET0 base pointer */ #define ENET0 ((ENET_Type *)ENET0_BASE) /** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS { ENET0_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET0 } #endif /** Interrupt vectors for the ENET peripheral type */ #define ENET_IRQS { ETHERNET_IRQn } #define ENET_PMT_IRQS { ETHERNET_PMT_IRQn } #define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } /* Backward compatibility */ #define ENET ENET0 /*! * @} */ /* end of group ENET_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ERM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer * @{ */ /** ERM - Register Layout Typedef */ typedef struct { __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ __IO uint32_t SR1; /**< ERM Status Register 1, offset: 0x14 */ uint8_t RESERVED_1[232]; __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ uint8_t RESERVED_2[4]; __I uint32_t EAR1; /**< ERM Memory 1 Error Address Register, offset: 0x110 */ __I uint32_t SYN1; /**< ERM Memory 1 Syndrome Register, offset: 0x114 */ __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ uint8_t RESERVED_3[4]; __I uint32_t EAR2; /**< ERM Memory 2 Error Address Register, offset: 0x120 */ __I uint32_t SYN2; /**< ERM Memory 2 Syndrome Register, offset: 0x124 */ __IO uint32_t CORR_ERR_CNT2; /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128 */ uint8_t RESERVED_4[4]; __I uint32_t EAR3; /**< ERM Memory 3 Error Address Register, offset: 0x130 */ __I uint32_t SYN3; /**< ERM Memory 3 Syndrome Register, offset: 0x134 */ __IO uint32_t CORR_ERR_CNT3; /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138 */ uint8_t RESERVED_5[4]; __I uint32_t EAR4; /**< ERM Memory 4 Error Address Register, offset: 0x140 */ __I uint32_t SYN4; /**< ERM Memory 4 Syndrome Register, offset: 0x144 */ __IO uint32_t CORR_ERR_CNT4; /**< ERM Memory 4 Correctable Error Count Register, offset: 0x148 */ uint8_t RESERVED_6[4]; __I uint32_t EAR5; /**< ERM Memory 5 Error Address Register, offset: 0x150 */ __I uint32_t SYN5; /**< ERM Memory 5 Syndrome Register, offset: 0x154 */ __IO uint32_t CORR_ERR_CNT5; /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158 */ uint8_t RESERVED_7[4]; __I uint32_t EAR6; /**< ERM Memory 6 Error Address Register, offset: 0x160 */ __I uint32_t SYN6; /**< ERM Memory 6 Syndrome Register, offset: 0x164 */ __IO uint32_t CORR_ERR_CNT6; /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168 */ uint8_t RESERVED_8[12]; __IO uint32_t CORR_ERR_CNT7; /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178 */ uint8_t RESERVED_9[8]; __I uint32_t SYN8; /**< ERM Memory 8 Syndrome Register, offset: 0x184 */ __IO uint32_t CORR_ERR_CNT8; /**< ERM Memory 8 Correctable Error Count Register, offset: 0x188 */ uint8_t RESERVED_10[12]; __IO uint32_t CORR_ERR_CNT9; /**< ERM Memory 9 Correctable Error Count Register, offset: 0x198 */ } ERM_Type; /* ---------------------------------------------------------------------------- -- ERM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ERM_Register_Masks ERM Register Masks * @{ */ /*! @name CR0 - ERM Configuration Register 0 */ /*! @{ */ #define ERM_CR0_ENCIE7_MASK (0x4U) #define ERM_CR0_ENCIE7_SHIFT (2U) /*! ENCIE7 - ENCIE7 * 0b0..Interrupt notification of Memory 7 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 7 non-correctable error events is enabled. */ #define ERM_CR0_ENCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE7_SHIFT)) & ERM_CR0_ENCIE7_MASK) #define ERM_CR0_ESCIE7_MASK (0x8U) #define ERM_CR0_ESCIE7_SHIFT (3U) /*! ESCIE7 - ESCIE7 * 0b0..Interrupt notification of Memory 7 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 7 single-bit correction events is enabled. */ #define ERM_CR0_ESCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE7_SHIFT)) & ERM_CR0_ESCIE7_MASK) #define ERM_CR0_ENCIE6_MASK (0x40U) #define ERM_CR0_ENCIE6_SHIFT (6U) /*! ENCIE6 - ENCIE6 * 0b0..Interrupt notification of Memory 6 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 6 non-correctable error events is enabled. */ #define ERM_CR0_ENCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE6_SHIFT)) & ERM_CR0_ENCIE6_MASK) #define ERM_CR0_ESCIE6_MASK (0x80U) #define ERM_CR0_ESCIE6_SHIFT (7U) /*! ESCIE6 - ESCIE6 * 0b0..Interrupt notification of Memory 6 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 6 single-bit correction events is enabled. */ #define ERM_CR0_ESCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE6_SHIFT)) & ERM_CR0_ESCIE6_MASK) #define ERM_CR0_ENCIE5_MASK (0x400U) #define ERM_CR0_ENCIE5_SHIFT (10U) /*! ENCIE5 - ENCIE5 * 0b0..Interrupt notification of Memory 5 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 5 non-correctable error events is enabled. */ #define ERM_CR0_ENCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE5_SHIFT)) & ERM_CR0_ENCIE5_MASK) #define ERM_CR0_ESCIE5_MASK (0x800U) #define ERM_CR0_ESCIE5_SHIFT (11U) /*! ESCIE5 - ESCIE5 * 0b0..Interrupt notification of Memory 5 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 5 single-bit correction events is enabled. */ #define ERM_CR0_ESCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE5_SHIFT)) & ERM_CR0_ESCIE5_MASK) #define ERM_CR0_ENCIE4_MASK (0x4000U) #define ERM_CR0_ENCIE4_SHIFT (14U) /*! ENCIE4 - ENCIE4 * 0b0..Interrupt notification of Memory 4 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 4 non-correctable error events is enabled. */ #define ERM_CR0_ENCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE4_SHIFT)) & ERM_CR0_ENCIE4_MASK) #define ERM_CR0_ESCIE4_MASK (0x8000U) #define ERM_CR0_ESCIE4_SHIFT (15U) /*! ESCIE4 - ESCIE4 * 0b0..Interrupt notification of Memory 4 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 4 single-bit correction events is enabled. */ #define ERM_CR0_ESCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE4_SHIFT)) & ERM_CR0_ESCIE4_MASK) #define ERM_CR0_ENCIE3_MASK (0x40000U) #define ERM_CR0_ENCIE3_SHIFT (18U) /*! ENCIE3 - ENCIE3 * 0b0..Interrupt notification of Memory 3 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 3 non-correctable error events is enabled. */ #define ERM_CR0_ENCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE3_SHIFT)) & ERM_CR0_ENCIE3_MASK) #define ERM_CR0_ESCIE3_MASK (0x80000U) #define ERM_CR0_ESCIE3_SHIFT (19U) /*! ESCIE3 - ESCIE3 * 0b0..Interrupt notification of Memory 3 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 3 single-bit correction events is enabled. */ #define ERM_CR0_ESCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE3_SHIFT)) & ERM_CR0_ESCIE3_MASK) #define ERM_CR0_ENCIE2_MASK (0x400000U) #define ERM_CR0_ENCIE2_SHIFT (22U) /*! ENCIE2 - ENCIE2 * 0b0..Interrupt notification of Memory 2 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 2 non-correctable error events is enabled. */ #define ERM_CR0_ENCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE2_SHIFT)) & ERM_CR0_ENCIE2_MASK) #define ERM_CR0_ESCIE2_MASK (0x800000U) #define ERM_CR0_ESCIE2_SHIFT (23U) /*! ESCIE2 - ESCIE2 * 0b0..Interrupt notification of Memory 2 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 2 single-bit correction events is enabled. */ #define ERM_CR0_ESCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE2_SHIFT)) & ERM_CR0_ESCIE2_MASK) #define ERM_CR0_ENCIE1_MASK (0x4000000U) #define ERM_CR0_ENCIE1_SHIFT (26U) /*! ENCIE1 - ENCIE1 * 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled. */ #define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) #define ERM_CR0_ESCIE1_MASK (0x8000000U) #define ERM_CR0_ESCIE1_SHIFT (27U) /*! ESCIE1 - ESCIE1 * 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled. */ #define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) #define ERM_CR0_ENCIE0_MASK (0x40000000U) #define ERM_CR0_ENCIE0_SHIFT (30U) /*! ENCIE0 - ENCIE0 * 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled. */ #define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) #define ERM_CR0_ESCIE0_MASK (0x80000000U) #define ERM_CR0_ESCIE0_SHIFT (31U) /*! ESCIE0 - ESCIE0 * 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled. */ #define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) /*! @} */ /*! @name CR1 - ERM Configuration Register 1 */ /*! @{ */ #define ERM_CR1_ENCIE9_MASK (0x4000000U) #define ERM_CR1_ENCIE9_SHIFT (26U) /*! ENCIE9 - ENCIE9 * 0b0..Interrupt notification of Memory 9 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 9 non-correctable error events is enabled. */ #define ERM_CR1_ENCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE9_SHIFT)) & ERM_CR1_ENCIE9_MASK) #define ERM_CR1_ESCIE9_MASK (0x8000000U) #define ERM_CR1_ESCIE9_SHIFT (27U) /*! ESCIE9 - ESCIE9 * 0b0..Interrupt notification of Memory 9 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 9 single-bit correction events is enabled. */ #define ERM_CR1_ESCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE9_SHIFT)) & ERM_CR1_ESCIE9_MASK) #define ERM_CR1_ENCIE8_MASK (0x40000000U) #define ERM_CR1_ENCIE8_SHIFT (30U) /*! ENCIE8 - ENCIE8 * 0b0..Interrupt notification of Memory 8 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 8 non-correctable error events is enabled. */ #define ERM_CR1_ENCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE8_SHIFT)) & ERM_CR1_ENCIE8_MASK) #define ERM_CR1_ESCIE8_MASK (0x80000000U) #define ERM_CR1_ESCIE8_SHIFT (31U) /*! ESCIE8 - ESCIE8 * 0b0..Interrupt notification of Memory 8 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 8 single-bit correction events is enabled. */ #define ERM_CR1_ESCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE8_SHIFT)) & ERM_CR1_ESCIE8_MASK) /*! @} */ /*! @name SR0 - ERM Status Register 0 */ /*! @{ */ #define ERM_SR0_NCE7_MASK (0x4U) #define ERM_SR0_NCE7_SHIFT (2U) /*! NCE7 - NCE7 * 0b0..No non-correctable error event on Memory 7 detected. * 0b1..Non-correctable error event on Memory 7 detected. */ #define ERM_SR0_NCE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE7_SHIFT)) & ERM_SR0_NCE7_MASK) #define ERM_SR0_SBC7_MASK (0x8U) #define ERM_SR0_SBC7_SHIFT (3U) /*! SBC7 - SBC7 * 0b0..No single-bit correction event on Memory 7 detected. * 0b1..Single-bit correction event on Memory 7 detected. */ #define ERM_SR0_SBC7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC7_SHIFT)) & ERM_SR0_SBC7_MASK) #define ERM_SR0_NCE6_MASK (0x40U) #define ERM_SR0_NCE6_SHIFT (6U) /*! NCE6 - NCE6 * 0b0..No non-correctable error event on Memory 6 detected. * 0b1..Non-correctable error event on Memory 6 detected. */ #define ERM_SR0_NCE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE6_SHIFT)) & ERM_SR0_NCE6_MASK) #define ERM_SR0_SBC6_MASK (0x80U) #define ERM_SR0_SBC6_SHIFT (7U) /*! SBC6 - SBC6 * 0b0..No single-bit correction event on Memory 6 detected. * 0b1..Single-bit correction event on Memory 6 detected. */ #define ERM_SR0_SBC6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC6_SHIFT)) & ERM_SR0_SBC6_MASK) #define ERM_SR0_NCE5_MASK (0x400U) #define ERM_SR0_NCE5_SHIFT (10U) /*! NCE5 - NCE5 * 0b0..No non-correctable error event on Memory 5 detected. * 0b1..Non-correctable error event on Memory 5 detected. */ #define ERM_SR0_NCE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE5_SHIFT)) & ERM_SR0_NCE5_MASK) #define ERM_SR0_SBC5_MASK (0x800U) #define ERM_SR0_SBC5_SHIFT (11U) /*! SBC5 - SBC5 * 0b0..No single-bit correction event on Memory 5 detected. * 0b1..Single-bit correction event on Memory 5 detected. */ #define ERM_SR0_SBC5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC5_SHIFT)) & ERM_SR0_SBC5_MASK) #define ERM_SR0_NCE4_MASK (0x4000U) #define ERM_SR0_NCE4_SHIFT (14U) /*! NCE4 - NCE4 * 0b0..No non-correctable error event on Memory 4 detected. * 0b1..Non-correctable error event on Memory 4 detected. */ #define ERM_SR0_NCE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE4_SHIFT)) & ERM_SR0_NCE4_MASK) #define ERM_SR0_SBC4_MASK (0x8000U) #define ERM_SR0_SBC4_SHIFT (15U) /*! SBC4 - SBC4 * 0b0..No single-bit correction event on Memory 4 detected. * 0b1..Single-bit correction event on Memory 4 detected. */ #define ERM_SR0_SBC4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC4_SHIFT)) & ERM_SR0_SBC4_MASK) #define ERM_SR0_NCE3_MASK (0x40000U) #define ERM_SR0_NCE3_SHIFT (18U) /*! NCE3 - NCE3 * 0b0..No non-correctable error event on Memory 3 detected. * 0b1..Non-correctable error event on Memory 3 detected. */ #define ERM_SR0_NCE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE3_SHIFT)) & ERM_SR0_NCE3_MASK) #define ERM_SR0_SBC3_MASK (0x80000U) #define ERM_SR0_SBC3_SHIFT (19U) /*! SBC3 - SBC3 * 0b0..No single-bit correction event on Memory 3 detected. * 0b1..Single-bit correction event on Memory 3 detected. */ #define ERM_SR0_SBC3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC3_SHIFT)) & ERM_SR0_SBC3_MASK) #define ERM_SR0_NCE2_MASK (0x400000U) #define ERM_SR0_NCE2_SHIFT (22U) /*! NCE2 - NCE2 * 0b0..No non-correctable error event on Memory 2 detected. * 0b1..Non-correctable error event on Memory 2 detected. */ #define ERM_SR0_NCE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE2_SHIFT)) & ERM_SR0_NCE2_MASK) #define ERM_SR0_SBC2_MASK (0x800000U) #define ERM_SR0_SBC2_SHIFT (23U) /*! SBC2 - SBC2 * 0b0..No single-bit correction event on Memory 2 detected. * 0b1..Single-bit correction event on Memory 2 detected. */ #define ERM_SR0_SBC2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC2_SHIFT)) & ERM_SR0_SBC2_MASK) #define ERM_SR0_NCE1_MASK (0x4000000U) #define ERM_SR0_NCE1_SHIFT (26U) /*! NCE1 - NCE1 * 0b0..No non-correctable error event on Memory 1 detected. * 0b1..Non-correctable error event on Memory 1 detected. */ #define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) #define ERM_SR0_SBC1_MASK (0x8000000U) #define ERM_SR0_SBC1_SHIFT (27U) /*! SBC1 - SBC1 * 0b0..No single-bit correction event on Memory 1 detected. * 0b1..Single-bit correction event on Memory 1 detected. */ #define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) #define ERM_SR0_NCE0_MASK (0x40000000U) #define ERM_SR0_NCE0_SHIFT (30U) /*! NCE0 - NCE0 * 0b0..No non-correctable error event on Memory 0 detected. * 0b1..Non-correctable error event on Memory 0 detected. */ #define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) #define ERM_SR0_SBC0_MASK (0x80000000U) #define ERM_SR0_SBC0_SHIFT (31U) /*! SBC0 - SBC0 * 0b0..No single-bit correction event on Memory 0 detected. * 0b1..Single-bit correction event on Memory 0 detected. */ #define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) /*! @} */ /*! @name SR1 - ERM Status Register 1 */ /*! @{ */ #define ERM_SR1_NCE9_MASK (0x4000000U) #define ERM_SR1_NCE9_SHIFT (26U) /*! NCE9 - NCE9 * 0b0..No non-correctable error event on Memory 9 detected. * 0b1..Non-correctable error event on Memory 9 detected. */ #define ERM_SR1_NCE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE9_SHIFT)) & ERM_SR1_NCE9_MASK) #define ERM_SR1_SBC9_MASK (0x8000000U) #define ERM_SR1_SBC9_SHIFT (27U) /*! SBC9 - SBC9 * 0b0..No single-bit correction event on Memory 9 detected. * 0b1..Single-bit correction event on Memory 9 detected. */ #define ERM_SR1_SBC9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC9_SHIFT)) & ERM_SR1_SBC9_MASK) #define ERM_SR1_NCE8_MASK (0x40000000U) #define ERM_SR1_NCE8_SHIFT (30U) /*! NCE8 - NCE8 * 0b0..No non-correctable error event on Memory 8 detected. * 0b1..Non-correctable error event on Memory 8 detected. */ #define ERM_SR1_NCE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE8_SHIFT)) & ERM_SR1_NCE8_MASK) #define ERM_SR1_SBC8_MASK (0x80000000U) #define ERM_SR1_SBC8_SHIFT (31U) /*! SBC8 - SBC8 * 0b0..No single-bit correction event on Memory 8 detected. * 0b1..Single-bit correction event on Memory 8 detected. */ #define ERM_SR1_SBC8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC8_SHIFT)) & ERM_SR1_SBC8_MASK) /*! @} */ /*! @name EAR0 - ERM Memory 0 Error Address Register */ /*! @{ */ #define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) #define ERM_EAR0_EAR_SHIFT (0U) /*! EAR - EAR */ #define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) /*! @} */ /*! @name SYN0 - ERM Memory 0 Syndrome Register */ /*! @{ */ #define ERM_SYN0_SYNDROME_MASK (0xFF000000U) #define ERM_SYN0_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) /*! @} */ /*! @name EAR1 - ERM Memory 1 Error Address Register */ /*! @{ */ #define ERM_EAR1_EAR_MASK (0xFFFFFFFFU) #define ERM_EAR1_EAR_SHIFT (0U) /*! EAR - EAR */ #define ERM_EAR1_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR1_EAR_SHIFT)) & ERM_EAR1_EAR_MASK) /*! @} */ /*! @name SYN1 - ERM Memory 1 Syndrome Register */ /*! @{ */ #define ERM_SYN1_SYNDROME_MASK (0xFF000000U) #define ERM_SYN1_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define ERM_SYN1_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN1_SYNDROME_SHIFT)) & ERM_SYN1_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) /*! @} */ /*! @name EAR2 - ERM Memory 2 Error Address Register */ /*! @{ */ #define ERM_EAR2_EAR_MASK (0xFFFFFFFFU) #define ERM_EAR2_EAR_SHIFT (0U) /*! EAR - EAR */ #define ERM_EAR2_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR2_EAR_SHIFT)) & ERM_EAR2_EAR_MASK) /*! @} */ /*! @name SYN2 - ERM Memory 2 Syndrome Register */ /*! @{ */ #define ERM_SYN2_SYNDROME_MASK (0xFF000000U) #define ERM_SYN2_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define ERM_SYN2_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN2_SYNDROME_SHIFT)) & ERM_SYN2_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT2_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT2_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT2_COUNT_SHIFT)) & ERM_CORR_ERR_CNT2_COUNT_MASK) /*! @} */ /*! @name EAR3 - ERM Memory 3 Error Address Register */ /*! @{ */ #define ERM_EAR3_EAR_MASK (0xFFFFFFFFU) #define ERM_EAR3_EAR_SHIFT (0U) /*! EAR - EAR */ #define ERM_EAR3_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR3_EAR_SHIFT)) & ERM_EAR3_EAR_MASK) /*! @} */ /*! @name SYN3 - ERM Memory 3 Syndrome Register */ /*! @{ */ #define ERM_SYN3_SYNDROME_MASK (0xFF000000U) #define ERM_SYN3_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define ERM_SYN3_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN3_SYNDROME_SHIFT)) & ERM_SYN3_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT3_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT3_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT3_COUNT_SHIFT)) & ERM_CORR_ERR_CNT3_COUNT_MASK) /*! @} */ /*! @name EAR4 - ERM Memory 4 Error Address Register */ /*! @{ */ #define ERM_EAR4_EAR_MASK (0xFFFFFFFFU) #define ERM_EAR4_EAR_SHIFT (0U) /*! EAR - EAR */ #define ERM_EAR4_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR4_EAR_SHIFT)) & ERM_EAR4_EAR_MASK) /*! @} */ /*! @name SYN4 - ERM Memory 4 Syndrome Register */ /*! @{ */ #define ERM_SYN4_SYNDROME_MASK (0xFF000000U) #define ERM_SYN4_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define ERM_SYN4_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN4_SYNDROME_SHIFT)) & ERM_SYN4_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT4 - ERM Memory 4 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT4_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT4_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT4_COUNT_SHIFT)) & ERM_CORR_ERR_CNT4_COUNT_MASK) /*! @} */ /*! @name EAR5 - ERM Memory 5 Error Address Register */ /*! @{ */ #define ERM_EAR5_EAR_MASK (0xFFFFFFFFU) #define ERM_EAR5_EAR_SHIFT (0U) /*! EAR - EAR */ #define ERM_EAR5_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR5_EAR_SHIFT)) & ERM_EAR5_EAR_MASK) /*! @} */ /*! @name SYN5 - ERM Memory 5 Syndrome Register */ /*! @{ */ #define ERM_SYN5_SYNDROME_MASK (0xFF000000U) #define ERM_SYN5_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define ERM_SYN5_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN5_SYNDROME_SHIFT)) & ERM_SYN5_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT5_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT5_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT5_COUNT_SHIFT)) & ERM_CORR_ERR_CNT5_COUNT_MASK) /*! @} */ /*! @name EAR6 - ERM Memory 6 Error Address Register */ /*! @{ */ #define ERM_EAR6_EAR_MASK (0xFFFFFFFFU) #define ERM_EAR6_EAR_SHIFT (0U) /*! EAR - EAR */ #define ERM_EAR6_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR6_EAR_SHIFT)) & ERM_EAR6_EAR_MASK) /*! @} */ /*! @name SYN6 - ERM Memory 6 Syndrome Register */ /*! @{ */ #define ERM_SYN6_SYNDROME_MASK (0xFF000000U) #define ERM_SYN6_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define ERM_SYN6_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN6_SYNDROME_SHIFT)) & ERM_SYN6_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT6_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT6_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT6_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT6_COUNT_SHIFT)) & ERM_CORR_ERR_CNT6_COUNT_MASK) /*! @} */ /*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT7_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT7_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT7_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT7_COUNT_SHIFT)) & ERM_CORR_ERR_CNT7_COUNT_MASK) /*! @} */ /*! @name SYN8 - ERM Memory 8 Syndrome Register */ /*! @{ */ #define ERM_SYN8_SYNDROME_MASK (0xFF000000U) #define ERM_SYN8_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define ERM_SYN8_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN8_SYNDROME_SHIFT)) & ERM_SYN8_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT8 - ERM Memory 8 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT8_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT8_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT8_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT8_COUNT_SHIFT)) & ERM_CORR_ERR_CNT8_COUNT_MASK) /*! @} */ /*! @name CORR_ERR_CNT9 - ERM Memory 9 Correctable Error Count Register */ /*! @{ */ #define ERM_CORR_ERR_CNT9_COUNT_MASK (0xFFU) #define ERM_CORR_ERR_CNT9_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define ERM_CORR_ERR_CNT9_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT9_COUNT_SHIFT)) & ERM_CORR_ERR_CNT9_COUNT_MASK) /*! @} */ /*! * @} */ /* end of group ERM_Register_Masks */ /* ERM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral ERM0 base address */ #define ERM0_BASE (0x5005C000u) /** Peripheral ERM0 base address */ #define ERM0_BASE_NS (0x4005C000u) /** Peripheral ERM0 base pointer */ #define ERM0 ((ERM_Type *)ERM0_BASE) /** Peripheral ERM0 base pointer */ #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) /** Array initializer of ERM peripheral base addresses */ #define ERM_BASE_ADDRS { ERM0_BASE } /** Array initializer of ERM peripheral base pointers */ #define ERM_BASE_PTRS { ERM0 } /** Array initializer of ERM peripheral base addresses */ #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } /** Array initializer of ERM peripheral base pointers */ #define ERM_BASE_PTRS_NS { ERM0_NS } #else /** Peripheral ERM0 base address */ #define ERM0_BASE (0x4005C000u) /** Peripheral ERM0 base pointer */ #define ERM0 ((ERM_Type *)ERM0_BASE) /** Array initializer of ERM peripheral base addresses */ #define ERM_BASE_ADDRS { ERM0_BASE } /** Array initializer of ERM peripheral base pointers */ #define ERM_BASE_PTRS { ERM0 } #endif /*! * @} */ /* end of group ERM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EVTG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EVTG_Peripheral_Access_Layer EVTG Peripheral Access Layer * @{ */ /** EVTG - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10 */ __IO uint16_t EVTG_AOI0_BFT01; /**< AOI0 Boolean Function Term 0 and 1 Configuration, array offset: 0x0, array step: 0x10 */ __IO uint16_t EVTG_AOI0_BFT23; /**< AOI0 Boolean Function Term 2 and 3 Configuration, array offset: 0x2, array step: 0x10 */ __IO uint16_t EVTG_AOI1_BFT01; /**< AOI1 Boolean Function Term 0 and 1 Configuration, array offset: 0x4, array step: 0x10 */ __IO uint16_t EVTG_AOI1_BFT23; /**< AOI1 Boolean Function Term 2 and 3 Configuration, array offset: 0x6, array step: 0x10 */ uint8_t RESERVED_0[2]; __IO uint16_t EVTG_CTRL; /**< Control and Status, array offset: 0xA, array step: 0x10 */ __IO uint16_t EVTG_AOI0_FILT; /**< AOI0 Output Filter, array offset: 0xC, array step: 0x10 */ __IO uint16_t EVTG_AOI1_FILT; /**< AOI1 Output Filter, array offset: 0xE, array step: 0x10 */ } EVTG_INST[4]; } EVTG_Type; /* ---------------------------------------------------------------------------- -- EVTG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EVTG_Register_Masks EVTG Register Masks * @{ */ /*! @name EVTG_INST_EVTG_AOI0_BFT01 - AOI0 Boolean Function Term 0 and 1 Configuration */ /*! @{ */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK (0x3U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT (0U) /*! PT1_DC - Product Term 1, D Input Configuration * 0b00..Force the D input in this product term to a logical zero * 0b01..Pass the D input in this product term * 0b10..Complement the D input in this product term * 0b11..Force the D input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK (0xCU) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT (2U) /*! PT1_CC - Product Term 1, C Input Configuration * 0b00..Force the C input in this product term to a logical zero * 0b01..Pass the C input in this product term * 0b10..Complement the C input in this product term * 0b11..Force the C input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK (0x30U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT (4U) /*! PT1_BC - Product Term 1, B Input Configuration * 0b00..Force the B input in this product term to a logical zero * 0b01..Pass the B input in this product term * 0b10..Complement the B input in this product term * 0b11..Force the B input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK (0xC0U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT (6U) /*! PT1_AC - Product Term 1, A Input Configuration * 0b00..Force the A input in this product term to a logical zero * 0b01..Pass the A input in this product term * 0b10..Complement the A input in this product term * 0b11..Force the A input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK (0x300U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT (8U) /*! PT0_DC - Product Term 0, D Input Configuration * 0b00..Force the D input in this product term to a logical zero * 0b01..Pass the D input in this product term * 0b10..Complement the D input in this product term * 0b11..Force the D input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK (0xC00U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT (10U) /*! PT0_CC - Product Term 0, C Input Configuration * 0b00..Force the C input in this product term to a logical zero * 0b01..Pass the C input in this product term * 0b10..Complement the C input in this product term * 0b11..Force the C input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK (0x3000U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT (12U) /*! PT0_BC - Product Term 0, B Input Configuration * 0b00..Force the B input in this product term to a logical zero * 0b01..Pass the B input in this product term * 0b10..Complement the B input in this product term * 0b11..Force the B input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK (0xC000U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT (14U) /*! PT0_AC - Product Term 0, A Input Configuration * 0b00..Force the A input in this product term to a logical zero * 0b01..Pass the A input in this product term * 0b10..Complement the A input in this product term * 0b11..Force the A input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK) /*! @} */ /* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT01 */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT01_COUNT (4U) /*! @name EVTG_INST_EVTG_AOI0_BFT23 - AOI0 Boolean Function Term 2 and 3 Configuration */ /*! @{ */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK (0x3U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT (0U) /*! PT3_DC - Product Term 3, D Input Configuration * 0b00..Force the D input in this product term to a logical zero * 0b01..Pass the D input in this product term * 0b10..Complement the D input in this product term * 0b11..Force the D input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK (0xCU) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT (2U) /*! PT3_CC - Product Term 3, C Input Configuration * 0b00..Force the C input in this product term to a logical zero * 0b01..Pass the C input in this product term * 0b10..Complement the C input in this product term * 0b11..Force the C input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK (0x30U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT (4U) /*! PT3_BC - Product Term 3, B Input Configuration * 0b00..Force the B input in this product term to a logical zero * 0b01..Pass the B input in this product term * 0b10..Complement the B input in this product term * 0b11..Force the B input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK (0xC0U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT (6U) /*! PT3_AC - Product Term 3, A Input Configuration * 0b00..Force the A input in this product term to a logical zero * 0b01..Pass the A input in this product term * 0b10..Complement the A input in this product term * 0b11..Force the A input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK (0x300U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT (8U) /*! PT2_DC - Product Term 2, D Input Configuration * 0b00..Force the D input in this product term to a logical zero * 0b01..Pass the D input in this product term * 0b10..Complement the D input in this product term * 0b11..Force the D input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK (0xC00U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT (10U) /*! PT2_CC - Product Term 2, C Input Configuration * 0b00..Force the C input in this product term to a logical zero * 0b01..Pass the C input in this product term * 0b10..Complement the C input in this product term * 0b11..Force the C input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK (0x3000U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT (12U) /*! PT2_BC - Product Term 2, B Input Configuration * 0b00..Force the B input in this product term to a logical zero * 0b01..Pass the B input in this product term * 0b10..Complement the B input in this product term * 0b11..Force the B input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK (0xC000U) #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT (14U) /*! PT2_AC - Product Term 2, A Input Configuration * 0b00..Force the A input in this product term to a logical zero * 0b01..Pass the A input in this product term * 0b10..Complement the A input in this product term * 0b11..Force the A input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK) /*! @} */ /* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT23 */ #define EVTG_EVTG_INST_EVTG_AOI0_BFT23_COUNT (4U) /*! @name EVTG_INST_EVTG_AOI1_BFT01 - AOI1 Boolean Function Term 0 and 1 Configuration */ /*! @{ */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK (0x3U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT (0U) /*! PT1_DC - Product Term 1, D Input Configuration * 0b00..Force the D input in this product term to a logical zero * 0b01..Pass the D input in this product term * 0b10..Complement the D input in this product term * 0b11..Force the D input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK (0xCU) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT (2U) /*! PT1_CC - Product Term 1, C Input Configuration * 0b00..Force the C input in this product term to a logical zero * 0b01..Pass the C input in this product term * 0b10..Complement the C input in this product term * 0b11..Force the C input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK (0x30U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT (4U) /*! PT1_BC - Product Term 1, B Input Configuration * 0b00..Force the B input in this product term to a logical zero * 0b01..Pass the B input in this product term * 0b10..Complement the B input in this product term * 0b11..Force the B input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK (0xC0U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT (6U) /*! PT1_AC - Product Term 1, A Input Configuration * 0b00..Force the A input in this product term to a logical zero * 0b01..Pass the A input in this product term * 0b10..Complement the A input in this product term * 0b11..Force the A input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK (0x300U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT (8U) /*! PT0_DC - Product Term 0, D Input Configuration * 0b00..Force the D input in this product term to a logical zero * 0b01..Pass the D input in this product term * 0b10..Complement the D input in this product term * 0b11..Force the D input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK (0xC00U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT (10U) /*! PT0_CC - Product Term 0, C Input Configuration * 0b00..Force the C input in this product term to a logical zero * 0b01..Pass the C input in this product term * 0b10..Complement the C input in this product term * 0b11..Force the C input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK (0x3000U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT (12U) /*! PT0_BC - Product Term 0, B Input Configuration * 0b00..Force the B input in this product term to a logical zero * 0b01..Pass the B input in this product term * 0b10..Complement the B input in this product term * 0b11..Force the B input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK (0xC000U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT (14U) /*! PT0_AC - Product Term 0, A Input Configuration * 0b00..Force the A input in this product term to a logical zero * 0b01..Pass the A input in this product term * 0b10..Complement the A input in this product term * 0b11..Force the A input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK) /*! @} */ /* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT01 */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT01_COUNT (4U) /*! @name EVTG_INST_EVTG_AOI1_BFT23 - AOI1 Boolean Function Term 2 and 3 Configuration */ /*! @{ */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK (0x3U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT (0U) /*! PT3_DC - Product Term 3, D Input Configuration * 0b00..Force the D input in this product term to a logical zero * 0b01..Pass the D input in this product term * 0b10..Complement the D input in this product term * 0b11..Force the D input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK (0xCU) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT (2U) /*! PT3_CC - Product Term 3, C Input Configuration * 0b00..Force the C input in this product term to a logical zero * 0b01..Pass the C input in this product term * 0b10..Complement the C input in this product term * 0b11..Force the C input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK (0x30U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT (4U) /*! PT3_BC - Product Term 3, B Input Configuration * 0b00..Force the B input in this product term to a logical zero * 0b01..Pass the B input in this product term * 0b10..Complement the B input in this product term * 0b11..Force the B input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK (0xC0U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT (6U) /*! PT3_AC - Product Term 3, A Input Configuration * 0b00..Force the A input in this product term to a logical zero * 0b01..Pass the A input in this product term * 0b10..Complement the A input in this product term * 0b11..Force the A input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK (0x300U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT (8U) /*! PT2_DC - Product Term 2, D Input Configuration * 0b00..Force the D input in this product term to a logical zero * 0b01..Pass the D input in this product term * 0b10..Complement the D input in this product term * 0b11..Force the D input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK (0xC00U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT (10U) /*! PT2_CC - Product Term 2, C Input Configuration * 0b00..Force the C input in this product term to a logical zero * 0b01..Pass the C input in this product term * 0b10..Complement the C input in this product term * 0b11..Force the C input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK (0x3000U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT (12U) /*! PT2_BC - Product Term 2, B Input Configuration * 0b00..Force the B input in this product term to a logical zero * 0b01..Pass the B input in this product term * 0b10..Complement the B input in this product term * 0b11..Force the B input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK (0xC000U) #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT (14U) /*! PT2_AC - Product Term 2, A Input Configuration * 0b00..Force the A input in this product term to a logical zero * 0b01..Pass the A input in this product term * 0b10..Complement the A input in this product term * 0b11..Force the A input in this product term to a logical one */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK) /*! @} */ /* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT23 */ #define EVTG_EVTG_INST_EVTG_AOI1_BFT23_COUNT (4U) /*! @name EVTG_INST_EVTG_CTRL - Control and Status */ /*! @{ */ #define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK (0x1U) #define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT (0U) /*! FF_INIT - Flip flop Initial Value Configuration * 0b0..0 * 0b1..1 */ #define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK) #define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK (0x2U) #define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT (1U) /*! INIT_EN - Flip-Flop Initial Output Enable Control * 0b0..Write 0 does not generate enable pulse * 0b1..Write 1 generates enable pulse */ #define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK) #define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK (0x1CU) #define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT (2U) /*! MODE_SEL - Flip-Flop Mode Selection * 0b000..Bypass mode * 0b001..RS Trigger mode * 0b010..T-FF mode * 0b011..D-FF mode * 0b100..JK-FF mode * 0b101..Latch mode * 0b110..Reserved * 0b111..Reserved */ #define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK) #define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK (0xC0U) #define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT (6U) /*! FB_OVRD - EVTG Output Feedback Override Control * 0b00..Replace An * 0b01..Replace Bn * 0b10..Replace Cn * 0b11..Replace Dn */ #define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK) #define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK (0xF00U) #define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT (8U) /*! SYNC_CTRL - Synchronize Control * 0bxxx1..EVTG input "An" will be synced by two bus clk cycles * 0bxxx0..EVTG input "An" will not be synced * 0bxx1x..EVTG input "Bn" will be synced by two bus clk cycles * 0bxx0x..EVTG input "Bn" will not be synced * 0bx1xx..EVTG input "Cn" will be synced by two bus clk cycles * 0bx0xx..EVTG input "Cn" will not be synced * 0b1xxx..EVTG input "Dn" will be synced by two bus clk cycles * 0b0xxx..EVTG input "Dn" will not be synced */ #define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK) #define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK (0x3000U) #define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT (12U) /*! FORCE_BYPASS - Force Bypass Control * 0bx1..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_0(Filter_0) value directly to EVTG_OUTA * 0bx0..Will not force the bypass * 0b1x..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_1(Filter_1) value directly to EVTG_OUTB * 0b0x..Will not force the bypass */ #define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK) /*! @} */ /* The count of EVTG_EVTG_INST_EVTG_CTRL */ #define EVTG_EVTG_INST_EVTG_CTRL_COUNT (4U) /*! @name EVTG_INST_EVTG_AOI0_FILT - AOI0 Output Filter */ /*! @{ */ #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK (0xFFU) #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT (0U) /*! FILT_PER - Output Filter Sample Period */ #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK) #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK (0x700U) #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT (8U) /*! FILT_CNT - Output Filter Sample Count */ #define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK) /*! @} */ /* The count of EVTG_EVTG_INST_EVTG_AOI0_FILT */ #define EVTG_EVTG_INST_EVTG_AOI0_FILT_COUNT (4U) /*! @name EVTG_INST_EVTG_AOI1_FILT - AOI1 Output Filter */ /*! @{ */ #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK (0xFFU) #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT (0U) /*! FILT_PER - Output Filter Sample Period */ #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK) #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK (0x700U) #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT (8U) /*! FILT_CNT - Output Filter Sample Count */ #define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK) /*! @} */ /* The count of EVTG_EVTG_INST_EVTG_AOI1_FILT */ #define EVTG_EVTG_INST_EVTG_AOI1_FILT_COUNT (4U) /*! * @} */ /* end of group EVTG_Register_Masks */ /* EVTG - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral EVTG0 base address */ #define EVTG0_BASE (0x500D2000u) /** Peripheral EVTG0 base address */ #define EVTG0_BASE_NS (0x400D2000u) /** Peripheral EVTG0 base pointer */ #define EVTG0 ((EVTG_Type *)EVTG0_BASE) /** Peripheral EVTG0 base pointer */ #define EVTG0_NS ((EVTG_Type *)EVTG0_BASE_NS) /** Array initializer of EVTG peripheral base addresses */ #define EVTG_BASE_ADDRS { EVTG0_BASE } /** Array initializer of EVTG peripheral base pointers */ #define EVTG_BASE_PTRS { EVTG0 } /** Array initializer of EVTG peripheral base addresses */ #define EVTG_BASE_ADDRS_NS { EVTG0_BASE_NS } /** Array initializer of EVTG peripheral base pointers */ #define EVTG_BASE_PTRS_NS { EVTG0_NS } #else /** Peripheral EVTG0 base address */ #define EVTG0_BASE (0x400D2000u) /** Peripheral EVTG0 base pointer */ #define EVTG0 ((EVTG_Type *)EVTG0_BASE) /** Array initializer of EVTG peripheral base addresses */ #define EVTG_BASE_ADDRS { EVTG0_BASE } /** Array initializer of EVTG peripheral base pointers */ #define EVTG_BASE_PTRS { EVTG0 } #endif /*! * @} */ /* end of group EVTG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EWM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer * @{ */ /** EWM - Register Layout Typedef */ typedef struct { __IO uint8_t CTRL; /**< Control, offset: 0x0 */ __O uint8_t SERV; /**< Service, offset: 0x1 */ __IO uint8_t CMPL; /**< Compare Low, offset: 0x2 */ __IO uint8_t CMPH; /**< Compare High, offset: 0x3 */ __IO uint8_t CLKCTRL; /**< Clock Control, offset: 0x4 */ __IO uint8_t CLKPRESCALER; /**< Clock Prescaler, offset: 0x5 */ } EWM_Type; /* ---------------------------------------------------------------------------- -- EWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Register_Masks EWM Register Masks * @{ */ /*! @name CTRL - Control */ /*! @{ */ #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) /*! EWMEN - EWM Enable * 0b0..Disables * 0b1..Enables */ #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) #define EWM_CTRL_ASSIN_MASK (0x2U) #define EWM_CTRL_ASSIN_SHIFT (1U) /*! ASSIN - Assertion State Select * 0b0..Logic 0 * 0b1..Logic 1 */ #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) #define EWM_CTRL_INEN_MASK (0x4U) #define EWM_CTRL_INEN_SHIFT (2U) /*! INEN - Input Enable * 0b0..Disables * 0b1..Enables */ #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) /*! INTEN - Interrupt Enable * 0b1..Generates interrupt requests * 0b0..Deasserts interrupt requests */ #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) /*! @} */ /*! @name SERV - Service */ /*! @{ */ #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) /*! SERVICE - Service */ #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) /*! @} */ /*! @name CMPL - Compare Low */ /*! @{ */ #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) /*! COMPAREL - Compare Low */ #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) /*! @} */ /*! @name CMPH - Compare High */ /*! @{ */ #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) /*! COMPAREH - Compare High */ #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) /*! @} */ /*! @name CLKCTRL - Clock Control */ /*! @{ */ #define EWM_CLKCTRL_CLKSEL_MASK (0x3U) #define EWM_CLKCTRL_CLKSEL_SHIFT (0U) /*! CLKSEL - Clock Select */ #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) /*! @} */ /*! @name CLKPRESCALER - Clock Prescaler */ /*! @{ */ #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) /*! CLK_DIV - Clock Divider */ #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) /*! @} */ /*! * @} */ /* end of group EWM_Register_Masks */ /* EWM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral EWM0 base address */ #define EWM0_BASE (0x500C0000u) /** Peripheral EWM0 base address */ #define EWM0_BASE_NS (0x400C0000u) /** Peripheral EWM0 base pointer */ #define EWM0 ((EWM_Type *)EWM0_BASE) /** Peripheral EWM0 base pointer */ #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) /** Array initializer of EWM peripheral base addresses */ #define EWM_BASE_ADDRS { EWM0_BASE } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS { EWM0 } /** Array initializer of EWM peripheral base addresses */ #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS_NS { EWM0_NS } #else /** Peripheral EWM0 base address */ #define EWM0_BASE (0x400C0000u) /** Peripheral EWM0 base pointer */ #define EWM0 ((EWM_Type *)EWM0_BASE) /** Array initializer of EWM peripheral base addresses */ #define EWM_BASE_ADDRS { EWM0_BASE } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS { EWM0 } #endif /*! * @} */ /* end of group EWM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FLEXIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer * @{ */ /** FLEXIO - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ __I uint32_t PIN; /**< Pin State, offset: 0xC */ __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ uint8_t RESERVED_2[4]; __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ uint8_t RESERVED_3[4]; __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ uint8_t RESERVED_4[4]; __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ uint8_t RESERVED_5[8]; __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_6[96]; __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_7[224]; __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_8[96]; __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ uint8_t RESERVED_9[96]; __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_10[96]; __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ uint8_t RESERVED_11[96]; __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_12[96]; __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_13[96]; __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ uint8_t RESERVED_14[352]; __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ uint8_t RESERVED_15[96]; __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ uint8_t RESERVED_16[96]; __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ uint8_t RESERVED_17[96]; __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ uint8_t RESERVED_18[96]; __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_19[96]; __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ } FLEXIO_Type; /* ---------------------------------------------------------------------------- -- FLEXIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented * 0b0000000000000001..State, logic, and parallel modes supported * 0b0000000000000010..Pin control registers supported * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) #define FLEXIO_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) #define FLEXIO_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) /*! SHIFTER - Shifter Number */ #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) #define FLEXIO_PARAM_TIMER_SHIFT (8U) /*! TIMER - Timer Number */ #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) #define FLEXIO_PARAM_PIN_SHIFT (16U) /*! PIN - Pin Number */ #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) /*! TRIGGER - Trigger Number */ #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) /*! @} */ /*! @name CTRL - FLEXIO Control */ /*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) /*! FLEXEN - FLEXIO Enable * 0b0..Disable * 0b1..Enable */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) /*! SWRST - Software Reset * 0b0..Disabled * 0b1..Enabled */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) /*! FASTACC - Fast Access * 0b0..Normal * 0b1..Fast */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) /*! DBGE - Debug Enable * 0b0..Disable * 0b1..Enable */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) /*! DOZEN - Doze Enable * 0b0..Enable * 0b1..Disable */ #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) /*! @} */ /*! @name PIN - Pin State */ /*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) #define FLEXIO_PIN_PDI_SHIFT (0U) /*! PDI - Pin Data Input */ #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /*! @} */ /*! @name SHIFTSTAT - Shifter Status */ /*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) /*! SSF - Shifter Status Flag * 0b00000000..Clear * 0b00000001..Set * 0b00000000..No effect * 0b00000001..Clear the flag */ #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) /*! @} */ /*! @name SHIFTERR - Shifter Error */ /*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) /*! SEF - Shifter Error Flag * 0b00000000..Clear * 0b00000001..Set * 0b00000000..No effect * 0b00000001..Clear the flag */ #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) /*! @} */ /*! @name TIMSTAT - Timer Status Flag */ /*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) /*! TSF - Timer Status Flag * 0b00000000..Clear * 0b00000001..Set * 0b00000000..No effect * 0b00000001..Clear the flag */ #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) /*! @} */ /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ /*! @{ */ #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) /*! SSIE - Shifter Status Interrupt Enable */ #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) /*! @} */ /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ /*! @{ */ #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) /*! SEIE - Shifter Error Interrupt Enable */ #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) /*! @} */ /*! @name TIMIEN - Timer Interrupt Enable */ /*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) /*! TEIE - Timer Status Interrupt Enable */ #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) /*! @} */ /*! @name SHIFTSDEN - Shifter Status DMA Enable */ /*! @{ */ #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) /*! SSDE - Shifter Status DMA Enable */ #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) /*! @} */ /*! @name TIMERSDEN - Timer Status DMA Enable */ /*! @{ */ #define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) #define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) /*! TSDE - Timer Status DMA Enable */ #define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) /*! @} */ /*! @name SHIFTSTATE - Shifter State */ /*! @{ */ #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) /*! STATE - Current State Pointer */ #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) /*! @} */ /*! @name TRGSTAT - Trigger Status */ /*! @{ */ #define FLEXIO_TRGSTAT_ETSF_MASK (0xFFU) #define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) /*! ETSF - External Trigger Status Flag * 0b00000000..Clear * 0b00000001..Set * 0b00000000..No effect * 0b00000001..Clear the flag */ #define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) /*! @} */ /*! @name TRIGIEN - External Trigger Interrupt Enable */ /*! @{ */ #define FLEXIO_TRIGIEN_TRIE_MASK (0xFFU) #define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) /*! TRIE - External Trigger Interrupt Enable */ #define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) /*! @} */ /*! @name PINSTAT - Pin Status */ /*! @{ */ #define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) #define FLEXIO_PINSTAT_PSF_SHIFT (0U) /*! PSF - Pin Status Flag * 0b00000000000000000000000000000000..Clear * 0b00000000000000000000000000000001..Set * 0b00000000000000000000000000000000..No effect * 0b00000000000000000000000000000001..Clear the flag */ #define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) /*! @} */ /*! @name PINIEN - Pin Interrupt Enable */ /*! @{ */ #define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) #define FLEXIO_PINIEN_PSIE_SHIFT (0U) /*! PSIE - Pin Status Interrupt Enable */ #define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) /*! @} */ /*! @name PINREN - Pin Rising Edge Enable */ /*! @{ */ #define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) #define FLEXIO_PINREN_PRE_SHIFT (0U) /*! PRE - Pin Rising Edge */ #define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) /*! @} */ /*! @name PINFEN - Pin Falling Edge Enable */ /*! @{ */ #define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) #define FLEXIO_PINFEN_PFE_SHIFT (0U) /*! PFE - Pin Falling Edge */ #define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) /*! @} */ /*! @name PINOUTD - Pin Output Data */ /*! @{ */ #define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTD_OUTD_SHIFT (0U) /*! OUTD - Output Data */ #define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) /*! @} */ /*! @name PINOUTE - Pin Output Enable */ /*! @{ */ #define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTE_OUTE_SHIFT (0U) /*! OUTE - Output Enable */ #define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) /*! @} */ /*! @name PINOUTDIS - Pin Output Disable */ /*! @{ */ #define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) /*! OUTDIS - Output Disable */ #define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) /*! @} */ /*! @name PINOUTCLR - Pin Output Clear */ /*! @{ */ #define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) /*! OUTCLR - Output Clear */ #define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) /*! @} */ /*! @name PINOUTSET - Pin Output Set */ /*! @{ */ #define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) /*! OUTSET - Output Set */ #define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) /*! @} */ /*! @name PINOUTTOG - Pin Output Toggle */ /*! @{ */ #define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) /*! OUTTOG - Output Toggle */ #define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) /*! @} */ /*! @name SHIFTCTL - Shifter Control */ /*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) /*! SMOD - Shifter Mode * 0b000..Disable * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer * 0b011..Reserved * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents * 0b110..State mode; SHIFTBUF contents store programmable state attributes * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) /*! PINPOL - Shifter Pin Polarity * 0b0..Active high * 0b1..Active low */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) /*! PINSEL - Shifter Pin Select */ #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) /*! PINCFG - Shifter Pin Configuration * 0b00..Shifter pin output disabled * 0b01..Shifter pin open-drain or bidirectional output enable * 0b10..Shifter pin bidirectional output data * 0b11..Shifter pin output */ #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) /*! TIMPOL - Timer Polarity * 0b0..Positive edge * 0b1..Negative edge */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) /*! TIMSEL - Timer Select */ #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) /*! @} */ /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (8U) /*! @name SHIFTCFG - Shifter Configuration */ /*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) /*! SSTART - Shifter Start * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, * Receiver and Match Store modes set error flag * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, * Receiver and Match Store modes set error flag */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) /*! SSTOP - Shifter Stop * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, * Receiver and Match Store modes store receive data on the configured shift edge * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the * configured shift edge) * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the * configured shift edge) */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) /*! INSRC - Input Source * 0b0..Pin * 0b1..Shifter n+1 output */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) #define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) #define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) /*! LATST - Late Store * 0b0..Store the pre-shift register state * 0b1..Store the post-shift register state */ #define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) #define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) #define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) /*! SSIZE - Shifter Size * 0b0..32-bit * 0b1..24-bit */ #define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) /*! PWIDTH - Parallel Width */ #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /*! @} */ /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (8U) /*! @name SHIFTBUF - Shifter Buffer */ /*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) /*! SHIFTBUF - Shift Buffer */ #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (8U) /*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) /*! SHIFTBUFBIS - Shift Buffer */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (8U) /*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) /*! SHIFTBUFBYS - Shift Buffer */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (8U) /*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) /*! SHIFTBUFBBS - Shift Buffer */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (8U) /*! @name TIMCTL - Timer Control */ /*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) /*! TIMOD - Timer Mode * 0b000..Timer disabled * 0b001..Dual 8-bit counters baud mode * 0b010..Dual 8-bit counters PWM high mode * 0b011..Single 16-bit counter mode * 0b100..Single 16-bit counter disable mode * 0b101..Dual 8-bit counters word mode * 0b110..Dual 8-bit counters PWM low mode * 0b111..Single 16-bit input capture mode */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) #define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) /*! ONETIM - Timer One Time Operation * 0b0..Generate the timer enable event as normal * 0b1..Block the timer enable event unless the timer status flag is clear */ #define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) #define FLEXIO_TIMCTL_PININS_MASK (0x40U) #define FLEXIO_TIMCTL_PININS_SHIFT (6U) /*! PININS - Timer Pin Input Select * 0b0..PINSEL selects timer pin input and output * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL */ #define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) /*! PINPOL - Timer Pin Polarity * 0b0..Active high * 0b1..Active low */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) /*! PINSEL - Timer Pin Select */ #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) /*! PINCFG - Timer Pin Configuration * 0b00..Timer pin output disabled * 0b01..Timer pin open-drain or bidirectional output enable * 0b10..Timer pin bidirectional output data * 0b11..Timer pin output */ #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) /*! TRGSRC - Trigger Source * 0b0..External * 0b1..Internal */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) /*! TRGPOL - Trigger Polarity * 0b0..Active high * 0b1..Active low */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) /*! TRGSEL - Trigger Select */ #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /*! @} */ /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (8U) /*! @name TIMCFG - Timer Configuration */ /*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) /*! TSTART - Timer Start * 0b0..Disabled * 0b1..Enabled */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) /*! TSTOP - Timer Stop * 0b00..Disabled * 0b01..Enabled on timer compare * 0b10..Enabled on timer disable * 0b11..Enabled on timer compare and timer disable */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) /*! TIMENA - Timer Enable * 0b000..Timer always enabled * 0b001..Timer enabled on timer n-1 enable * 0b010..Timer enabled on trigger high * 0b011..Timer enabled on trigger high and pin high * 0b100..Timer enabled on pin rising edge * 0b101..Timer enabled on pin rising edge and trigger high * 0b110..Timer enabled on trigger rising edge * 0b111..Timer enabled on trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) /*! TIMDIS - Timer Disable * 0b000..Timer never disabled * 0b001..Timer disabled on timer n-1 disable * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low * 0b100..Timer disabled on pin rising or falling edge * 0b101..Timer disabled on pin rising or falling edge provided trigger is high * 0b110..Timer disabled on trigger falling edge * 0b111..Reserved */ #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) /*! TIMRST - Timer Reset * 0b000..Never reset timer * 0b001..Timer reset on timer output high. * 0b010..Timer reset on timer pin equal to timer output * 0b011..Timer reset on timer trigger equal to timer output * 0b100..Timer reset on timer pin rising edge * 0b101..Reserved * 0b110..Timer reset on trigger rising edge * 0b111..Timer reset on trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) #define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) /*! TIMDEC - Timer Decrement * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) /*! TIMOUT - Timer Output * 0b00..Logic one when enabled; not affected by timer reset * 0b01..Logic zero when enabled; not affected by timer reset * 0b10..Logic one when enabled and on timer reset * 0b11..Logic zero when enabled and on timer reset */ #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) /*! @} */ /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (8U) /*! @name TIMCMP - Timer Compare */ /*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) #define FLEXIO_TIMCMP_CMP_SHIFT (0U) /*! CMP - Timer Compare Value */ #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) /*! @} */ /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (8U) /*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) /*! SHIFTBUFNBS - Shift Buffer */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFNBS */ #define FLEXIO_SHIFTBUFNBS_COUNT (8U) /*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) /*! SHIFTBUFHWS - Shift Buffer */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFHWS */ #define FLEXIO_SHIFTBUFHWS_COUNT (8U) /*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) /*! SHIFTBUFNIS - Shift Buffer */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFNIS */ #define FLEXIO_SHIFTBUFNIS_COUNT (8U) /*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) /*! SHIFTBUFOES - Shift Buffer */ #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFOES */ #define FLEXIO_SHIFTBUFOES_COUNT (8U) /*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) /*! SHIFTBUFEOS - Shift Buffer */ #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFEOS */ #define FLEXIO_SHIFTBUFEOS_COUNT (8U) /*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) /*! SHIFTBUFHBS - Shift Buffer */ #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFHBS */ #define FLEXIO_SHIFTBUFHBS_COUNT (8U) /*! * @} */ /* end of group FLEXIO_Register_Masks */ /* FLEXIO - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral FLEXIO0 base address */ #define FLEXIO0_BASE (0x50105000u) /** Peripheral FLEXIO0 base address */ #define FLEXIO0_BASE_NS (0x40105000u) /** Peripheral FLEXIO0 base pointer */ #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) /** Peripheral FLEXIO0 base pointer */ #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) /** Array initializer of FLEXIO peripheral base addresses */ #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } /** Array initializer of FLEXIO peripheral base pointers */ #define FLEXIO_BASE_PTRS { FLEXIO0 } /** Array initializer of FLEXIO peripheral base addresses */ #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } /** Array initializer of FLEXIO peripheral base pointers */ #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } #else /** Peripheral FLEXIO0 base address */ #define FLEXIO0_BASE (0x40105000u) /** Peripheral FLEXIO0 base pointer */ #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) /** Array initializer of FLEXIO peripheral base addresses */ #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } /** Array initializer of FLEXIO peripheral base pointers */ #define FLEXIO_BASE_PTRS { FLEXIO0 } #endif /** Interrupt vectors for the FLEXIO peripheral type */ #define FLEXIO_IRQS { FLEXIO_IRQn } /*! * @} */ /* end of group FLEXIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FLEXSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer * @{ */ /** FLEXSPI - Register Layout Typedef */ typedef struct { __IO uint32_t MCR0; /**< Module Control 0, offset: 0x0 */ __IO uint32_t MCR1; /**< Module Control 1, offset: 0x4 */ __IO uint32_t MCR2; /**< Module Control 2, offset: 0x8 */ __IO uint32_t AHBCR; /**< AHB Bus Control, offset: 0xC */ __IO uint32_t INTEN; /**< Interrupt Enable, offset: 0x10 */ __IO uint32_t INTR; /**< Interrupt, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control, offset: 0x1C */ __IO uint32_t AHBRXBUFCR0[8]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; __IO uint32_t FLSHCR0[4]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ __IO uint32_t FLSHCR1[4]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ __IO uint32_t FLSHCR2[4]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control 4, offset: 0x94 */ uint8_t RESERVED_2[8]; __IO uint32_t IPCR0; /**< IP Control 0, offset: 0xA0 */ __IO uint32_t IPCR1; /**< IP Control 1, offset: 0xA4 */ __IO uint32_t IPCR2; /**< IP Control 2, offset: 0xA8 */ uint8_t RESERVED_3[4]; __O uint32_t IPCMD; /**< IP Command, offset: 0xB0 */ __IO uint32_t DLPR; /**< Data Learning Pattern, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ __IO uint32_t DLLCR[2]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __I uint32_t STS0; /**< Status 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status 1, offset: 0xE4 */ __I uint32_t STS2; /**< Status 2, offset: 0xE8 */ __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status, offset: 0xEC */ __I uint32_t IPRXFSTS; /**< IP Receive FIFO Status, offset: 0xF0 */ __I uint32_t IPTXFSTS; /**< IP Transmit FIFO Status, offset: 0xF4 */ uint8_t RESERVED_5[8]; __I uint32_t RFDR[32]; /**< IP Receive FIFO Data 0..IP Receive FIFO Data 31, array offset: 0x100, array step: 0x4 */ __O uint32_t TFDR[32]; /**< IP TX FIFO Data 0..IP TX FIFO Data 31, array offset: 0x180, array step: 0x4 */ __IO uint32_t LUT[64]; /**< Lookup Table 0..Lookup Table 63, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_6[288]; __IO uint32_t HADDRSTART; /**< HADDR REMAP Start Address, offset: 0x420 */ __IO uint32_t HADDREND; /**< HADDR REMAP END ADDR, offset: 0x424 */ __IO uint32_t HADDROFFSET; /**< HADDR Remap Offset, offset: 0x428 */ __IO uint32_t IPEDCTRL; /**< IPED Function Control, offset: 0x42C */ __IO uint32_t IPSNSZSTART0; /**< IPS Nonsecure Region 0 Start Address, offset: 0x430 */ __IO uint32_t IPSNSZEND0; /**< IPS Nonsecure Region 0 End Address, offset: 0x434 */ __IO uint32_t IPSNSZSTART1; /**< IPS Nonsecure Region 1 Start Address, offset: 0x438 */ __IO uint32_t IPSNSZEND1; /**< IPS Nonsecure Region 1 End Address, offset: 0x43C */ __IO uint32_t AHBBUFREGIONSTART0; /**< Receive Buffer Start Address of Region 0, offset: 0x440 */ __IO uint32_t AHBBUFREGIONEND0; /**< Receive Buffer Region 0 End Address, offset: 0x444 */ __IO uint32_t AHBBUFREGIONSTART1; /**< Receive Buffer Start Address of Region 1, offset: 0x448 */ __IO uint32_t AHBBUFREGIONEND1; /**< Receive Buffer Region 1 End Address, offset: 0x44C */ __IO uint32_t AHBBUFREGIONSTART2; /**< Receive Buffer Start Address of Region 2, offset: 0x450 */ __IO uint32_t AHBBUFREGIONEND2; /**< Receive Buffer Region 2 End Address, offset: 0x454 */ __IO uint32_t AHBBUFREGIONSTART3; /**< Receive Buffer Start Address of Region 3, offset: 0x458 */ __IO uint32_t AHBBUFREGIONEND3; /**< Receive Buffer Region 3 End Address, offset: 0x45C */ uint8_t RESERVED_7[160]; __IO uint32_t IPEDCTXCTRL[2]; /**< IPED context control 0..IPED context control 1, array offset: 0x500, array step: 0x4 */ uint8_t RESERVED_8[24]; __IO uint32_t IPEDCTX0IV0; /**< IPED Context0 IV0, offset: 0x520 */ __IO uint32_t IPEDCTX0IV1; /**< IPED Context0 IV1, offset: 0x524 */ __IO uint32_t IPEDCTX0START; /**< Start Address of Region, offset: 0x528 */ __IO uint32_t IPEDCTX0END; /**< End Address of Region, offset: 0x52C */ __IO uint32_t IPEDCTX0AAD0; /**< IPED Context0 Additional Authenticated Data0, offset: 0x530 */ __IO uint32_t IPEDCTX0AAD1; /**< IPED Context0 Additional Authenticated Data1, offset: 0x534 */ uint8_t RESERVED_9[8]; __IO uint32_t IPEDCTX1IV0; /**< IPED Context1 IV0, offset: 0x540 */ __IO uint32_t IPEDCTX1IV1; /**< IPED Context1 IV1, offset: 0x544 */ __IO uint32_t IPEDCTX1START; /**< Start Address of Region, offset: 0x548 */ __IO uint32_t IPEDCTX1END; /**< End Address of Region, offset: 0x54C */ __IO uint32_t IPEDCTX1AAD0; /**< IPED Context1 Additional Authenticated Data0, offset: 0x550 */ __IO uint32_t IPEDCTX1AAD1; /**< IPED Context1 Additional Authenticated Data1, offset: 0x554 */ uint8_t RESERVED_10[8]; __IO uint32_t IPEDCTX2IV0; /**< IPED Context2 IV0, offset: 0x560 */ __IO uint32_t IPEDCTX2IV1; /**< IPED Context2 IV1, offset: 0x564 */ __IO uint32_t IPEDCTX2START; /**< Start Address of Region, offset: 0x568 */ __IO uint32_t IPEDCTX2END; /**< End Address of Region, offset: 0x56C */ __IO uint32_t IPEDCTX2AAD0; /**< IPED Context2 Additional Authenticated Data0, offset: 0x570 */ __IO uint32_t IPEDCTX2AAD1; /**< IPED Context2 Additional Authenticated Data1, offset: 0x574 */ uint8_t RESERVED_11[8]; __IO uint32_t IPEDCTX3IV0; /**< IPED Context3 IV0, offset: 0x580 */ __IO uint32_t IPEDCTX3IV1; /**< IPED Context3 IV1, offset: 0x584 */ __IO uint32_t IPEDCTX3START; /**< Start Address of Region, offset: 0x588 */ __IO uint32_t IPEDCTX3END; /**< End Address of Region, offset: 0x58C */ __IO uint32_t IPEDCTX3AAD0; /**< IPED Context3 Additional Authenticated Data0, offset: 0x590 */ __IO uint32_t IPEDCTX3AAD1; /**< IPED Context3 Additional Authenticated Data1, offset: 0x594 */ uint8_t RESERVED_12[8]; __IO uint32_t IPEDCTX4IV0; /**< IPED Context4 IV0, offset: 0x5A0 */ __IO uint32_t IPEDCTX4IV1; /**< IPED Context4 IV1, offset: 0x5A4 */ __IO uint32_t IPEDCTX4START; /**< Start Address of Region, offset: 0x5A8 */ __IO uint32_t IPEDCTX4END; /**< End Address of Region, offset: 0x5AC */ __IO uint32_t IPEDCTX4AAD0; /**< IPED Context4 Additional Authenticated Data0, offset: 0x5B0 */ __IO uint32_t IPEDCTX4AAD1; /**< IPED Context4 Additional Authenticated Data1, offset: 0x5B4 */ uint8_t RESERVED_13[8]; __IO uint32_t IPEDCTX5IV0; /**< IPED Context5 IV0, offset: 0x5C0 */ __IO uint32_t IPEDCTX5IV1; /**< IPED Context5 IV1, offset: 0x5C4 */ __IO uint32_t IPEDCTX5START; /**< Start Address of Region, offset: 0x5C8 */ __IO uint32_t IPEDCTX5END; /**< End Address of Region, offset: 0x5CC */ __IO uint32_t IPEDCTX5AAD0; /**< IPED Context5 Additional Authenticated Data0, offset: 0x5D0 */ __IO uint32_t IPEDCTX5AAD1; /**< IPED Context5 Additional Authenticated Data1, offset: 0x5D4 */ uint8_t RESERVED_14[8]; __IO uint32_t IPEDCTX6IV0; /**< IPED Context6 IV0, offset: 0x5E0 */ __IO uint32_t IPEDCTX6IV1; /**< IPED Context6 IV1, offset: 0x5E4 */ __IO uint32_t IPEDCTX6START; /**< Start Address of Region, offset: 0x5E8 */ __IO uint32_t IPEDCTX6END; /**< End Address of Region, offset: 0x5EC */ __IO uint32_t IPEDCTX6AAD0; /**< IPED Context6 Additional Authenticated Data0, offset: 0x5F0 */ __IO uint32_t IPEDCTX6AAD1; /**< IPED Context6 Additional Authenticated Data1, offset: 0x5F4 */ } FLEXSPI_Type; /* ---------------------------------------------------------------------------- -- FLEXSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks * @{ */ /*! @name MCR0 - Module Control 0 */ /*! @{ */ #define FLEXSPI_MCR0_SWRESET_MASK (0x1U) #define FLEXSPI_MCR0_SWRESET_SHIFT (0U) /*! SWRESET - Software Reset * 0b0..No impact * 0b1..Software reset */ #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) #define FLEXSPI_MCR0_MDIS_MASK (0x2U) #define FLEXSPI_MCR0_MDIS_SHIFT (1U) /*! MDIS - Module Disable * 0b0..No impact * 0b1..Module disable */ #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock Source for Flash Reading * 0b00..Dummy Read strobe that FlexSPI generates, looped back internally * 0b01..Dummy Read strobe that FlexSPI generates, looped back from DQS pad * 0b10..SCLK output clock and looped back from SCLK pad * 0b11..Flash-memory-provided read strobe and input from DQS pad */ #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) /*! ARDFEN - AHB Read Access to IP Receive FIFO Enable * 0b0..AHB read access disabled. IP bus reads IP receive FIFO. AHB Bus read access to IP receive FIFO memory space produces bus error. * 0b1..AHB read access enabled. AHB bus reads IP receive FIFO. IP Bus read access to IP receive FIFO memory * space returns data zero and causes no bus error. */ #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) /*! ATDFEN - AHB Write Access to IP Transmit FIFO Enable * 0b0..AHB write access disabled. IP bus writes to IP transmit FIFO. AHB bus write access to IP transmit FIFO memory space produces bus error. * 0b1..AHB write access enabled. AHB bus writes to IP transmit FIFO. IP Bus write access to IP transmit FIFO * memory space is ignored and causes no bus error. */ #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) #define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) #define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) /*! SERCLKDIV - Serial Root Clock Divider * 0b000..Divided by 1 * 0b001..Divided by 2 * 0b010..Divided by 3 * 0b011..Divided by 4 * 0b100..Divided by 5 * 0b101..Divided by 6 * 0b110..Divided by 7 * 0b111..Divided by 8 */ #define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) #define FLEXSPI_MCR0_HSEN_MASK (0x800U) #define FLEXSPI_MCR0_HSEN_SHIFT (11U) /*! HSEN - Half Speed Serial Flash Memory Access Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) /*! DOZEEN - Doze Mode Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) #define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) /*! COMBINATIONEN - Combination Mode Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) /*! SCKFREERUNEN - SCLK Free-running Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) #define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) #define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) /*! LEARNEN - Data Learning Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) /*! IPGRANTWAIT - Timeout Wait Cycle for IP Command Grant */ #define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) /*! AHBGRANTWAIT - Timeouts Wait Cycle for AHB command Grant */ #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) /*! @} */ /*! @name MCR1 - Module Control 1 */ /*! @{ */ #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) /*! AHBBUSWAIT - AHB Bus Wait */ #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) /*! SEQWAIT - Command Sequence Wait */ #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) /*! @} */ /*! @name MCR2 - Module Control 2 */ /*! @{ */ #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) /*! CLRAHBBUFOPT - Clear AHB Buffer * 0b0..Not cleared automatically * 0b1..Cleared automatically */ #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) /*! CLRLEARNPHASE - Clear Learn Phase Selection * 0b0..No impact * 0b1..Reset sample clock phase selection to 0 */ #define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) /*! SAMEDEVICEEN - Same Device Enable * 0b0..In Individual mode, FLSHA1CRx and FLSHA2CRx, FLSHB1CRx and FLSHB2CRx settings are applied to Flash A1, * A2, B1, B2 separately. In Parallel mode, FLSHA1CRx register setting is applied to Flash A1 and B1, FLSHA2CRx * register setting is applied to Flash A2 and B2. FLSHB1CRx and FLSHB2CRx register settings are ignored. * 0b1..FLSHA1CR0, FLSHA1CR1, and FLSHA1CR2 register settings are applied to Flash A1, A2, B1, B2. FLSHA2CRx, * FLSHB1CRx, and FLSHB2CRx settings are ignored. */ #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) /*! SCKBDIFFOPT - SCLK Port B Differential Output * 0b1..Use B_SCLK pad as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash memory access is not available. * 0b0..Use B_SCLK pad as port B SCLK clock output. Port B flash memory access is available. */ #define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) #define FLEXSPI_MCR2_RXCLKSRC_B_MASK (0x600000U) #define FLEXSPI_MCR2_RXCLKSRC_B_SHIFT (21U) /*! RXCLKSRC_B - Port B Receiver Clock Source * 0b00..Dummy read strobe that FlexSPI generates, looped back internally. * 0b01..Dummy read strobe that FlexSPI generates, looped back from DQS pad. * 0b10..SCLK output clock and looped back from SCLK pad * 0b11..Flash-memory-provided read strobe and input from DQS pad */ #define FLEXSPI_MCR2_RXCLKSRC_B(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RXCLKSRC_B_SHIFT)) & FLEXSPI_MCR2_RXCLKSRC_B_MASK) #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK (0x800000U) #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT (23U) /*! RX_CLK_SRC_DIFF - Sample Clock Source Different * 0b0..Use MCR0[RXCLKSRC] for Port A and Port B. MCR2[RXCLKSRC_B] is ignored and MCR0[RXCLKSRC] selects the * Sample Clock source for Flash Reading of both ports A and B. * 0b1..Use MCR0[RXCLKSRC] for Port A, and MCR2[RXCLKSRC_B] for Port B. MCR0[RXCLKSRC] selects the Sample Clock * source for Flash Reading of port A (A_SCLK) and MCR2[RXCLKSRC_B] selects the Sample Clock source for Flash * Reading of port B (B_SCLK). */ #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT)) & FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK) #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) /*! RESUMEWAIT - Resume Wait Duration */ #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) /*! @} */ /*! @name AHBCR - AHB Bus Control */ /*! @{ */ #define FLEXSPI_AHBCR_APAREN_MASK (0x1U) #define FLEXSPI_AHBCR_APAREN_SHIFT (0U) /*! APAREN - AHB Parallel Mode Enable * 0b0..Flash is accessed in Individual mode. * 0b1..Flash is accessed in Parallel mode. */ #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) #define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U) #define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U) /*! CLRAHBRXBUF - Clear AHB Receive Buffer * 0b0..No impact. * 0b1..Enable clear operation. */ #define FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) #define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK (0x4U) #define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT (2U) /*! CLRAHBTXBUF - Clear AHB Transmit Buffer * 0b0..No impact. * 0b1..Enable clear operation. */ #define FLEXSPI_AHBCR_CLRAHBTXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) /*! CACHABLEEN - Cacheable Read Access Enable * 0b0..Disabled. When an AHB bus cacheable read access occurs, FlexSPI does not check whether it hit the AHB transmit buffer. * 0b1..Enabled. When an AHB bus cacheable read access occurs, FlexSPI first checks whether the access hit the AHB transmit buffer. */ #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) /*! BUFFERABLEEN - Bufferable Write Access Enable * 0b0..Disabled. For all AHB write accesses (bufferable or nonbufferable), FlexSPI returns AHB Bus Ready after * transmitting all data and finishing command. * 0b1..Enabled. For AHB bufferable write access, FlexSPI returns AHB Bus Ready when the arbitrator grants the * AHB command. FlexSPI does not wait for the AHB command to finish. */ #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) /*! PREFETCHEN - AHB Read Prefetch Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) /*! READADDROPT - AHB Read Address Option * 0b0..AHB read burst start address alignment is limited when flash memory is accessed in parallel mode or flash is word-addressable. * 0b1..AHB read burst start address alignment is not limited. FlexSPI fetches more data than the AHB burst requires for address alignment. */ #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) #define FLEXSPI_AHBCR_RESUMEDISABLE_MASK (0x80U) #define FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT (7U) /*! RESUMEDISABLE - AHB Read Resume Disable * 0b0..Suspended AHB read prefetch resumes when AHB is IDLE. * 0b1..Suspended AHB read prefetch does not resume once aborted, */ #define FLEXSPI_AHBCR_RESUMEDISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT)) & FLEXSPI_AHBCR_RESUMEDISABLE_MASK) #define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) #define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) /*! READSZALIGN - AHB Read Size Alignment * 0b0..Register settings such as PREFETCH_EN determine AHB read size. * 0b1..AHB read size to up size to 8 bytes aligned, no prefetching */ #define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) #define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) #define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) /*! ALIGNMENT - AHB Boundary Alignment * 0b00..No limit * 0b01..1 KB * 0b10..512 bytes * 0b11..256 bytes */ #define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) #define FLEXSPI_AHBCR_AFLASHBASE_MASK (0xE0000000U) #define FLEXSPI_AHBCR_AFLASHBASE_SHIFT (29U) /*! AFLASHBASE - AHB Memory-Mapped Flash Base Address */ #define FLEXSPI_AHBCR_AFLASHBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable */ /*! @{ */ #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) /*! IPCMDDONEEN - IP-Triggered Command Sequences Execution Finished Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) #define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) /*! IPCMDGEEN - IP-Triggered Command Sequences Grant Timeout Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) #define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) /*! AHBCMDGEEN - AHB-Triggered Command Sequences Grant Timeout Interrupt Enable. * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) #define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) #define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) /*! IPCMDERREN - IP-Triggered Command Sequences Error Detected Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) #define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) /*! AHBCMDERREN - AHB-Triggered Command Sequences Error Detected Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) #define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) #define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) /*! IPRXWAEN - IP Receive FIFO Watermark Available Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) #define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) #define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) /*! IPTXWEEN - IP Transmit FIFO Watermark Empty Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) #define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) #define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) /*! DATALEARNFAILEN - Data Learning Failed Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) /*! SCKSTOPBYRDEN - SCLK Stopped By Read Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) /*! SCKSTOPBYWREN - SCLK Stopped By Write Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) /*! AHBBUSTIMEOUTEN - AHB Bus Timeout Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) /*! SEQTIMEOUTEN - Sequence execution Timeout Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U) #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U) /*! IPCMDSECUREVIOEN - IP Command Security Violation Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) #define FLEXSPI_INTEN_AHBGCMERREN_MASK (0x20000U) #define FLEXSPI_INTEN_AHBGCMERREN_SHIFT (17U) /*! AHBGCMERREN - AHB Read GCM Error Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_AHBGCMERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBGCMERREN_SHIFT)) & FLEXSPI_INTEN_AHBGCMERREN_MASK) /*! @} */ /*! @name INTR - Interrupt */ /*! @{ */ #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) /*! IPCMDDONE - IP-Triggered Command Sequences Execution Finished * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) #define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) #define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) /*! IPCMDGE - IP-Triggered Command Sequences Grant Timeout * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) #define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) /*! AHBCMDGE - AHB-Triggered Command Sequences Grant Timeout * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) #define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) #define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) /*! IPCMDERR - IP-Triggered Command Sequences Error * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) #define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) #define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) /*! AHBCMDERR - AHB-Triggered Command Sequences Error * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) #define FLEXSPI_INTR_IPRXWA_MASK (0x20U) #define FLEXSPI_INTR_IPRXWA_SHIFT (5U) /*! IPRXWA - IP Receive FIFO Watermark Available * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) #define FLEXSPI_INTR_IPTXWE_MASK (0x40U) #define FLEXSPI_INTR_IPTXWE_SHIFT (6U) /*! IPTXWE - IP Transmit FIFO Watermark Empty * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) #define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) #define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) /*! DATALEARNFAIL - Data Learning Failed * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) #define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) /*! SCKSTOPBYRD - SCLK Stopped Due To Full Receive FIFO * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) #define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) /*! SCKSTOPBYWR - SCLK Stopped Due To Empty Transmit FIFO * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) /*! AHBBUSTIMEOUT - AHB Bus Timeout * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) /*! SEQTIMEOUT - Sequence Execution Timeout * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) #define FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U) #define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U) /*! IPCMDSECUREVIO - IP Command Security Violation * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) #define FLEXSPI_INTR_AHBGCMERR_MASK (0x20000U) #define FLEXSPI_INTR_AHBGCMERR_SHIFT (17U) /*! AHBGCMERR - AHB Read GCM Error * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_AHBGCMERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBGCMERR_SHIFT)) & FLEXSPI_INTR_AHBGCMERR_MASK) /*! @} */ /*! @name LUTKEY - LUT Key */ /*! @{ */ #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define FLEXSPI_LUTKEY_KEY_SHIFT (0U) /*! KEY - LUT Key */ #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) /*! @} */ /*! @name LUTCR - LUT Control */ /*! @{ */ #define FLEXSPI_LUTCR_LOCK_MASK (0x1U) #define FLEXSPI_LUTCR_LOCK_SHIFT (0U) /*! LOCK - Lock LUT * 0b0..LUT is unlocked (LUTCR[UNLOCK] must be 1) * 0b1..LUT is locked and cannot be written */ #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) /*! UNLOCK - Unlock LUT * 0b0..LUT is locked (LUTCR[LOCK] must be 1) * 0b1..LUT is unlocked and can be written */ #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) #define FLEXSPI_LUTCR_PROTECT_MASK (0x4U) #define FLEXSPI_LUTCR_PROTECT_SHIFT (2U) /*! PROTECT - LUT Protection * 0b0..Not protected. All IPS controllers can access LUTCR and LUT memory. * 0b1..Protected. Only secure IPS controller can change the value of LUTCR and write to LUT memory. */ #define FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) /*! @} */ /*! @name AHBRXBUFCR0 - AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0 */ /*! @{ */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) /*! BUFSZ - AHB Receive Buffer Size */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0x1F0000U) #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) /*! MSTRID - AHB Controller ID */ #define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) /*! PRIORITY - AHB Controller Read Priority */ #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) #define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) #define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) /*! REGIONEN - AHB Receive Buffer Address Region Enable * 0b0..Disabled. The buffer hit is based on the value of MSTRID only. * 0b1..Enabled. The buffer hit is based on the value of MSTRID and the address within AHBBUFREGIONSTARTn and AHBREGIONENDn. */ #define FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) /*! PREFETCHEN - AHB Read Prefetch Enable * 0b0..Disabled * 0b1..Enabled when is enabled. */ #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ /* The count of FLEXSPI_AHBRXBUFCR0 */ #define FLEXSPI_AHBRXBUFCR0_COUNT (8U) /*! @name FLSHCR0 - Flash Control 0 */ /*! @{ */ #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) /*! FLSHSZ - Flash Size in KB */ #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) #define FLEXSPI_FLSHCR0_ADDRSHIFT_MASK (0x20000000U) #define FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT (29U) /*! ADDRSHIFT - AHB Address Shift Function control * 0b0..Disabled * 0b1..Enabled */ #define FLEXSPI_FLSHCR0_ADDRSHIFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK) #define FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U) #define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U) /*! SPLITWREN - AHB Write Access Split Function Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) #define FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U) #define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U) /*! SPLITRDEN - AHB Read Access Split Function Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR0 */ #define FLEXSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash Control 1 */ /*! @{ */ #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) /*! TCSS - Serial Flash CS Setup Time */ #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) #define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) #define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) /*! TCSH - Serial Flash CS Hold Time */ #define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) #define FLEXSPI_FLSHCR1_WA_MASK (0x400U) #define FLEXSPI_FLSHCR1_WA_SHIFT (10U) /*! WA - Word-Addressable * 0b0..Byte-addressable * 0b1..Word-addressable */ #define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) #define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) #define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) /*! CAS - Column Address Size */ #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) /*! CSINTERVALUNIT - Chip Select Interval Unit * 0b0..1 serial clock cycle * 0b1..256 serial clock cycles */ #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) /*! CSINTERVAL - Chip Select Interval */ #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR1 */ #define FLEXSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash Control 2 */ /*! @{ */ #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) /*! ARDSEQID - Sequence Index for AHB Read-Triggered Command in LUT */ #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) /*! ARDSEQNUM - Sequence Number for AHB Read-Triggered Command */ #define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) #define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) /*! AWRSEQID - Sequence Index for AHB Write-Triggered Command */ #define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) /*! AWRSEQNUM - Sequence Number for AHB Write-Triggered Command */ #define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) #define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) /*! AWRWAIT - AHB Write Wait */ #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) /*! AWRWAITUNIT - AWRWAIT Unit * 0b000..2 * 0b001..8 * 0b010..32 * 0b011..128 * 0b100..512 * 0b101..2048 * 0b110..8192 * 0b111..32768 */ #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) /*! CLRINSTRPTR - Clear Instruction Pointer */ #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR2 */ #define FLEXSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control 4 */ /*! @{ */ #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) /*! WMOPT1 - Write Mask Option 1 * 0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in * individual mode, AHB or IP write burst start address alignment is not limited. * 0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in * individual mode, AHB or IP write burst start address alignment is limited. */ #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) /*! WMENA - Write Mask Enable for Port A * 0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven. * 0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output. */ #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) /*! WMENB - Write Mask Enable for Port B * 0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven. * 0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output. */ #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) /*! @} */ /*! @name IPCR0 - IP Control 0 */ /*! @{ */ #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) #define FLEXSPI_IPCR0_SFAR_SHIFT (0U) /*! SFAR - Serial Flash Address */ #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) /*! @} */ /*! @name IPCR1 - IP Control 1 */ /*! @{ */ #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) /*! IDATSZ - Flash Read/Program Data Size (in bytes) for IP command. */ #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) #define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) #define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) /*! ISEQID - Sequence Index in LUT for IP command. */ #define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) #define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) #define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */ #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) /*! IPAREN - Parallel Mode Enable for IP Commands * 0b0..Disabled. Flash memory is accessed in Individual mode. * 0b1..Enabled. Flash memory is accessed in Parallel mode. */ #define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) /*! @} */ /*! @name IPCR2 - IP Control 2 */ /*! @{ */ #define FLEXSPI_IPCR2_IPBLKAHBREQ_MASK (0x1U) #define FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT (0U) /*! IPBLKAHBREQ - IP Command Blocking AHB Command Request Enable * 0b0..IP commands do not block AHB command requests. * 0b1..IP commands block AHB command requests. */ #define FLEXSPI_IPCR2_IPBLKAHBREQ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBREQ_MASK) #define FLEXSPI_IPCR2_IPBLKAHBACK_MASK (0x2U) #define FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT (1U) /*! IPBLKAHBACK - IP Command Blocking AHB Command Acknowledgment Enable * 0b0..IP commands do not block AHB command acknowledgment. * 0b1..IP commands block AHB command acknowledgment. */ #define FLEXSPI_IPCR2_IPBLKAHBACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBACK_MASK) #define FLEXSPI_IPCR2_IPBLKALLAHB_MASK (0x4U) #define FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT (2U) /*! IPBLKALLAHB - IP Command Blocking All AHB Command Enable * 0b0..IP commands only block AHB commands that affect the IPED region. * 0b1..IP commands block all AHB commands. */ #define FLEXSPI_IPCR2_IPBLKALLAHB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT)) & FLEXSPI_IPCR2_IPBLKALLAHB_MASK) /*! @} */ /*! @name IPCMD - IP Command */ /*! @{ */ #define FLEXSPI_IPCMD_TRG_MASK (0x1U) #define FLEXSPI_IPCMD_TRG_SHIFT (0U) /*! TRG - Command Trigger * 0b0..No action * 0b1..Start the IP command that the IPCR0 and IPCR1 registers define. */ #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) /*! @} */ /*! @name DLPR - Data Learning Pattern */ /*! @{ */ #define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) #define FLEXSPI_DLPR_DLP_SHIFT (0U) /*! DLP - Data Learning Pattern */ #define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) /*! @} */ /*! @name IPRXFCR - IP Receive FIFO Control */ /*! @{ */ #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) /*! CLRIPRXF - Clear IP Receive FIFO * 0b0..No function * 0b1..A clock cycle pulse clears all valid data entries in IP receive FIFO. */ #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) /*! RXDMAEN - IP Receive FIFO Reading by DMA Enable * 0b0..Disabled. The processor reads the FIFO. * 0b1..Enabled. DMA reads the FIFO. */ #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x1FCU) #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) /*! RXWMRK - IP Receive FIFO Watermark Level */ #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) /*! @} */ /*! @name IPTXFCR - IP Transmit FIFO Control */ /*! @{ */ #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) /*! CLRIPTXF - Clear IP Transmit FIFO * 0b0..No function * 0b1..A clock cycle pulse clears all valid data entries in the IP transmit FIFO. */ #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) /*! TXDMAEN - Transmit FIFO DMA Enable * 0b0..Processor * 0b1..DMA */ #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) /*! TXWMRK - Transmit Watermark Level */ #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) /*! @} */ /*! @name DLLCR - DLL Control 0 */ /*! @{ */ #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) /*! DLLEN - DLL Calibration Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) #define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) #define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) /*! DLLRESET - DLL reset * 0b0..No function * 0b1..Force DLL reset. */ #define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) /*! SLVDLYTARGET - Target Delay Line */ #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) #define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) /*! OVRDEN - Target Clock Delay Line Override Value Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) /*! OVRDVAL - Target Clock Delay Line Override Value */ #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) #define FLEXSPI_DLLCR_REFPHASEGAP_MASK (0x18000U) #define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT (15U) /*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */ #define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) /*! @} */ /* The count of FLEXSPI_DLLCR */ #define FLEXSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status 0 */ /*! @{ */ #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) /*! SEQIDLE - SEQ_CTL State Machine Idle * 0b0..Not idle * 0b1..Idle */ #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) #define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) #define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) /*! ARBIDLE - ARB_CTL State Machine Idle * 0b0..Not idle * 0b1..Idle */ #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) /*! ARBCMDSRC - ARB Command Source * 0b00..Trigger source is AHB read command. * 0b01..Trigger source is AHB write command. * 0b10..Trigger source is IP command (by writing 1 to IPCMD[TRG]). * 0b11..Trigger source is a suspended command that has resumed. */ #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) #define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) #define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) /*! DATALEARNPHASEA - Data Learning Phase Selection on Port A */ #define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) #define FLEXSPI_STS0_DATALEARNPHASEB_MASK (0xF00U) #define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT (8U) /*! DATALEARNPHASEB - Data Learning Phase Selection on Port B */ #define FLEXSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK) /*! @} */ /*! @name STS1 - Status 1 */ /*! @{ */ #define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) /*! AHBCMDERRID - AHB Command Error ID */ #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - AHB Command Error Code * 0b0000..No error * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence * 0b0011..Unknown instruction opcode in the sequence * 0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence * 0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence * 0b1110..Sequence execution timeout */ #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) #define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) /*! IPCMDERRID - IP Command Error ID */ #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) /*! IPCMDERRCODE - IP Command Error Code * 0b0000..No error * 0b0010..IP command with JMP_ON_CS instruction used in the sequence * 0b0011..Unknown instruction opcode in the sequence * 0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence * 0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence * 0b0110..Flash memory access start address exceeds entire flash address range (A1, A2, B1, and B2) * 0b1110..Sequence execution timeout * 0b1111..Flash boundary crossed */ #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) /*! @} */ /*! @name STS2 - Status 2 */ /*! @{ */ #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) /*! ASLVLOCK - Flash A Sample Target Delay Line Locked * 0b0..Not locked * 0b1..Locked */ #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) #define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) #define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) /*! AREFLOCK - Flash A Sample Clock Reference Delay Line Locked * 0b0..Not locked * 0b1..Locked */ #define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) #define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) #define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) /*! ASLVSEL - Flash A Sample Clock Target Delay Line Delay Cell Number */ #define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) #define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) #define FLEXSPI_STS2_AREFSEL_SHIFT (8U) /*! AREFSEL - Flash A Sample Clock Reference Delay Line Delay Cell Number */ #define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) #define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) #define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) /*! BSLVLOCK - Flash B Sample Target Reference Delay Line Locked * 0b0..Not locked * 0b1..Locked */ #define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) #define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) #define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) /*! BREFLOCK - Flash B Sample Clock Reference Delay Line Locked * 0b0..Not locked * 0b1..Locked */ #define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) #define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) #define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) /*! BSLVSEL - Flash B Sample Clock Target Delay Line Delay Cell Number */ #define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) #define FLEXSPI_STS2_BREFSEL_SHIFT (24U) /*! BREFSEL - Flash B Sample Clock Reference Delay Line Delay Cell Number */ #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) /*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status */ /*! @{ */ #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) /*! ACTIVE - Active AHB Read Prefetch Suspended * 0b0..No suspended AHB read prefetch command. * 0b1..An AHB read prefetch command sequence has been suspended. */ #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) #define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) /*! BUFID - AHB Receive Buffer ID for Suspended Command Sequence */ #define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) /*! DATLFT - Data Left */ #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) /*! @} */ /*! @name IPRXFSTS - IP Receive FIFO Status */ /*! @{ */ #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) /*! FILL - Fill Level of IP Receive FIFO */ #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) /*! RDCNTR - Read Data Counter */ #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) /*! @} */ /*! @name IPTXFSTS - IP Transmit FIFO Status */ /*! @{ */ #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) /*! FILL - Fill Level of IP Transmit FIFO */ #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) /*! WRCNTR - Write Data Counter */ #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) /*! @} */ /*! @name RFDR - IP Receive FIFO Data 0..IP Receive FIFO Data 31 */ /*! @{ */ #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_RFDR_RXDATA_SHIFT (0U) /*! RXDATA - Receive Data */ #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) /*! @} */ /* The count of FLEXSPI_RFDR */ #define FLEXSPI_RFDR_COUNT (32U) /*! @name TFDR - IP TX FIFO Data 0..IP TX FIFO Data 31 */ /*! @{ */ #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_TFDR_TXDATA_SHIFT (0U) /*! TXDATA - Transmit Data */ #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) /*! @} */ /* The count of FLEXSPI_TFDR */ #define FLEXSPI_TFDR_COUNT (32U) /*! @name LUT - Lookup Table 0..Lookup Table 63 */ /*! @{ */ #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) #define FLEXSPI_LUT_OPERAND0_SHIFT (0U) /*! OPERAND0 - OPERAND0 */ #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) #define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) #define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) /*! NUM_PADS0 - NUM_PADS0 */ #define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) #define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) #define FLEXSPI_LUT_OPCODE0_SHIFT (10U) /*! OPCODE0 - OPCODE */ #define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) #define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) #define FLEXSPI_LUT_OPERAND1_SHIFT (16U) /*! OPERAND1 - OPERAND1 */ #define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) #define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) #define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) /*! NUM_PADS1 - NUM_PADS1 */ #define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) #define FLEXSPI_LUT_OPCODE1_SHIFT (26U) /*! OPCODE1 - OPCODE1 */ #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) /*! @} */ /* The count of FLEXSPI_LUT */ #define FLEXSPI_LUT_COUNT (64U) /*! @name HADDRSTART - HADDR REMAP Start Address */ /*! @{ */ #define FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U) #define FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U) /*! REMAPEN - AHB Bus Address Remap Enable * 0b0..HADDR REMAP Disabled * 0b1..HADDR REMAP Enabled */ #define FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) #define FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U) #define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U) /*! ADDRSTART - HADDR Start Address */ #define FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK) /*! @} */ /*! @name HADDREND - HADDR REMAP END ADDR */ /*! @{ */ #define FLEXSPI_HADDREND_ENDSTART_MASK (0xFFFFF000U) #define FLEXSPI_HADDREND_ENDSTART_SHIFT (12U) /*! ENDSTART - End Address of HADDR Remap Range */ #define FLEXSPI_HADDREND_ENDSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK) /*! @} */ /*! @name HADDROFFSET - HADDR Remap Offset */ /*! @{ */ #define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK (0xFFFFF000U) #define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT (12U) /*! ADDROFFSET - HADDR Offset */ #define FLEXSPI_HADDROFFSET_ADDROFFSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK) /*! @} */ /*! @name IPEDCTRL - IPED Function Control */ /*! @{ */ #define FLEXSPI_IPEDCTRL_CONFIG_MASK (0x1U) #define FLEXSPI_IPEDCTRL_CONFIG_SHIFT (0U) /*! CONFIG - IPED Mode Select * 0b0..Fully pipelined * 0b1..Not fully pipelined */ #define FLEXSPI_IPEDCTRL_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_CONFIG_SHIFT)) & FLEXSPI_IPEDCTRL_CONFIG_MASK) #define FLEXSPI_IPEDCTRL_IPED_EN_MASK (0x2U) #define FLEXSPI_IPEDCTRL_IPED_EN_SHIFT (1U) /*! IPED_EN - IPED Encryption and Decryption Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_IPEDCTRL_IPED_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_EN_MASK) #define FLEXSPI_IPEDCTRL_IPWR_EN_MASK (0x4U) #define FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT (2U) /*! IPWR_EN - IP Write IPED CTR Mode Encryption Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_IPEDCTRL_IPWR_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPWR_EN_MASK) #define FLEXSPI_IPEDCTRL_AHBWR_EN_MASK (0x8U) #define FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT (3U) /*! AHBWR_EN - AHB Write IPED CTR Mode Encryption Enable. * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_IPEDCTRL_AHBWR_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBWR_EN_MASK) #define FLEXSPI_IPEDCTRL_AHBRD_EN_MASK (0x10U) #define FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT (4U) /*! AHBRD_EN - AHB Read IPED CTR Mode Decryption Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_IPEDCTRL_AHBRD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBRD_EN_MASK) #define FLEXSPI_IPEDCTRL_IPGCMWR_MASK (0x40U) #define FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT (6U) /*! IPGCMWR - IP Write GCM Mode Enable * 0b0..Disabled * 0b1..Enabled */ #define FLEXSPI_IPEDCTRL_IPGCMWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_IPGCMWR_MASK) #define FLEXSPI_IPEDCTRL_AHGCMWR_MASK (0x80U) #define FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT (7U) /*! AHGCMWR - AHB Write IPED GCM Mode Encryption Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_IPEDCTRL_AHGCMWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_AHGCMWR_MASK) #define FLEXSPI_IPEDCTRL_AHBGCMRD_MASK (0x100U) #define FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT (8U) /*! AHBGCMRD - AHB Read IPED GCM Mode Decryption Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_IPEDCTRL_AHBGCMRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT)) & FLEXSPI_IPEDCTRL_AHBGCMRD_MASK) #define FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK (0x200U) #define FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT (9U) /*! IPED_PROTECT - IPED Protection * 0b0..No restrictions * 0b1..Only privileged controllers can write IPED registers. */ #define FLEXSPI_IPEDCTRL_IPED_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK) #define FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK (0x400U) #define FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT (10U) /*! IPED_SWRESET - Abort Current Decryption or Encryption * 0b0..No function. * 0b1..Aborts current decryption or encryption and waits for the next start operation. */ #define FLEXSPI_IPEDCTRL_IPED_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK) /*! @} */ /*! @name IPSNSZSTART0 - IPS Nonsecure Region 0 Start Address */ /*! @{ */ #define FLEXSPI_IPSNSZSTART0_start_address_MASK (0xFFFFF000U) #define FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U) /*! start_address - Start Address of Nonsecure Region */ #define FLEXSPI_IPSNSZSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK) /*! @} */ /*! @name IPSNSZEND0 - IPS Nonsecure Region 0 End Address */ /*! @{ */ #define FLEXSPI_IPSNSZEND0_end_address_MASK (0xFFFFF000U) #define FLEXSPI_IPSNSZEND0_end_address_SHIFT (12U) /*! end_address - End Address of Nonsecure Region */ #define FLEXSPI_IPSNSZEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK) /*! @} */ /*! @name IPSNSZSTART1 - IPS Nonsecure Region 1 Start Address */ /*! @{ */ #define FLEXSPI_IPSNSZSTART1_start_address_MASK (0xFFFFF000U) #define FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U) /*! start_address - Start Address of Nonsecure Region */ #define FLEXSPI_IPSNSZSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK) /*! @} */ /*! @name IPSNSZEND1 - IPS Nonsecure Region 1 End Address */ /*! @{ */ #define FLEXSPI_IPSNSZEND1_end_address_MASK (0xFFFFF000U) #define FLEXSPI_IPSNSZEND1_end_address_SHIFT (12U) /*! end_address - End Address of Nonsecure Region */ #define FLEXSPI_IPSNSZEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK) /*! @} */ /*! @name AHBBUFREGIONSTART0 - Receive Buffer Start Address of Region 0 */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT (12U) /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONEND0 - Receive Buffer Region 0 End Address */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT (12U) /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONSTART1 - Receive Buffer Start Address of Region 1 */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT (12U) /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONEND1 - Receive Buffer Region 1 End Address */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT (12U) /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONSTART2 - Receive Buffer Start Address of Region 2 */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT (12U) /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONEND2 - Receive Buffer Region 2 End Address */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT (12U) /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONSTART3 - Receive Buffer Start Address of Region 3 */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT (12U) /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONEND3 - Receive Buffer Region 3 End Address */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT (12U) /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK) /*! @} */ /*! @name IPEDCTXCTRLX_IPEDCTXCTRL - IPED context control 0..IPED context control 1 */ /*! @{ */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK (0x3U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT (0U) /*! CTX0_FREEZE0 - Context Register Freeze for Region 0 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK (0x3U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT (0U) /*! CTX0_FREEZE1 - Context Register Freeze for Region 0 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK (0xCU) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT (2U) /*! CTX1_FREEZE0 - Context Register Freeze for Region 1 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK (0xCU) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT (2U) /*! CTX1_FREEZE1 - Context Register Freeze for Region 1 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK (0x30U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT (4U) /*! CTX2_FREEZE0 - Context Register Freeze for Region 2 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK (0x30U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT (4U) /*! CTX2_FREEZE1 - Context Register Freeze for Region 2 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK (0xC0U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT (6U) /*! CTX3_FREEZE0 - Context Register Freeze for Region 3 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK (0xC0U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT (6U) /*! CTX3_FREEZE1 - Context Register Freeze for Region 3 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0_MASK (0x300U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0_SHIFT (8U) /*! CTX4_FREEZE0 - Context Register Freeze for Region 4 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE0_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1_MASK (0x300U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1_SHIFT (8U) /*! CTX4_FREEZE1 - Context Register Freeze for Region 4 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX4_FREEZE1_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0_MASK (0xC00U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0_SHIFT (10U) /*! CTX5_FREEZE0 - Context Register Freeze for Region 5 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE0_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1_MASK (0xC00U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1_SHIFT (10U) /*! CTX5_FREEZE1 - Context Register Freeze for Region 5 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX5_FREEZE1_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0_MASK (0x3000U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0_SHIFT (12U) /*! CTX6_FREEZE0 - Context Register Freeze for Region 6 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE0_MASK) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1_MASK (0x3000U) #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1_SHIFT (12U) /*! CTX6_FREEZE1 - Context Register Freeze for Region 6 */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX6_FREEZE1_MASK) /*! @} */ /* The count of FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL */ #define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_COUNT (2U) /*! @name IPEDCTX0IV0 - IPED Context0 IV0 */ /*! @{ */ #define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT (0U) /*! CTX0_IV0 - Lowest 32 bits of IV for region 0. */ #define FLEXSPI_IPEDCTX0IV0_CTX0_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT)) & FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK) /*! @} */ /*! @name IPEDCTX0IV1 - IPED Context0 IV1 */ /*! @{ */ #define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT (0U) /*! CTX0_IV1 - Highest 32 bits of IV for region 0. */ #define FLEXSPI_IPEDCTX0IV1_CTX0_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT)) & FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK) /*! @} */ /*! @name IPEDCTX0START - Start Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX0START_GCM_MASK (0x1U) #define FLEXSPI_IPEDCTX0START_GCM_SHIFT (0U) /*! GCM - GCM Mode Enable * 0b0..Disabled. CTR mode is used. * 0b1..Enabled. GCM mode is used. */ #define FLEXSPI_IPEDCTX0START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_GCM_SHIFT)) & FLEXSPI_IPEDCTX0START_GCM_MASK) #define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK (0x2U) #define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT (1U) /*! ahbbuserror_dis - AHB Bus Error Disable * 0b0..AHB bus errors enabled * 0b1..AHB bus errors disabled */ #define FLEXSPI_IPEDCTX0START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK) #define FLEXSPI_IPEDCTX0START_start_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX0START_start_address_SHIFT (8U) /*! start_address - Start Address */ #define FLEXSPI_IPEDCTX0START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_start_address_SHIFT)) & FLEXSPI_IPEDCTX0START_start_address_MASK) /*! @} */ /*! @name IPEDCTX0END - End Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX0END_end_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX0END_end_address_SHIFT (8U) /*! end_address - End Address of IPED Region */ #define FLEXSPI_IPEDCTX0END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0END_end_address_SHIFT)) & FLEXSPI_IPEDCTX0END_end_address_MASK) /*! @} */ /*! @name IPEDCTX0AAD0 - IPED Context0 Additional Authenticated Data0 */ /*! @{ */ #define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT (0U) /*! CTX0_AAD0 - CTX AAD */ #define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT)) & FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK) /*! @} */ /*! @name IPEDCTX0AAD1 - IPED Context0 Additional Authenticated Data1 */ /*! @{ */ #define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT (0U) /*! CTX0_AAD1 - CTX AAD */ #define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT)) & FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK) /*! @} */ /*! @name IPEDCTX1IV0 - IPED Context1 IV0 */ /*! @{ */ #define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT (0U) /*! CTX1_IV0 - Lowest 32 bits of IV for region 1. */ #define FLEXSPI_IPEDCTX1IV0_CTX1_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT)) & FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK) /*! @} */ /*! @name IPEDCTX1IV1 - IPED Context1 IV1 */ /*! @{ */ #define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT (0U) /*! CTX1_IV1 - Highest 32 bits of IV for region 1. */ #define FLEXSPI_IPEDCTX1IV1_CTX1_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT)) & FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK) /*! @} */ /*! @name IPEDCTX1START - Start Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX1START_GCM_MASK (0x1U) #define FLEXSPI_IPEDCTX1START_GCM_SHIFT (0U) /*! GCM - GCM Mode Enable * 0b0..Disabled. CTR mode is used. * 0b1..Enabled. GCM mode is used. */ #define FLEXSPI_IPEDCTX1START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_GCM_SHIFT)) & FLEXSPI_IPEDCTX1START_GCM_MASK) #define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK (0x2U) #define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT (1U) /*! ahbbuserror_dis - AHB Bus Error Disable * 0b0..AHB bus errors enabled * 0b1..AHB bus errors disabled */ #define FLEXSPI_IPEDCTX1START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK) #define FLEXSPI_IPEDCTX1START_start_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX1START_start_address_SHIFT (8U) /*! start_address - Start Address */ #define FLEXSPI_IPEDCTX1START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_start_address_SHIFT)) & FLEXSPI_IPEDCTX1START_start_address_MASK) /*! @} */ /*! @name IPEDCTX1END - End Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX1END_end_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX1END_end_address_SHIFT (8U) /*! end_address - End Address of IPED Region */ #define FLEXSPI_IPEDCTX1END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1END_end_address_SHIFT)) & FLEXSPI_IPEDCTX1END_end_address_MASK) /*! @} */ /*! @name IPEDCTX1AAD0 - IPED Context1 Additional Authenticated Data0 */ /*! @{ */ #define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT (0U) /*! CTX1_AAD0 - CTX AAD */ #define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT)) & FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK) /*! @} */ /*! @name IPEDCTX1AAD1 - IPED Context1 Additional Authenticated Data1 */ /*! @{ */ #define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT (0U) /*! CTX1_AAD1 - CTX AAD */ #define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT)) & FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK) /*! @} */ /*! @name IPEDCTX2IV0 - IPED Context2 IV0 */ /*! @{ */ #define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT (0U) /*! CTX2_IV0 - Lowest 32 bits of IV for region 2. */ #define FLEXSPI_IPEDCTX2IV0_CTX2_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT)) & FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK) /*! @} */ /*! @name IPEDCTX2IV1 - IPED Context2 IV1 */ /*! @{ */ #define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT (0U) /*! CTX2_IV1 - Highest 32 bits of IV for region 2. */ #define FLEXSPI_IPEDCTX2IV1_CTX2_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT)) & FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK) /*! @} */ /*! @name IPEDCTX2START - Start Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX2START_GCM_MASK (0x1U) #define FLEXSPI_IPEDCTX2START_GCM_SHIFT (0U) /*! GCM - GCM Mode Enable * 0b0..Disabled. CTR mode is used. * 0b1..Enabled. GCM mode is used. */ #define FLEXSPI_IPEDCTX2START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_GCM_SHIFT)) & FLEXSPI_IPEDCTX2START_GCM_MASK) #define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK (0x2U) #define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT (1U) /*! ahbbuserror_dis - AHB Bus Error Disable * 0b0..AHB bus errors enabled * 0b1..AHB bus errors disabled */ #define FLEXSPI_IPEDCTX2START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK) #define FLEXSPI_IPEDCTX2START_start_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX2START_start_address_SHIFT (8U) /*! start_address - Start Address */ #define FLEXSPI_IPEDCTX2START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_start_address_SHIFT)) & FLEXSPI_IPEDCTX2START_start_address_MASK) /*! @} */ /*! @name IPEDCTX2END - End Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX2END_end_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX2END_end_address_SHIFT (8U) /*! end_address - End Address of IPED Region */ #define FLEXSPI_IPEDCTX2END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2END_end_address_SHIFT)) & FLEXSPI_IPEDCTX2END_end_address_MASK) /*! @} */ /*! @name IPEDCTX2AAD0 - IPED Context2 Additional Authenticated Data0 */ /*! @{ */ #define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT (0U) /*! CTX2_AAD0 - CTX AAD */ #define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT)) & FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK) /*! @} */ /*! @name IPEDCTX2AAD1 - IPED Context2 Additional Authenticated Data1 */ /*! @{ */ #define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT (0U) /*! CTX2_AAD1 - CTX AAD */ #define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT)) & FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK) /*! @} */ /*! @name IPEDCTX3IV0 - IPED Context3 IV0 */ /*! @{ */ #define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT (0U) /*! CTX3_IV0 - Lowest 32 bits of IV for region 3. */ #define FLEXSPI_IPEDCTX3IV0_CTX3_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT)) & FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK) /*! @} */ /*! @name IPEDCTX3IV1 - IPED Context3 IV1 */ /*! @{ */ #define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT (0U) /*! CTX3_IV1 - Highest 32 bits of IV for region 3. */ #define FLEXSPI_IPEDCTX3IV1_CTX3_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT)) & FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK) /*! @} */ /*! @name IPEDCTX3START - Start Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX3START_GCM_MASK (0x1U) #define FLEXSPI_IPEDCTX3START_GCM_SHIFT (0U) /*! GCM - GCM Mode Enable * 0b0..Disabled. CTR mode is used. * 0b1..Enabled. GCM mode is used. */ #define FLEXSPI_IPEDCTX3START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_GCM_SHIFT)) & FLEXSPI_IPEDCTX3START_GCM_MASK) #define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK (0x2U) #define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT (1U) /*! ahbbuserror_dis - AHB Bus Error Disable * 0b0..AHB bus errors enabled * 0b1..AHB bus errors disabled */ #define FLEXSPI_IPEDCTX3START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK) #define FLEXSPI_IPEDCTX3START_start_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX3START_start_address_SHIFT (8U) /*! start_address - Start Address */ #define FLEXSPI_IPEDCTX3START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_start_address_SHIFT)) & FLEXSPI_IPEDCTX3START_start_address_MASK) /*! @} */ /*! @name IPEDCTX3END - End Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX3END_end_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX3END_end_address_SHIFT (8U) /*! end_address - End Address of IPED Region */ #define FLEXSPI_IPEDCTX3END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3END_end_address_SHIFT)) & FLEXSPI_IPEDCTX3END_end_address_MASK) /*! @} */ /*! @name IPEDCTX3AAD0 - IPED Context3 Additional Authenticated Data0 */ /*! @{ */ #define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT (0U) /*! CTX3_AAD0 - CTX AAD */ #define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT)) & FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK) /*! @} */ /*! @name IPEDCTX3AAD1 - IPED Context3 Additional Authenticated Data1 */ /*! @{ */ #define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT (0U) /*! CTX3_AAD1 - CTX AAD */ #define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT)) & FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK) /*! @} */ /*! @name IPEDCTX4IV0 - IPED Context4 IV0 */ /*! @{ */ #define FLEXSPI_IPEDCTX4IV0_CTX4_IV0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX4IV0_CTX4_IV0_SHIFT (0U) /*! CTX4_IV0 - Lowest 32 bits of IV for region 4. */ #define FLEXSPI_IPEDCTX4IV0_CTX4_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4IV0_CTX4_IV0_SHIFT)) & FLEXSPI_IPEDCTX4IV0_CTX4_IV0_MASK) /*! @} */ /*! @name IPEDCTX4IV1 - IPED Context4 IV1 */ /*! @{ */ #define FLEXSPI_IPEDCTX4IV1_CTX4_IV1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX4IV1_CTX4_IV1_SHIFT (0U) /*! CTX4_IV1 - Highest 32 bits of IV for region 4. */ #define FLEXSPI_IPEDCTX4IV1_CTX4_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4IV1_CTX4_IV1_SHIFT)) & FLEXSPI_IPEDCTX4IV1_CTX4_IV1_MASK) /*! @} */ /*! @name IPEDCTX4START - Start Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX4START_GCM_MASK (0x1U) #define FLEXSPI_IPEDCTX4START_GCM_SHIFT (0U) /*! GCM - GCM Mode Enable * 0b0..Disabled. CTR mode is used. * 0b1..Enabled. GCM mode is used. */ #define FLEXSPI_IPEDCTX4START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_GCM_SHIFT)) & FLEXSPI_IPEDCTX4START_GCM_MASK) #define FLEXSPI_IPEDCTX4START_ahbbuserror_dis_MASK (0x2U) #define FLEXSPI_IPEDCTX4START_ahbbuserror_dis_SHIFT (1U) /*! ahbbuserror_dis - AHB Bus Error Disable * 0b0..AHB bus errors enabled * 0b1..AHB bus errors disabled */ #define FLEXSPI_IPEDCTX4START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX4START_ahbbuserror_dis_MASK) #define FLEXSPI_IPEDCTX4START_start_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX4START_start_address_SHIFT (8U) /*! start_address - Start Address */ #define FLEXSPI_IPEDCTX4START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4START_start_address_SHIFT)) & FLEXSPI_IPEDCTX4START_start_address_MASK) /*! @} */ /*! @name IPEDCTX4END - End Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX4END_end_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX4END_end_address_SHIFT (8U) /*! end_address - End Address of IPED Region */ #define FLEXSPI_IPEDCTX4END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4END_end_address_SHIFT)) & FLEXSPI_IPEDCTX4END_end_address_MASK) /*! @} */ /*! @name IPEDCTX4AAD0 - IPED Context4 Additional Authenticated Data0 */ /*! @{ */ #define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_SHIFT (0U) /*! CTX4_AAD0 - CTX AAD */ #define FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_SHIFT)) & FLEXSPI_IPEDCTX4AAD0_CTX4_AAD0_MASK) /*! @} */ /*! @name IPEDCTX4AAD1 - IPED Context4 Additional Authenticated Data1 */ /*! @{ */ #define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_SHIFT (0U) /*! CTX4_AAD1 - CTX AAD */ #define FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_SHIFT)) & FLEXSPI_IPEDCTX4AAD1_CTX4_AAD1_MASK) /*! @} */ /*! @name IPEDCTX5IV0 - IPED Context5 IV0 */ /*! @{ */ #define FLEXSPI_IPEDCTX5IV0_CTX5_IV0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX5IV0_CTX5_IV0_SHIFT (0U) /*! CTX5_IV0 - Lowest 32 bits of IV for region 5. */ #define FLEXSPI_IPEDCTX5IV0_CTX5_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5IV0_CTX5_IV0_SHIFT)) & FLEXSPI_IPEDCTX5IV0_CTX5_IV0_MASK) /*! @} */ /*! @name IPEDCTX5IV1 - IPED Context5 IV1 */ /*! @{ */ #define FLEXSPI_IPEDCTX5IV1_CTX5_IV1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX5IV1_CTX5_IV1_SHIFT (0U) /*! CTX5_IV1 - Highest 32 bits of IV for region 5. */ #define FLEXSPI_IPEDCTX5IV1_CTX5_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5IV1_CTX5_IV1_SHIFT)) & FLEXSPI_IPEDCTX5IV1_CTX5_IV1_MASK) /*! @} */ /*! @name IPEDCTX5START - Start Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX5START_GCM_MASK (0x1U) #define FLEXSPI_IPEDCTX5START_GCM_SHIFT (0U) /*! GCM - GCM Mode Enable * 0b0..Disabled. CTR mode is used. * 0b1..Enabled. GCM mode is used. */ #define FLEXSPI_IPEDCTX5START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_GCM_SHIFT)) & FLEXSPI_IPEDCTX5START_GCM_MASK) #define FLEXSPI_IPEDCTX5START_ahbbuserror_dis_MASK (0x2U) #define FLEXSPI_IPEDCTX5START_ahbbuserror_dis_SHIFT (1U) /*! ahbbuserror_dis - AHB Bus Error Disable * 0b0..AHB bus errors enabled * 0b1..AHB bus errors disabled */ #define FLEXSPI_IPEDCTX5START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX5START_ahbbuserror_dis_MASK) #define FLEXSPI_IPEDCTX5START_start_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX5START_start_address_SHIFT (8U) /*! start_address - Start Address */ #define FLEXSPI_IPEDCTX5START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5START_start_address_SHIFT)) & FLEXSPI_IPEDCTX5START_start_address_MASK) /*! @} */ /*! @name IPEDCTX5END - End Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX5END_end_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX5END_end_address_SHIFT (8U) /*! end_address - End Address of IPED Region */ #define FLEXSPI_IPEDCTX5END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5END_end_address_SHIFT)) & FLEXSPI_IPEDCTX5END_end_address_MASK) /*! @} */ /*! @name IPEDCTX5AAD0 - IPED Context5 Additional Authenticated Data0 */ /*! @{ */ #define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_SHIFT (0U) /*! CTX5_AAD0 - CTX AAD */ #define FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_SHIFT)) & FLEXSPI_IPEDCTX5AAD0_CTX5_AAD0_MASK) /*! @} */ /*! @name IPEDCTX5AAD1 - IPED Context5 Additional Authenticated Data1 */ /*! @{ */ #define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_SHIFT (0U) /*! CTX5_AAD1 - CTX AAD */ #define FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_SHIFT)) & FLEXSPI_IPEDCTX5AAD1_CTX5_AAD1_MASK) /*! @} */ /*! @name IPEDCTX6IV0 - IPED Context6 IV0 */ /*! @{ */ #define FLEXSPI_IPEDCTX6IV0_CTX6_IV0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX6IV0_CTX6_IV0_SHIFT (0U) /*! CTX6_IV0 - Lowest 32 bits of IV for region 6. */ #define FLEXSPI_IPEDCTX6IV0_CTX6_IV0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6IV0_CTX6_IV0_SHIFT)) & FLEXSPI_IPEDCTX6IV0_CTX6_IV0_MASK) /*! @} */ /*! @name IPEDCTX6IV1 - IPED Context6 IV1 */ /*! @{ */ #define FLEXSPI_IPEDCTX6IV1_CTX6_IV1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX6IV1_CTX6_IV1_SHIFT (0U) /*! CTX6_IV1 - Highest 32 bits of IV for region 6. */ #define FLEXSPI_IPEDCTX6IV1_CTX6_IV1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6IV1_CTX6_IV1_SHIFT)) & FLEXSPI_IPEDCTX6IV1_CTX6_IV1_MASK) /*! @} */ /*! @name IPEDCTX6START - Start Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX6START_GCM_MASK (0x1U) #define FLEXSPI_IPEDCTX6START_GCM_SHIFT (0U) /*! GCM - GCM Mode Enable * 0b0..Disabled. CTR mode is used. * 0b1..Enabled. GCM mode is used. */ #define FLEXSPI_IPEDCTX6START_GCM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_GCM_SHIFT)) & FLEXSPI_IPEDCTX6START_GCM_MASK) #define FLEXSPI_IPEDCTX6START_ahbbuserror_dis_MASK (0x2U) #define FLEXSPI_IPEDCTX6START_ahbbuserror_dis_SHIFT (1U) /*! ahbbuserror_dis - AHB Bus Error Disable * 0b0..AHB bus errors enabled * 0b1..AHB bus errors disabled */ #define FLEXSPI_IPEDCTX6START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX6START_ahbbuserror_dis_MASK) #define FLEXSPI_IPEDCTX6START_start_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX6START_start_address_SHIFT (8U) /*! start_address - Start Address */ #define FLEXSPI_IPEDCTX6START_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6START_start_address_SHIFT)) & FLEXSPI_IPEDCTX6START_start_address_MASK) /*! @} */ /*! @name IPEDCTX6END - End Address of Region */ /*! @{ */ #define FLEXSPI_IPEDCTX6END_end_address_MASK (0xFFFFFF00U) #define FLEXSPI_IPEDCTX6END_end_address_SHIFT (8U) /*! end_address - End Address of IPED Region */ #define FLEXSPI_IPEDCTX6END_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6END_end_address_SHIFT)) & FLEXSPI_IPEDCTX6END_end_address_MASK) /*! @} */ /*! @name IPEDCTX6AAD0 - IPED Context6 Additional Authenticated Data0 */ /*! @{ */ #define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_SHIFT (0U) /*! CTX6_AAD0 - CTX AAD */ #define FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_SHIFT)) & FLEXSPI_IPEDCTX6AAD0_CTX6_AAD0_MASK) /*! @} */ /*! @name IPEDCTX6AAD1 - IPED Context6 Additional Authenticated Data1 */ /*! @{ */ #define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_MASK (0xFFFFFFFFU) #define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_SHIFT (0U) /*! CTX6_AAD1 - CTX AAD */ #define FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_SHIFT)) & FLEXSPI_IPEDCTX6AAD1_CTX6_AAD1_MASK) /*! @} */ /*! * @} */ /* end of group FLEXSPI_Register_Masks */ /* FLEXSPI - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral FLEXSPI0 base address */ #define FLEXSPI0_BASE (0x500C8000u) /** Peripheral FLEXSPI0 base address */ #define FLEXSPI0_BASE_NS (0x400C8000u) /** Peripheral FLEXSPI0 base pointer */ #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) /** Peripheral FLEXSPI0 base pointer */ #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) /** Array initializer of FLEXSPI peripheral base addresses */ #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } /** Array initializer of FLEXSPI peripheral base pointers */ #define FLEXSPI_BASE_PTRS { FLEXSPI0 } /** Array initializer of FLEXSPI peripheral base addresses */ #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } /** Array initializer of FLEXSPI peripheral base pointers */ #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } #else /** Peripheral FLEXSPI0 base address */ #define FLEXSPI0_BASE (0x400C8000u) /** Peripheral FLEXSPI0 base pointer */ #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) /** Array initializer of FLEXSPI peripheral base addresses */ #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } /** Array initializer of FLEXSPI peripheral base pointers */ #define FLEXSPI_BASE_PTRS { FLEXSPI0 } #endif /** Interrupt vectors for the FLEXSPI peripheral type */ #define FLEXSPI_IRQS { FLEXSPI0_IRQn } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE (0x18000000u) /** FlexSPI0 AMBA end address */ #define FlexSPI0_AMBA_END (0x1FFFFFFFu) /** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE_NS (0x08000000U) /** FlexSPI0 AMBA end address */ #define FlexSPI0_AMBA_END_NS (0x0FFFFFFFU) /* FlexSPI0 alias1 base address. */ #define FlexSPI0_ALIAS1_BASE (0x80000000U) /* FlexSPI0 alias1 base NS address. */ #define FlexSPI0_ALIAS1_BASE_NS (0x90000000U) /* FlexSPI0 alias2 base address. */ #define FlexSPI0_ALIAS2_BASE (0xA0000000U) /* FlexSPI0 alias2 base NS address. */ #define FlexSPI0_ALIAS2_BASE_NS (0xB0000000U) #else /** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE (0x08000000U) /** FlexSPI0 AMBA end address */ #define FlexSPI0_AMBA_END (0x0FFFFFFFU) /* FlexSPI0 alias1 base address. */ #define FlexSPI0_ALIAS1_BASE (0x80000000U) /* FlexSPI0 alias2 base address. */ #define FlexSPI0_ALIAS2_BASE (0xA0000000U) #endif /*! * @} */ /* end of group FLEXSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FMU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer * @{ */ /** FMU - Register Layout Typedef */ typedef struct { __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t FCCOB[8]; /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */ } FMU_Type; /* ---------------------------------------------------------------------------- -- FMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FMU_Register_Masks FMU Register Masks * @{ */ /*! @name FSTAT - Flash Status Register */ /*! @{ */ #define FMU_FSTAT_FAIL_MASK (0x1U) #define FMU_FSTAT_FAIL_SHIFT (0U) /*! FAIL - Command Fail Flag * 0b0..Error not detected * 0b1..Error detected */ #define FMU_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK) #define FMU_FSTAT_CMDABT_MASK (0x4U) #define FMU_FSTAT_CMDABT_SHIFT (2U) /*! CMDABT - Command Abort Flag * 0b0..No command abort detected * 0b1..Command abort detected */ #define FMU_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK) #define FMU_FSTAT_PVIOL_MASK (0x10U) #define FMU_FSTAT_PVIOL_SHIFT (4U) /*! PVIOL - Command Protection Violation Flag * 0b0..No protection violation detected * 0b1..Protection violation detected */ #define FMU_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK) #define FMU_FSTAT_ACCERR_MASK (0x20U) #define FMU_FSTAT_ACCERR_SHIFT (5U) /*! ACCERR - Command Access Error Flag * 0b0..No access error detected * 0b1..Access error detected */ #define FMU_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK) #define FMU_FSTAT_CWSABT_MASK (0x40U) #define FMU_FSTAT_CWSABT_SHIFT (6U) /*! CWSABT - Command Write Sequence Abort Flag * 0b0..Command write sequence not aborted * 0b1..Command write sequence aborted */ #define FMU_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK) #define FMU_FSTAT_CCIF_MASK (0x80U) #define FMU_FSTAT_CCIF_SHIFT (7U) /*! CCIF - Command Complete Interrupt Flag * 0b0..Flash command, initialization, or power mode recovery in progress * 0b1..Flash command, initialization, or power mode recovery has completed */ #define FMU_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK) #define FMU_FSTAT_CMDPRT_MASK (0x300U) #define FMU_FSTAT_CMDPRT_SHIFT (8U) /*! CMDPRT - Command protection level * 0b00..Secure, normal access * 0b01..Secure, privileged access * 0b10..Nonsecure, normal access * 0b11..Nonsecure, privileged access */ #define FMU_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK) #define FMU_FSTAT_CMDP_MASK (0x800U) #define FMU_FSTAT_CMDP_SHIFT (11U) /*! CMDP - Command protection status flag * 0b0..Command protection level and domain ID are stale * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set */ #define FMU_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK) #define FMU_FSTAT_CMDDID_MASK (0xF000U) #define FMU_FSTAT_CMDDID_SHIFT (12U) /*! CMDDID - Command domain ID */ #define FMU_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK) #define FMU_FSTAT_DFDIF_MASK (0x10000U) #define FMU_FSTAT_DFDIF_SHIFT (16U) /*! DFDIF - Double Bit Fault Detect Interrupt Flag * 0b0..Double bit fault not detected during a valid flash read access * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access */ #define FMU_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK) #define FMU_FSTAT_SALV_USED_MASK (0x20000U) #define FMU_FSTAT_SALV_USED_SHIFT (17U) /*! SALV_USED - Salvage Used for Erase operation * 0b0..Salvage not used during last operation * 0b1..Salvage used during the last erase operation */ #define FMU_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK) #define FMU_FSTAT_PEWEN_MASK (0x3000000U) #define FMU_FSTAT_PEWEN_SHIFT (24U) /*! PEWEN - Program-Erase Write Enable Control * 0b00..Writes are not enabled * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) * 0b10..Writes are enabled for one flash or IFR page (page programming) * 0b11..Reserved */ #define FMU_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK) #define FMU_FSTAT_PERDY_MASK (0x80000000U) #define FMU_FSTAT_PERDY_SHIFT (31U) /*! PERDY - Program-Erase Ready Control/Status Flag * 0b0..Program or sector erase command operation not stalled * 0b1..Program or sector erase command operation ready to execute */ #define FMU_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK) /*! @} */ /*! @name FCNFG - Flash Configuration Register */ /*! @{ */ #define FMU_FCNFG_CCIE_MASK (0x80U) #define FMU_FCNFG_CCIE_SHIFT (7U) /*! CCIE - Command Complete Interrupt Enable * 0b0..Command complete interrupt disabled * 0b1..Command complete interrupt enabled */ #define FMU_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK) #define FMU_FCNFG_ERSREQ_MASK (0x100U) #define FMU_FCNFG_ERSREQ_SHIFT (8U) /*! ERSREQ - Mass Erase Request * 0b0..No request or request complete * 0b1..Request to run the Mass Erase operation */ #define FMU_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK) #define FMU_FCNFG_DFDIE_MASK (0x10000U) #define FMU_FCNFG_DFDIE_SHIFT (16U) /*! DFDIE - Double Bit Fault Detect Interrupt Enable * 0b0..Double bit fault detect interrupt disabled * 0b1..Double bit fault detect interrupt enabled */ #define FMU_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK) #define FMU_FCNFG_ERSIEN0_MASK (0xF000000U) #define FMU_FCNFG_ERSIEN0_SHIFT (24U) /*! ERSIEN0 - Erase IFR Sector Enable - Block 0 * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command */ #define FMU_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK) #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) #define FMU_FCNFG_ERSIEN1_SHIFT (28U) /*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command */ #define FMU_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK) /*! @} */ /*! @name FCTRL - Flash Control Register */ /*! @{ */ #define FMU_FCTRL_RWSC_MASK (0xFU) #define FMU_FCTRL_RWSC_SHIFT (0U) /*! RWSC - Read Wait-State Control */ #define FMU_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK) #define FMU_FCTRL_FDFD_MASK (0x10000U) #define FMU_FCTRL_FDFD_SHIFT (16U) /*! FDFD - Force Double Bit Fault Detect * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt * request is generated if the DFDIE bit is set. */ #define FMU_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK) #define FMU_FCTRL_ABTREQ_MASK (0x1000000U) #define FMU_FCTRL_ABTREQ_SHIFT (24U) /*! ABTREQ - Abort Request * 0b0..No request to abort a command write sequence * 0b1..Request to abort a command write sequence */ #define FMU_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK) /*! @} */ /*! @name FCCOB - Flash Common Command Object Registers */ /*! @{ */ #define FMU_FCCOB_CCOBn_MASK (0xFFFFFFFFU) #define FMU_FCCOB_CCOBn_SHIFT (0U) /*! CCOBn - CCOBn */ #define FMU_FCCOB_CCOBn(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK) /*! @} */ /* The count of FMU_FCCOB */ #define FMU_FCCOB_COUNT (8U) /*! * @} */ /* end of group FMU_Register_Masks */ /* FMU - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral FMU0 base address */ #define FMU0_BASE (0x50043000u) /** Peripheral FMU0 base address */ #define FMU0_BASE_NS (0x40043000u) /** Peripheral FMU0 base pointer */ #define FMU0 ((FMU_Type *)FMU0_BASE) /** Peripheral FMU0 base pointer */ #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) /** Array initializer of FMU peripheral base addresses */ #define FMU_BASE_ADDRS { FMU0_BASE } /** Array initializer of FMU peripheral base pointers */ #define FMU_BASE_PTRS { FMU0 } /** Array initializer of FMU peripheral base addresses */ #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } /** Array initializer of FMU peripheral base pointers */ #define FMU_BASE_PTRS_NS { FMU0_NS } #else /** Peripheral FMU0 base address */ #define FMU0_BASE (0x40043000u) /** Peripheral FMU0 base pointer */ #define FMU0 ((FMU_Type *)FMU0_BASE) /** Array initializer of FMU peripheral base addresses */ #define FMU_BASE_ADDRS { FMU0_BASE } /** Array initializer of FMU peripheral base pointers */ #define FMU_BASE_PTRS { FMU0 } #endif /*! * @} */ /* end of group FMU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FMUTEST Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FMUTEST_Peripheral_Access_Layer FMUTEST Peripheral Access Layer * @{ */ /** FMUTEST - Register Layout Typedef */ typedef struct { __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ __I uint32_t FTEST; /**< Flash Test Register, offset: 0xC */ __IO uint32_t FCCOB0; /**< Flash Command Control 0 Register, offset: 0x10 */ __IO uint32_t FCCOB1; /**< Flash Command Control 1 Register, offset: 0x14 */ __IO uint32_t FCCOB2; /**< Flash Command Control 2 Register, offset: 0x18 */ __IO uint32_t FCCOB3; /**< Flash Command Control 3 Register, offset: 0x1C */ __IO uint32_t FCCOB4; /**< Flash Command Control 4 Register, offset: 0x20 */ __IO uint32_t FCCOB5; /**< Flash Command Control 5 Register, offset: 0x24 */ __IO uint32_t FCCOB6; /**< Flash Command Control 6 Register, offset: 0x28 */ __IO uint32_t FCCOB7; /**< Flash Command Control 7 Register, offset: 0x2C */ uint8_t RESERVED_0[208]; __IO uint32_t RESET_STATUS; /**< FMU Initialization Tracking Register, offset: 0x100 */ __IO uint32_t MCTL; /**< FMU Control Register, offset: 0x104 */ __I uint32_t BSEL_GEN; /**< FMU Block Select Generation Register, offset: 0x108 */ __IO uint32_t PWR_OPT; /**< Power Mode Options Register, offset: 0x10C */ __I uint32_t CMD_CHECK; /**< FMU Command Check Register, offset: 0x110 */ uint8_t RESERVED_1[12]; __IO uint32_t BSEL; /**< FMU Block Select Register, offset: 0x120 */ __IO uint32_t MSIZE; /**< FMU Memory Size Register, offset: 0x124 */ __IO uint32_t FLASH_RD_ADD; /**< Flash Read Address Register, offset: 0x128 */ uint8_t RESERVED_2[4]; __IO uint32_t FLASH_STOP_ADD; /**< Flash Stop Address Register, offset: 0x130 */ __IO uint32_t FLASH_RD_CTRL; /**< Flash Read Control Register, offset: 0x134 */ __IO uint32_t MM_ADDR; /**< Memory Map Address Register, offset: 0x138 */ uint8_t RESERVED_3[4]; __IO uint32_t MM_WDATA; /**< Memory Map Write Data Register, offset: 0x140 */ __IO uint32_t MM_CTL; /**< Memory Map Control Register, offset: 0x144 */ __IO uint32_t UINT_CTL; /**< User Interface Control Register, offset: 0x148 */ __IO uint32_t RD_DATA0; /**< Read Data 0 Register, offset: 0x14C */ __IO uint32_t RD_DATA1; /**< Read Data 1 Register, offset: 0x150 */ __IO uint32_t RD_DATA2; /**< Read Data 2 Register, offset: 0x154 */ __IO uint32_t RD_DATA3; /**< Read Data 3 Register, offset: 0x158 */ __IO uint32_t PARITY; /**< Parity Register, offset: 0x15C */ __IO uint32_t RD_PATH_CTRL_STATUS; /**< Read Path Control and Status Register, offset: 0x160 */ __IO uint32_t SMW_DIN0; /**< SMW DIN 0 Register, offset: 0x164 */ __IO uint32_t SMW_DIN1; /**< SMW DIN 1 Register, offset: 0x168 */ __IO uint32_t SMW_DIN2; /**< SMW DIN 2 Register, offset: 0x16C */ __IO uint32_t SMW_DIN3; /**< SMW DIN 3 Register, offset: 0x170 */ __IO uint32_t SMW_ADDR; /**< SMW Address Register, offset: 0x174 */ __IO uint32_t SMW_CMD_WAIT; /**< SMW Command and Wait Register, offset: 0x178 */ __I uint32_t SMW_STATUS; /**< SMW Status Register, offset: 0x17C */ __IO uint32_t SOCTRIM0_0; /**< SoC Trim Phrase 0 Word 0 Register, offset: 0x180 */ __IO uint32_t SOCTRIM0_1; /**< SoC Trim Phrase 0 Word 1 Register, offset: 0x184 */ __IO uint32_t SOCTRIM0_2; /**< SoC Trim Phrase 0 Word 2 Register, offset: 0x188 */ __IO uint32_t SOCTRIM0_3; /**< SoC Trim Phrase 0 Word 3 Register, offset: 0x18C */ __IO uint32_t SOCTRIM1_0; /**< SoC Trim Phrase 1 Word 0 Register, offset: 0x190 */ __IO uint32_t SOCTRIM1_1; /**< SoC Trim Phrase 1 Word 1 Register, offset: 0x194 */ __IO uint32_t SOCTRIM1_2; /**< SoC Trim Phrase 1 Word 2 Register, offset: 0x198 */ __IO uint32_t SOCTRIM1_3; /**< SoC Trim Phrase 1 Word 3 Register, offset: 0x19C */ __IO uint32_t SOCTRIM2_0; /**< SoC Trim Phrase 2 Word 0 Register, offset: 0x1A0 */ __IO uint32_t SOCTRIM2_1; /**< SoC Trim Phrase 2 Word 1 Register, offset: 0x1A4 */ __IO uint32_t SOCTRIM2_2; /**< SoC Trim Phrase 2 Word 2 Register, offset: 0x1A8 */ __IO uint32_t SOCTRIM2_3; /**< SoC Trim Phrase 2 Word 3 Register, offset: 0x1AC */ __IO uint32_t SOCTRIM3_0; /**< SoC Trim Phrase 3 Word 0 Register, offset: 0x1B0 */ __IO uint32_t SOCTRIM3_1; /**< SoC Trim Phrase 3 Word 1 Register, offset: 0x1B4 */ __IO uint32_t SOCTRIM3_2; /**< SoC Trim Phrase 3 Word 2 Register, offset: 0x1B8 */ __IO uint32_t SOCTRIM3_3; /**< SoC Trim Phrase 3 Word 3 Register, offset: 0x1BC */ __IO uint32_t SOCTRIM4_0; /**< SoC Trim Phrase 4 Word 0 Register, offset: 0x1C0 */ __IO uint32_t SOCTRIM4_1; /**< SoC Trim Phrase 4 Word 1 Register, offset: 0x1C4 */ __IO uint32_t SOCTRIM4_2; /**< SoC Trim Phrase 4 Word 2 Register, offset: 0x1C8 */ __IO uint32_t SOCTRIM4_3; /**< SoC Trim Phrase 4 Word 3 Register, offset: 0x1CC */ __IO uint32_t SOCTRIM5_0; /**< SoC Trim Phrase 5 Word 0 Register, offset: 0x1D0 */ __IO uint32_t SOCTRIM5_1; /**< SoC Trim Phrase 5 Word 1 Register, offset: 0x1D4 */ __IO uint32_t SOCTRIM5_2; /**< SoC Trim Phrase 5 Word 2 Register, offset: 0x1D8 */ __IO uint32_t SOCTRIM5_3; /**< SoC Trim Phrase 5 Word 3 Register, offset: 0x1DC */ __IO uint32_t SOCTRIM6_0; /**< SoC Trim Phrase 6 Word 0 Register, offset: 0x1E0 */ __IO uint32_t SOCTRIM6_1; /**< SoC Trim Phrase 6 Word 1 Register, offset: 0x1E4 */ __IO uint32_t SOCTRIM6_2; /**< SoC Trim Phrase 6 Word 2 Register, offset: 0x1E8 */ __IO uint32_t SOCTRIM6_3; /**< SoC Trim Phrase 6 Word 3 Register, offset: 0x1EC */ __IO uint32_t SOCTRIM7_0; /**< SoC Trim Phrase 7 Word 0 Register, offset: 0x1F0 */ __IO uint32_t SOCTRIM7_1; /**< SoC Trim Phrase 7 Word 1 Register, offset: 0x1F4 */ __IO uint32_t SOCTRIM7_2; /**< SoC Trim Phrase 7 Word 2 Register, offset: 0x1F8 */ __IO uint32_t SOCTRIM7_3; /**< SoC Trim Phrase 7 Word 3 Register, offset: 0x1FC */ uint8_t RESERVED_4[4]; __IO uint32_t R_IP_CONFIG; /**< BIST Configuration Register, offset: 0x204 */ __IO uint32_t R_TESTCODE; /**< BIST Test Code Register, offset: 0x208 */ __IO uint32_t R_DFT_CTRL; /**< BIST DFT Control Register, offset: 0x20C */ __IO uint32_t R_ADR_CTRL; /**< BIST Address Control Register, offset: 0x210 */ __IO uint32_t R_DATA_CTRL0; /**< BIST Data Control 0 Register, offset: 0x214 */ __IO uint32_t R_PIN_CTRL; /**< BIST Pin Control Register, offset: 0x218 */ __IO uint32_t R_CNT_LOOP_CTRL; /**< BIST Loop Count Control Register, offset: 0x21C */ __IO uint32_t R_TIMER_CTRL; /**< BIST Timer Control Register, offset: 0x220 */ __IO uint32_t R_TEST_CTRL; /**< BIST Test Control Register, offset: 0x224 */ __O uint32_t R_ABORT_LOOP; /**< BIST Abort Loop Register, offset: 0x228 */ __I uint32_t R_ADR_QUERY; /**< BIST Address Query Register, offset: 0x22C */ __I uint32_t R_DOUT_QUERY0; /**< BIST DOUT Query 0 Register, offset: 0x230 */ uint8_t RESERVED_5[8]; __I uint32_t R_SMW_QUERY; /**< BIST SMW Query Register, offset: 0x23C */ __IO uint32_t R_SMW_SETTING0; /**< BIST SMW Setting 0 Register, offset: 0x240 */ __IO uint32_t R_SMW_SETTING1; /**< BIST SMW Setting 1 Register, offset: 0x244 */ __IO uint32_t R_SMP_WHV0; /**< BIST SMP WHV Setting 0 Register, offset: 0x248 */ __IO uint32_t R_SMP_WHV1; /**< BIST SMP WHV Setting 1 Register, offset: 0x24C */ __IO uint32_t R_SME_WHV0; /**< BIST SME WHV Setting 0 Register, offset: 0x250 */ __IO uint32_t R_SME_WHV1; /**< BIST SME WHV Setting 1 Register, offset: 0x254 */ __IO uint32_t R_SMW_SETTING2; /**< BIST SMW Setting 2 Register, offset: 0x258 */ __I uint32_t R_D_MISR0; /**< BIST DIN MISR 0 Register, offset: 0x25C */ __I uint32_t R_A_MISR0; /**< BIST Address MISR 0 Register, offset: 0x260 */ __I uint32_t R_C_MISR0; /**< BIST Control MISR 0 Register, offset: 0x264 */ __IO uint32_t R_SMW_SETTING3; /**< BIST SMW Setting 3 Register, offset: 0x268 */ __IO uint32_t R_DATA_CTRL1; /**< BIST Data Control 1 Register, offset: 0x26C */ __IO uint32_t R_DATA_CTRL2; /**< BIST Data Control 2 Register, offset: 0x270 */ __IO uint32_t R_DATA_CTRL3; /**< BIST Data Control 3 Register, offset: 0x274 */ uint8_t RESERVED_6[8]; __I uint32_t R_REPAIR0_0; /**< BIST Repair 0 for Block 0 Register, offset: 0x280 */ __I uint32_t R_REPAIR0_1; /**< BIST Repair 1 Block 0 Register, offset: 0x284 */ __I uint32_t R_REPAIR1_0; /**< BIST Repair 0 Block 1 Register, offset: 0x288 */ __I uint32_t R_REPAIR1_1; /**< BIST Repair 1 Block 1 Register, offset: 0x28C */ uint8_t RESERVED_7[132]; __IO uint32_t R_DATA_CTRL0_EX; /**< BIST Data Control 0 Extension Register, offset: 0x314 */ uint8_t RESERVED_8[8]; __IO uint32_t R_TIMER_CTRL_EX; /**< BIST Timer Control Extension Register, offset: 0x320 */ uint8_t RESERVED_9[12]; __I uint32_t R_DOUT_QUERY1; /**< BIST DOUT Query 1 Register, offset: 0x330 */ uint8_t RESERVED_10[40]; __I uint32_t R_D_MISR1; /**< BIST DIN MISR 1 Register, offset: 0x35C */ __I uint32_t R_A_MISR1; /**< BIST Address MISR 1 Register, offset: 0x360 */ __I uint32_t R_C_MISR1; /**< BIST Control MISR 1 Register, offset: 0x364 */ uint8_t RESERVED_11[4]; __IO uint32_t R_DATA_CTRL1_EX; /**< BIST Data Control 1 Extension Register, offset: 0x36C */ __IO uint32_t R_DATA_CTRL2_EX; /**< BIST Data Control 2 Extension Register, offset: 0x370 */ __IO uint32_t R_DATA_CTRL3_EX; /**< BIST Data Control 3 Extension Register, offset: 0x374 */ uint8_t RESERVED_12[136]; __IO uint32_t SMW_TIMER_OPTION; /**< SMW Timer Option Register, offset: 0x400 */ __IO uint32_t SMW_SETTING_OPTION0; /**< SMW Setting Option 0 Register, offset: 0x404 */ __IO uint32_t SMW_SETTING_OPTION2; /**< SMW Setting Option 2 Register, offset: 0x408 */ __IO uint32_t SMW_SETTING_OPTION3; /**< SMW Setting Option 3 Register, offset: 0x40C */ __IO uint32_t SMW_SMP_WHV_OPTION0; /**< SMW SMP WHV Option 0 Register, offset: 0x410 */ __IO uint32_t SMW_SME_WHV_OPTION0; /**< SMW SME WHV Option 0 Register, offset: 0x414 */ __IO uint32_t SMW_SETTING_OPTION1; /**< SMW Setting Option 1 Register, offset: 0x418 */ __IO uint32_t SMW_SMP_WHV_OPTION1; /**< SMW SMP WHV Option 1 Register, offset: 0x41C */ __IO uint32_t SMW_SME_WHV_OPTION1; /**< SMW SME WHV Option 1 Register, offset: 0x420 */ uint8_t RESERVED_13[220]; __IO uint32_t REPAIR0_0; /**< FMU Repair 0 Block 0 Register, offset: 0x500 */ __IO uint32_t REPAIR0_1; /**< FMU Repair 1 Block 0 Register, offset: 0x504 */ __IO uint32_t REPAIR1_0; /**< FMU Repair 0 Block 1 Register, offset: 0x508 */ __IO uint32_t REPAIR1_1; /**< FMU Repair 1 Block 1 Register, offset: 0x50C */ uint8_t RESERVED_14[240]; __IO uint32_t SMW_HB_SIGNALS; /**< SMW HB Signals Register, offset: 0x600 */ __IO uint32_t BIST_DUMP_CTRL; /**< BIST Datadump Control Register, offset: 0x604 */ uint8_t RESERVED_15[4]; __IO uint32_t ATX_PIN_CTRL; /**< ATX Pin Control Register, offset: 0x60C */ __IO uint32_t FAILCNT; /**< Fail Count Register, offset: 0x610 */ __IO uint32_t PGM_PULSE_CNT0; /**< Block 0 Program Pulse Count Register, offset: 0x614 */ __IO uint32_t PGM_PULSE_CNT1; /**< Block 1 Program Pulse Count Register, offset: 0x618 */ __IO uint32_t ERS_PULSE_CNT; /**< Erase Pulse Count Register, offset: 0x61C */ __IO uint32_t MAX_PULSE_CNT; /**< Maximum Pulse Count Register, offset: 0x620 */ __IO uint32_t PORT_CTRL; /**< Port Control Register, offset: 0x624 */ } FMUTEST_Type; /* ---------------------------------------------------------------------------- -- FMUTEST Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FMUTEST_Register_Masks FMUTEST Register Masks * @{ */ /*! @name FSTAT - Flash Status Register */ /*! @{ */ #define FMUTEST_FSTAT_FAIL_MASK (0x1U) #define FMUTEST_FSTAT_FAIL_SHIFT (0U) /*! FAIL - Command Fail Flag * 0b0..Error not detected * 0b1..Error detected */ #define FMUTEST_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_FAIL_SHIFT)) & FMUTEST_FSTAT_FAIL_MASK) #define FMUTEST_FSTAT_CMDABT_MASK (0x4U) #define FMUTEST_FSTAT_CMDABT_SHIFT (2U) /*! CMDABT - Command Abort Flag * 0b0..No command abort detected * 0b1..Command abort detected */ #define FMUTEST_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDABT_SHIFT)) & FMUTEST_FSTAT_CMDABT_MASK) #define FMUTEST_FSTAT_PVIOL_MASK (0x10U) #define FMUTEST_FSTAT_PVIOL_SHIFT (4U) /*! PVIOL - Command Protection Violation Flag * 0b0..No protection violation detected * 0b1..Protection violation detected */ #define FMUTEST_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PVIOL_SHIFT)) & FMUTEST_FSTAT_PVIOL_MASK) #define FMUTEST_FSTAT_ACCERR_MASK (0x20U) #define FMUTEST_FSTAT_ACCERR_SHIFT (5U) /*! ACCERR - Command Access Error Flag * 0b0..No access error detected * 0b1..Access error detected */ #define FMUTEST_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_ACCERR_SHIFT)) & FMUTEST_FSTAT_ACCERR_MASK) #define FMUTEST_FSTAT_CWSABT_MASK (0x40U) #define FMUTEST_FSTAT_CWSABT_SHIFT (6U) /*! CWSABT - Command Write Sequence Abort Flag * 0b0..Command write sequence not aborted * 0b1..Command write sequence aborted */ #define FMUTEST_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CWSABT_SHIFT)) & FMUTEST_FSTAT_CWSABT_MASK) #define FMUTEST_FSTAT_CCIF_MASK (0x80U) #define FMUTEST_FSTAT_CCIF_SHIFT (7U) /*! CCIF - Command Complete Interrupt Flag * 0b0..Flash command or initialization in progress * 0b1..Flash command or initialization has completed */ #define FMUTEST_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CCIF_SHIFT)) & FMUTEST_FSTAT_CCIF_MASK) #define FMUTEST_FSTAT_CMDPRT_MASK (0x300U) #define FMUTEST_FSTAT_CMDPRT_SHIFT (8U) /*! CMDPRT - Command Protection Level * 0b00..Secure, normal access * 0b01..Secure, privileged access * 0b10..Nonsecure, normal access * 0b11..Nonsecure, privileged access */ #define FMUTEST_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDPRT_SHIFT)) & FMUTEST_FSTAT_CMDPRT_MASK) #define FMUTEST_FSTAT_CMDP_MASK (0x800U) #define FMUTEST_FSTAT_CMDP_SHIFT (11U) /*! CMDP - Command Protection Status Flag * 0b0..Command protection level and domain ID are stale * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set */ #define FMUTEST_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDP_SHIFT)) & FMUTEST_FSTAT_CMDP_MASK) #define FMUTEST_FSTAT_CMDDID_MASK (0xF000U) #define FMUTEST_FSTAT_CMDDID_SHIFT (12U) /*! CMDDID - Command Domain ID */ #define FMUTEST_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDDID_SHIFT)) & FMUTEST_FSTAT_CMDDID_MASK) #define FMUTEST_FSTAT_DFDIF_MASK (0x10000U) #define FMUTEST_FSTAT_DFDIF_SHIFT (16U) /*! DFDIF - Double Bit Fault Detect Interrupt Flag * 0b0..Double bit fault not detected during a valid flash read access from the FMC * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC */ #define FMUTEST_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_DFDIF_SHIFT)) & FMUTEST_FSTAT_DFDIF_MASK) #define FMUTEST_FSTAT_SALV_USED_MASK (0x20000U) #define FMUTEST_FSTAT_SALV_USED_SHIFT (17U) /*! SALV_USED - Salvage Used for Erase operation * 0b0..Salvage not used during the last operation * 0b1..Salvage used during the last erase operation */ #define FMUTEST_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_SALV_USED_SHIFT)) & FMUTEST_FSTAT_SALV_USED_MASK) #define FMUTEST_FSTAT_PEWEN_MASK (0x3000000U) #define FMUTEST_FSTAT_PEWEN_SHIFT (24U) /*! PEWEN - Program-Erase Write Enable Control * 0b00..Writes are not enabled * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) * 0b10..Writes are enabled for one flash or IFR page (page programming) * 0b11..Reserved */ #define FMUTEST_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PEWEN_SHIFT)) & FMUTEST_FSTAT_PEWEN_MASK) #define FMUTEST_FSTAT_PERDY_MASK (0x80000000U) #define FMUTEST_FSTAT_PERDY_SHIFT (31U) /*! PERDY - Program/Erase Ready Control/Status Flag * 0b0..Program or sector erase command operation is not stalled * 0b1..Program or sector erase command operation is stalled */ #define FMUTEST_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PERDY_SHIFT)) & FMUTEST_FSTAT_PERDY_MASK) /*! @} */ /*! @name FCNFG - Flash Configuration Register */ /*! @{ */ #define FMUTEST_FCNFG_CCIE_MASK (0x80U) #define FMUTEST_FCNFG_CCIE_SHIFT (7U) /*! CCIE - Command Complete Interrupt Enable * 0b0..Command complete interrupt disabled * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. */ #define FMUTEST_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_CCIE_SHIFT)) & FMUTEST_FCNFG_CCIE_MASK) #define FMUTEST_FCNFG_ERSREQ_MASK (0x100U) #define FMUTEST_FCNFG_ERSREQ_SHIFT (8U) /*! ERSREQ - Mass Erase (Erase All) Request * 0b0..No request or request complete * 0b1..Request to run the Mass Erase operation */ #define FMUTEST_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSREQ_SHIFT)) & FMUTEST_FCNFG_ERSREQ_MASK) #define FMUTEST_FCNFG_DFDIE_MASK (0x10000U) #define FMUTEST_FCNFG_DFDIE_SHIFT (16U) /*! DFDIE - Double Bit Fault Detect Interrupt Enable * 0b0..Double bit fault detect interrupt disabled * 0b1..Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set */ #define FMUTEST_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_DFDIE_SHIFT)) & FMUTEST_FCNFG_DFDIE_MASK) #define FMUTEST_FCNFG_ERSIEN0_MASK (0xF000000U) #define FMUTEST_FCNFG_ERSIEN0_SHIFT (24U) /*! ERSIEN0 - Erase IFR Sector Enable - Block 0 * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command */ #define FMUTEST_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN0_SHIFT)) & FMUTEST_FCNFG_ERSIEN0_MASK) #define FMUTEST_FCNFG_ERSIEN1_MASK (0xF0000000U) #define FMUTEST_FCNFG_ERSIEN1_SHIFT (28U) /*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command */ #define FMUTEST_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN1_SHIFT)) & FMUTEST_FCNFG_ERSIEN1_MASK) /*! @} */ /*! @name FCTRL - Flash Control Register */ /*! @{ */ #define FMUTEST_FCTRL_RWSC_MASK (0xFU) #define FMUTEST_FCTRL_RWSC_SHIFT (0U) /*! RWSC - Read Wait-State Control * 0b0000..no additional wait-states are added (single cycle access) * 0b0001..1 additional wait-state is added * 0b0010..2 additional wait-states are added * 0b0011..3 additional wait-states are added * 0b0100..4 additional wait-states are added * 0b0101..5 additional wait-states are added * 0b0110..6 additional wait-states are added * 0b0111..7 additional wait-states are added * 0b1000..8 additional wait-states are added * 0b1001..9 additional wait-states are added * 0b1010..10 additional wait-states are added * 0b1011..11 additional wait-states are added * 0b1100..12 additional wait-states are added * 0b1101..13 additional wait-states are added * 0b1110..14 additional wait-states are added * 0b1111..15 additional wait-states are added */ #define FMUTEST_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_RWSC_SHIFT)) & FMUTEST_FCTRL_RWSC_MASK) #define FMUTEST_FCTRL_LSACTIVE_MASK (0x100U) #define FMUTEST_FCTRL_LSACTIVE_SHIFT (8U) /*! LSACTIVE - Low Speed Active Mode * 0b0..Full speed active mode requested * 0b1..Low speed active mode requested */ #define FMUTEST_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_LSACTIVE_SHIFT)) & FMUTEST_FCTRL_LSACTIVE_MASK) #define FMUTEST_FCTRL_FDFD_MASK (0x10000U) #define FMUTEST_FCTRL_FDFD_SHIFT (16U) /*! FDFD - Force Double Bit Fault Detect * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set */ #define FMUTEST_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_FDFD_SHIFT)) & FMUTEST_FCTRL_FDFD_MASK) #define FMUTEST_FCTRL_ABTREQ_MASK (0x1000000U) #define FMUTEST_FCTRL_ABTREQ_SHIFT (24U) /*! ABTREQ - Abort Request * 0b0..No request to abort a command write sequence * 0b1..Request to abort a command write sequence */ #define FMUTEST_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_ABTREQ_SHIFT)) & FMUTEST_FCTRL_ABTREQ_MASK) /*! @} */ /*! @name FTEST - Flash Test Register */ /*! @{ */ #define FMUTEST_FTEST_TMECTL_MASK (0x1U) #define FMUTEST_FTEST_TMECTL_SHIFT (0U) /*! TMECTL - Test Mode Entry Control * 0b0..FTEST register always reads 0 and writes to FTEST are ignored * 0b1..FTEST register is readable and can be written to enable writability of TME */ #define FMUTEST_FTEST_TMECTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMECTL_SHIFT)) & FMUTEST_FTEST_TMECTL_MASK) #define FMUTEST_FTEST_TMEWR_MASK (0x2U) #define FMUTEST_FTEST_TMEWR_SHIFT (1U) /*! TMEWR - Test Mode Entry Writable * 0b0..TME bit is not writable * 0b1..TME bit is writable */ #define FMUTEST_FTEST_TMEWR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMEWR_SHIFT)) & FMUTEST_FTEST_TMEWR_MASK) #define FMUTEST_FTEST_TME_MASK (0x4U) #define FMUTEST_FTEST_TME_SHIFT (2U) /*! TME - Test Mode Entry * 0b0..Test mode entry not requested * 0b1..Test mode entry requested */ #define FMUTEST_FTEST_TME(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TME_SHIFT)) & FMUTEST_FTEST_TME_MASK) #define FMUTEST_FTEST_TMODE_MASK (0x8U) #define FMUTEST_FTEST_TMODE_SHIFT (3U) /*! TMODE - Test Mode Status * 0b0..Test mode not active * 0b1..Test mode active */ #define FMUTEST_FTEST_TMODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMODE_SHIFT)) & FMUTEST_FTEST_TMODE_MASK) #define FMUTEST_FTEST_TMELOCK_MASK (0x10U) #define FMUTEST_FTEST_TMELOCK_SHIFT (4U) /*! TMELOCK - Test Mode Entry Lock * 0b0..FTEST register not locked from accepting writes * 0b1..FTEST register locked from accepting writes */ #define FMUTEST_FTEST_TMELOCK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMELOCK_SHIFT)) & FMUTEST_FTEST_TMELOCK_MASK) /*! @} */ /*! @name FCCOB0 - Flash Command Control 0 Register */ /*! @{ */ #define FMUTEST_FCCOB0_CMDCODE_MASK (0xFFU) #define FMUTEST_FCCOB0_CMDCODE_SHIFT (0U) /*! CMDCODE - Command code */ #define FMUTEST_FCCOB0_CMDCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB0_CMDCODE_SHIFT)) & FMUTEST_FCCOB0_CMDCODE_MASK) /*! @} */ /*! @name FCCOB1 - Flash Command Control 1 Register */ /*! @{ */ #define FMUTEST_FCCOB1_CMDOPT_MASK (0xFFU) #define FMUTEST_FCCOB1_CMDOPT_SHIFT (0U) /*! CMDOPT - Command options */ #define FMUTEST_FCCOB1_CMDOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB1_CMDOPT_SHIFT)) & FMUTEST_FCCOB1_CMDOPT_MASK) /*! @} */ /*! @name FCCOB2 - Flash Command Control 2 Register */ /*! @{ */ #define FMUTEST_FCCOB2_CMDADDR_MASK (0xFFFFFFFFU) #define FMUTEST_FCCOB2_CMDADDR_SHIFT (0U) /*! CMDADDR - Command starting address */ #define FMUTEST_FCCOB2_CMDADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB2_CMDADDR_SHIFT)) & FMUTEST_FCCOB2_CMDADDR_MASK) /*! @} */ /*! @name FCCOB3 - Flash Command Control 3 Register */ /*! @{ */ #define FMUTEST_FCCOB3_CMDADDRE_MASK (0xFFFFFFFFU) #define FMUTEST_FCCOB3_CMDADDRE_SHIFT (0U) /*! CMDADDRE - Command ending address */ #define FMUTEST_FCCOB3_CMDADDRE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB3_CMDADDRE_SHIFT)) & FMUTEST_FCCOB3_CMDADDRE_MASK) /*! @} */ /*! @name FCCOB4 - Flash Command Control 4 Register */ /*! @{ */ #define FMUTEST_FCCOB4_CMDDATA0_MASK (0xFFFFFFFFU) #define FMUTEST_FCCOB4_CMDDATA0_SHIFT (0U) /*! CMDDATA0 - Command data word 0 */ #define FMUTEST_FCCOB4_CMDDATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB4_CMDDATA0_SHIFT)) & FMUTEST_FCCOB4_CMDDATA0_MASK) /*! @} */ /*! @name FCCOB5 - Flash Command Control 5 Register */ /*! @{ */ #define FMUTEST_FCCOB5_CMDDATA1_MASK (0xFFFFFFFFU) #define FMUTEST_FCCOB5_CMDDATA1_SHIFT (0U) /*! CMDDATA1 - Command data word 1 */ #define FMUTEST_FCCOB5_CMDDATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB5_CMDDATA1_SHIFT)) & FMUTEST_FCCOB5_CMDDATA1_MASK) /*! @} */ /*! @name FCCOB6 - Flash Command Control 6 Register */ /*! @{ */ #define FMUTEST_FCCOB6_CMDDATA2_MASK (0xFFFFFFFFU) #define FMUTEST_FCCOB6_CMDDATA2_SHIFT (0U) /*! CMDDATA2 - Command data word 2 */ #define FMUTEST_FCCOB6_CMDDATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB6_CMDDATA2_SHIFT)) & FMUTEST_FCCOB6_CMDDATA2_MASK) /*! @} */ /*! @name FCCOB7 - Flash Command Control 7 Register */ /*! @{ */ #define FMUTEST_FCCOB7_CMDDATA3_MASK (0xFFFFFFFFU) #define FMUTEST_FCCOB7_CMDDATA3_SHIFT (0U) /*! CMDDATA3 - Command data word 3 */ #define FMUTEST_FCCOB7_CMDDATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB7_CMDDATA3_SHIFT)) & FMUTEST_FCCOB7_CMDDATA3_MASK) /*! @} */ /*! @name RESET_STATUS - FMU Initialization Tracking Register */ /*! @{ */ #define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK (0x1U) #define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT (0U) /*! ARY_TRIM_DONE - Array Trim Complete * 0b0..Recall register load operation has not been completed * 0b1..Recall register load operation has completed */ #define FMUTEST_RESET_STATUS_ARY_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK) #define FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK (0x2U) #define FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT (1U) /*! FMU_PARM_EN - Status of the C0DE_C0DEh check to enable loading of the FMU parameters * 0b0..C0DE_C0DEh check not attempted * 0b1..C0DE_C0DEh check completed */ #define FMUTEST_RESET_STATUS_FMU_PARM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK) #define FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK (0x4U) #define FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT (2U) /*! FMU_PARM_DONE - FMU Register Load Complete * 0b0..FMU registers have not been loaded * 0b1..FMU registers have been loaded */ #define FMUTEST_RESET_STATUS_FMU_PARM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK) #define FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK (0x8U) #define FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT (3U) /*! SOC_TRIM_EN - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings * 0b0..C0DE_C0DEh check not attempted * 0b1..C0DE_C0DEh check completed */ #define FMUTEST_RESET_STATUS_SOC_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK) #define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK (0x10U) #define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT (4U) /*! SOC_TRIM_ECC - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings * 0b0..C0DE_C0DEh check failed * 0b1..C0DE_C0DEh check passed */ #define FMUTEST_RESET_STATUS_SOC_TRIM_ECC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK) #define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK (0x20U) #define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT (5U) /*! SOC_TRIM_DONE - SoC Trim Complete * 0b0..SoC Trim registers have not been updated * 0b1..All SoC Trim registers have been updated */ #define FMUTEST_RESET_STATUS_SOC_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK) #define FMUTEST_RESET_STATUS_RPR_DONE_MASK (0x40U) #define FMUTEST_RESET_STATUS_RPR_DONE_SHIFT (6U) /*! RPR_DONE - Array Repair Complete * 0b0..Repair registers have not been loaded * 0b1..Repair registers have been loaded */ #define FMUTEST_RESET_STATUS_RPR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RPR_DONE_SHIFT)) & FMUTEST_RESET_STATUS_RPR_DONE_MASK) #define FMUTEST_RESET_STATUS_INIT_DONE_MASK (0x80U) #define FMUTEST_RESET_STATUS_INIT_DONE_SHIFT (7U) /*! INIT_DONE - Initialization Done * 0b0..All initialization steps did not complete * 0b1..All initialization steps completed */ #define FMUTEST_RESET_STATUS_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_INIT_DONE_SHIFT)) & FMUTEST_RESET_STATUS_INIT_DONE_MASK) #define FMUTEST_RESET_STATUS_RST_SF_ERR_MASK (0x100U) #define FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT (8U) /*! RST_SF_ERR - ECC Single Fault during Reset Recovery * 0b0..No single-bit faults detected during initialization * 0b1..At least one single ECC fault was detected during initialization */ #define FMUTEST_RESET_STATUS_RST_SF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_SF_ERR_MASK) #define FMUTEST_RESET_STATUS_RST_DF_ERR_MASK (0x200U) #define FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT (9U) /*! RST_DF_ERR - ECC Double Fault during Reset Recovery * 0b0..No double-bit faults detected during initialization * 0b1..Double-bit ECC fault was detected during initialization */ #define FMUTEST_RESET_STATUS_RST_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_DF_ERR_MASK) #define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK (0x3FC00U) #define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT (10U) /*! SOC_TRIM_DF_ERR - ECC Double Fault during load of SoC Trim phrases */ #define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK) #define FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK (0x40000U) #define FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT (18U) /*! RST_PATCH_LD - Reset Patch Required * 0b0..No patch required to be loaded during reset * 0b1..Patch loaded during reset */ #define FMUTEST_RESET_STATUS_RST_PATCH_LD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT)) & FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK) #define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK (0x80000U) #define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT (19U) /*! RECALL_DATA_MISMATCH - Recall Data Mismatch * 0b0..Data read towards end of reset matched data read for Recall * 0b1..Data read towards end of reset did not match data read for recall */ #define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT)) & FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK) /*! @} */ /*! @name MCTL - FMU Control Register */ /*! @{ */ #define FMUTEST_MCTL_COREHLD_MASK (0x1U) #define FMUTEST_MCTL_COREHLD_SHIFT (0U) /*! COREHLD - Core Hold * 0b0..CPU access is allowed * 0b1..CPU access must be blocked */ #define FMUTEST_MCTL_COREHLD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_COREHLD_SHIFT)) & FMUTEST_MCTL_COREHLD_MASK) #define FMUTEST_MCTL_LSACT_EN_MASK (0x4U) #define FMUTEST_MCTL_LSACT_EN_SHIFT (2U) /*! LSACT_EN - LSACTIVE Feature Enable * 0b0..LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface. * 0b1..LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM. */ #define FMUTEST_MCTL_LSACT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACT_EN_SHIFT)) & FMUTEST_MCTL_LSACT_EN_MASK) #define FMUTEST_MCTL_LSACTWREN_MASK (0x8U) #define FMUTEST_MCTL_LSACTWREN_SHIFT (3U) /*! LSACTWREN - LSACTIVE Write Enable * 0b0..Unrestricted write access allowed * 0b1..Write access while CMP set must match CMDDID and CMDPRT */ #define FMUTEST_MCTL_LSACTWREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACTWREN_SHIFT)) & FMUTEST_MCTL_LSACTWREN_MASK) #define FMUTEST_MCTL_MASTER_REPAIR_EN_MASK (0x10U) #define FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT (4U) /*! MASTER_REPAIR_EN - Master Repair Enable * 0b0..Repair disabled * 0b1..Repair enable determined by bit 0 of each REPAIR register */ #define FMUTEST_MCTL_MASTER_REPAIR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT)) & FMUTEST_MCTL_MASTER_REPAIR_EN_MASK) #define FMUTEST_MCTL_RFCMDEN_MASK (0x20U) #define FMUTEST_MCTL_RFCMDEN_SHIFT (5U) /*! RFCMDEN - RF Active Command Enable Control * 0b0..Flash commands blocked (CCIF not writable) * 0b1..Flash commands allowed */ #define FMUTEST_MCTL_RFCMDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_RFCMDEN_SHIFT)) & FMUTEST_MCTL_RFCMDEN_MASK) #define FMUTEST_MCTL_CWSABTEN_MASK (0x40U) #define FMUTEST_MCTL_CWSABTEN_SHIFT (6U) /*! CWSABTEN - Command Write Sequence Abort Enable * 0b0..CWS abort feature is disabled * 0b1..CWS abort feature is enabled */ #define FMUTEST_MCTL_CWSABTEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_CWSABTEN_SHIFT)) & FMUTEST_MCTL_CWSABTEN_MASK) #define FMUTEST_MCTL_MRGRDDIS_MASK (0x80U) #define FMUTEST_MCTL_MRGRDDIS_SHIFT (7U) /*! MRGRDDIS - Margin Read Disable * 0b0..Margin Read Settings are enabled * 0b1..Margin Read Settings are disabled */ #define FMUTEST_MCTL_MRGRDDIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRDDIS_SHIFT)) & FMUTEST_MCTL_MRGRDDIS_MASK) #define FMUTEST_MCTL_MRGRD0_MASK (0xF00U) #define FMUTEST_MCTL_MRGRD0_SHIFT (8U) /*! MRGRD0 - Margin Read Setting for Program */ #define FMUTEST_MCTL_MRGRD0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD0_SHIFT)) & FMUTEST_MCTL_MRGRD0_MASK) #define FMUTEST_MCTL_MRGRD1_MASK (0xF000U) #define FMUTEST_MCTL_MRGRD1_SHIFT (12U) /*! MRGRD1 - Margin Read Setting for Erase */ #define FMUTEST_MCTL_MRGRD1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD1_SHIFT)) & FMUTEST_MCTL_MRGRD1_MASK) #define FMUTEST_MCTL_ERSAACK_MASK (0x10000U) #define FMUTEST_MCTL_ERSAACK_SHIFT (16U) /*! ERSAACK - Mass Erase (Erase All) Acknowledge * 0b0..Mass Erase operation is not active (operation has completed or has not started) * 0b1..Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation) */ #define FMUTEST_MCTL_ERSAACK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_ERSAACK_SHIFT)) & FMUTEST_MCTL_ERSAACK_MASK) #define FMUTEST_MCTL_SCAN_OBS_MASK (0x80000U) #define FMUTEST_MCTL_SCAN_OBS_SHIFT (19U) /*! SCAN_OBS - Scan Observability Control * 0b0..Normal functional behavior * 0b1..Enables observation of signals that may otherwise be ATPG untestable */ #define FMUTEST_MCTL_SCAN_OBS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SCAN_OBS_SHIFT)) & FMUTEST_MCTL_SCAN_OBS_MASK) #define FMUTEST_MCTL_BIST_CTL_MASK (0x100000U) #define FMUTEST_MCTL_BIST_CTL_SHIFT (20U) /*! BIST_CTL - BIST IP Control * 0b0..BIST IP disabled * 0b1..BIST IP enabled */ #define FMUTEST_MCTL_BIST_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_CTL_SHIFT)) & FMUTEST_MCTL_BIST_CTL_MASK) #define FMUTEST_MCTL_SMWR_CTL_MASK (0x200000U) #define FMUTEST_MCTL_SMWR_CTL_SHIFT (21U) /*! SMWR_CTL - SMWR IP Control * 0b0..SMWR IP disabled * 0b1..SMWR IP enabled */ #define FMUTEST_MCTL_SMWR_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SMWR_CTL_SHIFT)) & FMUTEST_MCTL_SMWR_CTL_MASK) #define FMUTEST_MCTL_SALV_DIS_MASK (0x1000000U) #define FMUTEST_MCTL_SALV_DIS_SHIFT (24U) /*! SALV_DIS - Salvage Disable * 0b0..Salvage enabled (ECC used during erase verify) * 0b1..Salvage disabled (ECC not used during erase verify) */ #define FMUTEST_MCTL_SALV_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SALV_DIS_SHIFT)) & FMUTEST_MCTL_SALV_DIS_MASK) #define FMUTEST_MCTL_SOC_ECC_CTL_MASK (0x2000000U) #define FMUTEST_MCTL_SOC_ECC_CTL_SHIFT (25U) /*! SOC_ECC_CTL - SOC ECC Control * 0b0..ECC is enabled for SOC read access * 0b1..ECC is disabled for SOC read access */ #define FMUTEST_MCTL_SOC_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SOC_ECC_CTL_SHIFT)) & FMUTEST_MCTL_SOC_ECC_CTL_MASK) #define FMUTEST_MCTL_FMU_ECC_CTL_MASK (0x4000000U) #define FMUTEST_MCTL_FMU_ECC_CTL_SHIFT (26U) /*! FMU_ECC_CTL - FMU ECC Control * 0b0..ECC is enabled for FMU program operations * 0b1..ECC is disabled for FMU program operations */ #define FMUTEST_MCTL_FMU_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_FMU_ECC_CTL_SHIFT)) & FMUTEST_MCTL_FMU_ECC_CTL_MASK) #define FMUTEST_MCTL_BIST_PWR_DIS_MASK (0x20000000U) #define FMUTEST_MCTL_BIST_PWR_DIS_SHIFT (29U) /*! BIST_PWR_DIS - BIST Power Mode Disable * 0b0..BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands) * 0b1..BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values */ #define FMUTEST_MCTL_BIST_PWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_PWR_DIS_SHIFT)) & FMUTEST_MCTL_BIST_PWR_DIS_MASK) #define FMUTEST_MCTL_OSC_H_MASK (0x80000000U) #define FMUTEST_MCTL_OSC_H_SHIFT (31U) /*! OSC_H - Oscillator control * 0b0..Use APB clock * 0b1..Use a known fixed-frequency clock, e.g. 12 MHz */ #define FMUTEST_MCTL_OSC_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_OSC_H_SHIFT)) & FMUTEST_MCTL_OSC_H_MASK) /*! @} */ /*! @name BSEL_GEN - FMU Block Select Generation Register */ /*! @{ */ #define FMUTEST_BSEL_GEN_SBSEL_GEN_MASK (0x3U) #define FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT (0U) /*! SBSEL_GEN - Generated SBSEL */ #define FMUTEST_BSEL_GEN_SBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_SBSEL_GEN_MASK) #define FMUTEST_BSEL_GEN_MBSEL_GEN_MASK (0x300U) #define FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT (8U) /*! MBSEL_GEN - Generated MBSEL */ #define FMUTEST_BSEL_GEN_MBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_MBSEL_GEN_MASK) /*! @} */ /*! @name PWR_OPT - Power Mode Options Register */ /*! @{ */ #define FMUTEST_PWR_OPT_PD_CDIV_MASK (0xFFU) #define FMUTEST_PWR_OPT_PD_CDIV_SHIFT (0U) /*! PD_CDIV - Power Down Clock Divider Setting */ #define FMUTEST_PWR_OPT_PD_CDIV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_CDIV_SHIFT)) & FMUTEST_PWR_OPT_PD_CDIV_MASK) #define FMUTEST_PWR_OPT_SLM_COUNT_MASK (0x3FF0000U) #define FMUTEST_PWR_OPT_SLM_COUNT_SHIFT (16U) /*! SLM_COUNT - Sleep Recovery Timer Count */ #define FMUTEST_PWR_OPT_SLM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_SLM_COUNT_SHIFT)) & FMUTEST_PWR_OPT_SLM_COUNT_MASK) #define FMUTEST_PWR_OPT_PD_TIMER_EN_MASK (0x80000000U) #define FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT (31U) /*! PD_TIMER_EN - Power Down BIST Timer Enable * 0b0..BIST timer is not triggered during Power Down recovery * 0b1..BIST timer is triggered during Power Down recovery (default behavior) */ #define FMUTEST_PWR_OPT_PD_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT)) & FMUTEST_PWR_OPT_PD_TIMER_EN_MASK) /*! @} */ /*! @name CMD_CHECK - FMU Command Check Register */ /*! @{ */ #define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK (0x1U) #define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT (0U) /*! ALIGNFAIL_PHR - Phrase Alignment Fail * 0b0..The address is phrase-aligned * 0b1..The address is not phrase-aligned */ #define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK) #define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK (0x2U) #define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT (1U) /*! ALIGNFAIL_PG - Page Alignment Fail * 0b0..The address is page-aligned * 0b1..The address is not page-aligned */ #define FMUTEST_CMD_CHECK_ALIGNFAIL_PG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK) #define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK (0x4U) #define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT (2U) /*! ALIGNFAIL_SCR - Sector Alignment Fail * 0b0..The address is sector-aligned * 0b1..The address is not sector-aligned */ #define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK) #define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK (0x8U) #define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT (3U) /*! ALIGNFAIL_BLK - Block Alignment Fail * 0b0..The address is block-aligned * 0b1..The address is not block-aligned */ #define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK) #define FMUTEST_CMD_CHECK_ADDR_FAIL_MASK (0x10U) #define FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT (4U) /*! ADDR_FAIL - Address Fail * 0b0..The address is within the flash or IFR address space * 0b1..The address is outside the flash or IFR address space */ #define FMUTEST_CMD_CHECK_ADDR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_ADDR_FAIL_MASK) #define FMUTEST_CMD_CHECK_IFR_CMD_MASK (0x20U) #define FMUTEST_CMD_CHECK_IFR_CMD_SHIFT (5U) /*! IFR_CMD - IFR Command * 0b0..The command operates on a main flash address * 0b1..The command operates on an IFR address */ #define FMUTEST_CMD_CHECK_IFR_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_IFR_CMD_SHIFT)) & FMUTEST_CMD_CHECK_IFR_CMD_MASK) #define FMUTEST_CMD_CHECK_ALL_CMD_MASK (0x40U) #define FMUTEST_CMD_CHECK_ALL_CMD_SHIFT (6U) /*! ALL_CMD - All Blocks Command * 0b0..The command operates on a single flash block * 0b1..The command operates on all flash blocks */ #define FMUTEST_CMD_CHECK_ALL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ALL_CMD_MASK) #define FMUTEST_CMD_CHECK_RANGE_FAIL_MASK (0x80U) #define FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT (7U) /*! RANGE_FAIL - Address Range Fail * 0b0..The address range is valid * 0b1..The address range is invalid */ #define FMUTEST_CMD_CHECK_RANGE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_RANGE_FAIL_MASK) #define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK (0x100U) #define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT (8U) /*! SCR_ALIGN_CHK - Sector Alignment Check * 0b0..No sector alignment check * 0b1..Sector alignment check */ #define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT)) & FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK) #define FMUTEST_CMD_CHECK_OPTION_FAIL_MASK (0x200U) #define FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT (9U) /*! OPTION_FAIL - Option Check Fail * 0b0..Option check passes for read command or command is not a read command * 0b1..Option check fails for read command */ #define FMUTEST_CMD_CHECK_OPTION_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_OPTION_FAIL_MASK) #define FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK (0x400U) #define FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT (10U) /*! ILLEGAL_CMD - Illegal Command * 0b0..Command is legal * 0b1..Command is illegal */ #define FMUTEST_CMD_CHECK_ILLEGAL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK) /*! @} */ /*! @name BSEL - FMU Block Select Register */ /*! @{ */ #define FMUTEST_BSEL_SBSEL_MASK (0x3U) #define FMUTEST_BSEL_SBSEL_SHIFT (0U) /*! SBSEL - Slave Block Select */ #define FMUTEST_BSEL_SBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_SBSEL_SHIFT)) & FMUTEST_BSEL_SBSEL_MASK) #define FMUTEST_BSEL_MBSEL_MASK (0x300U) #define FMUTEST_BSEL_MBSEL_SHIFT (8U) /*! MBSEL - Master Block Select */ #define FMUTEST_BSEL_MBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_MBSEL_SHIFT)) & FMUTEST_BSEL_MBSEL_MASK) /*! @} */ /*! @name MSIZE - FMU Memory Size Register */ /*! @{ */ #define FMUTEST_MSIZE_MAXADDR0_MASK (0xFFU) #define FMUTEST_MSIZE_MAXADDR0_SHIFT (0U) /*! MAXADDR0 - Size of Flash Block 0 */ #define FMUTEST_MSIZE_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR0_SHIFT)) & FMUTEST_MSIZE_MAXADDR0_MASK) #define FMUTEST_MSIZE_MAXADDR1_MASK (0xFF00U) #define FMUTEST_MSIZE_MAXADDR1_SHIFT (8U) /*! MAXADDR1 - Size of Flash Block 1 */ #define FMUTEST_MSIZE_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR1_SHIFT)) & FMUTEST_MSIZE_MAXADDR1_MASK) /*! @} */ /*! @name FLASH_RD_ADD - Flash Read Address Register */ /*! @{ */ #define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK (0xFFFFFFFFU) #define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT (0U) /*! FLASH_RD_ADD - Flash Read Address */ #define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT)) & FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK) /*! @} */ /*! @name FLASH_STOP_ADD - Flash Stop Address Register */ /*! @{ */ #define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK (0xFFFFFFFFU) #define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT (0U) /*! FLASH_STOP_ADD - Flash Stop Address */ #define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT)) & FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK) /*! @} */ /*! @name FLASH_RD_CTRL - Flash Read Control Register */ /*! @{ */ #define FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK (0x1U) #define FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT (0U) /*! FLASH_RD - Flash Read Enable * 0b0..Manual flash read not enabled.(default) * 0b1..Manual flash read enabled */ #define FMUTEST_FLASH_RD_CTRL_FLASH_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK) #define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK (0x2U) #define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT (1U) /*! WIDE_LOAD - Wide Load Enable * 0b0..Wide load mode disabled (default) * 0b1..Wide load mode enabled */ #define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK) #define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK (0x4U) #define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT (2U) /*! SINGLE_RD - Single Flash Read * 0b0..Normal UINT operation * 0b1..UINT configured for single cycle reads */ #define FMUTEST_FLASH_RD_CTRL_SINGLE_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK) /*! @} */ /*! @name MM_ADDR - Memory Map Address Register */ /*! @{ */ #define FMUTEST_MM_ADDR_MM_ADDR_MASK (0xFFFFFFFFU) #define FMUTEST_MM_ADDR_MM_ADDR_SHIFT (0U) /*! MM_ADDR - Memory Map Address */ #define FMUTEST_MM_ADDR_MM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_ADDR_MM_ADDR_SHIFT)) & FMUTEST_MM_ADDR_MM_ADDR_MASK) /*! @} */ /*! @name MM_WDATA - Memory Map Write Data Register */ /*! @{ */ #define FMUTEST_MM_WDATA_MM_WDATA_MASK (0xFFFFFFFFU) #define FMUTEST_MM_WDATA_MM_WDATA_SHIFT (0U) /*! MM_WDATA - Memory Map Write Data */ #define FMUTEST_MM_WDATA_MM_WDATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_WDATA_MM_WDATA_SHIFT)) & FMUTEST_MM_WDATA_MM_WDATA_MASK) /*! @} */ /*! @name MM_CTL - Memory Map Control Register */ /*! @{ */ #define FMUTEST_MM_CTL_MM_SEL_MASK (0x1U) #define FMUTEST_MM_CTL_MM_SEL_SHIFT (0U) /*! MM_SEL - Register Access Enable */ #define FMUTEST_MM_CTL_MM_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_SEL_SHIFT)) & FMUTEST_MM_CTL_MM_SEL_MASK) #define FMUTEST_MM_CTL_MM_RD_MASK (0x2U) #define FMUTEST_MM_CTL_MM_RD_SHIFT (1U) /*! MM_RD - Register R/W Control * 0b0..Write to register * 0b1..Read register */ #define FMUTEST_MM_CTL_MM_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_RD_SHIFT)) & FMUTEST_MM_CTL_MM_RD_MASK) #define FMUTEST_MM_CTL_BIST_ON_MASK (0x4U) #define FMUTEST_MM_CTL_BIST_ON_SHIFT (2U) /*! BIST_ON - BIST on * 0b0..BIST enable not forced by user interface * 0b1..BIST enable control by user interface */ #define FMUTEST_MM_CTL_BIST_ON(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_BIST_ON_SHIFT)) & FMUTEST_MM_CTL_BIST_ON_MASK) #define FMUTEST_MM_CTL_FORCE_SW_CLK_MASK (0x8U) #define FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT (3U) /*! FORCE_SW_CLK - Force Switch Clock * 0b0..Switch clock not forced on (gated normally) * 0b1..Switch clock forced on */ #define FMUTEST_MM_CTL_FORCE_SW_CLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT)) & FMUTEST_MM_CTL_FORCE_SW_CLK_MASK) /*! @} */ /*! @name UINT_CTL - User Interface Control Register */ /*! @{ */ #define FMUTEST_UINT_CTL_SET_FAIL_MASK (0x1U) #define FMUTEST_UINT_CTL_SET_FAIL_SHIFT (0U) /*! SET_FAIL - Set Fail On Exit * 0b0..FAIL flag should not be set on command exit (no failure detected) * 0b1..FAIL flag should be set on command exit */ #define FMUTEST_UINT_CTL_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_SET_FAIL_SHIFT)) & FMUTEST_UINT_CTL_SET_FAIL_MASK) #define FMUTEST_UINT_CTL_DBERR_MASK (0x2U) #define FMUTEST_UINT_CTL_DBERR_SHIFT (1U) /*! DBERR - Double-Bit ECC Fault Detect * 0b0..No double-bit fault detected during UINT-driven read sequence * 0b1..Double-bit fault detected during UINT-driven read sequence */ #define FMUTEST_UINT_CTL_DBERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_DBERR_SHIFT)) & FMUTEST_UINT_CTL_DBERR_MASK) /*! @} */ /*! @name RD_DATA0 - Read Data 0 Register */ /*! @{ */ #define FMUTEST_RD_DATA0_RD_DATA0_MASK (0xFFFFFFFFU) #define FMUTEST_RD_DATA0_RD_DATA0_SHIFT (0U) /*! RD_DATA0 - Read Data 0 */ #define FMUTEST_RD_DATA0_RD_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA0_RD_DATA0_SHIFT)) & FMUTEST_RD_DATA0_RD_DATA0_MASK) /*! @} */ /*! @name RD_DATA1 - Read Data 1 Register */ /*! @{ */ #define FMUTEST_RD_DATA1_RD_DATA1_MASK (0xFFFFFFFFU) #define FMUTEST_RD_DATA1_RD_DATA1_SHIFT (0U) /*! RD_DATA1 - Read Data 1 */ #define FMUTEST_RD_DATA1_RD_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA1_RD_DATA1_SHIFT)) & FMUTEST_RD_DATA1_RD_DATA1_MASK) /*! @} */ /*! @name RD_DATA2 - Read Data 2 Register */ /*! @{ */ #define FMUTEST_RD_DATA2_RD_DATA2_MASK (0xFFFFFFFFU) #define FMUTEST_RD_DATA2_RD_DATA2_SHIFT (0U) /*! RD_DATA2 - Read Data 2 */ #define FMUTEST_RD_DATA2_RD_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA2_RD_DATA2_SHIFT)) & FMUTEST_RD_DATA2_RD_DATA2_MASK) /*! @} */ /*! @name RD_DATA3 - Read Data 3 Register */ /*! @{ */ #define FMUTEST_RD_DATA3_RD_DATA3_MASK (0xFFFFFFFFU) #define FMUTEST_RD_DATA3_RD_DATA3_SHIFT (0U) /*! RD_DATA3 - Read Data 3 */ #define FMUTEST_RD_DATA3_RD_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA3_RD_DATA3_SHIFT)) & FMUTEST_RD_DATA3_RD_DATA3_MASK) /*! @} */ /*! @name PARITY - Parity Register */ /*! @{ */ #define FMUTEST_PARITY_PARITY_MASK (0x1FFU) #define FMUTEST_PARITY_PARITY_SHIFT (0U) /*! PARITY - Read data [136:128] */ #define FMUTEST_PARITY_PARITY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PARITY_PARITY_SHIFT)) & FMUTEST_PARITY_PARITY_MASK) /*! @} */ /*! @name RD_PATH_CTRL_STATUS - Read Path Control and Status Register */ /*! @{ */ #define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK (0xFFU) #define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT (0U) /*! RD_CAPT - Read Capture Clock Periods */ #define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK (0xFF00U) #define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT (8U) /*! SE_SIZE - SE Clock Periods */ #define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK (0x10000U) #define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT (16U) /*! ECC_ENABLEB - ECC Decoder Control * 0b0..ECC decoder enabled (default) * 0b1..ECC decoder disabled */ #define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK (0x20000U) #define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT (17U) /*! MISR_EN - MISR Enable * 0b0..MISR option disabled (default) * 0b1..MISR option enabled */ #define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK (0x40000U) #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT (18U) /*! CPY_PAR_EN - Copy Parity Enable * 0b0..Copy parity disabled * 0b1..Copy parity enabled */ #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK (0x80000U) #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT (19U) /*! BIST_MUX_TO_SMW - BIST Mux to SMW * 0b0..BIST drives fields * 0b1..SMW registers drive fields */ #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK (0xF00000U) #define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT (20U) /*! AD_SET - Multi-Cycle Address Setup Time */ #define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK (0x1000000U) #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT (24U) /*! WR_PATH_EN - Write Path Enable * 0b0..Writes to BIST setting registers driven by MM_WDATA * 0b1..Writes to BIST setting registers driven by SMW_DIN */ #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK (0x2000000U) #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT (25U) /*! WR_PATH_ECC_EN - Write Path ECC Enable * 0b0..ECC encoding disabled * 0b1..ECC encoding enabled */ #define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK (0x4000000U) #define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT (26U) /*! DBERR_REG - Double-Bit Error * 0b0..Double-bit fault not detected * 0b1..Double-bit fault detected on previous UINT flash read */ #define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK (0x8000000U) #define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT (27U) /*! SBERR_REG - Single-Bit Error * 0b0..Single-bit fault not detected * 0b1..Single-bit fault detected on previous UINT flash read */ #define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK (0x10000000U) #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT (28U) /*! CPY_PHRASE_EN - Copy Phrase Enable * 0b0..Copy Flash read data disabled * 0b1..Copy Flash read data enabled */ #define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK (0x20000000U) #define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT (29U) /*! SMW_ARRAY1_SMW0_SEL - SMW_ARRAY1_SMW0_SEL * 0b0..Select block 0 * 0b1..Select block 1 */ #define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK (0x40000000U) #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT (30U) /*! BIST_ECC_EN - BIST ECC Enable * 0b0..ECC correction disabled * 0b1..ECC correction enabled */ #define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK) #define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK (0x80000000U) #define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT (31U) /*! LAST_READ - Last Read * 0b0..Latest read not last in multi-address operation * 0b1..Latest read last in multi-address operation */ #define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK) /*! @} */ /*! @name SMW_DIN0 - SMW DIN 0 Register */ /*! @{ */ #define FMUTEST_SMW_DIN0_SMW_DIN0_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT (0U) /*! SMW_DIN0 - SMW DIN 0 */ #define FMUTEST_SMW_DIN0_SMW_DIN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT)) & FMUTEST_SMW_DIN0_SMW_DIN0_MASK) /*! @} */ /*! @name SMW_DIN1 - SMW DIN 1 Register */ /*! @{ */ #define FMUTEST_SMW_DIN1_SMW_DIN1_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT (0U) /*! SMW_DIN1 - SMW DIN 1 */ #define FMUTEST_SMW_DIN1_SMW_DIN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT)) & FMUTEST_SMW_DIN1_SMW_DIN1_MASK) /*! @} */ /*! @name SMW_DIN2 - SMW DIN 2 Register */ /*! @{ */ #define FMUTEST_SMW_DIN2_SMW_DIN2_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT (0U) /*! SMW_DIN2 - SMW DIN 2 */ #define FMUTEST_SMW_DIN2_SMW_DIN2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT)) & FMUTEST_SMW_DIN2_SMW_DIN2_MASK) /*! @} */ /*! @name SMW_DIN3 - SMW DIN 3 Register */ /*! @{ */ #define FMUTEST_SMW_DIN3_SMW_DIN3_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT (0U) /*! SMW_DIN3 - SMW DIN 3 */ #define FMUTEST_SMW_DIN3_SMW_DIN3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT)) & FMUTEST_SMW_DIN3_SMW_DIN3_MASK) /*! @} */ /*! @name SMW_ADDR - SMW Address Register */ /*! @{ */ #define FMUTEST_SMW_ADDR_SMW_ADDR_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT (0U) /*! SMW_ADDR - SMW Address */ #define FMUTEST_SMW_ADDR_SMW_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT)) & FMUTEST_SMW_ADDR_SMW_ADDR_MASK) /*! @} */ /*! @name SMW_CMD_WAIT - SMW Command and Wait Register */ /*! @{ */ #define FMUTEST_SMW_CMD_WAIT_CMD_MASK (0x7U) #define FMUTEST_SMW_CMD_WAIT_CMD_SHIFT (0U) /*! CMD - SMW Command * 0b000..IDLE * 0b001..ABORT * 0b010..SME2 to one-shot mass erase * 0b011..SME3 to sector erase on selected array * 0b100..SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit * 0b101..Reserved for SME4 (multi-sector erase) * 0b110..SMP2 to program phrase or page on selected array to repair cells of weak program after power loss * 0b111..Reserved */ #define FMUTEST_SMW_CMD_WAIT_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_CMD_SHIFT)) & FMUTEST_SMW_CMD_WAIT_CMD_MASK) #define FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK (0x8U) #define FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT (3U) /*! WAIT_EN - SMW Wait Enable * 0b0..Wait feature disabled * 0b1..Wait feature enabled */ #define FMUTEST_SMW_CMD_WAIT_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK) #define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK (0x10U) #define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT (4U) /*! WAIT_AUTO_SET - SMW Wait Auto Set */ #define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK) /*! @} */ /*! @name SMW_STATUS - SMW Status Register */ /*! @{ */ #define FMUTEST_SMW_STATUS_SMW_ERR_MASK (0x1U) #define FMUTEST_SMW_STATUS_SMW_ERR_SHIFT (0U) /*! SMW_ERR - SMW Error * 0b0..Error not detected * 0b1..Error detected */ #define FMUTEST_SMW_STATUS_SMW_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_ERR_SHIFT)) & FMUTEST_SMW_STATUS_SMW_ERR_MASK) #define FMUTEST_SMW_STATUS_SMW_BUSY_MASK (0x2U) #define FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT (1U) /*! SMW_BUSY - SMW Busy * 0b0..SMW command not active * 0b1..SMW command is active */ #define FMUTEST_SMW_STATUS_SMW_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_SMW_BUSY_MASK) #define FMUTEST_SMW_STATUS_BIST_BUSY_MASK (0x4U) #define FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT (2U) /*! BIST_BUSY - BIST Busy * 0b0..BIST Command not active * 0b1..BIST Command is active */ #define FMUTEST_SMW_STATUS_BIST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_BIST_BUSY_MASK) /*! @} */ /*! @name SOCTRIM0_0 - SoC Trim Phrase 0 Word 0 Register */ /*! @{ */ #define FMUTEST_SOCTRIM0_0_TRIM0_0_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT (0U) /*! TRIM0_0 - TRIM0_0 */ #define FMUTEST_SOCTRIM0_0_TRIM0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT)) & FMUTEST_SOCTRIM0_0_TRIM0_0_MASK) /*! @} */ /*! @name SOCTRIM0_1 - SoC Trim Phrase 0 Word 1 Register */ /*! @{ */ #define FMUTEST_SOCTRIM0_1_TRIM0_1_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT (0U) /*! TRIM0_1 - TRIM0_1 */ #define FMUTEST_SOCTRIM0_1_TRIM0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT)) & FMUTEST_SOCTRIM0_1_TRIM0_1_MASK) /*! @} */ /*! @name SOCTRIM0_2 - SoC Trim Phrase 0 Word 2 Register */ /*! @{ */ #define FMUTEST_SOCTRIM0_2_TRIM0_2_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT (0U) /*! TRIM0_2 - TRIM0_2 */ #define FMUTEST_SOCTRIM0_2_TRIM0_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT)) & FMUTEST_SOCTRIM0_2_TRIM0_2_MASK) /*! @} */ /*! @name SOCTRIM0_3 - SoC Trim Phrase 0 Word 3 Register */ /*! @{ */ #define FMUTEST_SOCTRIM0_3_TRIM0_3_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT (0U) /*! TRIM0_3 - TRIM0_3 */ #define FMUTEST_SOCTRIM0_3_TRIM0_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT)) & FMUTEST_SOCTRIM0_3_TRIM0_3_MASK) /*! @} */ /*! @name SOCTRIM1_0 - SoC Trim Phrase 1 Word 0 Register */ /*! @{ */ #define FMUTEST_SOCTRIM1_0_TRIM1_0_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT (0U) /*! TRIM1_0 - TRIM1_0 */ #define FMUTEST_SOCTRIM1_0_TRIM1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT)) & FMUTEST_SOCTRIM1_0_TRIM1_0_MASK) /*! @} */ /*! @name SOCTRIM1_1 - SoC Trim Phrase 1 Word 1 Register */ /*! @{ */ #define FMUTEST_SOCTRIM1_1_TRIM1_1_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT (0U) /*! TRIM1_1 - TRIM1_1 */ #define FMUTEST_SOCTRIM1_1_TRIM1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT)) & FMUTEST_SOCTRIM1_1_TRIM1_1_MASK) /*! @} */ /*! @name SOCTRIM1_2 - SoC Trim Phrase 1 Word 2 Register */ /*! @{ */ #define FMUTEST_SOCTRIM1_2_TRIM1_2_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT (0U) /*! TRIM1_2 - TRIM1_2 */ #define FMUTEST_SOCTRIM1_2_TRIM1_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT)) & FMUTEST_SOCTRIM1_2_TRIM1_2_MASK) /*! @} */ /*! @name SOCTRIM1_3 - SoC Trim Phrase 1 Word 3 Register */ /*! @{ */ #define FMUTEST_SOCTRIM1_3_TRIM1_3_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT (0U) /*! TRIM1_3 - TRIM1_3 */ #define FMUTEST_SOCTRIM1_3_TRIM1_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT)) & FMUTEST_SOCTRIM1_3_TRIM1_3_MASK) /*! @} */ /*! @name SOCTRIM2_0 - SoC Trim Phrase 2 Word 0 Register */ /*! @{ */ #define FMUTEST_SOCTRIM2_0_TRIM2_0_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT (0U) /*! TRIM2_0 - TRIM2_0 */ #define FMUTEST_SOCTRIM2_0_TRIM2_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT)) & FMUTEST_SOCTRIM2_0_TRIM2_0_MASK) /*! @} */ /*! @name SOCTRIM2_1 - SoC Trim Phrase 2 Word 1 Register */ /*! @{ */ #define FMUTEST_SOCTRIM2_1_TRIM2_1_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT (0U) /*! TRIM2_1 - TRIM2_1 */ #define FMUTEST_SOCTRIM2_1_TRIM2_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT)) & FMUTEST_SOCTRIM2_1_TRIM2_1_MASK) /*! @} */ /*! @name SOCTRIM2_2 - SoC Trim Phrase 2 Word 2 Register */ /*! @{ */ #define FMUTEST_SOCTRIM2_2_TRIM2_2_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT (0U) /*! TRIM2_2 - TRIM2_2 */ #define FMUTEST_SOCTRIM2_2_TRIM2_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT)) & FMUTEST_SOCTRIM2_2_TRIM2_2_MASK) /*! @} */ /*! @name SOCTRIM2_3 - SoC Trim Phrase 2 Word 3 Register */ /*! @{ */ #define FMUTEST_SOCTRIM2_3_TRIM2_3_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT (0U) /*! TRIM2_3 - TRIM2_3 */ #define FMUTEST_SOCTRIM2_3_TRIM2_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT)) & FMUTEST_SOCTRIM2_3_TRIM2_3_MASK) /*! @} */ /*! @name SOCTRIM3_0 - SoC Trim Phrase 3 Word 0 Register */ /*! @{ */ #define FMUTEST_SOCTRIM3_0_TRIM3_0_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT (0U) /*! TRIM3_0 - TRIM3_0 */ #define FMUTEST_SOCTRIM3_0_TRIM3_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT)) & FMUTEST_SOCTRIM3_0_TRIM3_0_MASK) /*! @} */ /*! @name SOCTRIM3_1 - SoC Trim Phrase 3 Word 1 Register */ /*! @{ */ #define FMUTEST_SOCTRIM3_1_TRIM3_1_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT (0U) /*! TRIM3_1 - TRIM3_1 */ #define FMUTEST_SOCTRIM3_1_TRIM3_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT)) & FMUTEST_SOCTRIM3_1_TRIM3_1_MASK) /*! @} */ /*! @name SOCTRIM3_2 - SoC Trim Phrase 3 Word 2 Register */ /*! @{ */ #define FMUTEST_SOCTRIM3_2_TRIM3_2_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT (0U) /*! TRIM3_2 - TRIM3_2 */ #define FMUTEST_SOCTRIM3_2_TRIM3_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT)) & FMUTEST_SOCTRIM3_2_TRIM3_2_MASK) /*! @} */ /*! @name SOCTRIM3_3 - SoC Trim Phrase 3 Word 3 Register */ /*! @{ */ #define FMUTEST_SOCTRIM3_3_TRIM3_3_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT (0U) /*! TRIM3_3 - TRIM3_3 */ #define FMUTEST_SOCTRIM3_3_TRIM3_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT)) & FMUTEST_SOCTRIM3_3_TRIM3_3_MASK) /*! @} */ /*! @name SOCTRIM4_0 - SoC Trim Phrase 4 Word 0 Register */ /*! @{ */ #define FMUTEST_SOCTRIM4_0_TRIM4_0_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT (0U) /*! TRIM4_0 - TRIM4_0 */ #define FMUTEST_SOCTRIM4_0_TRIM4_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT)) & FMUTEST_SOCTRIM4_0_TRIM4_0_MASK) /*! @} */ /*! @name SOCTRIM4_1 - SoC Trim Phrase 4 Word 1 Register */ /*! @{ */ #define FMUTEST_SOCTRIM4_1_TRIM4_1_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT (0U) /*! TRIM4_1 - TRIM4_1 */ #define FMUTEST_SOCTRIM4_1_TRIM4_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT)) & FMUTEST_SOCTRIM4_1_TRIM4_1_MASK) /*! @} */ /*! @name SOCTRIM4_2 - SoC Trim Phrase 4 Word 2 Register */ /*! @{ */ #define FMUTEST_SOCTRIM4_2_TRIM4_2_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT (0U) /*! TRIM4_2 - TRIM4_2 */ #define FMUTEST_SOCTRIM4_2_TRIM4_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT)) & FMUTEST_SOCTRIM4_2_TRIM4_2_MASK) /*! @} */ /*! @name SOCTRIM4_3 - SoC Trim Phrase 4 Word 3 Register */ /*! @{ */ #define FMUTEST_SOCTRIM4_3_TRIM4_3_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT (0U) /*! TRIM4_3 - TRIM4_3 */ #define FMUTEST_SOCTRIM4_3_TRIM4_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT)) & FMUTEST_SOCTRIM4_3_TRIM4_3_MASK) /*! @} */ /*! @name SOCTRIM5_0 - SoC Trim Phrase 5 Word 0 Register */ /*! @{ */ #define FMUTEST_SOCTRIM5_0_TRIM5_0_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT (0U) /*! TRIM5_0 - TRIM5_0 */ #define FMUTEST_SOCTRIM5_0_TRIM5_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT)) & FMUTEST_SOCTRIM5_0_TRIM5_0_MASK) /*! @} */ /*! @name SOCTRIM5_1 - SoC Trim Phrase 5 Word 1 Register */ /*! @{ */ #define FMUTEST_SOCTRIM5_1_TRIM5_1_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT (0U) /*! TRIM5_1 - TRIM5_1 */ #define FMUTEST_SOCTRIM5_1_TRIM5_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT)) & FMUTEST_SOCTRIM5_1_TRIM5_1_MASK) /*! @} */ /*! @name SOCTRIM5_2 - SoC Trim Phrase 5 Word 2 Register */ /*! @{ */ #define FMUTEST_SOCTRIM5_2_TRIM5_2_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT (0U) /*! TRIM5_2 - TRIM5_2 */ #define FMUTEST_SOCTRIM5_2_TRIM5_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT)) & FMUTEST_SOCTRIM5_2_TRIM5_2_MASK) /*! @} */ /*! @name SOCTRIM5_3 - SoC Trim Phrase 5 Word 3 Register */ /*! @{ */ #define FMUTEST_SOCTRIM5_3_TRIM5_3_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT (0U) /*! TRIM5_3 - TRIM5_3 */ #define FMUTEST_SOCTRIM5_3_TRIM5_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT)) & FMUTEST_SOCTRIM5_3_TRIM5_3_MASK) /*! @} */ /*! @name SOCTRIM6_0 - SoC Trim Phrase 6 Word 0 Register */ /*! @{ */ #define FMUTEST_SOCTRIM6_0_TRIM6_0_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT (0U) /*! TRIM6_0 - TRIM6_0 */ #define FMUTEST_SOCTRIM6_0_TRIM6_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT)) & FMUTEST_SOCTRIM6_0_TRIM6_0_MASK) /*! @} */ /*! @name SOCTRIM6_1 - SoC Trim Phrase 6 Word 1 Register */ /*! @{ */ #define FMUTEST_SOCTRIM6_1_TRIM6_1_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT (0U) /*! TRIM6_1 - TRIM6_1 */ #define FMUTEST_SOCTRIM6_1_TRIM6_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT)) & FMUTEST_SOCTRIM6_1_TRIM6_1_MASK) /*! @} */ /*! @name SOCTRIM6_2 - SoC Trim Phrase 6 Word 2 Register */ /*! @{ */ #define FMUTEST_SOCTRIM6_2_TRIM6_2_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT (0U) /*! TRIM6_2 - TRIM6_2 */ #define FMUTEST_SOCTRIM6_2_TRIM6_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT)) & FMUTEST_SOCTRIM6_2_TRIM6_2_MASK) /*! @} */ /*! @name SOCTRIM6_3 - SoC Trim Phrase 6 Word 3 Register */ /*! @{ */ #define FMUTEST_SOCTRIM6_3_TRIM6_3_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT (0U) /*! TRIM6_3 - TRIM6_3 */ #define FMUTEST_SOCTRIM6_3_TRIM6_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT)) & FMUTEST_SOCTRIM6_3_TRIM6_3_MASK) /*! @} */ /*! @name SOCTRIM7_0 - SoC Trim Phrase 7 Word 0 Register */ /*! @{ */ #define FMUTEST_SOCTRIM7_0_TRIM7_0_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT (0U) /*! TRIM7_0 - TRIM7_0 */ #define FMUTEST_SOCTRIM7_0_TRIM7_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT)) & FMUTEST_SOCTRIM7_0_TRIM7_0_MASK) /*! @} */ /*! @name SOCTRIM7_1 - SoC Trim Phrase 7 Word 1 Register */ /*! @{ */ #define FMUTEST_SOCTRIM7_1_TRIM7_1_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT (0U) /*! TRIM7_1 - TRIM7_1 */ #define FMUTEST_SOCTRIM7_1_TRIM7_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT)) & FMUTEST_SOCTRIM7_1_TRIM7_1_MASK) /*! @} */ /*! @name SOCTRIM7_2 - SoC Trim Phrase 7 Word 2 Register */ /*! @{ */ #define FMUTEST_SOCTRIM7_2_TRIM7_2_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT (0U) /*! TRIM7_2 - TRIM7_2 */ #define FMUTEST_SOCTRIM7_2_TRIM7_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT)) & FMUTEST_SOCTRIM7_2_TRIM7_2_MASK) /*! @} */ /*! @name SOCTRIM7_3 - SoC Trim Phrase 7 Word 3 Register */ /*! @{ */ #define FMUTEST_SOCTRIM7_3_TRIM7_3_MASK (0xFFFFFFFFU) #define FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT (0U) /*! TRIM7_3 - TRIM7_3 */ #define FMUTEST_SOCTRIM7_3_TRIM7_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT)) & FMUTEST_SOCTRIM7_3_TRIM7_3_MASK) /*! @} */ /*! @name R_IP_CONFIG - BIST Configuration Register */ /*! @{ */ #define FMUTEST_R_IP_CONFIG_IPSEL0_MASK (0x3U) #define FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT (0U) /*! IPSEL0 - Block 0 Select Control * 0b00..Unselect block 0 * 0b01..not used, reserved * 0b10..Enable block 0 test, repair off (default) * 0b11..Enable block 0 test, repair on */ #define FMUTEST_R_IP_CONFIG_IPSEL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL0_MASK) #define FMUTEST_R_IP_CONFIG_IPSEL1_MASK (0xCU) #define FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT (2U) /*! IPSEL1 - Block 1 Select Control * 0b00..Unselect block 1 * 0b01..not used, reserved * 0b10..Enable block 1 test, repair off (default) * 0b11..Enable block 1 test, repair on */ #define FMUTEST_R_IP_CONFIG_IPSEL1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL1_MASK) #define FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK (0xFF0U) #define FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT (4U) /*! BIST_CDIVL - Clock Divide Scalar for Long Pulse */ #define FMUTEST_R_IP_CONFIG_BIST_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK) #define FMUTEST_R_IP_CONFIG_CDIVS_MASK (0x7000U) #define FMUTEST_R_IP_CONFIG_CDIVS_SHIFT (12U) /*! CDIVS - Number of clock cycles to generate short pulse */ #define FMUTEST_R_IP_CONFIG_CDIVS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_CDIVS_SHIFT)) & FMUTEST_R_IP_CONFIG_CDIVS_MASK) #define FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK (0xF8000U) #define FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT (15U) /*! BIST_TVFY - Timer adjust for verify */ #define FMUTEST_R_IP_CONFIG_BIST_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK) #define FMUTEST_R_IP_CONFIG_TSTCTL_MASK (0x300000U) #define FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT (20U) /*! TSTCTL - BIST self-test control * 0b00..Default, disable both BIST self-test and MISR * 0b01..Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR. * 0b10..Enable MISR * 0b11..Enable both BIST self-test mode and MISR */ #define FMUTEST_R_IP_CONFIG_TSTCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_TSTCTL_MASK) #define FMUTEST_R_IP_CONFIG_DBGCTL_MASK (0x400000U) #define FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT (22U) /*! DBGCTL - Debug feature control * 0b0..Default * 0b1..Enable debug feature to collect failure address and data. */ #define FMUTEST_R_IP_CONFIG_DBGCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_DBGCTL_MASK) #define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK (0x800000U) #define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT (23U) /*! BIST_CLK_SEL - BIST Clock Select */ #define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK) #define FMUTEST_R_IP_CONFIG_SMWTST_MASK (0x3000000U) #define FMUTEST_R_IP_CONFIG_SMWTST_SHIFT (24U) /*! SMWTST - SMWR DOUT Function Control * 0b00..Default * 0b01..Enable SMWR self-test mode, DOUT from macro will be forced to all 0 * 0b10..Enable SMWR self-test mode, DOUT from macro will be forced to all 1 * 0b11..Reserved (unused) */ #define FMUTEST_R_IP_CONFIG_SMWTST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_SMWTST_SHIFT)) & FMUTEST_R_IP_CONFIG_SMWTST_MASK) #define FMUTEST_R_IP_CONFIG_ECCEN_MASK (0x4000000U) #define FMUTEST_R_IP_CONFIG_ECCEN_SHIFT (26U) /*! ECCEN - BIST ECC Control * 0b0..Default mode (no ECC encode or decode) * 0b1..Enable ECC encode/decode */ #define FMUTEST_R_IP_CONFIG_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_ECCEN_SHIFT)) & FMUTEST_R_IP_CONFIG_ECCEN_MASK) /*! @} */ /*! @name R_TESTCODE - BIST Test Code Register */ /*! @{ */ #define FMUTEST_R_TESTCODE_TESTCODE_MASK (0x3FU) #define FMUTEST_R_TESTCODE_TESTCODE_SHIFT (0U) /*! TESTCODE - Used to store test code information before running TMR-RST/TMRSET BIST command */ #define FMUTEST_R_TESTCODE_TESTCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TESTCODE_TESTCODE_SHIFT)) & FMUTEST_R_TESTCODE_TESTCODE_MASK) /*! @} */ /*! @name R_DFT_CTRL - BIST DFT Control Register */ /*! @{ */ #define FMUTEST_R_DFT_CTRL_DFT_XADR_MASK (0xFU) #define FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT (0U) /*! DFT_XADR - DFT XADR Pattern * 0b0000..XADR fixed, no change at all * 0b0001..XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of * row. For PROG operation, XADR increases by 1 after NVSTR falls. * 0b0010..XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern. * 0b0011..XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls. * 0b0100..XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls. * 0b0101..XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word * of a row. For PROG operation, XADR is increased by 2 when NVSTR falls. * 0b0110..XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls. * 0b0111..XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle. * 0b1000..XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0. * 0b1001..XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle. */ #define FMUTEST_R_DFT_CTRL_DFT_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_XADR_MASK) #define FMUTEST_R_DFT_CTRL_DFT_YADR_MASK (0xF0U) #define FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT (4U) /*! DFT_YADR - DFT YADR Pattern * 0b0000..YADR fixed, no change at all * 0b0001..YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern. * 0b0010..YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern. * 0b0011..YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG * operations, YADR increased by 1 after YE falls. * 0b0100..YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern. * 0b0101..YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls. * 0b0110..YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls. * 0b0111..YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row. * 0b1000..YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle. * 0b1001..YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0. */ #define FMUTEST_R_DFT_CTRL_DFT_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_YADR_MASK) #define FMUTEST_R_DFT_CTRL_DFT_DATA_MASK (0xF00U) #define FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT (8U) /*! DFT_DATA - DFT Data Pattern * 0b0000..CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle. * 0b0001..ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle. * 0b0010..Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern. * 0b0011..Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to * R_ADR_CTRL[GRPSEL] for modules with multiple groups. * 0b0100..Random data pattern which will be generated based on the initial seed set in R_DATA; for READ * operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected * groups. * 0b0101..DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If * more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched. * 0b0110..R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA * when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals * R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. * 0b0111..SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data * pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern. * 0b1000..REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 * and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared * against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only * one flash block can be selected. * 0b1001..REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1. */ #define FMUTEST_R_DFT_CTRL_DFT_DATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_MASK) #define FMUTEST_R_DFT_CTRL_CMP_MASK_MASK (0x3000U) #define FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT (12U) /*! CMP_MASK - Data Compare Mask * 0b00..Expected data is compared to DOUT * 0b01..Expected data (only 0s are considered) are compared to DOUT * 0b10..Expected data (only 1s are considered) are compared to DOUT */ #define FMUTEST_R_DFT_CTRL_CMP_MASK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT)) & FMUTEST_R_DFT_CTRL_CMP_MASK_MASK) #define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK (0x4000U) #define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT (14U) /*! DFT_DATA_SRC - DFT Data Source * 0b0..{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used * 0b1..{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used */ #define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK) /*! @} */ /*! @name R_ADR_CTRL - BIST Address Control Register */ /*! @{ */ #define FMUTEST_R_ADR_CTRL_GRPSEL_MASK (0xFU) #define FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT (0U) /*! GRPSEL - Data Group Select * 0b0000..Select no data * 0b0001..Select data slice [34:0] * 0b0010..Select data slice [69:35] * 0b0100..Select data slice [104:70] * 0b1000..Select data slice [136:105] * 0b1111..Select data [136:0] */ #define FMUTEST_R_ADR_CTRL_GRPSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT)) & FMUTEST_R_ADR_CTRL_GRPSEL_MASK) #define FMUTEST_R_ADR_CTRL_XADR_MASK (0xFFF0U) #define FMUTEST_R_ADR_CTRL_XADR_SHIFT (4U) /*! XADR - BIST XADR */ #define FMUTEST_R_ADR_CTRL_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_XADR_SHIFT)) & FMUTEST_R_ADR_CTRL_XADR_MASK) #define FMUTEST_R_ADR_CTRL_YADR_MASK (0x1F0000U) #define FMUTEST_R_ADR_CTRL_YADR_SHIFT (16U) /*! YADR - BIST YADR */ #define FMUTEST_R_ADR_CTRL_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_YADR_SHIFT)) & FMUTEST_R_ADR_CTRL_YADR_MASK) #define FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK (0xE00000U) #define FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT (21U) /*! PROG_ATTR - Program Attribute * 0b000..One YE pulse will program one data slice group * 0b001..One YE pulse will program two data slice groups * 0b010..One YE pulse will program three data slice groups (reserved) * 0b011..One YE pulse will program four data slice groups * 0b100..One YE pulse will program five data slice groups (reserved) * 0b101..One YE pulse will program six data slice groups (reserved) * 0b110..One YE pulse will program seven data slice groups (reserved) * 0b111..One YE pulse will program eight data slice groups (reserved) */ #define FMUTEST_R_ADR_CTRL_PROG_ATTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT)) & FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK) /*! @} */ /*! @name R_DATA_CTRL0 - BIST Data Control 0 Register */ /*! @{ */ #define FMUTEST_R_DATA_CTRL0_DATA0_MASK (0xFFFFFFFFU) #define FMUTEST_R_DATA_CTRL0_DATA0_SHIFT (0U) /*! DATA0 - BIST Data 0 Low */ #define FMUTEST_R_DATA_CTRL0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_DATA0_SHIFT)) & FMUTEST_R_DATA_CTRL0_DATA0_MASK) /*! @} */ /*! @name R_PIN_CTRL - BIST Pin Control Register */ /*! @{ */ #define FMUTEST_R_PIN_CTRL_MAS1_MASK (0x1U) #define FMUTEST_R_PIN_CTRL_MAS1_SHIFT (0U) /*! MAS1 - Mass Erase */ #define FMUTEST_R_PIN_CTRL_MAS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_MAS1_SHIFT)) & FMUTEST_R_PIN_CTRL_MAS1_MASK) #define FMUTEST_R_PIN_CTRL_IFREN_MASK (0x2U) #define FMUTEST_R_PIN_CTRL_IFREN_SHIFT (1U) /*! IFREN - IFR Enable */ #define FMUTEST_R_PIN_CTRL_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN_MASK) #define FMUTEST_R_PIN_CTRL_IFREN1_MASK (0x4U) #define FMUTEST_R_PIN_CTRL_IFREN1_SHIFT (2U) /*! IFREN1 - IFR1 Enable */ #define FMUTEST_R_PIN_CTRL_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN1_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN1_MASK) #define FMUTEST_R_PIN_CTRL_REDEN_MASK (0x8U) #define FMUTEST_R_PIN_CTRL_REDEN_SHIFT (3U) /*! REDEN - Redundancy Block Enable */ #define FMUTEST_R_PIN_CTRL_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_REDEN_SHIFT)) & FMUTEST_R_PIN_CTRL_REDEN_MASK) #define FMUTEST_R_PIN_CTRL_LVE_MASK (0x10U) #define FMUTEST_R_PIN_CTRL_LVE_SHIFT (4U) /*! LVE - Low Voltage Enable */ #define FMUTEST_R_PIN_CTRL_LVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_LVE_SHIFT)) & FMUTEST_R_PIN_CTRL_LVE_MASK) #define FMUTEST_R_PIN_CTRL_PV_MASK (0x20U) #define FMUTEST_R_PIN_CTRL_PV_SHIFT (5U) /*! PV - Program Verify Enable */ #define FMUTEST_R_PIN_CTRL_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PV_SHIFT)) & FMUTEST_R_PIN_CTRL_PV_MASK) #define FMUTEST_R_PIN_CTRL_EV_MASK (0x40U) #define FMUTEST_R_PIN_CTRL_EV_SHIFT (6U) /*! EV - Erase Verify Enable */ #define FMUTEST_R_PIN_CTRL_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_EV_SHIFT)) & FMUTEST_R_PIN_CTRL_EV_MASK) #define FMUTEST_R_PIN_CTRL_WIPGM_MASK (0x180U) #define FMUTEST_R_PIN_CTRL_WIPGM_SHIFT (7U) /*! WIPGM - Program Current */ #define FMUTEST_R_PIN_CTRL_WIPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WIPGM_SHIFT)) & FMUTEST_R_PIN_CTRL_WIPGM_MASK) #define FMUTEST_R_PIN_CTRL_WHV_MASK (0x1E00U) #define FMUTEST_R_PIN_CTRL_WHV_SHIFT (9U) /*! WHV - High Voltage Level */ #define FMUTEST_R_PIN_CTRL_WHV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WHV_SHIFT)) & FMUTEST_R_PIN_CTRL_WHV_MASK) #define FMUTEST_R_PIN_CTRL_WMV_MASK (0xE000U) #define FMUTEST_R_PIN_CTRL_WMV_SHIFT (13U) /*! WMV - Medium Voltage Level */ #define FMUTEST_R_PIN_CTRL_WMV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WMV_SHIFT)) & FMUTEST_R_PIN_CTRL_WMV_MASK) #define FMUTEST_R_PIN_CTRL_XE_MASK (0x10000U) #define FMUTEST_R_PIN_CTRL_XE_SHIFT (16U) /*! XE - X Address Enable */ #define FMUTEST_R_PIN_CTRL_XE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_XE_SHIFT)) & FMUTEST_R_PIN_CTRL_XE_MASK) #define FMUTEST_R_PIN_CTRL_YE_MASK (0x20000U) #define FMUTEST_R_PIN_CTRL_YE_SHIFT (17U) /*! YE - Y Address Enable */ #define FMUTEST_R_PIN_CTRL_YE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_YE_SHIFT)) & FMUTEST_R_PIN_CTRL_YE_MASK) #define FMUTEST_R_PIN_CTRL_SE_MASK (0x40000U) #define FMUTEST_R_PIN_CTRL_SE_SHIFT (18U) /*! SE - Sense Amp Enable */ #define FMUTEST_R_PIN_CTRL_SE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SE_SHIFT)) & FMUTEST_R_PIN_CTRL_SE_MASK) #define FMUTEST_R_PIN_CTRL_ERASE_MASK (0x80000U) #define FMUTEST_R_PIN_CTRL_ERASE_SHIFT (19U) /*! ERASE - Erase Mode */ #define FMUTEST_R_PIN_CTRL_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_ERASE_SHIFT)) & FMUTEST_R_PIN_CTRL_ERASE_MASK) #define FMUTEST_R_PIN_CTRL_PROG_MASK (0x100000U) #define FMUTEST_R_PIN_CTRL_PROG_SHIFT (20U) /*! PROG - Program Mode */ #define FMUTEST_R_PIN_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PROG_SHIFT)) & FMUTEST_R_PIN_CTRL_PROG_MASK) #define FMUTEST_R_PIN_CTRL_NVSTR_MASK (0x200000U) #define FMUTEST_R_PIN_CTRL_NVSTR_SHIFT (21U) /*! NVSTR - NVM Store */ #define FMUTEST_R_PIN_CTRL_NVSTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_NVSTR_SHIFT)) & FMUTEST_R_PIN_CTRL_NVSTR_MASK) #define FMUTEST_R_PIN_CTRL_SLM_MASK (0x400000U) #define FMUTEST_R_PIN_CTRL_SLM_SHIFT (22U) /*! SLM - Sleep Mode Enable */ #define FMUTEST_R_PIN_CTRL_SLM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SLM_SHIFT)) & FMUTEST_R_PIN_CTRL_SLM_MASK) #define FMUTEST_R_PIN_CTRL_RECALL_MASK (0x800000U) #define FMUTEST_R_PIN_CTRL_RECALL_SHIFT (23U) /*! RECALL - Recall Trim Code */ #define FMUTEST_R_PIN_CTRL_RECALL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_RECALL_SHIFT)) & FMUTEST_R_PIN_CTRL_RECALL_MASK) #define FMUTEST_R_PIN_CTRL_HEM_MASK (0x1000000U) #define FMUTEST_R_PIN_CTRL_HEM_SHIFT (24U) /*! HEM - HEM Control */ #define FMUTEST_R_PIN_CTRL_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_HEM_SHIFT)) & FMUTEST_R_PIN_CTRL_HEM_MASK) /*! @} */ /*! @name R_CNT_LOOP_CTRL - BIST Loop Count Control Register */ /*! @{ */ #define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK (0xFFFU) #define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT (0U) /*! LOOPCNT - Loop Count Control */ #define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK) #define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK (0x7000U) #define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT (12U) /*! LOOPOPT - Loop Option * 0b000..Loop is disabled; selected BIST operation is run once * 0b001..Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. * 0b010..Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. * 0b011..Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1. * 0b100..Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1. */ #define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK) #define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK (0x38000U) #define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT (15U) /*! LOOPUNIT - Loop Time Unit * 0b000..Clock cycles * 0b001..0.5 usec * 0b010..1 usec * 0b011..10 usec * 0b100..100 usec * 0b101..1 msec * 0b110..10 msec * 0b111..100 msec */ #define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK) #define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK (0x1FC0000U) #define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT (18U) /*! LOOPDLY - Loop Time Delay Scalar */ #define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK) /*! @} */ /*! @name R_TIMER_CTRL - BIST Timer Control Register */ /*! @{ */ #define FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK (0x7U) #define FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT (0U) /*! TNVSUNIT - Tnvs Time Unit * 0b000..Clock cycles * 0b001..0.5 usec * 0b010..1 usec * 0b011..10 usec * 0b100..100 usec * 0b101..1 msec * 0b110..10 msec * 0b111..100 msec */ #define FMUTEST_R_TIMER_CTRL_TNVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK) #define FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK (0x78U) #define FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT (3U) /*! TNVSDLY - Tnvs Time Delay Scalar */ #define FMUTEST_R_TIMER_CTRL_TNVSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK) #define FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK (0x380U) #define FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT (7U) /*! TNVHUNIT - Tnvh Time Unit * 0b000..Clock cycles * 0b001..0.5 usec * 0b010..1 usec * 0b011..10 usec * 0b100..100 usec * 0b101..1 msec * 0b110..10 msec * 0b111..100 msec */ #define FMUTEST_R_TIMER_CTRL_TNVHUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK) #define FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK (0x3C00U) #define FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT (10U) /*! TNVHDLY - Tnvh Time Delay Scalar */ #define FMUTEST_R_TIMER_CTRL_TNVHDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK) #define FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK (0x1C000U) #define FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT (14U) /*! TPGSUNIT - Tpgs Time Unit * 0b000..Clock cycles * 0b001..0.5 usec * 0b010..1 usec * 0b011..10 usec * 0b100..100 usec * 0b101..1 msec * 0b110..10 msec * 0b111..100 msec */ #define FMUTEST_R_TIMER_CTRL_TPGSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK) #define FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK (0x1E0000U) #define FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT (17U) /*! TPGSDLY - Tpgs Time Delay Scalar */ #define FMUTEST_R_TIMER_CTRL_TPGSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK) #define FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK (0xE00000U) #define FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT (21U) /*! TRCVUNIT - Trcv Time Unit * 0b000..Clock cycles * 0b001..0.5 usec * 0b010..1 usec * 0b011..10 usec * 0b100..100 usec * 0b101..1 msec * 0b110..10 msec * 0b111..100 msec */ #define FMUTEST_R_TIMER_CTRL_TRCVUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK) #define FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK (0xF000000U) #define FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT (24U) /*! TRCVDLY - Trcv Time Delay Scalar */ #define FMUTEST_R_TIMER_CTRL_TRCVDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK) #define FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK (0x70000000U) #define FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT (28U) /*! TLVSUNIT - Tlvs Time Unit * 0b000..Clock cycles * 0b001..0.5 usec * 0b010..1 usec * 0b011..10 usec * 0b100..100 usec * 0b101..1 msec * 0b110..10 msec * 0b111..100 msec */ #define FMUTEST_R_TIMER_CTRL_TLVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK) #define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK (0x80000000U) #define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT (31U) /*! TLVSDLY_L - Tlvs Time Delay Scalar Low */ #define FMUTEST_R_TIMER_CTRL_TLVSDLY_L(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK) /*! @} */ /*! @name R_TEST_CTRL - BIST Test Control Register */ /*! @{ */ #define FMUTEST_R_TEST_CTRL_BUSY_MASK (0x1U) #define FMUTEST_R_TEST_CTRL_BUSY_SHIFT (0U) /*! BUSY - BIST Busy Status * 0b0..BIST is idle * 0b1..BIST is busy */ #define FMUTEST_R_TEST_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_BUSY_SHIFT)) & FMUTEST_R_TEST_CTRL_BUSY_MASK) #define FMUTEST_R_TEST_CTRL_DEBUG_MASK (0x2U) #define FMUTEST_R_TEST_CTRL_DEBUG_SHIFT (1U) /*! DEBUG - BIST Debug Status */ #define FMUTEST_R_TEST_CTRL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUG_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUG_MASK) #define FMUTEST_R_TEST_CTRL_STATUS0_MASK (0x4U) #define FMUTEST_R_TEST_CTRL_STATUS0_SHIFT (2U) /*! STATUS0 - BIST Status 0 * 0b0..BIST test passed on flash block 0 * 0b1..BIST test failed on flash block 0 */ #define FMUTEST_R_TEST_CTRL_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS0_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS0_MASK) #define FMUTEST_R_TEST_CTRL_STATUS1_MASK (0x8U) #define FMUTEST_R_TEST_CTRL_STATUS1_SHIFT (3U) /*! STATUS1 - BIST status 1 * 0b0..BIST test passed on flash block 1 * 0b1..BIST test failed on flash block 1 */ #define FMUTEST_R_TEST_CTRL_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS1_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS1_MASK) #define FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK (0x10U) #define FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT (4U) /*! DEBUGRUN - BIST Continue Debug Run */ #define FMUTEST_R_TEST_CTRL_DEBUGRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK) #define FMUTEST_R_TEST_CTRL_STARTRUN_MASK (0x20U) #define FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT (5U) /*! STARTRUN - Run New BIST Operation */ #define FMUTEST_R_TEST_CTRL_STARTRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_STARTRUN_MASK) #define FMUTEST_R_TEST_CTRL_CMDINDEX_MASK (0xFFC0U) #define FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT (6U) /*! CMDINDEX - BIST Command Index (code) */ #define FMUTEST_R_TEST_CTRL_CMDINDEX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT)) & FMUTEST_R_TEST_CTRL_CMDINDEX_MASK) #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT (16U) /*! DISABLE_IP1 - BIST Disable IP1 */ #define FMUTEST_R_TEST_CTRL_DISABLE_IP1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK) /*! @} */ /*! @name R_ABORT_LOOP - BIST Abort Loop Register */ /*! @{ */ #define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK (0x1U) #define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT (0U) /*! ABORT_LOOP - Abort Loop * 0b0..No effect * 0b1..Abort BIST loop commands and force the loop counter to return to 0x0 */ #define FMUTEST_R_ABORT_LOOP_ABORT_LOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT)) & FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK) /*! @} */ /*! @name R_ADR_QUERY - BIST Address Query Register */ /*! @{ */ #define FMUTEST_R_ADR_QUERY_YADRFAIL_MASK (0x1FU) #define FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT (0U) /*! YADRFAIL - Failing YADR */ #define FMUTEST_R_ADR_QUERY_YADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_YADRFAIL_MASK) #define FMUTEST_R_ADR_QUERY_XADRFAIL_MASK (0x1FFE0U) #define FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT (5U) /*! XADRFAIL - Failing XADR */ #define FMUTEST_R_ADR_QUERY_XADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_XADRFAIL_MASK) /*! @} */ /*! @name R_DOUT_QUERY0 - BIST DOUT Query 0 Register */ /*! @{ */ #define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK (0xFFFFFFFFU) #define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT (0U) /*! DOUTFAIL - Failing DOUT Low */ #define FMUTEST_R_DOUT_QUERY0_DOUTFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT)) & FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK) /*! @} */ /*! @name R_SMW_QUERY - BIST SMW Query Register */ /*! @{ */ #define FMUTEST_R_SMW_QUERY_SMWLOOP_MASK (0x3FFU) #define FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT (0U) /*! SMWLOOP - SMW Total Loop Count */ #define FMUTEST_R_SMW_QUERY_SMWLOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLOOP_MASK) #define FMUTEST_R_SMW_QUERY_SMWLAST_MASK (0x7FC00U) #define FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT (10U) /*! SMWLAST - SMW Last Voltage Setting */ #define FMUTEST_R_SMW_QUERY_SMWLAST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLAST_MASK) /*! @} */ /*! @name R_SMW_SETTING0 - BIST SMW Setting 0 Register */ /*! @{ */ #define FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK (0x7FFFFFFFU) #define FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT (0U) /*! SMWPARM0 - SMW Parameter Set 0 */ #define FMUTEST_R_SMW_SETTING0_SMWPARM0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT)) & FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK) /*! @} */ /*! @name R_SMW_SETTING1 - BIST SMW Setting 1 Register */ /*! @{ */ #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) #define FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT (0U) /*! SMWPARM1 - SMW Parameter Set 1 */ #define FMUTEST_R_SMW_SETTING1_SMWPARM1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK) /*! @} */ /*! @name R_SMP_WHV0 - BIST SMP WHV Setting 0 Register */ /*! @{ */ #define FMUTEST_R_SMP_WHV0_SMPWHV0_MASK (0xFFFFFFFFU) #define FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT (0U) /*! SMPWHV0 - SMP WHV Parameter Set 0 */ #define FMUTEST_R_SMP_WHV0_SMPWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT)) & FMUTEST_R_SMP_WHV0_SMPWHV0_MASK) /*! @} */ /*! @name R_SMP_WHV1 - BIST SMP WHV Setting 1 Register */ /*! @{ */ #define FMUTEST_R_SMP_WHV1_SMPWHV1_MASK (0xFFFFFFFFU) #define FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT (0U) /*! SMPWHV1 - SMP WHV Parameter Set 1 */ #define FMUTEST_R_SMP_WHV1_SMPWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT)) & FMUTEST_R_SMP_WHV1_SMPWHV1_MASK) /*! @} */ /*! @name R_SME_WHV0 - BIST SME WHV Setting 0 Register */ /*! @{ */ #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) #define FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT (0U) /*! SMEWHV0 - SME WHV Parameter Set 0 */ #define FMUTEST_R_SME_WHV0_SMEWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK) /*! @} */ /*! @name R_SME_WHV1 - BIST SME WHV Setting 1 Register */ /*! @{ */ #define FMUTEST_R_SME_WHV1_SMEWHV1_MASK (0xFFFFFFFFU) #define FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT (0U) /*! SMEWHV1 - SME WHV Parameter Set 1 */ #define FMUTEST_R_SME_WHV1_SMEWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT)) & FMUTEST_R_SME_WHV1_SMEWHV1_MASK) /*! @} */ /*! @name R_SMW_SETTING2 - BIST SMW Setting 2 Register */ /*! @{ */ #define FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK (0x1FFFFFFFU) #define FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT (0U) /*! SMWPARM2 - SMW Parameter Set 2 */ #define FMUTEST_R_SMW_SETTING2_SMWPARM2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT)) & FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK) /*! @} */ /*! @name R_D_MISR0 - BIST DIN MISR 0 Register */ /*! @{ */ #define FMUTEST_R_D_MISR0_DATASIG0_MASK (0xFFFFFFFFU) #define FMUTEST_R_D_MISR0_DATASIG0_SHIFT (0U) /*! DATASIG0 - Data Signature */ #define FMUTEST_R_D_MISR0_DATASIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR0_DATASIG0_SHIFT)) & FMUTEST_R_D_MISR0_DATASIG0_MASK) /*! @} */ /*! @name R_A_MISR0 - BIST Address MISR 0 Register */ /*! @{ */ #define FMUTEST_R_A_MISR0_ADRSIG0_MASK (0xFFFFFFFFU) #define FMUTEST_R_A_MISR0_ADRSIG0_SHIFT (0U) /*! ADRSIG0 - Address Signature */ #define FMUTEST_R_A_MISR0_ADRSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR0_ADRSIG0_SHIFT)) & FMUTEST_R_A_MISR0_ADRSIG0_MASK) /*! @} */ /*! @name R_C_MISR0 - BIST Control MISR 0 Register */ /*! @{ */ #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) #define FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT (0U) /*! CTRLSIG0 - Control Signature */ #define FMUTEST_R_C_MISR0_CTRLSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK) /*! @} */ /*! @name R_SMW_SETTING3 - BIST SMW Setting 3 Register */ /*! @{ */ #define FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK (0x1FFFFU) #define FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT (0U) /*! SMWPARM3 - SMW Parameter Set 3 */ #define FMUTEST_R_SMW_SETTING3_SMWPARM3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT)) & FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK) /*! @} */ /*! @name R_DATA_CTRL1 - BIST Data Control 1 Register */ /*! @{ */ #define FMUTEST_R_DATA_CTRL1_DATA1_MASK (0xFFFFFFFFU) #define FMUTEST_R_DATA_CTRL1_DATA1_SHIFT (0U) /*! DATA1 - BIST Data 1 Low */ #define FMUTEST_R_DATA_CTRL1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_DATA1_SHIFT)) & FMUTEST_R_DATA_CTRL1_DATA1_MASK) /*! @} */ /*! @name R_DATA_CTRL2 - BIST Data Control 2 Register */ /*! @{ */ #define FMUTEST_R_DATA_CTRL2_DATA2_MASK (0xFFFFFFFFU) #define FMUTEST_R_DATA_CTRL2_DATA2_SHIFT (0U) /*! DATA2 - BIST Data 2 Low */ #define FMUTEST_R_DATA_CTRL2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_DATA2_SHIFT)) & FMUTEST_R_DATA_CTRL2_DATA2_MASK) /*! @} */ /*! @name R_DATA_CTRL3 - BIST Data Control 3 Register */ /*! @{ */ #define FMUTEST_R_DATA_CTRL3_DATA3_MASK (0xFFFFFFFFU) #define FMUTEST_R_DATA_CTRL3_DATA3_SHIFT (0U) /*! DATA3 - BIST Data 3 Low */ #define FMUTEST_R_DATA_CTRL3_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_DATA3_SHIFT)) & FMUTEST_R_DATA_CTRL3_DATA3_MASK) /*! @} */ /*! @name R_REPAIR0_0 - BIST Repair 0 for Block 0 Register */ /*! @{ */ #define FMUTEST_R_REPAIR0_0_RDIS0_0_MASK (0x1U) #define FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT (0U) /*! RDIS0_0 - Control Repair 0 in Block 0. * 0b0..Repair address is valid * 0b1..Repair address is not valid */ #define FMUTEST_R_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RDIS0_0_MASK) #define FMUTEST_R_REPAIR0_0_RADR0_0_MASK (0x1FEU) #define FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT (1U) /*! RADR0_0 - XADR for Repair 0 in Block 0 */ #define FMUTEST_R_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RADR0_0_MASK) /*! @} */ /*! @name R_REPAIR0_1 - BIST Repair 1 Block 0 Register */ /*! @{ */ #define FMUTEST_R_REPAIR0_1_RDIS0_1_MASK (0x1U) #define FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT (0U) /*! RDIS0_1 - Control Repair 1 in Block 0. * 0b0..Repair address is valid * 0b1..Repair address is not valid */ #define FMUTEST_R_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RDIS0_1_MASK) #define FMUTEST_R_REPAIR0_1_RADR0_1_MASK (0x1FEU) #define FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT (1U) /*! RADR0_1 - XADR for Repair 1 in Block 0. */ #define FMUTEST_R_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RADR0_1_MASK) /*! @} */ /*! @name R_REPAIR1_0 - BIST Repair 0 Block 1 Register */ /*! @{ */ #define FMUTEST_R_REPAIR1_0_RDIS1_0_MASK (0x1U) #define FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT (0U) /*! RDIS1_0 - Control Repair 0 in Block 1. * 0b0..Repair address is valid * 0b1..Repair address is not valid */ #define FMUTEST_R_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RDIS1_0_MASK) #define FMUTEST_R_REPAIR1_0_RADR1_0_MASK (0x1FEU) #define FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT (1U) /*! RADR1_0 - XADR for Repair 0 in Block 1. */ #define FMUTEST_R_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RADR1_0_MASK) /*! @} */ /*! @name R_REPAIR1_1 - BIST Repair 1 Block 1 Register */ /*! @{ */ #define FMUTEST_R_REPAIR1_1_RDIS1_1_MASK (0x1U) #define FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT (0U) /*! RDIS1_1 - Control Repair 1 in Block 1. * 0b0..Repair address is valid * 0b1..Repair address is not valid */ #define FMUTEST_R_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RDIS1_1_MASK) #define FMUTEST_R_REPAIR1_1_RADR1_1_MASK (0x1FEU) #define FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT (1U) /*! RADR1_1 - XADR for Repair 1 in Block 1. */ #define FMUTEST_R_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RADR1_1_MASK) /*! @} */ /*! @name R_DATA_CTRL0_EX - BIST Data Control 0 Extension Register */ /*! @{ */ #define FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK (0x7U) #define FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT (0U) /*! DATA0X - BIST Data 0 High */ #define FMUTEST_R_DATA_CTRL0_EX_DATA0X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT)) & FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK) /*! @} */ /*! @name R_TIMER_CTRL_EX - BIST Timer Control Extension Register */ /*! @{ */ #define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK (0x7U) #define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT (0U) /*! TLVSDLY_H - Tlvs Time Delay Scalar High */ #define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT)) & FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK) /*! @} */ /*! @name R_DOUT_QUERY1 - BIST DOUT Query 1 Register */ /*! @{ */ #define FMUTEST_R_DOUT_QUERY1_DOUT_MASK (0x7U) #define FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT (0U) /*! DOUT - Failing DOUT High */ #define FMUTEST_R_DOUT_QUERY1_DOUT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT)) & FMUTEST_R_DOUT_QUERY1_DOUT_MASK) /*! @} */ /*! @name R_D_MISR1 - BIST DIN MISR 1 Register */ /*! @{ */ #define FMUTEST_R_D_MISR1_DATASIG1_MASK (0xFFU) #define FMUTEST_R_D_MISR1_DATASIG1_SHIFT (0U) /*! DATASIG1 - MISR Data Signature High */ #define FMUTEST_R_D_MISR1_DATASIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR1_DATASIG1_SHIFT)) & FMUTEST_R_D_MISR1_DATASIG1_MASK) /*! @} */ /*! @name R_A_MISR1 - BIST Address MISR 1 Register */ /*! @{ */ #define FMUTEST_R_A_MISR1_ADRSIG1_MASK (0xFFU) #define FMUTEST_R_A_MISR1_ADRSIG1_SHIFT (0U) /*! ADRSIG1 - MISR Address Signature High */ #define FMUTEST_R_A_MISR1_ADRSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR1_ADRSIG1_SHIFT)) & FMUTEST_R_A_MISR1_ADRSIG1_MASK) /*! @} */ /*! @name R_C_MISR1 - BIST Control MISR 1 Register */ /*! @{ */ #define FMUTEST_R_C_MISR1_CTRLSIG1_MASK (0xFFU) #define FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT (0U) /*! CTRLSIG1 - MISR Control Signature High */ #define FMUTEST_R_C_MISR1_CTRLSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT)) & FMUTEST_R_C_MISR1_CTRLSIG1_MASK) /*! @} */ /*! @name R_DATA_CTRL1_EX - BIST Data Control 1 Extension Register */ /*! @{ */ #define FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK (0x7U) #define FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT (0U) /*! DATA1X - BIST Data 1 High */ #define FMUTEST_R_DATA_CTRL1_EX_DATA1X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT)) & FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK) /*! @} */ /*! @name R_DATA_CTRL2_EX - BIST Data Control 2 Extension Register */ /*! @{ */ #define FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK (0x7U) #define FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT (0U) /*! DATA2X - BIST Data 2 High */ #define FMUTEST_R_DATA_CTRL2_EX_DATA2X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT)) & FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK) /*! @} */ /*! @name R_DATA_CTRL3_EX - BIST Data Control 3 Extension Register */ /*! @{ */ #define FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK (0x7U) #define FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT (0U) /*! DATA3X - BIST Data 3 High */ #define FMUTEST_R_DATA_CTRL3_EX_DATA3X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT)) & FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK) /*! @} */ /*! @name SMW_TIMER_OPTION - SMW Timer Option Register */ /*! @{ */ #define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK (0xFFU) #define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT (0U) /*! SMW_CDIVL - Clock Divide Scalar for Long Pulse */ #define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK) #define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK (0x1F00U) #define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT (8U) /*! SMW_TVFY - Timer Adjust for Verify */ #define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK) /*! @} */ /*! @name SMW_SETTING_OPTION0 - SMW Setting Option 0 Register */ /*! @{ */ #define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK (0x1C000U) #define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT (14U) /*! MV_INIT - Medium Voltage Level Select Initial */ #define FMUTEST_SMW_SETTING_OPTION0_MV_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK) #define FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK (0xE0000U) #define FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT (17U) /*! MV_END - Medium Voltage Level Select Final */ #define FMUTEST_SMW_SETTING_OPTION0_MV_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK) #define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK (0xF00000U) #define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT (20U) /*! MV_MISC - Medium Voltage Control Misc */ #define FMUTEST_SMW_SETTING_OPTION0_MV_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK) #define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK (0x3000000U) #define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT (24U) /*! IPGM_INIT - Program Current Control Initial */ #define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK) #define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK (0xC000000U) #define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT (26U) /*! IPGM_END - Program Current Control Final */ #define FMUTEST_SMW_SETTING_OPTION0_IPGM_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK) #define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK (0x70000000U) #define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT (28U) /*! IPGM_MISC - Program Current Control Misc */ #define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK) /*! @} */ /*! @name SMW_SETTING_OPTION2 - SMW Setting Option 2 Register */ /*! @{ */ #define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK (0x7U) #define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT (0U) /*! THVS_CTRL - Thvs control */ #define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK) #define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK (0x38U) #define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT (3U) /*! TRCV_CTRL - Trcv Control */ #define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK) #define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK (0xC0U) #define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT (6U) /*! XTRA_ERS - Number of Post Shots for SME */ #define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK) #define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK (0x300U) #define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT (8U) /*! XTRA_PGM - Number of Post Shots for SMP */ #define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK) #define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK (0x3FC00U) #define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT (10U) /*! WHV_CNTR - WHV Counter */ #define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK) #define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK (0x1C0000U) #define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT (18U) /*! POST_TERS - Post Ters Time * 0b000..50 usec * 0b001..100 usec * 0b010..200 usec * 0b011..300 usec * 0b100..500 usec * 0b101..1 msec * 0b110..1.5 msec * 0b111..2 msec */ #define FMUTEST_SMW_SETTING_OPTION2_POST_TERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK) #define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK (0x600000U) #define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT (21U) /*! POST_TPGM - Post Tpgm Time * 0b00..1 usec * 0b01..2 usec * 0b10..4 usec * 0b11..8 usec */ #define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK) #define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK (0x1800000U) #define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT (23U) /*! VFY_OPT - Verify Option * 0b00..Skip verify for post shot only, verify for all other shots * 0b01..Skip verify for the 1st and post shots * 0b10..Skip the 1st, 2nd, and post shots * 0b11..Skip verify for all shots */ #define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK) #define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK (0x6000000U) #define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT (25U) /*! TPGM_OPT - Tpgm Option * 0b00..Fixed Tpgm for all shots, except post shot * 0b01..Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec * 0b10..Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec * 0b11..Unused */ #define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK) #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT (27U) /*! MASK0_OPT - MASK0_OPT * 0b0..Mask programmed bits passing PV until extra shot * 0b1..Always program bits even if they pass PV */ #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK) #define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK (0x10000000U) #define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT (28U) /*! DIS_PRER - Disable pre-PV Read before First Program Shot * 0b0..Enable pre-PV read before first program shot * 0b1..Disable pre-PV read before first program shot */ #define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK) /*! @} */ /*! @name SMW_SETTING_OPTION3 - SMW Setting Option 3 Register */ /*! @{ */ #define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK (0xFFU) #define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT (0U) /*! HEM_WHV_CNTR - WHV_COUNTER for HEM-erase Cycle */ #define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK) #define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK (0x1FF00U) #define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT (8U) /*! HEM_MAX_ERS - HEM Max Erase Shot Count */ #define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK) /*! @} */ /*! @name SMW_SMP_WHV_OPTION0 - SMW SMP WHV Option 0 Register */ /*! @{ */ #define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT (0U) /*! SMP_WHV_OPT0 - Smart Program WHV Option Low */ #define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK) /*! @} */ /*! @name SMW_SME_WHV_OPTION0 - SMW SME WHV Option 0 Register */ /*! @{ */ #define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT (0U) /*! SME_WHV_OPT0 - Smart Erase WHV Option Low */ #define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK) /*! @} */ /*! @name SMW_SETTING_OPTION1 - SMW Setting Option 1 Register */ /*! @{ */ #define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK (0x7U) #define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT (0U) /*! TERS_CTRL0 - Ters Control * 0b000..50 usec * 0b001..100 usec * 0b010..200 usec * 0b011..300 usec * 0b100..500 usec * 0b101..1 msec * 0b110..1.5 msec * 0b111..2 msec */ #define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK) #define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK (0x18U) #define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT (3U) /*! TPGM_CTRL - Tpgm Control * 0b00..1 usec * 0b01..2 usec * 0b10..4 usec * 0b11..8 usec */ #define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK) #define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK (0xE0U) #define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT (5U) /*! TNVS_CTRL - Tnvs Control * 0b000..5 usec * 0b001..8 usec * 0b010..11 usec * 0b011..14 usec * 0b100..17 usec * 0b101..20 usec * 0b110..23 usec * 0b111..26 usec */ #define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK) #define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK (0x700U) #define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT (8U) /*! TNVH_CTRL - Tnvh Control * 0b000..2 usec * 0b001..2.5 usec * 0b010..3 usec * 0b011..3.5 usec * 0b100..4 usec * 0b101..4.5 usec * 0b110..5 usec * 0b111..5.5 usec */ #define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK) #define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK (0x3800U) #define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT (11U) /*! TPGS_CTRL - Tpgs Control * 0b000..1 usec * 0b001..2 usec * 0b010..3 usec * 0b011..4 usec * 0b100..5 usec * 0b101..6 usec * 0b110..7 usec * 0b111..8 usec */ #define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK) #define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK (0x7FC000U) #define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT (14U) /*! MAX_ERASE - Number of Erase Shots */ #define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK) #define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK (0xF800000U) #define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT (23U) /*! MAX_PROG - Number of Program Shots */ #define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK) /*! @} */ /*! @name SMW_SMP_WHV_OPTION1 - SMW SMP WHV Option 1 Register */ /*! @{ */ #define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT (0U) /*! SMP_WHV_OPT1 - Smart Program WHV Option High */ #define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK) /*! @} */ /*! @name SMW_SME_WHV_OPTION1 - SMW SME WHV Option 1 Register */ /*! @{ */ #define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK (0xFFFFFFFFU) #define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT (0U) /*! SME_WHV_OPT1 - Smart Erase WHV Option High */ #define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK) /*! @} */ /*! @name REPAIR0_0 - FMU Repair 0 Block 0 Register */ /*! @{ */ #define FMUTEST_REPAIR0_0_RDIS0_0_MASK (0x1U) #define FMUTEST_REPAIR0_0_RDIS0_0_SHIFT (0U) /*! RDIS0_0 - RDIS0_0 * 0b0..Repair address is valid * 0b1..Repair address is not valid */ #define FMUTEST_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_REPAIR0_0_RDIS0_0_MASK) #define FMUTEST_REPAIR0_0_RADR0_0_MASK (0x1FEU) #define FMUTEST_REPAIR0_0_RADR0_0_SHIFT (1U) /*! RADR0_0 - RADR0_0 */ #define FMUTEST_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_REPAIR0_0_RADR0_0_MASK) /*! @} */ /*! @name REPAIR0_1 - FMU Repair 1 Block 0 Register */ /*! @{ */ #define FMUTEST_REPAIR0_1_RDIS0_1_MASK (0x1U) #define FMUTEST_REPAIR0_1_RDIS0_1_SHIFT (0U) /*! RDIS0_1 - RDIS0_1 * 0b0..Repair address is valid * 0b1..Repair address is not valid */ #define FMUTEST_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_REPAIR0_1_RDIS0_1_MASK) #define FMUTEST_REPAIR0_1_RADR0_1_MASK (0x1FEU) #define FMUTEST_REPAIR0_1_RADR0_1_SHIFT (1U) /*! RADR0_1 - RADR0_1 */ #define FMUTEST_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_REPAIR0_1_RADR0_1_MASK) /*! @} */ /*! @name REPAIR1_0 - FMU Repair 0 Block 1 Register */ /*! @{ */ #define FMUTEST_REPAIR1_0_RDIS1_0_MASK (0x1U) #define FMUTEST_REPAIR1_0_RDIS1_0_SHIFT (0U) /*! RDIS1_0 - RDIS1_0 * 0b0..Repair address is valid * 0b1..Repair address is not valid */ #define FMUTEST_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_REPAIR1_0_RDIS1_0_MASK) #define FMUTEST_REPAIR1_0_RADR1_0_MASK (0x1FEU) #define FMUTEST_REPAIR1_0_RADR1_0_SHIFT (1U) /*! RADR1_0 - RADR1_0 */ #define FMUTEST_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_REPAIR1_0_RADR1_0_MASK) /*! @} */ /*! @name REPAIR1_1 - FMU Repair 1 Block 1 Register */ /*! @{ */ #define FMUTEST_REPAIR1_1_RDIS1_1_MASK (0x1U) #define FMUTEST_REPAIR1_1_RDIS1_1_SHIFT (0U) /*! RDIS1_1 - RDIS1_1 * 0b0..Repair address is valid * 0b1..Repair address is not valid */ #define FMUTEST_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_REPAIR1_1_RDIS1_1_MASK) #define FMUTEST_REPAIR1_1_RADR1_1_MASK (0x1FEU) #define FMUTEST_REPAIR1_1_RADR1_1_SHIFT (1U) /*! RADR1_1 - RADR1_1 */ #define FMUTEST_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_REPAIR1_1_RADR1_1_MASK) /*! @} */ /*! @name SMW_HB_SIGNALS - SMW HB Signals Register */ /*! @{ */ #define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK (0x7U) #define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT (0U) /*! SMW_ARRAY - SMW Region Select * 0b000..Main array * 0b001..IFR space only or main (and REDEN space) with IFR space for mass erase * 0b010..IFR1 space * 0b100..REDEN space */ #define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK) #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK (0x8U) #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT (3U) /*! USER_IFREN1 - IFR1 Enable * 0b0..IFREN1 input to the flash array is driven LOW * 0b1..IFREN1 input to the flash array is driven HIGH */ #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK) #define FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK (0x10U) #define FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT (4U) /*! USER_PV - Program Verify * 0b0..PV input to the flash array is driven LOW * 0b1..PV input to the flash array is driven HIGH */ #define FMUTEST_SMW_HB_SIGNALS_USER_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK) #define FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK (0x20U) #define FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT (5U) /*! USER_EV - Erase Verify * 0b0..EV input to the flash array is driven LOW * 0b1..EV input to the flash array is driven HIGH */ #define FMUTEST_SMW_HB_SIGNALS_USER_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK) #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK (0x40U) #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT (6U) /*! USER_IFREN - IFR Enable * 0b0..IFREN input to the flash array is driven LOW * 0b1..IFREN input to the flash array is driven HIGH */ #define FMUTEST_SMW_HB_SIGNALS_USER_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK) #define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK (0x80U) #define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT (7U) /*! USER_REDEN - Repair Read Enable * 0b0..REDEN input to the flash array is driven LOW * 0b1..REDEN input to the flash array is driven HIGH */ #define FMUTEST_SMW_HB_SIGNALS_USER_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK) #define FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK (0x100U) #define FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT (8U) /*! USER_HEM - High Endurance Enable * 0b0..HEM input to SMW / BIST PIN_CTRL[24] is driven LOW * 0b1..HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH */ #define FMUTEST_SMW_HB_SIGNALS_USER_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK) /*! @} */ /*! @name BIST_DUMP_CTRL - BIST Datadump Control Register */ /*! @{ */ #define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK (0x10000U) #define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT (16U) /*! BIST_DONE - BIST Done * 0b0..The BIST (or data dump) is running * 0b1..The BIST (or data dump) has completed */ #define FMUTEST_BIST_DUMP_CTRL_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK) #define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK (0x20000U) #define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT (17U) /*! BIST_FAIL - BIST Fail * 0b0..The last BIST operation completed successfully (or could not fail) * 0b1..The last BIST operation failed */ #define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK (0x40000U) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT (18U) /*! DATADUMP - Data Dump Enable */ #define FMUTEST_BIST_DUMP_CTRL_DATADUMP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK (0x80000U) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT (19U) /*! DATADUMP_TRIG - Data Dump Trigger */ #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK (0x300000U) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT (20U) /*! DATADUMP_PATT - Data Dump Pattern Select * 0b00..All ones * 0b01..All zeroes * 0b10..Checkerboard * 0b11..Inverse checkerboard */ #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK (0x400000U) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT (22U) /*! DATADUMP_MRGEN - Data Dump Margin Enable * 0b0..Normal read pulse shape * 0b1..Margin read pulse shape */ #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK (0x800000U) #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT (23U) /*! DATADUMP_MRGTYPE - Data Dump Margin Type * 0b0..DIN method used * 0b1..TM method used */ #define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK) /*! @} */ /*! @name ATX_PIN_CTRL - ATX Pin Control Register */ /*! @{ */ #define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK (0xFFU) #define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT (0U) /*! TM_TO_ATX - TM to ATX * 0b00000001..TM[0] to ATX0 * 0b00000010..TM[1] to ATX0 * 0b00000100..TM[2] to ATX0 * 0b00001000..TM[3] to ATX0 * 0b00010000..TM[0] to ATX1 * 0b00100000..TM[1] to ATX1 * 0b01000000..TM[2] to ATX1 * 0b10000000..TM[3] to ATX1 */ #define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT)) & FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK) /*! @} */ /*! @name FAILCNT - Fail Count Register */ /*! @{ */ #define FMUTEST_FAILCNT_FAILCNT_MASK (0xFFFFFFFFU) #define FMUTEST_FAILCNT_FAILCNT_SHIFT (0U) /*! FAILCNT - Fail Count */ #define FMUTEST_FAILCNT_FAILCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FAILCNT_FAILCNT_SHIFT)) & FMUTEST_FAILCNT_FAILCNT_MASK) /*! @} */ /*! @name PGM_PULSE_CNT0 - Block 0 Program Pulse Count Register */ /*! @{ */ #define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK (0xFFFFFFFFU) #define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT (0U) /*! PGM_CNT0 - Program Pulse Count */ #define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT)) & FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK) /*! @} */ /*! @name PGM_PULSE_CNT1 - Block 1 Program Pulse Count Register */ /*! @{ */ #define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK (0xFFFFFFFFU) #define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT (0U) /*! PGM_CNT1 - Program Pulse Count */ #define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT)) & FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK) /*! @} */ /*! @name ERS_PULSE_CNT - Erase Pulse Count Register */ /*! @{ */ #define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK (0xFFFFU) #define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT (0U) /*! ERS_CNT0 - Block 0 Erase Pulse Count */ #define FMUTEST_ERS_PULSE_CNT_ERS_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK) #define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK (0xFFFF0000U) #define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT (16U) /*! ERS_CNT1 - Block 1 Erase Pulse Count */ #define FMUTEST_ERS_PULSE_CNT_ERS_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK) /*! @} */ /*! @name MAX_PULSE_CNT - Maximum Pulse Count Register */ /*! @{ */ #define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK (0x1FFU) #define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT (0U) /*! LAST_PCNT - Last SMW Operation's Pulse Count */ #define FMUTEST_MAX_PULSE_CNT_LAST_PCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK) #define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK (0x1FF0000U) #define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT (16U) /*! MAX_ERS_CNT - Maximum Erase Pulse Count */ #define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK) #define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK (0xF8000000U) #define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT (27U) /*! MAX_PGM_CNT - Maximum Program Pulse Count */ #define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK) /*! @} */ /*! @name PORT_CTRL - Port Control Register */ /*! @{ */ #define FMUTEST_PORT_CTRL_BDONE_SEL_MASK (0x3U) #define FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT (0U) /*! BDONE_SEL - BIST Done Select * 0b00..Select internal bist_done signal from current module instantiation * 0b01..Select ipt_bist_fail signal from current module instantiation * 0b10..Select ipt_bist_done signal from other module instantiation * 0b11..Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation */ #define FMUTEST_PORT_CTRL_BDONE_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BDONE_SEL_MASK) #define FMUTEST_PORT_CTRL_BSDO_SEL_MASK (0xCU) #define FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT (2U) /*! BSDO_SEL - BIST Serial Data Output Select * 0b00..Select internal bist_sdo signal from current module instantiation * 0b01..Select ipt_bist_done signal from current module instantiation * 0b10..Select ipt_bist_sdo signal from other module instantiation * 0b11..Select ipt_bist_done signal from other module instantiation */ #define FMUTEST_PORT_CTRL_BSDO_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BSDO_SEL_MASK) /*! @} */ /*! * @} */ /* end of group FMUTEST_Register_Masks */ /* FMUTEST - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral FMU0TEST base address */ #define FMU0TEST_BASE (0x50043000u) /** Peripheral FMU0TEST base address */ #define FMU0TEST_BASE_NS (0x40043000u) /** Peripheral FMU0TEST base pointer */ #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) /** Peripheral FMU0TEST base pointer */ #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) /** Array initializer of FMUTEST peripheral base addresses */ #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } /** Array initializer of FMUTEST peripheral base pointers */ #define FMUTEST_BASE_PTRS { FMU0TEST } /** Array initializer of FMUTEST peripheral base addresses */ #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } /** Array initializer of FMUTEST peripheral base pointers */ #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } #else /** Peripheral FMU0TEST base address */ #define FMU0TEST_BASE (0x40043000u) /** Peripheral FMU0TEST base pointer */ #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) /** Array initializer of FMUTEST peripheral base addresses */ #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } /** Array initializer of FMUTEST peripheral base pointers */ #define FMUTEST_BASE_PTRS { FMU0TEST } #endif /*! * @} */ /* end of group FMUTEST_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FREQME Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer * @{ */ /** FREQME - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ __I uint32_t CTRL_R; /**< Control (in Read mode), offset: 0x0 */ __O uint32_t CTRL_W; /**< Control (in Write mode), offset: 0x0 */ }; __IO uint32_t CTRLSTAT; /**< Control Status, offset: 0x4 */ __IO uint32_t MIN; /**< Minimum, offset: 0x8 */ __IO uint32_t MAX; /**< Maximum, offset: 0xC */ } FREQME_Type; /* ---------------------------------------------------------------------------- -- FREQME Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FREQME_Register_Masks FREQME Register Masks * @{ */ /*! @name CTRL_R - Control (in Read mode) */ /*! @{ */ #define FREQME_CTRL_R_RESULT_MASK (0x7FFFFFFFU) #define FREQME_CTRL_R_RESULT_SHIFT (0U) #define FREQME_CTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK) #define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) #define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) /*! MEASURE_IN_PROGRESS - Measurement In Progress * 0b0..Complete * 0b1..In progress */ #define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) /*! @} */ /*! @name CTRL_W - Control (in Write mode) */ /*! @{ */ #define FREQME_CTRL_W_REF_SCALE_MASK (0x1FU) #define FREQME_CTRL_W_REF_SCALE_SHIFT (0U) /*! REF_SCALE - Reference Clock Scaling Factor */ #define FREQME_CTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK) #define FREQME_CTRL_W_PULSE_MODE_MASK (0x100U) #define FREQME_CTRL_W_PULSE_MODE_SHIFT (8U) /*! PULSE_MODE - Pulse Width Measurement Mode Select * 0b0..Frequency Measurement mode * 0b1..Pulse Width Measurement mode */ #define FREQME_CTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK) #define FREQME_CTRL_W_PULSE_POL_MASK (0x200U) #define FREQME_CTRL_W_PULSE_POL_SHIFT (9U) /*! PULSE_POL - Pulse Polarity * 0b0..High period * 0b1..Low period */ #define FREQME_CTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK) #define FREQME_CTRL_W_LT_MIN_INT_EN_MASK (0x1000U) #define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT (12U) /*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define FREQME_CTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK) #define FREQME_CTRL_W_GT_MAX_INT_EN_MASK (0x2000U) #define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT (13U) /*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define FREQME_CTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK) #define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) #define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT (14U) /*! RESULT_READY_INT_EN - Result Ready Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define FREQME_CTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK) #define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) #define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) /*! CONTINUOUS_MODE_EN - Continuous Mode Enable * 0b0..Disable * 0b1..Enable */ #define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK) #define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) #define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) /*! MEASURE_IN_PROGRESS - Measurement In Progress * 0b0..Terminates measurement * 0b1..Initiates measurement */ #define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK) /*! @} */ /*! @name CTRLSTAT - Control Status */ /*! @{ */ #define FREQME_CTRLSTAT_REF_SCALE_MASK (0x1FU) #define FREQME_CTRLSTAT_REF_SCALE_SHIFT (0U) /*! REF_SCALE - Reference Scale */ #define FREQME_CTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK) #define FREQME_CTRLSTAT_PULSE_MODE_MASK (0x100U) #define FREQME_CTRLSTAT_PULSE_MODE_SHIFT (8U) /*! PULSE_MODE - Pulse Mode * 0b0..Frequency Measurement mode * 0b1..Pulse Width Measurement mode */ #define FREQME_CTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK) #define FREQME_CTRLSTAT_PULSE_POL_MASK (0x200U) #define FREQME_CTRLSTAT_PULSE_POL_SHIFT (9U) /*! PULSE_POL - Pulse Polarity * 0b0..High period * 0b1..Low period */ #define FREQME_CTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK) #define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) #define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) /*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define FREQME_CTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK) #define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) #define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) /*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define FREQME_CTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK) #define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) #define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) /*! RESULT_READY_INT_EN - Result Ready Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK) #define FREQME_CTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) #define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT (24U) /*! LT_MIN_STAT - Less Than Minimum Results Status * 0b0..Greater than MIN[MIN_VALUE] * 0b1..Less than MIN[MIN_VALUE] */ #define FREQME_CTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK) #define FREQME_CTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) #define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT (25U) /*! GT_MAX_STAT - Greater Than Maximum Result Status * 0b0..Less than MAX[MAX_VALUE] * 0b1..Greater than MAX[MAX_VALUE] */ #define FREQME_CTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK) #define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) #define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT (26U) /*! RESULT_READY_STAT - Result Ready Status * 0b0..Not complete * 0b1..Complete */ #define FREQME_CTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK) #define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) #define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) /*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status * 0b0..Disabled * 0b1..Enabled */ #define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) #define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) #define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) /*! MEASURE_IN_PROGRESS - Measurement in Progress Status * 0b0..Not in progress * 0b1..In progress */ #define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK) /*! @} */ /*! @name MIN - Minimum */ /*! @{ */ #define FREQME_MIN_MIN_VALUE_MASK (0x7FFFFFFFU) #define FREQME_MIN_MIN_VALUE_SHIFT (0U) /*! MIN_VALUE - Minimum Value */ #define FREQME_MIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK) /*! @} */ /*! @name MAX - Maximum */ /*! @{ */ #define FREQME_MAX_MAX_VALUE_MASK (0x7FFFFFFFU) #define FREQME_MAX_MAX_VALUE_SHIFT (0U) /*! MAX_VALUE - Maximum Value */ #define FREQME_MAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK) /*! @} */ /*! * @} */ /* end of group FREQME_Register_Masks */ /* FREQME - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral FREQME0 base address */ #define FREQME0_BASE (0x50011000u) /** Peripheral FREQME0 base address */ #define FREQME0_BASE_NS (0x40011000u) /** Peripheral FREQME0 base pointer */ #define FREQME0 ((FREQME_Type *)FREQME0_BASE) /** Peripheral FREQME0 base pointer */ #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) /** Array initializer of FREQME peripheral base addresses */ #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } /** Array initializer of FREQME peripheral base addresses */ #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS_NS { FREQME0_NS } #else /** Peripheral FREQME0 base address */ #define FREQME0_BASE (0x40011000u) /** Peripheral FREQME0 base pointer */ #define FREQME0 ((FREQME_Type *)FREQME0_BASE) /** Array initializer of FREQME peripheral base addresses */ #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } #endif /** Interrupt vectors for the FREQME peripheral type */ #define FREQME_IRQS { Freqme_IRQn } /*! * @} */ /* end of group FREQME_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GDET Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GDET_Peripheral_Access_Layer GDET Peripheral Access Layer * @{ */ /** GDET - Register Layout Typedef */ typedef struct { __IO uint32_t GDET_CONF_0; /**< GDET Configuration 0 Register, offset: 0x0 */ __IO uint32_t GDET_CONF_1; /**< GDET Configuration 1 Register, offset: 0x4 */ __IO uint32_t GDET_ENABLE1; /**< GDET Enable Register, offset: 0x8 */ __IO uint32_t GDET_CONF_2; /**< GDET Configuration 2 Register, offset: 0xC */ __IO uint32_t GDET_CONF_3; /**< GDET Configuration 3 Register, offset: 0x10 */ __IO uint32_t GDET_CONF_4; /**< GDET Configuration 4 Register, offset: 0x14 */ __IO uint32_t GDET_CONF_5; /**< GDET Configuration 5 Register, offset: 0x18 */ uint8_t RESERVED_0[4004]; __IO uint32_t GDET_RESET; /**< GDET Reset Register, offset: 0xFC0 */ __IO uint32_t GDET_TEST; /**< GDET Test Register, offset: 0xFC4 */ uint8_t RESERVED_1[4]; __IO uint32_t GDET_DLY_CTRL; /**< GDET Delay Control Register, offset: 0xFCC */ } GDET_Type; /* ---------------------------------------------------------------------------- -- GDET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GDET_Register_Masks GDET Register Masks * @{ */ /*! @name GDET_CONF_0 - GDET Configuration 0 Register */ /*! @{ */ #define GDET_GDET_CONF_0_FIELD_3_0_MASK (0xFU) #define GDET_GDET_CONF_0_FIELD_3_0_SHIFT (0U) /*! FIELD_3_0 - GDET Configuration 0 Field 3_0 */ #define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) #define GDET_GDET_CONF_0_FIELD_3_0_MASK (0xFU) #define GDET_GDET_CONF_0_FIELD_3_0_SHIFT (0U) /*! field_3_0 - GDET configuration 0 Field 3_0 */ #define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) #define GDET_GDET_CONF_0_SBZ_MASK (0x10U) #define GDET_GDET_CONF_0_SBZ_SHIFT (4U) /*! SBZ - Should Be Left to Zero */ #define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) #define GDET_GDET_CONF_0_SBZ_MASK (0x10U) #define GDET_GDET_CONF_0_SBZ_SHIFT (4U) /*! sbz - Should be left to zero */ #define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) #define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) #define GDET_GDET_CONF_0_RFU_SHIFT (5U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) #define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) #define GDET_GDET_CONF_0_RFU_SHIFT (5U) /*! rfu - Reserved for Future Use */ #define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) /*! @} */ /*! @name GDET_CONF_1 - GDET Configuration 1 Register */ /*! @{ */ #define GDET_GDET_CONF_1_FIELD_1_0_MASK (0x3U) #define GDET_GDET_CONF_1_FIELD_1_0_SHIFT (0U) /*! FIELD_1_0 - GDET Configuration 1 Field 1_0 */ #define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) #define GDET_GDET_CONF_1_FIELD_1_0_MASK (0x3U) #define GDET_GDET_CONF_1_FIELD_1_0_SHIFT (0U) /*! field_1_0 - GDET configuration 1 Field 1_0 */ #define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) #define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) #define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) /*! FIELD_3_2 - GDET Configuration 1 Field 3_2 */ #define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) #define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) #define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) /*! field_3_2 - GDET configuration 1 Field 3_2 */ #define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) #define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) #define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) /*! SBZ1 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) #define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) #define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) /*! sbz1 - Should be left to zero */ #define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) #define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) #define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) /*! SBZ2 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) #define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) #define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) /*! sbz2 - Should be left to zero */ #define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) #define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) #define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) /*! SBZ3 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) #define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) #define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) /*! sbz3 - Should be left to zero */ #define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) #define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) #define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) /*! FIELD_7 - GDET Configuration 1 Field 7 */ #define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) #define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) #define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) /*! field_7 - GDET configuration 1 Field 7 */ #define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) #define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) #define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) /*! FIELD_8 - GDET Configuration 1 Field 8 */ #define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) #define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) #define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) /*! field_8 - GDET configuration 1 Field 8 */ #define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) #define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) #define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) /*! SBZ4 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) #define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) #define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) /*! sbz4 - Should be left to zero */ #define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) #define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) #define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) /*! SBZ5 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) #define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) #define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) /*! sbz5 - Should be left to zero */ #define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) #define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) #define GDET_GDET_CONF_1_RFU_SHIFT (11U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) #define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) #define GDET_GDET_CONF_1_RFU_SHIFT (11U) /*! rfu - Reserved for Future Use */ #define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) /*! @} */ /*! @name GDET_ENABLE1 - GDET Enable Register */ /*! @{ */ #define GDET_GDET_ENABLE1_EN1_MASK (0x1U) #define GDET_GDET_ENABLE1_EN1_SHIFT (0U) /*! EN1 - If set, the detector will be clock gated */ #define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) #define GDET_GDET_ENABLE1_EN1_MASK (0x1U) #define GDET_GDET_ENABLE1_EN1_SHIFT (0U) /*! en1 - If set, the detector will be clock gated */ #define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) #define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) #define GDET_GDET_ENABLE1_RFU_SHIFT (1U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) #define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) #define GDET_GDET_ENABLE1_RFU_SHIFT (1U) /*! rfu - Reserved for Future Use */ #define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) /*! @} */ /*! @name GDET_CONF_2 - GDET Configuration 2 Register */ /*! @{ */ #define GDET_GDET_CONF_2_FIELD_6_0_MASK (0x7FU) #define GDET_GDET_CONF_2_FIELD_6_0_SHIFT (0U) /*! FIELD_6_0 - GDET Configuration 2 Field 6_0 */ #define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) #define GDET_GDET_CONF_2_FIELD_6_0_MASK (0x7FU) #define GDET_GDET_CONF_2_FIELD_6_0_SHIFT (0U) /*! field_6_0 - GDET configuration 2 Field 6_0 */ #define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) #define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) #define GDET_GDET_CONF_2_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) #define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) #define GDET_GDET_CONF_2_RFU1_SHIFT (7U) /*! rfu1 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) #define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) #define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) /*! FIELD_21_16 - GDET Configuration 2 Field 21_16 */ #define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) #define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) #define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) /*! field_21_16 - GDET configuration 2 Field 21_16 */ #define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) #define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) #define GDET_GDET_CONF_2_RFU2_SHIFT (22U) /*! RFU2 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) #define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) #define GDET_GDET_CONF_2_RFU2_SHIFT (22U) /*! rfu2 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) #define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) #define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) /*! FIELD_29_24 - GDET Configuration 2 Field 29_24 */ #define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) #define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) #define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) /*! field_29_24 - GDET configuration 2 Field 29_24 */ #define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) #define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) #define GDET_GDET_CONF_2_RFU3_SHIFT (30U) /*! RFU3 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) #define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) #define GDET_GDET_CONF_2_RFU3_SHIFT (30U) /*! rfu3 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) /*! @} */ /*! @name GDET_CONF_3 - GDET Configuration 3 Register */ /*! @{ */ #define GDET_GDET_CONF_3_FIELD_6_0_MASK (0x7FU) #define GDET_GDET_CONF_3_FIELD_6_0_SHIFT (0U) /*! FIELD_6_0 - GDET Configuration 3 Field 6_0 */ #define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) #define GDET_GDET_CONF_3_FIELD_6_0_MASK (0x7FU) #define GDET_GDET_CONF_3_FIELD_6_0_SHIFT (0U) /*! field_6_0 - GDET configuration 3 Field 6_0 */ #define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) #define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) #define GDET_GDET_CONF_3_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) #define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) #define GDET_GDET_CONF_3_RFU1_SHIFT (7U) /*! rfu1 - Reserved for Future Use */ #define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) /*! @} */ /*! @name GDET_CONF_4 - GDET Configuration 4 Register */ /*! @{ */ #define GDET_GDET_CONF_4_FIELD_6_0_MASK (0x7FU) #define GDET_GDET_CONF_4_FIELD_6_0_SHIFT (0U) /*! FIELD_6_0 - GDET Configuration 4 Field 6_0 */ #define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) #define GDET_GDET_CONF_4_FIELD_6_0_MASK (0x7FU) #define GDET_GDET_CONF_4_FIELD_6_0_SHIFT (0U) /*! field_6_0 - GDET configuration 4 Field 6_0 */ #define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) #define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) #define GDET_GDET_CONF_4_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) #define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) #define GDET_GDET_CONF_4_RFU1_SHIFT (7U) /*! rfu1 - Reserved for Future Use */ #define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) /*! @} */ /*! @name GDET_CONF_5 - GDET Configuration 5 Register */ /*! @{ */ #define GDET_GDET_CONF_5_FIELD_5_0_MASK (0x3FU) #define GDET_GDET_CONF_5_FIELD_5_0_SHIFT (0U) /*! FIELD_5_0 - GDET Configuration 5 Field 5_0 */ #define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) #define GDET_GDET_CONF_5_FIELD_5_0_MASK (0x3FU) #define GDET_GDET_CONF_5_FIELD_5_0_SHIFT (0U) /*! field_5_0 - GDET configuration 5 Field 5_0 */ #define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) #define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) #define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) /*! FIELD_11_6 - GDET Configuration 5 Field 11_6 */ #define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) #define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) #define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) /*! field_11_6 - GDET configuration 5 Field 11_6 */ #define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) #define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) #define GDET_GDET_CONF_5_RFU1_SHIFT (12U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) #define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) #define GDET_GDET_CONF_5_RFU1_SHIFT (12U) /*! rfu1 - Reserved for Future Use */ #define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) /*! @} */ /*! @name GDET_RESET - GDET Reset Register */ /*! @{ */ #define GDET_GDET_RESET_RFU1_MASK (0x7U) #define GDET_GDET_RESET_RFU1_SHIFT (0U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) #define GDET_GDET_RESET_RFU1_MASK (0x7U) #define GDET_GDET_RESET_RFU1_SHIFT (0U) /*! rfu1 - Reserved for Future Use */ #define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) #define GDET_GDET_RESET_SFT_RST_MASK (0x8U) #define GDET_GDET_RESET_SFT_RST_SHIFT (3U) /*! SFT_RST - Soft Reset for the Core Reset */ #define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) #define GDET_GDET_RESET_SFT_RST_MASK (0x8U) #define GDET_GDET_RESET_SFT_RST_SHIFT (3U) /*! sft_rst - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0 */ #define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) #define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) #define GDET_GDET_RESET_RFU2_SHIFT (4U) /*! RFU2 - Reserved for Future Use */ #define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) #define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) #define GDET_GDET_RESET_RFU2_SHIFT (4U) /*! rfu2 - Reserved for Future Use */ #define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) /*! @} */ /*! @name GDET_TEST - GDET Test Register */ /*! @{ */ #define GDET_GDET_TEST_SBZ_MASK (0x1U) #define GDET_GDET_TEST_SBZ_SHIFT (0U) /*! SBZ - Should Be Left to Zero */ #define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) #define GDET_GDET_TEST_SBZ_MASK (0x1U) #define GDET_GDET_TEST_SBZ_SHIFT (0U) /*! sbz - Should be left to zero */ #define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) #define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) #define GDET_GDET_TEST_RFU_SHIFT (1U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) #define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) #define GDET_GDET_TEST_RFU_SHIFT (1U) /*! rfu - Reserved for Future Use */ #define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) /*! @} */ /*! @name GDET_DLY_CTRL - GDET Delay Control Register */ /*! @{ */ #define GDET_GDET_DLY_CTRL_VOL_SEL_MASK (0x3U) #define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT (0U) /*! VOL_SEL - GDET Delay Control of the Voltage Mode */ #define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) #define GDET_GDET_DLY_CTRL_VOL_SEL_MASK (0x3U) #define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT (0U) /*! vol_sel - GDET delay control of the voltage mode. Used to select the trim code appropiate to the voltage mode. */ #define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) /*! SW_VOL_CTRL - Select the Control of the Trim Code to the Delay Line */ #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) /*! sw_vol_ctrl - Select the control of the trim code to the delay line via HW port (0) or SW SFR (1) */ #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) #define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) #define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) #define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) #define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) /*! rfu - Reserved for Future Use */ #define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) /*! @} */ /*! * @} */ /* end of group GDET_Register_Masks */ /* GDET - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral GDET0 base address */ #define GDET0_BASE (0x50024000u) /** Peripheral GDET0 base address */ #define GDET0_BASE_NS (0x40024000u) /** Peripheral GDET0 base pointer */ #define GDET0 ((GDET_Type *)GDET0_BASE) /** Peripheral GDET0 base pointer */ #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) /** Peripheral GDET1 base address */ #define GDET1_BASE (0x50025000u) /** Peripheral GDET1 base address */ #define GDET1_BASE_NS (0x40025000u) /** Peripheral GDET1 base pointer */ #define GDET1 ((GDET_Type *)GDET1_BASE) /** Peripheral GDET1 base pointer */ #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) /** Array initializer of GDET peripheral base addresses */ #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } /** Array initializer of GDET peripheral base pointers */ #define GDET_BASE_PTRS { GDET0, GDET1 } /** Array initializer of GDET peripheral base addresses */ #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } /** Array initializer of GDET peripheral base pointers */ #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } #else /** Peripheral GDET0 base address */ #define GDET0_BASE (0x40024000u) /** Peripheral GDET0 base pointer */ #define GDET0 ((GDET_Type *)GDET0_BASE) /** Peripheral GDET1 base address */ #define GDET1_BASE (0x40025000u) /** Peripheral GDET1 base pointer */ #define GDET1 ((GDET_Type *)GDET1_BASE) /** Array initializer of GDET peripheral base addresses */ #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } /** Array initializer of GDET peripheral base pointers */ #define GDET_BASE_PTRS { GDET0, GDET1 } #endif /*! * @} */ /* end of group GDET_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer * @{ */ /** GPIO - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t LOCK; /**< Lock, offset: 0xC */ __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ uint8_t RESERVED_1[32]; __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ __O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ __O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ __O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ uint8_t RESERVED_2[4]; __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ __O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ __O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ uint8_t RESERVED_3[24]; __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ } GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define GPIO_VERID_FEATURE_MASK (0xFFFFU) #define GPIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Basic implementation * 0b0000000000000001..Protection registers implemented */ #define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) #define GPIO_VERID_MINOR_MASK (0xFF0000U) #define GPIO_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define GPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK) #define GPIO_VERID_MAJOR_MASK (0xFF000000U) #define GPIO_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define GPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define GPIO_PARAM_IRQNUM_MASK (0xFU) #define GPIO_PARAM_IRQNUM_SHIFT (0U) /*! IRQNUM - Interrupt Number */ #define GPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK) /*! @} */ /*! @name LOCK - Lock */ /*! @{ */ #define GPIO_LOCK_PCNS_MASK (0x1U) #define GPIO_LOCK_PCNS_SHIFT (0U) /*! PCNS - Lock PCNS * 0b0..Writable in Secure-Privilege state * 0b1..Not writable until the next reset */ #define GPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK) #define GPIO_LOCK_ICNS_MASK (0x2U) #define GPIO_LOCK_ICNS_SHIFT (1U) /*! ICNS - Lock ICNS * 0b0..Writable in Secure-Privilege state * 0b1..Not writable until the next reset */ #define GPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK) #define GPIO_LOCK_PCNP_MASK (0x4U) #define GPIO_LOCK_PCNP_SHIFT (2U) /*! PCNP - Lock PCNP * 0b0..Writable in Secure-Privilege state * 0b1..Not writable until the next reset */ #define GPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK) #define GPIO_LOCK_ICNP_MASK (0x8U) #define GPIO_LOCK_ICNP_SHIFT (3U) /*! ICNP - Lock ICNP * 0b0..Writable in Secure-Privilege state * 0b1..Not writable until the next reset */ #define GPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK) /*! @} */ /*! @name PCNS - Pin Control Nonsecure */ /*! @{ */ #define GPIO_PCNS_NSE0_MASK (0x1U) #define GPIO_PCNS_NSE0_SHIFT (0U) /*! NSE0 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK) #define GPIO_PCNS_NSE1_MASK (0x2U) #define GPIO_PCNS_NSE1_SHIFT (1U) /*! NSE1 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK) #define GPIO_PCNS_NSE2_MASK (0x4U) #define GPIO_PCNS_NSE2_SHIFT (2U) /*! NSE2 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK) #define GPIO_PCNS_NSE3_MASK (0x8U) #define GPIO_PCNS_NSE3_SHIFT (3U) /*! NSE3 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK) #define GPIO_PCNS_NSE4_MASK (0x10U) #define GPIO_PCNS_NSE4_SHIFT (4U) /*! NSE4 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK) #define GPIO_PCNS_NSE5_MASK (0x20U) #define GPIO_PCNS_NSE5_SHIFT (5U) /*! NSE5 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK) #define GPIO_PCNS_NSE6_MASK (0x40U) #define GPIO_PCNS_NSE6_SHIFT (6U) /*! NSE6 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK) #define GPIO_PCNS_NSE7_MASK (0x80U) #define GPIO_PCNS_NSE7_SHIFT (7U) /*! NSE7 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK) #define GPIO_PCNS_NSE8_MASK (0x100U) #define GPIO_PCNS_NSE8_SHIFT (8U) /*! NSE8 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK) #define GPIO_PCNS_NSE9_MASK (0x200U) #define GPIO_PCNS_NSE9_SHIFT (9U) /*! NSE9 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK) #define GPIO_PCNS_NSE10_MASK (0x400U) #define GPIO_PCNS_NSE10_SHIFT (10U) /*! NSE10 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK) #define GPIO_PCNS_NSE11_MASK (0x800U) #define GPIO_PCNS_NSE11_SHIFT (11U) /*! NSE11 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK) #define GPIO_PCNS_NSE12_MASK (0x1000U) #define GPIO_PCNS_NSE12_SHIFT (12U) /*! NSE12 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK) #define GPIO_PCNS_NSE13_MASK (0x2000U) #define GPIO_PCNS_NSE13_SHIFT (13U) /*! NSE13 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK) #define GPIO_PCNS_NSE14_MASK (0x4000U) #define GPIO_PCNS_NSE14_SHIFT (14U) /*! NSE14 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK) #define GPIO_PCNS_NSE15_MASK (0x8000U) #define GPIO_PCNS_NSE15_SHIFT (15U) /*! NSE15 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK) #define GPIO_PCNS_NSE16_MASK (0x10000U) #define GPIO_PCNS_NSE16_SHIFT (16U) /*! NSE16 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK) #define GPIO_PCNS_NSE17_MASK (0x20000U) #define GPIO_PCNS_NSE17_SHIFT (17U) /*! NSE17 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK) #define GPIO_PCNS_NSE18_MASK (0x40000U) #define GPIO_PCNS_NSE18_SHIFT (18U) /*! NSE18 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK) #define GPIO_PCNS_NSE19_MASK (0x80000U) #define GPIO_PCNS_NSE19_SHIFT (19U) /*! NSE19 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK) #define GPIO_PCNS_NSE20_MASK (0x100000U) #define GPIO_PCNS_NSE20_SHIFT (20U) /*! NSE20 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK) #define GPIO_PCNS_NSE21_MASK (0x200000U) #define GPIO_PCNS_NSE21_SHIFT (21U) /*! NSE21 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK) #define GPIO_PCNS_NSE22_MASK (0x400000U) #define GPIO_PCNS_NSE22_SHIFT (22U) /*! NSE22 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK) #define GPIO_PCNS_NSE23_MASK (0x800000U) #define GPIO_PCNS_NSE23_SHIFT (23U) /*! NSE23 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK) #define GPIO_PCNS_NSE24_MASK (0x1000000U) #define GPIO_PCNS_NSE24_SHIFT (24U) /*! NSE24 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK) #define GPIO_PCNS_NSE25_MASK (0x2000000U) #define GPIO_PCNS_NSE25_SHIFT (25U) /*! NSE25 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK) #define GPIO_PCNS_NSE26_MASK (0x4000000U) #define GPIO_PCNS_NSE26_SHIFT (26U) /*! NSE26 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK) #define GPIO_PCNS_NSE27_MASK (0x8000000U) #define GPIO_PCNS_NSE27_SHIFT (27U) /*! NSE27 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK) #define GPIO_PCNS_NSE28_MASK (0x10000000U) #define GPIO_PCNS_NSE28_SHIFT (28U) /*! NSE28 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK) #define GPIO_PCNS_NSE29_MASK (0x20000000U) #define GPIO_PCNS_NSE29_SHIFT (29U) /*! NSE29 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK) #define GPIO_PCNS_NSE30_MASK (0x40000000U) #define GPIO_PCNS_NSE30_SHIFT (30U) /*! NSE30 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK) #define GPIO_PCNS_NSE31_MASK (0x80000000U) #define GPIO_PCNS_NSE31_SHIFT (31U) /*! NSE31 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK) /*! @} */ /*! @name ICNS - Interrupt Control Nonsecure */ /*! @{ */ #define GPIO_ICNS_NSE0_MASK (0x1U) #define GPIO_ICNS_NSE0_SHIFT (0U) /*! NSE0 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK) #define GPIO_ICNS_NSE1_MASK (0x2U) #define GPIO_ICNS_NSE1_SHIFT (1U) /*! NSE1 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define GPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK) /*! @} */ /*! @name PCNP - Pin Control Nonprivilege */ /*! @{ */ #define GPIO_PCNP_NPE0_MASK (0x1U) #define GPIO_PCNP_NPE0_SHIFT (0U) /*! NPE0 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK) #define GPIO_PCNP_NPE1_MASK (0x2U) #define GPIO_PCNP_NPE1_SHIFT (1U) /*! NPE1 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK) #define GPIO_PCNP_NPE2_MASK (0x4U) #define GPIO_PCNP_NPE2_SHIFT (2U) /*! NPE2 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK) #define GPIO_PCNP_NPE3_MASK (0x8U) #define GPIO_PCNP_NPE3_SHIFT (3U) /*! NPE3 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK) #define GPIO_PCNP_NPE4_MASK (0x10U) #define GPIO_PCNP_NPE4_SHIFT (4U) /*! NPE4 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK) #define GPIO_PCNP_NPE5_MASK (0x20U) #define GPIO_PCNP_NPE5_SHIFT (5U) /*! NPE5 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK) #define GPIO_PCNP_NPE6_MASK (0x40U) #define GPIO_PCNP_NPE6_SHIFT (6U) /*! NPE6 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK) #define GPIO_PCNP_NPE7_MASK (0x80U) #define GPIO_PCNP_NPE7_SHIFT (7U) /*! NPE7 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK) #define GPIO_PCNP_NPE8_MASK (0x100U) #define GPIO_PCNP_NPE8_SHIFT (8U) /*! NPE8 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK) #define GPIO_PCNP_NPE9_MASK (0x200U) #define GPIO_PCNP_NPE9_SHIFT (9U) /*! NPE9 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK) #define GPIO_PCNP_NPE10_MASK (0x400U) #define GPIO_PCNP_NPE10_SHIFT (10U) /*! NPE10 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK) #define GPIO_PCNP_NPE11_MASK (0x800U) #define GPIO_PCNP_NPE11_SHIFT (11U) /*! NPE11 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK) #define GPIO_PCNP_NPE12_MASK (0x1000U) #define GPIO_PCNP_NPE12_SHIFT (12U) /*! NPE12 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK) #define GPIO_PCNP_NPE13_MASK (0x2000U) #define GPIO_PCNP_NPE13_SHIFT (13U) /*! NPE13 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK) #define GPIO_PCNP_NPE14_MASK (0x4000U) #define GPIO_PCNP_NPE14_SHIFT (14U) /*! NPE14 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK) #define GPIO_PCNP_NPE15_MASK (0x8000U) #define GPIO_PCNP_NPE15_SHIFT (15U) /*! NPE15 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK) #define GPIO_PCNP_NPE16_MASK (0x10000U) #define GPIO_PCNP_NPE16_SHIFT (16U) /*! NPE16 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK) #define GPIO_PCNP_NPE17_MASK (0x20000U) #define GPIO_PCNP_NPE17_SHIFT (17U) /*! NPE17 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK) #define GPIO_PCNP_NPE18_MASK (0x40000U) #define GPIO_PCNP_NPE18_SHIFT (18U) /*! NPE18 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK) #define GPIO_PCNP_NPE19_MASK (0x80000U) #define GPIO_PCNP_NPE19_SHIFT (19U) /*! NPE19 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK) #define GPIO_PCNP_NPE20_MASK (0x100000U) #define GPIO_PCNP_NPE20_SHIFT (20U) /*! NPE20 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK) #define GPIO_PCNP_NPE21_MASK (0x200000U) #define GPIO_PCNP_NPE21_SHIFT (21U) /*! NPE21 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK) #define GPIO_PCNP_NPE22_MASK (0x400000U) #define GPIO_PCNP_NPE22_SHIFT (22U) /*! NPE22 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK) #define GPIO_PCNP_NPE23_MASK (0x800000U) #define GPIO_PCNP_NPE23_SHIFT (23U) /*! NPE23 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK) #define GPIO_PCNP_NPE24_MASK (0x1000000U) #define GPIO_PCNP_NPE24_SHIFT (24U) /*! NPE24 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK) #define GPIO_PCNP_NPE25_MASK (0x2000000U) #define GPIO_PCNP_NPE25_SHIFT (25U) /*! NPE25 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK) #define GPIO_PCNP_NPE26_MASK (0x4000000U) #define GPIO_PCNP_NPE26_SHIFT (26U) /*! NPE26 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK) #define GPIO_PCNP_NPE27_MASK (0x8000000U) #define GPIO_PCNP_NPE27_SHIFT (27U) /*! NPE27 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK) #define GPIO_PCNP_NPE28_MASK (0x10000000U) #define GPIO_PCNP_NPE28_SHIFT (28U) /*! NPE28 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK) #define GPIO_PCNP_NPE29_MASK (0x20000000U) #define GPIO_PCNP_NPE29_SHIFT (29U) /*! NPE29 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK) #define GPIO_PCNP_NPE30_MASK (0x40000000U) #define GPIO_PCNP_NPE30_SHIFT (30U) /*! NPE30 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK) #define GPIO_PCNP_NPE31_MASK (0x80000000U) #define GPIO_PCNP_NPE31_SHIFT (31U) /*! NPE31 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK) /*! @} */ /*! @name ICNP - Interrupt Control Nonprivilege */ /*! @{ */ #define GPIO_ICNP_NPE0_MASK (0x1U) #define GPIO_ICNP_NPE0_SHIFT (0U) /*! NPE0 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK) #define GPIO_ICNP_NPE1_MASK (0x2U) #define GPIO_ICNP_NPE1_SHIFT (1U) /*! NPE1 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define GPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK) /*! @} */ /*! @name PDOR - Port Data Output */ /*! @{ */ #define GPIO_PDOR_PDO0_MASK (0x1U) #define GPIO_PDOR_PDO0_SHIFT (0U) /*! PDO0 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) #define GPIO_PDOR_PDO1_MASK (0x2U) #define GPIO_PDOR_PDO1_SHIFT (1U) /*! PDO1 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) #define GPIO_PDOR_PDO2_MASK (0x4U) #define GPIO_PDOR_PDO2_SHIFT (2U) /*! PDO2 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) #define GPIO_PDOR_PDO3_MASK (0x8U) #define GPIO_PDOR_PDO3_SHIFT (3U) /*! PDO3 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) #define GPIO_PDOR_PDO4_MASK (0x10U) #define GPIO_PDOR_PDO4_SHIFT (4U) /*! PDO4 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) #define GPIO_PDOR_PDO5_MASK (0x20U) #define GPIO_PDOR_PDO5_SHIFT (5U) /*! PDO5 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) #define GPIO_PDOR_PDO6_MASK (0x40U) #define GPIO_PDOR_PDO6_SHIFT (6U) /*! PDO6 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) #define GPIO_PDOR_PDO7_MASK (0x80U) #define GPIO_PDOR_PDO7_SHIFT (7U) /*! PDO7 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) #define GPIO_PDOR_PDO8_MASK (0x100U) #define GPIO_PDOR_PDO8_SHIFT (8U) /*! PDO8 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) #define GPIO_PDOR_PDO9_MASK (0x200U) #define GPIO_PDOR_PDO9_SHIFT (9U) /*! PDO9 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) #define GPIO_PDOR_PDO10_MASK (0x400U) #define GPIO_PDOR_PDO10_SHIFT (10U) /*! PDO10 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) #define GPIO_PDOR_PDO11_MASK (0x800U) #define GPIO_PDOR_PDO11_SHIFT (11U) /*! PDO11 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) #define GPIO_PDOR_PDO12_MASK (0x1000U) #define GPIO_PDOR_PDO12_SHIFT (12U) /*! PDO12 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) #define GPIO_PDOR_PDO13_MASK (0x2000U) #define GPIO_PDOR_PDO13_SHIFT (13U) /*! PDO13 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) #define GPIO_PDOR_PDO14_MASK (0x4000U) #define GPIO_PDOR_PDO14_SHIFT (14U) /*! PDO14 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) #define GPIO_PDOR_PDO15_MASK (0x8000U) #define GPIO_PDOR_PDO15_SHIFT (15U) /*! PDO15 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) #define GPIO_PDOR_PDO16_MASK (0x10000U) #define GPIO_PDOR_PDO16_SHIFT (16U) /*! PDO16 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) #define GPIO_PDOR_PDO17_MASK (0x20000U) #define GPIO_PDOR_PDO17_SHIFT (17U) /*! PDO17 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) #define GPIO_PDOR_PDO18_MASK (0x40000U) #define GPIO_PDOR_PDO18_SHIFT (18U) /*! PDO18 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) #define GPIO_PDOR_PDO19_MASK (0x80000U) #define GPIO_PDOR_PDO19_SHIFT (19U) /*! PDO19 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) #define GPIO_PDOR_PDO20_MASK (0x100000U) #define GPIO_PDOR_PDO20_SHIFT (20U) /*! PDO20 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) #define GPIO_PDOR_PDO21_MASK (0x200000U) #define GPIO_PDOR_PDO21_SHIFT (21U) /*! PDO21 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) #define GPIO_PDOR_PDO22_MASK (0x400000U) #define GPIO_PDOR_PDO22_SHIFT (22U) /*! PDO22 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) #define GPIO_PDOR_PDO23_MASK (0x800000U) #define GPIO_PDOR_PDO23_SHIFT (23U) /*! PDO23 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) #define GPIO_PDOR_PDO24_MASK (0x1000000U) #define GPIO_PDOR_PDO24_SHIFT (24U) /*! PDO24 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) #define GPIO_PDOR_PDO25_MASK (0x2000000U) #define GPIO_PDOR_PDO25_SHIFT (25U) /*! PDO25 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) #define GPIO_PDOR_PDO26_MASK (0x4000000U) #define GPIO_PDOR_PDO26_SHIFT (26U) /*! PDO26 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) #define GPIO_PDOR_PDO27_MASK (0x8000000U) #define GPIO_PDOR_PDO27_SHIFT (27U) /*! PDO27 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) #define GPIO_PDOR_PDO28_MASK (0x10000000U) #define GPIO_PDOR_PDO28_SHIFT (28U) /*! PDO28 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) #define GPIO_PDOR_PDO29_MASK (0x20000000U) #define GPIO_PDOR_PDO29_SHIFT (29U) /*! PDO29 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) #define GPIO_PDOR_PDO30_MASK (0x40000000U) #define GPIO_PDOR_PDO30_SHIFT (30U) /*! PDO30 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) #define GPIO_PDOR_PDO31_MASK (0x80000000U) #define GPIO_PDOR_PDO31_SHIFT (31U) /*! PDO31 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) /*! @} */ /*! @name PSOR - Port Set Output */ /*! @{ */ #define GPIO_PSOR_PTSO0_MASK (0x1U) #define GPIO_PSOR_PTSO0_SHIFT (0U) /*! PTSO0 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) #define GPIO_PSOR_PTSO1_MASK (0x2U) #define GPIO_PSOR_PTSO1_SHIFT (1U) /*! PTSO1 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) #define GPIO_PSOR_PTSO2_MASK (0x4U) #define GPIO_PSOR_PTSO2_SHIFT (2U) /*! PTSO2 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) #define GPIO_PSOR_PTSO3_MASK (0x8U) #define GPIO_PSOR_PTSO3_SHIFT (3U) /*! PTSO3 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) #define GPIO_PSOR_PTSO4_MASK (0x10U) #define GPIO_PSOR_PTSO4_SHIFT (4U) /*! PTSO4 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) #define GPIO_PSOR_PTSO5_MASK (0x20U) #define GPIO_PSOR_PTSO5_SHIFT (5U) /*! PTSO5 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) #define GPIO_PSOR_PTSO6_MASK (0x40U) #define GPIO_PSOR_PTSO6_SHIFT (6U) /*! PTSO6 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) #define GPIO_PSOR_PTSO7_MASK (0x80U) #define GPIO_PSOR_PTSO7_SHIFT (7U) /*! PTSO7 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) #define GPIO_PSOR_PTSO8_MASK (0x100U) #define GPIO_PSOR_PTSO8_SHIFT (8U) /*! PTSO8 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) #define GPIO_PSOR_PTSO9_MASK (0x200U) #define GPIO_PSOR_PTSO9_SHIFT (9U) /*! PTSO9 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) #define GPIO_PSOR_PTSO10_MASK (0x400U) #define GPIO_PSOR_PTSO10_SHIFT (10U) /*! PTSO10 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) #define GPIO_PSOR_PTSO11_MASK (0x800U) #define GPIO_PSOR_PTSO11_SHIFT (11U) /*! PTSO11 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) #define GPIO_PSOR_PTSO12_MASK (0x1000U) #define GPIO_PSOR_PTSO12_SHIFT (12U) /*! PTSO12 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) #define GPIO_PSOR_PTSO13_MASK (0x2000U) #define GPIO_PSOR_PTSO13_SHIFT (13U) /*! PTSO13 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) #define GPIO_PSOR_PTSO14_MASK (0x4000U) #define GPIO_PSOR_PTSO14_SHIFT (14U) /*! PTSO14 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) #define GPIO_PSOR_PTSO15_MASK (0x8000U) #define GPIO_PSOR_PTSO15_SHIFT (15U) /*! PTSO15 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) #define GPIO_PSOR_PTSO16_MASK (0x10000U) #define GPIO_PSOR_PTSO16_SHIFT (16U) /*! PTSO16 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) #define GPIO_PSOR_PTSO17_MASK (0x20000U) #define GPIO_PSOR_PTSO17_SHIFT (17U) /*! PTSO17 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) #define GPIO_PSOR_PTSO18_MASK (0x40000U) #define GPIO_PSOR_PTSO18_SHIFT (18U) /*! PTSO18 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) #define GPIO_PSOR_PTSO19_MASK (0x80000U) #define GPIO_PSOR_PTSO19_SHIFT (19U) /*! PTSO19 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) #define GPIO_PSOR_PTSO20_MASK (0x100000U) #define GPIO_PSOR_PTSO20_SHIFT (20U) /*! PTSO20 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) #define GPIO_PSOR_PTSO21_MASK (0x200000U) #define GPIO_PSOR_PTSO21_SHIFT (21U) /*! PTSO21 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) #define GPIO_PSOR_PTSO22_MASK (0x400000U) #define GPIO_PSOR_PTSO22_SHIFT (22U) /*! PTSO22 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) #define GPIO_PSOR_PTSO23_MASK (0x800000U) #define GPIO_PSOR_PTSO23_SHIFT (23U) /*! PTSO23 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) #define GPIO_PSOR_PTSO24_MASK (0x1000000U) #define GPIO_PSOR_PTSO24_SHIFT (24U) /*! PTSO24 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) #define GPIO_PSOR_PTSO25_MASK (0x2000000U) #define GPIO_PSOR_PTSO25_SHIFT (25U) /*! PTSO25 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) #define GPIO_PSOR_PTSO26_MASK (0x4000000U) #define GPIO_PSOR_PTSO26_SHIFT (26U) /*! PTSO26 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) #define GPIO_PSOR_PTSO27_MASK (0x8000000U) #define GPIO_PSOR_PTSO27_SHIFT (27U) /*! PTSO27 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) #define GPIO_PSOR_PTSO28_MASK (0x10000000U) #define GPIO_PSOR_PTSO28_SHIFT (28U) /*! PTSO28 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) #define GPIO_PSOR_PTSO29_MASK (0x20000000U) #define GPIO_PSOR_PTSO29_SHIFT (29U) /*! PTSO29 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) #define GPIO_PSOR_PTSO30_MASK (0x40000000U) #define GPIO_PSOR_PTSO30_SHIFT (30U) /*! PTSO30 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) #define GPIO_PSOR_PTSO31_MASK (0x80000000U) #define GPIO_PSOR_PTSO31_SHIFT (31U) /*! PTSO31 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) /*! @} */ /*! @name PCOR - Port Clear Output */ /*! @{ */ #define GPIO_PCOR_PTCO0_MASK (0x1U) #define GPIO_PCOR_PTCO0_SHIFT (0U) /*! PTCO0 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) #define GPIO_PCOR_PTCO1_MASK (0x2U) #define GPIO_PCOR_PTCO1_SHIFT (1U) /*! PTCO1 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) #define GPIO_PCOR_PTCO2_MASK (0x4U) #define GPIO_PCOR_PTCO2_SHIFT (2U) /*! PTCO2 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) #define GPIO_PCOR_PTCO3_MASK (0x8U) #define GPIO_PCOR_PTCO3_SHIFT (3U) /*! PTCO3 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) #define GPIO_PCOR_PTCO4_MASK (0x10U) #define GPIO_PCOR_PTCO4_SHIFT (4U) /*! PTCO4 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) #define GPIO_PCOR_PTCO5_MASK (0x20U) #define GPIO_PCOR_PTCO5_SHIFT (5U) /*! PTCO5 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) #define GPIO_PCOR_PTCO6_MASK (0x40U) #define GPIO_PCOR_PTCO6_SHIFT (6U) /*! PTCO6 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) #define GPIO_PCOR_PTCO7_MASK (0x80U) #define GPIO_PCOR_PTCO7_SHIFT (7U) /*! PTCO7 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) #define GPIO_PCOR_PTCO8_MASK (0x100U) #define GPIO_PCOR_PTCO8_SHIFT (8U) /*! PTCO8 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) #define GPIO_PCOR_PTCO9_MASK (0x200U) #define GPIO_PCOR_PTCO9_SHIFT (9U) /*! PTCO9 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) #define GPIO_PCOR_PTCO10_MASK (0x400U) #define GPIO_PCOR_PTCO10_SHIFT (10U) /*! PTCO10 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) #define GPIO_PCOR_PTCO11_MASK (0x800U) #define GPIO_PCOR_PTCO11_SHIFT (11U) /*! PTCO11 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) #define GPIO_PCOR_PTCO12_MASK (0x1000U) #define GPIO_PCOR_PTCO12_SHIFT (12U) /*! PTCO12 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) #define GPIO_PCOR_PTCO13_MASK (0x2000U) #define GPIO_PCOR_PTCO13_SHIFT (13U) /*! PTCO13 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) #define GPIO_PCOR_PTCO14_MASK (0x4000U) #define GPIO_PCOR_PTCO14_SHIFT (14U) /*! PTCO14 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) #define GPIO_PCOR_PTCO15_MASK (0x8000U) #define GPIO_PCOR_PTCO15_SHIFT (15U) /*! PTCO15 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) #define GPIO_PCOR_PTCO16_MASK (0x10000U) #define GPIO_PCOR_PTCO16_SHIFT (16U) /*! PTCO16 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) #define GPIO_PCOR_PTCO17_MASK (0x20000U) #define GPIO_PCOR_PTCO17_SHIFT (17U) /*! PTCO17 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) #define GPIO_PCOR_PTCO18_MASK (0x40000U) #define GPIO_PCOR_PTCO18_SHIFT (18U) /*! PTCO18 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) #define GPIO_PCOR_PTCO19_MASK (0x80000U) #define GPIO_PCOR_PTCO19_SHIFT (19U) /*! PTCO19 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) #define GPIO_PCOR_PTCO20_MASK (0x100000U) #define GPIO_PCOR_PTCO20_SHIFT (20U) /*! PTCO20 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) #define GPIO_PCOR_PTCO21_MASK (0x200000U) #define GPIO_PCOR_PTCO21_SHIFT (21U) /*! PTCO21 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) #define GPIO_PCOR_PTCO22_MASK (0x400000U) #define GPIO_PCOR_PTCO22_SHIFT (22U) /*! PTCO22 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) #define GPIO_PCOR_PTCO23_MASK (0x800000U) #define GPIO_PCOR_PTCO23_SHIFT (23U) /*! PTCO23 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) #define GPIO_PCOR_PTCO24_MASK (0x1000000U) #define GPIO_PCOR_PTCO24_SHIFT (24U) /*! PTCO24 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) #define GPIO_PCOR_PTCO25_MASK (0x2000000U) #define GPIO_PCOR_PTCO25_SHIFT (25U) /*! PTCO25 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) #define GPIO_PCOR_PTCO26_MASK (0x4000000U) #define GPIO_PCOR_PTCO26_SHIFT (26U) /*! PTCO26 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) #define GPIO_PCOR_PTCO27_MASK (0x8000000U) #define GPIO_PCOR_PTCO27_SHIFT (27U) /*! PTCO27 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) #define GPIO_PCOR_PTCO28_MASK (0x10000000U) #define GPIO_PCOR_PTCO28_SHIFT (28U) /*! PTCO28 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) #define GPIO_PCOR_PTCO29_MASK (0x20000000U) #define GPIO_PCOR_PTCO29_SHIFT (29U) /*! PTCO29 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) #define GPIO_PCOR_PTCO30_MASK (0x40000000U) #define GPIO_PCOR_PTCO30_SHIFT (30U) /*! PTCO30 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) #define GPIO_PCOR_PTCO31_MASK (0x80000000U) #define GPIO_PCOR_PTCO31_SHIFT (31U) /*! PTCO31 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) /*! @} */ /*! @name PTOR - Port Toggle Output */ /*! @{ */ #define GPIO_PTOR_PTTO0_MASK (0x1U) #define GPIO_PTOR_PTTO0_SHIFT (0U) /*! PTTO0 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) #define GPIO_PTOR_PTTO1_MASK (0x2U) #define GPIO_PTOR_PTTO1_SHIFT (1U) /*! PTTO1 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) #define GPIO_PTOR_PTTO2_MASK (0x4U) #define GPIO_PTOR_PTTO2_SHIFT (2U) /*! PTTO2 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) #define GPIO_PTOR_PTTO3_MASK (0x8U) #define GPIO_PTOR_PTTO3_SHIFT (3U) /*! PTTO3 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) #define GPIO_PTOR_PTTO4_MASK (0x10U) #define GPIO_PTOR_PTTO4_SHIFT (4U) /*! PTTO4 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) #define GPIO_PTOR_PTTO5_MASK (0x20U) #define GPIO_PTOR_PTTO5_SHIFT (5U) /*! PTTO5 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) #define GPIO_PTOR_PTTO6_MASK (0x40U) #define GPIO_PTOR_PTTO6_SHIFT (6U) /*! PTTO6 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) #define GPIO_PTOR_PTTO7_MASK (0x80U) #define GPIO_PTOR_PTTO7_SHIFT (7U) /*! PTTO7 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) #define GPIO_PTOR_PTTO8_MASK (0x100U) #define GPIO_PTOR_PTTO8_SHIFT (8U) /*! PTTO8 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) #define GPIO_PTOR_PTTO9_MASK (0x200U) #define GPIO_PTOR_PTTO9_SHIFT (9U) /*! PTTO9 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) #define GPIO_PTOR_PTTO10_MASK (0x400U) #define GPIO_PTOR_PTTO10_SHIFT (10U) /*! PTTO10 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) #define GPIO_PTOR_PTTO11_MASK (0x800U) #define GPIO_PTOR_PTTO11_SHIFT (11U) /*! PTTO11 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) #define GPIO_PTOR_PTTO12_MASK (0x1000U) #define GPIO_PTOR_PTTO12_SHIFT (12U) /*! PTTO12 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) #define GPIO_PTOR_PTTO13_MASK (0x2000U) #define GPIO_PTOR_PTTO13_SHIFT (13U) /*! PTTO13 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) #define GPIO_PTOR_PTTO14_MASK (0x4000U) #define GPIO_PTOR_PTTO14_SHIFT (14U) /*! PTTO14 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) #define GPIO_PTOR_PTTO15_MASK (0x8000U) #define GPIO_PTOR_PTTO15_SHIFT (15U) /*! PTTO15 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) #define GPIO_PTOR_PTTO16_MASK (0x10000U) #define GPIO_PTOR_PTTO16_SHIFT (16U) /*! PTTO16 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) #define GPIO_PTOR_PTTO17_MASK (0x20000U) #define GPIO_PTOR_PTTO17_SHIFT (17U) /*! PTTO17 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) #define GPIO_PTOR_PTTO18_MASK (0x40000U) #define GPIO_PTOR_PTTO18_SHIFT (18U) /*! PTTO18 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) #define GPIO_PTOR_PTTO19_MASK (0x80000U) #define GPIO_PTOR_PTTO19_SHIFT (19U) /*! PTTO19 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) #define GPIO_PTOR_PTTO20_MASK (0x100000U) #define GPIO_PTOR_PTTO20_SHIFT (20U) /*! PTTO20 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) #define GPIO_PTOR_PTTO21_MASK (0x200000U) #define GPIO_PTOR_PTTO21_SHIFT (21U) /*! PTTO21 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) #define GPIO_PTOR_PTTO22_MASK (0x400000U) #define GPIO_PTOR_PTTO22_SHIFT (22U) /*! PTTO22 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) #define GPIO_PTOR_PTTO23_MASK (0x800000U) #define GPIO_PTOR_PTTO23_SHIFT (23U) /*! PTTO23 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) #define GPIO_PTOR_PTTO24_MASK (0x1000000U) #define GPIO_PTOR_PTTO24_SHIFT (24U) /*! PTTO24 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) #define GPIO_PTOR_PTTO25_MASK (0x2000000U) #define GPIO_PTOR_PTTO25_SHIFT (25U) /*! PTTO25 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) #define GPIO_PTOR_PTTO26_MASK (0x4000000U) #define GPIO_PTOR_PTTO26_SHIFT (26U) /*! PTTO26 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) #define GPIO_PTOR_PTTO27_MASK (0x8000000U) #define GPIO_PTOR_PTTO27_SHIFT (27U) /*! PTTO27 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) #define GPIO_PTOR_PTTO28_MASK (0x10000000U) #define GPIO_PTOR_PTTO28_SHIFT (28U) /*! PTTO28 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) #define GPIO_PTOR_PTTO29_MASK (0x20000000U) #define GPIO_PTOR_PTTO29_SHIFT (29U) /*! PTTO29 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) #define GPIO_PTOR_PTTO30_MASK (0x40000000U) #define GPIO_PTOR_PTTO30_SHIFT (30U) /*! PTTO30 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) #define GPIO_PTOR_PTTO31_MASK (0x80000000U) #define GPIO_PTOR_PTTO31_SHIFT (31U) /*! PTTO31 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) /*! @} */ /*! @name PDIR - Port Data Input */ /*! @{ */ #define GPIO_PDIR_PDI0_MASK (0x1U) #define GPIO_PDIR_PDI0_SHIFT (0U) /*! PDI0 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) #define GPIO_PDIR_PDI1_MASK (0x2U) #define GPIO_PDIR_PDI1_SHIFT (1U) /*! PDI1 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) #define GPIO_PDIR_PDI2_MASK (0x4U) #define GPIO_PDIR_PDI2_SHIFT (2U) /*! PDI2 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) #define GPIO_PDIR_PDI3_MASK (0x8U) #define GPIO_PDIR_PDI3_SHIFT (3U) /*! PDI3 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) #define GPIO_PDIR_PDI4_MASK (0x10U) #define GPIO_PDIR_PDI4_SHIFT (4U) /*! PDI4 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) #define GPIO_PDIR_PDI5_MASK (0x20U) #define GPIO_PDIR_PDI5_SHIFT (5U) /*! PDI5 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) #define GPIO_PDIR_PDI6_MASK (0x40U) #define GPIO_PDIR_PDI6_SHIFT (6U) /*! PDI6 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) #define GPIO_PDIR_PDI7_MASK (0x80U) #define GPIO_PDIR_PDI7_SHIFT (7U) /*! PDI7 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) #define GPIO_PDIR_PDI8_MASK (0x100U) #define GPIO_PDIR_PDI8_SHIFT (8U) /*! PDI8 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) #define GPIO_PDIR_PDI9_MASK (0x200U) #define GPIO_PDIR_PDI9_SHIFT (9U) /*! PDI9 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) #define GPIO_PDIR_PDI10_MASK (0x400U) #define GPIO_PDIR_PDI10_SHIFT (10U) /*! PDI10 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) #define GPIO_PDIR_PDI11_MASK (0x800U) #define GPIO_PDIR_PDI11_SHIFT (11U) /*! PDI11 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) #define GPIO_PDIR_PDI12_MASK (0x1000U) #define GPIO_PDIR_PDI12_SHIFT (12U) /*! PDI12 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) #define GPIO_PDIR_PDI13_MASK (0x2000U) #define GPIO_PDIR_PDI13_SHIFT (13U) /*! PDI13 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) #define GPIO_PDIR_PDI14_MASK (0x4000U) #define GPIO_PDIR_PDI14_SHIFT (14U) /*! PDI14 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) #define GPIO_PDIR_PDI15_MASK (0x8000U) #define GPIO_PDIR_PDI15_SHIFT (15U) /*! PDI15 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) #define GPIO_PDIR_PDI16_MASK (0x10000U) #define GPIO_PDIR_PDI16_SHIFT (16U) /*! PDI16 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) #define GPIO_PDIR_PDI17_MASK (0x20000U) #define GPIO_PDIR_PDI17_SHIFT (17U) /*! PDI17 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) #define GPIO_PDIR_PDI18_MASK (0x40000U) #define GPIO_PDIR_PDI18_SHIFT (18U) /*! PDI18 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) #define GPIO_PDIR_PDI19_MASK (0x80000U) #define GPIO_PDIR_PDI19_SHIFT (19U) /*! PDI19 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) #define GPIO_PDIR_PDI20_MASK (0x100000U) #define GPIO_PDIR_PDI20_SHIFT (20U) /*! PDI20 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) #define GPIO_PDIR_PDI21_MASK (0x200000U) #define GPIO_PDIR_PDI21_SHIFT (21U) /*! PDI21 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) #define GPIO_PDIR_PDI22_MASK (0x400000U) #define GPIO_PDIR_PDI22_SHIFT (22U) /*! PDI22 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) #define GPIO_PDIR_PDI23_MASK (0x800000U) #define GPIO_PDIR_PDI23_SHIFT (23U) /*! PDI23 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) #define GPIO_PDIR_PDI24_MASK (0x1000000U) #define GPIO_PDIR_PDI24_SHIFT (24U) /*! PDI24 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) #define GPIO_PDIR_PDI25_MASK (0x2000000U) #define GPIO_PDIR_PDI25_SHIFT (25U) /*! PDI25 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) #define GPIO_PDIR_PDI26_MASK (0x4000000U) #define GPIO_PDIR_PDI26_SHIFT (26U) /*! PDI26 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) #define GPIO_PDIR_PDI27_MASK (0x8000000U) #define GPIO_PDIR_PDI27_SHIFT (27U) /*! PDI27 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) #define GPIO_PDIR_PDI28_MASK (0x10000000U) #define GPIO_PDIR_PDI28_SHIFT (28U) /*! PDI28 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) #define GPIO_PDIR_PDI29_MASK (0x20000000U) #define GPIO_PDIR_PDI29_SHIFT (29U) /*! PDI29 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) #define GPIO_PDIR_PDI30_MASK (0x40000000U) #define GPIO_PDIR_PDI30_SHIFT (30U) /*! PDI30 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) #define GPIO_PDIR_PDI31_MASK (0x80000000U) #define GPIO_PDIR_PDI31_SHIFT (31U) /*! PDI31 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) /*! @} */ /*! @name PDDR - Port Data Direction */ /*! @{ */ #define GPIO_PDDR_PDD0_MASK (0x1U) #define GPIO_PDDR_PDD0_SHIFT (0U) /*! PDD0 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) #define GPIO_PDDR_PDD1_MASK (0x2U) #define GPIO_PDDR_PDD1_SHIFT (1U) /*! PDD1 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) #define GPIO_PDDR_PDD2_MASK (0x4U) #define GPIO_PDDR_PDD2_SHIFT (2U) /*! PDD2 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) #define GPIO_PDDR_PDD3_MASK (0x8U) #define GPIO_PDDR_PDD3_SHIFT (3U) /*! PDD3 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) #define GPIO_PDDR_PDD4_MASK (0x10U) #define GPIO_PDDR_PDD4_SHIFT (4U) /*! PDD4 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) #define GPIO_PDDR_PDD5_MASK (0x20U) #define GPIO_PDDR_PDD5_SHIFT (5U) /*! PDD5 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) #define GPIO_PDDR_PDD6_MASK (0x40U) #define GPIO_PDDR_PDD6_SHIFT (6U) /*! PDD6 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) #define GPIO_PDDR_PDD7_MASK (0x80U) #define GPIO_PDDR_PDD7_SHIFT (7U) /*! PDD7 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) #define GPIO_PDDR_PDD8_MASK (0x100U) #define GPIO_PDDR_PDD8_SHIFT (8U) /*! PDD8 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) #define GPIO_PDDR_PDD9_MASK (0x200U) #define GPIO_PDDR_PDD9_SHIFT (9U) /*! PDD9 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) #define GPIO_PDDR_PDD10_MASK (0x400U) #define GPIO_PDDR_PDD10_SHIFT (10U) /*! PDD10 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) #define GPIO_PDDR_PDD11_MASK (0x800U) #define GPIO_PDDR_PDD11_SHIFT (11U) /*! PDD11 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) #define GPIO_PDDR_PDD12_MASK (0x1000U) #define GPIO_PDDR_PDD12_SHIFT (12U) /*! PDD12 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) #define GPIO_PDDR_PDD13_MASK (0x2000U) #define GPIO_PDDR_PDD13_SHIFT (13U) /*! PDD13 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) #define GPIO_PDDR_PDD14_MASK (0x4000U) #define GPIO_PDDR_PDD14_SHIFT (14U) /*! PDD14 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) #define GPIO_PDDR_PDD15_MASK (0x8000U) #define GPIO_PDDR_PDD15_SHIFT (15U) /*! PDD15 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) #define GPIO_PDDR_PDD16_MASK (0x10000U) #define GPIO_PDDR_PDD16_SHIFT (16U) /*! PDD16 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) #define GPIO_PDDR_PDD17_MASK (0x20000U) #define GPIO_PDDR_PDD17_SHIFT (17U) /*! PDD17 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) #define GPIO_PDDR_PDD18_MASK (0x40000U) #define GPIO_PDDR_PDD18_SHIFT (18U) /*! PDD18 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) #define GPIO_PDDR_PDD19_MASK (0x80000U) #define GPIO_PDDR_PDD19_SHIFT (19U) /*! PDD19 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) #define GPIO_PDDR_PDD20_MASK (0x100000U) #define GPIO_PDDR_PDD20_SHIFT (20U) /*! PDD20 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) #define GPIO_PDDR_PDD21_MASK (0x200000U) #define GPIO_PDDR_PDD21_SHIFT (21U) /*! PDD21 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) #define GPIO_PDDR_PDD22_MASK (0x400000U) #define GPIO_PDDR_PDD22_SHIFT (22U) /*! PDD22 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) #define GPIO_PDDR_PDD23_MASK (0x800000U) #define GPIO_PDDR_PDD23_SHIFT (23U) /*! PDD23 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) #define GPIO_PDDR_PDD24_MASK (0x1000000U) #define GPIO_PDDR_PDD24_SHIFT (24U) /*! PDD24 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) #define GPIO_PDDR_PDD25_MASK (0x2000000U) #define GPIO_PDDR_PDD25_SHIFT (25U) /*! PDD25 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) #define GPIO_PDDR_PDD26_MASK (0x4000000U) #define GPIO_PDDR_PDD26_SHIFT (26U) /*! PDD26 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) #define GPIO_PDDR_PDD27_MASK (0x8000000U) #define GPIO_PDDR_PDD27_SHIFT (27U) /*! PDD27 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) #define GPIO_PDDR_PDD28_MASK (0x10000000U) #define GPIO_PDDR_PDD28_SHIFT (28U) /*! PDD28 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) #define GPIO_PDDR_PDD29_MASK (0x20000000U) #define GPIO_PDDR_PDD29_SHIFT (29U) /*! PDD29 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) #define GPIO_PDDR_PDD30_MASK (0x40000000U) #define GPIO_PDDR_PDD30_SHIFT (30U) /*! PDD30 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) #define GPIO_PDDR_PDD31_MASK (0x80000000U) #define GPIO_PDDR_PDD31_SHIFT (31U) /*! PDD31 - Port Data Direction * 0b0..Input * 0b1..Output */ #define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) /*! @} */ /*! @name PIDR - Port Input Disable */ /*! @{ */ #define GPIO_PIDR_PID0_MASK (0x1U) #define GPIO_PIDR_PID0_SHIFT (0U) /*! PID0 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) #define GPIO_PIDR_PID1_MASK (0x2U) #define GPIO_PIDR_PID1_SHIFT (1U) /*! PID1 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) #define GPIO_PIDR_PID2_MASK (0x4U) #define GPIO_PIDR_PID2_SHIFT (2U) /*! PID2 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) #define GPIO_PIDR_PID3_MASK (0x8U) #define GPIO_PIDR_PID3_SHIFT (3U) /*! PID3 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) #define GPIO_PIDR_PID4_MASK (0x10U) #define GPIO_PIDR_PID4_SHIFT (4U) /*! PID4 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) #define GPIO_PIDR_PID5_MASK (0x20U) #define GPIO_PIDR_PID5_SHIFT (5U) /*! PID5 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) #define GPIO_PIDR_PID6_MASK (0x40U) #define GPIO_PIDR_PID6_SHIFT (6U) /*! PID6 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) #define GPIO_PIDR_PID7_MASK (0x80U) #define GPIO_PIDR_PID7_SHIFT (7U) /*! PID7 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) #define GPIO_PIDR_PID8_MASK (0x100U) #define GPIO_PIDR_PID8_SHIFT (8U) /*! PID8 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) #define GPIO_PIDR_PID9_MASK (0x200U) #define GPIO_PIDR_PID9_SHIFT (9U) /*! PID9 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) #define GPIO_PIDR_PID10_MASK (0x400U) #define GPIO_PIDR_PID10_SHIFT (10U) /*! PID10 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) #define GPIO_PIDR_PID11_MASK (0x800U) #define GPIO_PIDR_PID11_SHIFT (11U) /*! PID11 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) #define GPIO_PIDR_PID12_MASK (0x1000U) #define GPIO_PIDR_PID12_SHIFT (12U) /*! PID12 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) #define GPIO_PIDR_PID13_MASK (0x2000U) #define GPIO_PIDR_PID13_SHIFT (13U) /*! PID13 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) #define GPIO_PIDR_PID14_MASK (0x4000U) #define GPIO_PIDR_PID14_SHIFT (14U) /*! PID14 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) #define GPIO_PIDR_PID15_MASK (0x8000U) #define GPIO_PIDR_PID15_SHIFT (15U) /*! PID15 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) #define GPIO_PIDR_PID16_MASK (0x10000U) #define GPIO_PIDR_PID16_SHIFT (16U) /*! PID16 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) #define GPIO_PIDR_PID17_MASK (0x20000U) #define GPIO_PIDR_PID17_SHIFT (17U) /*! PID17 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) #define GPIO_PIDR_PID18_MASK (0x40000U) #define GPIO_PIDR_PID18_SHIFT (18U) /*! PID18 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) #define GPIO_PIDR_PID19_MASK (0x80000U) #define GPIO_PIDR_PID19_SHIFT (19U) /*! PID19 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) #define GPIO_PIDR_PID20_MASK (0x100000U) #define GPIO_PIDR_PID20_SHIFT (20U) /*! PID20 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) #define GPIO_PIDR_PID21_MASK (0x200000U) #define GPIO_PIDR_PID21_SHIFT (21U) /*! PID21 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) #define GPIO_PIDR_PID22_MASK (0x400000U) #define GPIO_PIDR_PID22_SHIFT (22U) /*! PID22 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) #define GPIO_PIDR_PID23_MASK (0x800000U) #define GPIO_PIDR_PID23_SHIFT (23U) /*! PID23 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) #define GPIO_PIDR_PID24_MASK (0x1000000U) #define GPIO_PIDR_PID24_SHIFT (24U) /*! PID24 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) #define GPIO_PIDR_PID25_MASK (0x2000000U) #define GPIO_PIDR_PID25_SHIFT (25U) /*! PID25 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) #define GPIO_PIDR_PID26_MASK (0x4000000U) #define GPIO_PIDR_PID26_SHIFT (26U) /*! PID26 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) #define GPIO_PIDR_PID27_MASK (0x8000000U) #define GPIO_PIDR_PID27_SHIFT (27U) /*! PID27 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) #define GPIO_PIDR_PID28_MASK (0x10000000U) #define GPIO_PIDR_PID28_SHIFT (28U) /*! PID28 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) #define GPIO_PIDR_PID29_MASK (0x20000000U) #define GPIO_PIDR_PID29_SHIFT (29U) /*! PID29 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) #define GPIO_PIDR_PID30_MASK (0x40000000U) #define GPIO_PIDR_PID30_SHIFT (30U) /*! PID30 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) #define GPIO_PIDR_PID31_MASK (0x80000000U) #define GPIO_PIDR_PID31_SHIFT (31U) /*! PID31 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) /*! @} */ /*! @name PDR - Pin Data */ /*! @{ */ #define GPIO_PDR_PD_MASK (0x1U) #define GPIO_PDR_PD_SHIFT (0U) /*! PD - Pin Data (I/O) * 0b0..Logic zero * 0b1..Logic one */ #define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) /*! @} */ /* The count of GPIO_PDR */ #define GPIO_PDR_COUNT (32U) /*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ /*! @{ */ #define GPIO_ICR_IRQC_MASK (0xF0000U) #define GPIO_ICR_IRQC_SHIFT (16U) /*! IRQC - Interrupt Configuration * 0b0000..ISF is disabled * 0b0001..ISF and DMA request on rising edge * 0b0010..ISF and DMA request on falling edge * 0b0011..ISF and DMA request on either edge * 0b0100..Reserved * 0b0101..ISF sets on rising edge * 0b0110..ISF sets on falling edge * 0b0111..ISF sets on either edge * 0b1000..ISF and interrupt when logic 0 * 0b1001..ISF and interrupt on rising edge * 0b1010..ISF and interrupt on falling edge * 0b1011..ISF and Interrupt on either edge * 0b1100..ISF and interrupt when logic 1 * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers * to generate the output trigger for use by other peripherals) * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other * enabled triggers to generate the output trigger for use by other peripherals) * 0b1111..Reserved */ #define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) #define GPIO_ICR_IRQS_MASK (0x100000U) #define GPIO_ICR_IRQS_SHIFT (20U) /*! IRQS - Interrupt Select * 0b0..Interrupt, trigger output, or DMA request 0 * 0b1..Interrupt, trigger output, or DMA request 1 */ #define GPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK) #define GPIO_ICR_LK_MASK (0x800000U) #define GPIO_ICR_LK_SHIFT (23U) /*! LK - Lock * 0b0..Lock * 0b1..Do not lock */ #define GPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK) #define GPIO_ICR_ISF_MASK (0x1000000U) #define GPIO_ICR_ISF_SHIFT (24U) /*! ISF - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) /*! @} */ /* The count of GPIO_ICR */ #define GPIO_ICR_COUNT (32U) /*! @name GICLR - Global Interrupt Control Low */ /*! @{ */ #define GPIO_GICLR_GIWE0_MASK (0x1U) #define GPIO_GICLR_GIWE0_SHIFT (0U) /*! GIWE0 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) #define GPIO_GICLR_GIWE1_MASK (0x2U) #define GPIO_GICLR_GIWE1_SHIFT (1U) /*! GIWE1 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) #define GPIO_GICLR_GIWE2_MASK (0x4U) #define GPIO_GICLR_GIWE2_SHIFT (2U) /*! GIWE2 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) #define GPIO_GICLR_GIWE3_MASK (0x8U) #define GPIO_GICLR_GIWE3_SHIFT (3U) /*! GIWE3 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) #define GPIO_GICLR_GIWE4_MASK (0x10U) #define GPIO_GICLR_GIWE4_SHIFT (4U) /*! GIWE4 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) #define GPIO_GICLR_GIWE5_MASK (0x20U) #define GPIO_GICLR_GIWE5_SHIFT (5U) /*! GIWE5 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) #define GPIO_GICLR_GIWE6_MASK (0x40U) #define GPIO_GICLR_GIWE6_SHIFT (6U) /*! GIWE6 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) #define GPIO_GICLR_GIWE7_MASK (0x80U) #define GPIO_GICLR_GIWE7_SHIFT (7U) /*! GIWE7 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) #define GPIO_GICLR_GIWE8_MASK (0x100U) #define GPIO_GICLR_GIWE8_SHIFT (8U) /*! GIWE8 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) #define GPIO_GICLR_GIWE9_MASK (0x200U) #define GPIO_GICLR_GIWE9_SHIFT (9U) /*! GIWE9 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) #define GPIO_GICLR_GIWE10_MASK (0x400U) #define GPIO_GICLR_GIWE10_SHIFT (10U) /*! GIWE10 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) #define GPIO_GICLR_GIWE11_MASK (0x800U) #define GPIO_GICLR_GIWE11_SHIFT (11U) /*! GIWE11 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) #define GPIO_GICLR_GIWE12_MASK (0x1000U) #define GPIO_GICLR_GIWE12_SHIFT (12U) /*! GIWE12 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) #define GPIO_GICLR_GIWE13_MASK (0x2000U) #define GPIO_GICLR_GIWE13_SHIFT (13U) /*! GIWE13 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) #define GPIO_GICLR_GIWE14_MASK (0x4000U) #define GPIO_GICLR_GIWE14_SHIFT (14U) /*! GIWE14 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) #define GPIO_GICLR_GIWE15_MASK (0x8000U) #define GPIO_GICLR_GIWE15_SHIFT (15U) /*! GIWE15 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) #define GPIO_GICLR_GIWD_MASK (0xFFFF0000U) #define GPIO_GICLR_GIWD_SHIFT (16U) /*! GIWD - Global Interrupt Write Data */ #define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) /*! @} */ /*! @name GICHR - Global Interrupt Control High */ /*! @{ */ #define GPIO_GICHR_GIWE16_MASK (0x1U) #define GPIO_GICHR_GIWE16_SHIFT (0U) /*! GIWE16 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) #define GPIO_GICHR_GIWE17_MASK (0x2U) #define GPIO_GICHR_GIWE17_SHIFT (1U) /*! GIWE17 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) #define GPIO_GICHR_GIWE18_MASK (0x4U) #define GPIO_GICHR_GIWE18_SHIFT (2U) /*! GIWE18 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) #define GPIO_GICHR_GIWE19_MASK (0x8U) #define GPIO_GICHR_GIWE19_SHIFT (3U) /*! GIWE19 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) #define GPIO_GICHR_GIWE20_MASK (0x10U) #define GPIO_GICHR_GIWE20_SHIFT (4U) /*! GIWE20 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) #define GPIO_GICHR_GIWE21_MASK (0x20U) #define GPIO_GICHR_GIWE21_SHIFT (5U) /*! GIWE21 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) #define GPIO_GICHR_GIWE22_MASK (0x40U) #define GPIO_GICHR_GIWE22_SHIFT (6U) /*! GIWE22 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) #define GPIO_GICHR_GIWE23_MASK (0x80U) #define GPIO_GICHR_GIWE23_SHIFT (7U) /*! GIWE23 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) #define GPIO_GICHR_GIWE24_MASK (0x100U) #define GPIO_GICHR_GIWE24_SHIFT (8U) /*! GIWE24 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) #define GPIO_GICHR_GIWE25_MASK (0x200U) #define GPIO_GICHR_GIWE25_SHIFT (9U) /*! GIWE25 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) #define GPIO_GICHR_GIWE26_MASK (0x400U) #define GPIO_GICHR_GIWE26_SHIFT (10U) /*! GIWE26 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) #define GPIO_GICHR_GIWE27_MASK (0x800U) #define GPIO_GICHR_GIWE27_SHIFT (11U) /*! GIWE27 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) #define GPIO_GICHR_GIWE28_MASK (0x1000U) #define GPIO_GICHR_GIWE28_SHIFT (12U) /*! GIWE28 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) #define GPIO_GICHR_GIWE29_MASK (0x2000U) #define GPIO_GICHR_GIWE29_SHIFT (13U) /*! GIWE29 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) #define GPIO_GICHR_GIWE30_MASK (0x4000U) #define GPIO_GICHR_GIWE30_SHIFT (14U) /*! GIWE30 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) #define GPIO_GICHR_GIWE31_MASK (0x8000U) #define GPIO_GICHR_GIWE31_SHIFT (15U) /*! GIWE31 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) #define GPIO_GICHR_GIWD_MASK (0xFFFF0000U) #define GPIO_GICHR_GIWD_SHIFT (16U) /*! GIWD - Global Interrupt Write Data */ #define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) /*! @} */ /*! @name ISFR - Interrupt Status Flag */ /*! @{ */ #define GPIO_ISFR_ISF0_MASK (0x1U) #define GPIO_ISFR_ISF0_SHIFT (0U) /*! ISF0 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) #define GPIO_ISFR_ISF1_MASK (0x2U) #define GPIO_ISFR_ISF1_SHIFT (1U) /*! ISF1 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) #define GPIO_ISFR_ISF2_MASK (0x4U) #define GPIO_ISFR_ISF2_SHIFT (2U) /*! ISF2 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) #define GPIO_ISFR_ISF3_MASK (0x8U) #define GPIO_ISFR_ISF3_SHIFT (3U) /*! ISF3 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) #define GPIO_ISFR_ISF4_MASK (0x10U) #define GPIO_ISFR_ISF4_SHIFT (4U) /*! ISF4 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) #define GPIO_ISFR_ISF5_MASK (0x20U) #define GPIO_ISFR_ISF5_SHIFT (5U) /*! ISF5 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) #define GPIO_ISFR_ISF6_MASK (0x40U) #define GPIO_ISFR_ISF6_SHIFT (6U) /*! ISF6 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) #define GPIO_ISFR_ISF7_MASK (0x80U) #define GPIO_ISFR_ISF7_SHIFT (7U) /*! ISF7 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) #define GPIO_ISFR_ISF8_MASK (0x100U) #define GPIO_ISFR_ISF8_SHIFT (8U) /*! ISF8 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) #define GPIO_ISFR_ISF9_MASK (0x200U) #define GPIO_ISFR_ISF9_SHIFT (9U) /*! ISF9 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) #define GPIO_ISFR_ISF10_MASK (0x400U) #define GPIO_ISFR_ISF10_SHIFT (10U) /*! ISF10 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) #define GPIO_ISFR_ISF11_MASK (0x800U) #define GPIO_ISFR_ISF11_SHIFT (11U) /*! ISF11 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) #define GPIO_ISFR_ISF12_MASK (0x1000U) #define GPIO_ISFR_ISF12_SHIFT (12U) /*! ISF12 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) #define GPIO_ISFR_ISF13_MASK (0x2000U) #define GPIO_ISFR_ISF13_SHIFT (13U) /*! ISF13 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) #define GPIO_ISFR_ISF14_MASK (0x4000U) #define GPIO_ISFR_ISF14_SHIFT (14U) /*! ISF14 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) #define GPIO_ISFR_ISF15_MASK (0x8000U) #define GPIO_ISFR_ISF15_SHIFT (15U) /*! ISF15 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) #define GPIO_ISFR_ISF16_MASK (0x10000U) #define GPIO_ISFR_ISF16_SHIFT (16U) /*! ISF16 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) #define GPIO_ISFR_ISF17_MASK (0x20000U) #define GPIO_ISFR_ISF17_SHIFT (17U) /*! ISF17 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) #define GPIO_ISFR_ISF18_MASK (0x40000U) #define GPIO_ISFR_ISF18_SHIFT (18U) /*! ISF18 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) #define GPIO_ISFR_ISF19_MASK (0x80000U) #define GPIO_ISFR_ISF19_SHIFT (19U) /*! ISF19 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) #define GPIO_ISFR_ISF20_MASK (0x100000U) #define GPIO_ISFR_ISF20_SHIFT (20U) /*! ISF20 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) #define GPIO_ISFR_ISF21_MASK (0x200000U) #define GPIO_ISFR_ISF21_SHIFT (21U) /*! ISF21 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) #define GPIO_ISFR_ISF22_MASK (0x400000U) #define GPIO_ISFR_ISF22_SHIFT (22U) /*! ISF22 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) #define GPIO_ISFR_ISF23_MASK (0x800000U) #define GPIO_ISFR_ISF23_SHIFT (23U) /*! ISF23 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) #define GPIO_ISFR_ISF24_MASK (0x1000000U) #define GPIO_ISFR_ISF24_SHIFT (24U) /*! ISF24 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) #define GPIO_ISFR_ISF25_MASK (0x2000000U) #define GPIO_ISFR_ISF25_SHIFT (25U) /*! ISF25 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) #define GPIO_ISFR_ISF26_MASK (0x4000000U) #define GPIO_ISFR_ISF26_SHIFT (26U) /*! ISF26 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) #define GPIO_ISFR_ISF27_MASK (0x8000000U) #define GPIO_ISFR_ISF27_SHIFT (27U) /*! ISF27 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) #define GPIO_ISFR_ISF28_MASK (0x10000000U) #define GPIO_ISFR_ISF28_SHIFT (28U) /*! ISF28 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) #define GPIO_ISFR_ISF29_MASK (0x20000000U) #define GPIO_ISFR_ISF29_SHIFT (29U) /*! ISF29 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) #define GPIO_ISFR_ISF30_MASK (0x40000000U) #define GPIO_ISFR_ISF30_SHIFT (30U) /*! ISF30 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) #define GPIO_ISFR_ISF31_MASK (0x80000000U) #define GPIO_ISFR_ISF31_SHIFT (31U) /*! ISF31 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) /*! @} */ /* The count of GPIO_ISFR */ #define GPIO_ISFR_COUNT (2U) /*! * @} */ /* end of group GPIO_Register_Masks */ /* GPIO - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x50096000u) /** Peripheral GPIO0 base address */ #define GPIO0_BASE_NS (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) /** Peripheral GPIO0_ALIAS1 base address */ #define GPIO0_ALIAS1_BASE (0x50097000u) /** Peripheral GPIO0_ALIAS1 base address */ #define GPIO0_ALIAS1_BASE_NS (0x40097000u) /** Peripheral GPIO0_ALIAS1 base pointer */ #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO0_ALIAS1 base pointer */ #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ #define GPIO1_BASE_NS (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) /** Peripheral GPIO1_ALIAS1 base address */ #define GPIO1_ALIAS1_BASE (0x50099000u) /** Peripheral GPIO1_ALIAS1 base address */ #define GPIO1_ALIAS1_BASE_NS (0x40099000u) /** Peripheral GPIO1_ALIAS1 base pointer */ #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO1_ALIAS1 base pointer */ #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ #define GPIO2_BASE_NS (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) /** Peripheral GPIO2_ALIAS1 base address */ #define GPIO2_ALIAS1_BASE (0x5009B000u) /** Peripheral GPIO2_ALIAS1 base address */ #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) /** Peripheral GPIO2_ALIAS1 base pointer */ #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO2_ALIAS1 base pointer */ #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ #define GPIO3_BASE_NS (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) /** Peripheral GPIO3_ALIAS1 base address */ #define GPIO3_ALIAS1_BASE (0x5009D000u) /** Peripheral GPIO3_ALIAS1 base address */ #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) /** Peripheral GPIO3_ALIAS1 base pointer */ #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO3_ALIAS1 base pointer */ #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ #define GPIO4_BASE_NS (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) /** Peripheral GPIO4_ALIAS1 base address */ #define GPIO4_ALIAS1_BASE (0x5009F000u) /** Peripheral GPIO4_ALIAS1 base address */ #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) /** Peripheral GPIO4_ALIAS1 base pointer */ #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO4_ALIAS1 base pointer */ #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ #define GPIO5_BASE_NS (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE_NS (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0_ALIAS1 base address */ #define GPIO0_ALIAS1_BASE (0x40097000u) /** Peripheral GPIO0_ALIAS1 base pointer */ #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1_ALIAS1 base address */ #define GPIO1_ALIAS1_BASE (0x40099000u) /** Peripheral GPIO1_ALIAS1 base pointer */ #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2_ALIAS1 base address */ #define GPIO2_ALIAS1_BASE (0x4009B000u) /** Peripheral GPIO2_ALIAS1 base pointer */ #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3_ALIAS1 base address */ #define GPIO3_ALIAS1_BASE (0x4009D000u) /** Peripheral GPIO3_ALIAS1 base pointer */ #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4_ALIAS1 base address */ #define GPIO4_ALIAS1_BASE (0x4009F000u) /** Peripheral GPIO4_ALIAS1 base pointer */ #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* Interrupt vectors for the GPIO peripheral type */ #define GPIO_IRQS {GPIO00_IRQn, GPIO10_IRQn, GPIO20_IRQn, GPIO30_IRQn,GPIO40_IRQn,GPIO50_IRQn} #define GPIO_IRQS_1 {GPIO01_IRQn, GPIO11_IRQn, GPIO21_IRQn, GPIO31_IRQn,GPIO41_IRQn,GPIO51_IRQn} /*! * @} */ /* end of group GPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HPDAC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HPDAC_Peripheral_Access_Layer HPDAC Peripheral Access Layer * @{ */ /** HPDAC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version Identifier, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __O uint32_t DATA; /**< Data, offset: 0x8 */ __IO uint32_t GCR; /**< Global Control, offset: 0xC */ __IO uint32_t FCR; /**< DAC FIFO Control, offset: 0x10 */ __I uint32_t FPR; /**< DAC FIFO Pointer, offset: 0x14 */ __IO uint32_t FSR; /**< FIFO Status, offset: 0x18 */ __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ __IO uint32_t DER; /**< DMA Enable, offset: 0x20 */ __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ __O uint32_t TCR; /**< Trigger Control, offset: 0x28 */ __IO uint32_t PCR; /**< Periodic Trigger Control, offset: 0x2C */ } HPDAC_Type; /* ---------------------------------------------------------------------------- -- HPDAC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HPDAC_Register_Masks HPDAC Register Masks * @{ */ /*! @name VERID - Version Identifier */ /*! @{ */ #define HPDAC_VERID_FEATURE_MASK (0xFFFFU) #define HPDAC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number */ #define HPDAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_VERID_FEATURE_SHIFT)) & HPDAC_VERID_FEATURE_MASK) #define HPDAC_VERID_MINOR_MASK (0xFF0000U) #define HPDAC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define HPDAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_VERID_MINOR_SHIFT)) & HPDAC_VERID_MINOR_MASK) #define HPDAC_VERID_MAJOR_MASK (0xFF000000U) #define HPDAC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define HPDAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_VERID_MAJOR_SHIFT)) & HPDAC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define HPDAC_PARAM_FIFOSZ_MASK (0x7U) #define HPDAC_PARAM_FIFOSZ_SHIFT (0U) /*! FIFOSZ - FIFO Size * 0b000..Reserved * 0b001..FIFO depth is 4 * 0b010..FIFO depth is 8 * 0b011..FIFO depth is 16 * 0b100..FIFO depth is 32 * 0b101..FIFO depth is 64 * 0b110..FIFO depth is 128 * 0b111..FIFO depth is 256 */ #define HPDAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_PARAM_FIFOSZ_SHIFT)) & HPDAC_PARAM_FIFOSZ_MASK) /*! @} */ /*! @name DATA - Data */ /*! @{ */ #define HPDAC_DATA_DATA_MASK (0x3FFFU) #define HPDAC_DATA_DATA_SHIFT (0U) /*! DATA - FIFO Entry or Buffer Entry */ #define HPDAC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_DATA_DATA_SHIFT)) & HPDAC_DATA_DATA_MASK) /*! @} */ /*! @name GCR - Global Control */ /*! @{ */ #define HPDAC_GCR_DACEN_MASK (0x1U) #define HPDAC_GCR_DACEN_SHIFT (0U) /*! DACEN - DAC Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_GCR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_GCR_DACEN_SHIFT)) & HPDAC_GCR_DACEN_MASK) #define HPDAC_GCR_FIFOEN_MASK (0x8U) #define HPDAC_GCR_FIFOEN_SHIFT (3U) /*! FIFOEN - FIFO Enable * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion. * 0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion. */ #define HPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_GCR_FIFOEN_SHIFT)) & HPDAC_GCR_FIFOEN_MASK) #define HPDAC_GCR_SWMD_MASK (0x10U) #define HPDAC_GCR_SWMD_SHIFT (4U) /*! SWMD - Swing Back Mode * 0b0..Disables * 0b1..Enables */ #define HPDAC_GCR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_GCR_SWMD_SHIFT)) & HPDAC_GCR_SWMD_MASK) #define HPDAC_GCR_TRGSEL_MASK (0x20U) #define HPDAC_GCR_TRGSEL_SHIFT (5U) /*! TRGSEL - DAC Trigger Select * 0b0..Hardware trigger * 0b1..Software trigger */ #define HPDAC_GCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_GCR_TRGSEL_SHIFT)) & HPDAC_GCR_TRGSEL_MASK) #define HPDAC_GCR_PTGEN_MASK (0x40U) #define HPDAC_GCR_PTGEN_SHIFT (6U) /*! PTGEN - DAC Periodic Trigger Mode Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_GCR_PTGEN(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_GCR_PTGEN_SHIFT)) & HPDAC_GCR_PTGEN_MASK) #define HPDAC_GCR_BUF_EN_MASK (0x20000U) #define HPDAC_GCR_BUF_EN_SHIFT (17U) /*! BUF_EN - Buffer Enable * 0b0..Not used * 0b1..Used */ #define HPDAC_GCR_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_GCR_BUF_EN_SHIFT)) & HPDAC_GCR_BUF_EN_MASK) /*! @} */ /*! @name FCR - DAC FIFO Control */ /*! @{ */ #define HPDAC_FCR_WML_MASK (0x1FU) #define HPDAC_FCR_WML_SHIFT (0U) /*! WML - Watermark Level */ #define HPDAC_FCR_WML(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FCR_WML_SHIFT)) & HPDAC_FCR_WML_MASK) /*! @} */ /*! @name FPR - DAC FIFO Pointer */ /*! @{ */ #define HPDAC_FPR_FIFO_RPT_MASK (0x1FU) #define HPDAC_FPR_FIFO_RPT_SHIFT (0U) /*! FIFO_RPT - FIFO Read Pointer */ #define HPDAC_FPR_FIFO_RPT(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FPR_FIFO_RPT_SHIFT)) & HPDAC_FPR_FIFO_RPT_MASK) #define HPDAC_FPR_FIFO_WPT_MASK (0x1F0000U) #define HPDAC_FPR_FIFO_WPT_SHIFT (16U) /*! FIFO_WPT - FIFO Write Pointer */ #define HPDAC_FPR_FIFO_WPT(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FPR_FIFO_WPT_SHIFT)) & HPDAC_FPR_FIFO_WPT_MASK) /*! @} */ /*! @name FSR - FIFO Status */ /*! @{ */ #define HPDAC_FSR_FULL_MASK (0x1U) #define HPDAC_FSR_FULL_SHIFT (0U) /*! FULL - FIFO Full Flag * 0b0..Not full * 0b1..Full */ #define HPDAC_FSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FSR_FULL_SHIFT)) & HPDAC_FSR_FULL_MASK) #define HPDAC_FSR_EMPTY_MASK (0x2U) #define HPDAC_FSR_EMPTY_SHIFT (1U) /*! EMPTY - FIFO Empty Flag * 0b0..Not empty * 0b1..Empty */ #define HPDAC_FSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FSR_EMPTY_SHIFT)) & HPDAC_FSR_EMPTY_MASK) #define HPDAC_FSR_WM_MASK (0x4U) #define HPDAC_FSR_WM_SHIFT (2U) /*! WM - FIFO Watermark Status Flag * 0b0..Data in FIFO is more than watermark level * 0b1..Data in FIFO is less than or equal to watermark level */ #define HPDAC_FSR_WM(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FSR_WM_SHIFT)) & HPDAC_FSR_WM_MASK) #define HPDAC_FSR_SWBK_MASK (0x8U) #define HPDAC_FSR_SWBK_SHIFT (3U) /*! SWBK - Swing Back One Cycle Complete Flag * 0b0..No swing back cycle has completed since the last time the flag was cleared * 0b1..At least one swing back cycle has occurred since the last time the flag was cleared */ #define HPDAC_FSR_SWBK(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FSR_SWBK_SHIFT)) & HPDAC_FSR_SWBK_MASK) #define HPDAC_FSR_OF_MASK (0x40U) #define HPDAC_FSR_OF_SHIFT (6U) /*! OF - FIFO Overflow Flag * 0b0..No overflow has occurred since the last time the flag was cleared * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared */ #define HPDAC_FSR_OF(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FSR_OF_SHIFT)) & HPDAC_FSR_OF_MASK) #define HPDAC_FSR_UF_MASK (0x80U) #define HPDAC_FSR_UF_SHIFT (7U) /*! UF - FIFO Underflow Flag * 0b0..No underflow has occurred since the last time the flag was cleared * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared */ #define HPDAC_FSR_UF(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FSR_UF_SHIFT)) & HPDAC_FSR_UF_MASK) #define HPDAC_FSR_PTGCOCO_MASK (0x100U) #define HPDAC_FSR_PTGCOCO_SHIFT (8U) /*! PTGCOCO - Period Trigger Mode Conversion Complete Flag * 0b0..Not completed or not started * 0b1..Completed */ #define HPDAC_FSR_PTGCOCO(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_FSR_PTGCOCO_SHIFT)) & HPDAC_FSR_PTGCOCO_MASK) /*! @} */ /*! @name IER - Interrupt Enable */ /*! @{ */ #define HPDAC_IER_FULL_IE_MASK (0x1U) #define HPDAC_IER_FULL_IE_SHIFT (0U) /*! FULL_IE - FIFO Full Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_IER_FULL_IE(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_IER_FULL_IE_SHIFT)) & HPDAC_IER_FULL_IE_MASK) #define HPDAC_IER_EMPTY_IE_MASK (0x2U) #define HPDAC_IER_EMPTY_IE_SHIFT (1U) /*! EMPTY_IE - FIFO Empty Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_IER_EMPTY_IE(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_IER_EMPTY_IE_SHIFT)) & HPDAC_IER_EMPTY_IE_MASK) #define HPDAC_IER_WM_IE_MASK (0x4U) #define HPDAC_IER_WM_IE_SHIFT (2U) /*! WM_IE - FIFO Watermark Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_IER_WM_IE(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_IER_WM_IE_SHIFT)) & HPDAC_IER_WM_IE_MASK) #define HPDAC_IER_SWBK_IE_MASK (0x8U) #define HPDAC_IER_SWBK_IE_SHIFT (3U) /*! SWBK_IE - Swing Back One Cycle Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_IER_SWBK_IE(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_IER_SWBK_IE_SHIFT)) & HPDAC_IER_SWBK_IE_MASK) #define HPDAC_IER_OF_IE_MASK (0x40U) #define HPDAC_IER_OF_IE_SHIFT (6U) /*! OF_IE - FIFO Overflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_IER_OF_IE(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_IER_OF_IE_SHIFT)) & HPDAC_IER_OF_IE_MASK) #define HPDAC_IER_UF_IE_MASK (0x80U) #define HPDAC_IER_UF_IE_SHIFT (7U) /*! UF_IE - FIFO Underflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_IER_UF_IE(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_IER_UF_IE_SHIFT)) & HPDAC_IER_UF_IE_MASK) #define HPDAC_IER_PTGCOCO_IE_MASK (0x100U) #define HPDAC_IER_PTGCOCO_IE_SHIFT (8U) /*! PTGCOCO_IE - PTG Mode Conversion Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_IER_PTGCOCO_IE(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_IER_PTGCOCO_IE_SHIFT)) & HPDAC_IER_PTGCOCO_IE_MASK) /*! @} */ /*! @name DER - DMA Enable */ /*! @{ */ #define HPDAC_DER_EMPTY_DMAEN_MASK (0x2U) #define HPDAC_DER_EMPTY_DMAEN_SHIFT (1U) /*! EMPTY_DMAEN - FIFO Empty DMA Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_DER_EMPTY_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_DER_EMPTY_DMAEN_SHIFT)) & HPDAC_DER_EMPTY_DMAEN_MASK) #define HPDAC_DER_WM_DMAEN_MASK (0x4U) #define HPDAC_DER_WM_DMAEN_SHIFT (2U) /*! WM_DMAEN - FIFO Watermark DMA Enable * 0b0..Disables * 0b1..Enables */ #define HPDAC_DER_WM_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_DER_WM_DMAEN_SHIFT)) & HPDAC_DER_WM_DMAEN_MASK) /*! @} */ /*! @name RCR - Reset Control */ /*! @{ */ #define HPDAC_RCR_SWRST_MASK (0x1U) #define HPDAC_RCR_SWRST_SHIFT (0U) /*! SWRST - Software Reset * 0b0..No effect * 0b1..Software reset */ #define HPDAC_RCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_RCR_SWRST_SHIFT)) & HPDAC_RCR_SWRST_MASK) #define HPDAC_RCR_FIFORST_MASK (0x2U) #define HPDAC_RCR_FIFORST_SHIFT (1U) /*! FIFORST - FIFO Reset * 0b0..No effect * 0b1..FIFO reset */ #define HPDAC_RCR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_RCR_FIFORST_SHIFT)) & HPDAC_RCR_FIFORST_MASK) /*! @} */ /*! @name TCR - Trigger Control */ /*! @{ */ #define HPDAC_TCR_SWTRG_MASK (0x1U) #define HPDAC_TCR_SWTRG_SHIFT (0U) /*! SWTRG - Software Trigger * 0b0..Not valid * 0b1..Valid */ #define HPDAC_TCR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_TCR_SWTRG_SHIFT)) & HPDAC_TCR_SWTRG_MASK) /*! @} */ /*! @name PCR - Periodic Trigger Control */ /*! @{ */ #define HPDAC_PCR_PTG_NUM_MASK (0xFFFFU) #define HPDAC_PCR_PTG_NUM_SHIFT (0U) /*! PTG_NUM - Periodic Trigger Number */ #define HPDAC_PCR_PTG_NUM(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_PCR_PTG_NUM_SHIFT)) & HPDAC_PCR_PTG_NUM_MASK) #define HPDAC_PCR_PTG_PERIOD_MASK (0xFFFF0000U) #define HPDAC_PCR_PTG_PERIOD_SHIFT (16U) /*! PTG_PERIOD - Periodic Trigger Period Width */ #define HPDAC_PCR_PTG_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_PCR_PTG_PERIOD_SHIFT)) & HPDAC_PCR_PTG_PERIOD_MASK) /*! @} */ /*! * @} */ /* end of group HPDAC_Register_Masks */ /* HPDAC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral DAC2 base address */ #define DAC2_BASE (0x50114000u) /** Peripheral DAC2 base address */ #define DAC2_BASE_NS (0x40114000u) /** Peripheral DAC2 base pointer */ #define DAC2 ((HPDAC_Type *)DAC2_BASE) /** Peripheral DAC2 base pointer */ #define DAC2_NS ((HPDAC_Type *)DAC2_BASE_NS) /** Array initializer of HPDAC peripheral base addresses */ #define HPDAC_BASE_ADDRS { DAC2_BASE } /** Array initializer of HPDAC peripheral base pointers */ #define HPDAC_BASE_PTRS { DAC2 } /** Array initializer of HPDAC peripheral base addresses */ #define HPDAC_BASE_ADDRS_NS { DAC2_BASE_NS } /** Array initializer of HPDAC peripheral base pointers */ #define HPDAC_BASE_PTRS_NS { DAC2_NS } #else /** Peripheral DAC2 base address */ #define DAC2_BASE (0x40114000u) /** Peripheral DAC2 base pointer */ #define DAC2 ((HPDAC_Type *)DAC2_BASE) /** Array initializer of HPDAC peripheral base addresses */ #define HPDAC_BASE_ADDRS { DAC2_BASE } /** Array initializer of HPDAC peripheral base pointers */ #define HPDAC_BASE_PTRS { DAC2 } #endif /*! * @} */ /* end of group HPDAC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2S Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer * @{ */ /** I2S - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */ __IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */ __IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */ __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ __O uint32_t TDR[2]; /**< Transmit Data, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[24]; __I uint32_t TFR[2]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */ uint8_t RESERVED_1[24]; __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ uint8_t RESERVED_2[36]; __IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */ __IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */ __IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */ __IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */ __IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */ __IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */ __I uint32_t RDR[2]; /**< Receive Data, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_3[24]; __I uint32_t RFR[2]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */ uint8_t RESERVED_5[28]; __IO uint32_t MCR; /**< MCLK Control, offset: 0x100 */ } I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard feature set */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) #define I2S_VERID_MINOR_MASK (0xFF0000U) #define I2S_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) #define I2S_VERID_MAJOR_MASK (0xFF000000U) #define I2S_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) /*! DATALINE - Number of Data Lines */ #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) #define I2S_PARAM_FIFO_MASK (0xF00U) #define I2S_PARAM_FIFO_SHIFT (8U) /*! FIFO - FIFO Size */ #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) #define I2S_PARAM_FRAME_MASK (0xF0000U) #define I2S_PARAM_FRAME_SHIFT (16U) /*! FRAME - Frame Size */ #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) /*! @} */ /*! @name TCSR - Transmit Control */ /*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Watermark not reached * 0b1..Watermark reached */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..Not empty * 0b1..Empty */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect * 0b1..Software reset */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect * 0b1..FIFO reset */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) /*! TE - Transmitter Enable * 0b0..Disable * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @} */ /*! @name TCR1 - Transmit Configuration 1 */ /*! @{ */ #define I2S_TCR1_TFW_MASK (0x7U) #define I2S_TCR1_TFW_SHIFT (0U) /*! TFW - Transmit FIFO Watermark * 0b000..1 * 0b001..2 * 0b010-0b110..(TFW +1) * 0b111..8 */ #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /*! @} */ /*! @name TCR2 - Transmit Configuration 2 */ /*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BYP_MASK (0x800000U) #define I2S_TCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass * 0b0..Disable * 0b1..Enable */ #define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Generate externally in Target mode * 0b1..Generate internally in Controller mode */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Active high * 0b1..Active low */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus clock * 0b01..Controller clock (MCLK) option 1 * 0b10..Controller clock (MCLK) option 2 * 0b11..Controller clock (MCLK) option 3 */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..Disable * 0b1..Enable */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source * 0b1..Swap the bit clock source */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b00..Asynchronous mode * 0b01..Synchronous with receiver * 0b10..Synchronous with another SAI transmitter * 0b11..Synchronous with another SAI receiver */ #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) /*! @} */ /*! @name TCR3 - Transmit Configuration 3 */ /*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration */ #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) #define I2S_TCR3_TCE_MASK (0x30000U) #define I2S_TCR3_TCE_SHIFT (16U) /*! TCE - Transmit Channel Enable */ #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) #define I2S_TCR3_CFR_MASK (0x3000000U) #define I2S_TCR3_CFR_SHIFT (24U) /*! CFR - Channel FIFO Reset */ #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) /*! @} */ /*! @name TCR4 - Transmit Configuration 4 */ /*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Generated externally in Target mode * 0b1..Generated internally in Controller mode */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Active high * 0b1..Active low */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) /*! ONDEM - On-Demand Mode * 0b0..Generated continuously * 0b1..Generated after the FIFO warning flag is cleared */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..First bit of the frame * 0b1..One bit before the first bit of the frame */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB * 0b1..MSB */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) /*! CHMOD - Channel Mode * 0b0..TDM mode * 0b1..Output mode */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width */ #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size */ #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..Disable FIFO packing * 0b01..Reserved * 0b10..Enable 8-bit FIFO packing * 0b11..Enable 16-bit FIFO packing */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode * 0b00..Disable * 0b01..Enable on FIFO reads (from transmit shift registers) * 0b10..Enable on FIFO writes (by software) * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..Continue from the start of the next frame * 0b1..Continue from the same word that caused the FIFO error */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) /*! @} */ /*! @name TCR5 - Transmit Configuration 5 */ /*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted * 0b00000..0 * 0b00001-0b11110..FBT * 0b11111..31 */ #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width * 0b00111..8 * 0b01000..9 * 0b01001-0b11110..(W0W value + 1) * 0b11111..32 */ #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) /*! WNW - Word N Width * 0b00111..8 * 0b01000..9 * 0b01001-0b11110..(WNW value + 1) * 0b11111..32 */ #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @} */ /*! @name TDR - Transmit Data */ /*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) /*! TDR - Transmit Data */ #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) /*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (2U) /*! @name TFR - Transmit FIFO */ /*! @{ */ #define I2S_TFR_RFP_MASK (0xFU) #define I2S_TFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) #define I2S_TFR_WFP_MASK (0xF0000U) #define I2S_TFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) #define I2S_TFR_WCP_MASK (0x80000000U) #define I2S_TFR_WCP_SHIFT (31U) /*! WCP - Write Channel Pointer * 0b0..No effect * 0b1..Next FIFO to be written */ #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) /*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (2U) /*! @name TMR - Transmit Mask */ /*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) /*! TWM - Transmit Word Mask * 0b00000000000000000000000000000000..Enable * 0b00000000000000000000000000000001..Mask */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /*! @} */ /*! @name RCSR - Receive Control */ /*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Watermark not reached * 0b1..Watermark reached */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..Not full * 0b1..Full */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..No error * 0b1..Receive overflow detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect * 0b1..Software reset */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect * 0b1..Reset */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Disable after completing the current frame * 0b1..Enable */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) /*! RE - Receiver Enable * 0b0..Disable * 0b1..Enable (or receiver disabled and not yet reached end of frame) */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @} */ /*! @name RCR1 - Receive Configuration 1 */ /*! @{ */ #define I2S_RCR1_RFW_MASK (0x7U) #define I2S_RCR1_RFW_SHIFT (0U) /*! RFW - Receive FIFO Watermark * 0b000..1 * 0b001..2 * 0b010-0b110..(RFW value + 1) * 0b111..8 */ #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /*! @} */ /*! @name RCR2 - Receive Configuration 2 */ /*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BYP_MASK (0x800000U) #define I2S_RCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass * 0b0..Disable * 0b1..Enable */ #define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Generated externally in Target mode * 0b1..Generated internally in Controller mode */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Active high * 0b1..Active low */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus clock * 0b01..Controller clock (MCLK) option 1 * 0b10..Controller clock (MCLK) option 2 * 0b11..Controller clock (MCLK) option 3 */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..Disable * 0b1..Enable */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source * 0b1..Swap the bit clock source */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b00..Asynchronous mode * 0b01..Synchronous with transmitter * 0b10..Synchronous with another SAI receiver * 0b11..Synchronous with another SAI transmitter */ #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) /*! @} */ /*! @name RCR3 - Receive Configuration 3 */ /*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration * 0b00000..Word 1 * 0b00001..Word 2 * 0b00010-0b11110..Word (WDFL value + 1) * 0b11111..Word 32 */ #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) #define I2S_RCR3_RCE_MASK (0x30000U) #define I2S_RCR3_RCE_SHIFT (16U) /*! RCE - Receive Channel Enable */ #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) #define I2S_RCR3_CFR_MASK (0x3000000U) #define I2S_RCR3_CFR_SHIFT (24U) /*! CFR - Channel FIFO Reset */ #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) /*! @} */ /*! @name RCR4 - Receive Configuration 4 */ /*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Generated externally in Target mode * 0b1..Generated internally in Controller mode */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Active high * 0b1..Active low */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) /*! ONDEM - On-Demand Mode * 0b0..Generated continuously * 0b1..Generated when the FIFO warning flag is 0 */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..First bit of the frame * 0b1..One bit before the first bit of the frame */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB * 0b1..MSB */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width * 0b00000..1 * 0b00001..2 * 0b00010-0b11110..(SYWD value + 1) * 0b11111..32 */ #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size * 0b00000..1 * 0b00001..2 * 0b00010-0b11110..(FRSZ value + 1) * 0b11111..32 */ #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..Disable * 0b01..Reserved * 0b10..Enable 8-bit FIFO packing * 0b11..Enable 16-bit FIFO packing */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode * 0b00..Disable * 0b01..Enable on FIFO writes (from receive shift registers) * 0b10..Enable on FIFO reads (by software) * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..From the start of the next frame after the FIFO error flag is cleared * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) /*! @} */ /*! @name RCR5 - Receive Configuration 5 */ /*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted * 0b00000..0 * 0b00001-0b11110..FBT value * 0b11111..31 */ #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width * 0b00000..1 * 0b00001..2 * 0b00010-0b11110..(W0W value + 1) * 0b11111..32 */ #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) /*! WNW - Word N Width * 0b00111..8 * 0b01000..9 * 0b01001-0b11110..(WNW value + 1) * 0b11111..32 */ #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @} */ /*! @name RDR - Receive Data */ /*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) /*! RDR - Receive Data */ #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) /*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (2U) /*! @name RFR - Receive FIFO */ /*! @{ */ #define I2S_RFR_RFP_MASK (0xFU) #define I2S_RFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) /*! RCP - Read Channel Pointer * 0b0..No effect * 0b1..Next FIFO to be read */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) #define I2S_RFR_WFP_MASK (0xF0000U) #define I2S_RFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) /*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (2U) /*! @name RMR - Receive Mask */ /*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) /*! RWM - Receive Word Mask * 0b00000000000000000000000000000000..Enable * 0b00000000000000000000000000000001..Mask */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /*! @} */ /*! @name MCR - MCLK Control */ /*! @{ */ #define I2S_MCR_DIV_MASK (0xFFU) #define I2S_MCR_DIV_SHIFT (0U) /*! DIV - MCLK Post Divide */ #define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK) #define I2S_MCR_DIVEN_MASK (0x800000U) #define I2S_MCR_DIVEN_SHIFT (23U) /*! DIVEN - MCLK Post Divide Enable * 0b0..Disable * 0b1..Enable */ #define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) #define I2S_MCR_MSEL_MASK (0x3000000U) #define I2S_MCR_MSEL_SHIFT (24U) /*! MSEL - MCLK Select * 0b00..Controller clock (MCLK) option 1 * 0b01..Reserved * 0b10..Controller clock (MCLK) option 2 * 0b11..Controller clock (MCLK) option 3 */ #define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) #define I2S_MCR_MOE_MASK (0x40000000U) #define I2S_MCR_MOE_SHIFT (30U) /*! MOE - MCLK Output Enable * 0b0..Input * 0b1..Output */ #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) /*! @} */ /*! * @} */ /* end of group I2S_Register_Masks */ /* I2S - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral SAI0 base address */ #define SAI0_BASE (0x50106000u) /** Peripheral SAI0 base address */ #define SAI0_BASE_NS (0x40106000u) /** Peripheral SAI0 base pointer */ #define SAI0 ((I2S_Type *)SAI0_BASE) /** Peripheral SAI0 base pointer */ #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) /** Peripheral SAI1 base address */ #define SAI1_BASE (0x50107000u) /** Peripheral SAI1 base address */ #define SAI1_BASE_NS (0x40107000u) /** Peripheral SAI1 base pointer */ #define SAI1 ((I2S_Type *)SAI1_BASE) /** Peripheral SAI1 base pointer */ #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS { SAI0, SAI1 } /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } #else /** Peripheral SAI0 base address */ #define SAI0_BASE (0x40106000u) /** Peripheral SAI0 base pointer */ #define SAI0 ((I2S_Type *)SAI0_BASE) /** Peripheral SAI1 base address */ #define SAI1_BASE (0x40107000u) /** Peripheral SAI1 base pointer */ #define SAI1 ((I2S_Type *)SAI1_BASE) /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS { SAI0, SAI1 } #endif /** Interrupt vectors for the I2S peripheral type */ #define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } #define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } /*! * @} */ /* end of group I2S_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I3C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer * @{ */ /** I3C - Register Layout Typedef */ typedef struct { __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ uint8_t RESERVED_0[8]; __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ uint8_t RESERVED_1[4]; __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ uint8_t RESERVED_2[8]; __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ uint8_t RESERVED_3[4]; __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ __IO uint32_t SDYNADDR; /**< Target Dynamic Address, offset: 0x64 */ __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ uint8_t RESERVED_4[4]; __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ uint8_t RESERVED_5[8]; __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ uint8_t RESERVED_6[4]; __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ union { /* offset: 0xD0 */ __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ }; __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ union { /* offset: 0xD8 */ __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ }; __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ uint8_t RESERVED_7[4]; __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ uint8_t RESERVED_8[52]; __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ uint8_t RESERVED_9[32]; __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ uint8_t RESERVED_10[3764]; __I uint32_t SID; /**< Target Module ID, offset: 0xFFC */ } I3C_Type; /* ---------------------------------------------------------------------------- -- I3C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I3C_Register_Masks I3C Register Masks * @{ */ /*! @name MCONFIG - Controller Configuration */ /*! @{ */ #define I3C_MCONFIG_MSTENA_MASK (0x3U) #define I3C_MCONFIG_MSTENA_SHIFT (0U) /*! MSTENA - Controller Enable * 0b00..CONTROLLER_OFF * 0b01..CONTROLLER_ON * 0b10..CONTROLLER_CAPABLE * 0b11..I2C_CONTROLLER_MODE */ #define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) #define I3C_MCONFIG_DISTO_MASK (0x8U) #define I3C_MCONFIG_DISTO_SHIFT (3U) /*! DISTO - Disable Timeout * 0b1..Disabled, if configured * 0b0..Enabled */ #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) #define I3C_MCONFIG_HKEEP_MASK (0x30U) #define I3C_MCONFIG_HKEEP_SHIFT (4U) /*! HKEEP - High-Keeper * 0b00..None * 0b01..WIRED_IN * 0b10..PASSIVE_SDA * 0b11..PASSIVE_ON_SDA_SCL */ #define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) #define I3C_MCONFIG_ODSTOP_MASK (0x40U) #define I3C_MCONFIG_ODSTOP_SHIFT (6U) /*! ODSTOP - Open Drain Stop * 0b1..Enable * 0b0..Disable */ #define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) #define I3C_MCONFIG_PPBAUD_MASK (0xF00U) #define I3C_MCONFIG_PPBAUD_SHIFT (8U) /*! PPBAUD - Push-Pull Baud Rate */ #define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) #define I3C_MCONFIG_PPLOW_MASK (0xF000U) #define I3C_MCONFIG_PPLOW_SHIFT (12U) /*! PPLOW - Push-Pull Low */ #define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) #define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) #define I3C_MCONFIG_ODBAUD_SHIFT (16U) /*! ODBAUD - Open Drain Baud Rate */ #define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) #define I3C_MCONFIG_ODHPP_SHIFT (24U) /*! ODHPP - Open Drain High Push-Pull * 0b1..Enable * 0b0..Disable */ #define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) #define I3C_MCONFIG_SKEW_MASK (0xE000000U) #define I3C_MCONFIG_SKEW_SHIFT (25U) /*! SKEW - Skew */ #define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) #define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) #define I3C_MCONFIG_I2CBAUD_SHIFT (28U) /*! I2CBAUD - I2C Baud Rate */ #define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) /*! @} */ /*! @name SCONFIG - Target Configuration */ /*! @{ */ #define I3C_SCONFIG_SLVENA_MASK (0x1U) #define I3C_SCONFIG_SLVENA_SHIFT (0U) /*! SLVENA - Target Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) #define I3C_SCONFIG_NACK_MASK (0x2U) #define I3C_SCONFIG_NACK_SHIFT (1U) /*! NACK - Not Acknowledge * 0b1..Always enable NACK mode (works normally) * 0b0..Always disable NACK mode */ #define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) #define I3C_SCONFIG_MATCHSS_MASK (0x4U) #define I3C_SCONFIG_MATCHSS_SHIFT (2U) /*! MATCHSS - Match Start or Stop * 0b1..Enable * 0b0..Disable */ #define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) #define I3C_SCONFIG_S0IGNORE_MASK (0x8U) #define I3C_SCONFIG_S0IGNORE_SHIFT (3U) /*! S0IGNORE - Ignore TE0 or TE1 Errors * 0b1..Ignore TE0 or TE1 errors * 0b0..Do not ignore TE0 or TE1 errors */ #define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) #define I3C_SCONFIG_DDROK_MASK (0x10U) #define I3C_SCONFIG_DDROK_SHIFT (4U) /*! DDROK - Double Data Rate OK * 0b1..Allow HDR-DDR messaging * 0b0..Do not allow HDR-DDR messaging */ #define I3C_SCONFIG_DDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK) #define I3C_SCONFIG_IDRAND_MASK (0x100U) #define I3C_SCONFIG_IDRAND_SHIFT (8U) /*! IDRAND - ID random * 0b1..Random value * 0b0..Part number and an instance */ #define I3C_SCONFIG_IDRAND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK) #define I3C_SCONFIG_OFFLINE_MASK (0x200U) #define I3C_SCONFIG_OFFLINE_SHIFT (9U) /*! OFFLINE - Offline * 0b1..Enable * 0b0..Disable */ #define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) #define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U) #define I3C_SCONFIG_BAMATCH_SHIFT (16U) /*! BAMATCH - Bus Available Match */ #define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) #define I3C_SCONFIG_SADDR_MASK (0xFE000000U) #define I3C_SCONFIG_SADDR_SHIFT (25U) /*! SADDR - Static Address */ #define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) /*! @} */ /*! @name SSTATUS - Target Status */ /*! @{ */ #define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) #define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) /*! STNOTSTOP - Status not Stop * 0b1..Busy * 0b0..In STOP condition */ #define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) #define I3C_SSTATUS_STMSG_MASK (0x2U) #define I3C_SSTATUS_STMSG_SHIFT (1U) /*! STMSG - Status Message * 0b1..Busy * 0b0..Idle */ #define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) #define I3C_SSTATUS_STCCCH_MASK (0x4U) #define I3C_SSTATUS_STCCCH_SHIFT (2U) /*! STCCCH - Status Common Command Code Handler * 0b1..Handled automatically * 0b0..No CCC message handled */ #define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) #define I3C_SSTATUS_STREQRD_MASK (0x8U) #define I3C_SSTATUS_STREQRD_SHIFT (3U) /*! STREQRD - Status Request Read * 0b1..SDR read from this target or an IBI is being pushed out * 0b0..Not an SDR read */ #define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) #define I3C_SSTATUS_STREQWR_MASK (0x10U) #define I3C_SSTATUS_STREQWR_SHIFT (4U) /*! STREQWR - Status Request Write * 0b1..SDR write data from the controller, but not in ENTDAA mode * 0b0..Not an SDR write */ #define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) #define I3C_SSTATUS_STDAA_MASK (0x20U) #define I3C_SSTATUS_STDAA_SHIFT (5U) /*! STDAA - Status Dynamic Address Assignment * 0b1..In ENTDAA mode * 0b0..Not in ENTDAA mode */ #define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) #define I3C_SSTATUS_STHDR_MASK (0x40U) #define I3C_SSTATUS_STHDR_SHIFT (6U) /*! STHDR - Status High Data Rate * 0b1..I3C bus in HDR-DDR mode * 0b0..I3C bus not in HDR-DDR mode */ #define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) #define I3C_SSTATUS_START_MASK (0x100U) #define I3C_SSTATUS_START_SHIFT (8U) /*! START - Start * 0b1..Detected * 0b0..Not detected * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) #define I3C_SSTATUS_MATCHED_MASK (0x200U) #define I3C_SSTATUS_MATCHED_SHIFT (9U) /*! MATCHED - Matched * 0b1..Header matched * 0b0..Header not matched * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) #define I3C_SSTATUS_STOP_MASK (0x400U) #define I3C_SSTATUS_STOP_SHIFT (10U) /*! STOP - Stop * 0b1..Stopped state detected * 0b0..No Stopped state detected * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) #define I3C_SSTATUS_RX_PEND_MASK (0x800U) #define I3C_SSTATUS_RX_PEND_SHIFT (11U) /*! RX_PEND - Received Message Pending * 0b1..Received message pending * 0b0..No received message pending */ #define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) #define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - Transmit Buffer Not Full * 0b1..Transmit buffer not full * 0b0..Transmit buffer full */ #define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) #define I3C_SSTATUS_DACHG_MASK (0x2000U) #define I3C_SSTATUS_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change * 0b1..DA change detected * 0b0..No DA change detected * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) #define I3C_SSTATUS_CCC_MASK (0x4000U) #define I3C_SSTATUS_CCC_SHIFT (14U) /*! CCC - Common Command Code * 0b1..CCC received * 0b0..CCC not received * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) #define I3C_SSTATUS_ERRWARN_MASK (0x8000U) #define I3C_SSTATUS_ERRWARN_SHIFT (15U) /*! ERRWARN - Error Warning */ #define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) #define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) #define I3C_SSTATUS_HDRMATCH_SHIFT (16U) /*! HDRMATCH - High Data Rate Command Match * 0b1..Matched the I3C dynamic address * 0b0..Did not match * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) #define I3C_SSTATUS_CHANDLED_MASK (0x20000U) #define I3C_SSTATUS_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code Handled * 0b1..CCC handling in progress * 0b0..CCC handling not in progress * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) #define I3C_SSTATUS_EVENT_MASK (0x40000U) #define I3C_SSTATUS_EVENT_SHIFT (18U) /*! EVENT - Event * 0b1..IBI, CR, or HJ occurred * 0b0..No event occurred * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) #define I3C_SSTATUS_EVDET_MASK (0x300000U) #define I3C_SSTATUS_EVDET_SHIFT (20U) /*! EVDET - Event Details * 0b00..NONE (no event or no pending event) * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) */ #define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) #define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) #define I3C_SSTATUS_IBIDIS_SHIFT (24U) /*! IBIDIS - In-Band Interrupts Disable * 0b1..Disabled * 0b0..Enabled */ #define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) #define I3C_SSTATUS_MRDIS_MASK (0x2000000U) #define I3C_SSTATUS_MRDIS_SHIFT (25U) /*! MRDIS - Controller Requests Disable * 0b1..Disabled * 0b0..Enabled */ #define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) #define I3C_SSTATUS_HJDIS_MASK (0x8000000U) #define I3C_SSTATUS_HJDIS_SHIFT (27U) /*! HJDIS - Hot-Join Disabled * 0b1..Disabled * 0b0..Enabled */ #define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) #define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) #define I3C_SSTATUS_ACTSTATE_SHIFT (28U) /*! ACTSTATE - Activity State from Common Command Codes (CCC) * 0b00..NO_LATENCY (normal bus operations) * 0b01..LATENCY_1MS (1 ms of latency) * 0b10..LATENCY_100MS (100 ms of latency) * 0b11..LATENCY_10S (10 seconds of latency) */ #define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) #define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) #define I3C_SSTATUS_TIMECTRL_SHIFT (30U) /*! TIMECTRL - Time Control * 0b00..NO_TIME_CONTROL (no time control is enabled) * 0b01..SYNC_MODE (Synchronous mode is enabled) * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) */ #define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) /*! @} */ /*! @name SCTRL - Target Control */ /*! @{ */ #define I3C_SCTRL_EVENT_MASK (0x3U) #define I3C_SCTRL_EVENT_SHIFT (0U) /*! EVENT - Event * 0b00..NORMAL_MODE * 0b01..IBI * 0b10..CONTROLLER_REQUEST * 0b11..HOT_JOIN_REQUEST */ #define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) #define I3C_SCTRL_EXTDATA_MASK (0x8U) #define I3C_SCTRL_EXTDATA_SHIFT (3U) /*! EXTDATA - Extended Data * 0b1..Enable * 0b0..Disable */ #define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) #define I3C_SCTRL_IBIDATA_MASK (0xFF00U) #define I3C_SCTRL_IBIDATA_SHIFT (8U) /*! IBIDATA - In-Band Interrupt Data */ #define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) #define I3C_SCTRL_PENDINT_MASK (0xF0000U) #define I3C_SCTRL_PENDINT_SHIFT (16U) /*! PENDINT - Pending Interrupt */ #define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) #define I3C_SCTRL_ACTSTATE_MASK (0x300000U) #define I3C_SCTRL_ACTSTATE_SHIFT (20U) /*! ACTSTATE - Activity State of Target */ #define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) #define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) #define I3C_SCTRL_VENDINFO_SHIFT (24U) /*! VENDINFO - Vendor Information */ #define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) /*! @} */ /*! @name SINTSET - Target Interrupt Set */ /*! @{ */ #define I3C_SINTSET_START_MASK (0x100U) #define I3C_SINTSET_START_SHIFT (8U) /*! START - Start Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) #define I3C_SINTSET_MATCHED_MASK (0x200U) #define I3C_SINTSET_MATCHED_SHIFT (9U) /*! MATCHED - Match Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) #define I3C_SINTSET_STOP_MASK (0x400U) #define I3C_SINTSET_STOP_SHIFT (10U) /*! STOP - Stop Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) #define I3C_SINTSET_RXPEND_MASK (0x800U) #define I3C_SINTSET_RXPEND_SHIFT (11U) /*! RXPEND - Receive Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) #define I3C_SINTSET_TXSEND_MASK (0x1000U) #define I3C_SINTSET_TXSEND_SHIFT (12U) /*! TXSEND - Transmit Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) #define I3C_SINTSET_DACHG_MASK (0x2000U) #define I3C_SINTSET_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) #define I3C_SINTSET_CCC_MASK (0x4000U) #define I3C_SINTSET_CCC_SHIFT (14U) /*! CCC - Common Command Code (CCC) Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) #define I3C_SINTSET_ERRWARN_MASK (0x8000U) #define I3C_SINTSET_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) #define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) #define I3C_SINTSET_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - Double Data Rate Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) #define I3C_SINTSET_CHANDLED_MASK (0x20000U) #define I3C_SINTSET_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code (CCC) Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) #define I3C_SINTSET_EVENT_MASK (0x40000U) #define I3C_SINTSET_EVENT_SHIFT (18U) /*! EVENT - Event Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) /*! @} */ /*! @name SINTCLR - Target Interrupt Clear */ /*! @{ */ #define I3C_SINTCLR_START_MASK (0x100U) #define I3C_SINTCLR_START_SHIFT (8U) /*! START - START Interrupt Enable Clear */ #define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) #define I3C_SINTCLR_MATCHED_MASK (0x200U) #define I3C_SINTCLR_MATCHED_SHIFT (9U) /*! MATCHED - Matched Interrupt Enable Clear */ #define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) #define I3C_SINTCLR_STOP_MASK (0x400U) #define I3C_SINTCLR_STOP_SHIFT (10U) /*! STOP - STOP Interrupt Enable Clear */ #define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) #define I3C_SINTCLR_RXPEND_MASK (0x800U) #define I3C_SINTCLR_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Enable Clear */ #define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) #define I3C_SINTCLR_TXSEND_MASK (0x1000U) #define I3C_SINTCLR_TXSEND_SHIFT (12U) /*! TXSEND - TXSEND Interrupt Enable Clear */ #define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) #define I3C_SINTCLR_DACHG_MASK (0x2000U) #define I3C_SINTCLR_DACHG_SHIFT (13U) /*! DACHG - DACHG Interrupt Enable Clear */ #define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) #define I3C_SINTCLR_CCC_MASK (0x4000U) #define I3C_SINTCLR_CCC_SHIFT (14U) /*! CCC - CCC Interrupt Enable Clear */ #define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) #define I3C_SINTCLR_ERRWARN_MASK (0x8000U) #define I3C_SINTCLR_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Enable Clear */ #define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) #define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) #define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear */ #define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) #define I3C_SINTCLR_CHANDLED_MASK (0x20000U) #define I3C_SINTCLR_CHANDLED_SHIFT (17U) /*! CHANDLED - CHANDLED Interrupt Enable Clear */ #define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) #define I3C_SINTCLR_EVENT_MASK (0x40000U) #define I3C_SINTCLR_EVENT_SHIFT (18U) /*! EVENT - EVENT Interrupt Enable Clear */ #define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) /*! @} */ /*! @name SINTMASKED - Target Interrupt Mask */ /*! @{ */ #define I3C_SINTMASKED_START_MASK (0x100U) #define I3C_SINTMASKED_START_SHIFT (8U) /*! START - START Interrupt Mask */ #define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) #define I3C_SINTMASKED_MATCHED_MASK (0x200U) #define I3C_SINTMASKED_MATCHED_SHIFT (9U) /*! MATCHED - MATCHED Interrupt Mask */ #define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) #define I3C_SINTMASKED_STOP_MASK (0x400U) #define I3C_SINTMASKED_STOP_SHIFT (10U) /*! STOP - STOP Interrupt Mask */ #define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) #define I3C_SINTMASKED_RXPEND_MASK (0x800U) #define I3C_SINTMASKED_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Mask */ #define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) #define I3C_SINTMASKED_TXSEND_MASK (0x1000U) #define I3C_SINTMASKED_TXSEND_SHIFT (12U) /*! TXSEND - TXSEND Interrupt Mask */ #define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) #define I3C_SINTMASKED_DACHG_MASK (0x2000U) #define I3C_SINTMASKED_DACHG_SHIFT (13U) /*! DACHG - DACHG Interrupt Mask */ #define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) #define I3C_SINTMASKED_CCC_MASK (0x4000U) #define I3C_SINTMASKED_CCC_SHIFT (14U) /*! CCC - CCC Interrupt Mask */ #define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) #define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_SINTMASKED_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Mask */ #define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) #define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) #define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - DDRMATCHED Interrupt Mask */ #define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) #define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) #define I3C_SINTMASKED_CHANDLED_SHIFT (17U) /*! CHANDLED - CHANDLED Interrupt Mask */ #define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) #define I3C_SINTMASKED_EVENT_MASK (0x40000U) #define I3C_SINTMASKED_EVENT_SHIFT (18U) /*! EVENT - EVENT Interrupt Mask */ #define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) /*! @} */ /*! @name SERRWARN - Target Errors and Warnings */ /*! @{ */ #define I3C_SERRWARN_ORUN_MASK (0x1U) #define I3C_SERRWARN_ORUN_SHIFT (0U) /*! ORUN - Overrun Error * 0b1..Overrun error * 0b0..No overrun error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) #define I3C_SERRWARN_URUN_MASK (0x2U) #define I3C_SERRWARN_URUN_SHIFT (1U) /*! URUN - Underrun Error * 0b1..Underrun error * 0b0..No underrun error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) #define I3C_SERRWARN_URUNNACK_MASK (0x4U) #define I3C_SERRWARN_URUNNACK_SHIFT (2U) /*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error * 0b1..Underrun; not acknowledged error * 0b0..No underrun; not acknowledged error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) #define I3C_SERRWARN_TERM_MASK (0x8U) #define I3C_SERRWARN_TERM_SHIFT (3U) /*! TERM - Terminated Error * 0b1..Terminated error * 0b0..No terminated error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) #define I3C_SERRWARN_INVSTART_MASK (0x10U) #define I3C_SERRWARN_INVSTART_SHIFT (4U) /*! INVSTART - Invalid Start Error * 0b1..Invalid start error * 0b0..No invalid start error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) #define I3C_SERRWARN_SPAR_MASK (0x100U) #define I3C_SERRWARN_SPAR_SHIFT (8U) /*! SPAR - SDR Parity Error * 0b1..SDR parity error * 0b0..No SDR parity error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) #define I3C_SERRWARN_HPAR_MASK (0x200U) #define I3C_SERRWARN_HPAR_SHIFT (9U) /*! HPAR - HDR Parity Error * 0b1..HDR parity error * 0b0..No HDR parity error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) #define I3C_SERRWARN_HCRC_MASK (0x400U) #define I3C_SERRWARN_HCRC_SHIFT (10U) /*! HCRC - HDR-DDR CRC Error * 0b1..HDR-DDR CRC error occurred * 0b0..No HDR-DDR CRC error occurred * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) #define I3C_SERRWARN_S0S1_MASK (0x800U) #define I3C_SERRWARN_S0S1_SHIFT (11U) /*! S0S1 - TE0 or TE1 Error * 0b1..TE0 or TE1 error occurred * 0b0..No TE0 or TE1 error occurred * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) #define I3C_SERRWARN_OREAD_MASK (0x10000U) #define I3C_SERRWARN_OREAD_SHIFT (16U) /*! OREAD - Over-Read Error * 0b1..Over-read error * 0b0..No over-read error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) #define I3C_SERRWARN_OWRITE_MASK (0x20000U) #define I3C_SERRWARN_OWRITE_SHIFT (17U) /*! OWRITE - Over-Write Error * 0b1..Overwrite error * 0b0..No overwrite error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) /*! @} */ /*! @name SDMACTRL - Target DMA Control */ /*! @{ */ #define I3C_SDMACTRL_DMAFB_MASK (0x3U) #define I3C_SDMACTRL_DMAFB_SHIFT (0U) /*! DMAFB - DMA Read (From-Bus) Trigger * 0b00..DMA not used * 0b01..DMA enabled for one frame * 0b10..DMA enabled until turned off * 0b11.. */ #define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) #define I3C_SDMACTRL_DMATB_MASK (0xCU) #define I3C_SDMACTRL_DMATB_SHIFT (2U) /*! DMATB - DMA Write (To-Bus) Trigger * 0b00..DMA not used * 0b01..DMA enabled for one frame * 0b10..DMA enabled until turned off * 0b11.. */ #define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) #define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) #define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) /*! DMAWIDTH - Width of DMA Operations * 0b00, 0b01..Byte * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) * 0b11.. */ #define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) /*! @} */ /*! @name SDATACTRL - Target Data Control */ /*! @{ */ #define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) /*! FLUSHTB - Flush To-Bus Buffer or FIFO */ #define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) #define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) /*! FLUSHFB - Flush From-Bus Buffer or FIFO */ #define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) #define I3C_SDATACTRL_UNLOCK_MASK (0x8U) #define I3C_SDATACTRL_UNLOCK_SHIFT (3U) /*! UNLOCK - Unlock * 0b0..Cannot be changed * 0b1..Can be changed */ #define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) #define I3C_SDATACTRL_TXTRIG_MASK (0x30U) #define I3C_SDATACTRL_TXTRIG_SHIFT (4U) /*! TXTRIG - Transmit Trigger Level * 0b00..Trigger when empty * 0b01..Trigger when 1/4 full or less * 0b10..Trigger when 1/2 full or less * 0b11..Default (trigger when 1 less than full or less) */ #define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) #define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) #define I3C_SDATACTRL_RXTRIG_SHIFT (6U) /*! RXTRIG - Receive Trigger Level * 0b00..Trigger when not empty * 0b01..Trigger when 1/4 or more full * 0b10..Trigger when 1/2 or more full * 0b11..Trigger when 3/4 or more full */ #define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) #define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) #define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) /*! TXCOUNT - Count of Bytes in Transmit */ #define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) #define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) #define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Count of Bytes in Receive */ #define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) #define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_SDATACTRL_TXFULL_SHIFT (30U) /*! TXFULL - Transmit is Full * 0b1..Full * 0b0..Not full */ #define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) #define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) /*! RXEMPTY - Receive is Empty * 0b1..Empty * 0b0..Not empty */ #define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) /*! @} */ /*! @name SWDATAB - Target Write Data Byte */ /*! @{ */ #define I3C_SWDATAB_DATA_MASK (0xFFU) #define I3C_SWDATAB_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) #define I3C_SWDATAB_END_MASK (0x100U) #define I3C_SWDATAB_END_SHIFT (8U) /*! END - End * 0b1..End * 0b0..Not the end */ #define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) #define I3C_SWDATAB_END_ALSO_MASK (0x10000U) #define I3C_SWDATAB_END_ALSO_SHIFT (16U) /*! END_ALSO - End Also * 0b1..End * 0b0..Not the end */ #define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) /*! @} */ /*! @name SWDATABE - Target Write Data Byte End */ /*! @{ */ #define I3C_SWDATABE_DATA_MASK (0xFFU) #define I3C_SWDATABE_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) /*! @} */ /*! @name SWDATAH - Target Write Data Halfword */ /*! @{ */ #define I3C_SWDATAH_DATA0_MASK (0xFFU) #define I3C_SWDATAH_DATA0_SHIFT (0U) /*! DATA0 - Data 0 */ #define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) #define I3C_SWDATAH_DATA1_MASK (0xFF00U) #define I3C_SWDATAH_DATA1_SHIFT (8U) /*! DATA1 - Data 1 */ #define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) #define I3C_SWDATAH_END_MASK (0x10000U) #define I3C_SWDATAH_END_SHIFT (16U) /*! END - End of Message * 0b1..End * 0b0..Not the end */ #define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) /*! @} */ /*! @name SWDATAHE - Target Write Data Halfword End */ /*! @{ */ #define I3C_SWDATAHE_DATA0_MASK (0xFFU) #define I3C_SWDATAHE_DATA0_SHIFT (0U) /*! DATA0 - Data 0 */ #define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) #define I3C_SWDATAHE_DATA1_MASK (0xFF00U) #define I3C_SWDATAHE_DATA1_SHIFT (8U) /*! DATA1 - Data 1 */ #define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) /*! @} */ /*! @name SRDATAB - Target Read Data Byte */ /*! @{ */ #define I3C_SRDATAB_DATA0_MASK (0xFFU) #define I3C_SRDATAB_DATA0_SHIFT (0U) /*! DATA0 - Data 0 */ #define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) /*! @} */ /*! @name SRDATAH - Target Read Data Halfword */ /*! @{ */ #define I3C_SRDATAH_LSB_MASK (0xFFU) #define I3C_SRDATAH_LSB_SHIFT (0U) /*! LSB - Low Byte */ #define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) #define I3C_SRDATAH_MSB_MASK (0xFF00U) #define I3C_SRDATAH_MSB_SHIFT (8U) /*! MSB - High Byte */ #define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) /*! @} */ /*! @name SWDATAB1 - Target Write Data Byte */ /*! @{ */ #define I3C_SWDATAB1_DATA_MASK (0xFFU) #define I3C_SWDATAB1_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) /*! @} */ /*! @name SCAPABILITIES2 - Target Capabilities 2 */ /*! @{ */ #define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) #define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) /*! MAPCNT - Map Count */ #define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) #define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) #define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) /*! I2C10B - I2C 10-bit Address * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) #define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) #define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) /*! I2CRST - I2C Software Reset * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) #define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) #define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) /*! I2CDEVID - I2C Device ID * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) #define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) #define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) /*! IBIEXT - In-Band Interrupt EXTDATA * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) #define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) #define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) /*! IBIXREG - In-Band Interrupt Extended Register * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) #define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) #define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) /*! SLVRST - Target Reset * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) #define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) #define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) /*! GROUP - Group * 0b00..v1.1 group addressing not supported * 0b01..One group supported * 0b10..Two groups supported * 0b11..Three groups supported */ #define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) #define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) #define I3C_SCAPABILITIES2_AASA_SHIFT (21U) /*! AASA - SETAASA * 0b1..SETAASA supported * 0b0..SETAASA not supported */ #define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) #define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) #define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) /*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable * 0b1..Subscriber capable * 0b0..Not subscriber capable */ #define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) #define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) #define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) /*! SSTWR - Target-Target(s)-Tunnel Write Capable * 0b1..Write capable * 0b0..Not write capable */ #define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) /*! @} */ /*! @name SCAPABILITIES - Target Capabilities */ /*! @{ */ #define I3C_SCAPABILITIES_IDENA_MASK (0x3U) #define I3C_SCAPABILITIES_IDENA_SHIFT (0U) /*! IDENA - ID 48b Handler * 0b00..Application * 0b01..Hardware * 0b10..Hardware, but the I3C module instance handles ID 48b * 0b11..A part number register (PARTNO) */ #define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) #define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) #define I3C_SCAPABILITIES_IDREG_SHIFT (2U) /*! IDREG - ID Register * 0b0000..All ID register features disabled * 0bxxx1..ID Instance is a register; used if there is no PARTNO register * 0bxx1x..An ID Random field is available * 0bx1xx..A Device Characteristic Register (DCR) is available * 0b1xxx..A Bus Characteristics Register (BCR) is available */ #define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) #define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) #define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) /*! HDRSUPP - High Data Rate Support * 0b00..No HDR modes supported * 0b01..DDR mode supported * *.. */ #define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) #define I3C_SCAPABILITIES_MASTER_MASK (0x200U) #define I3C_SCAPABILITIES_MASTER_SHIFT (9U) /*! MASTER - Controller * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) #define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) #define I3C_SCAPABILITIES_SADDR_SHIFT (10U) /*! SADDR - Static Address * 0b00..No static address * 0b01..Static address is fixed in hardware * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) * 0b11..SCONFIG register supplies the static address */ #define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) #define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) #define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) /*! CCCHANDLE - Common Command Codes Handling * 0b0000..All handling features disabled * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] */ #define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) #define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) #define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) /*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events * 0b00000..Application cannot generate IBI, CR, or HJ * 0bxxxx1..Application can generate an IBI * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register * 0bxx1xx..Application can generate a controller request for a secondary controller * 0bx1xxx..Application can generate a Hot-Join event * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing */ #define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) #define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) #define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) /*! TIMECTRL - Time Control * 0b0..No time control supported * 0b1..At least one time-control type supported */ #define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) #define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) #define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) /*! EXTFIFO - External FIFO * 0b000..No external FIFO available * 0b001..Standard available or free external FIFO * 0b010..Request track external FIFO * *.. */ #define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) #define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) #define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) /*! FIFOTX - FIFO Transmit * 0b00..Two * 0b01..Four * 0b10..Eight * 0b11..16 or larger */ #define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) #define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) #define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) /*! FIFORX - FIFO Receive * 0b00..Two or three * 0b01..Four * 0b10..Eight * 0b11..16 or larger */ #define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) #define I3C_SCAPABILITIES_INT_MASK (0x40000000U) #define I3C_SCAPABILITIES_INT_SHIFT (30U) /*! INT - Interrupts * 0b1..Supported * 0b0..Not supported */ #define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) #define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) #define I3C_SCAPABILITIES_DMA_SHIFT (31U) /*! DMA - Direct Memory Access * 0b1..Supported * 0b0..Not supported */ #define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) /*! @} */ /*! @name SDYNADDR - Target Dynamic Address */ /*! @{ */ #define I3C_SDYNADDR_DAVALID_MASK (0x1U) #define I3C_SDYNADDR_DAVALID_SHIFT (0U) /*! DAVALID - Dynamic Address Valid * 0b0..DANOTASSIGNED: a dynamic address is not assigned * 0b1..DAASSIGNED: a dynamic address is assigned */ #define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) #define I3C_SDYNADDR_DADDR_MASK (0xFEU) #define I3C_SDYNADDR_DADDR_SHIFT (1U) /*! DADDR - Dynamic Address */ #define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK) #define I3C_SDYNADDR_MAPSA_MASK (0x1000U) #define I3C_SDYNADDR_MAPSA_SHIFT (12U) /*! MAPSA - Map a Static Address */ #define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK) #define I3C_SDYNADDR_SA10B_MASK (0xE000U) #define I3C_SDYNADDR_SA10B_SHIFT (13U) /*! SA10B - 10-Bit Static Address */ #define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) #define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) #define I3C_SDYNADDR_KEY_SHIFT (16U) /*! KEY - Key */ #define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK) /*! @} */ /*! @name SMAXLIMITS - Target Maximum Limits */ /*! @{ */ #define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) #define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) /*! MAXRD - Maximum Read Length */ #define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) #define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) #define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) /*! MAXWR - Maximum Write Length */ #define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) /*! @} */ /*! @name SIDPARTNO - Target ID Part Number */ /*! @{ */ #define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) #define I3C_SIDPARTNO_PARTNO_SHIFT (0U) /*! PARTNO - Part Number */ #define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) /*! @} */ /*! @name SIDEXT - Target ID Extension */ /*! @{ */ #define I3C_SIDEXT_DCR_MASK (0xFF00U) #define I3C_SIDEXT_DCR_SHIFT (8U) /*! DCR - Device Characteristic Register */ #define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) #define I3C_SIDEXT_BCR_MASK (0xFF0000U) #define I3C_SIDEXT_BCR_SHIFT (16U) /*! BCR - Bus Characteristics Register */ #define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) /*! @} */ /*! @name SVENDORID - Target Vendor ID */ /*! @{ */ #define I3C_SVENDORID_VID_MASK (0x7FFFU) #define I3C_SVENDORID_VID_SHIFT (0U) /*! VID - Vendor ID */ #define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) /*! @} */ /*! @name STCCLOCK - Target Time Control Clock */ /*! @{ */ #define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) #define I3C_STCCLOCK_ACCURACY_SHIFT (0U) /*! ACCURACY - Clock Accuracy */ #define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) #define I3C_STCCLOCK_FREQ_MASK (0xFF00U) #define I3C_STCCLOCK_FREQ_SHIFT (8U) /*! FREQ - Clock Frequency */ #define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) /*! @} */ /*! @name SMSGMAPADDR - Target Message Map Address */ /*! @{ */ #define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) #define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) /*! MAPLAST - Matched Address Index */ #define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) #define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) #define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) /*! LASTSTATIC - Last Static Address Matched * 0b1..I2C static address * 0b0..I3C dynamic address */ #define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) #define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) #define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) /*! MAPLASTM1 - Matched Previous Address Index 1 */ #define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) #define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) #define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) /*! MAPLASTM2 - Matched Previous Index 2 */ #define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) /*! @} */ /*! @name MCTRL - Controller Control */ /*! @{ */ #define I3C_MCTRL_REQUEST_MASK (0x7U) #define I3C_MCTRL_REQUEST_SHIFT (0U) /*! REQUEST - Request * 0b000..NONE * 0b001..EMITSTARTADDR * 0b010..EMITSTOP * 0b011..IBIACKNACK * 0b100..PROCESSDAA * 0b101.. * 0b110..Force Exit and Target Reset * 0b111..AUTOIBI */ #define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) #define I3C_MCTRL_TYPE_MASK (0x30U) #define I3C_MCTRL_TYPE_SHIFT (4U) /*! TYPE - Bus Type with EmitStartAddr * 0b00..I3C * 0b01..I2C * 0b10..DDR * 0b11.. */ #define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) #define I3C_MCTRL_IBIRESP_MASK (0xC0U) #define I3C_MCTRL_IBIRESP_SHIFT (6U) /*! IBIRESP - In-Band Interrupt Response * 0b00..ACK (acknowledge) * 0b01..NACK (reject) * 0b10..Acknowledge with mandatory byte * 0b11..Manual */ #define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) #define I3C_MCTRL_DIR_MASK (0x100U) #define I3C_MCTRL_DIR_SHIFT (8U) /*! DIR - Direction * 0b0..Write * 0b1..Read */ #define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) #define I3C_MCTRL_ADDR_MASK (0xFE00U) #define I3C_MCTRL_ADDR_SHIFT (9U) /*! ADDR - Address */ #define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) #define I3C_MCTRL_RDTERM_MASK (0xFF0000U) #define I3C_MCTRL_RDTERM_SHIFT (16U) /*! RDTERM - Read Terminate Counter */ #define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) /*! @} */ /*! @name MSTATUS - Controller Status */ /*! @{ */ #define I3C_MSTATUS_STATE_MASK (0x7U) #define I3C_MSTATUS_STATE_SHIFT (0U) /*! STATE - State of the Controller * 0b000..IDLE (bus has stopped) * 0b001..SLVREQ (target request) * 0b010..MSGSDR * 0b011..NORMACT * 0b100..MSGDDR * 0b101..DAA * 0b110..IBIACK * 0b111..IBIRCV */ #define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) #define I3C_MSTATUS_BETWEEN_MASK (0x10U) #define I3C_MSTATUS_BETWEEN_SHIFT (4U) /*! BETWEEN - Between * 0b0..Inactive (for other cases) * 0b1..Active */ #define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) #define I3C_MSTATUS_NACKED_MASK (0x20U) #define I3C_MSTATUS_NACKED_SHIFT (5U) /*! NACKED - Not Acknowledged * 0b1..NACKed (not acknowledged) * 0b0..Not NACKed */ #define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) #define I3C_MSTATUS_IBITYPE_MASK (0xC0U) #define I3C_MSTATUS_IBITYPE_SHIFT (6U) /*! IBITYPE - In-Band Interrupt (IBI) Type * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) * 0b01..IBI * 0b10..CR * 0b11..HJ */ #define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) #define I3C_MSTATUS_SLVSTART_MASK (0x100U) #define I3C_MSTATUS_SLVSTART_SHIFT (8U) /*! SLVSTART - Target Start * 0b1..Target requesting START * 0b0..Target not requesting START * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) #define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) #define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - Controller Control Done * 0b1..Done * 0b0..Not done * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) #define I3C_MSTATUS_COMPLETE_MASK (0x400U) #define I3C_MSTATUS_COMPLETE_SHIFT (10U) /*! COMPLETE - Complete * 0b1..Complete * 0b0..Not complete * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) #define I3C_MSTATUS_RXPEND_MASK (0x800U) #define I3C_MSTATUS_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND * 0b1..Receive message pending * 0b0..No receive message pending */ #define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) #define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TX Buffer or FIFO Not Full * 0b1..Receive buffer or FIFO not full * 0b0..Receive buffer or FIFO full */ #define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) #define I3C_MSTATUS_IBIWON_MASK (0x2000U) #define I3C_MSTATUS_IBIWON_SHIFT (13U) /*! IBIWON - In-Band Interrupt (IBI) Won * 0b1..IBI arbitration won * 0b0..No IBI arbitration won * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) #define I3C_MSTATUS_ERRWARN_MASK (0x8000U) #define I3C_MSTATUS_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning * 0b1..Error or warning * 0b0..No error or warning */ #define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) #define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) #define I3C_MSTATUS_NOWMASTER_SHIFT (19U) /*! NOWMASTER - Module is now Controller * 0b1..Controller * 0b0..Not a controller * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) #define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) #define I3C_MSTATUS_IBIADDR_SHIFT (24U) /*! IBIADDR - IBI Address */ #define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) /*! @} */ /*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ /*! @{ */ #define I3C_MIBIRULES_ADDR0_MASK (0x3FU) #define I3C_MIBIRULES_ADDR0_SHIFT (0U) /*! ADDR0 - ADDR0 */ #define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) #define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) #define I3C_MIBIRULES_ADDR1_SHIFT (6U) /*! ADDR1 - ADDR1 */ #define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) #define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) #define I3C_MIBIRULES_ADDR2_SHIFT (12U) /*! ADDR2 - ADDR2 */ #define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) #define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) #define I3C_MIBIRULES_ADDR3_SHIFT (18U) /*! ADDR3 - ADDR3 */ #define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) #define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) #define I3C_MIBIRULES_ADDR4_SHIFT (24U) /*! ADDR4 - ADDR4 */ #define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) #define I3C_MIBIRULES_MSB0_MASK (0x40000000U) #define I3C_MIBIRULES_MSB0_SHIFT (30U) /*! MSB0 - Most Significant Address Bit is 0 * 0b1..MSB is 0 * 0b0..MSB is not 0 */ #define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) #define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) #define I3C_MIBIRULES_NOBYTE_SHIFT (31U) /*! NOBYTE - No IBI byte * 0b1..Without mandatory IBI byte * 0b0..With mandatory IBI byte */ #define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) /*! @} */ /*! @name MINTSET - Controller Interrupt Set */ /*! @{ */ #define I3C_MINTSET_SLVSTART_MASK (0x100U) #define I3C_MINTSET_SLVSTART_SHIFT (8U) /*! SLVSTART - Target Start Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) #define I3C_MINTSET_MCTRLDONE_MASK (0x200U) #define I3C_MINTSET_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - Controller Control Done Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) #define I3C_MINTSET_COMPLETE_MASK (0x400U) #define I3C_MINTSET_COMPLETE_SHIFT (10U) /*! COMPLETE - Completed Message Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) #define I3C_MINTSET_RXPEND_MASK (0x800U) #define I3C_MINTSET_RXPEND_SHIFT (11U) /*! RXPEND - Receive Pending Interrupt Enable */ #define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) #define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) #define I3C_MINTSET_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) #define I3C_MINTSET_IBIWON_MASK (0x2000U) #define I3C_MINTSET_IBIWON_SHIFT (13U) /*! IBIWON - IBI Won Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) #define I3C_MINTSET_ERRWARN_MASK (0x8000U) #define I3C_MINTSET_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) #define I3C_MINTSET_NOWMASTER_MASK (0x80000U) #define I3C_MINTSET_NOWMASTER_SHIFT (19U) /*! NOWMASTER - Now Controller Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) /*! @} */ /*! @name MINTCLR - Controller Interrupt Clear */ /*! @{ */ #define I3C_MINTCLR_SLVSTART_MASK (0x100U) #define I3C_MINTCLR_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) #define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) #define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) #define I3C_MINTCLR_COMPLETE_MASK (0x400U) #define I3C_MINTCLR_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) #define I3C_MINTCLR_RXPEND_MASK (0x800U) #define I3C_MINTCLR_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) #define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) #define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) #define I3C_MINTCLR_IBIWON_MASK (0x2000U) #define I3C_MINTCLR_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) #define I3C_MINTCLR_ERRWARN_MASK (0x8000U) #define I3C_MINTCLR_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) #define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) #define I3C_MINTCLR_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) /*! @} */ /*! @name MINTMASKED - Controller Interrupt Mask */ /*! @{ */ #define I3C_MINTMASKED_SLVSTART_MASK (0x100U) #define I3C_MINTMASKED_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) #define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) #define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) #define I3C_MINTMASKED_COMPLETE_MASK (0x400U) #define I3C_MINTMASKED_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) #define I3C_MINTMASKED_RXPEND_MASK (0x800U) #define I3C_MINTMASKED_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Mask */ #define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) #define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) #define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) #define I3C_MINTMASKED_IBIWON_MASK (0x2000U) #define I3C_MINTMASKED_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) #define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_MINTMASKED_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) #define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) #define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) /*! @} */ /*! @name MERRWARN - Controller Errors and Warnings */ /*! @{ */ #define I3C_MERRWARN_NACK_MASK (0x4U) #define I3C_MERRWARN_NACK_SHIFT (2U) /*! NACK - Not Acknowledge Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) #define I3C_MERRWARN_WRABT_MASK (0x8U) #define I3C_MERRWARN_WRABT_SHIFT (3U) /*! WRABT - Write Abort Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) #define I3C_MERRWARN_HPAR_MASK (0x200U) #define I3C_MERRWARN_HPAR_SHIFT (9U) /*! HPAR - High Data Rate Parity * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) #define I3C_MERRWARN_HCRC_MASK (0x400U) #define I3C_MERRWARN_HCRC_SHIFT (10U) /*! HCRC - High Data Rate CRC Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) #define I3C_MERRWARN_OREAD_MASK (0x10000U) #define I3C_MERRWARN_OREAD_SHIFT (16U) /*! OREAD - Overread Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) #define I3C_MERRWARN_OWRITE_MASK (0x20000U) #define I3C_MERRWARN_OWRITE_SHIFT (17U) /*! OWRITE - Overwrite Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) #define I3C_MERRWARN_MSGERR_MASK (0x40000U) #define I3C_MERRWARN_MSGERR_SHIFT (18U) /*! MSGERR - Message Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) #define I3C_MERRWARN_INVREQ_MASK (0x80000U) #define I3C_MERRWARN_INVREQ_SHIFT (19U) /*! INVREQ - Invalid Request Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) #define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) #define I3C_MERRWARN_TIMEOUT_SHIFT (20U) /*! TIMEOUT - Timeout Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) /*! @} */ /*! @name MDMACTRL - Controller DMA Control */ /*! @{ */ #define I3C_MDMACTRL_DMAFB_MASK (0x3U) #define I3C_MDMACTRL_DMAFB_SHIFT (0U) /*! DMAFB - DMA from Bus * 0b00..DMA not used * 0b01..Enable DMA for one frame * 0b10..Enable DMA until DMA is turned off * 0b11.. */ #define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) #define I3C_MDMACTRL_DMATB_MASK (0xCU) #define I3C_MDMACTRL_DMATB_SHIFT (2U) /*! DMATB - DMA to Bus * 0b00..DMA not used * 0b01..Enable DMA for one frame (ended by DMA or terminated) * 0b10..Enable DMA until DMA is turned off * 0b11.. */ #define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) #define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) #define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) /*! DMAWIDTH - DMA Width * 0b00, 0b01..Byte * 0b10..Halfword (16 bits) * 0b11.. */ #define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) /*! @} */ /*! @name MDATACTRL - Controller Data Control */ /*! @{ */ #define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) /*! FLUSHTB - Flush To-Bus Buffer or FIFO * 0b1..Flush the buffer * 0b0..No action */ #define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) #define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) /*! FLUSHFB - Flush From-Bus Buffer or FIFO * 0b1..Flush the buffer * 0b0..No action */ #define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) #define I3C_MDATACTRL_UNLOCK_MASK (0x8U) #define I3C_MDATACTRL_UNLOCK_SHIFT (3U) /*! UNLOCK - Unlock * 0b0..Locked * 0b1..Unlocked */ #define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) #define I3C_MDATACTRL_TXTRIG_MASK (0x30U) #define I3C_MDATACTRL_TXTRIG_SHIFT (4U) /*! TXTRIG - Transmit Trigger Level * 0b00..Trigger when empty * 0b01..Trigger when 1/4 full or less * 0b10..Trigger when 1/2 full or less * 0b11..Trigger when 1 less than full or less (default) */ #define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) #define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) #define I3C_MDATACTRL_RXTRIG_SHIFT (6U) /*! RXTRIG - Receive Trigger Level * 0b00..Trigger when not empty * 0b01..Trigger when 1/4 full or more * 0b10..Trigger when 1/2 full or more * 0b11..Trigger when 3/4 full or more */ #define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) #define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) #define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) /*! TXCOUNT - Transmit Byte Count */ #define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) #define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) #define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Receive Byte Count */ #define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) #define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_MDATACTRL_TXFULL_SHIFT (30U) /*! TXFULL - Transmit is Full * 0b0..Not full * 0b1..Full */ #define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) #define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) /*! RXEMPTY - Receive is Empty * 0b0..Not empty * 0b1..Empty */ #define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) /*! @} */ /*! @name MWDATAB - Controller Write Data Byte */ /*! @{ */ #define I3C_MWDATAB_VALUE_MASK (0xFFU) #define I3C_MWDATAB_VALUE_SHIFT (0U) /*! VALUE - Data Byte */ #define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) #define I3C_MWDATAB_END_MASK (0x100U) #define I3C_MWDATAB_END_SHIFT (8U) /*! END - End of Message * 0b0..Not the end * 0b1..End */ #define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) #define I3C_MWDATAB_END_ALSO_MASK (0x10000U) #define I3C_MWDATAB_END_ALSO_SHIFT (16U) /*! END_ALSO - End of Message ALSO * 0b0..Not the end * 0b1..End */ #define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) /*! @} */ /*! @name MWDATABE - Controller Write Data Byte End */ /*! @{ */ #define I3C_MWDATABE_VALUE_MASK (0xFFU) #define I3C_MWDATABE_VALUE_SHIFT (0U) /*! VALUE - Data */ #define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) /*! @} */ /*! @name MWDATAH - Controller Write Data Halfword */ /*! @{ */ #define I3C_MWDATAH_DATA0_MASK (0xFFU) #define I3C_MWDATAH_DATA0_SHIFT (0U) /*! DATA0 - Data Byte 0 */ #define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) #define I3C_MWDATAH_DATA1_MASK (0xFF00U) #define I3C_MWDATAH_DATA1_SHIFT (8U) /*! DATA1 - Data Byte 1 */ #define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) #define I3C_MWDATAH_END_MASK (0x10000U) #define I3C_MWDATAH_END_SHIFT (16U) /*! END - End of Message * 0b0..Not the end * 0b1..End */ #define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) /*! @} */ /*! @name MWDATAHE - Controller Write Data Halfword End */ /*! @{ */ #define I3C_MWDATAHE_DATA0_MASK (0xFFU) #define I3C_MWDATAHE_DATA0_SHIFT (0U) /*! DATA0 - Data Byte 0 */ #define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) #define I3C_MWDATAHE_DATA1_MASK (0xFF00U) #define I3C_MWDATAHE_DATA1_SHIFT (8U) /*! DATA1 - Data Byte 1 */ #define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) /*! @} */ /*! @name MRDATAB - Controller Read Data Byte */ /*! @{ */ #define I3C_MRDATAB_VALUE_MASK (0xFFU) #define I3C_MRDATAB_VALUE_SHIFT (0U) /*! VALUE - Value */ #define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) /*! @} */ /*! @name MRDATAH - Controller Read Data Halfword */ /*! @{ */ #define I3C_MRDATAH_LSB_MASK (0xFFU) #define I3C_MRDATAH_LSB_SHIFT (0U) /*! LSB - Low Byte */ #define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) #define I3C_MRDATAH_MSB_MASK (0xFF00U) #define I3C_MRDATAH_MSB_SHIFT (8U) /*! MSB - High Byte */ #define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) /*! @} */ /*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ /*! @{ */ #define I3C_MWDATAB1_VALUE_MASK (0xFFU) #define I3C_MWDATAB1_VALUE_SHIFT (0U) /*! VALUE - Value */ #define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) /*! @} */ /*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ /*! @{ */ #define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) #define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) /*! DIR - Direction * 0b0..Write * 0b1..Read */ #define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) #define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) #define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) /*! ADDR - Address */ #define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) #define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) #define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) /*! END - End of SDR Message * 0b0..Not the end * 0b1..End */ #define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) #define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) #define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) /*! I2C - I2C * 0b0..I3C message * 0b1..I2C message */ #define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) #define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) #define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) /*! LEN - Length */ #define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) /*! @} */ /*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ /*! @{ */ #define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) #define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) /*! DATA16B - Data */ #define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) /*! @} */ /*! @name MRMSG_SDR - Controller Read Message in SDR mode */ /*! @{ */ #define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) #define I3C_MRMSG_SDR_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) /*! @} */ /*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ /*! @{ */ #define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) #define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) /*! ADDRCMD - Address Command */ #define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) /*! @} */ /*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ /*! @{ */ #define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) #define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) /*! LEN - Length of Message */ #define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) #define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) #define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) /*! END - End of Message * 0b1..End * 0b0..Not the end */ #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) /*! @} */ /*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ /*! @{ */ #define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) #define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) /*! DATA16B - Data */ #define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) /*! @} */ /*! @name MRMSG_DDR - Controller Read Message in DDR mode */ /*! @{ */ #define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) #define I3C_MRMSG_DDR_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) /*! @} */ /*! @name MDYNADDR - Controller Dynamic Address */ /*! @{ */ #define I3C_MDYNADDR_DAVALID_MASK (0x1U) #define I3C_MDYNADDR_DAVALID_SHIFT (0U) /*! DAVALID - Dynamic Address Valid * 0b1..Valid DA assigned * 0b0..No valid DA assigned */ #define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) #define I3C_MDYNADDR_DADDR_MASK (0xFEU) #define I3C_MDYNADDR_DADDR_SHIFT (1U) /*! DADDR - Dynamic Address */ #define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) /*! @} */ /*! @name SMAPCTRL0 - Map Feature Control 0 */ /*! @{ */ #define I3C_SMAPCTRL0_ENA_MASK (0x1U) #define I3C_SMAPCTRL0_ENA_SHIFT (0U) /*! ENA - Enable Primary Dynamic Address * 0b0..Disabled * 0b1..Enabled */ #define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) #define I3C_SMAPCTRL0_DA_MASK (0xFEU) #define I3C_SMAPCTRL0_DA_SHIFT (1U) /*! DA - Dynamic Address */ #define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) #define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) #define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) /*! CAUSE - Cause * 0b000..No information (this value occurs when not configured to write DA) * 0b001..Set using ENTDAA * 0b010..Set using SETDASA, SETAASA, or SETNEWDA * 0b011..Cleared using RSTDAA * 0b100..Auto MAP change happened last * *.. */ #define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) /*! @} */ /*! @name IBIEXT1 - Extended IBI Data 1 */ /*! @{ */ #define I3C_IBIEXT1_CNT_MASK (0x7U) #define I3C_IBIEXT1_CNT_SHIFT (0U) /*! CNT - Count */ #define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) #define I3C_IBIEXT1_MAX_MASK (0x70U) #define I3C_IBIEXT1_MAX_SHIFT (4U) /*! MAX - Maximum */ #define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) #define I3C_IBIEXT1_EXT1_MASK (0xFF00U) #define I3C_IBIEXT1_EXT1_SHIFT (8U) /*! EXT1 - Extra Byte 1 */ #define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) #define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) #define I3C_IBIEXT1_EXT2_SHIFT (16U) /*! EXT2 - Extra Byte 2 */ #define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) #define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) #define I3C_IBIEXT1_EXT3_SHIFT (24U) /*! EXT3 - Extra Byte 3 */ #define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) /*! @} */ /*! @name IBIEXT2 - Extended IBI Data 2 */ /*! @{ */ #define I3C_IBIEXT2_EXT4_MASK (0xFFU) #define I3C_IBIEXT2_EXT4_SHIFT (0U) /*! EXT4 - Extra Byte 4 */ #define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) #define I3C_IBIEXT2_EXT5_MASK (0xFF00U) #define I3C_IBIEXT2_EXT5_SHIFT (8U) /*! EXT5 - Extra Byte 5 */ #define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) #define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) #define I3C_IBIEXT2_EXT6_SHIFT (16U) /*! EXT6 - Extra Byte 6 */ #define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) #define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) #define I3C_IBIEXT2_EXT7_SHIFT (24U) /*! EXT7 - Extra Byte 7 */ #define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) /*! @} */ /*! @name SID - Target Module ID */ /*! @{ */ #define I3C_SID_ID_MASK (0xFFFFFFFFU) #define I3C_SID_ID_SHIFT (0U) /*! ID - ID */ #define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK) /*! @} */ /*! * @} */ /* end of group I3C_Register_Masks */ /* I3C - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral I3C0 base address */ #define I3C0_BASE (0x50021000u) /** Peripheral I3C0 base address */ #define I3C0_BASE_NS (0x40021000u) /** Peripheral I3C0 base pointer */ #define I3C0 ((I3C_Type *)I3C0_BASE) /** Peripheral I3C0 base pointer */ #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) /** Peripheral I3C1 base address */ #define I3C1_BASE (0x50022000u) /** Peripheral I3C1 base address */ #define I3C1_BASE_NS (0x40022000u) /** Peripheral I3C1 base pointer */ #define I3C1 ((I3C_Type *)I3C1_BASE) /** Peripheral I3C1 base pointer */ #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) /** Array initializer of I3C peripheral base addresses */ #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } /** Array initializer of I3C peripheral base pointers */ #define I3C_BASE_PTRS { I3C0, I3C1 } /** Array initializer of I3C peripheral base addresses */ #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } /** Array initializer of I3C peripheral base pointers */ #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } #else /** Peripheral I3C0 base address */ #define I3C0_BASE (0x40021000u) /** Peripheral I3C0 base pointer */ #define I3C0 ((I3C_Type *)I3C0_BASE) /** Peripheral I3C1 base address */ #define I3C1_BASE (0x40022000u) /** Peripheral I3C1 base pointer */ #define I3C1 ((I3C_Type *)I3C1_BASE) /** Array initializer of I3C peripheral base addresses */ #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } /** Array initializer of I3C peripheral base pointers */ #define I3C_BASE_PTRS { I3C0, I3C1 } #endif /** Interrupt vectors for the I3C peripheral type */ #define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } /*! * @} */ /* end of group I3C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- INPUTMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer * @{ */ /** INPUTMUX - Register Layout Typedef */ typedef struct { __IO uint32_t SCT0_INMUX[8]; /**< Inputmux Register for SCT0 Input, array offset: 0x0, array step: 0x4 */ __IO uint32_t CTIMER0CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x20 */ __IO uint32_t CTIMER0CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x24 */ __IO uint32_t CTIMER0CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x28 */ __IO uint32_t CTIMER0CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x2C */ __IO uint32_t TIMER0TRIG; /**< Trigger Register for CTIMER, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t CTIMER1CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x40 */ __IO uint32_t CTIMER1CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x44 */ __IO uint32_t CTIMER1CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x48 */ __IO uint32_t CTIMER1CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x4C */ __IO uint32_t TIMER1TRIG; /**< Trigger Register for CTIMER, offset: 0x50 */ uint8_t RESERVED_1[12]; __IO uint32_t CTIMER2CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x60 */ __IO uint32_t CTIMER2CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x64 */ __IO uint32_t CTIMER2CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x68 */ __IO uint32_t CTIMER2CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x6C */ __IO uint32_t TIMER2TRIG; /**< Trigger Register for CTIMER, offset: 0x70 */ uint8_t RESERVED_2[44]; __IO uint32_t SMARTDMAARCHB_INMUX[8]; /**< Inputmux Register for SMARTDMA Arch B Inputs, array offset: 0xA0, array step: 0x4 */ __IO uint32_t PINTSEL[8]; /**< Pin Interrupt Select, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_3[160]; __IO uint32_t FREQMEAS_REF; /**< Selection for Frequency Measurement Reference Clock, offset: 0x180 */ __IO uint32_t FREQMEAS_TAR; /**< Selection for Frequency Measurement Target Clock, offset: 0x184 */ uint8_t RESERVED_4[24]; __IO uint32_t CTIMER3CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A0 */ __IO uint32_t CTIMER3CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A4 */ __IO uint32_t CTIMER3CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A8 */ __IO uint32_t CTIMER3CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1AC */ __IO uint32_t TIMER3TRIG; /**< Trigger Register for CTIMER, offset: 0x1B0 */ uint8_t RESERVED_5[12]; __IO uint32_t CTIMER4CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C0 */ __IO uint32_t CTIMER4CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C4 */ __IO uint32_t CTIMER4CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C8 */ __IO uint32_t CTIMER4CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1CC */ __IO uint32_t TIMER4TRIG; /**< Trigger Register for CTIMER, offset: 0x1D0 */ uint8_t RESERVED_6[140]; __IO uint32_t CMP0_TRIG; /**< CMP0 Input Connections, offset: 0x260 */ uint8_t RESERVED_7[28]; __IO uint32_t ADC0_TRIG[4]; /**< ADC Trigger Input Connections, array offset: 0x280, array step: 0x4 */ uint8_t RESERVED_8[48]; __IO uint32_t ADC1_TRIG[4]; /**< ADC Trigger Input Connections, array offset: 0x2C0, array step: 0x4 */ uint8_t RESERVED_9[48]; __IO uint32_t DAC0_TRIG; /**< DAC0 Trigger Inputs, offset: 0x300 */ uint8_t RESERVED_10[28]; __IO uint32_t DAC1_TRIG; /**< DAC1 Trigger Inputs, offset: 0x320 */ uint8_t RESERVED_11[28]; __IO uint32_t DAC2_TRIG; /**< DAC2 Trigger Inputs, offset: 0x340 */ uint8_t RESERVED_12[28]; struct { /* offset: 0x360, array step: 0x20 */ __IO uint32_t QDC_TRIG; /**< QDC0 Trigger Input Connections..QDC1 Trigger Input Connections, array offset: 0x360, array step: 0x20 */ __IO uint32_t QDC_HOME; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x364, array step: 0x20 */ __IO uint32_t QDC_INDEX; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x368, array step: 0x20 */ __IO uint32_t QDC_PHASEB; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x36C, array step: 0x20 */ __IO uint32_t QDC_PHASEA; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x370, array step: 0x20 */ uint8_t RESERVED_0[12]; } QDCN[2]; __IO uint32_t FLEXPWM0_SM_EXTSYNC[4]; /**< PWM0 External Synchronization, array offset: 0x3A0, array step: 0x4 */ __IO uint32_t FLEXPWM0_SM_EXTA[4]; /**< PWM0 Input Trigger Connections, array offset: 0x3B0, array step: 0x4 */ __IO uint32_t FLEXPWM0_EXTFORCE; /**< PWM0 External Force Trigger Connections, offset: 0x3C0 */ __IO uint32_t FLEXPWM0_FAULT[4]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C4, array step: 0x4 */ uint8_t RESERVED_13[12]; __IO uint32_t FLEXPWM1_SM_EXTSYNC[4]; /**< PWM1 External Synchronization, array offset: 0x3E0, array step: 0x4 */ __IO uint32_t FLEXPWM1_SM_EXTA[4]; /**< PWM1 Input EXTA Connections, array offset: 0x3F0, array step: 0x4 */ __IO uint32_t FLEXPWM1_EXTFORCE; /**< PWM1 External Force Trigger Connections, offset: 0x400 */ __IO uint32_t FLEXPWM1_FAULT[4]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x404, array step: 0x4 */ uint8_t RESERVED_14[12]; __IO uint32_t PWM0_EXT_CLK; /**< PWM0 External Clock Trigger, offset: 0x420 */ __IO uint32_t PWM1_EXT_CLK; /**< PWM1 External Clock Trigger, offset: 0x424 */ uint8_t RESERVED_15[24]; __IO uint32_t EVTG_TRIG[16]; /**< EVTG Trigger Input Connections, array offset: 0x440, array step: 0x4 */ __IO uint32_t USBFS_TRIG; /**< USB-FS Trigger Input Connections, offset: 0x480 */ uint8_t RESERVED_16[28]; __IO uint32_t TSI_TRIG; /**< TSI Trigger Input Connections, offset: 0x4A0 */ uint8_t RESERVED_17[28]; __IO uint32_t EXT_TRIG[8]; /**< EXT Trigger Connections, array offset: 0x4C0, array step: 0x4 */ __IO uint32_t CMP1_TRIG; /**< CMP1 Input Connections, offset: 0x4E0 */ uint8_t RESERVED_18[28]; __IO uint32_t CMP2_TRIG; /**< CMP2 Input Connections, offset: 0x500 */ uint8_t RESERVED_19[28]; __IO uint32_t SINC_FILTER_CH[5]; /**< SINC Filter Channel Trigger Input Connections, array offset: 0x520, array step: 0x4 */ uint8_t RESERVED_20[76]; __IO uint32_t OPAMP_TRIG[3]; /**< OPAMP Trigger Input Connections, array offset: 0x580, array step: 0x4 */ uint8_t RESERVED_21[20]; __IO uint32_t FLEXCOMM0_TRIG; /**< LP_FLEXCOMM0 Trigger Input Connections, offset: 0x5A0 */ uint8_t RESERVED_22[28]; __IO uint32_t FLEXCOMM1_TRIG; /**< LP_FLEXCOMM1 Trigger Input Connections, offset: 0x5C0 */ uint8_t RESERVED_23[28]; __IO uint32_t FLEXCOMM2_TRIG; /**< LP_FLEXCOMM2 Trigger Input Connections, offset: 0x5E0 */ uint8_t RESERVED_24[28]; __IO uint32_t FLEXCOMM3_TRIG; /**< LP_FLEXCOMM3 Trigger Input Connections, offset: 0x600 */ uint8_t RESERVED_25[28]; __IO uint32_t FLEXCOMM4_TRIG; /**< LP_FLEXCOMM4 Trigger Input Connections, offset: 0x620 */ uint8_t RESERVED_26[28]; __IO uint32_t FLEXCOMM5_TRIG; /**< LP_FLEXCOMM5 Trigger Input Connections, offset: 0x640 */ uint8_t RESERVED_27[28]; __IO uint32_t FLEXCOMM6_TRIG; /**< LP_FLEXCOMM6 Trigger Input Connections, offset: 0x660 */ uint8_t RESERVED_28[28]; __IO uint32_t FLEXCOMM7_TRIG; /**< LP_FLEXCOMM7 Trigger Input Connections, offset: 0x680 */ uint8_t RESERVED_29[28]; __IO uint32_t FLEXCOMM8_TRIG; /**< LP_FLEXCOMM8 Trigger Input Connections, offset: 0x6A0 */ uint8_t RESERVED_30[28]; __IO uint32_t FLEXCOMM9_TRIG; /**< LP_FLEXCOMM9 Trigger Input Connections, offset: 0x6C0 */ uint8_t RESERVED_31[28]; __IO uint32_t FLEXIO_TRIG[8]; /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */ __IO uint32_t DMA0_REQ_ENABLE0; /**< DMA0 Request Enable0, offset: 0x700 */ __O uint32_t DMA0_REQ_ENABLE0_SET; /**< DMA0 Request Enable0, offset: 0x704 */ __O uint32_t DMA0_REQ_ENABLE0_CLR; /**< DMA0 Request Enable0, offset: 0x708 */ __O uint32_t DMA0_REQ_ENABLE0_TOG; /**< DMA0 Request Enable0, offset: 0x70C */ __IO uint32_t DMA0_REQ_ENABLE1; /**< DMA0 Request Enable1, offset: 0x710 */ __O uint32_t DMA0_REQ_ENABLE1_SET; /**< DMA0 Request Enable1, offset: 0x714 */ __O uint32_t DMA0_REQ_ENABLE1_CLR; /**< DMA0 Request Enable1, offset: 0x718 */ __O uint32_t DMA0_REQ_ENABLE1_TOG; /**< DMA0 Request Enable1, offset: 0x71C */ __IO uint32_t DMA0_REQ_ENABLE2; /**< DMA0 Request Enable2, offset: 0x720 */ __O uint32_t DMA0_REQ_ENABLE2_SET; /**< DMA0 Request Enable2, offset: 0x724 */ __O uint32_t DMA0_REQ_ENABLE2_CLR; /**< DMA0 Request Enable2, offset: 0x728 */ __O uint32_t DMA0_REQ_ENABLE2_TOG; /**< DMA0 Request Enable2, offset: 0x72C */ __IO uint32_t DMA0_REQ_ENABLE3; /**< DMA0 Request Enable3, offset: 0x730 */ __O uint32_t DMA0_REQ_ENABLE3_SET; /**< DMA0 Request Enable3, offset: 0x734 */ __O uint32_t DMA0_REQ_ENABLE3_CLR; /**< DMA0 Request Enable3, offset: 0x738 */ uint8_t RESERVED_32[68]; __IO uint32_t DMA1_REQ_ENABLE0; /**< DMA1 Request Enable0, offset: 0x780 */ __O uint32_t DMA1_REQ_ENABLE0_SET; /**< DMA1 Request Enable0, offset: 0x784 */ __O uint32_t DMA1_REQ_ENABLE0_CLR; /**< DMA1 Request Enable0, offset: 0x788 */ __O uint32_t DMA1_REQ_ENABLE0_TOG; /**< DMA1 Request Enable0, offset: 0x78C */ __IO uint32_t DMA1_REQ_ENABLE1; /**< DMA1 Request Enable1, offset: 0x790 */ __O uint32_t DMA1_REQ_ENABLE1_SET; /**< DMA1 Request Enable1, offset: 0x794 */ __O uint32_t DMA1_REQ_ENABLE1_CLR; /**< DMA1 Request Enable1, offset: 0x798 */ __O uint32_t DMA1_REQ_ENABLE1_TOG; /**< DMA1 Request Enable1, offset: 0x79C */ __IO uint32_t DMA1_REQ_ENABLE2; /**< DMA1 Request Enable2, offset: 0x7A0 */ __O uint32_t DMA1_REQ_ENABLE2_SET; /**< DMA1 Request Enable2, offset: 0x7A4 */ __O uint32_t DMA1_REQ_ENABLE2_CLR; /**< DMA1 Request Enable2, offset: 0x7A8 */ __O uint32_t DMA1_REQ_ENABLE2_TOG; /**< DMA1 Request Enable2, offset: 0x7AC */ __IO uint32_t DMA1_REQ_ENABLE3; /**< DMA1 Request Enable3, offset: 0x7B0 */ __O uint32_t DMA1_REQ_ENABLE3_SET; /**< DMA1 Request Enable3, offset: 0x7B4 */ __O uint32_t DMA1_REQ_ENABLE3_CLR; /**< DMA1 Request Enable3, offset: 0x7B8 */ } INPUTMUX_Type; /* ---------------------------------------------------------------------------- -- INPUTMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks * @{ */ /*! @name INPUTMUX_SCT0_SCT0_INMUX - Inputmux Register for SCT0 Input */ /*! @{ */ #define INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP_MASK (0x7FU) #define INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP_SHIFT (0U) /*! INP - Input number to SCT0 inputs. * 0b0000000..SCT0_IN0 input is selected * 0b0000001..SCT0_IN1 input is selected * 0b0000010..SCT0_IN2 input is selected * 0b0000011..SCT0_IN3 input is selected * 0b0000100..SCT0_IN4 input is selected * 0b0000101..SCT0_IN5 input is selected * 0b0000110..SCT0_IN6 input is selected * 0b0000111..SCT0_IN7 input is selected * 0b0001000..CTIMER0_MAT0 input is selected * 0b0001001..CTIMER1_MAT0 input is selected * 0b0001010..CTIMER2_MAT0 input is selected * 0b0001011..CTIMER3_MAT0 input is selected * 0b0001100..CTIMER4_MAT0 input is selected * 0b0001101..ADC0 ADC0_IRQ input is selected * 0b0001110..PINT GPIO_INT_BMAT input is selected * 0b0001111..usb0 start of frame input is selected * 0b0010000..usb1 start of frame input is selected * 0b0010001..SINC Filter CH0 Conversion Complete input is selected * 0b0010010..SINC Filter CH1 Conversion Complete input is selected * 0b0010011..SINC Filter CH2 Conversion Complete input is selected * 0b0010100..SINC Filter CH3 Conversion Complete input is selected * 0b0010101..SINC Filter CH4 Conversion Complete input is selected * 0b0010110..Reserved * 0b0010111..DEBUG_HALTED input is selected * 0b0011000..ADC1_IRQ input is selected * 0b0011001..ADC0_tcomp[0] input is selected * 0b0011010..ADC0_tcomp[1] input is selected * 0b0011011..ADC0_tcomp[2] input is selected * 0b0011100..ADC0_tcomp[3] input is selected * 0b0011101..ADC1_tcomp[0] input is selected * 0b0011110..ADC1_tcomp[1] input is selected * 0b0011111..ADC1_tcomp[2] input is selected * 0b0100000..ADC1_tcomp[3] input is selected * 0b0100001..CMP0_OUT input is selected * 0b0100010..CMP1_OUT input is selected * 0b0100011..CMP2_OUT input is selected * 0b0100100..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0100101..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100110..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100111..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0101000..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0101001..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0101010..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0101011..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0101100..QDC0_CMP/POS_MATCH input is selected * 0b0101101..QDC1_CMP/POS_MATCH input is selected * 0b0101110..EVTG_OUT0A input is selected * 0b0101111..EVTG_OUT0B input is selected * 0b0110000..EVTG_OUT1A input is selected * 0b0110001..EVTG_OUT1B input is selected * 0b0110010..EVTG_OUT2A input is selected * 0b0110011..EVTG_OUT2B input is selected * 0b0110100..EVTG_OUT3A input is selected * 0b0110101..EVTG_OUT3B input is selected * 0b0110110..FC3_P0 (SDO, SDA) input is selected * 0b0110111..FC3_P1 (SCK, TXD, SCL) input is selected * 0b0111000..FC3_P2 (RTS, SCLS, TXD) input is selected * 0b0111001..FC3_P3 (PCS[0], CTS, SDAS) input is selected * 0b0111010..Reserved * 0b0111011..Reserved * 0b0111100..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected * 0b0111101..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected * 0b0111110..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected * 0b0111111..LP_FLEXCOMM1 trig 0 input is selected * 0b1000000..LP_FLEXCOMM1 trig 1 input is selected * 0b1000001..LP_FLEXCOMM1 trig 2 input is selected * 0b1000010..LP_FLEXCOMM2 trig 0 input is selected * 0b1000011..LP_FLEXCOMM2 trig 1 input is selected * 0b1000100..LP_FLEXCOMM2 trig 2 input is selected * 0b1000101..LP_FLEXCOMM3 trig 0 input is selected * 0b1000110..LP_FLEXCOMM3 trig 1 input is selected * 0b1000111..LP_FLEXCOMM3 trig 2 input is selected * 0b1001000..LP_FLEXCOMM3 trig 3 input is selected * 0b1001001..SAI0 TX BCLK input is selected * 0b1001010..SAI0 RX BCLK input is selected * 0b1001011..SAI1 TX BCLK input is selected * 0b1001100..SAI1 RX BCLK input is selected * *.. */ #define INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP_SHIFT)) & INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_INP_MASK) /*! @} */ /* The count of INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX */ #define INPUTMUX_INPUTMUX_SCT0_SCT0_INMUX_COUNT (8U) /*! @name CTIMER0CAP0 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER0CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP0_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP0_INP_SHIFT)) & INPUTMUX_CTIMER0CAP0_INP_MASK) /*! @} */ /*! @name CTIMER0CAP1 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER0CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP1_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP1_INP_SHIFT)) & INPUTMUX_CTIMER0CAP1_INP_MASK) /*! @} */ /*! @name CTIMER0CAP2 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER0CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP2_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP2_INP_SHIFT)) & INPUTMUX_CTIMER0CAP2_INP_MASK) /*! @} */ /*! @name CTIMER0CAP3 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER0CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP3_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP3_INP_SHIFT)) & INPUTMUX_CTIMER0CAP3_INP_MASK) /*! @} */ /*! @name TIMER0TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) /*! @} */ /*! @name CTIMER1CAP0 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER1CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP0_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP0_INP_SHIFT)) & INPUTMUX_CTIMER1CAP0_INP_MASK) /*! @} */ /*! @name CTIMER1CAP1 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER1CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP1_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP1_INP_SHIFT)) & INPUTMUX_CTIMER1CAP1_INP_MASK) /*! @} */ /*! @name CTIMER1CAP2 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER1CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP2_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP2_INP_SHIFT)) & INPUTMUX_CTIMER1CAP2_INP_MASK) /*! @} */ /*! @name CTIMER1CAP3 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER1CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP3_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP3_INP_SHIFT)) & INPUTMUX_CTIMER1CAP3_INP_MASK) /*! @} */ /*! @name TIMER1TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) /*! @} */ /*! @name CTIMER2CAP0 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER2CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP0_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP0_INP_SHIFT)) & INPUTMUX_CTIMER2CAP0_INP_MASK) /*! @} */ /*! @name CTIMER2CAP1 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER2CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP1_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP1_INP_SHIFT)) & INPUTMUX_CTIMER2CAP1_INP_MASK) /*! @} */ /*! @name CTIMER2CAP2 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER2CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP2_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP2_INP_SHIFT)) & INPUTMUX_CTIMER2CAP2_INP_MASK) /*! @} */ /*! @name CTIMER2CAP3 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER2CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP3_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP3_INP_SHIFT)) & INPUTMUX_CTIMER2CAP3_INP_MASK) /*! @} */ /*! @name TIMER2TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) /*! @} */ /*! @name INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX - Inputmux Register for SMARTDMA Arch B Inputs */ /*! @{ */ #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK (0x7FU) #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT (0U) /*! INP - Input number select to SmartDMA ARCHB input * 0b0000000..FlexIO interrupt is selected as input * 0b0000001..GPIO P0_1 input is selected * 0b0000010..GPIO P0_2 input is selected * 0b0000011..GPIO P0_3 input is selected * 0b0000100..GPIO P0_4 input is selected * 0b0000101..GPIO P0_5 input is selected * 0b0000110..GPIO P0_6 input is selected * 0b0000111..GPIO P0_7 input is selected * 0b0001000..GPIO P0_8 input is selected * 0b0001001..GPIO P0_9 input is selected * 0b0001010..GPIO P0_10 input is selected * 0b0001011..GPIO P0_11 input is selected * 0b0001100..GPIO P0_12 input is selected * 0b0001101..GPIO P0_13 input is selected * 0b0001110..GPIO P0_14 input is selected * 0b0001111..GPIO P0_15 input is selected * 0b0010000..SCT0 SCT_OUT8 input is selected * 0b0010001..SCT0 SCT_OUT9 input is selected * 0b0010010..Reserved * 0b0010011..Reserved * 0b0010100..MRT0 MRT_CH0_IRQ input is selected * 0b0010101..MRT0 MRT_CH1_IRQ input is selected * 0b0010110..CTIMER4_MAT3 input is selected * 0b0010111..CTIMER4_MAT2 input is selected * 0b0011000..CTIMER3_MAT3 input is selected * 0b0011001..CTIMER3_MAT2 input is selected * 0b0011010..CTIMER1_MAT3 input is selected * 0b0011011..CTIMER1_MAT2 input is selected * 0b0011100..UTICK0 UTICK_IRQ input is selected * 0b0011101..WWDT0 WDT0_IRQ input is selected * 0b0011110..ADC0 ADC0_IRQ input is selected * 0b0011111..CMP0_IRQ input is selected * 0b0100000..Reserved * 0b0100001..LP_FLEXCOMM7_IRQ input is selected * 0b0100010..LP_FLEXCOMM6_IRQ input is selected * 0b0100011..LP_FLEXCOMM5_IRQ input is selected * 0b0100100..LP_FLEXCOMM4_IRQ input is selected * 0b0100101..LP_FLEXCOMM3_IRQ input is selected * 0b0100110..LP_FLEXCOMM2_IRQ input is selected * 0b0100111..LP_FLEXCOMM1_IRQ input is selected * 0b0101000..LP_FLEXCOMM0_IRQ input is selected * 0b0101001..DMA0_IRQ input is selected * 0b0101010..DMA1_IRQ input is selected * 0b0101011..SYS_IRQSYS_IRQ combines the CDOG IRQ, WWDT IRQ, MBC secure violation IRQ, Secure AHB Matrix secure * violation IRQ, GDET IRQ, ELS S50 error IRQ, PKC error IRQ, and VBAT IRQ using the logical OR * operation. input is selected * 0b0101100..RTC_COMBO_IRQ input is selected * 0b0101101..ARM_TXEV input is selected * 0b0101110..PINT0 GPIO_INT_BMATCH input is selected * 0b0101111..Reserved * 0b0110000..Reserved * 0b0110001..CMP0_OUT input is selected * 0b0110010..usb0 start of frame input is selected * 0b0110011..usb1 start of frame input is selected * 0b0110100..OSTIMER0 OS_EVENT_TIMER_IRQ input is selected * 0b0110101..ADC1_IRQ input is selected * 0b0110110..CMP0_IRQ/CMP1_IRQ/CMP2_IRQ input is selected * 0b0110111..DAC0_IRQ input is selected * 0b0111000..DAC1_IRQ/DAC2_IRQ input is selected * 0b0111001..PWM0_IRQ input is selected * 0b0111010..PWM1_IRQ input is selected * 0b0111011..QDC0_IRQ input is selected * 0b0111100..QDC1_IRQ input is selected * 0b0111101..EVTG_OUT0A input is selected * 0b0111110..EVTG_OUT1A input is selected * 0b0111111..Reserved * 0b1000000..Reserved * 0b1000001..GPIO1_alias0 GPIO1 Pin Event Trig 0 input is selected * 0b1000010..GPIO1_alias1 GPIO1 Pin Event Trig 1 input is selected * 0b1000011..GPIO2_alias0 GPIO2 Pin Event Trig 0 input is selected * 0b1000100..GPIO2_alias1 GPIO2 Pin Event Trig 1 input is selected * 0b1000101..GPIO3_alias0 GPIO3 Pin Event Trig 0 input is selected * 0b1000110..GPIO3_alias1 GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT)) & INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK) /*! @} */ /* The count of INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX */ #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_COUNT (8U) /*! @name INPUTMUX_GPIO_INT_PINTSEL - Pin Interrupt Select */ /*! @{ */ #define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK (0x7FU) #define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT (0U) /*! INP - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INP = (x * * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. * 0b0000000..GPIO P0_0 input is selected * 0b0000001..GPIO P0_1 input is selected * 0b0000010..GPIO P0_2 input is selected * 0b0000011..GPIO P0_3 input is selected * 0b0000100..GPIO P0_4 input is selected * 0b0000101..GPIO P0_5 input is selected * 0b0000110..GPIO P0_6 input is selected * 0b0000111..GPIO P0_7 input is selected * 0b0001000..GPIO P0_8 input is selected * 0b0001001..GPIO P0_9 input is selected * 0b0001010..GPIO P0_10 input is selected * 0b0001011..GPIO P0_11 input is selected * 0b0001100..GPIO P0_12 input is selected * 0b0001101..GPIO P0_13 input is selected * 0b0001110..GPIO P0_14 input is selected * 0b0001111..GPIO P0_15 input is selected * 0b0010000..GPIO P0_16 input is selected * 0b0010001..GPIO P0_17 input is selected * 0b0010010..GPIO P0_18 input is selected * 0b0010011..GPIO P0_19 input is selected * 0b0010100..GPIO P0_20 input is selected * 0b0010101..GPIO P0_21 input is selected * 0b0010110..GPIO P0_22 input is selected * 0b0010111..GPIO P0_23 input is selected * 0b0011000..GPIO P0_24 input is selected * 0b0011001..GPIO P0_25 input is selected * 0b0011010..GPIO P0_26 input is selected * 0b0011011..GPIO P0_27 input is selected * 0b0011100..GPIO P0_28 input is selected * 0b0011101..GPIO P0_29 input is selected * 0b0011110..GPIO P0_30 input is selected * 0b0011111..GPIO P0_31 input is selected * 0b0100000..GPIO P1_0 input is selected * 0b0100001..GPIO P1_1 input is selected * 0b0100010..GPIO P1_2 input is selected * 0b0100011..GPIO P1_3 input is selected * 0b0100100..GPIO P1_4 input is selected * 0b0100101..GPIO P1_5 input is selected * 0b0100110..GPIO P1_6 input is selected * 0b0100111..GPIO P1_7 input is selected * 0b0101000..GPIO P1_8 input is selected * 0b0101001..GPIO P1_9 input is selected * 0b0101010..GPIO P1_10 input is selected * 0b0101011..GPIO P1_11 input is selected * 0b0101100..GPIO P1_12 input is selected * 0b0101101..GPIO P1_13 input is selected * 0b0101110..GPIO P1_14 input is selected * 0b0101111..GPIO P1_15 input is selected * 0b0110000..GPIO P1_16 input is selected * 0b0110001..GPIO P1_17 input is selected * 0b0110010..GPIO P1_18 input is selected * 0b0110011..GPIO P1_19 input is selected * 0b0110100..GPIO P1_20 input is selected * 0b0110101..GPIO P1_21 input is selected * 0b0110110..GPIO P1_22 input is selected * 0b0110111..GPIO P1_23 input is selected * 0b0111000..Reserved * 0b0111001..Reserved * 0b0111010..Reserved * 0b0111011..Reserved * 0b0111100..Reserved * 0b0111101..Reserved * 0b0111110..GPIO P1_30 input is selected * 0b0111111..GPIO P1_31 input is selected * *.. */ #define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT)) & INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK) /*! @} */ /* The count of INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL */ #define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_COUNT (8U) /*! @name FREQMEAS_REF - Selection for Frequency Measurement Reference Clock */ /*! @{ */ #define INPUTMUX_FREQMEAS_REF_INP_MASK (0x3FU) #define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) /*! INP - Clock source number (binary value) for frequency measure function reference clock. * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected * 0b000001..FRO_12M input is selected * 0b000010..FRO_144M input is selected * 0b000011..Reserved * 0b000100..OSC_32K input is selected * 0b000101..CPU/system_clk input is selected * 0b000110..FREQME_CLK_IN0 input is selected * 0b000111..FREQME_CLK_IN1 input is selected * 0b001000..EVTG_OUT0A input is selected * 0b001001..EVTG_OUT1A input is selected * *.. */ #define INPUTMUX_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK) /*! @} */ /*! @name FREQMEAS_TAR - Selection for Frequency Measurement Target Clock */ /*! @{ */ #define INPUTMUX_FREQMEAS_TAR_INP_MASK (0x3FU) #define INPUTMUX_FREQMEAS_TAR_INP_SHIFT (0U) /*! INP - Clock source number (binary value) for frequency measure function target clock. * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected * 0b000001..FRO_12M input is selected * 0b000010..FRO_144M input is selected * 0b000011..Reserved * 0b000100..OSC_32K input is selected * 0b000101..CPU/system_clk input is selected * 0b000110..FREQME_CLK_IN0 input is selected * 0b000111..FREQME_CLK_IN1 input is selected * 0b001000..EVTG_OUT0A input is selected * 0b001001..EVTG_OUT1A input is selected * *.. */ #define INPUTMUX_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK) /*! @} */ /*! @name CTIMER3CAP0 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER3CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP0_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP0_INP_SHIFT)) & INPUTMUX_CTIMER3CAP0_INP_MASK) /*! @} */ /*! @name CTIMER3CAP1 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER3CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP1_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP1_INP_SHIFT)) & INPUTMUX_CTIMER3CAP1_INP_MASK) /*! @} */ /*! @name CTIMER3CAP2 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER3CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP2_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP2_INP_SHIFT)) & INPUTMUX_CTIMER3CAP2_INP_MASK) /*! @} */ /*! @name CTIMER3CAP3 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER3CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP3_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP3_INP_SHIFT)) & INPUTMUX_CTIMER3CAP3_INP_MASK) /*! @} */ /*! @name TIMER3TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER3TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER3TRIG_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER3TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK) /*! @} */ /*! @name CTIMER4CAP0 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER4CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP0_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP0_INP_SHIFT)) & INPUTMUX_CTIMER4CAP0_INP_MASK) /*! @} */ /*! @name CTIMER4CAP1 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER4CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP1_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP1_INP_SHIFT)) & INPUTMUX_CTIMER4CAP1_INP_MASK) /*! @} */ /*! @name CTIMER4CAP2 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER4CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP2_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP2_INP_SHIFT)) & INPUTMUX_CTIMER4CAP2_INP_MASK) /*! @} */ /*! @name CTIMER4CAP3 - Capture Select Register for CTIMER Inputs */ /*! @{ */ #define INPUTMUX_CTIMER4CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP3_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP3_INP_SHIFT)) & INPUTMUX_CTIMER4CAP3_INP_MASK) /*! @} */ /*! @name TIMER4TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER4TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER4TRIG_INP_SHIFT (0U) /*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected * 0b0000011..CT_INP3 input is selected * 0b0000100..CT_INP4 input is selected * 0b0000101..CT_INP5 input is selected * 0b0000110..CT_INP6 input is selected * 0b0000111..CT_INP7 input is selected * 0b0001000..CT_INP8 input is selected * 0b0001001..CT_INP9 input is selected * 0b0001010..CT_INP10 input is selected * 0b0001011..CT_INP11 input is selected * 0b0001100..CT_INP12 input is selected * 0b0001101..CT_INP13 input is selected * 0b0001110..CT_INP14 input is selected * 0b0001111..CT_INP15 input is selected * 0b0010000..CT_INP16 input is selected * 0b0010001..CT_INP17 input is selected * 0b0010010..CT_INP18 input is selected * 0b0010011..CT_INP19 input is selected * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b0100110..QDC0_CMP/POS_MATCH input is selected * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected * 0b0101011..EVTG_OUT1B input is selected * 0b0101100..EVTG_OUT2A input is selected * 0b0101101..EVTG_OUT2B input is selected * 0b0101110..EVTG_OUT3A input is selected * 0b0101111..EVTG_OUT3B input is selected * 0b0110000..Reserved * 0b0110001..Reserved * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER4TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK) /*! @} */ /*! @name CMP0_TRIG - CMP0 Input Connections */ /*! @{ */ #define INPUTMUX_CMP0_TRIG_TRIGIN_MASK (0x3FU) #define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - CMP0 input trigger * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT6 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT6 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER0_MAT0 input is selected * 0b001001..CTIMER4_MAT0 input is selected * 0b001010..Reserved * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC1_tcomp[0] input is selected * 0b001111..Reserved * 0b010000..Reserved * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b011001..QDC0_CMP/POS_MATCH input is selected * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected * 0b011110..EVTG_OUT1B input is selected * 0b011111..EVTG_OUT2A input is selected * 0b100000..EVTG_OUT2B input is selected * 0b100001..EVTG_OUT3A input is selected * 0b100010..EVTG_OUT3B input is selected * 0b100011..LPTMR0 input is selected * 0b100100..LPTMR1 input is selected * 0b100101..GPIO2 Pin Event Trig 0 input is selected * 0b100110..GPIO2 Pin Event Trig 1 input is selected * 0b100111..GPIO3 Pin Event Trig 0 input is selected * 0b101000..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_CMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK) /*! @} */ /*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger Input Connections */ /*! @{ */ #define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0xFFU) #define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - ADC0 trigger inputs * 0b00000000..PINT PIN_INT0 input is selected * 0b00000001..PINT PIN_INT1 input is selected * 0b00000010..SCT0 SCT_OUT4 input is selected * 0b00000011..SCT0 SCT_OUT5 input is selected * 0b00000100..SCT0 SCT_OUT9 input is selected * 0b00000101..CTIMER0_MAT3 input is selected * 0b00000110..CTIMER1_MAT3 input is selected * 0b00000111..CTIMER2_MAT3 input is selected * 0b00001000..CTIMER3_MAT3 input is selected * 0b00001001..CTIMER4_MAT3 input is selected * 0b00001010..DCDC_Burst_Done_Trig input is selected * 0b00001011..Reserved * 0b00001100..PINT GPIO_INT_BMAT input is selected * 0b00001101..ADC0_tcomp[0] input is selected * 0b00001110..ADC0_tcomp[1] input is selected * 0b00001111..ADC0_tcomp[2] input is selected * 0b00010000..ADC0_tcomp[3] input is selected * 0b00010001..ADC1_tcomp[0] input is selected * 0b00010010..ADC1_tcomp[1] input is selected * 0b00010011..ADC1_tcomp[2] input is selected * 0b00010100..ADC1_tcomp[3] input is selected * 0b00010101..CMP0_OUT input is selected * 0b00010110..CMP1_OUT input is selected * 0b00010111..CMP2_OUT input is selected * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected * 0b00101000..QDC0_CMP/POS_MATCH input is selected * 0b00101001..QDC1_CMP/POS_MATCH input is selected * 0b00101010..EVTG_OUT0A input is selected * 0b00101011..EVTG_OUT0B input is selected * 0b00101100..EVTG_OUT1A input is selected * 0b00101101..EVTG_OUT1B input is selected * 0b00101110..EVTG_OUT2A input is selected * 0b00101111..EVTG_OUT2B input is selected * 0b00110000..EVTG_OUT3A input is selected * 0b00110001..EVTG_OUT3B input is selected * 0b00110010..LPTMR0 input is selected * 0b00110011..LPTMR1 input is selected * 0b00110100..FlexIO CH0 input is selected * 0b00110101..FlexIO CH1 input is selected * 0b00110110..FlexIO CH2 input is selected * 0b00110111..FlexIO CH3 input is selected * 0b00111000..SINC Filter CH0 Conversion Complete input is selected * 0b00111001..SINC Filter CH1 Conversion Complete input is selected * 0b00111010..SINC Filter CH2 Conversion Complete input is selected * 0b00111011..SINC Filter CH3 Conversion Complete input is selected * 0b00111100..SINC Filter CH4 Conversion Complete input is selected * 0b00111101..GPIO2 Pin Event Trig 0 input is selected * 0b00111110..GPIO2 Pin Event Trig 1 input is selected * 0b00111111..GPIO3 Pin Event Trig 0 input is selected * 0b01000000..GPIO3 Pin Event Trig 1 input is selected * 0b01000001..WUU input is selected * *.. */ #define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK) /*! @} */ /* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */ #define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT (4U) /*! @name ADC1_TRIGN_ADC1_TRIG - ADC Trigger Input Connections */ /*! @{ */ #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0xFFU) #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - ADC1 trigger inputs * 0b00000000..PINT PIN_INT0 input is selected * 0b00000001..PINT PIN_INT2 input is selected * 0b00000010..SCT0 SCT_OUT4 input is selected * 0b00000011..SCT0 SCT_OUT5 input is selected * 0b00000100..SCT0 SCT_OUT3 input is selected * 0b00000101..CTIMER0_MAT3 input is selected * 0b00000110..CTIMER1_MAT3 input is selected * 0b00000111..CTIMER2_MAT3 input is selected * 0b00001000..CTIMER3_MAT2 input is selected * 0b00001001..CTIMER4_MAT1 input is selected * 0b00001010..DCDC_Burst_Done_Trig input is selected * 0b00001011..Reserved * 0b00001100..PINT GPIO_INT_BMAT input is selected * 0b00001101..ADC0_tcomp[0] input is selected * 0b00001110..ADC0_tcomp[1] input is selected * 0b00001111..ADC0_tcomp[2] input is selected * 0b00010000..ADC0_tcomp[3] input is selected * 0b00010001..ADC1_tcomp[0] input is selected * 0b00010010..ADC1_tcomp[1] input is selected * 0b00010011..ADC1_tcomp[2] input is selected * 0b00010100..ADC1_tcomp[3] input is selected * 0b00010101..CMP0_OUT input is selected * 0b00010110..CMP1_OUT input is selected * 0b00010111..CMP2_OUT input is selected * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected * 0b00101000..QDC0_CMP/POS_MATCH input is selected * 0b00101001..QDC1_CMP/POS_MATCH input is selected * 0b00101010..EVTG_OUT0A input is selected * 0b00101011..EVTG_OUT0B input is selected * 0b00101100..EVTG_OUT1A input is selected * 0b00101101..EVTG_OUT1B input is selected * 0b00101110..EVTG_OUT2A input is selected * 0b00101111..EVTG_OUT2B input is selected * 0b00110000..EVTG_OUT3A input is selected * 0b00110001..EVTG_OUT3B input is selected * 0b00110010..LPTMR0 input is selected * 0b00110011..LPTMR1 input is selected * 0b00110100..FlexIO CH0 input is selected * 0b00110101..FlexIO CH1 input is selected * 0b00110110..FlexIO CH2 input is selected * 0b00110111..FlexIO CH3 input is selected * 0b00111000..SINC Filter CH0 Conversion Complete input is selected * 0b00111001..SINC Filter CH1 Conversion Complete input is selected * 0b00111010..SINC Filter CH2 Conversion Complete input is selected * 0b00111011..SINC Filter CH3 Conversion Complete input is selected * 0b00111100..SINC Filter CH4 Conversion Complete input is selected * 0b00111101..GPIO2 Pin Event Trig 0 input is selected * 0b00111110..GPIO2 Pin Event Trig 1 input is selected * 0b00111111..GPIO3 Pin Event Trig 0 input is selected * 0b01000000..GPIO3 Pin Event Trig 1 input is selected * 0b01000001..WUU input is selected * *.. */ #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK) /*! @} */ /* The count of INPUTMUX_ADC1_TRIGN_ADC1_TRIG */ #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_COUNT (4U) /*! @name DAC0_TRIG - DAC0 Trigger Inputs */ /*! @{ */ #define INPUTMUX_DAC0_TRIG_TRIGIN_MASK (0x3FU) #define INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - DAC0 trigger input * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT3 input is selected * 0b000010..SCT0 SCT_OUT4 input is selected * 0b000011..SCT0 SCT_OUT5 input is selected * 0b000100..SCT0 SCT_OUT0 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..Reserved * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC1_tcomp[0] input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..LPTMR0 input is selected * 0b011011..LPTMR1 input is selected * 0b011100..GPIO2 Pin Event Trig 0 input is selected * 0b011101..GPIO2 Pin Event Trig 1 input is selected * 0b011110..GPIO3 Pin Event Trig 0 input is selected * 0b011111..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_DAC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC0_TRIG_TRIGIN_MASK) /*! @} */ /*! @name DAC1_TRIG - DAC1 Trigger Inputs */ /*! @{ */ #define INPUTMUX_DAC1_TRIG_TRIGIN_MASK (0x3FU) #define INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - DAC1 trigger input * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT0 SCT_OUT4 input is selected * 0b000011..SCT0 SCT_OUT5 input is selected * 0b000100..SCT0 SCT_OUT1 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER3_MAT1 input is selected * 0b001010..Reserved * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[1] input is selected * 0b001110..ADC1_tcomp[1] input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..LPTMR0 input is selected * 0b011011..LPTMR1 input is selected * 0b011100..GPIO2 Pin Event Trig 0 input is selected * 0b011101..GPIO2 Pin Event Trig 1 input is selected * 0b011110..GPIO3 Pin Event Trig 0 input is selected * 0b011111..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_DAC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC1_TRIG_TRIGIN_MASK) /*! @} */ /*! @name DAC2_TRIG - DAC2 Trigger Inputs */ /*! @{ */ #define INPUTMUX_DAC2_TRIG_TRIGIN_MASK (0x3FU) #define INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - DAC2 trigger input * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT0 SCT_OUT4 input is selected * 0b000011..SCT0 SCT_OUT5 input is selected * 0b000100..SCT0 SCT_OUT2 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT2 input is selected * 0b001001..CTIMER3_MAT2 input is selected * 0b001010..Reserved * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[2] input is selected * 0b001110..ADC1_tcomp[2] input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..LPTMR0 input is selected * 0b011011..LPTMR1 input is selected * 0b011100..GPIO2 Pin Event Trig 0 input is selected * 0b011101..GPIO2 Pin Event Trig 1 input is selected * 0b011110..GPIO3 Pin Event Trig 0 input is selected * 0b011111..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_DAC2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC2_TRIG_TRIGIN_MASK) /*! @} */ /*! @name QDCN_QDC_TRIG - QDC0 Trigger Input Connections..QDC1 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_QDCN_QDC_TRIG_INP_MASK (0x3FU) #define INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT (0U) /*! INP - QDC1 trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT1 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER1_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * *.. */ #define INPUTMUX_QDCN_QDC_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT)) & INPUTMUX_QDCN_QDC_TRIG_INP_MASK) /*! @} */ /* The count of INPUTMUX_QDCN_QDC_TRIG */ #define INPUTMUX_QDCN_QDC_TRIG_COUNT (2U) /*! @name QDCN_QDC_HOME - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ #define INPUTMUX_QDCN_QDC_HOME_INP_MASK (0x3FU) #define INPUTMUX_QDCN_QDC_HOME_INP_SHIFT (0U) /*! INP - QDC1 HOME input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT0 SCT_OUT4 input is selected * 0b000011..SCT0 SCT_OUT5 input is selected * 0b000100..SCT0 SCT_OUT1 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER1_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * *.. */ #define INPUTMUX_QDCN_QDC_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_HOME_INP_SHIFT)) & INPUTMUX_QDCN_QDC_HOME_INP_MASK) /*! @} */ /* The count of INPUTMUX_QDCN_QDC_HOME */ #define INPUTMUX_QDCN_QDC_HOME_COUNT (2U) /*! @name QDCN_QDC_INDEX - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ #define INPUTMUX_QDCN_QDC_INDEX_INP_MASK (0x3FU) #define INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT (0U) /*! INP - QDC1 INDEX input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT1 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER1_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * *.. */ #define INPUTMUX_QDCN_QDC_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT)) & INPUTMUX_QDCN_QDC_INDEX_INP_MASK) /*! @} */ /* The count of INPUTMUX_QDCN_QDC_INDEX */ #define INPUTMUX_QDCN_QDC_INDEX_COUNT (2U) /*! @name QDCN_QDC_PHASEB - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ #define INPUTMUX_QDCN_QDC_PHASEB_INP_MASK (0x3FU) #define INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT (0U) /*! INP - QDC1 PHASEB input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT1 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER1_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * *.. */ #define INPUTMUX_QDCN_QDC_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEB_INP_MASK) /*! @} */ /* The count of INPUTMUX_QDCN_QDC_PHASEB */ #define INPUTMUX_QDCN_QDC_PHASEB_COUNT (2U) /*! @name QDCN_QDC_PHASEA - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ #define INPUTMUX_QDCN_QDC_PHASEA_INP_MASK (0x3FU) #define INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT (0U) /*! INP - QDC1 PHASEA input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT1 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER1_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * *.. */ #define INPUTMUX_QDCN_QDC_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEA_INP_MASK) /*! @} */ /* The count of INPUTMUX_QDCN_QDC_PHASEA */ #define INPUTMUX_QDCN_QDC_PHASEA_COUNT (2U) /*! @name FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC - PWM0 External Synchronization */ /*! @{ */ #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT (0U) /*! TRIGIN - EXTSYNC input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT2 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER4_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * 0b110100..SINC Filter CH0 sync Break input is selected * 0b110101..SINC Filter CH1 sync Break input is selected * 0b110110..SINC Filter CH2 sync Break input is selected * 0b110111..SINC Filter CH3 sync Break input is selected * 0b111000..SINC Filter CH4 sync Break input is selected * 0b111001..GPIO2 Pin Event Trig 0 input is selected * 0b111010..GPIO2 Pin Event Trig 1 input is selected * 0b111011..GPIO3 Pin Event Trig 0 input is selected * 0b111100..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK) /*! @} */ /* The count of INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC */ #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_COUNT (4U) /*! @name FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA - PWM0 Input Trigger Connections */ /*! @{ */ #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT (0U) /*! TRIGIN - EXTA input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT2 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER4_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * 0b110100..SINC Filter CH0 sync Break input is selected * 0b110101..SINC Filter CH1 sync Break input is selected * 0b110110..SINC Filter CH2 sync Break input is selected * 0b110111..SINC Filter CH3 sync Break input is selected * 0b111000..SINC Filter CH4 sync Break input is selected * 0b111001..GPIO2 Pin Event Trig 0 input is selected * 0b111010..GPIO2 Pin Event Trig 1 input is selected * 0b111011..GPIO3 Pin Event Trig 0 input is selected * 0b111100..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK) /*! @} */ /* The count of INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA */ #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_COUNT (4U) /*! @name FLEXPWM0_EXTFORCE - PWM0 External Force Trigger Connections */ /*! @{ */ #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT (0U) /*! TRIGIN - EXTFORCE input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT2 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER4_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * 0b110100..SINC Filter CH0 sync Break input is selected * 0b110101..SINC Filter CH1 sync Break input is selected * 0b110110..SINC Filter CH2 sync Break input is selected * 0b110111..SINC Filter CH3 sync Break input is selected * 0b111000..SINC Filter CH4 sync Break input is selected * 0b111001..GPIO2 Pin Event Trig 0 input is selected * 0b111010..GPIO2 Pin Event Trig 1 input is selected * 0b111011..GPIO3 Pin Event Trig 0 input is selected * 0b111100..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK) /*! @} */ /*! @name FLEXPWM_FAULT_FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */ /*! @{ */ #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) /*! TRIGIN - FAULT input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT2 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER4_MAT0 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * 0b110100..SINC Filter CH0 sync Break input is selected * 0b110101..SINC Filter CH1 sync Break input is selected * 0b110110..SINC Filter CH2 sync Break input is selected * 0b110111..SINC Filter CH3 sync Break input is selected * 0b111000..SINC Filter CH4 sync Break input is selected * 0b111001..GPIO2 Pin Event Trig 0 input is selected * 0b111010..GPIO2 Pin Event Trig 1 input is selected * 0b111011..GPIO3 Pin Event Trig 0 input is selected * 0b111100..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK) /*! @} */ /* The count of INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT */ #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_COUNT (4U) /*! @name FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC - PWM1 External Synchronization */ /*! @{ */ #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT (0U) /*! TRIGIN - EXTSYNC input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT3 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER4_MAT1 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * 0b110100..SINC Filter CH0 sync Break input is selected * 0b110101..SINC Filter CH1 sync Break input is selected * 0b110110..SINC Filter CH2 sync Break input is selected * 0b110111..SINC Filter CH3 sync Break input is selected * 0b111000..SINC Filter CH4 sync Break input is selected * 0b111001..GPIO2 Pin Event Trig 0 input is selected * 0b111010..GPIO2 Pin Event Trig 1 input is selected * 0b111011..GPIO3 Pin Event Trig 0 input is selected * 0b111100..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK) /*! @} */ /* The count of INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC */ #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_COUNT (4U) /*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input EXTA Connections */ /*! @{ */ #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT (0U) /*! TRIGIN - EXTA input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT3 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER4_MAT1 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * 0b110100..SINC Filter CH0 sync Break input is selected * 0b110101..SINC Filter CH1 sync Break input is selected * 0b110110..SINC Filter CH2 sync Break input is selected * 0b110111..SINC Filter CH3 sync Break input is selected * 0b111000..SINC Filter CH4 sync Break input is selected * 0b111001..GPIO2 Pin Event Trig 0 input is selected * 0b111010..GPIO2 Pin Event Trig 1 input is selected * 0b111011..GPIO3 Pin Event Trig 0 input is selected * 0b111100..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK) /*! @} */ /* The count of INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA */ #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_COUNT (4U) /*! @name FLEXPWM1_EXTFORCE - PWM1 External Force Trigger Connections */ /*! @{ */ #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT (0U) /*! TRIGIN - EXTFORCE input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT3 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER4_MAT1 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * 0b110100..SINC Filter CH0 sync Break input is selected * 0b110101..SINC Filter CH1 sync Break input is selected * 0b110110..SINC Filter CH2 sync Break input is selected * 0b110111..SINC Filter CH3 sync Break input is selected * 0b111000..SINC Filter CH4 sync Break input is selected * 0b111001..GPIO2 Pin Event Trig 0 input is selected * 0b111010..GPIO2 Pin Event Trig 1 input is selected * 0b111011..GPIO3 Pin Event Trig 0 input is selected * 0b111100..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK) /*! @} */ /*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */ /*! @{ */ #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) /*! TRIGIN - FAULT input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT3 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER4_MAT1 input is selected * 0b001010..Reserved * 0b001011..ARM_TXEV input is selected * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected * 0b100000..QDC0_CMP/POS_MATCH input is selected * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected * 0b100101..EVTG_OUT1B input is selected * 0b100110..EVTG_OUT2A input is selected * 0b100111..EVTG_OUT2B input is selected * 0b101000..EVTG_OUT3A input is selected * 0b101001..EVTG_OUT3B input is selected * 0b101010..TRIG_IN0 input is selected * 0b101011..TRIG_IN1 input is selected * 0b101100..TRIG_IN2 input is selected * 0b101101..TRIG_IN3 input is selected * 0b101110..TRIG_IN4 input is selected * 0b101111..TRIG_IN5 input is selected * 0b110000..TRIG_IN6 input is selected * 0b110001..TRIG_IN7 input is selected * 0b110010..TRIG_IN8 input is selected * 0b110011..TRIG_IN9 input is selected * 0b110100..SINC Filter CH0 sync Break input is selected * 0b110101..SINC Filter CH1 sync Break input is selected * 0b110110..SINC Filter CH2 sync Break input is selected * 0b110111..SINC Filter CH3 sync Break input is selected * 0b111000..SINC Filter CH4 sync Break input is selected * 0b111001..GPIO2 Pin Event Trig 0 input is selected * 0b111010..GPIO2 Pin Event Trig 1 input is selected * 0b111011..GPIO3 Pin Event Trig 0 input is selected * 0b111100..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK) /*! @} */ /* The count of INPUTMUX_FLEXPWM1_FAULT */ #define INPUTMUX_FLEXPWM1_FAULT_COUNT (4U) /*! @name PWM0_EXT_CLK - PWM0 External Clock Trigger */ /*! @{ */ #define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0x7U) #define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) /*! TRIGIN - EXT_CLK input connections for PWM0 * 0b000..FRO16K input is selected * 0b001..OSC_32k input is selected * 0b010..EVTG_OUT0A input is selected * 0b011..EVTG_OUT1A input is selected * 0b100..TRIG_IN0 input is selected * 0b101..TRIG_IN7 input is selected * *.. */ #define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK) /*! @} */ /*! @name PWM1_EXT_CLK - PWM1 External Clock Trigger */ /*! @{ */ #define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) #define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) /*! TRIGIN - EXT_CLK input connections for PWM1 * 0b0000..FRO16K input is selected * 0b0001..OSC_32k input is selected * 0b0010..EVTG_OUT0A input is selected * 0b0011..EVTG_OUT1A input is selected * 0b0100..TRIG_IN0 input is selected * 0b0101..TRIG_IN7 input is selected * *.. */ #define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) /*! @} */ /*! @name EVTG_TRIGN_EVTG_TRIG - EVTG Trigger Input Connections */ /*! @{ */ #define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK (0x3FU) #define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT (0U) /*! INP - EVTG trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected * 0b000010..SCT_OUT0 input is selected * 0b000011..SCT_OUT1 input is selected * 0b000100..SCT_OUT2 input is selected * 0b000101..SCT_OUT3 input is selected * 0b000110..CTIMER0_MAT3 input is selected * 0b000111..CTIMER1_MAT3 input is selected * 0b001000..CTIMER2_MAT3 input is selected * 0b001001..CTIMER2_MAT2 input is selected * 0b001010..CTIMER3_MAT2 input is selected * 0b001011..CTIMER4_MAT2 input is selected * 0b001100..Reserved * 0b001101..PINT GPIO_INT_BMAT input is selected * 0b001110..ADC0_IRQ input is selected * 0b001111..ADC1_IRQ input is selected * 0b010000..ADC0_tcomp[0] input is selected * 0b010001..ADC0_tcomp[1] input is selected * 0b010010..ADC0_tcomp[2] input is selected * 0b010011..ADC0_tcomp[3] input is selected * 0b010100..ADC1_tcomp[0] input is selected * 0b010101..ADC1_tcomp[1] input is selected * 0b010110..ADC1_tcomp[2] input is selected * 0b010111..ADC1_tcomp[3] input is selected * 0b011000..CMP0_OUT input is selected * 0b011001..CMP1_OUT input is selected * 0b011010..CMP2_OUT input is selected * 0b011011..PWM0_SM0_MUX_TRIG0 input is selected * 0b011100..PWM0_SM0_MUX_TRIG1 input is selected * 0b011101..PWM0_SM1_MUX_TRIG0 input is selected * 0b011110..PWM0_SM1_MUX_TRIG1 input is selected * 0b011111..PWM0_SM2_MUX_TRIG0 input is selected * 0b100000..PWM0_SM2_MUX_TRIG1 input is selected * 0b100001..PWM0_SM3_MUX_TRIG0 input is selected * 0b100010..PWM0_SM3_MUX_TRIG1 input is selected * 0b100011..PWM1_SM0_MUX_TRIG0 input is selected * 0b100100..PWM1_SM0_MUX_TRIG1 input is selected * 0b100101..PWM1_SM1_MUX_TRIG0 input is selected * 0b100110..PWM1_SM1_MUX_TRIG1 input is selected * 0b100111..PWM1_SM2_MUX_TRIG0 input is selected * 0b101000..PWM1_SM2_MUX_TRIG1 input is selected * 0b101001..PWM1_SM3_MUX_TRIG0 input is selected * 0b101010..PWM1_SM3_MUX_TRIG1 input is selected * 0b101011..QDC0_CMP/POS_MATCH input is selected * 0b101100..QDC1_CMP/POS_MATCH input is selected * 0b101101..TRIG_IN0 input is selected * 0b101110..TRIG_IN1 input is selected * 0b101111..TRIG_IN2 input is selected * 0b110000..TRIG_IN3 input is selected * 0b110001..LPTMR0 input is selected * 0b110010..LPTMR1 input is selected * 0b110011..SINC Filter CH0 Break input is selected * 0b110100..SINC Filter CH1 Break input is selected * 0b110101..SINC Filter CH2 Break input is selected * 0b110110..SINC Filter CH3 Break input is selected * 0b110111..SINC Filter CH4 Break input is selected * 0b111000..Reserved * 0b111001..Reserved * *.. */ #define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT)) & INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK) /*! @} */ /* The count of INPUTMUX_EVTG_TRIGN_EVTG_TRIG */ #define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_COUNT (16U) /*! @name USBFS_TRIG - USB-FS Trigger Input Connections */ /*! @{ */ #define INPUTMUX_USBFS_TRIG_INP_MASK (0xFU) #define INPUTMUX_USBFS_TRIG_INP_SHIFT (0U) /*! INP - USB-FS trigger input connections. The trigger output of LP_FLEXCOMM is an input of peripheral INPUTMUX. * 0b0000..LP_FLEXCOMM 0 trigger out [3] input is selected * 0b0001..LP_FLEXCOMM 1 trigger out [3] input is selected * 0b0010..LP_FLEXCOMM 2 trigger out [3] input is selected * 0b0011..LP_FLEXCOMM 3 trigger out [3] input is selected * 0b0100..LP_FLEXCOMM 4 trigger out [3] input is selected * 0b0101..LP_FLEXCOMM 5 trigger out [3] input is selected * 0b0110..LP_FLEXCOMM 6 trigger out [3] input is selected * 0b0111..LP_FLEXCOMM 7 trigger out [3] input is selected * 0b1000..LP_FLEXCOMM 8 trigger out [3] input is selected * 0b1001..LP_FLEXCOMM 9 trigger out [3] input is selected * *.. */ #define INPUTMUX_USBFS_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_USBFS_TRIG_INP_SHIFT)) & INPUTMUX_USBFS_TRIG_INP_MASK) /*! @} */ /*! @name TSI_TRIG - TSI Trigger Input Connections */ /*! @{ */ #define INPUTMUX_TSI_TRIG_INP_MASK (0x3U) #define INPUTMUX_TSI_TRIG_INP_SHIFT (0U) /*! INP - TSI trigger input connections * 0b00..LPTMR0 input is selected * 0b01..LPTMR1 input is selected * *.. */ #define INPUTMUX_TSI_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TSI_TRIG_INP_SHIFT)) & INPUTMUX_TSI_TRIG_INP_MASK) /*! @} */ /*! @name EXT_TRIGN_EXT_TRIG - EXT Trigger Connections */ /*! @{ */ #define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK (0x3FU) #define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT (0U) /*! INP - TRIG_OUTa pin input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected * 0b000010..ADC0_IRQ input is selected * 0b000011..ADC1_IRQ input is selected * 0b000100..ADC0_tcomp[0] input is selected * 0b000101..ADC1_tcomp[0] input is selected * 0b000110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b000111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b001000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b001001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b001010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b001011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b001100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b001101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b001110..QDC0_CMP/POS_MATCH input is selected * 0b001111..QDC1_CMP/POS_MATCH input is selected * 0b010000..EVTG_OUT0A input is selected * 0b010001..EVTG_OUT0B input is selected * 0b010010..EVTG_OUT1A input is selected * 0b010011..EVTG_OUT1B input is selected * 0b010100..EVTG_OUT2A input is selected * 0b010101..EVTG_OUT2B input is selected * 0b010110..EVTG_OUT3A input is selected * 0b010111..EVTG_OUT3B input is selected * 0b011000..Reserved * 0b011001..Reserved * 0b011010..LPTMR0 input is selected * 0b011011..LPTMR1 input is selected * 0b011100..SCT Out0 input is selected * 0b011101..SCT Out1 input is selected * 0b011110..SCT Out2 input is selected * 0b011111..SCT Out3 input is selected * 0b100000..SCT Out4 input is selected * 0b100001..SCT Out5 input is selected * 0b100010..LP_FLEXCOMM0 trigger output 3 input is selected * 0b100011..LP_FLEXCOMM1 trigger output 3 input is selected * 0b100100..LP_FLEXCOMM2 trigger output 3 input is selected * 0b100101..LP_FLEXCOMM3 trigger output 3 input is selected * 0b100110..LP_FLEXCOMM4 trigger output 3 input is selected * 0b100111..LP_FLEXCOMM5 trigger output 3 input is selected * 0b101000..LP_FLEXCOMM6 trigger output 3 input is selected * 0b101001..LP_FLEXCOMM7 trigger output 3 input is selected * 0b101010..LP_FLEXCOMM8 trigger output 3 input is selected * 0b101011..LP_FLEXCOMM9 trigger output 3 input is selected * 0b101100..CMP0_OUT input is selected * 0b101101..CMP1_OUT input is selected * 0b101110..CMP2_OUT input is selected * 0b101111..ENET_PPS_OUT_0 input is selected * *.. */ #define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK) /*! @} */ /* The count of INPUTMUX_EXT_TRIGN_EXT_TRIG */ #define INPUTMUX_EXT_TRIGN_EXT_TRIG_COUNT (8U) /*! @name CMP1_TRIG - CMP1 Input Connections */ /*! @{ */ #define INPUTMUX_CMP1_TRIG_TRIGIN_MASK (0x3FU) #define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - CMP1 input trigger * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT7 input is selected * 0b000010..SCT0 SCT_OUT4 input is selected * 0b000011..SCT0 SCT_OUT5 input is selected * 0b000100..SCT0 SCT_OUT7 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER3_MAT1 input is selected * 0b001001..CTIMER4_MAT1 input is selected * 0b001010..Reserved * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[1] input is selected * 0b001110..ADC1_tcomp[1] input is selected * 0b001111..Reserved * 0b010000..Reserved * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b011001..QDC0_CMP/POS_MATCH input is selected * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected * 0b011110..EVTG_OUT1B input is selected * 0b011111..EVTG_OUT2A input is selected * 0b100000..EVTG_OUT2B input is selected * 0b100001..EVTG_OUT3A input is selected * 0b100010..EVTG_OUT3B input is selected * 0b100011..LPTMR0 input is selected * 0b100100..LPTMR1 input is selected * 0b100101..GPIO2 Pin Event Trig 0 input is selected * 0b100110..GPIO2 Pin Event Trig 1 input is selected * 0b100111..GPIO3 Pin Event Trig 0 input is selected * 0b101000..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_CMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK) /*! @} */ /*! @name CMP2_TRIG - CMP2 Input Connections */ /*! @{ */ #define INPUTMUX_CMP2_TRIG_TRIGIN_MASK (0x3FU) #define INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - CMP2 input trigger * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT0 SCT_OUT4 input is selected * 0b000011..SCT0 SCT_OUT5 input is selected * 0b000100..SCT0 SCT_OUT8 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER3_MAT2 input is selected * 0b001001..CTIMER4_MAT2 input is selected * 0b001010..Reserved * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[2] input is selected * 0b001110..ADC1_tcomp[2] input is selected * 0b001111..Reserved * 0b010000..Reserved * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected * 0b011001..QDC0_CMP/POS_MATCH input is selected * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected * 0b011110..EVTG_OUT1B input is selected * 0b011111..EVTG_OUT2A input is selected * 0b100000..EVTG_OUT2B input is selected * 0b100001..EVTG_OUT3A input is selected * 0b100010..EVTG_OUT3B input is selected * 0b100011..LPTMR0 input is selected * 0b100100..LPTMR1 input is selected * 0b100101..GPIO2 Pin Event Trig 0 input is selected * 0b100110..GPIO2 Pin Event Trig 1 input is selected * 0b100111..GPIO3 Pin Event Trig 0 input is selected * 0b101000..GPIO3 Pin Event Trig 1 input is selected * *.. */ #define INPUTMUX_CMP2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP2_TRIG_TRIGIN_MASK) /*! @} */ /*! @name SINC_FILTER_CHN_SINC_FILTER_CH - SINC Filter Channel Trigger Input Connections */ /*! @{ */ #define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_MASK (0x3FU) #define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_SHIFT (0U) /*! INP - SINC FILTER trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected * 0b000010..SCT_OUT4 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT9 input is selected * 0b000101..CTIMER0_MAT3 input is selected * 0b000110..CTIMER1_MAT3 input is selected * 0b000111..CTIMER2_MAT3 input is selected * 0b001000..CTIMER3_MAT3 input is selected * 0b001001..CTIMER4_MAT3 input is selected * 0b001010..Reserved * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected * 0b001111..ADC0_tcomp[2] input is selected * 0b010000..ADC0_tcomp[3] input is selected * 0b010001..ADC1_tcomp[0] input is selected * 0b010010..ADC1_tcomp[1] input is selected * 0b010011..ADC1_tcomp[2] input is selected * 0b010100..ADC1_tcomp[3] input is selected * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected * 0b100000..PWM1_SM0_MUX_TRIG0 input is selected * 0b100001..PWM1_SM0_MUX_TRIG1 input is selected * 0b100010..PWM1_SM1_MUX_TRIG0 input is selected * 0b100011..PWM1_SM1_MUX_TRIG1 input is selected * 0b100100..PWM1_SM2_MUX_TRIG0 input is selected * 0b100101..PWM1_SM2_MUX_TRIG1 input is selected * 0b100110..PWM1_SM3_MUX_TRIG0 input is selected * 0b100111..PWM1_SM3_MUX_TRIG1 input is selected * 0b101000..QDC0_CMP/POS_MATCH input is selected * 0b101001..QDC1_CMP/POS_MATCH input is selected * 0b101010..EVTG_OUT0A input is selected * 0b101011..EVTG_OUT0B input is selected * 0b101100..EVTG_OUT1A input is selected * 0b101101..EVTG_OUT1B input is selected * 0b101110..EVTG_OUT2A input is selected * 0b101111..EVTG_OUT2B input is selected * 0b110000..EVTG_OUT3A input is selected * 0b110001..EVTG_OUT3B input is selected * 0b110010..LPTMR0 input is selected * 0b110011..LPTMR1 input is selected * 0b110100..FlexIO CH0 input is selected * 0b110101..FlexIO CH1 input is selected * 0b110110..FlexIO CH2 input is selected * 0b110111..FlexIO CH3 input is selected * 0b111000..WUU input is selected * *.. */ #define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_MASK) /*! @} */ /* The count of INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH */ #define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_COUNT (5U) /*! @name OPAMPN_TRIG_OPAMP_TRIG - OPAMP Trigger Input Connections */ /*! @{ */ #define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_MASK (0x3FU) #define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_SHIFT (0U) /*! INP - OPAMP trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected * 0b000010..PINT PIN_INT2 input is selected * 0b000011..PINT PIN_INT3 input is selected * 0b000100..SCT_OUT4 input is selected * 0b000101..SCT_OUT5 input is selected * 0b000110..SCT_OUT6 input is selected * 0b000111..SCT_OUT7 input is selected * 0b001000..SCT_OUT8 input is selected * 0b001001..CTIMER0_MAT3 input is selected * 0b001010..CTIMER1_MAT3 input is selected * 0b001011..CTIMER2_MAT3 input is selected * 0b001100..CTIMER3_MAT3 input is selected * 0b001101..CTIMER4_MAT3 input is selected * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..ADC0_tcomp[0] input is selected * 0b010000..ADC0_tcomp[1] input is selected * 0b010001..ADC0_tcomp[2] input is selected * 0b010010..ADC0_tcomp[3] input is selected * 0b010011..ADC1_tcomp[0] input is selected * 0b010100..ADC1_tcomp[1] input is selected * 0b010101..ADC1_tcomp[2] input is selected * 0b010110..ADC1_tcomp[3] input is selected * 0b010111..PWM0_SM0_MUX_TRIG0 input is selected * 0b011000..PWM0_SM0_MUX_TRIG1 input is selected * 0b011001..PWM0_SM1_MUX_TRIG0 input is selected * 0b011010..PWM0_SM1_MUX_TRIG1 input is selected * 0b011011..PWM0_SM2_MUX_TRIG0 input is selected * 0b011100..PWM0_SM2_MUX_TRIG1 input is selected * 0b011101..PWM0_SM3_MUX_TRIG0 input is selected * 0b011110..PWM0_SM3_MUX_TRIG1 input is selected * 0b011111..PWM1_SM0_MUX_TRIG0 input is selected * 0b100000..PWM1_SM0_MUX_TRIG1 input is selected * 0b100001..PWM1_SM1_MUX_TRIG0 input is selected * 0b100010..PWM1_SM1_MUX_TRIG1 input is selected * 0b100011..PWM1_SM2_MUX_TRIG0 input is selected * 0b100100..PWM1_SM2_MUX_TRIG1 input is selected * 0b100101..PWM1_SM3_MUX_TRIG0 input is selected * 0b100110..PWM1_SM3_MUX_TRIG1 input is selected * 0b100111..EVTG_OUT0A input is selected * 0b101000..EVTG_OUT0B input is selected * 0b101001..EVTG_OUT1A input is selected * 0b101010..EVTG_OUT1B input is selected * 0b101011..EVTG_OUT2A input is selected * 0b101100..EVTG_OUT2B input is selected * 0b101101..EVTG_OUT3A input is selected * 0b101110..EVTG_OUT3B input is selected * 0b101111..TRIG_IN0 input is selected * 0b110000..TRIG_IN1 input is selected * 0b110001..TRIG_IN2 input is selected * 0b110010..TRIG_IN3 input is selected * 0b110011..FlexIO CH4 input is selected * 0b110100..FlexIO CH5 input is selected * 0b110101..FlexIO CH6 input is selected * 0b110110..FlexIO CH7 input is selected * *.. */ #define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_SHIFT)) & INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_MASK) /*! @} */ /* The count of INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG */ #define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_COUNT (3U) /*! @name FLEXCOMM0_TRIG - LP_FLEXCOMM0 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM0_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM0 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT6 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT6 input is selected * 0b000101..SCT_OUT7 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM0_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM1_TRIG - LP_FLEXCOMM1 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM1_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM1 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT6 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT6 input is selected * 0b000101..SCT_OUT7 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM1_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM2_TRIG - LP_FLEXCOMM2 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM2_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM2 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT6 input is selected * 0b000010..PINT PIN_INT7 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT8 input is selected * 0b000101..SCT_OUT9 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER3_MAT1 input is selected * 0b001010..CTIMER4_MAT1 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM2_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM2_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM3_TRIG - LP_FLEXCOMM3 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM3_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM3 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected * 0b000011..SCT_OUT5 input is selected * 0b000100..SCT_OUT8 input is selected * 0b000101..SCT_OUT9 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER3_MAT1 input is selected * 0b001010..CTIMER4_MAT1 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM3_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM3_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM4_TRIG - LP_FLEXCOMM4 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM4_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM4 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected * 0b000011..SCT_OUT0 input is selected * 0b000100..SCT_OUT1 input is selected * 0b000101..SCT_OUT2 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT2 input is selected * 0b001001..CTIMER3_MAT2 input is selected * 0b001010..CTIMER4_MAT2 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM4_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM4_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM5_TRIG - LP_FLEXCOMM5 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM5_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM5 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected * 0b000011..SCT_OUT0 input is selected * 0b000100..SCT_OUT1 input is selected * 0b000101..SCT_OUT2 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT2 input is selected * 0b001001..CTIMER3_MAT2 input is selected * 0b001010..CTIMER4_MAT2 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM5_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM5_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM6_TRIG - LP_FLEXCOMM6 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM6_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM6 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected * 0b000011..SCT_OUT0 input is selected * 0b000100..SCT_OUT3 input is selected * 0b000101..SCT_OUT4 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT3 input is selected * 0b001001..CTIMER3_MAT3 input is selected * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM6_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM6_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM7_TRIG - LP_FLEXCOMM7 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM7_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM7 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected * 0b000011..SCT_OUT0 input is selected * 0b000100..SCT_OUT3 input is selected * 0b000101..SCT_OUT4 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT3 input is selected * 0b001001..CTIMER3_MAT3 input is selected * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM7_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM7_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM8_TRIG - LP_FLEXCOMM8 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM8_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM8_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM8 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected * 0b000011..SCT_OUT0 input is selected * 0b000100..SCT_OUT3 input is selected * 0b000101..SCT_OUT4 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT3 input is selected * 0b001001..CTIMER3_MAT3 input is selected * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM8_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM8_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM8_TRIG_INP_MASK) /*! @} */ /*! @name FLEXCOMM9_TRIG - LP_FLEXCOMM9 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM9_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM9_TRIG_INP_SHIFT (0U) /*! INP - LP_FLEXCOMM9 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected * 0b000011..SCT_OUT0 input is selected * 0b000100..SCT_OUT3 input is selected * 0b000101..SCT_OUT4 input is selected * 0b000110..CTIMER0_MAT1 input is selected * 0b000111..CTIMER1_MAT1 input is selected * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected * 0b010001..CMP2_OUT input is selected * 0b010010..EVTG_OUT0A input is selected * 0b010011..EVTG_OUT0B input is selected * 0b010100..EVTG_OUT1A input is selected * 0b010101..EVTG_OUT1B input is selected * 0b010110..EVTG_OUT2A input is selected * 0b010111..EVTG_OUT2B input is selected * 0b011000..EVTG_OUT3A input is selected * 0b011001..EVTG_OUT3B input is selected * 0b011010..TRIG_IN0 input is selected * 0b011011..TRIG_IN1 input is selected * 0b011100..TRIG_IN2 input is selected * 0b011101..TRIG_IN3 input is selected * 0b011110..TRIG_IN4 input is selected * 0b011111..TRIG_IN10 input is selected * 0b100000..TRIG_IN11 input is selected * 0b100001..FlexIO CH4 input is selected * 0b100010..FlexIO CH5 input is selected * 0b100011..FlexIO CH6 input is selected * 0b100100..FlexIO CH7 input is selected * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected * 0b100110..GPIO2 Pin Event Trig 0 input is selected * 0b100111..GPIO2 Pin Event Trig 1 input is selected * 0b101000..GPIO3 Pin Event Trig 0 input is selected * 0b101001..GPIO3 Pin Event Trig 1 input is selected * 0b101010..WUU input is selected * *.. */ #define INPUTMUX_FLEXCOMM9_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM9_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM9_TRIG_INP_MASK) /*! @} */ /*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU) #define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U) /*! INP - Input number for FlexIO0. * 0b0000000..PINT PIN_INT4 input is selected * 0b0000001..PINT PIN_INT5 input is selected * 0b0000010..PINT PIN_INT6 input is selected * 0b0000011..PINT PIN_INT7 input is selected * 0b0000100..SCT_OUT5 input is selected * 0b0000101..SCT_OUT6 input is selected * 0b0000110..SCT_OUT7 input is selected * 0b0000111..SCT_OUT8 input is selected * 0b0001000..SCT_OUT9 input is selected * 0b0001001..T0_MAT1 input is selected * 0b0001010..T1_MAT1 input is selected * 0b0001011..T2_MAT1 input is selected * 0b0001100..T3_MAT1 input is selected * 0b0001101..T4_MAT1 input is selected * 0b0001110..LPTMR0 input is selected * 0b0001111..LPTMR1 input is selected * 0b0010000..Reserved * 0b0010001..PINT GPIO_INT_BMAT input is selected * 0b0010010..ADC0_tcomp[0] input is selected * 0b0010011..ADC0_tcomp[1] input is selected * 0b0010100..ADC0_tcomp[2] input is selected * 0b0010101..ADC0_tcomp[3] input is selected * 0b0010110..ADC1_tcomp[0] input is selected * 0b0010111..ADC1_tcomp[1] input is selected * 0b0011000..ADC1_tcomp[2] input is selected * 0b0011001..ADC1_tcomp[3] input is selected * 0b0011010..CMP0_OUT input is selected * 0b0011011..CMP1_OUT input is selected * 0b0011100..CMP2_OUT input is selected * 0b0011101..PWM0_SM0_MUX_TRIG0 input is selected * 0b0011110..PWM0_SM0_MUX_TRIG1 input is selected * 0b0011111..PWM0_SM1_MUX_TRIG0 input is selected * 0b0100000..PWM0_SM1_MUX_TRIG1 input is selected * 0b0100001..PWM0_SM2_MUX_TRIG0 input is selected * 0b0100010..PWM0_SM2_MUX_TRIG1 input is selected * 0b0100011..PWM0_SM3_MUX_TRIG0 input is selected * 0b0100100..PWM0_SM3_MUX_TRIG1 input is selected * 0b0100101..PWM1_SM0_MUX_TRIG0 input is selected * 0b0100110..PWM1_SM0_MUX_TRIG1 input is selected * 0b0100111..PWM1_SM1_MUX_TRIG0 input is selected * 0b0101000..PWM1_SM1_MUX_TRIG1 input is selected * 0b0101001..PWM1_SM2_MUX_TRIG0 input is selected * 0b0101010..PWM1_SM2_MUX_TRIG1 input is selected * 0b0101011..PWM1_SM3_MUX_TRIG0 input is selected * 0b0101100..PWM1_SM3_MUX_TRIG1 input is selected * 0b0101101..EVTG_OUT0A input is selected * 0b0101110..EVTG_OUT0B input is selected * 0b0101111..EVTG_OUT1A input is selected * 0b0110000..EVTG_OUT1B input is selected * 0b0110001..EVTG_OUT2A input is selected * 0b0110010..EVTG_OUT2B input is selected * 0b0110011..EVTG_OUT3A input is selected * 0b0110100..EVTG_OUT3B input is selected * 0b0110101..TRIG_IN0 input is selected * 0b0110110..TRIG_IN1 input is selected * 0b0110111..TRIG_IN2 input is selected * 0b0111000..TRIG_IN3 input is selected * 0b0111001..TRIG_IN4 input is selected * 0b0111010..SINC Filter CH0 Conversion Complete input is selected * 0b0111011..SINC Filter CH1 Conversion Complete input is selected * 0b0111100..SINC Filter CH2 Conversion Complete input is selected * 0b0111101..SINC Filter CH3 Conversion Complete input is selected * 0b0111110..SINC Filter CH4 Conversion Complete input is selected * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected * 0b1001100..WUU input is selected * *.. */ #define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK) /*! @} */ /* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */ #define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT (8U) /*! @name DMA0_REQ_ENABLE0 - DMA0 Request Enable0 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0_SHIFT (1U) /*! REQ1_EN0 - This register is used to enable and disable FLEXSPI0 receive event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ1_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0_SHIFT (2U) /*! REQ2_EN0 - This register is used to enable and disable FLEXSPI0 transmit event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ2_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT (3U) /*! REQ3_EN0 - This register is used to enable and disable PINT0 INT0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT (4U) /*! REQ4_EN0 - This register is used to enable and disable PINT0 INT1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT (5U) /*! REQ5_EN0 - This register is used to enable and disable PINT0 INT2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT (6U) /*! REQ6_EN0 - This register is used to enable and disable PINT0 INT3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT (7U) /*! REQ7_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT (8U) /*! REQ8_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT (9U) /*! REQ9_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT (10U) /*! REQ10_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT (11U) /*! REQ11_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT (12U) /*! REQ12_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT (13U) /*! REQ13_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT (14U) /*! REQ14_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT (15U) /*! REQ15_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT (16U) /*! REQ16_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT (17U) /*! REQ17_EN0 - This register is used to enable and disable WUU0 wake up event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT (18U) /*! REQ18_EN0 - This register is used to enable and disable MICFIL0 FIFO_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_SHIFT (19U) /*! REQ19_EN0 - This register is used to enable and disable SCT0 DMA0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_SHIFT (20U) /*! REQ20_EN0 - This register is used to enable and disable SCT0 DMA1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT (21U) /*! REQ21_EN0 - This register is used to enable and disable ADC0 FIFO A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT (22U) /*! REQ22_EN0 - This register is used to enable and disable ADC0 FIFO B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT (23U) /*! REQ23_EN0 - This register is used to enable and disable ADC1 FIFO A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT (24U) /*! REQ24_EN0 - This register is used to enable and disable ADC1 FIFO B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_SHIFT (25U) /*! REQ25_EN0 - This register is used to enable and disable DAC0 FIFO_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_SHIFT (26U) /*! REQ26_EN0 - This register is used to enable and disable DAC1 FIFO_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_SHIFT (27U) /*! REQ27_EN0 - This register is used to enable and disable DAC2 FIFO_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT (28U) /*! REQ28_EN0 - This register is used to enable and disable CMP0 DMA_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT (29U) /*! REQ29_EN0 - This register is used to enable and disable CMP1 DMA_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_SHIFT (30U) /*! REQ30_EN0 - This register is used to enable and disable CMP2 DMA_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT (31U) /*! REQ31_EN0 - This register is used to enable and disable EVTG0 OUT0A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE0_SET - DMA0 Request Enable0 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0_SHIFT (1U) /*! REQ1_EN0 - Writing a 1 to REQ1_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ1_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0_SHIFT (2U) /*! REQ2_EN0 - Writing a 1 to REQ2_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ2_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT (3U) /*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT (4U) /*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT (5U) /*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT (6U) /*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT (7U) /*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT (8U) /*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT (9U) /*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT (10U) /*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT (11U) /*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT (12U) /*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT (13U) /*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT (14U) /*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT (15U) /*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT (16U) /*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT (17U) /*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT (18U) /*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0_SHIFT (19U) /*! REQ19_EN0 - Writing a 1 to REQ19_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ19_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0_SHIFT (20U) /*! REQ20_EN0 - Writing a 1 to REQ20_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ20_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT (21U) /*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT (22U) /*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT (23U) /*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT (24U) /*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0_SHIFT (25U) /*! REQ25_EN0 - Writing a 1 to REQ25_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ25_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0_SHIFT (26U) /*! REQ26_EN0 - Writing a 1 to REQ26_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ26_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0_SHIFT (27U) /*! REQ27_EN0 - Writing a 1 to REQ27_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ27_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT (28U) /*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT (29U) /*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0_SHIFT (30U) /*! REQ30_EN0 - Writing a 1 to REQ30_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ30_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT (31U) /*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE0_CLR - DMA0 Request Enable0 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0_SHIFT (1U) /*! REQ1_EN0 - Writing a 1 to REQ1_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ1_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0_SHIFT (2U) /*! REQ2_EN0 - Writing a 1 to REQ2_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ2_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT (3U) /*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT (4U) /*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT (5U) /*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT (6U) /*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT (7U) /*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT (8U) /*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT (9U) /*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT (10U) /*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT (11U) /*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT (12U) /*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT (13U) /*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT (14U) /*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT (15U) /*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT (16U) /*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT (17U) /*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT (18U) /*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0_SHIFT (19U) /*! REQ19_EN0 - Writing a 1 to REQ19_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ19_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0_SHIFT (20U) /*! REQ20_EN0 - Writing a 1 to REQ20_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ20_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT (21U) /*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT (22U) /*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT (23U) /*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT (24U) /*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0_SHIFT (25U) /*! REQ25_EN0 - Writing a 1 to REQ25_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ25_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0_SHIFT (26U) /*! REQ26_EN0 - Writing a 1 to REQ26_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ26_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0_SHIFT (27U) /*! REQ27_EN0 - Writing a 1 to REQ27_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ27_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT (28U) /*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT (29U) /*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0_SHIFT (30U) /*! REQ30_EN0 - Writing a 1 to REQ30_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ30_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT (31U) /*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE0_TOG - DMA0 Request Enable0 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0_SHIFT (1U) /*! REQ1_EN0 - Writing a 1 to REQ1_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ1_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0_SHIFT (2U) /*! REQ2_EN0 - Writing a 1 to REQ2_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ2_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT (3U) /*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT (4U) /*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT (5U) /*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT (6U) /*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT (7U) /*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT (8U) /*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT (9U) /*! REQ9_EN0 - Writing a 1 to RE9_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT (10U) /*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT (11U) /*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT (12U) /*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT (13U) /*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT (14U) /*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT (15U) /*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT (16U) /*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT (17U) /*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT (18U) /*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0_SHIFT (19U) /*! REQ19_EN0 - Writing a 1 to REQ19_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ19_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0_SHIFT (20U) /*! REQ20_EN0 - Writing a 1 to REQ20_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ20_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT (21U) /*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT (22U) /*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT (23U) /*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT (24U) /*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0_SHIFT (25U) /*! REQ25_EN0 - Writing a 1 to REQ25_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ25_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0_SHIFT (26U) /*! REQ26_EN0 - Writing a 1 to REQ26_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ26_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0_SHIFT (27U) /*! REQ27_EN0 - Writing a 1 to REQ27_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ27_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT (28U) /*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT (29U) /*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0_SHIFT (30U) /*! REQ30_EN0 - Writing a 1 to REQ30_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ30_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT (31U) /*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ #define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE1 - DMA0 Request Enable1 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT (0U) /*! REQ32_EN0 - This register is used to enable and disable EVTG0 OUT0B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT (1U) /*! REQ33_EN0 - This register is used to enable and disable EVTG0 OUT1A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT (2U) /*! REQ34_EN0 - This register is used to enable and disable EVTG0 OUT1B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT (3U) /*! REQ35_EN0 - This register is used to enable and disable EVTG0 OUT2A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT (4U) /*! REQ36_EN0 - This register is used to enable and disable EVTG0 OUT2B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT (5U) /*! REQ37_EN0 - This register is used to enable and disable EVTG0 OUT3A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT (6U) /*! REQ38_EN0 - This register is used to enable and disable EVTG0 OUT3B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT (7U) /*! REQ39_EN0 - This register is used to enable and disable PWM0 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT (8U) /*! REQ40_EN0 - This register is used to enable and disable PWM0 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT (9U) /*! REQ41_EN0 - This register is used to enable and disable PWM0 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT (10U) /*! REQ42_EN0 - This register is used to enable and disable PWM0 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT (11U) /*! REQ43_EN0 - This register is used to enable and disable PWM0 Req_val0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT (12U) /*! REQ44_EN0 - This register is used to enable and disable PWM0 Req_val1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT (13U) /*! REQ45_EN0 - This register is used to enable and disable PWM0 Req_val2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT (14U) /*! REQ46_EN0 - This register is used to enable and disable PWM0 Req_val3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT (15U) /*! REQ47_EN0 - This register is used to enable and disable PWM1 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT (16U) /*! REQ48_EN0 - This register is used to enable and disable PWM1 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT (17U) /*! REQ49_EN0 - This register is used to enable and disable PWM1 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT (18U) /*! REQ50_EN0 - This register is used to enable and disable PWM1 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT (19U) /*! REQ51_EN0 - This register is used to enable and disable PWM1 Req_val0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT (20U) /*! REQ52_EN0 - This register is used to enable and disable PWM1 Req_val1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT (21U) /*! REQ53_EN0 - This register is used to enable and disable PWM1 Req_val2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT (22U) /*! REQ54_EN0 - This register is used to enable and disable PWM1 Req_val3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - This register is used to enable and disable LPTMR0 counter match event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT (26U) /*! REQ58_EN0 - This register is used to enable and disable LPTMR1 counter match event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT (27U) /*! REQ59_EN0 - This register is used to enable and disable CAN0 DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT (28U) /*! REQ60_EN0 - This register is used to enable and disable CAN1 DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT (29U) /*! REQ61_EN0 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT (30U) /*! REQ62_EN0 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT (31U) /*! REQ63_EN0 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE1_SET - DMA0 Request Enable1 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT (0U) /*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT (1U) /*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT (2U) /*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT (3U) /*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT (4U) /*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT (5U) /*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT (6U) /*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT (7U) /*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT (8U) /*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT (9U) /*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT (10U) /*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT (11U) /*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT (12U) /*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT (13U) /*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT (14U) /*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT (15U) /*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT (16U) /*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT (17U) /*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT (18U) /*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT (19U) /*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT (20U) /*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT (21U) /*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT (22U) /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT (26U) /*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT (27U) /*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT (28U) /*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT (29U) /*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT (30U) /*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT (31U) /*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE1_CLR - DMA0 Request Enable1 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT (0U) /*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT (1U) /*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT (2U) /*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT (3U) /*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT (4U) /*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT (5U) /*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT (6U) /*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT (7U) /*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT (8U) /*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT (9U) /*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT (10U) /*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT (11U) /*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT (12U) /*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT (13U) /*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT (14U) /*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT (15U) /*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT (16U) /*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT (17U) /*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT (18U) /*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT (19U) /*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT (20U) /*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT (21U) /*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT (22U) /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT (26U) /*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT (27U) /*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT (28U) /*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT (29U) /*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT (30U) /*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT (31U) /*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE1_TOG - DMA0 Request Enable1 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT (0U) /*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT (1U) /*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT (2U) /*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT (3U) /*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT (4U) /*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT (5U) /*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT (6U) /*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT (7U) /*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT (8U) /*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT (9U) /*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT (10U) /*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT (11U) /*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT (12U) /*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT (13U) /*! REQ45_EN0 - Writing a 1 to REQ55_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT (14U) /*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT (15U) /*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT (16U) /*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT (17U) /*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT (18U) /*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT (19U) /*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT (20U) /*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT (21U) /*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT (22U) /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT (26U) /*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT (27U) /*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT (28U) /*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT (29U) /*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT (30U) /*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT (31U) /*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE2 - DMA0 Request Enable2 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT (0U) /*! REQ64_EN0 - This register is used to enable and disable FlexIO0 shift register 3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT (1U) /*! REQ65_EN0 - This register is used to enable and disable FlexIO0 shift register 4 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT (2U) /*! REQ66_EN0 - This register is used to enable and disable FlexIO0 shift register 5 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT (3U) /*! REQ67_EN0 - This register is used to enable and disable FlexIO0 shift register 6 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT (4U) /*! REQ68_EN0 - This register is used to enable and disable FlexIO0 shift register 7 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT (5U) /*! REQ69_EN0 - This register is used to enable and disable LP_FLEXCOMM0 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT (6U) /*! REQ70_EN0 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT (7U) /*! REQ71_EN0 - This register is used to enable and disable LP_FLEXCOMM1 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT (8U) /*! REQ72_EN0 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT (9U) /*! REQ73_EN0 - This register is used to enable and disable LP_FLEXCOMM2 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT (10U) /*! REQ74_EN0 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT (11U) /*! REQ75_EN0 - This register is used to enable and disable LP_FLEXCOMM3 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT (12U) /*! REQ76_EN0 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT (13U) /*! REQ77_EN0 - This register is used to enable and disable LP_FLEXCOMM4 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT (14U) /*! REQ78_EN0 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT (15U) /*! REQ79_EN0 - This register is used to enable and disable LP_FLEXCOMM5 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT (16U) /*! REQ80_EN0 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT (17U) /*! REQ81_EN0 - This register is used to enable and disable LP_FLEXCOMM6 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT (18U) /*! REQ82_EN0 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT (19U) /*! REQ83_EN0 - This register is used to enable and disable LP_FLEXCOMM7 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT (20U) /*! REQ84_EN0 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_SHIFT (21U) /*! REQ85_EN0 - This register is used to enable and disable LP_FLEXCOMM8 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_SHIFT (22U) /*! REQ86_EN0 - This register is used to enable and disable LP_FLEXCOMM8 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_SHIFT (23U) /*! REQ87_EN0 - This register is used to enable and disable LP_FLEXCOMM9 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_SHIFT (24U) /*! REQ88_EN0 - This register is used to enable and disable LP_FLEXCOMM9 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - This register is used to enable and disable EMVSIM0 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_SHIFT (28U) /*! REQ92_EN0 - This register is used to enable and disable EMVSIM0 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_SHIFT (29U) /*! REQ93_EN0 - This register is used to enable and disable EMVSIM1 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_SHIFT (30U) /*! REQ94_EN0 - This register is used to enable and disable EMVSIM1 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT (31U) /*! REQ95_EN0 - This register is used to enable and disable I3C0 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE2_SET - DMA0 Request Enable2 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT (0U) /*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT (1U) /*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT (2U) /*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT (3U) /*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT (4U) /*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT (5U) /*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT (6U) /*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT (7U) /*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT (8U) /*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT (9U) /*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT (10U) /*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT (11U) /*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT (12U) /*! REQ76_EN0 - Writing a 1 to REQ876_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT (13U) /*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT (14U) /*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT (15U) /*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT (16U) /*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT (17U) /*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT (18U) /*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT (19U) /*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT (20U) /*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0_SHIFT (21U) /*! REQ85_EN0 - Writing a 1 to REQ85_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ85_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0_SHIFT (22U) /*! REQ86_EN0 - Writing a 1 to REQ86_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ86_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0_SHIFT (23U) /*! REQ87_EN0 - Writing a 1 to REQ87_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ87_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_SHIFT (24U) /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0_SHIFT (28U) /*! REQ92_EN0 - Writing a 1 to REQ92_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ92_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0_SHIFT (29U) /*! REQ93_EN0 - Writing a 1 to REQ93_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ93_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0_SHIFT (30U) /*! REQ94_EN0 - Writing a 1 to REQ94_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ94_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT (31U) /*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE2_CLR - DMA0 Request Enable2 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT (0U) /*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT (1U) /*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT (2U) /*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT (3U) /*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT (4U) /*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT (5U) /*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT (6U) /*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT (7U) /*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT (8U) /*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT (9U) /*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT (10U) /*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT (11U) /*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT (12U) /*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT (13U) /*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT (14U) /*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT (15U) /*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT (16U) /*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT (17U) /*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT (18U) /*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT (19U) /*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT (20U) /*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0_SHIFT (21U) /*! REQ85_EN0 - Writing a 1 to REQ85_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ85_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0_SHIFT (22U) /*! REQ86_EN0 - Writing a 1 to REQ86_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ86_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0_SHIFT (23U) /*! REQ87_EN0 - Writing a 1 to REQ87_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ87_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_SHIFT (24U) /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0_SHIFT (28U) /*! REQ92_EN0 - Writing a 1 to REQ92_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ92_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0_SHIFT (29U) /*! REQ93_EN0 - Writing a 1 to REQ93_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ93_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0_SHIFT (30U) /*! REQ94_EN0 - Writing a 1 to REQ94_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ94_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT (31U) /*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE2_TOG - DMA0 Request Enable2 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT (0U) /*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT (1U) /*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT (2U) /*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT (3U) /*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT (4U) /*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT (5U) /*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT (6U) /*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT (7U) /*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT (8U) /*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT (9U) /*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT (10U) /*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT (11U) /*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT (12U) /*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT (13U) /*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT (14U) /*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT (15U) /*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT (16U) /*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT (17U) /*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT (18U) /*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT (19U) /*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT (20U) /*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0_SHIFT (21U) /*! REQ85_EN0 - Writing a 1 to REQ85_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ85_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0_SHIFT (22U) /*! REQ86_EN0 - Writing a 1 to REQ86_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ86_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0_SHIFT (23U) /*! REQ87_EN0 - Writing a 1 to REQ87_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ87_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_SHIFT (24U) /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0_SHIFT (28U) /*! REQ92_EN0 - Writing a 1 to REQ92_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ92_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0_SHIFT (29U) /*! REQ93_EN0 - Writing a 1 to REQ93_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ93_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0_SHIFT (30U) /*! REQ94_EN0 - Writing a 1 to REQ94_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ94_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT (31U) /*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE3 - DMA0 Request Enable3 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT (0U) /*! REQ96_EN0 - This register is used to enable and disable I3C0 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT (1U) /*! REQ97_EN0 - This register is used to enable and disable I3C1 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT (2U) /*! REQ98_EN0 - This register is used to enable and disable I3C1 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT (3U) /*! REQ99_EN0 - This register is used to enable and disable SAI0 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT (4U) /*! REQ100_EN0 - This register is used to enable and disable SAI0 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT (5U) /*! REQ101_EN0 - This register is used to enable and disable SAI1 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT (6U) /*! REQ102_EN0 - This register is used to enable and disable SAI1 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_SHIFT (7U) /*! REQ103_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[0] or ipd_req_alt [0] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_SHIFT (8U) /*! REQ104_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[1] or ipd_req_alt [1] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_SHIFT (9U) /*! REQ105_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[2] or ipd_req_alt [2] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_SHIFT (10U) /*! REQ106_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[3] or ipd_req_alt [3] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_SHIFT (11U) /*! REQ107_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[4] or ipd_req_alt [4] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT (12U) /*! REQ108_EN0 - This register is used to enable and disable GPIO0 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT (13U) /*! REQ109_EN0 - This register is used to enable and disable GPIO0 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT (14U) /*! REQ110_EN0 - This register is used to enable and disable GPIO1 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT (15U) /*! REQ111_EN0 - This register is used to enable and disable GPIO1 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT (16U) /*! REQ112_EN0 - This register is used to enable and disable GPIO2 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT (17U) /*! REQ113_EN0 - This register is used to enable and disable GPIO2 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT (18U) /*! REQ114_EN0 - This register is used to enable and disable GPIO3 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT (19U) /*! REQ115_EN0 - This register is used to enable and disable GPIO3 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT (20U) /*! REQ116_EN0 - This register is used to enable and disable GPIO4 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT (21U) /*! REQ117_EN0 - This register is used to enable and disable GPIO4 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT (22U) /*! REQ118_EN0 - This register is used to enable and disable GPIO5 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT (23U) /*! REQ119_EN0 - This register is used to enable and disable GPIO5 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_SHIFT (24U) /*! REQ120_EN0 - This register is used to enable and disable TSI0 end of scan request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_SHIFT (25U) /*! REQ121_EN0 - This register is used to enable and disable TSI0 out of range request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE3_SET - DMA0 Request Enable3 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT (0U) /*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT (1U) /*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT (2U) /*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT (3U) /*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT (4U) /*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT (5U) /*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT (6U) /*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0_SHIFT (7U) /*! REQ103_EN0 - Writing a 1 to REQ103_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ103_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0_SHIFT (8U) /*! REQ104_EN0 - Writing a 1 to REQ104_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ104_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0_SHIFT (9U) /*! REQ105_EN0 - Writing a 1 to REQ105_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ105_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0_SHIFT (10U) /*! REQ106_EN0 - Writing a 1 to REQ106_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ106_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0_SHIFT (11U) /*! REQ107_EN0 - Writing a 1 to REQ107_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ107_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT (12U) /*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT (13U) /*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT (14U) /*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT (15U) /*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT (16U) /*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT (17U) /*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT (18U) /*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT (19U) /*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT (20U) /*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT (21U) /*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT (22U) /*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT (23U) /*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0_SHIFT (24U) /*! REQ120_EN0 - Writing a 1 to REQ120_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ120_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0_SHIFT (25U) /*! REQ121_EN0 - Writing a 1 to REQ121_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ121_EN0_MASK) /*! @} */ /*! @name DMA0_REQ_ENABLE3_CLR - DMA0 Request Enable3 */ /*! @{ */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT (0U) /*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT (1U) /*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT (2U) /*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT (3U) /*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT (4U) /*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT (5U) /*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT (6U) /*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0_SHIFT (7U) /*! REQ103_EN0 - Writing a 1 to REQ103_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ103_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0_SHIFT (8U) /*! REQ104_EN0 - Writing a 1 to REQ104_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ104_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0_SHIFT (9U) /*! REQ105_EN0 - Writing a 1 to REQ105_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ105_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0_SHIFT (10U) /*! REQ106_EN0 - Writing a 1 to REQ106_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ106_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0_SHIFT (11U) /*! REQ107_EN0 - Writing a 1 to REQ107_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ107_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT (12U) /*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT (13U) /*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT (14U) /*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT (15U) /*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT (16U) /*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT (17U) /*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT (18U) /*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT (19U) /*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT (20U) /*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT (21U) /*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT (22U) /*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT (23U) /*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0_SHIFT (24U) /*! REQ120_EN0 - Writing a 1 to REQ120_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ120_EN0_MASK) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0_SHIFT (25U) /*! REQ121_EN0 - Writing a 1 to REQ121_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ121_EN0_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE0 - DMA1 Request Enable0 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1_SHIFT (1U) /*! REQ1_EN1 - This register is used to enable and disable FLEXSPI0 receive event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ1_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1_SHIFT (2U) /*! REQ2_EN1 - This register is used to enable and disable FLEXSPI0 transmit event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ2_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT (3U) /*! REQ3_EN1 - This register is used to enable and disable PINT0 INT0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT (4U) /*! REQ4_EN1 - This register is used to enable and disable PINT0 INT1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT (5U) /*! REQ5_EN1 - This register is used to enable and disable PINT0 INT2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT (6U) /*! REQ6_EN1 - This register is used to enable and disable PINT0 INT3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT (7U) /*! REQ7_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT (8U) /*! REQ8_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT (9U) /*! REQ9_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT (10U) /*! REQ10_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT (11U) /*! REQ11_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT (12U) /*! REQ12_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT (13U) /*! REQ13_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT (14U) /*! REQ14_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT (15U) /*! REQ15_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT (16U) /*! REQ16_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT (17U) /*! REQ17_EN1 - This register is used to enable and disable WUU0 wake up event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT (18U) /*! REQ18_EN1 - This register is used to enable and disable MICFIL0 FIFO_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_SHIFT (19U) /*! REQ19_EN1 - This register is used to enable and disable SCT0 DMA0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_SHIFT (20U) /*! REQ20_EN1 - This register is used to enable and disable SCT0 DMA1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT (21U) /*! REQ21_EN1 - This register is used to enable and disable ADC0 FIFO A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT (22U) /*! REQ22_EN1 - This register is used to enable and disable ADC0 FIFO B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT (23U) /*! REQ23_EN1 - This register is used to enable and disable ADC1 FIFO A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT (24U) /*! REQ24_EN1 - This register is used to enable and disable ADC1 FIFO B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_SHIFT (25U) /*! REQ25_EN1 - This register is used to enable and disable DAC0 FIFO_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_SHIFT (26U) /*! REQ26_EN1 - This register is used to enable and disable DAC1 FIFO_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_SHIFT (27U) /*! REQ27_EN1 - This register is used to enable and disable DAC2 FIFO_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT (28U) /*! REQ28_EN1 - This register is used to enable and disable CMP0 DMA_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT (29U) /*! REQ29_EN1 - This register is used to enable and disable CMP1 DMA_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_SHIFT (30U) /*! REQ30_EN1 - This register is used to enable and disable CMP2 DMA_request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT (31U) /*! REQ31_EN1 - This register is used to enable and disable EVTG0 OUT0A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE0_SET - DMA1 Request Enable0 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1_SHIFT (1U) /*! REQ1_EN1 - Writing a 1 to REQ1_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ1_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1_SHIFT (2U) /*! REQ2_EN1 - Writing a 1 to REQ2_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ2_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT (3U) /*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT (4U) /*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT (5U) /*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT (6U) /*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT (7U) /*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT (8U) /*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT (9U) /*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT (10U) /*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT (11U) /*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT (12U) /*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT (13U) /*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT (14U) /*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT (15U) /*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT (16U) /*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT (17U) /*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT (18U) /*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1_SHIFT (19U) /*! REQ19_EN1 - Writing a 1 to REQ19_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ19_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1_SHIFT (20U) /*! REQ20_EN1 - Writing a 1 to REQ20_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ20_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT (21U) /*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT (22U) /*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT (23U) /*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT (24U) /*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1_SHIFT (25U) /*! REQ25_EN1 - Writing a 1 to REQ25_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ25_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1_SHIFT (26U) /*! REQ26_EN1 - Writing a 1 to REQ26_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ26_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1_SHIFT (27U) /*! REQ27_EN1 - Writing a 1 to REQ27_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ27_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT (28U) /*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT (29U) /*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1_SHIFT (30U) /*! REQ30_EN1 - Writing a 1 to REQ30_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ30_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT (31U) /*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE0_CLR - DMA1 Request Enable0 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1_SHIFT (1U) /*! REQ1_EN1 - Writing a 1 to REQ1_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ1_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1_SHIFT (2U) /*! REQ2_EN1 - Writing a 1 to REQ2_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ2_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT (3U) /*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT (4U) /*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT (5U) /*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT (6U) /*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT (7U) /*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT (8U) /*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT (9U) /*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT (10U) /*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT (11U) /*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT (12U) /*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT (13U) /*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT (14U) /*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT (15U) /*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT (16U) /*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT (17U) /*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT (18U) /*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1_SHIFT (19U) /*! REQ19_EN1 - Writing a 1 to REQ19_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ19_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1_SHIFT (20U) /*! REQ20_EN1 - Writing a 1 to REQ20_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ20_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT (21U) /*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT (22U) /*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT (23U) /*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT (24U) /*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1_SHIFT (25U) /*! REQ25_EN1 - Writing a 1 to REQ25_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ25_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1_SHIFT (26U) /*! REQ26_EN1 - Writing a 1 to REQ26_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ26_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1_SHIFT (27U) /*! REQ27_EN1 - Writing a 1 to REQ27_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ27_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT (28U) /*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT (29U) /*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1_SHIFT (30U) /*! REQ30_EN1 - Writing a 1 to REQ30_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ30_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT (31U) /*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE0_TOG - DMA1 Request Enable0 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1_SHIFT (1U) /*! REQ1_EN1 - Writing a 1 to REQ1_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ1_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1_SHIFT (2U) /*! REQ2_EN1 - Writing a 1 to REQ2_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ2_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT (3U) /*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT (4U) /*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT (5U) /*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT (6U) /*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT (7U) /*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT (8U) /*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT (9U) /*! REQ9_EN1 - Writing a 1 to RE9_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT (10U) /*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT (11U) /*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT (12U) /*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT (13U) /*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT (14U) /*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT (15U) /*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT (16U) /*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT (17U) /*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT (18U) /*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1_SHIFT (19U) /*! REQ19_EN1 - Writing a 1 to REQ19_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ19_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1_SHIFT (20U) /*! REQ20_EN1 - Writing a 1 to REQ20_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ20_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT (21U) /*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT (22U) /*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT (23U) /*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT (24U) /*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1_SHIFT (25U) /*! REQ25_EN1 - Writing a 1 to REQ25_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ25_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1_SHIFT (26U) /*! REQ26_EN1 - Writing a 1 to REQ26_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ26_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1_SHIFT (27U) /*! REQ27_EN1 - Writing a 1 to REQ27_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ27_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT (28U) /*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT (29U) /*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1_SHIFT (30U) /*! REQ30_EN1 - Writing a 1 to REQ30_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ30_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT (31U) /*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ #define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE1 - DMA1 Request Enable1 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT (0U) /*! REQ32_EN1 - This register is used to enable and disable EVTG0 OUT0B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT (1U) /*! REQ33_EN1 - This register is used to enable and disable EVTG0 OUT1A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT (2U) /*! REQ34_EN1 - This register is used to enable and disable EVTG0 OUT1B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT (3U) /*! REQ35_EN1 - This register is used to enable and disable EVTG0 OUT2A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT (4U) /*! REQ36_EN1 - This register is used to enable and disable EVTG0 OUT2B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT (5U) /*! REQ37_EN1 - This register is used to enable and disable EVTG0 OUT3A request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT (6U) /*! REQ38_EN1 - This register is used to enable and disable EVTG0 OUT3B request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT (7U) /*! REQ39_EN1 - This register is used to enable and disable PWM0 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT (8U) /*! REQ40_EN1 - This register is used to enable and disable PWM0 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT (9U) /*! REQ41_EN1 - This register is used to enable and disable PWM0 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT (10U) /*! REQ42_EN1 - This register is used to enable and disable PWM0 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT (11U) /*! REQ43_EN1 - This register is used to enable and disable PWM0 Req_val0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT (12U) /*! REQ44_EN1 - This register is used to enable and disable PWM0 Req_val1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT (13U) /*! REQ45_EN1 - This register is used to enable and disable PWM0 Req_val2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT (14U) /*! REQ46_EN1 - This register is used to enable and disable PWM0 Req_val3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT (15U) /*! REQ47_EN1 - This register is used to enable and disable PWM1 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT (16U) /*! REQ48_EN1 - This register is used to enable and disable PWM1 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT (17U) /*! REQ49_EN1 - This register is used to enable and disable PWM1 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT (18U) /*! REQ50_EN1 - This register is used to enable and disable PWM1 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT (19U) /*! REQ51_EN1 - This register is used to enable and disable PWM1 Req_val0 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT (20U) /*! REQ52_EN1 - This register is used to enable and disable PWM1 Req_val1 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT (21U) /*! REQ53_EN1 - This register is used to enable and disable PWM1 Req_val2 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT (22U) /*! REQ54_EN1 - This register is used to enable and disable PWM1 Req_val3 request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - This register is used to enable and disable LPTMR0 counter match event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT (26U) /*! REQ58_EN1 - This register is used to enable and disable LPTMR1 counter match event request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT (27U) /*! REQ59_EN1 - This register is used to enable and disable CAN0 DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT (28U) /*! REQ60_EN1 - This register is used to enable and disable CAN1 DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT (29U) /*! REQ61_EN1 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT (30U) /*! REQ62_EN1 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT (31U) /*! REQ63_EN1 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE1_SET - DMA1 Request Enable1 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT (0U) /*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT (1U) /*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT (2U) /*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT (3U) /*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT (4U) /*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT (5U) /*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT (6U) /*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT (7U) /*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT (8U) /*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT (9U) /*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT (10U) /*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT (11U) /*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT (12U) /*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT (13U) /*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT (14U) /*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT (15U) /*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT (16U) /*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT (17U) /*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT (18U) /*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT (19U) /*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT (20U) /*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT (21U) /*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT (22U) /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT (26U) /*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT (27U) /*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT (28U) /*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT (29U) /*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT (30U) /*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT (31U) /*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE1_CLR - DMA1 Request Enable1 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT (0U) /*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT (1U) /*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT (2U) /*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT (3U) /*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT (4U) /*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT (5U) /*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT (6U) /*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT (7U) /*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT (8U) /*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT (9U) /*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT (10U) /*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT (11U) /*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT (12U) /*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT (13U) /*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT (14U) /*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT (15U) /*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT (16U) /*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT (17U) /*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT (18U) /*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT (19U) /*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT (20U) /*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT (21U) /*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT (22U) /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT (26U) /*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT (27U) /*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT (28U) /*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT (29U) /*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT (30U) /*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT (31U) /*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE1_TOG - DMA1 Request Enable1 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT (0U) /*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT (1U) /*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT (2U) /*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT (3U) /*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT (4U) /*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT (5U) /*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT (6U) /*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT (7U) /*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT (8U) /*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT (9U) /*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT (10U) /*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT (11U) /*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT (12U) /*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT (13U) /*! REQ45_EN1 - Writing a 1 to REQ55_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT (14U) /*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT (15U) /*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT (16U) /*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT (17U) /*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT (18U) /*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT (19U) /*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT (20U) /*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT (21U) /*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT (22U) /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT (26U) /*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT (27U) /*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT (28U) /*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT (29U) /*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT (30U) /*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT (31U) /*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE2 - DMA1 Request Enable2 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT (0U) /*! REQ64_EN1 - This register is used to enable and disable FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT (1U) /*! REQ65_EN1 - This register is used to enable and disable FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT (2U) /*! REQ66_EN1 - This register is used to enable and disable FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT (3U) /*! REQ67_EN1 - This register is used to enable and disable FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT (4U) /*! REQ68_EN1 - This register is used to enable and disable FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT (5U) /*! REQ69_EN1 - This register is used to enable and disable LP_FLEXCOMM0 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT (6U) /*! REQ70_EN1 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT (7U) /*! REQ71_EN1 - This register is used to enable and disable LP_FLEXCOMM1 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT (8U) /*! REQ72_EN1 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT (9U) /*! REQ73_EN1 - This register is used to enable and disable LP_FLEXCOMM2 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT (10U) /*! REQ74_EN1 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT (11U) /*! REQ75_EN1 - This register is used to enable and disable LP_FLEXCOMM3 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT (12U) /*! REQ76_EN1 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT (13U) /*! REQ77_EN1 - This register is used to enable and disable LP_FLEXCOMM4 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT (14U) /*! REQ78_EN1 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT (15U) /*! REQ79_EN1 - This register is used to enable and disable LP_FLEXCOMM5 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT (16U) /*! REQ80_EN1 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT (17U) /*! REQ81_EN1 - This register is used to enable and disable LP_FLEXCOMM6 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT (18U) /*! REQ82_EN1 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT (19U) /*! REQ83_EN1 - This register is used to enable and disable LP_FLEXCOMM7 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT (20U) /*! REQ84_EN1 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_SHIFT (21U) /*! REQ85_EN1 - This register is used to enable and disable LP_FLEXCOMM8 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_SHIFT (22U) /*! REQ86_EN1 - This register is used to enable and disable LP_FLEXCOMM8 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_SHIFT (23U) /*! REQ87_EN1 - This register is used to enable and disable LP_FLEXCOMM9 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_SHIFT (24U) /*! REQ88_EN1 - This register is used to enable and disable LP_FLEXCOMM9 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_SHIFT (27U) /*! REQ91_EN1 - This register is used to enable and disable EMVSIM0 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_SHIFT (28U) /*! REQ92_EN1 - This register is used to enable and disable EMVSIM0 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_SHIFT (29U) /*! REQ93_EN1 - This register is used to enable and disable EMVSIM1 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_SHIFT (30U) /*! REQ94_EN1 - This register is used to enable and disable EMVSIM1 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT (31U) /*! REQ95_EN1 - This register is used to enable and disable I3C0 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE2_SET - DMA1 Request Enable2 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT (0U) /*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT (1U) /*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT (2U) /*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT (3U) /*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT (4U) /*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT (5U) /*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT (6U) /*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT (7U) /*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT (8U) /*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT (9U) /*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT (10U) /*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT (11U) /*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT (12U) /*! REQ76_EN1 - Writing a 1 to REQ876_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT (13U) /*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT (14U) /*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT (15U) /*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT (16U) /*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT (17U) /*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT (18U) /*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT (19U) /*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT (20U) /*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT (21U) /*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT (22U) /*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT (23U) /*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT (24U) /*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT (25U) /*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT (26U) /*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT (27U) /*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT (28U) /*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT (29U) /*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT (30U) /*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT (31U) /*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE2_CLR - DMA1 Request Enable2 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT (0U) /*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT (1U) /*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT (2U) /*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT (3U) /*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT (4U) /*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT (5U) /*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT (6U) /*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT (7U) /*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT (8U) /*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT (9U) /*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT (10U) /*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT (11U) /*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT (12U) /*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT (13U) /*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT (14U) /*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT (15U) /*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT (16U) /*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT (17U) /*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT (18U) /*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT (19U) /*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT (20U) /*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT (21U) /*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT (22U) /*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT (23U) /*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT (24U) /*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT (25U) /*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT (26U) /*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT (27U) /*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT (28U) /*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT (29U) /*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT (30U) /*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT (31U) /*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE2_TOG - DMA1 Request Enable2 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT (0U) /*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT (1U) /*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT (2U) /*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT (3U) /*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT (4U) /*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT (5U) /*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT (6U) /*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT (7U) /*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT (8U) /*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT (9U) /*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT (10U) /*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT (11U) /*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT (12U) /*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT (13U) /*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT (14U) /*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT (15U) /*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT (16U) /*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT (17U) /*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT (18U) /*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT (19U) /*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT (20U) /*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT (21U) /*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT (22U) /*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT (23U) /*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT (24U) /*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT (25U) /*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT (26U) /*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT (27U) /*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT (28U) /*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT (29U) /*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT (30U) /*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT (31U) /*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ #define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE3 - DMA1 Request Enable3 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) /*! REQ96_EN1 - This register is used to enable and disable I3C0 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT (1U) /*! REQ97_EN1 - This register is used to enable and disable I3C1 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT (2U) /*! REQ98_EN1 - This register is used to enable and disable I3C1 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT (3U) /*! REQ99_EN1 - This register is used to enable and disable SAI0 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT (4U) /*! REQ100_EN1 - This register is used to enable and disable SAI0 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT (5U) /*! REQ101_EN1 - This register is used to enable and disable SAI1 receive request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT (6U) /*! REQ102_EN1 - This register is used to enable and disable SAI1 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_SHIFT (7U) /*! REQ103_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[0] or ipd_req_alt [0] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_SHIFT (8U) /*! REQ104_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[1] or ipd_req_alt [1] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_SHIFT (9U) /*! REQ105_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[2] or ipd_req_alt [2] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_SHIFT (10U) /*! REQ106_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[3] or ipd_req_alt [3] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_SHIFT (11U) /*! REQ107_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[4] or ipd_req_alt [4] request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT (12U) /*! REQ108_EN1 - This register is used to enable and disable GPIO0 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT (13U) /*! REQ109_EN1 - This register is used to enable and disable GPIO0 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT (14U) /*! REQ110_EN1 - This register is used to enable and disable GPIO1 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT (15U) /*! REQ111_EN1 - This register is used to enable and disable GPIO1 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT (16U) /*! REQ112_EN1 - This register is used to enable and disable GPIO2 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT (17U) /*! REQ113_EN1 - This register is used to enable and disable GPIO2 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT (18U) /*! REQ114_EN1 - This register is used to enable and disable GPIO3 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT (19U) /*! REQ115_EN1 - This register is used to enable and disable GPIO3 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT (20U) /*! REQ116_EN1 - This register is used to enable and disable GPIO4 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT (21U) /*! REQ117_EN1 - This register is used to enable and disable GPIO4 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT (22U) /*! REQ118_EN1 - This register is used to enable and disable GPIO5 pin event request 0. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT (23U) /*! REQ119_EN1 - This register is used to enable and disable GPIO5 pin event request 1. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_SHIFT (24U) /*! REQ120_EN1 - This register is used to enable and disable TSI0 end of scan request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_SHIFT (25U) /*! REQ121_EN1 - This register is used to enable and disable TSI0 out of range request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE3_SET - DMA1 Request Enable3 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT (0U) /*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT (1U) /*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT (2U) /*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT (3U) /*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT (4U) /*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT (5U) /*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT (6U) /*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT (7U) /*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT (8U) /*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT (9U) /*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT (10U) /*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT (11U) /*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT (12U) /*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT (13U) /*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT (14U) /*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT (15U) /*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT (16U) /*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT (17U) /*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT (18U) /*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT (19U) /*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT (20U) /*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT (21U) /*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT (22U) /*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT (23U) /*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT (24U) /*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT (25U) /*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK) /*! @} */ /*! @name DMA1_REQ_ENABLE3_CLR - DMA1 Request Enable3 */ /*! @{ */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT (0U) /*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT (1U) /*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT (2U) /*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT (3U) /*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT (4U) /*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT (5U) /*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT (6U) /*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT (7U) /*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT (8U) /*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT (9U) /*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT (10U) /*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT (11U) /*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT (12U) /*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT (13U) /*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT (14U) /*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT (15U) /*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT (16U) /*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT (17U) /*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT (18U) /*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT (19U) /*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT (20U) /*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT (21U) /*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT (22U) /*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT (23U) /*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT (24U) /*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT (25U) /*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3. */ #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK) /*! @} */ /*! * @} */ /* end of group INPUTMUX_Register_Masks */ /* INPUTMUX - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral INPUTMUX0 base address */ #define INPUTMUX0_BASE (0x50006000u) /** Peripheral INPUTMUX0 base address */ #define INPUTMUX0_BASE_NS (0x40006000u) /** Peripheral INPUTMUX0 base pointer */ #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) /** Peripheral INPUTMUX0 base pointer */ #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) /** Array initializer of INPUTMUX peripheral base addresses */ #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } /** Array initializer of INPUTMUX peripheral base pointers */ #define INPUTMUX_BASE_PTRS { INPUTMUX0 } /** Array initializer of INPUTMUX peripheral base addresses */ #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } /** Array initializer of INPUTMUX peripheral base pointers */ #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } #else /** Peripheral INPUTMUX0 base address */ #define INPUTMUX0_BASE (0x40006000u) /** Peripheral INPUTMUX0 base pointer */ #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) /** Array initializer of INPUTMUX peripheral base addresses */ #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } /** Array initializer of INPUTMUX peripheral base pointers */ #define INPUTMUX_BASE_PTRS { INPUTMUX0 } #endif /* Backward compatibility for INPUTMUX */ #define INPUTMUX INPUTMUX0 /*! * @} */ /* end of group INPUTMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- INTM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup INTM_Peripheral_Access_Layer INTM Peripheral Access Layer * @{ */ /** INTM - Register Layout Typedef */ typedef struct { __IO uint32_t INTM_MM; /**< Monitor Mode, offset: 0x0 */ __O uint32_t INTM_IACK; /**< Interrupt Acknowledge, offset: 0x4 */ struct { /* offset: 0x8, array step: 0x10 */ __IO uint32_t INTM_IRQSEL; /**< Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3, array offset: 0x8, array step: 0x10 */ __IO uint32_t INTM_LATENCY; /**< Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3, array offset: 0xC, array step: 0x10 */ __IO uint32_t INTM_TIMER; /**< Timer for Monitor 0..Timer for Monitor 3, array offset: 0x10, array step: 0x10 */ __I uint32_t INTM_STATUS; /**< Status for Monitor 0..Status for Monitor 3, array offset: 0x14, array step: 0x10 */ } MON[4]; } INTM_Type; /* ---------------------------------------------------------------------------- -- INTM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup INTM_Register_Masks INTM Register Masks * @{ */ /*! @name INTM_MM - Monitor Mode */ /*! @{ */ #define INTM_INTM_MM_MM_MASK (0x1U) #define INTM_INTM_MM_MM_SHIFT (0U) /*! MM - Monitor Mode * 0b1..Enable * 0b0..Disable */ #define INTM_INTM_MM_MM(x) (((uint32_t)(((uint32_t)(x)) << INTM_INTM_MM_MM_SHIFT)) & INTM_INTM_MM_MM_MASK) /*! @} */ /*! @name INTM_IACK - Interrupt Acknowledge */ /*! @{ */ #define INTM_INTM_IACK_IRQ_MASK (0x3FFU) #define INTM_INTM_IACK_IRQ_SHIFT (0U) /*! IRQ - Interrupt Request */ #define INTM_INTM_IACK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << INTM_INTM_IACK_IRQ_SHIFT)) & INTM_INTM_IACK_IRQ_MASK) /*! @} */ /*! @name MON_INTM_IRQSEL - Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3 */ /*! @{ */ #define INTM_MON_INTM_IRQSEL_IRQ_MASK (0x3FFU) #define INTM_MON_INTM_IRQSEL_IRQ_SHIFT (0U) /*! IRQ - Interrupt Request */ #define INTM_MON_INTM_IRQSEL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_IRQSEL_IRQ_SHIFT)) & INTM_MON_INTM_IRQSEL_IRQ_MASK) /*! @} */ /* The count of INTM_MON_INTM_IRQSEL */ #define INTM_MON_INTM_IRQSEL_COUNT (4U) /*! @name MON_INTM_LATENCY - Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3 */ /*! @{ */ #define INTM_MON_INTM_LATENCY_LAT_MASK (0xFFFFFFU) #define INTM_MON_INTM_LATENCY_LAT_SHIFT (0U) /*! LAT - Latency */ #define INTM_MON_INTM_LATENCY_LAT(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_LATENCY_LAT_SHIFT)) & INTM_MON_INTM_LATENCY_LAT_MASK) /*! @} */ /* The count of INTM_MON_INTM_LATENCY */ #define INTM_MON_INTM_LATENCY_COUNT (4U) /*! @name MON_INTM_TIMER - Timer for Monitor 0..Timer for Monitor 3 */ /*! @{ */ #define INTM_MON_INTM_TIMER_TIMER_MASK (0xFFFFFFU) #define INTM_MON_INTM_TIMER_TIMER_SHIFT (0U) /*! TIMER - Timer */ #define INTM_MON_INTM_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_TIMER_TIMER_SHIFT)) & INTM_MON_INTM_TIMER_TIMER_MASK) /*! @} */ /* The count of INTM_MON_INTM_TIMER */ #define INTM_MON_INTM_TIMER_COUNT (4U) /*! @name MON_INTM_STATUS - Status for Monitor 0..Status for Monitor 3 */ /*! @{ */ #define INTM_MON_INTM_STATUS_STATUS_MASK (0x1U) #define INTM_MON_INTM_STATUS_STATUS_SHIFT (0U) /*! STATUS - Monitor status * 0b1..Exceeded * 0b0..Did not exceed */ #define INTM_MON_INTM_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_STATUS_STATUS_SHIFT)) & INTM_MON_INTM_STATUS_STATUS_MASK) /*! @} */ /* The count of INTM_MON_INTM_STATUS */ #define INTM_MON_INTM_STATUS_COUNT (4U) /*! * @} */ /* end of group INTM_Register_Masks */ /* INTM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral INTM0 base address */ #define INTM0_BASE (0x5005D000u) /** Peripheral INTM0 base address */ #define INTM0_BASE_NS (0x4005D000u) /** Peripheral INTM0 base pointer */ #define INTM0 ((INTM_Type *)INTM0_BASE) /** Peripheral INTM0 base pointer */ #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) /** Array initializer of INTM peripheral base addresses */ #define INTM_BASE_ADDRS { INTM0_BASE } /** Array initializer of INTM peripheral base pointers */ #define INTM_BASE_PTRS { INTM0 } /** Array initializer of INTM peripheral base addresses */ #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } /** Array initializer of INTM peripheral base pointers */ #define INTM_BASE_PTRS_NS { INTM0_NS } #else /** Peripheral INTM0 base address */ #define INTM0_BASE (0x4005D000u) /** Peripheral INTM0 base pointer */ #define INTM0 ((INTM_Type *)INTM0_BASE) /** Array initializer of INTM peripheral base addresses */ #define INTM_BASE_ADDRS { INTM0_BASE } /** Array initializer of INTM peripheral base pointers */ #define INTM_BASE_PTRS { INTM0 } #endif /*! * @} */ /* end of group INTM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ITRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer * @{ */ /** ITRC - Register Layout Typedef */ typedef struct { __IO uint32_t STATUS; /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */ __IO uint32_t STATUS1; /**< ITRC IN16 to IN47 Status, offset: 0x4 */ __IO uint32_t OUT_SEL[7][2]; /**< Trigger Source IN0 to IN15 selector, array offset: 0x8, array step: index*0x8, index2*0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t OUT_SEL_1[7][2]; /**< Trigger Source IN16 to IN31 selector, array offset: 0x48, array step: index*0x8, index2*0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t OUT_SEL_2[7][2]; /**< Trigger source IN32 to IN47 selector, array offset: 0x88, array step: index*0x8, index2*0x4 */ uint8_t RESERVED_2[48]; __O uint32_t SW_EVENT0; /**< Software event 0, offset: 0xF0 */ __O uint32_t SW_EVENT1; /**< Software event 1, offset: 0xF4 */ } ITRC_Type; /* ---------------------------------------------------------------------------- -- ITRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ITRC_Register_Masks ITRC Register Masks * @{ */ /*! @name STATUS - ITRC outputs and IN0 to IN15 Status */ /*! @{ */ #define ITRC_STATUS_IN0_STATUS_MASK (0x1U) #define ITRC_STATUS_IN0_STATUS_SHIFT (0U) /*! IN0_STATUS - GDET0 & 1 interrupt. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK) #define ITRC_STATUS_IN1_STATUS_MASK (0x2U) #define ITRC_STATUS_IN1_STATUS_SHIFT (1U) /*! IN1_STATUS - TDET tamper output. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK) #define ITRC_STATUS_IN2_STATUS_MASK (0x4U) #define ITRC_STATUS_IN2_STATUS_SHIFT (2U) /*! IN2_STATUS - Code Watchdog 0 interrupt. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN2_STATUS_SHIFT)) & ITRC_STATUS_IN2_STATUS_MASK) #define ITRC_STATUS_IN3_STATUS_MASK (0x8U) #define ITRC_STATUS_IN3_STATUS_SHIFT (3U) /*! IN3_STATUS - VBAT volt tamper output. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN3_STATUS_SHIFT)) & ITRC_STATUS_IN3_STATUS_MASK) #define ITRC_STATUS_IN4_STATUS_MASK (0x10U) #define ITRC_STATUS_IN4_STATUS_SHIFT (4U) /*! IN4_STATUS - SPC VDD_CORE_LVD detect. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK) #define ITRC_STATUS_IN5_STATUS_MASK (0x20U) #define ITRC_STATUS_IN5_STATUS_SHIFT (5U) /*! IN5_STATUS - Watch Dog timer event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK) #define ITRC_STATUS_IN6_STATUS_MASK (0x40U) #define ITRC_STATUS_IN6_STATUS_SHIFT (6U) /*! IN6_STATUS - Flash ECC mismatch event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK) #define ITRC_STATUS_IN7_STATUS_MASK (0x80U) #define ITRC_STATUS_IN7_STATUS_SHIFT (7U) /*! IN7_STATUS - AHB secure bus checkers detected illegal access. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK) #define ITRC_STATUS_IN8_STATUS_MASK (0x100U) #define ITRC_STATUS_IN8_STATUS_SHIFT (8U) /*! IN8_STATUS - ELS error event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN8_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK) #define ITRC_STATUS_IN9_STATUS_MASK (0x200U) #define ITRC_STATUS_IN9_STATUS_SHIFT (9U) /*! IN9_STATUS - SPC VDD_CORE glitch detect event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN9_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN9_STATUS_SHIFT)) & ITRC_STATUS_IN9_STATUS_MASK) #define ITRC_STATUS_IN10_STATUS_MASK (0x400U) #define ITRC_STATUS_IN10_STATUS_SHIFT (10U) /*! IN10_STATUS - PKC module detected an error event. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN10_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK) #define ITRC_STATUS_IN11_STATUS_MASK (0x800U) #define ITRC_STATUS_IN11_STATUS_SHIFT (11U) /*! IN11_STATUS - Code Watchdog 1 interrupt. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN11_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN11_STATUS_SHIFT)) & ITRC_STATUS_IN11_STATUS_MASK) #define ITRC_STATUS_IN112_STATUS_MASK (0x1000U) #define ITRC_STATUS_IN112_STATUS_SHIFT (12U) /*! IN112_STATUS - Watchdog 1 timer event interrupt. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN112_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN112_STATUS_SHIFT)) & ITRC_STATUS_IN112_STATUS_MASK) #define ITRC_STATUS_IN113_STATUS_MASK (0x2000U) #define ITRC_STATUS_IN113_STATUS_SHIFT (13U) /*! IN113_STATUS - FREQME out of range status output. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN113_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN113_STATUS_SHIFT)) & ITRC_STATUS_IN113_STATUS_MASK) #define ITRC_STATUS_IN14_STATUS_MASK (0x4000U) #define ITRC_STATUS_IN14_STATUS_SHIFT (14U) /*! IN14_STATUS - Software event 0 occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN14_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK) #define ITRC_STATUS_IN15_STATUS_MASK (0x8000U) #define ITRC_STATUS_IN15_STATUS_SHIFT (15U) /*! IN15_STATUS - Software event 1 occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_IN15_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK) #define ITRC_STATUS_OUT0_STATUS_MASK (0x10000U) #define ITRC_STATUS_OUT0_STATUS_SHIFT (16U) /*! OUT0_STATUS - ITRC triggered ITRC_IRQ output. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_OUT0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK) #define ITRC_STATUS_OUT1_STATUS_MASK (0x20000U) #define ITRC_STATUS_OUT1_STATUS_SHIFT (17U) /*! OUT1_STATUS - ITRC triggered ELS_RESET to clear ELS key store. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_OUT1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK) #define ITRC_STATUS_OUT2_STATUS_MASK (0x40000U) #define ITRC_STATUS_OUT2_STATUS_SHIFT (18U) /*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_OUT2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK) #define ITRC_STATUS_OUT3_STATUS_MASK (0x80000U) #define ITRC_STATUS_OUT3_STATUS_SHIFT (19U) /*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_OUT3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK) #define ITRC_STATUS_OUT4_STATUS_MASK (0x100000U) #define ITRC_STATUS_OUT4_STATUS_SHIFT (20U) /*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_OUT4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK) #define ITRC_STATUS_OUT5_STATUS_MASK (0x200000U) #define ITRC_STATUS_OUT5_STATUS_SHIFT (21U) /*! OUT5_STATUS - ITRC triggered TMPR_OUT0 internal signal connected to various on-chip multiplexers. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_OUT5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK) #define ITRC_STATUS_OUT6_STATUS_MASK (0x400000U) #define ITRC_STATUS_OUT6_STATUS_SHIFT (22U) /*! OUT6_STATUS - ITRC triggered TMPR_OUT1 internal signal connected to various on-chip multiplexers. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS_OUT6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT6_STATUS_SHIFT)) & ITRC_STATUS_OUT6_STATUS_MASK) /*! @} */ /*! @name STATUS1 - ITRC IN16 to IN47 Status */ /*! @{ */ #define ITRC_STATUS1_IN16_STATUS_MASK (0x1U) #define ITRC_STATUS1_IN16_STATUS_SHIFT (0U) /*! IN16_STATUS - SSPC VDD_SYS_LVD detect event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN16_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN16_STATUS_SHIFT)) & ITRC_STATUS1_IN16_STATUS_MASK) #define ITRC_STATUS1_IN17_STATUS_MASK (0x2U) #define ITRC_STATUS1_IN17_STATUS_SHIFT (1U) /*! IN17_STATUS - SPC VDD_IO_LVD detect event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN17_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN17_STATUS_SHIFT)) & ITRC_STATUS1_IN17_STATUS_MASK) #define ITRC_STATUS1_IN18_STATUS_MASK (0x4U) #define ITRC_STATUS1_IN18_STATUS_SHIFT (2U) /*! IN18_STATUS - Reserved * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN18_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN18_STATUS_SHIFT)) & ITRC_STATUS1_IN18_STATUS_MASK) #define ITRC_STATUS1_IN19_STATUS_MASK (0x8U) #define ITRC_STATUS1_IN19_STATUS_SHIFT (3U) /*! IN19_STATUS - Reserved * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN19_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN19_STATUS_SHIFT)) & ITRC_STATUS1_IN19_STATUS_MASK) #define ITRC_STATUS1_IN20_STATUS_MASK (0x10U) #define ITRC_STATUS1_IN20_STATUS_SHIFT (4U) /*! IN20_STATUS - VBAT clock tamper output event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN20_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN20_STATUS_SHIFT)) & ITRC_STATUS1_IN20_STATUS_MASK) #define ITRC_STATUS1_IN24_21_STATUS_MASK (0x1E0U) #define ITRC_STATUS1_IN24_21_STATUS_SHIFT (5U) /*! IN24_21_STATUS - INTM interrupt monitor error 3~0 event occurred. * 0b0000..Output not triggered. * 0b0001..Output has been triggered. */ #define ITRC_STATUS1_IN24_21_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN24_21_STATUS_SHIFT)) & ITRC_STATUS1_IN24_21_STATUS_MASK) #define ITRC_STATUS1_IN32_25_STATUS_MASK (0x1FE00U) #define ITRC_STATUS1_IN32_25_STATUS_SHIFT (9U) /*! IN32_25_STATUS - MSF SOCTRIM 7~0 ECC error event occurred. * 0b00000000..Output not triggered. * 0b00000001..Output has been triggered. */ #define ITRC_STATUS1_IN32_25_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN32_25_STATUS_SHIFT)) & ITRC_STATUS1_IN32_25_STATUS_MASK) #define ITRC_STATUS1_IN33_STATUS_MASK (0x20000U) #define ITRC_STATUS1_IN33_STATUS_SHIFT (17U) /*! IN33_STATUS - GDET0/1 SFR error event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN33_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN33_STATUS_SHIFT)) & ITRC_STATUS1_IN33_STATUS_MASK) #define ITRC_STATUS1_IN34_STATUS_MASK (0x40000U) #define ITRC_STATUS1_IN34_STATUS_SHIFT (18U) /*! IN34_STATUS - SPC VDD_CORE high voltage detect event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN34_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN34_STATUS_SHIFT)) & ITRC_STATUS1_IN34_STATUS_MASK) #define ITRC_STATUS1_IN35_STATUS_MASK (0x80000U) #define ITRC_STATUS1_IN35_STATUS_SHIFT (19U) /*! IN35_STATUS - SPC VDD_SYS_HVD high voltage detect event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN35_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN35_STATUS_SHIFT)) & ITRC_STATUS1_IN35_STATUS_MASK) #define ITRC_STATUS1_IN36_STATUS_MASK (0x100000U) #define ITRC_STATUS1_IN36_STATUS_SHIFT (20U) /*! IN36_STATUS - SPC VDD_IO high voltage detect event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN36_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN36_STATUS_SHIFT)) & ITRC_STATUS1_IN36_STATUS_MASK) #define ITRC_STATUS1_IN37_STATUS_MASK (0x200000U) #define ITRC_STATUS1_IN37_STATUS_SHIFT (21U) /*! IN37_STATUS - FLEXSPI GCM error event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN37_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN37_STATUS_SHIFT)) & ITRC_STATUS1_IN37_STATUS_MASK) #define ITRC_STATUS1_IN46_STATUS_MASK (0x40000000U) #define ITRC_STATUS1_IN46_STATUS_SHIFT (30U) /*! IN46_STATUS - SM3 SGI error event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN46_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN46_STATUS_SHIFT)) & ITRC_STATUS1_IN46_STATUS_MASK) #define ITRC_STATUS1_IN47_STATUS_MASK (0x80000000U) #define ITRC_STATUS1_IN47_STATUS_SHIFT (31U) /*! IN47_STATUS - TRNG HW error event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ #define ITRC_STATUS1_IN47_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN47_STATUS_SHIFT)) & ITRC_STATUS1_IN47_STATUS_MASK) /*! @} */ /*! @name OUTX_SEL_OUTX_SELY_OUT_SEL - Trigger Source IN0 to IN15 selector */ /*! @{ */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK (0x3U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT (0U) /*! IN0_SELn - Selects digital glitch detector as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK (0xCU) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT (2U) /*! IN1_SELn - Selects TDET event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK (0x30U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT (4U) /*! IN2_SELn - Selects Code Watchdog 0 event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK (0xC0U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT (6U) /*! IN3_SELn - Selects VBAT voltage tamper event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK (0x300U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT (8U) /*! IN4_SELn - Selects low-voltage event on VDD_CORE rail as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK (0xC00U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT (10U) /*! IN5_SELn - Selects Watchdog 0 timer event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK (0x3000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT (12U) /*! IN6_SELn - Selects Flash ECC mismatch event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK (0xC000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT (14U) /*! IN7_SELn - Selects AHB secure bus or MBC bus illegal access event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK (0x30000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT (16U) /*! IN8_SELn - Selects ELS error event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK (0xC0000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT (18U) /*! IN9_SELn - Selects SPC VDD_CORE glitch detector as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK (0x300000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT (20U) /*! IN10_SELn - Selects PKC error event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK (0xC00000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT (22U) /*! IN11_SELn - Selects Code Watchdog 1 event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK (0x3000000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT (24U) /*! IN12_SELn - Selects Watchdog 1 timer event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK (0xC000000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT (26U) /*! IN13_SELn - Selects FREQME out of range status output as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK (0x30000000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT (28U) /*! IN14_SELn - Selects software event 0 as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK (0xC0000000U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT (30U) /*! IN15_SELn - Selects software event 1 as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK) /*! @} */ /* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT (7U) /* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT2 (2U) /*! @name OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 - Trigger Source IN16 to IN31 selector */ /*! @{ */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK (0x3U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT (0U) /*! IN16_SELn - Selects SPC VDD_SYS_LVD detect as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK (0xCU) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT (2U) /*! IN17_SELn - Selects SPC VDD_IO_LVD detect as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK (0x30U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT (4U) /*! IN18_SELn - Reserved. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK (0xC0U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT (6U) /*! IN19_SELn - Selects VBAT temperature tamper output event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK (0x300U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT (8U) /*! IN20_SELn - Selects VBAT clock tamper output event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK (0xC00U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT (10U) /*! IN21_SELn - Selects INTM interrupt monitor error 0 event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK (0x3000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT (12U) /*! IN22_SELn - Selects INTM interrupt monitor error 1 event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK (0xC000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT (14U) /*! IN23_SELn - Selects INTM interrupt monitor error 2 event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK (0x30000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT (16U) /*! IN24_SELn - Selects INTM interrupt monitor error 3 event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK (0xC0000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT (18U) /*! IN25_SELn - Selects MSF SOCTRIM 0 ECC error event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK (0x300000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT (20U) /*! IN26_SELn - Selects MSF SOCTRIM 1 ECC error event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK (0xC00000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT (22U) /*! IN27_SELn - Selects MSF SOCTRIM 2 ECC error event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK (0x3000000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT (24U) /*! IN28_SELn - Selects MSF SOCTRIM 3 ECC error event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK (0xC000000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT (26U) /*! IN29_SELn - Selects MSF SOCTRIM 4 ECC error event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK (0x30000000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT (28U) /*! IN30_SELn - Selects MSF SOCTRIM 5 ECC error event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK (0xC0000000U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT (30U) /*! IN31_SELn - Selects MSF SOCTRIM 6 ECC error event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK) /*! @} */ /* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT (7U) /* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT2 (2U) /*! @name OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 - Trigger source IN32 to IN47 selector */ /*! @{ */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK (0x3U) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT (0U) /*! IN32_SELn - Selects MSF SOCTRIM 7 ECC error event as a trigger source. */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK (0xCU) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT (2U) /*! IN33_SELn - Selects GDET0 & 1 SFR error detect as a trigger source. */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK (0x30U) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT (4U) /*! IN34_SELn - Selects SPC VDD_CORE_HVD as a trigger source. */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK (0xC0U) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT (6U) /*! IN35_SELn - Selects VDD_SYS_HVD as a trigger source. */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK (0x300U) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT (8U) /*! IN36_SELn - Selects VDD_IO_HVD as a trigger source. */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK (0xC00U) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT (10U) /*! IN37_SELn - Selects FLEXSPI GCM error as a trigger source. */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK (0x30000000U) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT (28U) /*! IN46_SELn - Selects SM3 SGI error as a trigger source. */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK (0xC0000000U) #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT (30U) /*! IN47_SELn - Selects TRNG HW Error as a trigger source. */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK) /*! @} */ /* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT (7U) /* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */ #define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT2 (2U) /*! @name SW_EVENT0 - Software event 0 */ /*! @{ */ #define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK (0xFFFFFFFFU) #define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT (0U) /*! TRIGGER_SW_EVENT_0 - Trigger software event 0. */ #define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK) /*! @} */ /*! @name SW_EVENT1 - Software event 1 */ /*! @{ */ #define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK (0xFFFFFFFFU) #define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT (0U) /*! TRIGGER_SW_EVENT_1 - Trigger software event 1. */ #define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK) /*! @} */ /*! * @} */ /* end of group ITRC_Register_Masks */ /* ITRC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral ITRC0 base address */ #define ITRC0_BASE (0x50026000u) /** Peripheral ITRC0 base address */ #define ITRC0_BASE_NS (0x40026000u) /** Peripheral ITRC0 base pointer */ #define ITRC0 ((ITRC_Type *)ITRC0_BASE) /** Peripheral ITRC0 base pointer */ #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) /** Array initializer of ITRC peripheral base addresses */ #define ITRC_BASE_ADDRS { ITRC0_BASE } /** Array initializer of ITRC peripheral base pointers */ #define ITRC_BASE_PTRS { ITRC0 } /** Array initializer of ITRC peripheral base addresses */ #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } /** Array initializer of ITRC peripheral base pointers */ #define ITRC_BASE_PTRS_NS { ITRC0_NS } #else /** Peripheral ITRC0 base address */ #define ITRC0_BASE (0x40026000u) /** Peripheral ITRC0 base pointer */ #define ITRC0 ((ITRC_Type *)ITRC0_BASE) /** Array initializer of ITRC peripheral base addresses */ #define ITRC_BASE_ADDRS { ITRC0_BASE } /** Array initializer of ITRC peripheral base pointers */ #define ITRC_BASE_PTRS { ITRC0 } #endif /*! * @} */ /* end of group ITRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer * @{ */ /** LPCMP - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ uint8_t RESERVED_0[4]; __IO uint32_t DCR; /**< DAC Control, offset: 0x18 */ __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ __IO uint32_t CSR; /**< Comparator Status, offset: 0x20 */ __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ __IO uint32_t RRCSR; /**< Round Robin Control and Status, offset: 0x2C */ __IO uint32_t RRSR; /**< Round Robin Status, offset: 0x30 */ uint8_t RESERVED_1[4]; __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ } LPCMP_Type; /* ---------------------------------------------------------------------------- -- LPCMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCMP_Register_Masks LPCMP Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define LPCMP_VERID_FEATURE_MASK (0xFFFFU) #define LPCMP_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000001..Round robin feature */ #define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) #define LPCMP_VERID_MINOR_MASK (0xFF0000U) #define LPCMP_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) #define LPCMP_VERID_MAJOR_MASK (0xFF000000U) #define LPCMP_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPCMP_PARAM_DAC_RES_MASK (0xFU) #define LPCMP_PARAM_DAC_RES_SHIFT (0U) /*! DAC_RES - DAC Resolution * 0b0000..4-bit DAC * 0b0001..6-bit DAC * 0b0010..8-bit DAC * 0b0011..10-bit DAC * 0b0100..12-bit DAC * 0b0101..14-bit DAC * 0b0110..16-bit DAC */ #define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) /*! @} */ /*! @name CCR0 - Comparator Control Register 0 */ /*! @{ */ #define LPCMP_CCR0_CMP_EN_MASK (0x1U) #define LPCMP_CCR0_CMP_EN_SHIFT (0U) /*! CMP_EN - Comparator Enable * 0b0..Disable (The analog logic remains off and consumes no power.) * 0b1..Enable */ #define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) #define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) #define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) /*! CMP_STOP_EN - Comparator Deep sleep Mode Enable * 0b0..Disables the analog comparator regardless of CMP_EN. * 0b1..Allows CMP_EN to enable the analog comparator. */ #define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) /*! @} */ /*! @name CCR1 - Comparator Control Register 1 */ /*! @{ */ #define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) #define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) /*! WINDOW_EN - Windowing Enable * 0b0..Disable * 0b1..Enable */ #define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) #define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) #define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) /*! SAMPLE_EN - Sampling Enable * 0b0..Disable * 0b1..Enable */ #define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) #define LPCMP_CCR1_DMA_EN_MASK (0x4U) #define LPCMP_CCR1_DMA_EN_SHIFT (2U) /*! DMA_EN - DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) #define LPCMP_CCR1_COUT_INV_MASK (0x8U) #define LPCMP_CCR1_COUT_INV_SHIFT (3U) /*! COUT_INV - Comparator Invert * 0b0..Do not invert * 0b1..Invert */ #define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) #define LPCMP_CCR1_COUT_SEL_MASK (0x10U) #define LPCMP_CCR1_COUT_SEL_SHIFT (4U) /*! COUT_SEL - Comparator Output Select * 0b0..Use COUT (filtered) * 0b1..Use COUTA (unfiltered) */ #define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) #define LPCMP_CCR1_COUT_PEN_MASK (0x20U) #define LPCMP_CCR1_COUT_PEN_SHIFT (5U) /*! COUT_PEN - Comparator Output Pin Enable * 0b0..Not available * 0b1..Available */ #define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) #define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U) #define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U) /*! COUTA_OWEN - COUTA_OW Enable * 0b0..COUTA holds the last sampled value. * 0b1..Enables the COUTA signal value to be defined by COUTA_OW. */ #define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK) #define LPCMP_CCR1_COUTA_OW_MASK (0x80U) #define LPCMP_CCR1_COUTA_OW_SHIFT (7U) /*! COUTA_OW - COUTA Output Level for Closed Window * 0b0..COUTA is 0 * 0b1..COUTA is 1 */ #define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK) #define LPCMP_CCR1_WINDOW_INV_MASK (0x100U) #define LPCMP_CCR1_WINDOW_INV_SHIFT (8U) /*! WINDOW_INV - WINDOW/SAMPLE Signal Invert * 0b0..Do not invert * 0b1..Invert */ #define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK) #define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U) #define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U) /*! WINDOW_CLS - COUT Event Window Close * 0b0..COUT event cannot close the window * 0b1..COUT event can close the window */ #define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK) #define LPCMP_CCR1_EVT_SEL_MASK (0xC00U) #define LPCMP_CCR1_EVT_SEL_SHIFT (10U) /*! EVT_SEL - COUT Event Select * 0b00..Rising edge * 0b01..Falling edge * 0b1x..Both edges */ #define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK) #define LPCMP_CCR1_FUNC_CLK_SEL_MASK (0x3000U) #define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT (12U) /*! FUNC_CLK_SEL - Functional Clock Source Select * 0b00..Select functional clock source 0 * 0b01..Select functional clock source 1 * 0b10..Select functional clock source 2 * 0b11..Select functional clock source 3 */ #define LPCMP_CCR1_FUNC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK) #define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) #define LPCMP_CCR1_FILT_CNT_SHIFT (16U) /*! FILT_CNT - Filter Sample Count * 0b000..Filter is bypassed: COUT = COUTA * 0b001..1 consecutive sample (Comparator output is simply sampled.) * 0b010..2 consecutive samples * 0b011..3 consecutive samples * 0b100..4 consecutive samples * 0b101..5 consecutive samples * 0b110..6 consecutive samples * 0b111..7 consecutive samples */ #define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) #define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) #define LPCMP_CCR1_FILT_PER_SHIFT (24U) /*! FILT_PER - Filter Sample Period */ #define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) /*! @} */ /*! @name CCR2 - Comparator Control Register 2 */ /*! @{ */ #define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) #define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) /*! CMP_HPMD - CMP High Power Mode Select * 0b0..Low power (speed) comparison mode * 0b1..High power (speed) comparison mode */ #define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) #define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) #define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) /*! CMP_NPMD - CMP Nano Power Mode Select * 0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator. * 0b1..Enables CMP Nano power mode. */ #define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) #define LPCMP_CCR2_HYSTCTR_MASK (0x30U) #define LPCMP_CCR2_HYSTCTR_SHIFT (4U) /*! HYSTCTR - Comparator Hysteresis Control * 0b00..Level 0: Analog comparator hysteresis 0 mV. * 0b01..Level 1: Analog comparator hysteresis 10 mV. * 0b10..Level 2: Analog comparator hysteresis 20 mV. * 0b11..Level 3: Analog comparator hysteresis 30 mV. */ #define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) #define LPCMP_CCR2_PSEL_MASK (0x70000U) #define LPCMP_CCR2_PSEL_SHIFT (16U) /*! PSEL - Plus Input MUX Select * 0b000..Input 0p * 0b001..Input 1p * 0b010..Input 2p * 0b011..Input 3p * 0b100..Input 4p * 0b101..Input 5p * 0b110..Reserved * 0b111..Internal DAC output */ #define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) #define LPCMP_CCR2_MSEL_MASK (0x700000U) #define LPCMP_CCR2_MSEL_SHIFT (20U) /*! MSEL - Minus Input MUX Select * 0b000..Input 0m * 0b001..Input 1m * 0b010..Input 2m * 0b011..Input 3m * 0b100..Input 4m * 0b101..Input 5m * 0b110..Reserved * 0b111..Internal DAC output */ #define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) /*! @} */ /*! @name DCR - DAC Control */ /*! @{ */ #define LPCMP_DCR_DAC_EN_MASK (0x1U) #define LPCMP_DCR_DAC_EN_SHIFT (0U) /*! DAC_EN - DAC Enable * 0b0..Disable * 0b1..Enable */ #define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) #define LPCMP_DCR_DAC_HPMD_MASK (0x2U) #define LPCMP_DCR_DAC_HPMD_SHIFT (1U) /*! DAC_HPMD - DAC High Power Mode * 0b0..Disable * 0b1..Enable */ #define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) #define LPCMP_DCR_VRSEL_MASK (0x100U) #define LPCMP_DCR_VRSEL_SHIFT (8U) /*! VRSEL - DAC Reference High Voltage Source Select * 0b0..VREFH0 * 0b1..VREFH1 */ #define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) #define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U) #define LPCMP_DCR_DAC_DATA_SHIFT (16U) /*! DAC_DATA - DAC Output Voltage Select */ #define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) /*! @} */ /*! @name IER - Interrupt Enable */ /*! @{ */ #define LPCMP_IER_CFR_IE_MASK (0x1U) #define LPCMP_IER_CFR_IE_SHIFT (0U) /*! CFR_IE - Comparator Flag Rising Interrupt Enable * 0b0..Disables the comparator flag rising interrupt. * 0b1..Enables the comparator flag rising interrupt when CFR is set. */ #define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) #define LPCMP_IER_CFF_IE_MASK (0x2U) #define LPCMP_IER_CFF_IE_SHIFT (1U) /*! CFF_IE - Comparator Flag Falling Interrupt Enable * 0b0..Disables the comparator flag falling interrupt. * 0b1..Enables the comparator flag falling interrupt when CFF is set. */ #define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) #define LPCMP_IER_RRF_IE_MASK (0x4U) #define LPCMP_IER_RRF_IE_SHIFT (2U) /*! RRF_IE - Round-Robin Flag Interrupt Enable * 0b0..Disables the round-robin flag interrupt. * 0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel. */ #define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK) /*! @} */ /*! @name CSR - Comparator Status */ /*! @{ */ #define LPCMP_CSR_CFR_MASK (0x1U) #define LPCMP_CSR_CFR_SHIFT (0U) /*! CFR - Analog Comparator Flag Rising * 0b0..Not detected * 0b1..Detected */ #define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) #define LPCMP_CSR_CFF_MASK (0x2U) #define LPCMP_CSR_CFF_SHIFT (1U) /*! CFF - Analog Comparator Flag Falling * 0b0..Not detected * 0b1..Detected */ #define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) #define LPCMP_CSR_RRF_MASK (0x4U) #define LPCMP_CSR_RRF_SHIFT (2U) /*! RRF - Round-Robin Flag * 0b0..Not detected * 0b1..Detected */ #define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK) #define LPCMP_CSR_COUT_MASK (0x100U) #define LPCMP_CSR_COUT_SHIFT (8U) /*! COUT - Analog Comparator Output */ #define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) /*! @} */ /*! @name RRCR0 - Round Robin Control Register 0 */ /*! @{ */ #define LPCMP_RRCR0_RR_EN_MASK (0x1U) #define LPCMP_RRCR0_RR_EN_SHIFT (0U) /*! RR_EN - Round-Robin Enable * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) #define LPCMP_RRCR0_RR_TRG_SEL_MASK (0x2U) #define LPCMP_RRCR0_RR_TRG_SEL_SHIFT (1U) /*! RR_TRG_SEL - Round-Robin Trigger Select * 0b0..External trigger * 0b1..Internal trigger */ #define LPCMP_RRCR0_RR_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK) #define LPCMP_RRCR0_RR_EXTTRG_SEL_MASK (0x3CU) #define LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT (2U) /*! RR_EXTTRG_SEL - External Trigger Source Select * 0b0000..Select external trigger source 0 * 0b0001..Select external trigger source 1 * 0b0010..Select external trigger source 2 * 0b0011..Select external trigger source 3 * 0b0100..Select external trigger source 4 * 0b0101..Select external trigger source 5 * 0b0110..Select external trigger source 6 * 0b0111..Select external trigger source 7 * 0b1000..Select external trigger source 8 * 0b1001..Select external trigger source 9 * 0b1010..Select external trigger source 10 * 0b1011..Select external trigger source 11 * 0b1100..Select external trigger source 12 * 0b1101..Select external trigger source 13 * 0b1110..Select external trigger source 14 * 0b1111..Select external trigger source 15 */ #define LPCMP_RRCR0_RR_EXTTRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_EXTTRG_SEL_MASK) #define LPCMP_RRCR0_RR_NSAM_MASK (0x300U) #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) /*! RR_NSAM - Number of Sample Clocks * 0b00..0 clock * 0b01..1 clock * 0b10..2 clocks * 0b11..3 clocks */ #define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK) #define LPCMP_RRCR0_RR_CLK_SEL_MASK (0x3000U) #define LPCMP_RRCR0_RR_CLK_SEL_SHIFT (12U) /*! RR_CLK_SEL - Round Robin Clock Source Select * 0b00..Select Round Robin clock Source 0 * 0b01..Select Round Robin clock Source 1 * 0b10..Select Round Robin clock Source 2 * 0b11..Select Round Robin clock Source 3 */ #define LPCMP_RRCR0_RR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK) #define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) #define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U) /*! RR_INITMOD - Initialization Delay Modulus * 0b000000..63 cycles (same as 111111b) * 0b000001-0b111111..1 to 63 cycles */ #define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK) #define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK (0xF000000U) #define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT (24U) /*! RR_SAMPLE_CNT - Number of Sample for One Channel * 0b0000..1 samples * 0b0001..2 samples * 0b0010..3 samples * 0b0011..4 samples * 0b0100..5 samples * 0b0101..6 samples * 0b0110..7 samples * 0b0111..8 samples * 0b1000..9 samples * 0b1001..10 samples * 0b1010..11 samples * 0b1011..12 samples * 0b1100..13 samples * 0b1101..14 samples * 0b1110..15 samples * 0b1111..16 samples */ #define LPCMP_RRCR0_RR_SAMPLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK) #define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK (0xF0000000U) #define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT (28U) /*! RR_SAMPLE_THRESHOLD - Sample Time Threshold * 0b0000..At least 1 sampled "1", the final result is "1" * 0b0001..At least 2 sampled "1", the final result is "1" * 0b0010..At least 3 sampled "1", the final result is "1" * 0b0011..At least 4 sampled "1", the final result is "1" * 0b0100..At least 5 sampled "1", the final result is "1" * 0b0101..At least 6 sampled "1", the final result is "1" * 0b0110..At least 7 sampled "1", the final result is "1" * 0b0111..At least 8 sampled "1", the final result is "1" * 0b1000..At least 9 sampled "1", the final result is "1" * 0b1001..At least 10 sampled "1", the final result is "1" * 0b1010..At least 11 sampled "1", the final result is "1" * 0b1011..At least 12 sampled "1", the final result is "1" * 0b1100..At least 13 sampled "1", the final result is "1" * 0b1101..At least 14 sampled "1", the final result is "1" * 0b1110..At least 15 sampled "1", the final result is "1" * 0b1111..At least 16 sampled "1", the final result is "1" */ #define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK) /*! @} */ /*! @name RRCR1 - Round Robin Control Register 1 */ /*! @{ */ #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) #define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) /*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) #define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) #define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) /*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) #define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) #define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) /*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) #define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) #define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) /*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) #define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) #define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) /*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) #define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) #define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) /*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) #define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) #define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) /*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) #define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) #define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) /*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode * 0b1..Enable * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) #define LPCMP_RRCR1_FIXP_MASK (0x10000U) #define LPCMP_RRCR1_FIXP_SHIFT (16U) /*! FIXP - Fixed Port * 0b0..Fix the plus port. Sweep only the inputs to the minus port. * 0b1..Fix the minus port. Sweep only the inputs to the plus port. */ #define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK) #define LPCMP_RRCR1_FIXCH_MASK (0x700000U) #define LPCMP_RRCR1_FIXCH_SHIFT (20U) /*! FIXCH - Fixed Channel Select * 0b000..Channel 0 * 0b001..Channel 1 * 0b010..Channel 2 * 0b011..Channel 3 * 0b100..Channel 4 * 0b101..Channel 5 * 0b110..Channel 6 * 0b111..Channel 7 */ #define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK) /*! @} */ /*! @name RRCSR - Round Robin Control and Status */ /*! @{ */ #define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U) #define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U) /*! RR_CH0OUT - Comparison Result for Channel 0 */ #define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK) #define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U) #define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U) /*! RR_CH1OUT - Comparison Result for Channel 1 */ #define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK) #define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U) #define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U) /*! RR_CH2OUT - Comparison Result for Channel 2 */ #define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK) #define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U) #define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U) /*! RR_CH3OUT - Comparison Result for Channel 3 */ #define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK) #define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U) #define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U) /*! RR_CH4OUT - Comparison Result for Channel 4 */ #define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK) #define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U) #define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U) /*! RR_CH5OUT - Comparison Result for Channel 5 */ #define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK) #define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U) #define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U) /*! RR_CH6OUT - Comparison Result for Channel 6 */ #define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK) #define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U) #define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U) /*! RR_CH7OUT - Comparison Result for Channel 7 */ #define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK) /*! @} */ /*! @name RRSR - Round Robin Status */ /*! @{ */ #define LPCMP_RRSR_RR_CH0F_MASK (0x1U) #define LPCMP_RRSR_RR_CH0F_SHIFT (0U) /*! RR_CH0F - Channel 0 Input Changed Flag * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) #define LPCMP_RRSR_RR_CH1F_MASK (0x2U) #define LPCMP_RRSR_RR_CH1F_SHIFT (1U) /*! RR_CH1F - Channel 1 Input Changed Flag * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) #define LPCMP_RRSR_RR_CH2F_MASK (0x4U) #define LPCMP_RRSR_RR_CH2F_SHIFT (2U) /*! RR_CH2F - Channel 2 Input Changed Flag * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) #define LPCMP_RRSR_RR_CH3F_MASK (0x8U) #define LPCMP_RRSR_RR_CH3F_SHIFT (3U) /*! RR_CH3F - Channel 3 Input Changed Flag * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) #define LPCMP_RRSR_RR_CH4F_MASK (0x10U) #define LPCMP_RRSR_RR_CH4F_SHIFT (4U) /*! RR_CH4F - Channel 4 Input Changed Flag * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) #define LPCMP_RRSR_RR_CH5F_MASK (0x20U) #define LPCMP_RRSR_RR_CH5F_SHIFT (5U) /*! RR_CH5F - Channel 5 Input Changed Flag * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) #define LPCMP_RRSR_RR_CH6F_MASK (0x40U) #define LPCMP_RRSR_RR_CH6F_SHIFT (6U) /*! RR_CH6F - Channel 6 Input Changed Flag * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) #define LPCMP_RRSR_RR_CH7F_MASK (0x80U) #define LPCMP_RRSR_RR_CH7F_SHIFT (7U) /*! RR_CH7F - Channel 7 Input Changed Flag * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) /*! @} */ /*! @name RRCR2 - Round Robin Control Register 2 */ /*! @{ */ #define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) #define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) /*! RR_TIMER_RELOAD - Number of Sample Clocks */ #define LPCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK) #define LPCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) #define LPCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) /*! RR_TIMER_EN - Round-Robin Internal Timer Enable * 0b0..Disables * 0b1..Enables */ #define LPCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK) /*! @} */ /*! * @} */ /* end of group LPCMP_Register_Masks */ /* LPCMP - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CMP0 base address */ #define CMP0_BASE (0x50051000u) /** Peripheral CMP0 base address */ #define CMP0_BASE_NS (0x40051000u) /** Peripheral CMP0 base pointer */ #define CMP0 ((LPCMP_Type *)CMP0_BASE) /** Peripheral CMP0 base pointer */ #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) /** Peripheral CMP1 base address */ #define CMP1_BASE (0x50052000u) /** Peripheral CMP1 base address */ #define CMP1_BASE_NS (0x40052000u) /** Peripheral CMP1 base pointer */ #define CMP1 ((LPCMP_Type *)CMP1_BASE) /** Peripheral CMP1 base pointer */ #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) /** Peripheral CMP2 base address */ #define CMP2_BASE (0x50053000u) /** Peripheral CMP2 base address */ #define CMP2_BASE_NS (0x40053000u) /** Peripheral CMP2 base pointer */ #define CMP2 ((LPCMP_Type *)CMP2_BASE) /** Peripheral CMP2 base pointer */ #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) /** Array initializer of LPCMP peripheral base addresses */ #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } /** Array initializer of LPCMP peripheral base pointers */ #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } /** Array initializer of LPCMP peripheral base addresses */ #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } /** Array initializer of LPCMP peripheral base pointers */ #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } #else /** Peripheral CMP0 base address */ #define CMP0_BASE (0x40051000u) /** Peripheral CMP0 base pointer */ #define CMP0 ((LPCMP_Type *)CMP0_BASE) /** Peripheral CMP1 base address */ #define CMP1_BASE (0x40052000u) /** Peripheral CMP1 base pointer */ #define CMP1 ((LPCMP_Type *)CMP1_BASE) /** Peripheral CMP2 base address */ #define CMP2_BASE (0x40053000u) /** Peripheral CMP2 base pointer */ #define CMP2 ((LPCMP_Type *)CMP2_BASE) /** Array initializer of LPCMP peripheral base addresses */ #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } /** Array initializer of LPCMP peripheral base pointers */ #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } #endif /** Interrupt vectors for the LPCMP peripheral type */ #define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } /*! * @} */ /* end of group LPCMP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPDAC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer * @{ */ /** LPDAC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version Identifier, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __O uint32_t DATA; /**< Data, offset: 0x8 */ __IO uint32_t GCR; /**< Global Control, offset: 0xC */ __IO uint32_t FCR; /**< DAC FIFO Control, offset: 0x10 */ __I uint32_t FPR; /**< DAC FIFO Pointer, offset: 0x14 */ __IO uint32_t FSR; /**< FIFO Status, offset: 0x18 */ __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ __IO uint32_t DER; /**< DMA Enable, offset: 0x20 */ __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ __O uint32_t TCR; /**< Trigger Control, offset: 0x28 */ __IO uint32_t PCR; /**< Periodic Trigger Control, offset: 0x2C */ } LPDAC_Type; /* ---------------------------------------------------------------------------- -- LPDAC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPDAC_Register_Masks LPDAC Register Masks * @{ */ /*! @name VERID - Version Identifier */ /*! @{ */ #define LPDAC_VERID_FEATURE_MASK (0xFFFFU) #define LPDAC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number */ #define LPDAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK) #define LPDAC_VERID_MINOR_MASK (0xFF0000U) #define LPDAC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPDAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK) #define LPDAC_VERID_MAJOR_MASK (0xFF000000U) #define LPDAC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPDAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPDAC_PARAM_FIFOSZ_MASK (0x7U) #define LPDAC_PARAM_FIFOSZ_SHIFT (0U) /*! FIFOSZ - FIFO Size * 0b000..Reserved * 0b001..FIFO depth is 4 * 0b010..FIFO depth is 8 * 0b011..FIFO depth is 16 * 0b100..FIFO depth is 32 * 0b101..FIFO depth is 64 * 0b110..FIFO depth is 128 * 0b111..FIFO depth is 256 */ #define LPDAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK) /*! @} */ /*! @name DATA - Data */ /*! @{ */ #define LPDAC_DATA_DATA_MASK (0xFFFU) #define LPDAC_DATA_DATA_SHIFT (0U) /*! DATA - FIFO Entry or Buffer Entry */ #define LPDAC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK) /*! @} */ /*! @name GCR - Global Control */ /*! @{ */ #define LPDAC_GCR_DACEN_MASK (0x1U) #define LPDAC_GCR_DACEN_SHIFT (0U) /*! DACEN - DAC Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_GCR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK) #define LPDAC_GCR_DACRFS_MASK (0x6U) #define LPDAC_GCR_DACRFS_SHIFT (1U) /*! DACRFS - DAC Reference Select * 0b00..Selects VREFH0 as the reference voltage. * 0b01..Selects VREFH1 as the reference voltage. * 0b10..Selects VREFH2 as the reference voltage. * 0b11..Reserved. */ #define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) #define LPDAC_GCR_FIFOEN_MASK (0x8U) #define LPDAC_GCR_FIFOEN_SHIFT (3U) /*! FIFOEN - FIFO Enable * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion. * 0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion. */ #define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) #define LPDAC_GCR_SWMD_MASK (0x10U) #define LPDAC_GCR_SWMD_SHIFT (4U) /*! SWMD - Swing Back Mode * 0b0..Disables * 0b1..Enables */ #define LPDAC_GCR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK) #define LPDAC_GCR_TRGSEL_MASK (0x20U) #define LPDAC_GCR_TRGSEL_SHIFT (5U) /*! TRGSEL - DAC Trigger Select * 0b0..Hardware trigger * 0b1..Software trigger */ #define LPDAC_GCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK) #define LPDAC_GCR_PTGEN_MASK (0x40U) #define LPDAC_GCR_PTGEN_SHIFT (6U) /*! PTGEN - DAC Periodic Trigger Mode Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_GCR_PTGEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_PTGEN_SHIFT)) & LPDAC_GCR_PTGEN_MASK) #define LPDAC_GCR_LATCH_CYC_MASK (0xF00U) #define LPDAC_GCR_LATCH_CYC_SHIFT (8U) /*! LATCH_CYC - RCLK Cycles Before Data Latch */ #define LPDAC_GCR_LATCH_CYC(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LATCH_CYC_SHIFT)) & LPDAC_GCR_LATCH_CYC_MASK) #define LPDAC_GCR_BUF_EN_MASK (0x20000U) #define LPDAC_GCR_BUF_EN_SHIFT (17U) /*! BUF_EN - Buffer Enable * 0b0..Not used * 0b1..Used */ #define LPDAC_GCR_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_EN_SHIFT)) & LPDAC_GCR_BUF_EN_MASK) #define LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK (0x100000U) #define LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT (20U) /*! IREF_PTAT_EXT_SEL - External On-Chip PTAT Current Reference Select * 0b0..Not selected * 0b1..Selected */ #define LPDAC_GCR_IREF_PTAT_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK) #define LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK (0x200000U) #define LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT (21U) /*! IREF_ZTC_EXT_SEL - External On-Chip ZTC Current Reference Select * 0b0..Not selected * 0b1..Selected */ #define LPDAC_GCR_IREF_ZTC_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK) #define LPDAC_GCR_BUF_SPD_CTRL_MASK (0x800000U) #define LPDAC_GCR_BUF_SPD_CTRL_SHIFT (23U) /*! BUF_SPD_CTRL - OPAMP as Buffer, Speed Control Signal * 0b0..Lower Low-Power mode * 0b1..Low-Power mode */ #define LPDAC_GCR_BUF_SPD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_SPD_CTRL_SHIFT)) & LPDAC_GCR_BUF_SPD_CTRL_MASK) /*! @} */ /*! @name FCR - DAC FIFO Control */ /*! @{ */ #define LPDAC_FCR_WML_MASK (0xFU) #define LPDAC_FCR_WML_SHIFT (0U) /*! WML - Watermark Level */ #define LPDAC_FCR_WML(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK) /*! @} */ /*! @name FPR - DAC FIFO Pointer */ /*! @{ */ #define LPDAC_FPR_FIFO_RPT_MASK (0xFU) #define LPDAC_FPR_FIFO_RPT_SHIFT (0U) /*! FIFO_RPT - FIFO Read Pointer */ #define LPDAC_FPR_FIFO_RPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK) #define LPDAC_FPR_FIFO_WPT_MASK (0xF0000U) #define LPDAC_FPR_FIFO_WPT_SHIFT (16U) /*! FIFO_WPT - FIFO Write Pointer */ #define LPDAC_FPR_FIFO_WPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK) /*! @} */ /*! @name FSR - FIFO Status */ /*! @{ */ #define LPDAC_FSR_FULL_MASK (0x1U) #define LPDAC_FSR_FULL_SHIFT (0U) /*! FULL - FIFO Full Flag * 0b0..Not full * 0b1..Full */ #define LPDAC_FSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK) #define LPDAC_FSR_EMPTY_MASK (0x2U) #define LPDAC_FSR_EMPTY_SHIFT (1U) /*! EMPTY - FIFO Empty Flag * 0b0..Not empty * 0b1..Empty */ #define LPDAC_FSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK) #define LPDAC_FSR_WM_MASK (0x4U) #define LPDAC_FSR_WM_SHIFT (2U) /*! WM - FIFO Watermark Status Flag * 0b0..Data in FIFO is more than watermark level * 0b1..Data in FIFO is less than or equal to watermark level */ #define LPDAC_FSR_WM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK) #define LPDAC_FSR_SWBK_MASK (0x8U) #define LPDAC_FSR_SWBK_SHIFT (3U) /*! SWBK - Swing Back One Cycle Complete Flag * 0b0..No swing back cycle has completed since the last time the flag was cleared * 0b1..At least one swing back cycle has occurred since the last time the flag was cleared */ #define LPDAC_FSR_SWBK(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK) #define LPDAC_FSR_OF_MASK (0x40U) #define LPDAC_FSR_OF_SHIFT (6U) /*! OF - FIFO Overflow Flag * 0b0..No overflow has occurred since the last time the flag was cleared * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared */ #define LPDAC_FSR_OF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK) #define LPDAC_FSR_UF_MASK (0x80U) #define LPDAC_FSR_UF_SHIFT (7U) /*! UF - FIFO Underflow Flag * 0b0..No underflow has occurred since the last time the flag was cleared * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared */ #define LPDAC_FSR_UF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK) #define LPDAC_FSR_PTGCOCO_MASK (0x100U) #define LPDAC_FSR_PTGCOCO_SHIFT (8U) /*! PTGCOCO - Period Trigger Mode Conversion Complete Flag * 0b0..Not completed or not started * 0b1..Completed */ #define LPDAC_FSR_PTGCOCO(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_PTGCOCO_SHIFT)) & LPDAC_FSR_PTGCOCO_MASK) /*! @} */ /*! @name IER - Interrupt Enable */ /*! @{ */ #define LPDAC_IER_FULL_IE_MASK (0x1U) #define LPDAC_IER_FULL_IE_SHIFT (0U) /*! FULL_IE - FIFO Full Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_IER_FULL_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK) #define LPDAC_IER_EMPTY_IE_MASK (0x2U) #define LPDAC_IER_EMPTY_IE_SHIFT (1U) /*! EMPTY_IE - FIFO Empty Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_IER_EMPTY_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK) #define LPDAC_IER_WM_IE_MASK (0x4U) #define LPDAC_IER_WM_IE_SHIFT (2U) /*! WM_IE - FIFO Watermark Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_IER_WM_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK) #define LPDAC_IER_SWBK_IE_MASK (0x8U) #define LPDAC_IER_SWBK_IE_SHIFT (3U) /*! SWBK_IE - Swing Back One Cycle Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_IER_SWBK_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK) #define LPDAC_IER_OF_IE_MASK (0x40U) #define LPDAC_IER_OF_IE_SHIFT (6U) /*! OF_IE - FIFO Overflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_IER_OF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK) #define LPDAC_IER_UF_IE_MASK (0x80U) #define LPDAC_IER_UF_IE_SHIFT (7U) /*! UF_IE - FIFO Underflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_IER_UF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK) #define LPDAC_IER_PTGCOCO_IE_MASK (0x100U) #define LPDAC_IER_PTGCOCO_IE_SHIFT (8U) /*! PTGCOCO_IE - PTG Mode Conversion Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_IER_PTGCOCO_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_PTGCOCO_IE_SHIFT)) & LPDAC_IER_PTGCOCO_IE_MASK) /*! @} */ /*! @name DER - DMA Enable */ /*! @{ */ #define LPDAC_DER_EMPTY_DMAEN_MASK (0x2U) #define LPDAC_DER_EMPTY_DMAEN_SHIFT (1U) /*! EMPTY_DMAEN - FIFO Empty DMA Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_DER_EMPTY_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK) #define LPDAC_DER_WM_DMAEN_MASK (0x4U) #define LPDAC_DER_WM_DMAEN_SHIFT (2U) /*! WM_DMAEN - FIFO Watermark DMA Enable * 0b0..Disables * 0b1..Enables */ #define LPDAC_DER_WM_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK) /*! @} */ /*! @name RCR - Reset Control */ /*! @{ */ #define LPDAC_RCR_SWRST_MASK (0x1U) #define LPDAC_RCR_SWRST_SHIFT (0U) /*! SWRST - Software Reset * 0b0..No effect * 0b1..Software reset */ #define LPDAC_RCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK) #define LPDAC_RCR_FIFORST_MASK (0x2U) #define LPDAC_RCR_FIFORST_SHIFT (1U) /*! FIFORST - FIFO Reset * 0b0..No effect * 0b1..FIFO reset */ #define LPDAC_RCR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK) /*! @} */ /*! @name TCR - Trigger Control */ /*! @{ */ #define LPDAC_TCR_SWTRG_MASK (0x1U) #define LPDAC_TCR_SWTRG_SHIFT (0U) /*! SWTRG - Software Trigger * 0b0..Not valid * 0b1..Valid */ #define LPDAC_TCR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK) /*! @} */ /*! @name PCR - Periodic Trigger Control */ /*! @{ */ #define LPDAC_PCR_PTG_NUM_MASK (0xFFFFU) #define LPDAC_PCR_PTG_NUM_SHIFT (0U) /*! PTG_NUM - Periodic Trigger Number */ #define LPDAC_PCR_PTG_NUM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_NUM_SHIFT)) & LPDAC_PCR_PTG_NUM_MASK) #define LPDAC_PCR_PTG_PERIOD_MASK (0xFFFF0000U) #define LPDAC_PCR_PTG_PERIOD_SHIFT (16U) /*! PTG_PERIOD - Periodic Trigger Period Width */ #define LPDAC_PCR_PTG_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_PERIOD_SHIFT)) & LPDAC_PCR_PTG_PERIOD_MASK) /*! @} */ /*! * @} */ /* end of group LPDAC_Register_Masks */ /* LPDAC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral DAC0 base address */ #define DAC0_BASE (0x5010F000u) /** Peripheral DAC0 base address */ #define DAC0_BASE_NS (0x4010F000u) /** Peripheral DAC0 base pointer */ #define DAC0 ((LPDAC_Type *)DAC0_BASE) /** Peripheral DAC0 base pointer */ #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) /** Peripheral DAC1 base address */ #define DAC1_BASE (0x50112000u) /** Peripheral DAC1 base address */ #define DAC1_BASE_NS (0x40112000u) /** Peripheral DAC1 base pointer */ #define DAC1 ((LPDAC_Type *)DAC1_BASE) /** Peripheral DAC1 base pointer */ #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) /** Array initializer of LPDAC peripheral base addresses */ #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } /** Array initializer of LPDAC peripheral base pointers */ #define LPDAC_BASE_PTRS { DAC0, DAC1 } /** Array initializer of LPDAC peripheral base addresses */ #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS } /** Array initializer of LPDAC peripheral base pointers */ #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS } #else /** Peripheral DAC0 base address */ #define DAC0_BASE (0x4010F000u) /** Peripheral DAC0 base pointer */ #define DAC0 ((LPDAC_Type *)DAC0_BASE) /** Peripheral DAC1 base address */ #define DAC1_BASE (0x40112000u) /** Peripheral DAC1 base pointer */ #define DAC1 ((LPDAC_Type *)DAC1_BASE) /** Array initializer of LPDAC peripheral base addresses */ #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } /** Array initializer of LPDAC peripheral base pointers */ #define LPDAC_BASE_PTRS { DAC0, DAC1 } #endif /** Interrupt vectors for the LPDAC peripheral type */ #define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn } /*! * @} */ /* end of group LPDAC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPI2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer * @{ */ /** LPI2C - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ uint8_t RESERVED_1[16]; __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ uint8_t RESERVED_2[4]; __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ uint8_t RESERVED_3[4]; __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ uint8_t RESERVED_4[4]; __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ uint8_t RESERVED_5[12]; __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ uint8_t RESERVED_6[4]; __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ uint8_t RESERVED_7[148]; __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ uint8_t RESERVED_8[20]; __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ uint8_t RESERVED_9[12]; __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ uint8_t RESERVED_10[8]; __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ uint8_t RESERVED_11[12]; __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ uint8_t RESERVED_12[4]; __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ uint8_t RESERVED_13[132]; __O uint32_t MTCBR[128]; /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */ __O uint32_t MTDBR[253]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ } LPI2C_Type; /* ---------------------------------------------------------------------------- -- LPI2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Register_Masks LPI2C Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000010..Controller only, with standard feature set * 0b0000000000000011..Controller and target, with standard feature set */ #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) #define LPI2C_VERID_MINOR_MASK (0xFF0000U) #define LPI2C_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) /*! MTXFIFO - Controller Transmit FIFO Size */ #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) /*! MRXFIFO - Controller Receive FIFO Size */ #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) /*! @} */ /*! @name MCR - Controller Control */ /*! @{ */ #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) /*! MEN - Controller Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..No effect * 0b1..Reset */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) /*! DOZEN - Doze Mode Enable * 0b0..Enable * 0b1..Disable */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) #define LPI2C_MCR_RTF_MASK (0x100U) #define LPI2C_MCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Reset transmit FIFO */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Reset receive FIFO */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) /*! @} */ /*! @name MSR - Controller Status */ /*! @{ */ #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data requested */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive data not ready * 0b1..Receive data ready */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag * 0b0..No Stop or repeated Start generated * 0b1..Stop or repeated Start generated * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) /*! SDF - Stop Detect Flag * 0b0..No Stop condition generated * 0b1..Stop condition generated * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag * 0b0..No unexpected NACK detected * 0b1..Unexpected NACK detected * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag * 0b0..Controller did not lose arbitration * 0b1..Controller lost arbitration * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag * 0b0..No FIFO error * 0b1..FIFO error * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag * 0b0..Pin low timeout did not occur * 0b1..Pin low timeout occurred * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag * 0b0..Matching data not received * 0b1..Matching data received * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_STF_MASK (0x8000U) #define LPI2C_MSR_STF_SHIFT (15U) /*! STF - Start Flag * 0b0..Start condition not detected * 0b1..Start condition detected * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) #define LPI2C_MSR_MBF_MASK (0x1000000U) #define LPI2C_MSR_MBF_SHIFT (24U) /*! MBF - Controller Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) /*! @} */ /*! @name MIER - Controller Interrupt Enable */ /*! @{ */ #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) /*! EPIE - End Packet Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) /*! SDIE - Stop Detect Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) /*! NDIE - NACK Detect Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) /*! ALIE - Arbitration Lost Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) /*! PLTIE - Pin Low Timeout Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) /*! DMIE - Data Match Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) #define LPI2C_MIER_STIE_MASK (0x8000U) #define LPI2C_MIER_STIE_SHIFT (15U) /*! STIE - Start Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) /*! @} */ /*! @name MDER - Controller DMA Enable */ /*! @{ */ #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) /*! @} */ /*! @name MCFGR0 - Controller Configuration 0 */ /*! @{ */ #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active low * 0b1..Active high */ #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0..Host request input is pin HREQ * 0b1..Host request input is input trigger */ #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) #define LPI2C_MCFGR0_HRDIR_MASK (0x8U) #define LPI2C_MCFGR0_HRDIR_SHIFT (3U) /*! HRDIR - Host Request Direction * 0b0..HREQ pin is input (for LPI2C controller) * 0b1..HREQ pin is output (for LPI2C target) */ #define LPI2C_MCFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK) #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO * 0b1..Received data is discarded unless MSR[DMF] is set */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) #define LPI2C_MCFGR0_RELAX_MASK (0x10000U) #define LPI2C_MCFGR0_RELAX_SHIFT (16U) /*! RELAX - Relaxed Mode * 0b0..Normal transfer * 0b1..Relaxed transfer */ #define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) #define LPI2C_MCFGR0_ABORT_MASK (0x20000U) #define LPI2C_MCFGR0_ABORT_SHIFT (17U) /*! ABORT - Abort Transfer * 0b0..Normal transfer * 0b1..Abort existing transfer and do not start a new one */ #define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) /*! @} */ /*! @name MCFGR1 - Controller Configuration 1 */ /*! @{ */ #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) /*! PRESCALE - Prescaler * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) /*! AUTOSTOP - Automatic Stop Generation * 0b0..No effect * 0b1..Stop automatically generated */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) /*! IGNACK - Ignore NACK * 0b0..No effect * 0b1..Treat a received NACK as an ACK */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) /*! TIMECFG - Timeout Configuration * 0b0..SCL * 0b1..SCL or SDA */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) #define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) /*! STOPCFG - Stop Configuration * 0b0..Any Stop condition * 0b1..Last Stop condition */ #define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) #define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) #define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) /*! STARTCFG - Start Configuration * 0b0..Sets when both I2C bus and LPI2C controller are idle * 0b1..Sets when I2C bus is idle */ #define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b000..Two-pin open drain mode * 0b001..Two-pin output only mode (Ultra-Fast mode) * 0b010..Two-pin push-pull mode * 0b011..Four-pin push-pull mode * 0b100..Two-pin open-drain mode with separate LPI2C target * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target * 0b110..Two-pin push-pull mode with separate LPI2C target * 0b111..Four-pin push-pull mode (inverted outputs) */ #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) /*! @} */ /*! @name MCFGR2 - Controller Configuration 2 */ /*! @{ */ #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) /*! BUSIDLE - Bus Idle Timeout */ #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) /*! @} */ /*! @name MCFGR3 - Controller Configuration 3 */ /*! @{ */ #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) /*! PINLOW - Pin Low Timeout */ #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) /*! @} */ /*! @name MDMR - Controller Data Match */ /*! @{ */ #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) /*! MATCH1 - Match 1 Value */ #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) /*! @} */ /*! @name MCCR0 - Controller Clock Configuration 0 */ /*! @{ */ #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR0_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) /*! @} */ /*! @name MCCR1 - Controller Clock Configuration 1 */ /*! @{ */ #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR1_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) /*! @} */ /*! @name MFCR - Controller FIFO Control */ /*! @{ */ #define LPI2C_MFCR_TXWATER_MASK (0x7U) #define LPI2C_MFCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) #define LPI2C_MFCR_RXWATER_MASK (0x70000U) #define LPI2C_MFCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) /*! @} */ /*! @name MFSR - Controller FIFO Status */ /*! @{ */ #define LPI2C_MFSR_TXCOUNT_MASK (0xFU) #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) #define LPI2C_MFSR_RXCOUNT_MASK (0xF0000U) #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) /*! @} */ /*! @name MTDR - Controller Transmit Data */ /*! @{ */ #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) /*! CMD - Command Data * 0b000..Transmit the value in DATA[7:0] * 0b001..Receive (DATA[7:0] + 1) bytes * 0b010..Generate Stop condition on I2C bus * 0b011..Receive and discard (DATA[7:0] + 1) bytes * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) /*! @} */ /*! @name MRDR - Controller Receive Data */ /*! @{ */ #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - Receive Empty * 0b0..Not empty * 0b1..Empty */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) /*! @} */ /*! @name MRDROR - Controller Receive Data Read Only */ /*! @{ */ #define LPI2C_MRDROR_DATA_MASK (0xFFU) #define LPI2C_MRDROR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) #define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty * 0b0..Not empty * 0b1..Empty */ #define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) /*! @} */ /*! @name SCR - Target Control */ /*! @{ */ #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) /*! SEN - Target Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Not reset * 0b1..Reset */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) /*! FILTEN - Filter Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) /*! FILTDZ - Filter Doze Enable * 0b0..Enable * 0b1..Disable */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..STDR is now empty */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..SRDR is now empty */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) /*! @} */ /*! @name SSR - Target Status */ /*! @{ */ #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data is requested */ #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Not ready * 0b1..Ready */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) /*! AVF - Address Valid Flag * 0b0..Not valid * 0b1..Valid */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) /*! TAF - Transmit ACK Flag * 0b0..Not required * 0b1..Required */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) /*! RSF - Repeated Start Flag * 0b0..No repeated Start detected * 0b1..Repeated Start detected * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) /*! SDF - Stop Detect Flag * 0b0..No Stop detected * 0b1..Stop detected * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) /*! BEF - Bit Error Flag * 0b0..No bit error occurred * 0b1..Bit error occurred * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) /*! FEF - FIFO Error Flag * 0b0..No FIFO error * 0b1..FIFO error * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) /*! AM0F - Address Match 0 Flag * 0b0..ADDR0 matching address not received * 0b1..ADDR0 matching address received */ #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Flag * 0b0..Matching address not received * 0b1..Matching address received */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) /*! GCF - General Call Flag * 0b0..General call address disabled or not detected * 0b1..General call address detected */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) /*! SARF - SMBus Alert Response Flag * 0b0..Disabled or not detected * 0b1..Enabled and detected */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) /*! SBF - Target Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) /*! @} */ /*! @name SIER - Target Interrupt Enable */ /*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) /*! AVIE - Address Valid Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) /*! TAIE - Transmit ACK Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) /*! RSIE - Repeated Start Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) /*! SDIE - Stop Detect Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) /*! BEIE - Bit Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) /*! AM0IE - Address Match 0 Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1IE_MASK (0x2000U) #define LPI2C_SIER_AM1IE_SHIFT (13U) /*! AM1IE - Address Match 1 Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) /*! GCIE - General Call Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) /*! SARIE - SMBus Alert Response Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) /*! @} */ /*! @name SDER - Target DMA Enable */ /*! @{ */ #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..Disable DMA request * 0b1..Enable DMA request */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) /*! AVDE - Address Valid DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) #define LPI2C_SDER_RSDE_MASK (0x100U) #define LPI2C_SDER_RSDE_SHIFT (8U) /*! RSDE - Repeated Start DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) #define LPI2C_SDER_SDDE_MASK (0x200U) #define LPI2C_SDER_SDDE_SHIFT (9U) /*! SDDE - Stop Detect DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) /*! @} */ /*! @name SCFGR0 - Target Configuration 0 */ /*! @{ */ #define LPI2C_SCFGR0_RDREQ_MASK (0x1U) #define LPI2C_SCFGR0_RDREQ_SHIFT (0U) /*! RDREQ - Read Request * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) #define LPI2C_SCFGR0_RDACK_MASK (0x2U) #define LPI2C_SCFGR0_RDACK_SHIFT (1U) /*! RDACK - Read Acknowledge Flag * 0b0..Read Request not acknowledged * 0b1..Read Request acknowledged */ #define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) /*! @} */ /*! @name SCFGR1 - Target Configuration 1 */ /*! @{ */ #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) /*! ADRSTALL - Address SCL Stall * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) /*! RXSTALL - RX SCL Stall * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) /*! TXDSTALL - Transmit Data SCL Stall * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) /*! ACKSTALL - ACK SCL Stall * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_RXNACK_MASK (0x10U) #define LPI2C_SCFGR1_RXNACK_SHIFT (4U) /*! RXNACK - Receive NACK * 0b0..ACK or NACK always determined by STAR[TXNACK] * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] */ #define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) /*! GCEN - General Call Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) /*! SAEN - SMBus Alert Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) /*! TXCFG - Transmit Flag Configuration * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty * 0b1..MSR[TDF] is set whenever STDR is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration * 0b0..Return received data, clear MSR[RDF] * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) /*! IGNACK - Ignore NACK * 0b0..End transfer on NACK * 0b1..Do not end transfer on NACK */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) /*! HSMEN - HS Mode Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) /*! ADDRCFG - Address Configuration * 0b000..Address match 0 (7-bit) * 0b001..Address match 0 (10-bit) * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) #define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) #define LPI2C_SCFGR1_RXALL_SHIFT (24U) /*! RXALL - Receive All * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) #define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) #define LPI2C_SCFGR1_RSCFG_SHIFT (25U) /*! RSCFG - Repeated Start Configuration * 0b0..Any repeated Start condition following an address match * 0b1..Any repeated Start condition */ #define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) #define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) #define LPI2C_SCFGR1_SDCFG_SHIFT (26U) /*! SDCFG - Stop Detect Configuration * 0b0..Any Stop condition following an address match * 0b1..Any Stop condition */ #define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) /*! @} */ /*! @name SCFGR2 - Target Configuration 2 */ /*! @{ */ #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) /*! CLKHOLD - Clock Hold Time */ #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) /*! DATAVD - Data Valid Delay */ #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) /*! @} */ /*! @name SAMR - Target Address Match */ /*! @{ */ #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) /*! ADDR0 - Address 0 Value */ #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) /*! ADDR1 - Address 1 Value */ #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) /*! @} */ /*! @name SASR - Target Address Status */ /*! @{ */ #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) /*! RADDR - Received Address */ #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) /*! ANV - Address Not Valid * 0b0..Valid * 0b1..Not valid */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) /*! @} */ /*! @name STAR - Target Transmit ACK */ /*! @{ */ #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) /*! TXNACK - Transmit NACK * 0b0..Transmit ACK * 0b1..Transmit NACK */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) /*! @} */ /*! @name STDR - Target Transmit Data */ /*! @{ */ #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) /*! @} */ /*! @name SRDR - Target Receive Data */ /*! @{ */ #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) /*! DATA - Received Data */ #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RADDR_MASK (0x700U) #define LPI2C_SRDR_RADDR_SHIFT (8U) /*! RADDR - Received Address */ #define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - Receive Empty * 0b0..Not empty * 0b1..Empty */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) /*! SOF - Start of Frame * 0b0..Not first * 0b1..First */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /*! @} */ /*! @name SRDROR - Target Receive Data Read Only */ /*! @{ */ #define LPI2C_SRDROR_DATA_MASK (0xFFU) #define LPI2C_SRDROR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) #define LPI2C_SRDROR_RADDR_MASK (0x700U) #define LPI2C_SRDROR_RADDR_SHIFT (8U) /*! RADDR - Received Address */ #define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) #define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - Receive Empty * 0b0..Not empty * 0b1..Empty */ #define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) #define LPI2C_SRDROR_SOF_MASK (0x8000U) #define LPI2C_SRDROR_SOF_SHIFT (15U) /*! SOF - Start of Frame * 0b0..Not the first * 0b1..First */ #define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) /*! @} */ /*! @name MTCBR - Controller Transmit Command Burst */ /*! @{ */ #define LPI2C_MTCBR_DATA_MASK (0xFFU) #define LPI2C_MTCBR_DATA_SHIFT (0U) /*! DATA - Data */ #define LPI2C_MTCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK) #define LPI2C_MTCBR_CMD_MASK (0x700U) #define LPI2C_MTCBR_CMD_SHIFT (8U) /*! CMD - Command */ #define LPI2C_MTCBR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK) /*! @} */ /* The count of LPI2C_MTCBR */ #define LPI2C_MTCBR_COUNT (128U) /*! @name MTDBR - Transmit Data Burst */ /*! @{ */ #define LPI2C_MTDBR_DATA0_MASK (0xFFU) #define LPI2C_MTDBR_DATA0_SHIFT (0U) /*! DATA0 - Data */ #define LPI2C_MTDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK) #define LPI2C_MTDBR_DATA1_MASK (0xFF00U) #define LPI2C_MTDBR_DATA1_SHIFT (8U) /*! DATA1 - Data */ #define LPI2C_MTDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK) #define LPI2C_MTDBR_DATA2_MASK (0xFF0000U) #define LPI2C_MTDBR_DATA2_SHIFT (16U) /*! DATA2 - Data */ #define LPI2C_MTDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK) #define LPI2C_MTDBR_DATA3_MASK (0xFF000000U) #define LPI2C_MTDBR_DATA3_SHIFT (24U) /*! DATA3 - Data */ #define LPI2C_MTDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK) /*! @} */ /* The count of LPI2C_MTDBR */ #define LPI2C_MTDBR_COUNT (253U) /*! * @} */ /* end of group LPI2C_Register_Masks */ /* LPI2C - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral LPI2C0 base address */ #define LPI2C0_BASE (0x50092800u) /** Peripheral LPI2C0 base address */ #define LPI2C0_BASE_NS (0x40092800u) /** Peripheral LPI2C0 base pointer */ #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) /** Peripheral LPI2C0 base pointer */ #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) /** Peripheral LPI2C1 base address */ #define LPI2C1_BASE (0x50093800u) /** Peripheral LPI2C1 base address */ #define LPI2C1_BASE_NS (0x40093800u) /** Peripheral LPI2C1 base pointer */ #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) /** Peripheral LPI2C1 base pointer */ #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) /** Peripheral LPI2C2 base address */ #define LPI2C2_BASE (0x50094800u) /** Peripheral LPI2C2 base address */ #define LPI2C2_BASE_NS (0x40094800u) /** Peripheral LPI2C2 base pointer */ #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) /** Peripheral LPI2C2 base pointer */ #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) /** Peripheral LPI2C3 base address */ #define LPI2C3_BASE (0x50095800u) /** Peripheral LPI2C3 base address */ #define LPI2C3_BASE_NS (0x40095800u) /** Peripheral LPI2C3 base pointer */ #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) /** Peripheral LPI2C3 base pointer */ #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) /** Peripheral LPI2C4 base address */ #define LPI2C4_BASE (0x500B4800u) /** Peripheral LPI2C4 base address */ #define LPI2C4_BASE_NS (0x400B4800u) /** Peripheral LPI2C4 base pointer */ #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) /** Peripheral LPI2C4 base pointer */ #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) /** Peripheral LPI2C5 base address */ #define LPI2C5_BASE (0x500B5800u) /** Peripheral LPI2C5 base address */ #define LPI2C5_BASE_NS (0x400B5800u) /** Peripheral LPI2C5 base pointer */ #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) /** Peripheral LPI2C5 base pointer */ #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) /** Peripheral LPI2C6 base address */ #define LPI2C6_BASE (0x500B6800u) /** Peripheral LPI2C6 base address */ #define LPI2C6_BASE_NS (0x400B6800u) /** Peripheral LPI2C6 base pointer */ #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) /** Peripheral LPI2C6 base pointer */ #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) /** Peripheral LPI2C7 base address */ #define LPI2C7_BASE (0x500B7800u) /** Peripheral LPI2C7 base address */ #define LPI2C7_BASE_NS (0x400B7800u) /** Peripheral LPI2C7 base pointer */ #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) /** Peripheral LPI2C7 base pointer */ #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) /** Peripheral LPI2C8 base address */ #define LPI2C8_BASE (0x500B8800u) /** Peripheral LPI2C8 base address */ #define LPI2C8_BASE_NS (0x400B8800u) /** Peripheral LPI2C8 base pointer */ #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) /** Peripheral LPI2C8 base pointer */ #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) /** Peripheral LPI2C9 base address */ #define LPI2C9_BASE (0x500B9800u) /** Peripheral LPI2C9 base address */ #define LPI2C9_BASE_NS (0x400B9800u) /** Peripheral LPI2C9 base pointer */ #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) /** Peripheral LPI2C9 base pointer */ #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) /** Array initializer of LPI2C peripheral base addresses */ #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } /** Array initializer of LPI2C peripheral base pointers */ #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } /** Array initializer of LPI2C peripheral base addresses */ #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } /** Array initializer of LPI2C peripheral base pointers */ #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } #else /** Peripheral LPI2C0 base address */ #define LPI2C0_BASE (0x40092800u) /** Peripheral LPI2C0 base pointer */ #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) /** Peripheral LPI2C1 base address */ #define LPI2C1_BASE (0x40093800u) /** Peripheral LPI2C1 base pointer */ #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) /** Peripheral LPI2C2 base address */ #define LPI2C2_BASE (0x40094800u) /** Peripheral LPI2C2 base pointer */ #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) /** Peripheral LPI2C3 base address */ #define LPI2C3_BASE (0x40095800u) /** Peripheral LPI2C3 base pointer */ #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) /** Peripheral LPI2C4 base address */ #define LPI2C4_BASE (0x400B4800u) /** Peripheral LPI2C4 base pointer */ #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) /** Peripheral LPI2C5 base address */ #define LPI2C5_BASE (0x400B5800u) /** Peripheral LPI2C5 base pointer */ #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) /** Peripheral LPI2C6 base address */ #define LPI2C6_BASE (0x400B6800u) /** Peripheral LPI2C6 base pointer */ #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) /** Peripheral LPI2C7 base address */ #define LPI2C7_BASE (0x400B7800u) /** Peripheral LPI2C7 base pointer */ #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) /** Peripheral LPI2C8 base address */ #define LPI2C8_BASE (0x400B8800u) /** Peripheral LPI2C8 base pointer */ #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) /** Peripheral LPI2C9 base address */ #define LPI2C9_BASE (0x400B9800u) /** Peripheral LPI2C9 base pointer */ #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) /** Array initializer of LPI2C peripheral base addresses */ #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } /** Array initializer of LPI2C peripheral base pointers */ #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } #endif /** Interrupt vectors for the LPI2C peripheral type */ #define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } /*! * @} */ /* end of group LPI2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer * @{ */ /** LPSPI - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CR; /**< Control, offset: 0x10 */ __IO uint32_t SR; /**< Status, offset: 0x14 */ __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ uint8_t RESERVED_3[16]; __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ uint8_t RESERVED_4[8]; __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ uint8_t RESERVED_5[896]; __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ __O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ __I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ } LPSPI_Type; /* ---------------------------------------------------------------------------- -- LPSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Register_Masks LPSPI Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Module Identification Number * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. * *.. */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) #define LPSPI_VERID_MINOR_MASK (0xFF0000U) #define LPSPI_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) #define LPSPI_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) #define LPSPI_PARAM_PCSNUM_SHIFT (16U) /*! PCSNUM - PCS Number */ #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) /*! @} */ /*! @name CR - Control */ /*! @{ */ #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) /*! MEN - Module Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) #define LPSPI_CR_RST_MASK (0x2U) #define LPSPI_CR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Not reset * 0b1..Reset */ #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) #define LPSPI_CR_RTF_MASK (0x100U) #define LPSPI_CR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Reset */ #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Reset */ #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) /*! @} */ /*! @name SR - Status */ /*! @{ */ #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data requested */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) #define LPSPI_SR_RDF_MASK (0x2U) #define LPSPI_SR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive data not ready * 0b1..Receive data ready */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) /*! WCF - Word Complete Flag * 0b0..Not complete * 0b1..Complete * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) /*! FCF - Frame Complete Flag * 0b0..Not complete * 0b1..Complete * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) /*! TCF - Transfer Complete Flag * 0b0..Not complete * 0b1..Complete * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) /*! TEF - Transmit Error Flag * 0b0..No underrun * 0b1..Underrun * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) /*! REF - Receive Error Flag * 0b0..No overflow * 0b1..Overflow * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) /*! DMF - Data Match Flag * 0b0..No match * 0b1..Match * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) /*! MBF - Module Busy Flag * 0b0..LPSPI is idle * 0b1..LPSPI is busy */ #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) /*! @} */ /*! @name IER - Interrupt Enable */ /*! @{ */ #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) #define LPSPI_IER_RDIE_MASK (0x2U) #define LPSPI_IER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) #define LPSPI_IER_WCIE_MASK (0x100U) #define LPSPI_IER_WCIE_SHIFT (8U) /*! WCIE - Word Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) #define LPSPI_IER_FCIE_MASK (0x200U) #define LPSPI_IER_FCIE_SHIFT (9U) /*! FCIE - Frame Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) #define LPSPI_IER_TCIE_MASK (0x400U) #define LPSPI_IER_TCIE_SHIFT (10U) /*! TCIE - Transfer Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) #define LPSPI_IER_TEIE_MASK (0x800U) #define LPSPI_IER_TEIE_SHIFT (11U) /*! TEIE - Transmit Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) #define LPSPI_IER_REIE_MASK (0x1000U) #define LPSPI_IER_REIE_SHIFT (12U) /*! REIE - Receive Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) /*! DMIE - Data Match Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) /*! @} */ /*! @name DER - DMA Enable */ /*! @{ */ #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) #define LPSPI_DER_FCDE_MASK (0x200U) #define LPSPI_DER_FCDE_SHIFT (9U) /*! FCDE - Frame Complete DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) /*! @} */ /*! @name CFGR0 - Configuration 0 */ /*! @{ */ #define LPSPI_CFGR0_HREN_MASK (0x1U) #define LPSPI_CFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) #define LPSPI_CFGR0_HRPOL_MASK (0x2U) #define LPSPI_CFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active high * 0b1..Active low */ #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) #define LPSPI_CFGR0_HRSEL_MASK (0x4U) #define LPSPI_CFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0..HREQ pin * 0b1..Input trigger */ #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) #define LPSPI_CFGR0_HRDIR_MASK (0x8U) #define LPSPI_CFGR0_HRDIR_SHIFT (3U) /*! HRDIR - Host Request Direction * 0b0..Input * 0b1..Output */ #define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK) #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) /*! @} */ /*! @name CFGR1 - Configuration 1 */ /*! @{ */ #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) /*! MASTER - Master Mode * 0b0..Slave mode * 0b1..Master mode */ #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) /*! SAMPLE - Sample Point * 0b0..SCK edge * 0b1..Delayed SCK edge */ #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) /*! AUTOPCS - Automatic PCS * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) /*! NOSTALL - No Stall * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) #define LPSPI_CFGR1_PARTIAL_MASK (0x10U) #define LPSPI_CFGR1_PARTIAL_SHIFT (4U) /*! PARTIAL - Partial Enable * 0b0..Discard * 0b1..Store */ #define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) /*! PCSPOL - Peripheral Chip Select Polarity * 0b0000..Active low * 0b0001..Active high */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) #define LPSPI_CFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001.. * 0b010..Match first data word with compare word * 0b011..Match any data word with compare word * 0b100..Sequential match, first data word * 0b101..Sequential match, any data word * 0b110..Match first data word (masked) with compare word (masked) * 0b111..Match any data word (masked) with compare word (masked) */ #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b00..SIN is used for input data; SOUT is used for output data * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported * 0b11..SOUT is used for input data; SIN is used for output data */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) /*! OUTCFG - Output Configuration * 0b0..Retain last value * 0b1..3-stated */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) /*! PCSCFG - Peripheral Chip Select Configuration * 0b0..PCS[3:2] configured for chip select function * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) */ #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) /*! @} */ /*! @name DMR0 - Data Match 0 */ /*! @{ */ #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) /*! @} */ /*! @name DMR1 - Data Match 1 */ /*! @{ */ #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) /*! MATCH1 - Match 1 Value */ #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) /*! @} */ /*! @name CCR - Clock Configuration */ /*! @{ */ #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) /*! SCKDIV - SCK Divider */ #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) #define LPSPI_CCR_DBT_MASK (0xFF00U) #define LPSPI_CCR_DBT_SHIFT (8U) /*! DBT - Delay Between Transfers */ #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) #define LPSPI_CCR_PCSSCK_SHIFT (16U) /*! PCSSCK - PCS-to-SCK Delay */ #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) /*! SCKPCS - SCK-to-PCS Delay */ #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) /*! @} */ /*! @name CCR1 - Clock Configuration 1 */ /*! @{ */ #define LPSPI_CCR1_SCKSET_MASK (0xFFU) #define LPSPI_CCR1_SCKSET_SHIFT (0U) /*! SCKSET - SCK Setup */ #define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) #define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) #define LPSPI_CCR1_SCKHLD_SHIFT (8U) /*! SCKHLD - SCK Hold */ #define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) #define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) #define LPSPI_CCR1_PCSPCS_SHIFT (16U) /*! PCSPCS - PCS to PCS Delay */ #define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) #define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) #define LPSPI_CCR1_SCKSCK_SHIFT (24U) /*! SCKSCK - SCK Inter-Frame Delay */ #define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) /*! @} */ /*! @name FCR - FIFO Control */ /*! @{ */ #define LPSPI_FCR_TXWATER_MASK (0x7U) #define LPSPI_FCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) #define LPSPI_FCR_RXWATER_MASK (0x70000U) #define LPSPI_FCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) /*! @} */ /*! @name FSR - FIFO Status */ /*! @{ */ #define LPSPI_FSR_TXCOUNT_MASK (0xFU) #define LPSPI_FSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) #define LPSPI_FSR_RXCOUNT_MASK (0xF0000U) #define LPSPI_FSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) /*! @} */ /*! @name TCR - Transmit Command */ /*! @{ */ #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) /*! FRAMESZ - Frame Size */ #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) #define LPSPI_TCR_WIDTH_MASK (0x30000U) #define LPSPI_TCR_WIDTH_SHIFT (16U) /*! WIDTH - Transfer Width * 0b00..1-bit transfer * 0b01..2-bit transfer * 0b10..4-bit transfer * 0b11..Reserved */ #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) #define LPSPI_TCR_TXMSK_MASK (0x40000U) #define LPSPI_TCR_TXMSK_SHIFT (18U) /*! TXMSK - Transmit Data Mask * 0b0..Normal transfer * 0b1..Mask transmit data */ #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) #define LPSPI_TCR_RXMSK_MASK (0x80000U) #define LPSPI_TCR_RXMSK_SHIFT (19U) /*! RXMSK - Receive Data Mask * 0b0..Normal transfer * 0b1..Mask receive data */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) #define LPSPI_TCR_CONTC_MASK (0x100000U) #define LPSPI_TCR_CONTC_SHIFT (20U) /*! CONTC - Continuing Command * 0b0..Command word for start of new transfer * 0b1..Command word for continuing transfer */ #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) /*! CONT - Continuous Transfer * 0b0..Disable * 0b1..Enable */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) /*! BYSW - Byte Swap * 0b0..Disable byte swap * 0b1..Enable byte swap */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) /*! LSBF - LSB First * 0b0..MSB first * 0b1..LSB first */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) #define LPSPI_TCR_PCS_MASK (0x3000000U) #define LPSPI_TCR_PCS_SHIFT (24U) /*! PCS - Peripheral Chip Select * 0b00..Transfer using PCS[0] * 0b01..Transfer using PCS[1] * 0b10..Transfer using PCS[2] * 0b11..Transfer using PCS[3] */ #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) #define LPSPI_TCR_PRESCALE_SHIFT (27U) /*! PRESCALE - Prescaler Value * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) #define LPSPI_TCR_CPHA_MASK (0x40000000U) #define LPSPI_TCR_CPHA_SHIFT (30U) /*! CPHA - Clock Phase * 0b0..Captured * 0b1..Changed */ #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) /*! CPOL - Clock Polarity * 0b0..Inactive low * 0b1..Inactive high */ #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) /*! @} */ /*! @name TDR - Transmit Data */ /*! @{ */ #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) /*! @} */ /*! @name RSR - Receive Status */ /*! @{ */ #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) /*! SOF - Start of Frame * 0b0..Subsequent data word * 0b1..First data word */ #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) /*! RXEMPTY - RX FIFO Empty * 0b0..Not empty * 0b1..Empty */ #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) /*! @} */ /*! @name RDR - Receive Data */ /*! @{ */ #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) /*! @} */ /*! @name RDROR - Receive Data Read Only */ /*! @{ */ #define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDROR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) /*! @} */ /*! @name TCBR - Transmit Command Burst */ /*! @{ */ #define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TCBR_DATA_SHIFT (0U) /*! DATA - Command Data */ #define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) /*! @} */ /*! @name TDBR - Transmit Data Burst */ /*! @{ */ #define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDBR_DATA_SHIFT (0U) /*! DATA - Data */ #define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) /*! @} */ /* The count of LPSPI_TDBR */ #define LPSPI_TDBR_COUNT (128U) /*! @name RDBR - Receive Data Burst */ /*! @{ */ #define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDBR_DATA_SHIFT (0U) /*! DATA - Data */ #define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) /*! @} */ /* The count of LPSPI_RDBR */ #define LPSPI_RDBR_COUNT (128U) /*! * @} */ /* end of group LPSPI_Register_Masks */ /* LPSPI - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral LPSPI0 base address */ #define LPSPI0_BASE (0x50092000u) /** Peripheral LPSPI0 base address */ #define LPSPI0_BASE_NS (0x40092000u) /** Peripheral LPSPI0 base pointer */ #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) /** Peripheral LPSPI0 base pointer */ #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) /** Peripheral LPSPI1 base address */ #define LPSPI1_BASE (0x50093000u) /** Peripheral LPSPI1 base address */ #define LPSPI1_BASE_NS (0x40093000u) /** Peripheral LPSPI1 base pointer */ #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) /** Peripheral LPSPI1 base pointer */ #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) /** Peripheral LPSPI2 base address */ #define LPSPI2_BASE (0x50094000u) /** Peripheral LPSPI2 base address */ #define LPSPI2_BASE_NS (0x40094000u) /** Peripheral LPSPI2 base pointer */ #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) /** Peripheral LPSPI2 base pointer */ #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) /** Peripheral LPSPI3 base address */ #define LPSPI3_BASE (0x50095000u) /** Peripheral LPSPI3 base address */ #define LPSPI3_BASE_NS (0x40095000u) /** Peripheral LPSPI3 base pointer */ #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) /** Peripheral LPSPI3 base pointer */ #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) /** Peripheral LPSPI4 base address */ #define LPSPI4_BASE (0x500B4000u) /** Peripheral LPSPI4 base address */ #define LPSPI4_BASE_NS (0x400B4000u) /** Peripheral LPSPI4 base pointer */ #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) /** Peripheral LPSPI4 base pointer */ #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) /** Peripheral LPSPI5 base address */ #define LPSPI5_BASE (0x500B5000u) /** Peripheral LPSPI5 base address */ #define LPSPI5_BASE_NS (0x400B5000u) /** Peripheral LPSPI5 base pointer */ #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) /** Peripheral LPSPI5 base pointer */ #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) /** Peripheral LPSPI6 base address */ #define LPSPI6_BASE (0x500B6000u) /** Peripheral LPSPI6 base address */ #define LPSPI6_BASE_NS (0x400B6000u) /** Peripheral LPSPI6 base pointer */ #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) /** Peripheral LPSPI6 base pointer */ #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) /** Peripheral LPSPI7 base address */ #define LPSPI7_BASE (0x500B7000u) /** Peripheral LPSPI7 base address */ #define LPSPI7_BASE_NS (0x400B7000u) /** Peripheral LPSPI7 base pointer */ #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) /** Peripheral LPSPI7 base pointer */ #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) /** Peripheral LPSPI8 base address */ #define LPSPI8_BASE (0x500B8000u) /** Peripheral LPSPI8 base address */ #define LPSPI8_BASE_NS (0x400B8000u) /** Peripheral LPSPI8 base pointer */ #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) /** Peripheral LPSPI8 base pointer */ #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) /** Peripheral LPSPI9 base address */ #define LPSPI9_BASE (0x500B9000u) /** Peripheral LPSPI9 base address */ #define LPSPI9_BASE_NS (0x400B9000u) /** Peripheral LPSPI9 base pointer */ #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) /** Peripheral LPSPI9 base pointer */ #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) /** Array initializer of LPSPI peripheral base addresses */ #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } /** Array initializer of LPSPI peripheral base pointers */ #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } /** Array initializer of LPSPI peripheral base addresses */ #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } /** Array initializer of LPSPI peripheral base pointers */ #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } #else /** Peripheral LPSPI0 base address */ #define LPSPI0_BASE (0x40092000u) /** Peripheral LPSPI0 base pointer */ #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) /** Peripheral LPSPI1 base address */ #define LPSPI1_BASE (0x40093000u) /** Peripheral LPSPI1 base pointer */ #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) /** Peripheral LPSPI2 base address */ #define LPSPI2_BASE (0x40094000u) /** Peripheral LPSPI2 base pointer */ #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) /** Peripheral LPSPI3 base address */ #define LPSPI3_BASE (0x40095000u) /** Peripheral LPSPI3 base pointer */ #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) /** Peripheral LPSPI4 base address */ #define LPSPI4_BASE (0x400B4000u) /** Peripheral LPSPI4 base pointer */ #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) /** Peripheral LPSPI5 base address */ #define LPSPI5_BASE (0x400B5000u) /** Peripheral LPSPI5 base pointer */ #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) /** Peripheral LPSPI6 base address */ #define LPSPI6_BASE (0x400B6000u) /** Peripheral LPSPI6 base pointer */ #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) /** Peripheral LPSPI7 base address */ #define LPSPI7_BASE (0x400B7000u) /** Peripheral LPSPI7 base pointer */ #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) /** Peripheral LPSPI8 base address */ #define LPSPI8_BASE (0x400B8000u) /** Peripheral LPSPI8 base pointer */ #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) /** Peripheral LPSPI9 base address */ #define LPSPI9_BASE (0x400B9000u) /** Peripheral LPSPI9 base pointer */ #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) /** Array initializer of LPSPI peripheral base addresses */ #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } /** Array initializer of LPSPI peripheral base pointers */ #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } #endif /** Interrupt vectors for the LPSPI peripheral type */ #define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } /*! * @} */ /* end of group LPSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer * @{ */ /** LPTMR - Register Layout Typedef */ typedef struct { __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ __IO uint32_t CMR; /**< Compare, offset: 0x8 */ __IO uint32_t CNR; /**< Counter, offset: 0xC */ } LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /*! @name CSR - Control Status */ /*! @{ */ #define LPTMR_CSR_TEN_MASK (0x1U) #define LPTMR_CSR_TEN_SHIFT (0U) /*! TEN - Timer Enable * 0b0..Disable * 0b1..Enable */ #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) #define LPTMR_CSR_TMS_MASK (0x2U) #define LPTMR_CSR_TMS_SHIFT (1U) /*! TMS - Timer Mode Select * 0b0..Time Counter * 0b1..Pulse Counter */ #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) #define LPTMR_CSR_TFC_MASK (0x4U) #define LPTMR_CSR_TFC_SHIFT (2U) /*! TFC - Timer Free-Running Counter * 0b0..Reset when TCF asserts * 0b1..Reset on overflow */ #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) #define LPTMR_CSR_TPP_MASK (0x8U) #define LPTMR_CSR_TPP_SHIFT (3U) /*! TPP - Timer Pin Polarity * 0b0..Active-high * 0b1..Active-low */ #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) #define LPTMR_CSR_TPS_MASK (0x30U) #define LPTMR_CSR_TPS_SHIFT (4U) /*! TPS - Timer Pin Select * 0b00..Input 0 * 0b01..Input 1 * 0b10..Input 2 * 0b11..Input 3 */ #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) #define LPTMR_CSR_TIE_MASK (0x40U) #define LPTMR_CSR_TIE_SHIFT (6U) /*! TIE - Timer Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) #define LPTMR_CSR_TCF_MASK (0x80U) #define LPTMR_CSR_TCF_SHIFT (7U) /*! TCF - Timer Compare Flag * 0b0..CNR != (CMR + 1) * 0b1..CNR = (CMR + 1) * 0b0..No effect * 0b1..Clear the flag */ #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) #define LPTMR_CSR_TDRE_MASK (0x100U) #define LPTMR_CSR_TDRE_SHIFT (8U) /*! TDRE - Timer DMA Request Enable * 0b0..Disable * 0b1..Enable */ #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) /*! @} */ /*! @name PSR - Prescaler and Glitch Filter */ /*! @{ */ #define LPTMR_PSR_PCS_MASK (0x3U) #define LPTMR_PSR_PCS_SHIFT (0U) /*! PCS - Prescaler and Glitch Filter Clock Select * 0b00..Clock 0 * 0b01..Clock 1 * 0b10..Clock 2 * 0b11..Clock 3 */ #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) #define LPTMR_PSR_PBYP_MASK (0x4U) #define LPTMR_PSR_PBYP_SHIFT (2U) /*! PBYP - Prescaler and Glitch Filter Bypass * 0b0..Prescaler and glitch filter enable * 0b1..Prescaler and glitch filter bypass */ #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) #define LPTMR_PSR_PRESCALE_MASK (0x78U) #define LPTMR_PSR_PRESCALE_SHIFT (3U) /*! PRESCALE - Prescaler and Glitch Filter Value * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges */ #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) /*! @} */ /*! @name CMR - Compare */ /*! @{ */ #define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) #define LPTMR_CMR_COMPARE_SHIFT (0U) /*! COMPARE - Compare Value */ #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) /*! @} */ /*! @name CNR - Counter */ /*! @{ */ #define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) #define LPTMR_CNR_COUNTER_SHIFT (0U) /*! COUNTER - Counter Value */ #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) /*! @} */ /*! * @} */ /* end of group LPTMR_Register_Masks */ /* LPTMR - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral LPTMR0 base address */ #define LPTMR0_BASE (0x5004A000u) /** Peripheral LPTMR0 base address */ #define LPTMR0_BASE_NS (0x4004A000u) /** Peripheral LPTMR0 base pointer */ #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) /** Peripheral LPTMR0 base pointer */ #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) /** Peripheral LPTMR1 base address */ #define LPTMR1_BASE (0x5004B000u) /** Peripheral LPTMR1 base address */ #define LPTMR1_BASE_NS (0x4004B000u) /** Peripheral LPTMR1 base pointer */ #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) /** Peripheral LPTMR1 base pointer */ #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) /** Array initializer of LPTMR peripheral base addresses */ #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } /** Array initializer of LPTMR peripheral base addresses */ #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } #else /** Peripheral LPTMR0 base address */ #define LPTMR0_BASE (0x4004A000u) /** Peripheral LPTMR0 base pointer */ #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) /** Peripheral LPTMR1 base address */ #define LPTMR1_BASE (0x4004B000u) /** Peripheral LPTMR1 base pointer */ #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) /** Array initializer of LPTMR peripheral base addresses */ #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } #endif /** Interrupt vectors for the LPTMR peripheral type */ #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } /*! * @} */ /* end of group LPTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer * @{ */ /** LPUART - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ __IO uint32_t STAT; /**< Status, offset: 0x14 */ __IO uint32_t CTRL; /**< Control, offset: 0x18 */ __IO uint32_t DATA; /**< Data, offset: 0x1C */ __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t MCR; /**< MODEM Control, offset: 0x40 */ __IO uint32_t MSR; /**< MODEM Status, offset: 0x44 */ __IO uint32_t REIR; /**< Receiver Extended Idle, offset: 0x48 */ __IO uint32_t TEIR; /**< Transmitter Extended Idle, offset: 0x4C */ __IO uint32_t HDCR; /**< Half Duplex Control, offset: 0x50 */ uint8_t RESERVED_1[4]; __IO uint32_t TOCR; /**< Timeout Control, offset: 0x58 */ __IO uint32_t TOSR; /**< Timeout Status, offset: 0x5C */ __IO uint32_t TIMEOUT[4]; /**< Timeout N, array offset: 0x60, array step: 0x4 */ uint8_t RESERVED_2[400]; __O uint32_t TCBR[128]; /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */ __O uint32_t TDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ } LPUART_Type; /* ---------------------------------------------------------------------------- -- LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Register_Masks LPUART Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000001..Standard feature set * 0b0000000000000011..Standard feature set with MODEM and IrDA support * 0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection */ #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) #define LPUART_VERID_MINOR_MASK (0xFF0000U) #define LPUART_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) /*! @} */ /*! @name GLOBAL - Global */ /*! @{ */ #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Not reset * 0b1..Reset */ #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) /*! @} */ /*! @name PINCFG - Pin Configuration */ /*! @{ */ #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) /*! TRGSEL - Trigger Select * 0b00..Input trigger disabled * 0b01..Input trigger used instead of the RXD pin input * 0b10..Input trigger used instead of the CTS_B pin input * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger */ #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) /*! @} */ /*! @name BAUD - Baud Rate */ /*! @{ */ #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) /*! SBR - Baud Rate Modulo Divisor */ #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) #define LPUART_BAUD_SBNS_MASK (0x2000U) #define LPUART_BAUD_SBNS_SHIFT (13U) /*! SBNS - Stop Bit Number Select * 0b0..One stop bit * 0b1..Two stop bits */ #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) /*! RXEDGIE - RX Input Active Edge Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) /*! LBKDIE - LIN Break Detect Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) /*! RESYNCDIS - Resynchronization Disable * 0b0..Enable * 0b1..Disable */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) /*! BOTHEDGE - Both Edge Sampling * 0b0..Rising edge * 0b1..Both rising and falling edges */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) /*! MATCFG - Match Configuration * 0b00..Address match wake-up * 0b01..Idle match wake-up * 0b10..Match on and match off * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) #define LPUART_BAUD_RIDMAE_SHIFT (20U) /*! RIDMAE - Receiver Idle DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) /*! RDMAE - Receiver Full DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) /*! TDMAE - Transmitter DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) /*! OSR - Oversampling Ratio * 0b00000..Results in an OSR of 16 * 0b00001..Reserved * 0b00010..Reserved * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) * 0b00111..Results in an OSR of 8 * 0b01000..Results in an OSR of 9 * 0b01001..Results in an OSR of 10 * 0b01010..Results in an OSR of 11 * 0b01011..Results in an OSR of 12 * 0b01100..Results in an OSR of 13 * 0b01101..Results in an OSR of 14 * 0b01110..Results in an OSR of 15 * 0b01111..Results in an OSR of 16 * 0b10000..Results in an OSR of 17 * 0b10001..Results in an OSR of 18 * 0b10010..Results in an OSR of 19 * 0b10011..Results in an OSR of 20 * 0b10100..Results in an OSR of 21 * 0b10101..Results in an OSR of 22 * 0b10110..Results in an OSR of 23 * 0b10111..Results in an OSR of 24 * 0b11000..Results in an OSR of 25 * 0b11001..Results in an OSR of 26 * 0b11010..Results in an OSR of 27 * 0b11011..Results in an OSR of 28 * 0b11100..Results in an OSR of 29 * 0b11101..Results in an OSR of 30 * 0b11110..Results in an OSR of 31 * 0b11111..Results in an OSR of 32 */ #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) #define LPUART_BAUD_M10_MASK (0x20000000U) #define LPUART_BAUD_M10_SHIFT (29U) /*! M10 - 10-Bit Mode Select * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters * 0b1..Receiver and transmitter use 10-bit data characters */ #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) /*! MAEN2 - Match Address Mode Enable 2 * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) /*! MAEN1 - Match Address Mode Enable 1 * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) /*! @} */ /*! @name STAT - Status */ /*! @{ */ #define LPUART_STAT_LBKFE_MASK (0x1U) #define LPUART_STAT_LBKFE_SHIFT (0U) /*! LBKFE - LIN Break Flag Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) #define LPUART_STAT_AME_MASK (0x2U) #define LPUART_STAT_AME_SHIFT (1U) /*! AME - Address Mark Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) #define LPUART_STAT_MSF_MASK (0x100U) #define LPUART_STAT_MSF_SHIFT (8U) /*! MSF - MODEM Status Flag * 0b0..Field is 0 * 0b1..Field is 1 */ #define LPUART_STAT_MSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK) #define LPUART_STAT_TSF_MASK (0x200U) #define LPUART_STAT_TSF_SHIFT (9U) /*! TSF - Timeout Status Flag * 0b0..Field is 0 * 0b1..Field is 1 */ #define LPUART_STAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK) #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) /*! MA2F - Match 2 Flag * 0b0..Not equal to MA2 * 0b1..Equal to MA2 * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) /*! MA1F - Match 1 Flag * 0b0..Not equal to MA1 * 0b1..Equal to MA1 * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) /*! PF - Parity Error Flag * 0b0..No parity error detected * 0b1..Parity error detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) /*! FE - Framing Error Flag * 0b0..No framing error detected (this does not guarantee that the framing is correct) * 0b1..Framing error detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) /*! NF - Noise Flag * 0b0..No noise detected * 0b1..Noise detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag * 0b0..No overrun * 0b1..Receive overrun (new LPUART data is lost) * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) /*! IDLE - Idle Line Flag * 0b0..Idle line detected * 0b1..Idle line not detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) #define LPUART_STAT_RDRF_MASK (0x200000U) #define LPUART_STAT_RDRF_SHIFT (21U) /*! RDRF - Receive Data Register Full Flag * 0b0..Equal to or less than watermark * 0b1..Greater than watermark */ #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) /*! TC - Transmission Complete Flag * 0b0..Transmitter active * 0b1..Transmitter idle */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) #define LPUART_STAT_TDRE_MASK (0x800000U) #define LPUART_STAT_TDRE_SHIFT (23U) /*! TDRE - Transmit Data Register Empty Flag * 0b0..Greater than watermark * 0b1..Equal to or less than watermark */ #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) #define LPUART_STAT_RAF_MASK (0x1000000U) #define LPUART_STAT_RAF_SHIFT (24U) /*! RAF - Receiver Active Flag * 0b0..Idle, waiting for a start bit * 0b1..Receiver active (RXD pin input not idle) */ #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) /*! LBKDE - LIN Break Detection Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) #define LPUART_STAT_BRK13_MASK (0x4000000U) #define LPUART_STAT_BRK13_SHIFT (26U) /*! BRK13 - Break Character Generation Length * 0b0..9 to 13 bit times * 0b1..12 to 15 bit times */ #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) #define LPUART_STAT_RWUID_MASK (0x8000000U) #define LPUART_STAT_RWUID_SHIFT (27U) /*! RWUID - Receive Wake Up Idle Detect * 0b0..STAT[IDLE] does not become 1 * 0b1..STAT[IDLE] becomes 1 */ #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) #define LPUART_STAT_RXINV_MASK (0x10000000U) #define LPUART_STAT_RXINV_SHIFT (28U) /*! RXINV - Receive Data Inversion * 0b0..Inverted * 0b1..Not inverted */ #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) #define LPUART_STAT_MSBF_MASK (0x20000000U) #define LPUART_STAT_MSBF_SHIFT (29U) /*! MSBF - MSB First * 0b0..LSB * 0b1..MSB */ #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag * 0b0..Not occurred * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) /*! LBKDIF - LIN Break Detect Interrupt Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) /*! @} */ /*! @name CTRL - Control */ /*! @{ */ #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) /*! PT - Parity Type * 0b0..Even parity * 0b1..Odd parity */ #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) /*! PE - Parity Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) #define LPUART_CTRL_ILT_MASK (0x4U) #define LPUART_CTRL_ILT_SHIFT (2U) /*! ILT - Idle Line Type Select * 0b0..After the start bit * 0b1..After the stop bit */ #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) /*! WAKE - Receiver Wake-Up Method Select * 0b0..Idle * 0b1..Mark */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) /*! M - 9-Bit Or 8-Bit Mode Select * 0b0..8-bit * 0b1..9-bit */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) #define LPUART_CTRL_RSRC_MASK (0x20U) #define LPUART_CTRL_RSRC_SHIFT (5U) /*! RSRC - Receiver Source Select * 0b0..Internal Loopback mode * 0b1..Single-wire mode */ #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) /*! DOZEEN - Doze Mode * 0b0..Enable * 0b1..Disable */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) #define LPUART_CTRL_LOOPS_MASK (0x80U) #define LPUART_CTRL_LOOPS_SHIFT (7U) /*! LOOPS - Loop Mode Select * 0b0..Normal operation: RXD and TXD use separate pins * 0b1..Loop mode or Single-Wire mode */ #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) #define LPUART_CTRL_IDLECFG_MASK (0x700U) #define LPUART_CTRL_IDLECFG_SHIFT (8U) /*! IDLECFG - Idle Configuration * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) /*! M7 - 7-Bit Mode Select * 0b0..8-bit to 10-bit * 0b1..7-bit */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) /*! MA2IE - Match 2 (MA2F) Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) /*! MA1IE - Match 1 (MA1F) Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) #define LPUART_CTRL_SBK_MASK (0x10000U) #define LPUART_CTRL_SBK_SHIFT (16U) /*! SBK - Send Break * 0b0..Normal transmitter operation * 0b1..Queue break character(s) to be sent */ #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) /*! RWU - Receiver Wake-Up Control * 0b0..Normal receiver operation * 0b1..LPUART receiver in standby, waiting for a wake-up condition */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) /*! RE - Receiver Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) /*! TE - Transmitter Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) /*! ILIE - Idle Line Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) /*! RIE - Receiver Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) /*! TCIE - Transmission Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) /*! TIE - Transmit Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) /*! PEIE - Parity Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) /*! FEIE - Framing Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) /*! NEIE - Noise Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) /*! ORIE - Overrun Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) #define LPUART_CTRL_TXINV_MASK (0x10000000U) #define LPUART_CTRL_TXINV_SHIFT (28U) /*! TXINV - Transmit Data Inversion * 0b0..Not inverted * 0b1..Inverted */ #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) /*! TXDIR - TXD Pin Direction in Single-Wire Mode * 0b0..Input * 0b1..Output */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) #define LPUART_CTRL_R9T8_MASK (0x40000000U) #define LPUART_CTRL_R9T8_SHIFT (30U) /*! R9T8 - Receive Bit 9 Transmit Bit 8 */ #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) /*! R8T9 - Receive Bit 8 Transmit Bit 9 */ #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) /*! @} */ /*! @name DATA - Data */ /*! @{ */ #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) /*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) #define LPUART_DATA_R1T1_MASK (0x2U) #define LPUART_DATA_R1T1_SHIFT (1U) /*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) #define LPUART_DATA_R2T2_MASK (0x4U) #define LPUART_DATA_R2T2_SHIFT (2U) /*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) #define LPUART_DATA_R3T3_MASK (0x8U) #define LPUART_DATA_R3T3_SHIFT (3U) /*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) #define LPUART_DATA_R4T4_MASK (0x10U) #define LPUART_DATA_R4T4_SHIFT (4U) /*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) #define LPUART_DATA_R5T5_MASK (0x20U) #define LPUART_DATA_R5T5_SHIFT (5U) /*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) #define LPUART_DATA_R6T6_MASK (0x40U) #define LPUART_DATA_R6T6_SHIFT (6U) /*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) #define LPUART_DATA_R7T7_MASK (0x80U) #define LPUART_DATA_R7T7_SHIFT (7U) /*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) #define LPUART_DATA_R8T8_MASK (0x100U) #define LPUART_DATA_R8T8_SHIFT (8U) /*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) #define LPUART_DATA_R9T9_MASK (0x200U) #define LPUART_DATA_R9T9_SHIFT (9U) /*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_LINBRK_MASK (0x400U) #define LPUART_DATA_LINBRK_SHIFT (10U) /*! LINBRK - LIN Break * 0b0..Not detected * 0b1..Detected */ #define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) /*! IDLINE - Idle Line * 0b0..Not idle * 0b1..Idle */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) /*! RXEMPT - Receive Buffer Empty * 0b0..Valid data * 0b1..Invalid data and empty */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) #define LPUART_DATA_FRETSC_MASK (0x2000U) #define LPUART_DATA_FRETSC_SHIFT (13U) /*! FRETSC - Frame Error Transmit Special Character * 0b0..Received without a frame error on reads or transmits a normal character on writes * 0b1..Received with a frame error on reads or transmits an idle or break character on writes */ #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) #define LPUART_DATA_PARITYE_MASK (0x4000U) #define LPUART_DATA_PARITYE_SHIFT (14U) /*! PARITYE - Parity Error * 0b0..Received without a parity error * 0b1..Received with a parity error */ #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) /*! NOISY - Noisy Data Received * 0b0..Received without noise * 0b1..Received with noise */ #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) /*! @} */ /*! @name MATCH - Match Address */ /*! @{ */ #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) /*! MA1 - Match Address 1 */ #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) /*! MA2 - Match Address 2 */ #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) /*! @} */ /*! @name MODIR - MODEM IrDA */ /*! @{ */ #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) /*! TXCTSE - Transmitter CTS Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) /*! TXRTSE - Transmitter RTS Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) /*! TXRTSPOL - Transmitter RTS Polarity * 0b0..Active low * 0b1..Active high */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver RTS Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) #define LPUART_MODIR_TXCTSC_SHIFT (4U) /*! TXCTSC - Transmit CTS Configuration * 0b0..Sampled at the start of each character * 0b1..Sampled when the transmitter is idle */ #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) /*! TXCTSSRC - Transmit CTS Source * 0b0..The CTS_B pin * 0b1..An internal connection to the receiver address match result */ #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) #define LPUART_MODIR_RTSWATER_MASK (0x700U) #define LPUART_MODIR_RTSWATER_SHIFT (8U) /*! RTSWATER - Receive RTS Configuration */ #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) #define LPUART_MODIR_TNP_MASK (0x30000U) #define LPUART_MODIR_TNP_SHIFT (16U) /*! TNP - Transmitter Narrow Pulse * 0b00..1 / OSR * 0b01..2 / OSR * 0b10..3 / OSR * 0b11..4 / OSR */ #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) /*! IREN - IR Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) /*! @} */ /*! @name FIFO - FIFO */ /*! @{ */ #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - Receive FIFO Buffer Depth * 0b000..1 * 0b001..4 * 0b010..8 * 0b011..16 * 0b100..32 * 0b101..64 * 0b110..128 * 0b111..256 */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) /*! RXFE - Receive FIFO Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) /*! TXFIFOSIZE - Transmit FIFO Buffer Depth * 0b000..1 * 0b001..4 * 0b010..8 * 0b011..16 * 0b100..32 * 0b101..64 * 0b110..128 * 0b111..256 */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) /*! TXFE - Transmit FIFO Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) /*! RXUFE - Receive FIFO Underflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) /*! TXOFE - Transmit FIFO Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) /*! RXIDEN - Receiver Idle Empty Enable * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) #define LPUART_FIFO_RXFLUSH_SHIFT (14U) /*! RXFLUSH - Receive FIFO Flush * 0b0..No effect * 0b1..All data flushed out */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) #define LPUART_FIFO_TXFLUSH_SHIFT (15U) /*! TXFLUSH - Transmit FIFO Flush * 0b0..No effect * 0b1..All data flushed out */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) /*! RXUF - Receiver FIFO Underflow Flag * 0b0..No underflow * 0b1..Underflow * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) /*! TXOF - Transmitter FIFO Overflow Flag * 0b0..No overflow * 0b1..Overflow * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) #define LPUART_FIFO_RXEMPT_MASK (0x400000U) #define LPUART_FIFO_RXEMPT_SHIFT (22U) /*! RXEMPT - Receive FIFO Or Buffer Empty * 0b0..Not empty * 0b1..Empty */ #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) /*! TXEMPT - Transmit FIFO Or Buffer Empty * 0b0..Not empty * 0b1..Empty */ #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) /*! @} */ /*! @name WATER - Watermark */ /*! @{ */ #define LPUART_WATER_TXWATER_MASK (0x7U) #define LPUART_WATER_TXWATER_SHIFT (0U) /*! TXWATER - Transmit Watermark */ #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) #define LPUART_WATER_TXCOUNT_MASK (0xF00U) #define LPUART_WATER_TXCOUNT_SHIFT (8U) /*! TXCOUNT - Transmit Counter */ #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) #define LPUART_WATER_RXWATER_MASK (0x70000U) #define LPUART_WATER_RXWATER_SHIFT (16U) /*! RXWATER - Receive Watermark */ #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) #define LPUART_WATER_RXCOUNT_MASK (0xF000000U) #define LPUART_WATER_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Receive Counter */ #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) /*! @} */ /*! @name DATARO - Data Read-Only */ /*! @{ */ #define LPUART_DATARO_DATA_MASK (0xFFFFU) #define LPUART_DATARO_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) /*! @} */ /*! @name MCR - MODEM Control */ /*! @{ */ #define LPUART_MCR_CTS_MASK (0x1U) #define LPUART_MCR_CTS_SHIFT (0U) /*! CTS - Clear To Send * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) #define LPUART_MCR_DSR_MASK (0x2U) #define LPUART_MCR_DSR_SHIFT (1U) /*! DSR - Data Set Ready * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) #define LPUART_MCR_RIN_MASK (0x4U) #define LPUART_MCR_RIN_SHIFT (2U) /*! RIN - Ring Indicator * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) #define LPUART_MCR_DCD_MASK (0x8U) #define LPUART_MCR_DCD_SHIFT (3U) /*! DCD - Data Carrier Detect * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) #define LPUART_MCR_DTR_MASK (0x100U) #define LPUART_MCR_DTR_SHIFT (8U) /*! DTR - Data Terminal Ready * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) #define LPUART_MCR_RTS_MASK (0x200U) #define LPUART_MCR_RTS_SHIFT (9U) /*! RTS - Request To Send * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) /*! @} */ /*! @name MSR - MODEM Status */ /*! @{ */ #define LPUART_MSR_DCTS_MASK (0x1U) #define LPUART_MSR_DCTS_SHIFT (0U) /*! DCTS - Delta Clear To Send * 0b0..Did not change state * 0b1..Changed state * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) #define LPUART_MSR_DDSR_MASK (0x2U) #define LPUART_MSR_DDSR_SHIFT (1U) /*! DDSR - Delta Data Set Ready * 0b0..Did not change state * 0b1..Changed state * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) #define LPUART_MSR_DRI_MASK (0x4U) #define LPUART_MSR_DRI_SHIFT (2U) /*! DRI - Delta Ring Indicator * 0b0..Did not change state * 0b1..Changed state * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) #define LPUART_MSR_DDCD_MASK (0x8U) #define LPUART_MSR_DDCD_SHIFT (3U) /*! DDCD - Delta Data Carrier Detect * 0b0..Did not change state * 0b1..Changed state * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) #define LPUART_MSR_CTS_MASK (0x10U) #define LPUART_MSR_CTS_SHIFT (4U) /*! CTS - Clear To Send * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) #define LPUART_MSR_DSR_MASK (0x20U) #define LPUART_MSR_DSR_SHIFT (5U) /*! DSR - Data Set Ready * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) #define LPUART_MSR_RIN_MASK (0x40U) #define LPUART_MSR_RIN_SHIFT (6U) /*! RIN - Ring Indicator * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) #define LPUART_MSR_DCD_MASK (0x80U) #define LPUART_MSR_DCD_SHIFT (7U) /*! DCD - Data Carrier Detect * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) /*! @} */ /*! @name REIR - Receiver Extended Idle */ /*! @{ */ #define LPUART_REIR_IDTIME_MASK (0x3FFFU) #define LPUART_REIR_IDTIME_SHIFT (0U) /*! IDTIME - Idle Time */ #define LPUART_REIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK) /*! @} */ /*! @name TEIR - Transmitter Extended Idle */ /*! @{ */ #define LPUART_TEIR_IDTIME_MASK (0x3FFFU) #define LPUART_TEIR_IDTIME_SHIFT (0U) /*! IDTIME - Idle Time */ #define LPUART_TEIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK) /*! @} */ /*! @name HDCR - Half Duplex Control */ /*! @{ */ #define LPUART_HDCR_TXSTALL_MASK (0x1U) #define LPUART_HDCR_TXSTALL_SHIFT (0U) /*! TXSTALL - Transmit Stall * 0b0..No effect * 0b1..Does not become busy */ #define LPUART_HDCR_TXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK) #define LPUART_HDCR_RXSEL_MASK (0x2U) #define LPUART_HDCR_RXSEL_SHIFT (1U) /*! RXSEL - Receive Select * 0b0..RXD * 0b1..TXD */ #define LPUART_HDCR_RXSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK) #define LPUART_HDCR_RXWRMSK_MASK (0x4U) #define LPUART_HDCR_RXWRMSK_SHIFT (2U) /*! RXWRMSK - Receive FIFO Write Mask * 0b0..Do not mask * 0b1..Mask */ #define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) #define LPUART_HDCR_RXMSK_MASK (0x8U) #define LPUART_HDCR_RXMSK_SHIFT (3U) /*! RXMSK - Receive Mask * 0b0..Do not mask * 0b1..Mask */ #define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) #define LPUART_HDCR_RTSEXT_MASK (0xFF00U) #define LPUART_HDCR_RTSEXT_SHIFT (8U) /*! RTSEXT - RTS Extended */ #define LPUART_HDCR_RTSEXT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK) /*! @} */ /*! @name TOCR - Timeout Control */ /*! @{ */ #define LPUART_TOCR_TOEN_MASK (0xFU) #define LPUART_TOCR_TOEN_SHIFT (0U) /*! TOEN - Timeout Enable */ #define LPUART_TOCR_TOEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK) #define LPUART_TOCR_TOIE_MASK (0xF00U) #define LPUART_TOCR_TOIE_SHIFT (8U) /*! TOIE - Timeout Interrupt Enable */ #define LPUART_TOCR_TOIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK) /*! @} */ /*! @name TOSR - Timeout Status */ /*! @{ */ #define LPUART_TOSR_TOZ_MASK (0xFU) #define LPUART_TOSR_TOZ_SHIFT (0U) /*! TOZ - Timeout Zero */ #define LPUART_TOSR_TOZ(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK) #define LPUART_TOSR_TOF_MASK (0xF00U) #define LPUART_TOSR_TOF_SHIFT (8U) /*! TOF - Timeout Flag * 0b0000..Not occurred * 0b0001..Occurred * 0b0000..No effect * 0b0001..Clear the flag */ #define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) /*! @} */ /*! @name TIMEOUT - Timeout N */ /*! @{ */ #define LPUART_TIMEOUT_TIMEOUT_MASK (0x3FFFU) #define LPUART_TIMEOUT_TIMEOUT_SHIFT (0U) /*! TIMEOUT - Timeout Value */ #define LPUART_TIMEOUT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK) #define LPUART_TIMEOUT_CFG_MASK (0xC0000000U) #define LPUART_TIMEOUT_CFG_SHIFT (30U) /*! CFG - Idle Configuration * 0b00..Becomes 1 after timeout characters are received * 0b01..Becomes 1 when idle for timeout bit clocks * 0b10..Becomes 1 when idle for timeout bit clocks following the next character * 0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached */ #define LPUART_TIMEOUT_CFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK) /*! @} */ /* The count of LPUART_TIMEOUT */ #define LPUART_TIMEOUT_COUNT (4U) /*! @name TCBR - Transmit Command Burst */ /*! @{ */ #define LPUART_TCBR_DATA_MASK (0xFFFFU) #define LPUART_TCBR_DATA_SHIFT (0U) /*! DATA - Data */ #define LPUART_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK) /*! @} */ /* The count of LPUART_TCBR */ #define LPUART_TCBR_COUNT (128U) /*! @name TDBR - Transmit Data Burst */ /*! @{ */ #define LPUART_TDBR_DATA0_MASK (0xFFU) #define LPUART_TDBR_DATA0_SHIFT (0U) /*! DATA0 - Data0 */ #define LPUART_TDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK) #define LPUART_TDBR_DATA1_MASK (0xFF00U) #define LPUART_TDBR_DATA1_SHIFT (8U) /*! DATA1 - Data1 */ #define LPUART_TDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK) #define LPUART_TDBR_DATA2_MASK (0xFF0000U) #define LPUART_TDBR_DATA2_SHIFT (16U) /*! DATA2 - Data2 */ #define LPUART_TDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK) #define LPUART_TDBR_DATA3_MASK (0xFF000000U) #define LPUART_TDBR_DATA3_SHIFT (24U) /*! DATA3 - Data3 */ #define LPUART_TDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK) /*! @} */ /* The count of LPUART_TDBR */ #define LPUART_TDBR_COUNT (256U) /*! * @} */ /* end of group LPUART_Register_Masks */ /* LPUART - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral LPUART0 base address */ #define LPUART0_BASE (0x50092000u) /** Peripheral LPUART0 base address */ #define LPUART0_BASE_NS (0x40092000u) /** Peripheral LPUART0 base pointer */ #define LPUART0 ((LPUART_Type *)LPUART0_BASE) /** Peripheral LPUART0 base pointer */ #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) /** Peripheral LPUART1 base address */ #define LPUART1_BASE (0x50093000u) /** Peripheral LPUART1 base address */ #define LPUART1_BASE_NS (0x40093000u) /** Peripheral LPUART1 base pointer */ #define LPUART1 ((LPUART_Type *)LPUART1_BASE) /** Peripheral LPUART1 base pointer */ #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) /** Peripheral LPUART2 base address */ #define LPUART2_BASE (0x50094000u) /** Peripheral LPUART2 base address */ #define LPUART2_BASE_NS (0x40094000u) /** Peripheral LPUART2 base pointer */ #define LPUART2 ((LPUART_Type *)LPUART2_BASE) /** Peripheral LPUART2 base pointer */ #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) /** Peripheral LPUART3 base address */ #define LPUART3_BASE (0x50095000u) /** Peripheral LPUART3 base address */ #define LPUART3_BASE_NS (0x40095000u) /** Peripheral LPUART3 base pointer */ #define LPUART3 ((LPUART_Type *)LPUART3_BASE) /** Peripheral LPUART3 base pointer */ #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) /** Peripheral LPUART4 base address */ #define LPUART4_BASE (0x500B4000u) /** Peripheral LPUART4 base address */ #define LPUART4_BASE_NS (0x400B4000u) /** Peripheral LPUART4 base pointer */ #define LPUART4 ((LPUART_Type *)LPUART4_BASE) /** Peripheral LPUART4 base pointer */ #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) /** Peripheral LPUART5 base address */ #define LPUART5_BASE (0x500B5000u) /** Peripheral LPUART5 base address */ #define LPUART5_BASE_NS (0x400B5000u) /** Peripheral LPUART5 base pointer */ #define LPUART5 ((LPUART_Type *)LPUART5_BASE) /** Peripheral LPUART5 base pointer */ #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) /** Peripheral LPUART6 base address */ #define LPUART6_BASE (0x500B6000u) /** Peripheral LPUART6 base address */ #define LPUART6_BASE_NS (0x400B6000u) /** Peripheral LPUART6 base pointer */ #define LPUART6 ((LPUART_Type *)LPUART6_BASE) /** Peripheral LPUART6 base pointer */ #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) /** Peripheral LPUART7 base address */ #define LPUART7_BASE (0x500B7000u) /** Peripheral LPUART7 base address */ #define LPUART7_BASE_NS (0x400B7000u) /** Peripheral LPUART7 base pointer */ #define LPUART7 ((LPUART_Type *)LPUART7_BASE) /** Peripheral LPUART7 base pointer */ #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) /** Peripheral LPUART8 base address */ #define LPUART8_BASE (0x500B8000u) /** Peripheral LPUART8 base address */ #define LPUART8_BASE_NS (0x400B8000u) /** Peripheral LPUART8 base pointer */ #define LPUART8 ((LPUART_Type *)LPUART8_BASE) /** Peripheral LPUART8 base pointer */ #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) /** Peripheral LPUART9 base address */ #define LPUART9_BASE (0x500B9000u) /** Peripheral LPUART9 base address */ #define LPUART9_BASE_NS (0x400B9000u) /** Peripheral LPUART9 base pointer */ #define LPUART9 ((LPUART_Type *)LPUART9_BASE) /** Peripheral LPUART9 base pointer */ #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) /** Array initializer of LPUART peripheral base addresses */ #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } /** Array initializer of LPUART peripheral base addresses */ #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } #else /** Peripheral LPUART0 base address */ #define LPUART0_BASE (0x40092000u) /** Peripheral LPUART0 base pointer */ #define LPUART0 ((LPUART_Type *)LPUART0_BASE) /** Peripheral LPUART1 base address */ #define LPUART1_BASE (0x40093000u) /** Peripheral LPUART1 base pointer */ #define LPUART1 ((LPUART_Type *)LPUART1_BASE) /** Peripheral LPUART2 base address */ #define LPUART2_BASE (0x40094000u) /** Peripheral LPUART2 base pointer */ #define LPUART2 ((LPUART_Type *)LPUART2_BASE) /** Peripheral LPUART3 base address */ #define LPUART3_BASE (0x40095000u) /** Peripheral LPUART3 base pointer */ #define LPUART3 ((LPUART_Type *)LPUART3_BASE) /** Peripheral LPUART4 base address */ #define LPUART4_BASE (0x400B4000u) /** Peripheral LPUART4 base pointer */ #define LPUART4 ((LPUART_Type *)LPUART4_BASE) /** Peripheral LPUART5 base address */ #define LPUART5_BASE (0x400B5000u) /** Peripheral LPUART5 base pointer */ #define LPUART5 ((LPUART_Type *)LPUART5_BASE) /** Peripheral LPUART6 base address */ #define LPUART6_BASE (0x400B6000u) /** Peripheral LPUART6 base pointer */ #define LPUART6 ((LPUART_Type *)LPUART6_BASE) /** Peripheral LPUART7 base address */ #define LPUART7_BASE (0x400B7000u) /** Peripheral LPUART7 base pointer */ #define LPUART7 ((LPUART_Type *)LPUART7_BASE) /** Peripheral LPUART8 base address */ #define LPUART8_BASE (0x400B8000u) /** Peripheral LPUART8 base pointer */ #define LPUART8 ((LPUART_Type *)LPUART8_BASE) /** Peripheral LPUART9 base address */ #define LPUART9_BASE (0x400B9000u) /** Peripheral LPUART9 base pointer */ #define LPUART9 ((LPUART_Type *)LPUART9_BASE) /** Array initializer of LPUART peripheral base addresses */ #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } #endif /** Interrupt vectors for the LPUART peripheral type */ #define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } #define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } /*! * @} */ /* end of group LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LP_FLEXCOMM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LP_FLEXCOMM_Peripheral_Access_Layer LP_FLEXCOMM Peripheral Access Layer * @{ */ /** LP_FLEXCOMM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4084]; __I uint32_t ISTAT; /**< Interrupt Status, offset: 0xFF4 */ __IO uint32_t PSELID; /**< Peripheral Select and ID, offset: 0xFF8 */ } LP_FLEXCOMM_Type; /* ---------------------------------------------------------------------------- -- LP_FLEXCOMM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LP_FLEXCOMM_Register_Masks LP_FLEXCOMM Register Masks * @{ */ /*! @name ISTAT - Interrupt Status */ /*! @{ */ #define LP_FLEXCOMM_ISTAT_UARTTX_MASK (0x1U) #define LP_FLEXCOMM_ISTAT_UARTTX_SHIFT (0U) /*! UARTTX - UART TX Interrupt * 0b0..Clear * 0b1..Set */ #define LP_FLEXCOMM_ISTAT_UARTTX(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTTX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTTX_MASK) #define LP_FLEXCOMM_ISTAT_UARTRX_MASK (0x2U) #define LP_FLEXCOMM_ISTAT_UARTRX_SHIFT (1U) /*! UARTRX - UART RX Interrupt * 0b0..Clear * 0b1..Set */ #define LP_FLEXCOMM_ISTAT_UARTRX(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTRX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTRX_MASK) #define LP_FLEXCOMM_ISTAT_SPI_MASK (0x4U) #define LP_FLEXCOMM_ISTAT_SPI_SHIFT (2U) /*! SPI - SPI Interrupt * 0b0..Clear * 0b1..Set */ #define LP_FLEXCOMM_ISTAT_SPI(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_SPI_SHIFT)) & LP_FLEXCOMM_ISTAT_SPI_MASK) #define LP_FLEXCOMM_ISTAT_I2CM_MASK (0x10U) #define LP_FLEXCOMM_ISTAT_I2CM_SHIFT (4U) /*! I2CM - I2C Controller Interrupt * 0b0..Clear * 0b1..Set */ #define LP_FLEXCOMM_ISTAT_I2CM(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CM_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CM_MASK) #define LP_FLEXCOMM_ISTAT_I2CS_MASK (0x20U) #define LP_FLEXCOMM_ISTAT_I2CS_SHIFT (5U) /*! I2CS - I2C Subordinate Interrupt * 0b0..Clear * 0b1..Set */ #define LP_FLEXCOMM_ISTAT_I2CS(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CS_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CS_MASK) /*! @} */ /*! @name PSELID - Peripheral Select and ID */ /*! @{ */ #define LP_FLEXCOMM_PSELID_PERSEL_MASK (0x7U) #define LP_FLEXCOMM_PSELID_PERSEL_SHIFT (0U) /*! PERSEL - Peripheral Select * 0b000..No peripheral selected * 0b001..UART * 0b011..I2C * 0b111..UART and I2C * 0b010..SPI */ #define LP_FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_PERSEL_SHIFT)) & LP_FLEXCOMM_PSELID_PERSEL_MASK) #define LP_FLEXCOMM_PSELID_LOCK_MASK (0x8U) #define LP_FLEXCOMM_PSELID_LOCK_SHIFT (3U) /*! LOCK - Lock * 0b0..PERSEL is writable * 0b1..PERSEL is not writable */ #define LP_FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_LOCK_SHIFT)) & LP_FLEXCOMM_PSELID_LOCK_MASK) #define LP_FLEXCOMM_PSELID_UARTPRESENT_MASK (0x10U) #define LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT (4U) /*! UARTPRESENT - UART Present * 0b0..Not supported * 0b1..Supported */ #define LP_FLEXCOMM_PSELID_UARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_UARTPRESENT_MASK) #define LP_FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) #define LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) /*! SPIPRESENT - SPI Present * 0b0..Not supported * 0b1..Supported */ #define LP_FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_SPIPRESENT_MASK) #define LP_FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) #define LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) /*! I2CPRESENT - I2C Present * 0b0..Not supported * 0b1..Supported */ #define LP_FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_I2CPRESENT_MASK) #define LP_FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) #define LP_FLEXCOMM_PSELID_ID_SHIFT (12U) /*! ID - LP_FLEXCOMM interface ID */ #define LP_FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_ID_SHIFT)) & LP_FLEXCOMM_PSELID_ID_MASK) /*! @} */ /*! * @} */ /* end of group LP_FLEXCOMM_Register_Masks */ /* LP_FLEXCOMM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral LP_FLEXCOMM0 base address */ #define LP_FLEXCOMM0_BASE (0x50092000u) /** Peripheral LP_FLEXCOMM0 base address */ #define LP_FLEXCOMM0_BASE_NS (0x40092000u) /** Peripheral LP_FLEXCOMM0 base pointer */ #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) /** Peripheral LP_FLEXCOMM0 base pointer */ #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) /** Peripheral LP_FLEXCOMM1 base address */ #define LP_FLEXCOMM1_BASE (0x50093000u) /** Peripheral LP_FLEXCOMM1 base address */ #define LP_FLEXCOMM1_BASE_NS (0x40093000u) /** Peripheral LP_FLEXCOMM1 base pointer */ #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) /** Peripheral LP_FLEXCOMM1 base pointer */ #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) /** Peripheral LP_FLEXCOMM2 base address */ #define LP_FLEXCOMM2_BASE (0x50094000u) /** Peripheral LP_FLEXCOMM2 base address */ #define LP_FLEXCOMM2_BASE_NS (0x40094000u) /** Peripheral LP_FLEXCOMM2 base pointer */ #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) /** Peripheral LP_FLEXCOMM2 base pointer */ #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) /** Peripheral LP_FLEXCOMM3 base address */ #define LP_FLEXCOMM3_BASE (0x50095000u) /** Peripheral LP_FLEXCOMM3 base address */ #define LP_FLEXCOMM3_BASE_NS (0x40095000u) /** Peripheral LP_FLEXCOMM3 base pointer */ #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) /** Peripheral LP_FLEXCOMM3 base pointer */ #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) /** Peripheral LP_FLEXCOMM4 base address */ #define LP_FLEXCOMM4_BASE (0x500B4000u) /** Peripheral LP_FLEXCOMM4 base address */ #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) /** Peripheral LP_FLEXCOMM4 base pointer */ #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) /** Peripheral LP_FLEXCOMM4 base pointer */ #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) /** Peripheral LP_FLEXCOMM5 base address */ #define LP_FLEXCOMM5_BASE (0x500B5000u) /** Peripheral LP_FLEXCOMM5 base address */ #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) /** Peripheral LP_FLEXCOMM5 base pointer */ #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) /** Peripheral LP_FLEXCOMM5 base pointer */ #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) /** Peripheral LP_FLEXCOMM6 base address */ #define LP_FLEXCOMM6_BASE (0x500B6000u) /** Peripheral LP_FLEXCOMM6 base address */ #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) /** Peripheral LP_FLEXCOMM6 base pointer */ #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) /** Peripheral LP_FLEXCOMM6 base pointer */ #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) /** Peripheral LP_FLEXCOMM7 base address */ #define LP_FLEXCOMM7_BASE (0x500B7000u) /** Peripheral LP_FLEXCOMM7 base address */ #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) /** Peripheral LP_FLEXCOMM7 base pointer */ #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) /** Peripheral LP_FLEXCOMM7 base pointer */ #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) /** Peripheral LP_FLEXCOMM8 base address */ #define LP_FLEXCOMM8_BASE (0x500B8000u) /** Peripheral LP_FLEXCOMM8 base address */ #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) /** Peripheral LP_FLEXCOMM8 base pointer */ #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) /** Peripheral LP_FLEXCOMM8 base pointer */ #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) /** Peripheral LP_FLEXCOMM9 base address */ #define LP_FLEXCOMM9_BASE (0x500B9000u) /** Peripheral LP_FLEXCOMM9 base address */ #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) /** Peripheral LP_FLEXCOMM9 base pointer */ #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) /** Peripheral LP_FLEXCOMM9 base pointer */ #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) /** Array initializer of LP_FLEXCOMM peripheral base addresses */ #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } /** Array initializer of LP_FLEXCOMM peripheral base pointers */ #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } /** Array initializer of LP_FLEXCOMM peripheral base addresses */ #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } /** Array initializer of LP_FLEXCOMM peripheral base pointers */ #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } #else /** Peripheral LP_FLEXCOMM0 base address */ #define LP_FLEXCOMM0_BASE (0x40092000u) /** Peripheral LP_FLEXCOMM0 base pointer */ #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) /** Peripheral LP_FLEXCOMM1 base address */ #define LP_FLEXCOMM1_BASE (0x40093000u) /** Peripheral LP_FLEXCOMM1 base pointer */ #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) /** Peripheral LP_FLEXCOMM2 base address */ #define LP_FLEXCOMM2_BASE (0x40094000u) /** Peripheral LP_FLEXCOMM2 base pointer */ #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) /** Peripheral LP_FLEXCOMM3 base address */ #define LP_FLEXCOMM3_BASE (0x40095000u) /** Peripheral LP_FLEXCOMM3 base pointer */ #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) /** Peripheral LP_FLEXCOMM4 base address */ #define LP_FLEXCOMM4_BASE (0x400B4000u) /** Peripheral LP_FLEXCOMM4 base pointer */ #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) /** Peripheral LP_FLEXCOMM5 base address */ #define LP_FLEXCOMM5_BASE (0x400B5000u) /** Peripheral LP_FLEXCOMM5 base pointer */ #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) /** Peripheral LP_FLEXCOMM6 base address */ #define LP_FLEXCOMM6_BASE (0x400B6000u) /** Peripheral LP_FLEXCOMM6 base pointer */ #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) /** Peripheral LP_FLEXCOMM7 base address */ #define LP_FLEXCOMM7_BASE (0x400B7000u) /** Peripheral LP_FLEXCOMM7 base pointer */ #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) /** Peripheral LP_FLEXCOMM8 base address */ #define LP_FLEXCOMM8_BASE (0x400B8000u) /** Peripheral LP_FLEXCOMM8 base pointer */ #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) /** Peripheral LP_FLEXCOMM9 base address */ #define LP_FLEXCOMM9_BASE (0x400B9000u) /** Peripheral LP_FLEXCOMM9 base pointer */ #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) /** Array initializer of LP_FLEXCOMM peripheral base addresses */ #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } /** Array initializer of LP_FLEXCOMM peripheral base pointers */ #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } #endif /** Interrupt vectors for the LP_FLEXCOMM peripheral type */ #define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } /*! * @} */ /* end of group LP_FLEXCOMM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MAILBOX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer * @{ */ /** MAILBOX - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10 */ __IO uint32_t IRQ; /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1) Interrupt, array offset: 0x0, array step: 0x10 */ __O uint32_t IRQSET; /**< Cortex-M33 (CPU0) Interrupt Set..CoolFlux (CPU1) Interrupt Set, array offset: 0x4, array step: 0x10 */ __O uint32_t IRQCLR; /**< Cortex-M33 (CPU0) Interrupt Clear..CoolFlux (CPU1) Interrupt Clear, array offset: 0x8, array step: 0x10 */ uint8_t RESERVED_0[4]; } MBOXIRQ[2]; uint8_t RESERVED_0[216]; __IO uint32_t MUTEX; /**< Mutual Exclusion, offset: 0xF8 */ } MAILBOX_Type; /* ---------------------------------------------------------------------------- -- MAILBOX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks * @{ */ /*! @name MBOXIRQ_IRQ - Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1) Interrupt */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) /*! INTREQ - Interrupt Request */ #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) /*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQ */ #define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) /*! @name MBOXIRQ_IRQSET - Cortex-M33 (CPU0) Interrupt Set..CoolFlux (CPU1) Interrupt Set */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) /*! INTREQSET - Interrupt Request Set 1 */ #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) /*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQSET */ #define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) /*! @name MBOXIRQ_IRQCLR - Cortex-M33 (CPU0) Interrupt Clear..CoolFlux (CPU1) Interrupt Clear */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) /*! INTREQCLR - Interrupt Request Clear 1 */ #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) /*! @} */ /* The count of MAILBOX_MBOXIRQ_IRQCLR */ #define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) /*! @name MUTEX - Mutual Exclusion */ /*! @{ */ #define MAILBOX_MUTEX_EX_MASK (0x1U) #define MAILBOX_MUTEX_EX_SHIFT (0U) /*! EX - Mutual Exclusion Request * 0b0..Resource unavailable * 0b1..Resource available */ #define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) /*! @} */ /*! * @} */ /* end of group MAILBOX_Register_Masks */ /* MAILBOX - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral MAILBOX base address */ #define MAILBOX_BASE (0x500B2000u) /** Peripheral MAILBOX base address */ #define MAILBOX_BASE_NS (0x400B2000u) /** Peripheral MAILBOX base pointer */ #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) /** Peripheral MAILBOX base pointer */ #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) /** Array initializer of MAILBOX peripheral base addresses */ #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } /** Array initializer of MAILBOX peripheral base pointers */ #define MAILBOX_BASE_PTRS { MAILBOX } /** Array initializer of MAILBOX peripheral base addresses */ #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } /** Array initializer of MAILBOX peripheral base pointers */ #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } #else /** Peripheral MAILBOX base address */ #define MAILBOX_BASE (0x400B2000u) /** Peripheral MAILBOX base pointer */ #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) /** Array initializer of MAILBOX peripheral base addresses */ #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } /** Array initializer of MAILBOX peripheral base pointers */ #define MAILBOX_BASE_PTRS { MAILBOX } #endif /*! * @} */ /* end of group MAILBOX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MRT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer * @{ */ /** MRT - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10 */ __IO uint32_t INTVAL; /**< Time Interval Value, array offset: 0x0, array step: 0x10 */ __I uint32_t TIMER; /**< Timer, array offset: 0x4, array step: 0x10 */ __IO uint32_t CTRL; /**< Control, array offset: 0x8, array step: 0x10 */ __IO uint32_t STAT; /**< Status, array offset: 0xC, array step: 0x10 */ } CHANNEL[4]; uint8_t RESERVED_0[176]; __IO uint32_t MODCFG; /**< Module Configuration, offset: 0xF0 */ __I uint32_t IDLE_CH; /**< Idle Channel, offset: 0xF4 */ __IO uint32_t IRQ_FLAG; /**< Global Interrupt Flag, offset: 0xF8 */ } MRT_Type; /* ---------------------------------------------------------------------------- -- MRT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MRT_Register_Masks MRT Register Masks * @{ */ /*! @name CHANNEL_INTVAL - Time Interval Value */ /*! @{ */ #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) /*! IVALUE - Time Interval Load Value. */ #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) /*! LOAD - Force Load Enable * 0b0..No force load * 0b1..Force load */ #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) /*! @} */ /* The count of MRT_CHANNEL_INTVAL */ #define MRT_CHANNEL_INTVAL_COUNT (4U) /*! @name CHANNEL_TIMER - Timer */ /*! @{ */ #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) /*! VALUE - Current Timer Value */ #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) /*! @} */ /* The count of MRT_CHANNEL_TIMER */ #define MRT_CHANNEL_TIMER_COUNT (4U) /*! @name CHANNEL_CTRL - Control */ /*! @{ */ #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) /*! INTEN - Interrupt request * 0b0..Disabled * 0b1..Enabled */ #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) /*! MODE - MRT Operating mode * 0b00..Repeat Interrupt mode * 0b01..One-Shot Interrupt mode * 0b10..One-Shot Stall mode * 0b11..Reserved */ #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) /*! @} */ /* The count of MRT_CHANNEL_CTRL */ #define MRT_CHANNEL_CTRL_COUNT (4U) /*! @name CHANNEL_STAT - Status */ /*! @{ */ #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) /*! INTFLAG - Interrupt Flag * 0b0..No pending interrupt. * 0b1..Pending interrupt. */ #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) /*! RUN - Timer n State * 0b0..Idle state. * 0b1..Running. */ #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) /*! INUSE - Channel-In-Use flag * 0b0..This timer channel is not in use. * 0b1..This timer channel is in use. */ #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) /*! @} */ /* The count of MRT_CHANNEL_STAT */ #define MRT_CHANNEL_STAT_COUNT (4U) /*! @name MODCFG - Module Configuration */ /*! @{ */ #define MRT_MODCFG_NOC_MASK (0xFU) #define MRT_MODCFG_NOC_SHIFT (0U) /*! NOC - Number of Channels */ #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) #define MRT_MODCFG_NOB_MASK (0x1F0U) #define MRT_MODCFG_NOB_SHIFT (4U) /*! NOB - Number of Bits */ #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) #define MRT_MODCFG_MULTITASK_SHIFT (31U) /*! MULTITASK - MULTITASK * 0b0..Hardware status mode. * 0b1..Multitask mode */ #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) /*! @} */ /*! @name IDLE_CH - Idle Channel */ /*! @{ */ #define MRT_IDLE_CH_CHAN_MASK (0xF0U) #define MRT_IDLE_CH_CHAN_SHIFT (4U) /*! CHAN - Idle Channel */ #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) /*! @} */ /*! @name IRQ_FLAG - Global Interrupt Flag */ /*! @{ */ #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) /*! GFLAG0 - Interrupt Flag * 0b0..No pending interrupt. * 0b1..Pending interrupt */ #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) /*! GFLAG1 - Interrupt Flag */ #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) /*! GFLAG2 - Interrupt Flag */ #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) /*! GFLAG3 - Interrupt Flag */ #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) /*! @} */ /*! * @} */ /* end of group MRT_Register_Masks */ /* MRT - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral MRT0 base address */ #define MRT0_BASE (0x50013000u) /** Peripheral MRT0 base address */ #define MRT0_BASE_NS (0x40013000u) /** Peripheral MRT0 base pointer */ #define MRT0 ((MRT_Type *)MRT0_BASE) /** Peripheral MRT0 base pointer */ #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) /** Array initializer of MRT peripheral base addresses */ #define MRT_BASE_ADDRS { MRT0_BASE } /** Array initializer of MRT peripheral base pointers */ #define MRT_BASE_PTRS { MRT0 } /** Array initializer of MRT peripheral base addresses */ #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } /** Array initializer of MRT peripheral base pointers */ #define MRT_BASE_PTRS_NS { MRT0_NS } #else /** Peripheral MRT0 base address */ #define MRT0_BASE (0x40013000u) /** Peripheral MRT0 base pointer */ #define MRT0 ((MRT_Type *)MRT0_BASE) /** Array initializer of MRT peripheral base addresses */ #define MRT_BASE_ADDRS { MRT0_BASE } /** Array initializer of MRT peripheral base pointers */ #define MRT_BASE_PTRS { MRT0 } #endif /** Interrupt vectors for the MRT peripheral type */ #define MRT_IRQS { MRT0_IRQn } /*! * @} */ /* end of group MRT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NPX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NPX_Peripheral_Access_Layer NPX Peripheral Access Layer * @{ */ /** NPX - Register Layout Typedef */ typedef struct { __IO uint32_t NPXCR; /**< NPX Control Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __I uint32_t NPXSR; /**< NPX Status Register, offset: 0x8 */ uint8_t RESERVED_1[4]; __O uint32_t CACMSK; /**< Flash Cache Obfuscation Mask, offset: 0x10 */ uint8_t RESERVED_2[12]; __IO uint32_t REMAP; /**< Data Remap, offset: 0x20 */ uint8_t RESERVED_3[28]; struct { /* offset: 0x40, array step: 0x10 */ __IO uint32_t VMAPCTX_WD[2]; /**< Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3, array offset: 0x40, array step: index*0x10, index2*0x4 */ __O uint32_t BIVCTX_WD[2]; /**< Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3, array offset: 0x48, array step: index*0x10, index2*0x4 */ } CTX_VALID_IV_ARRAY[4]; } NPX_Type; /* ---------------------------------------------------------------------------- -- NPX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NPX_Register_Masks NPX Register Masks * @{ */ /*! @name NPXCR - NPX Control Register */ /*! @{ */ #define NPX_NPXCR_GEE_MASK (0x1U) #define NPX_NPXCR_GEE_SHIFT (0U) /*! GEE - Global Encryption Enable * 0b1..Global encryption enabled. NPX on-the-fly encryption is enabled if the flash access hits in a valid * memory context. Subsequent reads return 1. * 0b0..Global encryption disabled. NPX on-the-fly encryption is disabled. Subsequent reads return 0. */ #define NPX_NPXCR_GEE(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GEE_SHIFT)) & NPX_NPXCR_GEE_MASK) #define NPX_NPXCR_GDE_MASK (0x4U) #define NPX_NPXCR_GDE_SHIFT (2U) /*! GDE - Global Decryption Enable * 0b1..Global decryption enabled. NPX on-the-fly decryption is globally enabled. Subsequent reads return 1. * 0b0..Global decryption disabled. NPX on-the-fly decryption is globally disabled. Subsequent reads return 0. */ #define NPX_NPXCR_GDE(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GDE_SHIFT)) & NPX_NPXCR_GDE_MASK) #define NPX_NPXCR_GLK_MASK (0x10U) #define NPX_NPXCR_GLK_SHIFT (4U) /*! GLK - Global Lock Enable * 0b1..Lock enabled: cannot write to VMAPCTXn, NPXCR, or CACMSK. Subsequent reads return 1. * 0b0..Lock disabled. Subsequent reads return 0. */ #define NPX_NPXCR_GLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GLK_SHIFT)) & NPX_NPXCR_GLK_MASK) #define NPX_NPXCR_MLK_MASK (0x40U) #define NPX_NPXCR_MLK_SHIFT (6U) /*! MLK - Mask Lock Enable * 0b1..Lock enabled: cannot write to mask. Subsequent reads return 1. * 0b0..Lock disabled. Subsequent reads return 0. */ #define NPX_NPXCR_MLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_MLK_SHIFT)) & NPX_NPXCR_MLK_MASK) #define NPX_NPXCR_CTX0LK_MASK (0x100U) #define NPX_NPXCR_CTX0LK_SHIFT (8U) /*! CTX0LK - Lock Enable for Context 0 * 0b1..Lock enabled: cannot write to VMAPCTX0 (becomes read-only) * 0b0..Lock disabled: VMAPCTX0 remains read-write */ #define NPX_NPXCR_CTX0LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX0LK_SHIFT)) & NPX_NPXCR_CTX0LK_MASK) #define NPX_NPXCR_CTX1LK_MASK (0x400U) #define NPX_NPXCR_CTX1LK_SHIFT (10U) /*! CTX1LK - Lock Enable for Context 1 * 0b1..Lock enabled: cannot write to VMAPCTX1 (becomes read-only) * 0b0..Lock disabled: VMAPCTX1 remains read-write */ #define NPX_NPXCR_CTX1LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX1LK_SHIFT)) & NPX_NPXCR_CTX1LK_MASK) #define NPX_NPXCR_CTX2LK_MASK (0x1000U) #define NPX_NPXCR_CTX2LK_SHIFT (12U) /*! CTX2LK - Lock Enable for Context 2 * 0b1..Lock enabled: cannot write to VMAPCTX2 (becomes read-only) * 0b0..Lock disabled: VMAPCTX2 remains read-write */ #define NPX_NPXCR_CTX2LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX2LK_SHIFT)) & NPX_NPXCR_CTX2LK_MASK) #define NPX_NPXCR_CTX3LK_MASK (0x4000U) #define NPX_NPXCR_CTX3LK_SHIFT (14U) /*! CTX3LK - Lock Enable for Context 3 * 0b1..Lock enabled: cannot write to VMAPCTX3 (becomes read-only) * 0b0..Lock disabled: VMAPCTX3 remains read-write */ #define NPX_NPXCR_CTX3LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX3LK_SHIFT)) & NPX_NPXCR_CTX3LK_MASK) /*! @} */ /*! @name NPXSR - NPX Status Register */ /*! @{ */ #define NPX_NPXSR_NUMCTX_MASK (0xFU) #define NPX_NPXSR_NUMCTX_SHIFT (0U) /*! NUMCTX - Number of implemented memory contexts * 0b0000..No (zero) implemented memory contexts * 0b0001..1 implemented memory contexts * 0b0010..2 implemented memory contexts * 0b0011..3 implemented memory contexts * 0b0100..4 implemented memory contexts */ #define NPX_NPXSR_NUMCTX(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_NUMCTX_SHIFT)) & NPX_NPXSR_NUMCTX_MASK) #define NPX_NPXSR_V0_MASK (0x100U) #define NPX_NPXSR_V0_SHIFT (8U) /*! V0 - Key n Valid * 0b0..Not valid * 0b1..Valid */ #define NPX_NPXSR_V0(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V0_SHIFT)) & NPX_NPXSR_V0_MASK) #define NPX_NPXSR_V1_MASK (0x200U) #define NPX_NPXSR_V1_SHIFT (9U) /*! V1 - Key n Valid * 0b0..Not valid * 0b1..Valid */ #define NPX_NPXSR_V1(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V1_SHIFT)) & NPX_NPXSR_V1_MASK) #define NPX_NPXSR_V2_MASK (0x400U) #define NPX_NPXSR_V2_SHIFT (10U) /*! V2 - Key n Valid * 0b0..Not valid * 0b1..Valid */ #define NPX_NPXSR_V2(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V2_SHIFT)) & NPX_NPXSR_V2_MASK) #define NPX_NPXSR_V3_MASK (0x800U) #define NPX_NPXSR_V3_SHIFT (11U) /*! V3 - Key n Valid * 0b0..Not valid * 0b1..Valid */ #define NPX_NPXSR_V3(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V3_SHIFT)) & NPX_NPXSR_V3_MASK) /*! @} */ /*! @name CACMSK - Flash Cache Obfuscation Mask */ /*! @{ */ #define NPX_CACMSK_OBMASK_MASK (0xFFFFFFFFU) #define NPX_CACMSK_OBMASK_SHIFT (0U) /*! OBMASK - Obfuscation Mask */ #define NPX_CACMSK_OBMASK(x) (((uint32_t)(((uint32_t)(x)) << NPX_CACMSK_OBMASK_SHIFT)) & NPX_CACMSK_OBMASK_MASK) /*! @} */ /*! @name REMAP - Data Remap */ /*! @{ */ #define NPX_REMAP_REMAPLK_MASK (0x1U) #define NPX_REMAP_REMAPLK_SHIFT (0U) /*! REMAPLK - Remap Lock Enable * 0b1..Lock enabled: cannot write to REMAP * 0b0..Lock disabled: can write to REMAP */ #define NPX_REMAP_REMAPLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_REMAPLK_SHIFT)) & NPX_REMAP_REMAPLK_MASK) #define NPX_REMAP_LIM_MASK (0x1F0000U) #define NPX_REMAP_LIM_SHIFT (16U) /*! LIM - LIM Remapping Address */ #define NPX_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIM_SHIFT)) & NPX_REMAP_LIM_MASK) #define NPX_REMAP_LIMDP_MASK (0x1F000000U) #define NPX_REMAP_LIMDP_SHIFT (24U) /*! LIMDP - LIMDP Remapping Address */ #define NPX_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIMDP_SHIFT)) & NPX_REMAP_LIMDP_MASK) /*! @} */ /*! @name CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD - Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3 */ /*! @{ */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK (0x1U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT (0U) /*! VAL0 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK (0x1U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT (0U) /*! VAL32 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK (0x2U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT (1U) /*! VAL1 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK (0x2U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT (1U) /*! VAL33 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK (0x4U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT (2U) /*! VAL2 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK (0x4U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT (2U) /*! VAL34 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK (0x8U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT (3U) /*! VAL3 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK (0x8U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT (3U) /*! VAL35 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK (0x10U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT (4U) /*! VAL4 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK (0x10U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT (4U) /*! VAL36 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK (0x20U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT (5U) /*! VAL5 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK (0x20U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT (5U) /*! VAL37 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK (0x40U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT (6U) /*! VAL6 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK (0x40U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT (6U) /*! VAL38 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK (0x80U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT (7U) /*! VAL7 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK (0x80U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT (7U) /*! VAL39 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK (0x100U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT (8U) /*! VAL8 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK (0x100U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT (8U) /*! VAL40 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK (0x200U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT (9U) /*! VAL9 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK (0x200U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT (9U) /*! VAL41 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK (0x400U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT (10U) /*! VAL10 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK (0x400U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT (10U) /*! VAL42 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK (0x800U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT (11U) /*! VAL11 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK (0x800U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT (11U) /*! VAL43 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK (0x1000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT (12U) /*! VAL12 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK (0x1000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT (12U) /*! VAL44 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK (0x2000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT (13U) /*! VAL13 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK (0x2000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT (13U) /*! VAL45 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK (0x4000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT (14U) /*! VAL14 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK (0x4000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT (14U) /*! VAL46 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK (0x8000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT (15U) /*! VAL15 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK (0x8000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT (15U) /*! VAL47 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK (0x10000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT (16U) /*! VAL16 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK (0x10000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT (16U) /*! VAL48 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK (0x20000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT (17U) /*! VAL17 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK (0x20000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT (17U) /*! VAL49 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK (0x40000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT (18U) /*! VAL18 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK (0x40000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT (18U) /*! VAL50 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK (0x80000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT (19U) /*! VAL19 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK (0x80000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT (19U) /*! VAL51 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK (0x100000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT (20U) /*! VAL20 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK (0x100000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT (20U) /*! VAL52 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK (0x200000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT (21U) /*! VAL21 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK (0x200000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT (21U) /*! VAL53 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK (0x400000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT (22U) /*! VAL22 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK (0x400000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT (22U) /*! VAL54 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK (0x800000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT (23U) /*! VAL23 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK (0x800000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT (23U) /*! VAL55 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK (0x1000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT (24U) /*! VAL24 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK (0x1000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT (24U) /*! VAL56 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK (0x2000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT (25U) /*! VAL25 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK (0x2000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT (25U) /*! VAL57 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK (0x4000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT (26U) /*! VAL26 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK (0x4000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT (26U) /*! VAL58 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK (0x8000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT (27U) /*! VAL27 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK (0x8000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT (27U) /*! VAL59 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK (0x10000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT (28U) /*! VAL28 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK (0x10000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT (28U) /*! VAL60 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK (0x20000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT (29U) /*! VAL29 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK (0x20000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT (29U) /*! VAL61 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK (0x40000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT (30U) /*! VAL30 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK (0x40000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT (30U) /*! VAL62 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK (0x80000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT (31U) /*! VAL31 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK (0x80000000U) #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT (31U) /*! VAL63 - Block valid enable for encryption/decryption * 0b0..Disable * 0b1..Enable */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK) /*! @} */ /* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT (4U) /* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */ #define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT2 (2U) /*! @name CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD - Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3 */ /*! @{ */ #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK (0xFFFFFFFFU) #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT (0U) /*! BIV_WD0 - Block Initial Vector Word0 */ #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK) #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK (0xFFFFFFFFU) #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT (0U) /*! BIV_WD1 - Block Initial Vector Word1 */ #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK) /*! @} */ /* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */ #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT (4U) /* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */ #define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT2 (2U) /*! * @} */ /* end of group NPX_Register_Masks */ /* NPX - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral NPX0 base address */ #define NPX0_BASE (0x500CC000u) /** Peripheral NPX0 base address */ #define NPX0_BASE_NS (0x400CC000u) /** Peripheral NPX0 base pointer */ #define NPX0 ((NPX_Type *)NPX0_BASE) /** Peripheral NPX0 base pointer */ #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) /** Array initializer of NPX peripheral base addresses */ #define NPX_BASE_ADDRS { NPX0_BASE } /** Array initializer of NPX peripheral base pointers */ #define NPX_BASE_PTRS { NPX0 } /** Array initializer of NPX peripheral base addresses */ #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } /** Array initializer of NPX peripheral base pointers */ #define NPX_BASE_PTRS_NS { NPX0_NS } #else /** Peripheral NPX0 base address */ #define NPX0_BASE (0x400CC000u) /** Peripheral NPX0 base pointer */ #define NPX0 ((NPX_Type *)NPX0_BASE) /** Array initializer of NPX peripheral base addresses */ #define NPX_BASE_ADDRS { NPX0_BASE } /** Array initializer of NPX peripheral base pointers */ #define NPX_BASE_PTRS { NPX0 } #endif /*! * @} */ /* end of group NPX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OPAMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OPAMP_Peripheral_Access_Layer OPAMP Peripheral Access Layer * @{ */ /** OPAMP - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t OPAMP_CTR; /**< OPAMP Control, offset: 0x8 */ } OPAMP_Type; /* ---------------------------------------------------------------------------- -- OPAMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OPAMP_Register_Masks OPAMP Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define OPAMP_VERID_FEATURE_MASK (0xFFFFU) #define OPAMP_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number */ #define OPAMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_FEATURE_SHIFT)) & OPAMP_VERID_FEATURE_MASK) #define OPAMP_VERID_MINOR_MASK (0xFF0000U) #define OPAMP_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define OPAMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MINOR_SHIFT)) & OPAMP_VERID_MINOR_MASK) #define OPAMP_VERID_MAJOR_MASK (0xFF000000U) #define OPAMP_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define OPAMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MAJOR_SHIFT)) & OPAMP_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define OPAMP_PARAM_PGA_FUNCTION_MASK (0x1U) #define OPAMP_PARAM_PGA_FUNCTION_SHIFT (0U) /*! PGA_FUNCTION - PGA Function Option * 0b0..Core amplifier enabled * 0b1..PGA function enabled */ #define OPAMP_PARAM_PGA_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_PARAM_PGA_FUNCTION_SHIFT)) & OPAMP_PARAM_PGA_FUNCTION_MASK) /*! @} */ /*! @name OPAMP_CTR - OPAMP Control */ /*! @{ */ #define OPAMP_OPAMP_CTR_EN_MASK (0x1U) #define OPAMP_OPAMP_CTR_EN_SHIFT (0U) /*! EN - OPAMP Enable * 0b0..Disable * 0b1..Enable */ #define OPAMP_OPAMP_CTR_EN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_EN_SHIFT)) & OPAMP_OPAMP_CTR_EN_MASK) #define OPAMP_OPAMP_CTR_MODE_MASK (0x2U) #define OPAMP_OPAMP_CTR_MODE_SHIFT (1U) /*! MODE - Mode Selection * 0b0..High performance mode * 0b1..Low power mode */ #define OPAMP_OPAMP_CTR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_MODE_SHIFT)) & OPAMP_OPAMP_CTR_MODE_MASK) #define OPAMP_OPAMP_CTR_BIASC_MASK (0xCU) #define OPAMP_OPAMP_CTR_BIASC_SHIFT (2U) /*! BIASC - Bias Current Trim Selection * 0b00..Default * 0b01..Increase current * 0b10..Decrease current * 0b11..Further decrease current */ #define OPAMP_OPAMP_CTR_BIASC(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_BIASC_SHIFT)) & OPAMP_OPAMP_CTR_BIASC_MASK) #define OPAMP_OPAMP_CTR_INTREF_MASK (0x30U) #define OPAMP_OPAMP_CTR_INTREF_SHIFT (4U) /*! INTREF - Provide OPAMP rail to rail voltage selection * 0b00..Select OPAMP input rail to rail voltage from 0 to VDD_ANA * 0b01..Select OPAMP input rail to rail voltage from 0 to VDD_ANA-0.8V * 0b10..Select OPAMP input rail to rail voltage from 0.8V to VDD_ANA * 0b11..Not allowed */ #define OPAMP_OPAMP_CTR_INTREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INTREF_SHIFT)) & OPAMP_OPAMP_CTR_INTREF_MASK) #define OPAMP_OPAMP_CTR_TRIGMD_MASK (0x100U) #define OPAMP_OPAMP_CTR_TRIGMD_SHIFT (8U) /*! TRIGMD - Trigger Mode * 0b0..Disable * 0b1..Enable */ #define OPAMP_OPAMP_CTR_TRIGMD(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_TRIGMD_SHIFT)) & OPAMP_OPAMP_CTR_TRIGMD_MASK) #define OPAMP_OPAMP_CTR_INPSEL_MASK (0x200U) #define OPAMP_OPAMP_CTR_INPSEL_SHIFT (9U) /*! INPSEL - Positive Input Channel Selection * 0b0..When OPAMP is not in trigger mode, select positive input 0 (INP0) * 0b1..When OPAMP is not in trigger mode, select positive input 1 (INP1) */ #define OPAMP_OPAMP_CTR_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INPSEL_SHIFT)) & OPAMP_OPAMP_CTR_INPSEL_MASK) #define OPAMP_OPAMP_CTR_INPF_MASK (0x1000U) #define OPAMP_OPAMP_CTR_INPF_SHIFT (12U) /*! INPF - Positive Input Connection Status * 0b0..Positive input 0 (INP0) * 0b1..Positive input 1 (INP1) */ #define OPAMP_OPAMP_CTR_INPF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INPF_SHIFT)) & OPAMP_OPAMP_CTR_INPF_MASK) #define OPAMP_OPAMP_CTR_BUFEN_MASK (0x10000U) #define OPAMP_OPAMP_CTR_BUFEN_SHIFT (16U) /*! BUFEN - Reference Buffer * 0b0..Disables * 0b1..Enables */ #define OPAMP_OPAMP_CTR_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_BUFEN_SHIFT)) & OPAMP_OPAMP_CTR_BUFEN_MASK) #define OPAMP_OPAMP_CTR_PREF_MASK (0x60000U) #define OPAMP_OPAMP_CTR_PREF_SHIFT (17U) /*! PREF - Positive Reference Voltage Selection * 0b00..Input 0 * 0b01..Input 1 * 0b10..Input 2 * 0b11..Input 3 */ #define OPAMP_OPAMP_CTR_PREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PREF_SHIFT)) & OPAMP_OPAMP_CTR_PREF_MASK) #define OPAMP_OPAMP_CTR_ADCSW1_MASK (0x100000U) #define OPAMP_OPAMP_CTR_ADCSW1_SHIFT (20U) /*! ADCSW1 - Measure Switch 1 * 0b0..Measure negative gain resistor ladder voltage switch off * 0b1..Measure negative gain resistor ladder voltage switch on */ #define OPAMP_OPAMP_CTR_ADCSW1(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_ADCSW1_SHIFT)) & OPAMP_OPAMP_CTR_ADCSW1_MASK) #define OPAMP_OPAMP_CTR_ADCSW2_MASK (0x200000U) #define OPAMP_OPAMP_CTR_ADCSW2_SHIFT (21U) /*! ADCSW2 - Measure Switch 2 * 0b0..Measure positive gain resistor ladder reference voltage switch off * 0b1..Measure positive gain resistor ladder reference voltage switch on */ #define OPAMP_OPAMP_CTR_ADCSW2(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_ADCSW2_SHIFT)) & OPAMP_OPAMP_CTR_ADCSW2_MASK) #define OPAMP_OPAMP_CTR_OUTSW_MASK (0x400000U) #define OPAMP_OPAMP_CTR_OUTSW_SHIFT (22U) /*! OUTSW - Output Switch * 0b0..OPAMP out to negative gain resistor ladder switch off * 0b1..OPAMP out to negative gain resistor ladder switch on */ #define OPAMP_OPAMP_CTR_OUTSW(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_OUTSW_SHIFT)) & OPAMP_OPAMP_CTR_OUTSW_MASK) #define OPAMP_OPAMP_CTR_PGAIN_MASK (0x7000000U) #define OPAMP_OPAMP_CTR_PGAIN_SHIFT (24U) /*! PGAIN - Positive PGA Selection * 0b000..Positive input 1 (INP1) * 0b001..Pgain=1 * 0b010..Pgain=2 * 0b011..Pgain=4 * 0b100..Pgain=8 * 0b101..Pgain=16 * 0b110..Pgain=33 * 0b111..Pgain=64 */ #define OPAMP_OPAMP_CTR_PGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PGAIN_SHIFT)) & OPAMP_OPAMP_CTR_PGAIN_MASK) #define OPAMP_OPAMP_CTR_NGAIN_MASK (0x70000000U) #define OPAMP_OPAMP_CTR_NGAIN_SHIFT (28U) /*! NGAIN - Negative PGA Selection * 0b000..Buffer * 0b001..Ngain=1 * 0b010..Ngain=2 * 0b011..Ngain=4 * 0b100..Ngain=8 * 0b101..Ngain=16 * 0b110..Ngain=33 * 0b111..Ngain=64 */ #define OPAMP_OPAMP_CTR_NGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_NGAIN_SHIFT)) & OPAMP_OPAMP_CTR_NGAIN_MASK) /*! @} */ /*! * @} */ /* end of group OPAMP_Register_Masks */ /* OPAMP - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral OPAMP0 base address */ #define OPAMP0_BASE (0x50110000u) /** Peripheral OPAMP0 base address */ #define OPAMP0_BASE_NS (0x40110000u) /** Peripheral OPAMP0 base pointer */ #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) /** Peripheral OPAMP0 base pointer */ #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) /** Peripheral OPAMP1 base address */ #define OPAMP1_BASE (0x50113000u) /** Peripheral OPAMP1 base address */ #define OPAMP1_BASE_NS (0x40113000u) /** Peripheral OPAMP1 base pointer */ #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) /** Peripheral OPAMP1 base pointer */ #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) /** Peripheral OPAMP2 base address */ #define OPAMP2_BASE (0x50115000u) /** Peripheral OPAMP2 base address */ #define OPAMP2_BASE_NS (0x40115000u) /** Peripheral OPAMP2 base pointer */ #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) /** Peripheral OPAMP2 base pointer */ #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) /** Array initializer of OPAMP peripheral base addresses */ #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } /** Array initializer of OPAMP peripheral base pointers */ #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } /** Array initializer of OPAMP peripheral base addresses */ #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } /** Array initializer of OPAMP peripheral base pointers */ #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } #else /** Peripheral OPAMP0 base address */ #define OPAMP0_BASE (0x40110000u) /** Peripheral OPAMP0 base pointer */ #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) /** Peripheral OPAMP1 base address */ #define OPAMP1_BASE (0x40113000u) /** Peripheral OPAMP1 base pointer */ #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) /** Peripheral OPAMP2 base address */ #define OPAMP2_BASE (0x40115000u) /** Peripheral OPAMP2 base pointer */ #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) /** Array initializer of OPAMP peripheral base addresses */ #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } /** Array initializer of OPAMP peripheral base pointers */ #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } #endif /*! * @} */ /* end of group OPAMP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OSTIMER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer * @{ */ /** OSTIMER - Register Layout Typedef */ typedef struct { __I uint32_t EVTIMERL; /**< EVTIMER Low, offset: 0x0 */ __I uint32_t EVTIMERH; /**< EVTIMER High, offset: 0x4 */ __I uint32_t CAPTURE_L; /**< Local Capture Low for CPU, offset: 0x8 */ __I uint32_t CAPTURE_H; /**< Local Capture High for CPU, offset: 0xC */ __IO uint32_t MATCH_L; /**< Local Match Low for CPU, offset: 0x10 */ __IO uint32_t MATCH_H; /**< Local Match High for CPU, offset: 0x14 */ uint8_t RESERVED_0[4]; __IO uint32_t OSEVENT_CTRL; /**< OSTIMER Control for CPU, offset: 0x1C */ } OSTIMER_Type; /* ---------------------------------------------------------------------------- -- OSTIMER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks * @{ */ /*! @name EVTIMERL - EVTIMER Low */ /*! @{ */ #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) /*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) /*! @} */ /*! @name EVTIMERH - EVTIMER High */ /*! @{ */ #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) /*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) /*! @} */ /*! @name CAPTURE_L - Local Capture Low for CPU */ /*! @{ */ #define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) #define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) /*! CAPTURE_VALUE - EVTimer Capture Value */ #define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) /*! @} */ /*! @name CAPTURE_H - Local Capture High for CPU */ /*! @{ */ #define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) #define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) /*! CAPTURE_VALUE - EVTimer Capture Value */ #define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) /*! @} */ /*! @name MATCH_L - Local Match Low for CPU */ /*! @{ */ #define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) #define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) /*! MATCH_VALUE - EVTimer Match Value */ #define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) /*! @} */ /*! @name MATCH_H - Local Match High for CPU */ /*! @{ */ #define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) #define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) /*! MATCH_VALUE - EVTimer Match Value */ #define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) /*! @} */ /*! @name OSEVENT_CTRL - OSTIMER Control for CPU */ /*! @{ */ #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) /*! OSTIMER_INTRFLAG - Interrupt Flag */ #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) /*! OSTIMER_INTENA - Interrupt or Wake-Up Request * 0b0..Interrupts blocked * 0b1..Interrupts enabled */ #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) /*! MATCH_WR_RDY - EVTimer Match Write Ready */ #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) /*! @} */ /*! * @} */ /* end of group OSTIMER_Register_Masks */ /* OSTIMER - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral OSTIMER0 base address */ #define OSTIMER0_BASE (0x50049000u) /** Peripheral OSTIMER0 base address */ #define OSTIMER0_BASE_NS (0x40049000u) /** Peripheral OSTIMER0 base pointer */ #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) /** Peripheral OSTIMER0 base pointer */ #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) /** Array initializer of OSTIMER peripheral base addresses */ #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } /** Array initializer of OSTIMER peripheral base pointers */ #define OSTIMER_BASE_PTRS { OSTIMER0 } /** Array initializer of OSTIMER peripheral base addresses */ #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } /** Array initializer of OSTIMER peripheral base pointers */ #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } #else /** Peripheral OSTIMER0 base address */ #define OSTIMER0_BASE (0x40049000u) /** Peripheral OSTIMER0 base pointer */ #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) /** Array initializer of OSTIMER peripheral base addresses */ #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } /** Array initializer of OSTIMER peripheral base pointers */ #define OSTIMER_BASE_PTRS { OSTIMER0 } #endif /** Interrupt vectors for the OSTIMER peripheral type */ #define OSTIMER_IRQS { OS_EVENT_IRQn } /*! * @} */ /* end of group OSTIMER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OTPC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer * @{ */ /** OTPC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameters, offset: 0x4 */ __IO uint32_t SR; /**< Status, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t RWC; /**< Read and Write Control, offset: 0x10 */ __IO uint32_t RLC; /**< Reload Control, offset: 0x14 */ __IO uint32_t PCR; /**< Power Control, offset: 0x18 */ uint8_t RESERVED_1[4]; __IO uint32_t WDATA; /**< Write Data, offset: 0x20 */ __I uint32_t RDATA; /**< Read Data, offset: 0x24 */ uint8_t RESERVED_2[8]; __IO uint32_t TIMING1; /**< Timing1, offset: 0x30 */ __IO uint32_t TIMING2; /**< Timing2, offset: 0x34 */ uint8_t RESERVED_3[456]; __I uint32_t LOCK; /**< Lock, offset: 0x200 */ __I uint32_t SECURE; /**< Secure, offset: 0x204 */ __I uint32_t SECURE_INV; /**< Inverted Secure, offset: 0x208 */ __I uint32_t DBG_KEY; /**< Debug and Key, offset: 0x20C */ __IO uint32_t MISC_CFG; /**< MISC Config, offset: 0x210 */ __IO uint32_t PHANTOM_CFG; /**< PHANTOM Config, offset: 0x214 */ __IO uint32_t FLEX_CFG0; /**< Flexible Config 0, offset: 0x218 */ __IO uint32_t FLEX_CFG1; /**< Flexible Config 1, offset: 0x21C */ } OTPC_Type; /* ---------------------------------------------------------------------------- -- OTPC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OTPC_Register_Masks OTPC Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define OTPC_VERID_FEATURE_MASK (0xFFFFU) #define OTPC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard feature set */ #define OTPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_FEATURE_SHIFT)) & OTPC_VERID_FEATURE_MASK) #define OTPC_VERID_MINOR_MASK (0xFF0000U) #define OTPC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define OTPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MINOR_SHIFT)) & OTPC_VERID_MINOR_MASK) #define OTPC_VERID_MAJOR_MASK (0xFF000000U) #define OTPC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define OTPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MAJOR_SHIFT)) & OTPC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameters */ /*! @{ */ #define OTPC_PARAM_NUM_FUSE_MASK (0xFFFFU) #define OTPC_PARAM_NUM_FUSE_SHIFT (0U) /*! NUM_FUSE - Number of fuse bytes */ #define OTPC_PARAM_NUM_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PARAM_NUM_FUSE_SHIFT)) & OTPC_PARAM_NUM_FUSE_MASK) /*! @} */ /*! @name SR - Status */ /*! @{ */ #define OTPC_SR_BUSY_MASK (0x1U) #define OTPC_SR_BUSY_SHIFT (0U) /*! BUSY - Busy status * 0b0..Not busy (transaction complete) * 0b1..Busy */ #define OTPC_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_BUSY_SHIFT)) & OTPC_SR_BUSY_MASK) #define OTPC_SR_ERROR_MASK (0x2U) #define OTPC_SR_ERROR_SHIFT (1U) /*! ERROR - Error flag * 0b0..No error * 0b1..Error */ #define OTPC_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ERROR_SHIFT)) & OTPC_SR_ERROR_MASK) #define OTPC_SR_ECC_SF_MASK (0x4U) #define OTPC_SR_ECC_SF_SHIFT (2U) /*! ECC_SF - ECC single fault * 0b0..No fault * 0b1..Fault */ #define OTPC_SR_ECC_SF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_SF_SHIFT)) & OTPC_SR_ECC_SF_MASK) #define OTPC_SR_ECC_DF_MASK (0x8U) #define OTPC_SR_ECC_DF_SHIFT (3U) /*! ECC_DF - ECC double fault * 0b0..No fault * 0b1..Fault */ #define OTPC_SR_ECC_DF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_DF_SHIFT)) & OTPC_SR_ECC_DF_MASK) #define OTPC_SR_TRI_F_MASK (0x10U) #define OTPC_SR_TRI_F_SHIFT (4U) /*! TRI_F - Triple voting fault * 0b0..No fault * 0b1..Fault */ #define OTPC_SR_TRI_F(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_TRI_F_SHIFT)) & OTPC_SR_TRI_F_MASK) #define OTPC_SR_RD_FUSE_LOCK_MASK (0x100U) #define OTPC_SR_RD_FUSE_LOCK_SHIFT (8U) /*! RD_FUSE_LOCK - Read fuse lock error * 0b0..No error * 0b1..Error */ #define OTPC_SR_RD_FUSE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_FUSE_LOCK_SHIFT)) & OTPC_SR_RD_FUSE_LOCK_MASK) #define OTPC_SR_WR_FUSE_LOCK_MASK (0x200U) #define OTPC_SR_WR_FUSE_LOCK_SHIFT (9U) /*! WR_FUSE_LOCK - Write fuse lock error * 0b0..No error * 0b1..Error */ #define OTPC_SR_WR_FUSE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_FUSE_LOCK_SHIFT)) & OTPC_SR_WR_FUSE_LOCK_MASK) #define OTPC_SR_RD_REG_LOCK_MASK (0x400U) #define OTPC_SR_RD_REG_LOCK_SHIFT (10U) /*! RD_REG_LOCK - Read register lock error * 0b0..No error * 0b1..Error */ #define OTPC_SR_RD_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_REG_LOCK_SHIFT)) & OTPC_SR_RD_REG_LOCK_MASK) #define OTPC_SR_WR_REG_LOCK_MASK (0x800U) #define OTPC_SR_WR_REG_LOCK_SHIFT (11U) /*! WR_REG_LOCK - Write register lock error * 0b0..No error * 0b1..Error */ #define OTPC_SR_WR_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_LOCK_SHIFT)) & OTPC_SR_WR_REG_LOCK_MASK) #define OTPC_SR_WR_REG_BUSY_MASK (0x1000U) #define OTPC_SR_WR_REG_BUSY_SHIFT (12U) /*! WR_REG_BUSY - Write register when busy error * 0b0..No error * 0b1..Error */ #define OTPC_SR_WR_REG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_BUSY_SHIFT)) & OTPC_SR_WR_REG_BUSY_MASK) #define OTPC_SR_WR_POWER_OFF_MASK (0x2000U) #define OTPC_SR_WR_POWER_OFF_SHIFT (13U) /*! WR_POWER_OFF - Write when power off error * 0b0..No error * 0b1..Error */ #define OTPC_SR_WR_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_POWER_OFF_SHIFT)) & OTPC_SR_WR_POWER_OFF_MASK) #define OTPC_SR_FSM_MASK (0x10000U) #define OTPC_SR_FSM_SHIFT (16U) /*! FSM - Finite-state machine error * 0b0..No error * 0b1..Error */ #define OTPC_SR_FSM(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSM_SHIFT)) & OTPC_SR_FSM_MASK) #define OTPC_SR_FLC_MASK (0x20000U) #define OTPC_SR_FLC_SHIFT (17U) /*! FLC - Fuse load counter error * 0b0..No error * 0b1..Error */ #define OTPC_SR_FLC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FLC_SHIFT)) & OTPC_SR_FLC_MASK) #define OTPC_SR_ADC_MASK (0x40000U) #define OTPC_SR_ADC_SHIFT (18U) /*! ADC - Address and data compare error * 0b0..No error * 0b1..Error */ #define OTPC_SR_ADC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ADC_SHIFT)) & OTPC_SR_ADC_MASK) #define OTPC_SR_IRC_MASK (0x80000U) #define OTPC_SR_IRC_SHIFT (19U) /*! IRC - Inverted register compare error * 0b0..No error * 0b1..Error */ #define OTPC_SR_IRC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_IRC_SHIFT)) & OTPC_SR_IRC_MASK) #define OTPC_SR_FSC_MASK (0x100000U) #define OTPC_SR_FSC_SHIFT (20U) /*! FSC - Fuse and shadow register compare error * 0b0..No error * 0b1..Error */ #define OTPC_SR_FSC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSC_SHIFT)) & OTPC_SR_FSC_MASK) /*! @} */ /*! @name RWC - Read and Write Control */ /*! @{ */ #define OTPC_RWC_ADDR_MASK (0x7FU) #define OTPC_RWC_ADDR_SHIFT (0U) /*! ADDR - EFUSE address */ #define OTPC_RWC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_ADDR_SHIFT)) & OTPC_RWC_ADDR_MASK) #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) #define OTPC_RWC_WR_ALL1S_SHIFT (12U) /*! WR_ALL1S - Write all 1s * 0b0..Uses the WDATA value * 0b1..Writes all 1s */ #define OTPC_RWC_WR_ALL1S(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK) #define OTPC_RWC_READ_EFUSE_MASK (0x2000U) #define OTPC_RWC_READ_EFUSE_SHIFT (13U) /*! READ_EFUSE - Read EFUSE * 0b0..Starts program operation when the WR_UNLOCK value is 0x9527; otherwise, takes no action. * 0b1..Starts read operation */ #define OTPC_RWC_READ_EFUSE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_EFUSE_SHIFT)) & OTPC_RWC_READ_EFUSE_MASK) #define OTPC_RWC_READ_UPDATE_MASK (0x4000U) #define OTPC_RWC_READ_UPDATE_SHIFT (14U) /*! READ_UPDATE - Read update * 0b0..Shadow register does not update * 0b1..Shadow register updates */ #define OTPC_RWC_READ_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_UPDATE_SHIFT)) & OTPC_RWC_READ_UPDATE_MASK) #define OTPC_RWC_WR_UNLOCK_MASK (0xFFFF0000U) #define OTPC_RWC_WR_UNLOCK_SHIFT (16U) /*! WR_UNLOCK - Write Unlock */ #define OTPC_RWC_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_UNLOCK_SHIFT)) & OTPC_RWC_WR_UNLOCK_MASK) /*! @} */ /*! @name RLC - Reload Control */ /*! @{ */ #define OTPC_RLC_RELOAD_SHADOWS_MASK (0x1U) #define OTPC_RLC_RELOAD_SHADOWS_SHIFT (0U) /*! RELOAD_SHADOWS - Reload shadow registers * 0b0..No action (when writing) or reload complete (when reading) * 0b1..Reload */ #define OTPC_RLC_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RLC_RELOAD_SHADOWS_SHIFT)) & OTPC_RLC_RELOAD_SHADOWS_MASK) /*! @} */ /*! @name PCR - Power Control */ /*! @{ */ #define OTPC_PCR_HVREQ_MASK (0x1U) #define OTPC_PCR_HVREQ_SHIFT (0U) /*! HVREQ - Strong switch request * 0b0..Turn off * 0b1..Turn on */ #define OTPC_PCR_HVREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_HVREQ_SHIFT)) & OTPC_PCR_HVREQ_MASK) #define OTPC_PCR_LVREQ_MASK (0x2U) #define OTPC_PCR_LVREQ_SHIFT (1U) /*! LVREQ - Weak switch request * 0b0..Turn off * 0b1..Turn on */ #define OTPC_PCR_LVREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_LVREQ_SHIFT)) & OTPC_PCR_LVREQ_MASK) #define OTPC_PCR_PDREQ_MASK (0x4U) #define OTPC_PCR_PDREQ_SHIFT (2U) /*! PDREQ - Power down request * 0b0..PD pin is set to low when OTPC is in idle state. It means EFUSE hardmacro is in standby mode. Idle state * means OTPC is not in read and program modes. * 0b1..PD pin is set to high when OTPC is in idle state. It means EFUSE hardmacro is in power down mode. */ #define OTPC_PCR_PDREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_PDREQ_SHIFT)) & OTPC_PCR_PDREQ_MASK) /*! @} */ /*! @name WDATA - Write Data */ /*! @{ */ #define OTPC_WDATA_DAT_MASK (0xFFFFFFFFU) #define OTPC_WDATA_DAT_SHIFT (0U) /*! DAT - Write data */ #define OTPC_WDATA_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_WDATA_DAT_SHIFT)) & OTPC_WDATA_DAT_MASK) /*! @} */ /*! @name RDATA - Read Data */ /*! @{ */ #define OTPC_RDATA_DAT_MASK (0xFFFFFFFFU) #define OTPC_RDATA_DAT_SHIFT (0U) /*! DAT - Read data */ #define OTPC_RDATA_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RDATA_DAT_SHIFT)) & OTPC_RDATA_DAT_MASK) /*! @} */ /*! @name TIMING1 - Timing1 */ /*! @{ */ #define OTPC_TIMING1_TADDR_MASK (0xFU) #define OTPC_TIMING1_TADDR_SHIFT (0U) /*! TADDR - Address to STROBE setup and hold time */ #define OTPC_TIMING1_TADDR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TADDR_SHIFT)) & OTPC_TIMING1_TADDR_MASK) #define OTPC_TIMING1_TRELAX_MASK (0xF0U) #define OTPC_TIMING1_TRELAX_SHIFT (4U) /*! TRELAX - CSB, PGENB and LOAD to STROBE setup and hold time */ #define OTPC_TIMING1_TRELAX(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRELAX_SHIFT)) & OTPC_TIMING1_TRELAX_MASK) #define OTPC_TIMING1_TRD_MASK (0x3F00U) #define OTPC_TIMING1_TRD_SHIFT (8U) /*! TRD - Read strobe pulse width time */ #define OTPC_TIMING1_TRD(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRD_SHIFT)) & OTPC_TIMING1_TRD_MASK) #define OTPC_TIMING1_TPS_MASK (0x3F0000U) #define OTPC_TIMING1_TPS_SHIFT (16U) /*! TPS - PS to CSB setup and hold time between power switch and chip select assertion */ #define OTPC_TIMING1_TPS(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPS_SHIFT)) & OTPC_TIMING1_TPS_MASK) #define OTPC_TIMING1_TPD_MASK (0xFF000000U) #define OTPC_TIMING1_TPD_SHIFT (24U) /*! TPD - PD to CSB setup time between power down signal deassertion and chip select signal assertion */ #define OTPC_TIMING1_TPD(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK) /*! @} */ /*! @name TIMING2 - Timing2 */ /*! @{ */ #define OTPC_TIMING2_TPGM_MASK (0xFFFU) #define OTPC_TIMING2_TPGM_SHIFT (0U) /*! TPGM - Typical program strobe pulse width time */ #define OTPC_TIMING2_TPGM(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING2_TPGM_SHIFT)) & OTPC_TIMING2_TPGM_MASK) /*! @} */ /*! @name LOCK - Lock */ /*! @{ */ #define OTPC_LOCK_NXP_PART_CFG_LOCK_MASK (0x7U) #define OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT (0U) /*! NXP_PART_CFG_LOCK - NXP Part Config Lock */ #define OTPC_LOCK_NXP_PART_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT)) & OTPC_LOCK_NXP_PART_CFG_LOCK_MASK) #define OTPC_LOCK_NXP_EXT_LOCK_MASK (0x38U) #define OTPC_LOCK_NXP_EXT_LOCK_SHIFT (3U) /*! NXP_EXT_LOCK - NXP EXT Lock */ #define OTPC_LOCK_NXP_EXT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_EXT_LOCK_SHIFT)) & OTPC_LOCK_NXP_EXT_LOCK_MASK) #define OTPC_LOCK_BOOT_CFG_LOCK_MASK (0xE00U) #define OTPC_LOCK_BOOT_CFG_LOCK_SHIFT (9U) /*! BOOT_CFG_LOCK - Boot config Lock */ #define OTPC_LOCK_BOOT_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_BOOT_CFG_LOCK_SHIFT)) & OTPC_LOCK_BOOT_CFG_LOCK_MASK) #define OTPC_LOCK_PRINCE_CFG_LOCK_MASK (0x7000U) #define OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT (12U) /*! PRINCE_CFG_LOCK - Prince Config Lock */ #define OTPC_LOCK_PRINCE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT)) & OTPC_LOCK_PRINCE_CFG_LOCK_MASK) #define OTPC_LOCK_OSCAA_KEY_LOCK_MASK (0x38000U) #define OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT (15U) /*! OSCAA_KEY_LOCK - OSCAA Key Lock */ #define OTPC_LOCK_OSCAA_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT)) & OTPC_LOCK_OSCAA_KEY_LOCK_MASK) #define OTPC_LOCK_CUST_LOCK0_MASK (0x1C0000U) #define OTPC_LOCK_CUST_LOCK0_SHIFT (18U) /*! CUST_LOCK0 - CUST Lock 0 */ #define OTPC_LOCK_CUST_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK0_SHIFT)) & OTPC_LOCK_CUST_LOCK0_MASK) #define OTPC_LOCK_CUST_LOCK1_MASK (0xE00000U) #define OTPC_LOCK_CUST_LOCK1_SHIFT (21U) /*! CUST_LOCK1 - CUST Lock 1 */ #define OTPC_LOCK_CUST_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK1_SHIFT)) & OTPC_LOCK_CUST_LOCK1_MASK) #define OTPC_LOCK_CUST_LOCK2_MASK (0x7000000U) #define OTPC_LOCK_CUST_LOCK2_SHIFT (24U) /*! CUST_LOCK2 - CUST Lock 2 */ #define OTPC_LOCK_CUST_LOCK2(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK2_SHIFT)) & OTPC_LOCK_CUST_LOCK2_MASK) #define OTPC_LOCK_CUST_LOCK3_MASK (0x38000000U) #define OTPC_LOCK_CUST_LOCK3_SHIFT (27U) /*! CUST_LOCK3 - CUST Lock 3 */ #define OTPC_LOCK_CUST_LOCK3(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK3_SHIFT)) & OTPC_LOCK_CUST_LOCK3_MASK) /*! @} */ /*! @name SECURE - Secure */ /*! @{ */ #define OTPC_SECURE_DAT_MASK (0xFFFFFFFFU) #define OTPC_SECURE_DAT_SHIFT (0U) /*! DAT - Data */ #define OTPC_SECURE_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_DAT_SHIFT)) & OTPC_SECURE_DAT_MASK) /*! @} */ /*! @name SECURE_INV - Inverted Secure */ /*! @{ */ #define OTPC_SECURE_INV_DAT_MASK (0xFFFFFFFFU) #define OTPC_SECURE_INV_DAT_SHIFT (0U) /*! DAT - Data */ #define OTPC_SECURE_INV_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_INV_DAT_SHIFT)) & OTPC_SECURE_INV_DAT_MASK) /*! @} */ /*! @name DBG_KEY - Debug and Key */ /*! @{ */ #define OTPC_DBG_KEY_DAT_MASK (0xFFFFFFFFU) #define OTPC_DBG_KEY_DAT_SHIFT (0U) /*! DAT - Data */ #define OTPC_DBG_KEY_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_DBG_KEY_DAT_SHIFT)) & OTPC_DBG_KEY_DAT_MASK) /*! @} */ /*! @name MISC_CFG - MISC Config */ /*! @{ */ #define OTPC_MISC_CFG_DAT_MASK (0xFFFFFFFFU) #define OTPC_MISC_CFG_DAT_SHIFT (0U) /*! DAT - Data */ #define OTPC_MISC_CFG_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_MISC_CFG_DAT_SHIFT)) & OTPC_MISC_CFG_DAT_MASK) /*! @} */ /*! @name PHANTOM_CFG - PHANTOM Config */ /*! @{ */ #define OTPC_PHANTOM_CFG_DAT_MASK (0xFFFFFFFFU) #define OTPC_PHANTOM_CFG_DAT_SHIFT (0U) /*! DAT - Data */ #define OTPC_PHANTOM_CFG_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PHANTOM_CFG_DAT_SHIFT)) & OTPC_PHANTOM_CFG_DAT_MASK) /*! @} */ /*! @name FLEX_CFG0 - Flexible Config 0 */ /*! @{ */ #define OTPC_FLEX_CFG0_DAT_MASK (0xFFFFFFFFU) #define OTPC_FLEX_CFG0_DAT_SHIFT (0U) /*! DAT - Data */ #define OTPC_FLEX_CFG0_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG0_DAT_SHIFT)) & OTPC_FLEX_CFG0_DAT_MASK) /*! @} */ /*! @name FLEX_CFG1 - Flexible Config 1 */ /*! @{ */ #define OTPC_FLEX_CFG1_DAT_MASK (0xFFFFFFFFU) #define OTPC_FLEX_CFG1_DAT_SHIFT (0U) /*! DAT - Data */ #define OTPC_FLEX_CFG1_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG1_DAT_SHIFT)) & OTPC_FLEX_CFG1_DAT_MASK) /*! @} */ /*! * @} */ /* end of group OTPC_Register_Masks */ /* OTPC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral OTPC0 base address */ #define OTPC0_BASE (0x500C9000u) /** Peripheral OTPC0 base address */ #define OTPC0_BASE_NS (0x400C9000u) /** Peripheral OTPC0 base pointer */ #define OTPC0 ((OTPC_Type *)OTPC0_BASE) /** Peripheral OTPC0 base pointer */ #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) /** Array initializer of OTPC peripheral base addresses */ #define OTPC_BASE_ADDRS { OTPC0_BASE } /** Array initializer of OTPC peripheral base pointers */ #define OTPC_BASE_PTRS { OTPC0 } /** Array initializer of OTPC peripheral base addresses */ #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } /** Array initializer of OTPC peripheral base pointers */ #define OTPC_BASE_PTRS_NS { OTPC0_NS } #else /** Peripheral OTPC0 base address */ #define OTPC0_BASE (0x400C9000u) /** Peripheral OTPC0 base pointer */ #define OTPC0 ((OTPC_Type *)OTPC0_BASE) /** Array initializer of OTPC peripheral base addresses */ #define OTPC_BASE_ADDRS { OTPC0_BASE } /** Array initializer of OTPC peripheral base pointers */ #define OTPC_BASE_PTRS { OTPC0 } #endif /*! * @} */ /* end of group OTPC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PDM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer * @{ */ /** PDM - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL_1; /**< MICFIL Control 1, offset: 0x0 */ __IO uint32_t CTRL_2; /**< MICFIL Control 2, offset: 0x4 */ __IO uint32_t STAT; /**< MICFIL Status, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control, offset: 0x10 */ __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status, offset: 0x14 */ uint8_t RESERVED_1[12]; __I uint32_t DATACH[4]; /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */ uint8_t RESERVED_2[48]; __I uint32_t DC_CTRL; /**< MICFIL DC Remover Control, offset: 0x64 */ __IO uint32_t DC_OUT_CTRL; /**< MICFIL Output DC Remover Control, offset: 0x68 */ uint8_t RESERVED_3[8]; __IO uint32_t RANGE_CTRL; /**< MICFIL Range Control, offset: 0x74 */ uint8_t RESERVED_4[4]; __IO uint32_t RANGE_STAT; /**< MICFIL Range Status, offset: 0x7C */ __IO uint32_t FSYNC_CTRL; /**< Frame Synchronization Control, offset: 0x80 */ __I uint32_t VERID; /**< Version ID, offset: 0x84 */ __I uint32_t PARAM; /**< Parameter, offset: 0x88 */ } PDM_Type; /* ---------------------------------------------------------------------------- -- PDM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PDM_Register_Masks PDM Register Masks * @{ */ /*! @name CTRL_1 - MICFIL Control 1 */ /*! @{ */ #define PDM_CTRL_1_CH0EN_MASK (0x1U) #define PDM_CTRL_1_CH0EN_SHIFT (0U) /*! CH0EN - Channel 0 Enable */ #define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) #define PDM_CTRL_1_CH1EN_MASK (0x2U) #define PDM_CTRL_1_CH1EN_SHIFT (1U) /*! CH1EN - Channel 1 Enable */ #define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) #define PDM_CTRL_1_CH2EN_MASK (0x4U) #define PDM_CTRL_1_CH2EN_SHIFT (2U) /*! CH2EN - Channel 2 Enable */ #define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) #define PDM_CTRL_1_CH3EN_MASK (0x8U) #define PDM_CTRL_1_CH3EN_SHIFT (3U) /*! CH3EN - Channel 3 Enable */ #define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) #define PDM_CTRL_1_FSYNCEN_MASK (0x10000U) #define PDM_CTRL_1_FSYNCEN_SHIFT (16U) /*! FSYNCEN - Frame Synchronization Enable * 0b0..Disables * 0b1..Enables */ #define PDM_CTRL_1_FSYNCEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK) #define PDM_CTRL_1_DECFILS_MASK (0x100000U) #define PDM_CTRL_1_DECFILS_SHIFT (20U) /*! DECFILS - Decimation Filter Enable in Stop * 0b0..Stops decimation filter * 0b1..Keeps decimation filter running */ #define PDM_CTRL_1_DECFILS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK) #define PDM_CTRL_1_ERREN_MASK (0x800000U) #define PDM_CTRL_1_ERREN_SHIFT (23U) /*! ERREN - Error Interruption Enable * 0b0..Disables * 0b1..Enables */ #define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) #define PDM_CTRL_1_DISEL_MASK (0x3000000U) #define PDM_CTRL_1_DISEL_SHIFT (24U) /*! DISEL - DMA Interrupt Selection * 0b00..Disables DMA and interrupt requests * 0b01..Enables DMA requests * 0b10..Enables interrupt requests * 0b11..Reserved */ #define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) #define PDM_CTRL_1_DBGE_MASK (0x4000000U) #define PDM_CTRL_1_DBGE_SHIFT (26U) /*! DBGE - Module Enable in Debug * 0b0..Disables after completing the current frame * 0b1..Enables operation */ #define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) #define PDM_CTRL_1_SRES_MASK (0x8000000U) #define PDM_CTRL_1_SRES_SHIFT (27U) /*! SRES - Software Reset * 0b0..No action * 0b1..Software reset */ #define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) #define PDM_CTRL_1_DBG_MASK (0x10000000U) #define PDM_CTRL_1_DBG_SHIFT (28U) /*! DBG - Debug Mode * 0b0..Normal * 0b1..Debug */ #define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) #define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) #define PDM_CTRL_1_PDMIEN_SHIFT (29U) /*! PDMIEN - MICFIL Enable * 0b0..Stops MICFIL operation * 0b1..Starts MICFIL operation */ #define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) #define PDM_CTRL_1_DOZEN_MASK (0x40000000U) #define PDM_CTRL_1_DOZEN_SHIFT (30U) /*! DOZEN - Stop Enable * 0b0..Disables * 0b1..Enables */ #define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) #define PDM_CTRL_1_MDIS_MASK (0x80000000U) #define PDM_CTRL_1_MDIS_SHIFT (31U) /*! MDIS - Module Disable * 0b0..Normal mode * 0b1..DLL mode */ #define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) /*! @} */ /*! @name CTRL_2 - MICFIL Control 2 */ /*! @{ */ #define PDM_CTRL_2_CLKDIV_MASK (0xFFU) #define PDM_CTRL_2_CLKDIV_SHIFT (0U) /*! CLKDIV - Clock Divider * 0b00000000..Internal clock divider value = 0 * 0b00000001..Internal clock divider value = 1 * 0b00000010-0b11111110..... * 0b11111111..Internal clock divider value = 255 */ #define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) #define PDM_CTRL_2_CLKDIVDIS_MASK (0x8000U) #define PDM_CTRL_2_CLKDIVDIS_SHIFT (15U) /*! CLKDIVDIS - Clock Divider Disable * 0b0..Enables * 0b1..Disables */ #define PDM_CTRL_2_CLKDIVDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIVDIS_SHIFT)) & PDM_CTRL_2_CLKDIVDIS_MASK) #define PDM_CTRL_2_CICOSR_MASK (0xF0000U) #define PDM_CTRL_2_CICOSR_SHIFT (16U) /*! CICOSR - CIC Decimation Rate * 0b0000..CIC oversampling rate = 0 * 0b0001..CIC oversampling rate = 1 * 0b0010-0b1110..... * 0b1111..CIC oversampling rate = 15 */ #define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) #define PDM_CTRL_2_QSEL_MASK (0xE000000U) #define PDM_CTRL_2_QSEL_SHIFT (25U) /*! QSEL - Quality Mode * 0b001..High-Quality mode * 0b000..Medium-Quality mode * 0b111..Low-Quality mode * 0b110..Very-Low-Quality 0 mode * 0b101..Very-Low-Quality 1 mode * 0b100..Very-Low-Quality 2 mode */ #define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) /*! @} */ /*! @name STAT - MICFIL Status */ /*! @{ */ #define PDM_STAT_CH0F_MASK (0x1U) #define PDM_STAT_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) #define PDM_STAT_CH1F_MASK (0x2U) #define PDM_STAT_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) #define PDM_STAT_CH2F_MASK (0x4U) #define PDM_STAT_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) #define PDM_STAT_CH3F_MASK (0x8U) #define PDM_STAT_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) #define PDM_STAT_BSY_FIL_MASK (0x80000000U) #define PDM_STAT_BSY_FIL_SHIFT (31U) /*! BSY_FIL - Busy Flag * 0b1..MICFIL is running * 0b0..MICFIL is stopped */ #define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) /*! @} */ /*! @name FIFO_CTRL - MICFIL FIFO Control */ /*! @{ */ #define PDM_FIFO_CTRL_FIFOWMK_MASK (0xFU) #define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) /*! FIFOWMK - FIFO Watermark Control */ #define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) /*! @} */ /*! @name FIFO_STAT - MICFIL FIFO Status */ /*! @{ */ #define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) #define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) /*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) #define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) #define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) /*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) #define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) #define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) /*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) #define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) #define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) /*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) #define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) #define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) /*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) #define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) #define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) /*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) #define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) #define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) /*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) #define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) #define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) /*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) /*! @} */ /*! @name DATACHN_DATACH - MICFIL Output Result */ /*! @{ */ #define PDM_DATACHN_DATACH_DATA_MASK (0xFFFFFFFFU) #define PDM_DATACHN_DATACH_DATA_SHIFT (0U) /*! DATA - Channel n Data */ #define PDM_DATACHN_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACHN_DATACH_DATA_SHIFT)) & PDM_DATACHN_DATACH_DATA_MASK) /*! @} */ /* The count of PDM_DATACHN_DATACH */ #define PDM_DATACHN_DATACH_COUNT (4U) /*! @name DC_CTRL - MICFIL DC Remover Control */ /*! @{ */ #define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) #define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) /*! DCCONFIG0 - Channel 0 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) #define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) #define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) /*! DCCONFIG1 - Channel 1 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) #define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) #define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) /*! DCCONFIG2 - Channel 2 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) #define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) #define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) /*! DCCONFIG3 - Channel 3 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) /*! @} */ /*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */ /*! @{ */ #define PDM_DC_OUT_CTRL_DCCONFIG0_MASK (0x3U) #define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT (0U) /*! DCCONFIG0 - Channel 0 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG1_MASK (0xCU) #define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT (2U) /*! DCCONFIG1 - Channel 1 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG2_MASK (0x30U) #define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT (4U) /*! DCCONFIG2 - Channel 2 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG3_MASK (0xC0U) #define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT (6U) /*! DCCONFIG3 - Channel 3 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK) /*! @} */ /*! @name RANGE_CTRL - MICFIL Range Control */ /*! @{ */ #define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) /*! RANGEADJ0 - Channel 0 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) #define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) /*! RANGEADJ1 - Channel 1 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) #define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) /*! RANGEADJ2 - Channel 2 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) #define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) /*! RANGEADJ3 - Channel 3 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) /*! @} */ /*! @name RANGE_STAT - MICFIL Range Status */ /*! @{ */ #define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) #define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) #define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) #define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) #define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) #define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) #define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) #define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) #define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) #define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) #define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) #define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) #define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) #define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) #define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) #define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) /*! @} */ /*! @name FSYNC_CTRL - Frame Synchronization Control */ /*! @{ */ #define PDM_FSYNC_CTRL_FSYNCLEN_MASK (0xFFFFFFFFU) #define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT (0U) /*! FSYNCLEN - Frame Synchronization Window Length */ #define PDM_FSYNC_CTRL_FSYNCLEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK) /*! @} */ /*! @name VERID - Version ID */ /*! @{ */ #define PDM_VERID_FEATURE_MASK (0xFFFFU) #define PDM_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number */ #define PDM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK) #define PDM_VERID_MINOR_MASK (0xFF0000U) #define PDM_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define PDM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK) #define PDM_VERID_MAJOR_MASK (0xFF000000U) #define PDM_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define PDM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define PDM_PARAM_NPAIR_MASK (0xFU) #define PDM_PARAM_NPAIR_SHIFT (0U) /*! NPAIR - Number of Microphone Pairs * 0b0000..None * 0b0001..1 pair * 0b0010..2 pairs * 0b0011-0b1110..... * 0b1111..15 pairs */ #define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) #define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) #define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) /*! FIFO_PTRWID - FIFO Pointer Width * 0b0000..0 bits * 0b0001..1 bit * 0b0010..2 bits * 0b0011-0b1110..... * 0b1111..15 bits */ #define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) #define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) #define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT (8U) /*! FIL_OUT_WIDTH_24B - Filter Output Width * 0b0..16 bits * 0b1..24 bits */ #define PDM_PARAM_FIL_OUT_WIDTH_24B(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK) #define PDM_PARAM_LOW_POWER_MASK (0x200U) #define PDM_PARAM_LOW_POWER_SHIFT (9U) /*! LOW_POWER - Low-Power Decimation Filter * 0b0..Disables * 0b1..Enables */ #define PDM_PARAM_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK) #define PDM_PARAM_DC_BYPASS_MASK (0x400U) #define PDM_PARAM_DC_BYPASS_SHIFT (10U) /*! DC_BYPASS - Input DC Remover Bypass * 0b0..Active * 0b1..Disabled */ #define PDM_PARAM_DC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK) #define PDM_PARAM_DC_OUT_BYPASS_MASK (0x800U) #define PDM_PARAM_DC_OUT_BYPASS_SHIFT (11U) /*! DC_OUT_BYPASS - Output DC Remover Bypass * 0b0..Active * 0b1..Disabled */ #define PDM_PARAM_DC_OUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK) /*! @} */ /*! * @} */ /* end of group PDM_Register_Masks */ /* PDM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral PDM base address */ #define PDM_BASE (0x5010C000u) /** Peripheral PDM base address */ #define PDM_BASE_NS (0x4010C000u) /** Peripheral PDM base pointer */ #define PDM ((PDM_Type *)PDM_BASE) /** Peripheral PDM base pointer */ #define PDM_NS ((PDM_Type *)PDM_BASE_NS) /** Array initializer of PDM peripheral base addresses */ #define PDM_BASE_ADDRS { PDM_BASE } /** Array initializer of PDM peripheral base pointers */ #define PDM_BASE_PTRS { PDM } /** Array initializer of PDM peripheral base addresses */ #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } /** Array initializer of PDM peripheral base pointers */ #define PDM_BASE_PTRS_NS { PDM_NS } #else /** Peripheral PDM base address */ #define PDM_BASE (0x4010C000u) /** Peripheral PDM base pointer */ #define PDM ((PDM_Type *)PDM_BASE) /** Array initializer of PDM peripheral base addresses */ #define PDM_BASE_ADDRS { PDM_BASE } /** Array initializer of PDM peripheral base pointers */ #define PDM_BASE_PTRS { PDM } #endif /** Interrupt vectors for the PDM peripheral type */ #define PDM_IRQS { PDM_EVENT_IRQn } /*! * @} */ /* end of group PDM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PINT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer * @{ */ /** PINT - Register Layout Typedef */ typedef struct { __IO uint32_t ISEL; /**< Pin Interrupt Mode, offset: 0x0 */ __IO uint32_t IENR; /**< Pin Interrupt Level or Rising-Edge Interrupt Enable, offset: 0x4 */ __O uint32_t SIENR; /**< Pin Interrupt Level or Rising-Edge Interrupt Set, offset: 0x8 */ __IO uint32_t CIENR; /**< Pin Interrupt Level (Rising-Edge Interrupt) Clear, offset: 0xC */ __IO uint32_t IENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Enable, offset: 0x10 */ __O uint32_t SIENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Set, offset: 0x14 */ __O uint32_t CIENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Clear, offset: 0x18 */ __IO uint32_t RISE; /**< Pin Interrupt Rising Edge, offset: 0x1C */ __IO uint32_t FALL; /**< Pin Interrupt Falling Edge, offset: 0x20 */ __IO uint32_t IST; /**< Pin Interrupt Status, offset: 0x24 */ __IO uint32_t PMCTRL; /**< Pattern-Match Interrupt Control, offset: 0x28 */ __IO uint32_t PMSRC; /**< Pattern-Match Interrupt Bit-Slice Source, offset: 0x2C */ __IO uint32_t PMCFG; /**< Pattern-Match Interrupt Bit Slice Configuration, offset: 0x30 */ } PINT_Type; /* ---------------------------------------------------------------------------- -- PINT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PINT_Register_Masks PINT Register Masks * @{ */ /*! @name ISEL - Pin Interrupt Mode */ /*! @{ */ #define PINT_ISEL_PMODE_MASK (0xFFU) #define PINT_ISEL_PMODE_SHIFT (0U) /*! PMODE - Interrupt mode * 0b00000000..In bit n configures the interrupt to be edge-sensitive * 0b00000001..In bit n configures the interrupt to be level-sensitive */ #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) /*! @} */ /*! @name IENR - Pin Interrupt Level or Rising-Edge Interrupt Enable */ /*! @{ */ #define PINT_IENR_ENRL_MASK (0xFFU) #define PINT_IENR_ENRL_SHIFT (0U) /*! ENRL - Enables Interrupt * 0b00000000..In bit n disables the corresponding interrupt * 0b00000001..In bit n enables the corresponding interrupt */ #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) /*! @} */ /*! @name SIENR - Pin Interrupt Level or Rising-Edge Interrupt Set */ /*! @{ */ #define PINT_SIENR_SETENRL_MASK (0xFFU) #define PINT_SIENR_SETENRL_SHIFT (0U) /*! SETENRL - Configures IENR * 0b00000000..No operation for interrupt n * 0b00000001..Enable rising edge or level interrupt for interrupt n */ #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) /*! @} */ /*! @name CIENR - Pin Interrupt Level (Rising-Edge Interrupt) Clear */ /*! @{ */ #define PINT_CIENR_CENRL_MASK (0xFFU) #define PINT_CIENR_CENRL_SHIFT (0U) /*! CENRL - Clear bits in IENR * 0b00000000..No operation * 0b00000001..Disable rising edge or level interrupt */ #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) /*! @} */ /*! @name IENF - Pin Interrupt Active Level or Falling-Edge Interrupt Enable */ /*! @{ */ #define PINT_IENF_ENAF_MASK (0xFFU) #define PINT_IENF_ENAF_SHIFT (0U) /*! ENAF - Enables Interrupt * 0b00000000..Disable (set active interrupt level LOW) * 0b00000001..Enable (set active interrupt level HIGH) */ #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) /*! @} */ /*! @name SIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Set */ /*! @{ */ #define PINT_SIENF_SETENAF_MASK (0xFFU) #define PINT_SIENF_SETENAF_SHIFT (0U) /*! SETENAF * 0b00000000..Writes 0 to IENF. * 0b00000001..Select HIGH-active interrupt or enable falling-edge interrupt */ #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) /*! @} */ /*! @name CIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Clear */ /*! @{ */ #define PINT_CIENF_CENAF_MASK (0xFFU) #define PINT_CIENF_CENAF_SHIFT (0U) /*! CENAF - Writes 0 to IENF * 0b00000000..No operation * 0b00000001..LOW-active interrupt selected or falling-edge interrupt disabled */ #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) /*! @} */ /*! @name RISE - Pin Interrupt Rising Edge */ /*! @{ */ #define PINT_RISE_RDET_MASK (0xFFU) #define PINT_RISE_RDET_SHIFT (0U) /*! RDET - Rising-Edge Detect * 0b00000000..Read 0- No rising edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation * 0b00000001..Read 1- Rising edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear rising-edge detection for this pin */ #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) /*! @} */ /*! @name FALL - Pin Interrupt Falling Edge */ /*! @{ */ #define PINT_FALL_FDET_MASK (0xFFU) #define PINT_FALL_FDET_SHIFT (0U) /*! FDET - Falling-Edge Detect * 0b00000000..Read 0- No falling edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation * 0b00000001..Read 1- Falling edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear falling-edge detection for this bit */ #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) /*! @} */ /*! @name IST - Pin Interrupt Status */ /*! @{ */ #define PINT_IST_PSTAT_MASK (0xFFU) #define PINT_IST_PSTAT_SHIFT (0U) /*! PSTAT - Pin Interrupt Status * 0b00000000..Read 0- Interrupt is not requested, Write 0- No operation * 0b00000001..Read 1- Interrupt is requested, Write 1 (edge-sensitive)- clear rising- and falling-edge detection * for this pin, Write 1 (level-sensitive)- switch the active level for this pin in */ #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) /*! @} */ /*! @name PMCTRL - Pattern-Match Interrupt Control */ /*! @{ */ #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) /*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function * or by the pattern-match function. If this value is 0b, interrupts are driven in response to the * standard pin interrupt function. If this value is 1b, interrupts are driven in response to * pattern matches. * 0b0..Pin interrupt * 0b1..Pattern match */ #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified * Boolean expression evaluates to true. If this value is 0b, RXEV output to the CPU is disabled. If * this value is 1b, RXEV output to the CPU is enabled. * 0b0..Disabled * 0b1..Enabled */ #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) #define PINT_PMCTRL_PMAT_SHIFT (24U) /*! PMAT - Pattern Matches * 0b00000001..The corresponding product term is matched by the current state of the appropriate inputs */ #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) /*! @} */ /*! @name PMSRC - Pattern-Match Interrupt Bit-Slice Source */ /*! @{ */ #define PINT_PMSRC_SRC0_MASK (0x700U) #define PINT_PMSRC_SRC0_SHIFT (8U) /*! SRC0 - Selects the input source for bit slice 0 * 0b000..Input 0 (selects the pin identified in PINSEL0) * 0b001..Input 1 (selects the pin identified in PINSEL1) * 0b010..Input 2 (selects the pin identified in PINSEL2) * 0b011..Input 3 (selects the pin identified in PINSEL3) * 0b100..Input 4 (selects the pin identified in PINSEL4) * 0b101..Input 5 (selects the pin identified in PINSEL5) * 0b110..Input 6 (selects the pin identified in PINSEL6) * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) #define PINT_PMSRC_SRC1_MASK (0x3800U) #define PINT_PMSRC_SRC1_SHIFT (11U) /*! SRC1 - Selects the input source for bit slice 1 * 0b000..Input 0 (selects the pin identified in PINSEL0) * 0b001..Input 1 (selects the pin identified in PINSEL1) * 0b010..Input 2 (selects the pin identified in PINSEL2) * 0b011..Input 3 (selects the pin identified in PINSEL3) * 0b100..Input 4 (selects the pin identified in PINSEL4) * 0b101..Input 5 (selects the pin identified in PINSEL5) * 0b110..Input 6 (selects the pin identified in PINSEL6) * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) #define PINT_PMSRC_SRC2_MASK (0x1C000U) #define PINT_PMSRC_SRC2_SHIFT (14U) /*! SRC2 - Selects the input source for bit slice 2 * 0b000..Input 0 (selects the pin identified in PINSEL0) * 0b001..Input 1 (selects the pin identified in PINSEL1) * 0b010..Input 2 (selects the pin identified in PINSEL2) * 0b011..Input 3 (selects the pin identified in PINSEL3) * 0b100..Input 4 (selects the pin identified in PINSEL4) * 0b101..Input 5 (selects the pin identified in PINSEL5) * 0b110..Input 6 (selects the pin identified in PINSEL6) * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) #define PINT_PMSRC_SRC3_MASK (0xE0000U) #define PINT_PMSRC_SRC3_SHIFT (17U) /*! SRC3 - Selects the input source for bit slice 3 * 0b000..Input 0 (selects the pin identified in PINSEL0) * 0b001..Input 1 (selects the pin identified in PINSEL1) * 0b010..Input 2 (selects the pin identified in PINSEL2) * 0b011..Input 3 (selects the pin identified in PINSEL3) * 0b100..Input 4 (selects the pin identified in PINSEL4) * 0b101..Input 5 (selects the pin identified in PINSEL5) * 0b110..Input 6 (selects the pin identified in PINSEL6) * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) #define PINT_PMSRC_SRC4_MASK (0x700000U) #define PINT_PMSRC_SRC4_SHIFT (20U) /*! SRC4 - Selects the input source for bit slice 4 * 0b000..Input 0 (selects the pin identified in PINSEL0) * 0b001..Input 1 (selects the pin identified in PINSEL1) * 0b010..Input 2 (selects the pin identified in PINSEL2) * 0b011..Input 3 (selects the pin identified in PINSEL3) * 0b100..Input 4 (selects the pin identified in PINSEL4) * 0b101..Input 5 (selects the pin identified in PINSEL5) * 0b110..Input 6 (selects the pin identified in PINSEL6) * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) #define PINT_PMSRC_SRC5_MASK (0x3800000U) #define PINT_PMSRC_SRC5_SHIFT (23U) /*! SRC5 - Selects the input source for bit slice 5 * 0b000..Input 0 (selects the pin identified in PINSEL0) * 0b001..Input 1 (selects the pin identified in PINSEL1) * 0b010..Input 2 (selects the pin identified in PINSEL2) * 0b011..Input 3 (selects the pin identified in PINSEL3) * 0b100..Input 4 (selects the pin identified in PINSEL4) * 0b101..Input 5 (selects the pin identified in PINSEL5) * 0b110..Input 6 (selects the pin identified in PINSEL6) * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) #define PINT_PMSRC_SRC6_MASK (0x1C000000U) #define PINT_PMSRC_SRC6_SHIFT (26U) /*! SRC6 - Selects the input source for bit slice 6 * 0b000..Input 0 (selects the pin identified in PINSEL0) * 0b001..Input 1 (selects the pin identified in PINSEL1) * 0b010..Input 2 (selects the pin identified in PINSEL2) * 0b011..Input 3 (selects the pin identified in PINSEL3) * 0b100..Input 4 (selects the pin identified in PINSEL4) * 0b101..Input 5 (selects the pin identified in PINSEL5) * 0b110..Input 6 (selects the pin identified in PINSEL6) * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) #define PINT_PMSRC_SRC7_MASK (0xE0000000U) #define PINT_PMSRC_SRC7_SHIFT (29U) /*! SRC7 - Selects the input source for bit slice 7 * 0b000..Input 0 (selects the pin identified in PINSEL0) * 0b001..Input 1 (selects the pin identified in PINSEL1) * 0b010..Input 2 (selects the pin identified in PINSEL2) * 0b011..Input 3 (selects the pin identified in PINSEL3) * 0b100..Input 4 (selects the pin identified in PINSEL4) * 0b101..Input 5 (selects the pin identified in PINSEL5) * 0b110..Input 6 (selects the pin identified in PINSEL6) * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) /*! @} */ /*! @name PMCFG - Pattern-Match Interrupt Bit Slice Configuration */ /*! @{ */ #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. Slice 0 is not an endpoint. Slice 0 is * the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the * minterm evaluates as true. * 0b0..No effect * 0b1..Endpoint */ #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. Slice 1 is not an endpoint. Slice 1 is * the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the * minterm evaluates as true. * 0b0..No effect * 0b1..Endpoint */ #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. Slice 2 is not an endpoint. Slice 2 is * the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the * minterm evaluates as true. * 0b0..No effect * 0b1..Endpoint */ #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. Slice 3 is not an endpoint. Slice 3 is * the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the * minterm evaluates as true. * 0b0..No effect * 0b1..Endpoint */ #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. Slice 4 is not an endpoint. Slice 4 is * the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the * minterm evaluates as true. * 0b0..No effect * 0b1..Endpoint */ #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. Slice 5 is not an endpoint. Slice 5 is * the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the * minterm evaluates as true. * 0b0..No effect * 0b1..Endpoint */ #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. Slice 6 is not an endpoint. Slice 6 is * the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the * minterm evaluates as true. * 0b0..No effect * 0b1..Endpoint */ #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) #define PINT_PMCFG_CFG0_MASK (0x700U) #define PINT_PMCFG_CFG0_SHIFT (8U) /*! CFG0 - Match Configuration * 0b000..Constant HIGH * 0b001..Sticky rising edge * 0b010..Sticky falling edge * 0b011..Sticky rising or falling edge * 0b100..High level * 0b101..Low level * 0b110..Constant 0 * 0b111..Event (Nonsticky rising or falling edge) */ #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) #define PINT_PMCFG_CFG1_MASK (0x3800U) #define PINT_PMCFG_CFG1_SHIFT (11U) /*! CFG1 - Match Configuration * 0b000..Constant HIGH * 0b001..Sticky rising edge * 0b010..Sticky falling edge * 0b011..Sticky rising or falling edge * 0b100..High level * 0b101..Low level * 0b110..Constant 0 * 0b111..Event (Nonsticky rising or falling edge) */ #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) #define PINT_PMCFG_CFG2_MASK (0x1C000U) #define PINT_PMCFG_CFG2_SHIFT (14U) /*! CFG2 - Match Configuration * 0b000..Constant HIGH * 0b001..Sticky rising edge * 0b010..Sticky falling edge * 0b011..Sticky rising or falling edge * 0b100..High level * 0b101..Low level * 0b110..Constant 0 * 0b111..Event (Nonsticky rising or falling edge) */ #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) #define PINT_PMCFG_CFG3_MASK (0xE0000U) #define PINT_PMCFG_CFG3_SHIFT (17U) /*! CFG3 - Match Configuration * 0b000..Constant HIGH * 0b001..Sticky rising edge * 0b010..Sticky falling edge * 0b011..Sticky rising or falling edge * 0b100..High level * 0b101..Low level * 0b110..Constant 0 * 0b111..Event (Nonsticky rising or falling edge) */ #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) #define PINT_PMCFG_CFG4_MASK (0x700000U) #define PINT_PMCFG_CFG4_SHIFT (20U) /*! CFG4 - Match Configuration * 0b000..Constant HIGH * 0b001..Sticky rising edge * 0b010..Sticky falling edge * 0b011..Sticky rising or falling edge * 0b100..High level * 0b101..Low level * 0b110..Constant 0 * 0b111..Event (Nonsticky rising or falling edge) */ #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) #define PINT_PMCFG_CFG5_MASK (0x3800000U) #define PINT_PMCFG_CFG5_SHIFT (23U) /*! CFG5 - Match Configuration * 0b000..Constant HIGH * 0b001..Sticky rising edge * 0b010..Sticky falling edge * 0b011..Sticky rising or falling edge * 0b100..High level * 0b101..Low level * 0b110..Constant 0 * 0b111..Event (Nonsticky rising or falling edge) */ #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) #define PINT_PMCFG_CFG6_MASK (0x1C000000U) #define PINT_PMCFG_CFG6_SHIFT (26U) /*! CFG6 - Match Configuration * 0b000..Constant HIGH * 0b001..Sticky rising edge * 0b010..Sticky falling edge * 0b011..Sticky rising or falling edge * 0b100..High level * 0b101..Low level * 0b110..Constant 0 * 0b111..Event (Nonsticky rising or falling edge) */ #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) #define PINT_PMCFG_CFG7_MASK (0xE0000000U) #define PINT_PMCFG_CFG7_SHIFT (29U) /*! CFG7 - Match Configuration * 0b000..Constant HIGH * 0b001..Sticky rising edge * 0b010..Sticky falling edge * 0b011..Sticky rising or falling edge * 0b100..High level * 0b101..Low level * 0b110..Constant 0 * 0b111..Event (Nonsticky rising or falling edge) */ #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) /*! @} */ /*! * @} */ /* end of group PINT_Register_Masks */ /* PINT - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral PINT0 base address */ #define PINT0_BASE (0x50004000u) /** Peripheral PINT0 base address */ #define PINT0_BASE_NS (0x40004000u) /** Peripheral PINT0 base pointer */ #define PINT0 ((PINT_Type *)PINT0_BASE) /** Peripheral PINT0 base pointer */ #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) /** Array initializer of PINT peripheral base addresses */ #define PINT_BASE_ADDRS { PINT0_BASE } /** Array initializer of PINT peripheral base pointers */ #define PINT_BASE_PTRS { PINT0 } /** Array initializer of PINT peripheral base addresses */ #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } /** Array initializer of PINT peripheral base pointers */ #define PINT_BASE_PTRS_NS { PINT0_NS } #else /** Peripheral PINT0 base address */ #define PINT0_BASE (0x40004000u) /** Peripheral PINT0 base pointer */ #define PINT0 ((PINT_Type *)PINT0_BASE) /** Array initializer of PINT peripheral base addresses */ #define PINT_BASE_ADDRS { PINT0_BASE } /** Array initializer of PINT peripheral base pointers */ #define PINT_BASE_PTRS { PINT0 } #endif /** Interrupt vectors for the PINT peripheral type */ #define PINT_IRQS { PINT0_IRQn } /* Backward compatibility */ #define PINT PINT0 /*! * @} */ /* end of group PINT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PKC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer * @{ */ /** PKC - Register Layout Typedef */ typedef struct { __I uint32_t PKC_STATUS; /**< Status Register, offset: 0x0 */ __IO uint32_t PKC_CTRL; /**< Control Register, offset: 0x4 */ __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ __IO uint32_t PKC_XYPTR1; /**< X+Y pointer register, parameter set 1, offset: 0x14 */ __IO uint32_t PKC_ZRPTR1; /**< Z+R pointer register, parameter set 1, offset: 0x18 */ __IO uint32_t PKC_LEN1; /**< Length register, parameter set 1, offset: 0x1C */ __IO uint32_t PKC_MODE2; /**< Mode register, parameter set 2, offset: 0x20 */ __IO uint32_t PKC_XYPTR2; /**< X+Y pointer register, parameter set 2, offset: 0x24 */ __IO uint32_t PKC_ZRPTR2; /**< Z+R pointer register, parameter set 2, offset: 0x28 */ __IO uint32_t PKC_LEN2; /**< Length register, parameter set 2, offset: 0x2C */ uint8_t RESERVED_1[16]; __IO uint32_t PKC_UPTR; /**< Universal pointer FUP program, offset: 0x40 */ __IO uint32_t PKC_UPTRT; /**< Universal pointer FUP table, offset: 0x44 */ __IO uint32_t PKC_ULEN; /**< Universal pointer length, offset: 0x48 */ uint8_t RESERVED_2[4]; __IO uint32_t PKC_MCDATA; /**< MC pattern data interface, offset: 0x50 */ uint8_t RESERVED_3[12]; __I uint32_t PKC_VERSION; /**< PKC version register, offset: 0x60 */ uint8_t RESERVED_4[3916]; __O uint32_t PKC_SOFT_RST; /**< Software reset, offset: 0xFB0 */ uint8_t RESERVED_5[12]; __I uint32_t PKC_ACCESS_ERR; /**< Access Error, offset: 0xFC0 */ __O uint32_t PKC_ACCESS_ERR_CLR; /**< Clear Access Error, offset: 0xFC4 */ uint8_t RESERVED_6[16]; __O uint32_t PKC_INT_CLR_ENABLE; /**< Interrupt enable clear, offset: 0xFD8 */ __O uint32_t PKC_INT_SET_ENABLE; /**< Interrupt enable set, offset: 0xFDC */ __I uint32_t PKC_INT_STATUS; /**< Interrupt status, offset: 0xFE0 */ __I uint32_t PKC_INT_ENABLE; /**< Interrupt enable, offset: 0xFE4 */ __O uint32_t PKC_INT_CLR_STATUS; /**< Interrupt status clear, offset: 0xFE8 */ __O uint32_t PKC_INT_SET_STATUS; /**< Interrupt status set, offset: 0xFEC */ uint8_t RESERVED_7[12]; __I uint32_t PKC_MODULE_ID; /**< Module ID, offset: 0xFFC */ } PKC_Type; /* ---------------------------------------------------------------------------- -- PKC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PKC_Register_Masks PKC Register Masks * @{ */ /*! @name PKC_STATUS - Status Register */ /*! @{ */ #define PKC_PKC_STATUS_ACTIV_MASK (0x1U) #define PKC_PKC_STATUS_ACTIV_SHIFT (0U) /*! ACTIV - PKC ACTIV */ #define PKC_PKC_STATUS_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK) #define PKC_PKC_STATUS_CARRY_MASK (0x2U) #define PKC_PKC_STATUS_CARRY_SHIFT (1U) /*! CARRY - Carry overflow flag */ #define PKC_PKC_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK) #define PKC_PKC_STATUS_ZERO_MASK (0x4U) #define PKC_PKC_STATUS_ZERO_SHIFT (2U) /*! ZERO - Zero result flag */ #define PKC_PKC_STATUS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK) #define PKC_PKC_STATUS_GOANY_MASK (0x8U) #define PKC_PKC_STATUS_GOANY_SHIFT (3U) /*! GOANY - Combined GO status flag */ #define PKC_PKC_STATUS_GOANY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK) #define PKC_PKC_STATUS_LOCKED_MASK (0x60U) #define PKC_PKC_STATUS_LOCKED_SHIFT (5U) /*! LOCKED - Parameter set locked */ #define PKC_PKC_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK) /*! @} */ /*! @name PKC_CTRL - Control Register */ /*! @{ */ #define PKC_PKC_CTRL_RESET_MASK (0x1U) #define PKC_PKC_CTRL_RESET_SHIFT (0U) /*! RESET - PKC reset control bit */ #define PKC_PKC_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK) #define PKC_PKC_CTRL_STOP_MASK (0x2U) #define PKC_PKC_CTRL_STOP_SHIFT (1U) /*! STOP - Freeze PKC calculation */ #define PKC_PKC_CTRL_STOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK) #define PKC_PKC_CTRL_GOD1_MASK (0x4U) #define PKC_PKC_CTRL_GOD1_SHIFT (2U) /*! GOD1 - Control bit to start direct operation using parameter set 1 */ #define PKC_PKC_CTRL_GOD1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK) #define PKC_PKC_CTRL_GOD2_MASK (0x8U) #define PKC_PKC_CTRL_GOD2_SHIFT (3U) /*! GOD2 - Control bit to start direct operation using parameter set 2 */ #define PKC_PKC_CTRL_GOD2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK) #define PKC_PKC_CTRL_GOM1_MASK (0x10U) #define PKC_PKC_CTRL_GOM1_SHIFT (4U) /*! GOM1 - Control bit to start MC pattern using parameter set 1 */ #define PKC_PKC_CTRL_GOM1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK) #define PKC_PKC_CTRL_GOM2_MASK (0x20U) #define PKC_PKC_CTRL_GOM2_SHIFT (5U) /*! GOM2 - Control bit to start MC pattern using parameter set 2 */ #define PKC_PKC_CTRL_GOM2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK) #define PKC_PKC_CTRL_GOU_MASK (0x40U) #define PKC_PKC_CTRL_GOU_SHIFT (6U) /*! GOU - Control bit to start pipe operation */ #define PKC_PKC_CTRL_GOU(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK) #define PKC_PKC_CTRL_GF2CONV_MASK (0x80U) #define PKC_PKC_CTRL_GF2CONV_SHIFT (7U) /*! GF2CONV - Convert to GF2 calculation modes */ #define PKC_PKC_CTRL_GF2CONV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK) #define PKC_PKC_CTRL_CLRCACHE_MASK (0x100U) #define PKC_PKC_CTRL_CLRCACHE_SHIFT (8U) /*! CLRCACHE - Clear universal pointer cache */ #define PKC_PKC_CTRL_CLRCACHE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK) #define PKC_PKC_CTRL_CACHE_EN_MASK (0x200U) #define PKC_PKC_CTRL_CACHE_EN_SHIFT (9U) /*! CACHE_EN - Enable universal pointer cache */ #define PKC_PKC_CTRL_CACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK) #define PKC_PKC_CTRL_REDMUL_MASK (0xC00U) #define PKC_PKC_CTRL_REDMUL_SHIFT (10U) /*! REDMUL - Reduced multiplier mode * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 * 0b01..Reserved - Error Generated if selected * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 * 0b11..Reserved - Error Generated if selected */ #define PKC_PKC_CTRL_REDMUL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK) /*! @} */ /*! @name PKC_CFG - Configuration register */ /*! @{ */ #define PKC_PKC_CFG_IDLEOP_MASK (0x1U) #define PKC_PKC_CFG_IDLEOP_SHIFT (0U) #define PKC_PKC_CFG_IDLEOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK) #define PKC_PKC_CFG_RFU1_MASK (0x2U) #define PKC_PKC_CFG_RFU1_SHIFT (1U) #define PKC_PKC_CFG_RFU1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK) #define PKC_PKC_CFG_RFU2_MASK (0x4U) #define PKC_PKC_CFG_RFU2_SHIFT (2U) #define PKC_PKC_CFG_RFU2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK) #define PKC_PKC_CFG_CLKRND_MASK (0x8U) #define PKC_PKC_CFG_CLKRND_SHIFT (3U) #define PKC_PKC_CFG_CLKRND(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK) #define PKC_PKC_CFG_REDMULNOISE_MASK (0x10U) #define PKC_PKC_CFG_REDMULNOISE_SHIFT (4U) #define PKC_PKC_CFG_REDMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK) #define PKC_PKC_CFG_RNDDLY_MASK (0xE0U) #define PKC_PKC_CFG_RNDDLY_SHIFT (5U) #define PKC_PKC_CFG_RNDDLY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK) #define PKC_PKC_CFG_SBXNOISE_MASK (0x100U) #define PKC_PKC_CFG_SBXNOISE_SHIFT (8U) #define PKC_PKC_CFG_SBXNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK) #define PKC_PKC_CFG_ALPNOISE_MASK (0x200U) #define PKC_PKC_CFG_ALPNOISE_SHIFT (9U) #define PKC_PKC_CFG_ALPNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK) #define PKC_PKC_CFG_FMULNOISE_MASK (0x400U) #define PKC_PKC_CFG_FMULNOISE_SHIFT (10U) #define PKC_PKC_CFG_FMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK) /*! @} */ /*! @name PKC_MODE1 - Mode register, parameter set 1 */ /*! @{ */ #define PKC_PKC_MODE1_MODE_MASK (0xFFU) #define PKC_PKC_MODE1_MODE_SHIFT (0U) /*! MODE - Calculation Mode / MC Start address */ #define PKC_PKC_MODE1_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK) /*! @} */ /*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ /*! @{ */ #define PKC_PKC_XYPTR1_XPTR_MASK (0xFFFFU) #define PKC_PKC_XYPTR1_XPTR_SHIFT (0U) /*! XPTR - Start address of X operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR1_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK) #define PKC_PKC_XYPTR1_YPTR_MASK (0xFFFF0000U) #define PKC_PKC_XYPTR1_YPTR_SHIFT (16U) /*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR1_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK) /*! @} */ /*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */ /*! @{ */ #define PKC_PKC_ZRPTR1_ZPTR_MASK (0xFFFFU) #define PKC_PKC_ZRPTR1_ZPTR_SHIFT (0U) /*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ #define PKC_PKC_ZRPTR1_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK) #define PKC_PKC_ZRPTR1_RPTR_MASK (0xFFFF0000U) #define PKC_PKC_ZRPTR1_RPTR_SHIFT (16U) /*! RPTR - Start address of R result in PKCRAM with byte granularity */ #define PKC_PKC_ZRPTR1_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK) /*! @} */ /*! @name PKC_LEN1 - Length register, parameter set 1 */ /*! @{ */ #define PKC_PKC_LEN1_LEN_MASK (0xFFFFU) #define PKC_PKC_LEN1_LEN_SHIFT (0U) /*! LEN - Operand length */ #define PKC_PKC_LEN1_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK) #define PKC_PKC_LEN1_MCLEN_MASK (0xFFFF0000U) #define PKC_PKC_LEN1_MCLEN_SHIFT (16U) /*! MCLEN - Loop counter for microcode pattern */ #define PKC_PKC_LEN1_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK) /*! @} */ /*! @name PKC_MODE2 - Mode register, parameter set 2 */ /*! @{ */ #define PKC_PKC_MODE2_MODE_MASK (0xFFU) #define PKC_PKC_MODE2_MODE_SHIFT (0U) /*! MODE - Calculation Mode / MC Start address */ #define PKC_PKC_MODE2_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK) /*! @} */ /*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ /*! @{ */ #define PKC_PKC_XYPTR2_XPTR_MASK (0xFFFFU) #define PKC_PKC_XYPTR2_XPTR_SHIFT (0U) /*! XPTR - Start address of X operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR2_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK) #define PKC_PKC_XYPTR2_YPTR_MASK (0xFFFF0000U) #define PKC_PKC_XYPTR2_YPTR_SHIFT (16U) /*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR2_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK) /*! @} */ /*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ /*! @{ */ #define PKC_PKC_ZRPTR2_ZPT_MASK (0xFFFFU) #define PKC_PKC_ZRPTR2_ZPT_SHIFT (0U) /*! ZPT - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ #define PKC_PKC_ZRPTR2_ZPT(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPT_SHIFT)) & PKC_PKC_ZRPTR2_ZPT_MASK) #define PKC_PKC_ZRPTR2_RPTR_MASK (0xFFFF0000U) #define PKC_PKC_ZRPTR2_RPTR_SHIFT (16U) /*! RPTR - Start address of R result in PKCRAM with byte granularity */ #define PKC_PKC_ZRPTR2_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK) /*! @} */ /*! @name PKC_LEN2 - Length register, parameter set 2 */ /*! @{ */ #define PKC_PKC_LEN2_LEN_MASK (0xFFFFU) #define PKC_PKC_LEN2_LEN_SHIFT (0U) /*! LEN - Operand length */ #define PKC_PKC_LEN2_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK) #define PKC_PKC_LEN2_MCLEN_MASK (0xFFFF0000U) #define PKC_PKC_LEN2_MCLEN_SHIFT (16U) /*! MCLEN - Loop counter for microcode pattern */ #define PKC_PKC_LEN2_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK) /*! @} */ /*! @name PKC_UPTR - Universal pointer FUP program */ /*! @{ */ #define PKC_PKC_UPTR_PTR_MASK (0xFFFFFFFFU) #define PKC_PKC_UPTR_PTR_SHIFT (0U) /*! PTR - Pointer to start address of PKC FUP program */ #define PKC_PKC_UPTR_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK) /*! @} */ /*! @name PKC_UPTRT - Universal pointer FUP table */ /*! @{ */ #define PKC_PKC_UPTRT_PTR_MASK (0xFFFFFFFFU) #define PKC_PKC_UPTRT_PTR_SHIFT (0U) /*! PTR - Pointer to start address of PKC FUP table */ #define PKC_PKC_UPTRT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK) /*! @} */ /*! @name PKC_ULEN - Universal pointer length */ /*! @{ */ #define PKC_PKC_ULEN_LEN_MASK (0xFFU) #define PKC_PKC_ULEN_LEN_SHIFT (0U) /*! LEN - Length of universal pointer calculation */ #define PKC_PKC_ULEN_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK) /*! @} */ /*! @name PKC_MCDATA - MC pattern data interface */ /*! @{ */ #define PKC_PKC_MCDATA_MCDATA_MASK (0xFFFFFFFFU) #define PKC_PKC_MCDATA_MCDATA_SHIFT (0U) /*! MCDATA - Microcode read/write data */ #define PKC_PKC_MCDATA_MCDATA(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK) /*! @} */ /*! @name PKC_VERSION - PKC version register */ /*! @{ */ #define PKC_PKC_VERSION_MULSIZE_MASK (0x3U) #define PKC_PKC_VERSION_MULSIZE_SHIFT (0U) /*! MULSIZE * 0b01..32-bit multiplier * 0b10..64-bit multiplier * 0b11..128-bit multiplier * 0b10..128-bit multiplier * 0b01..64-bit multiplier */ #define PKC_PKC_VERSION_MULSIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK) #define PKC_PKC_VERSION_MCAVAIL_MASK (0x4U) #define PKC_PKC_VERSION_MCAVAIL_SHIFT (2U) #define PKC_PKC_VERSION_MCAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK) #define PKC_PKC_VERSION_UPAVAIL_MASK (0x8U) #define PKC_PKC_VERSION_UPAVAIL_SHIFT (3U) #define PKC_PKC_VERSION_UPAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK) #define PKC_PKC_VERSION_UPCACHEAVAIL_MASK (0x10U) #define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT (4U) #define PKC_PKC_VERSION_UPCACHEAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK) #define PKC_PKC_VERSION_GF2AVAIL_MASK (0x20U) #define PKC_PKC_VERSION_GF2AVAIL_SHIFT (5U) #define PKC_PKC_VERSION_GF2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK) #define PKC_PKC_VERSION_PARAMNUM_MASK (0xC0U) #define PKC_PKC_VERSION_PARAMNUM_SHIFT (6U) #define PKC_PKC_VERSION_PARAMNUM(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK) #define PKC_PKC_VERSION_SBX0AVAIL_MASK (0x100U) #define PKC_PKC_VERSION_SBX0AVAIL_SHIFT (8U) #define PKC_PKC_VERSION_SBX0AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK) #define PKC_PKC_VERSION_SBX1AVAIL_MASK (0x200U) #define PKC_PKC_VERSION_SBX1AVAIL_SHIFT (9U) #define PKC_PKC_VERSION_SBX1AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK) #define PKC_PKC_VERSION_SBX2AVAIL_MASK (0x400U) #define PKC_PKC_VERSION_SBX2AVAIL_SHIFT (10U) #define PKC_PKC_VERSION_SBX2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK) #define PKC_PKC_VERSION_SBX3AVAIL_MASK (0x800U) #define PKC_PKC_VERSION_SBX3AVAIL_SHIFT (11U) #define PKC_PKC_VERSION_SBX3AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK) #define PKC_PKC_VERSION_MCRECONF_SIZE_MASK (0xFF000U) #define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT (12U) #define PKC_PKC_VERSION_MCRECONF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK) /*! @} */ /*! @name PKC_SOFT_RST - Software reset */ /*! @{ */ #define PKC_PKC_SOFT_RST_SOFT_RST_MASK (0x1U) #define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT (0U) #define PKC_PKC_SOFT_RST_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK) /*! @} */ /*! @name PKC_ACCESS_ERR - Access Error */ /*! @{ */ #define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK (0x1U) #define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT (0U) /*! APB_NOTAV - APB Error */ #define PKC_PKC_ACCESS_ERR_APB_NOTAV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK) #define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK (0x2U) #define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT (1U) /*! APB_WRGMD - APB Error */ #define PKC_PKC_ACCESS_ERR_APB_WRGMD(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK) #define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK (0xF0U) #define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT (4U) #define PKC_PKC_ACCESS_ERR_APB_MASTER(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK) #define PKC_PKC_ACCESS_ERR_AHB_MASK (0x400U) #define PKC_PKC_ACCESS_ERR_AHB_SHIFT (10U) /*! AHB - AHB Error */ #define PKC_PKC_ACCESS_ERR_AHB(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK) #define PKC_PKC_ACCESS_ERR_PKCC_MASK (0x10000U) #define PKC_PKC_ACCESS_ERR_PKCC_SHIFT (16U) #define PKC_PKC_ACCESS_ERR_PKCC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK) #define PKC_PKC_ACCESS_ERR_FDET_MASK (0x20000U) #define PKC_PKC_ACCESS_ERR_FDET_SHIFT (17U) #define PKC_PKC_ACCESS_ERR_FDET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK) #define PKC_PKC_ACCESS_ERR_CTRL_MASK (0x40000U) #define PKC_PKC_ACCESS_ERR_CTRL_SHIFT (18U) #define PKC_PKC_ACCESS_ERR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK) #define PKC_PKC_ACCESS_ERR_UCRC_MASK (0x80000U) #define PKC_PKC_ACCESS_ERR_UCRC_SHIFT (19U) #define PKC_PKC_ACCESS_ERR_UCRC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK) /*! @} */ /*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ /*! @{ */ #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK (0x1U) #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT (0U) #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK) /*! @} */ /*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ /*! @{ */ #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT (0U) #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK) /*! @} */ /*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ /*! @{ */ #define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT (0U) #define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK) /*! @} */ /*! @name PKC_INT_STATUS - Interrupt status */ /*! @{ */ #define PKC_PKC_INT_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT (0U) /*! INT_PDONE - End-of-computation status flag */ #define PKC_PKC_INT_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK) /*! @} */ /*! @name PKC_INT_ENABLE - Interrupt enable */ /*! @{ */ #define PKC_PKC_INT_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT (0U) /*! EN_PDONE - PDONE interrupt enable flag */ #define PKC_PKC_INT_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK) /*! @} */ /*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ /*! @{ */ #define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT (0U) #define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK) /*! @} */ /*! @name PKC_INT_SET_STATUS - Interrupt status set */ /*! @{ */ #define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT (0U) #define PKC_PKC_INT_SET_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK) /*! @} */ /*! @name PKC_MODULE_ID - Module ID */ /*! @{ */ #define PKC_PKC_MODULE_ID_SIZE_MASK (0xFFU) #define PKC_PKC_MODULE_ID_SIZE_SHIFT (0U) #define PKC_PKC_MODULE_ID_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK) #define PKC_PKC_MODULE_ID_MINOR_REV_MASK (0xF00U) #define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT (8U) #define PKC_PKC_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK) #define PKC_PKC_MODULE_ID_MAJOR_REV_MASK (0xF000U) #define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT (12U) #define PKC_PKC_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK) #define PKC_PKC_MODULE_ID_ID_MASK (0xFFFF0000U) #define PKC_PKC_MODULE_ID_ID_SHIFT (16U) #define PKC_PKC_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK) /*! @} */ /*! * @} */ /* end of group PKC_Register_Masks */ /* PKC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral PKC0 base address */ #define PKC0_BASE (0x5002B000u) /** Peripheral PKC0 base address */ #define PKC0_BASE_NS (0x4002B000u) /** Peripheral PKC0 base pointer */ #define PKC0 ((PKC_Type *)PKC0_BASE) /** Peripheral PKC0 base pointer */ #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) /** Array initializer of PKC peripheral base addresses */ #define PKC_BASE_ADDRS { PKC0_BASE } /** Array initializer of PKC peripheral base pointers */ #define PKC_BASE_PTRS { PKC0 } /** Array initializer of PKC peripheral base addresses */ #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } /** Array initializer of PKC peripheral base pointers */ #define PKC_BASE_PTRS_NS { PKC0_NS } #else /** Peripheral PKC0 base address */ #define PKC0_BASE (0x4002B000u) /** Peripheral PKC0 base pointer */ #define PKC0 ((PKC_Type *)PKC0_BASE) /** Array initializer of PKC peripheral base addresses */ #define PKC_BASE_ADDRS { PKC0_BASE } /** Array initializer of PKC peripheral base pointers */ #define PKC_BASE_PTRS { PKC0 } #endif /*! * @} */ /* end of group PKC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PLU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer * @{ */ /** PLU - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x20 */ __IO uint32_t INP_MUX[5]; /**< Input select register for LUTn (0 to 25), Inputx (5 inputs), array offset: 0x0, array step: index*0x20, index2*0x4 */ uint8_t RESERVED_0[12]; } LUT[26]; uint8_t RESERVED_0[1216]; __IO uint32_t LUT_TRUTH[26]; /**< PLU LUT truth table, array offset: 0x800, array step: 0x4 */ uint8_t RESERVED_1[152]; __I uint32_t OUTPUTS; /**< PLU outputs, offset: 0x900 */ __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control, offset: 0x904 */ uint8_t RESERVED_2[760]; __IO uint32_t OUTPUT_MUX[8]; /**< PLU output multiplexer, array offset: 0xC00, array step: 0x4 */ } PLU_Type; /* ---------------------------------------------------------------------------- -- PLU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PLU_Register_Masks PLU Register Masks * @{ */ /*! @name LUT_INP_MUX - Input select register for LUTn (0 to 25), Inputx (5 inputs) */ /*! @{ */ #define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) #define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) /*! LUTn_INPx - Selects the input source to be connected to LUTn_INPx * 0b000000..PLU primary inputs 0 * 0b000001..PLU primary inputs 1 * 0b000010..PLU primary inputs 2 * 0b000011..PLU primary inputs 3 * 0b000100..PLU primary inputs 4 * 0b000101..PLU primary inputs 5 * 0b000110..Output of LUT0 * 0b000111..Output of LUT1 * 0b001000..Output of LUT2 * 0b001001..Output of LUT3 * 0b001010..Output of LUT4 * 0b001011..Output of LUT5 * 0b001100..Output of LUT6 * 0b001101..Output of LUT7 * 0b001110..Output of LUT8 * 0b001111..Output of LUT9 * 0b010000..Output of LUT10 * 0b010001..Output of LUT11 * 0b010010..Output of LUT12 * 0b010011..Output of LUT13 * 0b010100..Output of LUT14 * 0b010101..Output of LUT15 * 0b010110..Output of LUT16 * 0b010111..Output of LUT17 * 0b011000..Output of LUT18 * 0b011001..Output of LUT19 * 0b011010..Output of LUT20 * 0b011011..Output of LUT21 * 0b011100..Output of LUT22 * 0b011101..Output of LUT23 * 0b011110..Output of LUT24 * 0b011111..Output of LUT25 * 0b100000..State[0] * 0b100001..State[1] * 0b100010..State[2] * 0b100011..State[3] */ #define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) /*! @} */ /* The count of PLU_LUT_INP_MUX */ #define PLU_LUT_INP_MUX_COUNT (26U) /* The count of PLU_LUT_INP_MUX */ #define PLU_LUT_INP_MUX_COUNT2 (5U) /*! @name LUT_TRUTH - PLU LUT truth table */ /*! @{ */ #define PLU_LUT_TRUTH_LUT_TRUTH_MASK (0xFFFFFFFFU) #define PLU_LUT_TRUTH_LUT_TRUTH_SHIFT (0U) /*! LUT_TRUTH - LUT truth table */ #define PLU_LUT_TRUTH_LUT_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUT_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUT_TRUTH_MASK) /*! @} */ /* The count of PLU_LUT_TRUTH */ #define PLU_LUT_TRUTH_COUNT (26U) /*! @name OUTPUTS - PLU outputs */ /*! @{ */ #define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) #define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) /*! OUTPUT_STATE - Output state */ #define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) /*! @} */ /*! @name WAKEINT_CTRL - Wakeup interrupt control */ /*! @{ */ #define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) #define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) /*! MASK - Interrupt mask */ #define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) #define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) #define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) /*! FILTER_MODE - Filter Mode * 0b00..Bypass mode * 0b01..Filter 1 clock period * 0b10..Filter 2 clock period * 0b11..Filter 3 clock period */ #define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) #define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) #define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) /*! FILTER_CLKSEL - Filter clock select * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. * 0b01..Selects the 12 MHz FRO as the filter clock. * 0b10..Reserved * 0b11..Reserved */ #define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) #define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) #define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) /*! LATCH_ENABLE - Latch the interrupt */ #define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) #define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) #define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) /*! INTR_CLEAR - Write to clear wakeint_latched */ #define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) /*! @} */ /*! @name OUTPUT_MUX - PLU output multiplexer */ /*! @{ */ #define PLU_OUTPUT_MUX_OUTPUT_MASK (0x1FU) #define PLU_OUTPUT_MUX_OUTPUT_SHIFT (0U) /*! OUTPUT - Selects the source to be connected to PLU output n. * 0b00000..LUT output 0 * 0b00001..LUT output 1 * 0b00010..LUT output 2 * 0b00011..LUT output 3 * 0b00100..LUT output 4 * 0b00101..LUT output 5 * 0b00110..LUT output 6 * 0b00111..LUT output 7 * 0b01000..LUT output 8 * 0b01001..LUT output 9 * 0b01010..LUT output 10 * 0b01011..LUT output 11 * 0b01100..LUT output 12 * 0b01101..LUT output 13 * 0b01110..LUT output 14 * 0b01111..LUT output 15 * 0b10000..LUT output 16 * 0b10001..LUT output 17 * 0b10010..LUT output 18 * 0b10011..LUT output 19 * 0b10100..LUT output 20 * 0b10101..LUT output 21 * 0b10110..LUT output 22 * 0b10111..LUT output 23 * 0b11000..LUT output 24 * 0b11001..LUT output 25 * 0b11010..State[0] * 0b11011..State[1] * 0b11100..State[2] * 0b11101..State[3] */ #define PLU_OUTPUT_MUX_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUT_SHIFT)) & PLU_OUTPUT_MUX_OUTPUT_MASK) /*! @} */ /* The count of PLU_OUTPUT_MUX */ #define PLU_OUTPUT_MUX_COUNT (8U) /*! * @} */ /* end of group PLU_Register_Masks */ /* PLU - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral PLU0 base address */ #define PLU0_BASE (0x50034000u) /** Peripheral PLU0 base address */ #define PLU0_BASE_NS (0x40034000u) /** Peripheral PLU0 base pointer */ #define PLU0 ((PLU_Type *)PLU0_BASE) /** Peripheral PLU0 base pointer */ #define PLU0_NS ((PLU_Type *)PLU0_BASE_NS) /** Array initializer of PLU peripheral base addresses */ #define PLU_BASE_ADDRS { PLU0_BASE } /** Array initializer of PLU peripheral base pointers */ #define PLU_BASE_PTRS { PLU0 } /** Array initializer of PLU peripheral base addresses */ #define PLU_BASE_ADDRS_NS { PLU0_BASE_NS } /** Array initializer of PLU peripheral base pointers */ #define PLU_BASE_PTRS_NS { PLU0_NS } #else /** Peripheral PLU0 base address */ #define PLU0_BASE (0x40034000u) /** Peripheral PLU0 base pointer */ #define PLU0 ((PLU_Type *)PLU0_BASE) /** Array initializer of PLU peripheral base addresses */ #define PLU_BASE_ADDRS { PLU0_BASE } /** Array initializer of PLU peripheral base pointers */ #define PLU_BASE_PTRS { PLU0 } #endif /* Backward compatibility */ #define PLU PLU0 /*! * @} */ /* end of group PLU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PORT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer * @{ */ /** PORT - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ uint8_t RESERVED_0[12]; __O uint32_t GPCLR; /**< Global Pin Control Low, offset: 0x10 */ __O uint32_t GPCHR; /**< Global Pin Control High, offset: 0x14 */ uint8_t RESERVED_1[8]; __IO uint32_t CONFIG; /**< Configuration, offset: 0x20 */ uint8_t RESERVED_2[28]; __I uint32_t EDFR; /**< EFT Detect Flag, offset: 0x40 */ __IO uint32_t EDIER; /**< EFT Detect Interrupt Enable, offset: 0x44 */ __IO uint32_t EDCR; /**< EFT Detect Clear, offset: 0x48 */ uint8_t RESERVED_3[20]; __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ uint8_t RESERVED_4[24]; __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ } PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define PORT_VERID_FEATURE_MASK (0xFFFFU) #define PORT_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Basic implementation */ #define PORT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK) #define PORT_VERID_MINOR_MASK (0xFF0000U) #define PORT_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define PORT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK) #define PORT_VERID_MAJOR_MASK (0xFF000000U) #define PORT_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define PORT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK) /*! @} */ /*! @name GPCLR - Global Pin Control Low */ /*! @{ */ #define PORT_GPCLR_GPWD_MASK (0xFFFFU) #define PORT_GPCLR_GPWD_SHIFT (0U) /*! GPWD - Global Pin Write Data */ #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) #define PORT_GPCLR_GPWE0_MASK (0x10000U) #define PORT_GPCLR_GPWE0_SHIFT (16U) /*! GPWE0 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK) #define PORT_GPCLR_GPWE1_MASK (0x20000U) #define PORT_GPCLR_GPWE1_SHIFT (17U) /*! GPWE1 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK) #define PORT_GPCLR_GPWE2_MASK (0x40000U) #define PORT_GPCLR_GPWE2_SHIFT (18U) /*! GPWE2 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK) #define PORT_GPCLR_GPWE3_MASK (0x80000U) #define PORT_GPCLR_GPWE3_SHIFT (19U) /*! GPWE3 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK) #define PORT_GPCLR_GPWE4_MASK (0x100000U) #define PORT_GPCLR_GPWE4_SHIFT (20U) /*! GPWE4 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK) #define PORT_GPCLR_GPWE5_MASK (0x200000U) #define PORT_GPCLR_GPWE5_SHIFT (21U) /*! GPWE5 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK) #define PORT_GPCLR_GPWE6_MASK (0x400000U) #define PORT_GPCLR_GPWE6_SHIFT (22U) /*! GPWE6 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK) #define PORT_GPCLR_GPWE7_MASK (0x800000U) #define PORT_GPCLR_GPWE7_SHIFT (23U) /*! GPWE7 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK) #define PORT_GPCLR_GPWE8_MASK (0x1000000U) #define PORT_GPCLR_GPWE8_SHIFT (24U) /*! GPWE8 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK) #define PORT_GPCLR_GPWE9_MASK (0x2000000U) #define PORT_GPCLR_GPWE9_SHIFT (25U) /*! GPWE9 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK) #define PORT_GPCLR_GPWE10_MASK (0x4000000U) #define PORT_GPCLR_GPWE10_SHIFT (26U) /*! GPWE10 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK) #define PORT_GPCLR_GPWE11_MASK (0x8000000U) #define PORT_GPCLR_GPWE11_SHIFT (27U) /*! GPWE11 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK) #define PORT_GPCLR_GPWE12_MASK (0x10000000U) #define PORT_GPCLR_GPWE12_SHIFT (28U) /*! GPWE12 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK) #define PORT_GPCLR_GPWE13_MASK (0x20000000U) #define PORT_GPCLR_GPWE13_SHIFT (29U) /*! GPWE13 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK) #define PORT_GPCLR_GPWE14_MASK (0x40000000U) #define PORT_GPCLR_GPWE14_SHIFT (30U) /*! GPWE14 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK) #define PORT_GPCLR_GPWE15_MASK (0x80000000U) #define PORT_GPCLR_GPWE15_SHIFT (31U) /*! GPWE15 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCLR_GPWE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK) /*! @} */ /*! @name GPCHR - Global Pin Control High */ /*! @{ */ #define PORT_GPCHR_GPWD_MASK (0xFFFFU) #define PORT_GPCHR_GPWD_SHIFT (0U) /*! GPWD - Global Pin Write Data */ #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) #define PORT_GPCHR_GPWE16_MASK (0x10000U) #define PORT_GPCHR_GPWE16_SHIFT (16U) /*! GPWE16 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK) #define PORT_GPCHR_GPWE17_MASK (0x20000U) #define PORT_GPCHR_GPWE17_SHIFT (17U) /*! GPWE17 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK) #define PORT_GPCHR_GPWE18_MASK (0x40000U) #define PORT_GPCHR_GPWE18_SHIFT (18U) /*! GPWE18 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK) #define PORT_GPCHR_GPWE19_MASK (0x80000U) #define PORT_GPCHR_GPWE19_SHIFT (19U) /*! GPWE19 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK) #define PORT_GPCHR_GPWE20_MASK (0x100000U) #define PORT_GPCHR_GPWE20_SHIFT (20U) /*! GPWE20 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK) #define PORT_GPCHR_GPWE21_MASK (0x200000U) #define PORT_GPCHR_GPWE21_SHIFT (21U) /*! GPWE21 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK) #define PORT_GPCHR_GPWE22_MASK (0x400000U) #define PORT_GPCHR_GPWE22_SHIFT (22U) /*! GPWE22 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK) #define PORT_GPCHR_GPWE23_MASK (0x800000U) #define PORT_GPCHR_GPWE23_SHIFT (23U) /*! GPWE23 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK) #define PORT_GPCHR_GPWE24_MASK (0x1000000U) #define PORT_GPCHR_GPWE24_SHIFT (24U) /*! GPWE24 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK) #define PORT_GPCHR_GPWE25_MASK (0x2000000U) #define PORT_GPCHR_GPWE25_SHIFT (25U) /*! GPWE25 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK) #define PORT_GPCHR_GPWE26_MASK (0x4000000U) #define PORT_GPCHR_GPWE26_SHIFT (26U) /*! GPWE26 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK) #define PORT_GPCHR_GPWE27_MASK (0x8000000U) #define PORT_GPCHR_GPWE27_SHIFT (27U) /*! GPWE27 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK) #define PORT_GPCHR_GPWE28_MASK (0x10000000U) #define PORT_GPCHR_GPWE28_SHIFT (28U) /*! GPWE28 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK) #define PORT_GPCHR_GPWE29_MASK (0x20000000U) #define PORT_GPCHR_GPWE29_SHIFT (29U) /*! GPWE29 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK) #define PORT_GPCHR_GPWE30_MASK (0x40000000U) #define PORT_GPCHR_GPWE30_SHIFT (30U) /*! GPWE30 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK) #define PORT_GPCHR_GPWE31_MASK (0x80000000U) #define PORT_GPCHR_GPWE31_SHIFT (31U) /*! GPWE31 - Global Pin Write Enable * 0b0..Not updated * 0b1..Updated */ #define PORT_GPCHR_GPWE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK) /*! @} */ /*! @name CONFIG - Configuration */ /*! @{ */ #define PORT_CONFIG_RANGE_MASK (0x1U) #define PORT_CONFIG_RANGE_SHIFT (0U) /*! RANGE - Port Voltage Range * 0b0..1.71 V-3.6 V * 0b1..2.70 V-3.6 V */ #define PORT_CONFIG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK) /*! @} */ /*! @name EDFR - EFT Detect Flag */ /*! @{ */ #define PORT_EDFR_EDF0_MASK (0x1U) #define PORT_EDFR_EDF0_SHIFT (0U) /*! EDF0 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF0(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF0_SHIFT)) & PORT_EDFR_EDF0_MASK) #define PORT_EDFR_EDF1_MASK (0x2U) #define PORT_EDFR_EDF1_SHIFT (1U) /*! EDF1 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF1(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF1_SHIFT)) & PORT_EDFR_EDF1_MASK) #define PORT_EDFR_EDF2_MASK (0x4U) #define PORT_EDFR_EDF2_SHIFT (2U) /*! EDF2 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF2(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF2_SHIFT)) & PORT_EDFR_EDF2_MASK) #define PORT_EDFR_EDF3_MASK (0x8U) #define PORT_EDFR_EDF3_SHIFT (3U) /*! EDF3 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF3(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF3_SHIFT)) & PORT_EDFR_EDF3_MASK) #define PORT_EDFR_EDF4_MASK (0x10U) #define PORT_EDFR_EDF4_SHIFT (4U) /*! EDF4 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF4(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF4_SHIFT)) & PORT_EDFR_EDF4_MASK) #define PORT_EDFR_EDF5_MASK (0x20U) #define PORT_EDFR_EDF5_SHIFT (5U) /*! EDF5 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF5(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF5_SHIFT)) & PORT_EDFR_EDF5_MASK) #define PORT_EDFR_EDF6_MASK (0x40U) #define PORT_EDFR_EDF6_SHIFT (6U) /*! EDF6 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF6(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF6_SHIFT)) & PORT_EDFR_EDF6_MASK) #define PORT_EDFR_EDF7_MASK (0x80U) #define PORT_EDFR_EDF7_SHIFT (7U) /*! EDF7 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF7(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF7_SHIFT)) & PORT_EDFR_EDF7_MASK) #define PORT_EDFR_EDF8_MASK (0x100U) #define PORT_EDFR_EDF8_SHIFT (8U) /*! EDF8 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF8_SHIFT)) & PORT_EDFR_EDF8_MASK) #define PORT_EDFR_EDF9_MASK (0x200U) #define PORT_EDFR_EDF9_SHIFT (9U) /*! EDF9 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF9_SHIFT)) & PORT_EDFR_EDF9_MASK) #define PORT_EDFR_EDF10_MASK (0x400U) #define PORT_EDFR_EDF10_SHIFT (10U) /*! EDF10 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF10_SHIFT)) & PORT_EDFR_EDF10_MASK) #define PORT_EDFR_EDF11_MASK (0x800U) #define PORT_EDFR_EDF11_SHIFT (11U) /*! EDF11 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF11_SHIFT)) & PORT_EDFR_EDF11_MASK) #define PORT_EDFR_EDF12_MASK (0x1000U) #define PORT_EDFR_EDF12_SHIFT (12U) /*! EDF12 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF12_SHIFT)) & PORT_EDFR_EDF12_MASK) #define PORT_EDFR_EDF13_MASK (0x2000U) #define PORT_EDFR_EDF13_SHIFT (13U) /*! EDF13 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF13_SHIFT)) & PORT_EDFR_EDF13_MASK) #define PORT_EDFR_EDF14_MASK (0x4000U) #define PORT_EDFR_EDF14_SHIFT (14U) /*! EDF14 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF14_SHIFT)) & PORT_EDFR_EDF14_MASK) #define PORT_EDFR_EDF15_MASK (0x8000U) #define PORT_EDFR_EDF15_SHIFT (15U) /*! EDF15 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF15_SHIFT)) & PORT_EDFR_EDF15_MASK) #define PORT_EDFR_EDF16_MASK (0x10000U) #define PORT_EDFR_EDF16_SHIFT (16U) /*! EDF16 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF16_SHIFT)) & PORT_EDFR_EDF16_MASK) #define PORT_EDFR_EDF17_MASK (0x20000U) #define PORT_EDFR_EDF17_SHIFT (17U) /*! EDF17 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF17_SHIFT)) & PORT_EDFR_EDF17_MASK) #define PORT_EDFR_EDF18_MASK (0x40000U) #define PORT_EDFR_EDF18_SHIFT (18U) /*! EDF18 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF18_SHIFT)) & PORT_EDFR_EDF18_MASK) #define PORT_EDFR_EDF19_MASK (0x80000U) #define PORT_EDFR_EDF19_SHIFT (19U) /*! EDF19 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF19_SHIFT)) & PORT_EDFR_EDF19_MASK) #define PORT_EDFR_EDF20_MASK (0x100000U) #define PORT_EDFR_EDF20_SHIFT (20U) /*! EDF20 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF20_SHIFT)) & PORT_EDFR_EDF20_MASK) #define PORT_EDFR_EDF21_MASK (0x200000U) #define PORT_EDFR_EDF21_SHIFT (21U) /*! EDF21 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF21_SHIFT)) & PORT_EDFR_EDF21_MASK) #define PORT_EDFR_EDF22_MASK (0x400000U) #define PORT_EDFR_EDF22_SHIFT (22U) /*! EDF22 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF22_SHIFT)) & PORT_EDFR_EDF22_MASK) #define PORT_EDFR_EDF23_MASK (0x800000U) #define PORT_EDFR_EDF23_SHIFT (23U) /*! EDF23 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF23_SHIFT)) & PORT_EDFR_EDF23_MASK) #define PORT_EDFR_EDF24_MASK (0x1000000U) #define PORT_EDFR_EDF24_SHIFT (24U) /*! EDF24 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF24_SHIFT)) & PORT_EDFR_EDF24_MASK) #define PORT_EDFR_EDF25_MASK (0x2000000U) #define PORT_EDFR_EDF25_SHIFT (25U) /*! EDF25 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF25_SHIFT)) & PORT_EDFR_EDF25_MASK) #define PORT_EDFR_EDF26_MASK (0x4000000U) #define PORT_EDFR_EDF26_SHIFT (26U) /*! EDF26 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF26_SHIFT)) & PORT_EDFR_EDF26_MASK) #define PORT_EDFR_EDF27_MASK (0x8000000U) #define PORT_EDFR_EDF27_SHIFT (27U) /*! EDF27 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF27_SHIFT)) & PORT_EDFR_EDF27_MASK) #define PORT_EDFR_EDF28_MASK (0x10000000U) #define PORT_EDFR_EDF28_SHIFT (28U) /*! EDF28 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF28_SHIFT)) & PORT_EDFR_EDF28_MASK) #define PORT_EDFR_EDF29_MASK (0x20000000U) #define PORT_EDFR_EDF29_SHIFT (29U) /*! EDF29 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF29_SHIFT)) & PORT_EDFR_EDF29_MASK) #define PORT_EDFR_EDF30_MASK (0x40000000U) #define PORT_EDFR_EDF30_SHIFT (30U) /*! EDF30 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF30_SHIFT)) & PORT_EDFR_EDF30_MASK) #define PORT_EDFR_EDF31_MASK (0x80000000U) #define PORT_EDFR_EDF31_SHIFT (31U) /*! EDF31 - EFT Detect Flag * 0b0..No EFT event detected * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF31_SHIFT)) & PORT_EDFR_EDF31_MASK) /*! @} */ /*! @name EDIER - EFT Detect Interrupt Enable */ /*! @{ */ #define PORT_EDIER_EDIE0_MASK (0x1U) #define PORT_EDIER_EDIE0_SHIFT (0U) /*! EDIE0 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE0_SHIFT)) & PORT_EDIER_EDIE0_MASK) #define PORT_EDIER_EDIE1_MASK (0x2U) #define PORT_EDIER_EDIE1_SHIFT (1U) /*! EDIE1 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE1_SHIFT)) & PORT_EDIER_EDIE1_MASK) #define PORT_EDIER_EDIE2_MASK (0x4U) #define PORT_EDIER_EDIE2_SHIFT (2U) /*! EDIE2 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE2_SHIFT)) & PORT_EDIER_EDIE2_MASK) #define PORT_EDIER_EDIE3_MASK (0x8U) #define PORT_EDIER_EDIE3_SHIFT (3U) /*! EDIE3 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE3_SHIFT)) & PORT_EDIER_EDIE3_MASK) #define PORT_EDIER_EDIE4_MASK (0x10U) #define PORT_EDIER_EDIE4_SHIFT (4U) /*! EDIE4 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE4_SHIFT)) & PORT_EDIER_EDIE4_MASK) #define PORT_EDIER_EDIE5_MASK (0x20U) #define PORT_EDIER_EDIE5_SHIFT (5U) /*! EDIE5 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE5_SHIFT)) & PORT_EDIER_EDIE5_MASK) #define PORT_EDIER_EDIE6_MASK (0x40U) #define PORT_EDIER_EDIE6_SHIFT (6U) /*! EDIE6 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE6_SHIFT)) & PORT_EDIER_EDIE6_MASK) #define PORT_EDIER_EDIE7_MASK (0x80U) #define PORT_EDIER_EDIE7_SHIFT (7U) /*! EDIE7 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE7_SHIFT)) & PORT_EDIER_EDIE7_MASK) #define PORT_EDIER_EDIE8_MASK (0x100U) #define PORT_EDIER_EDIE8_SHIFT (8U) /*! EDIE8 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE8_SHIFT)) & PORT_EDIER_EDIE8_MASK) #define PORT_EDIER_EDIE9_MASK (0x200U) #define PORT_EDIER_EDIE9_SHIFT (9U) /*! EDIE9 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE9_SHIFT)) & PORT_EDIER_EDIE9_MASK) #define PORT_EDIER_EDIE10_MASK (0x400U) #define PORT_EDIER_EDIE10_SHIFT (10U) /*! EDIE10 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE10_SHIFT)) & PORT_EDIER_EDIE10_MASK) #define PORT_EDIER_EDIE11_MASK (0x800U) #define PORT_EDIER_EDIE11_SHIFT (11U) /*! EDIE11 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE11_SHIFT)) & PORT_EDIER_EDIE11_MASK) #define PORT_EDIER_EDIE12_MASK (0x1000U) #define PORT_EDIER_EDIE12_SHIFT (12U) /*! EDIE12 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE12_SHIFT)) & PORT_EDIER_EDIE12_MASK) #define PORT_EDIER_EDIE13_MASK (0x2000U) #define PORT_EDIER_EDIE13_SHIFT (13U) /*! EDIE13 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE13_SHIFT)) & PORT_EDIER_EDIE13_MASK) #define PORT_EDIER_EDIE14_MASK (0x4000U) #define PORT_EDIER_EDIE14_SHIFT (14U) /*! EDIE14 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE14_SHIFT)) & PORT_EDIER_EDIE14_MASK) #define PORT_EDIER_EDIE15_MASK (0x8000U) #define PORT_EDIER_EDIE15_SHIFT (15U) /*! EDIE15 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE15_SHIFT)) & PORT_EDIER_EDIE15_MASK) #define PORT_EDIER_EDIE16_MASK (0x10000U) #define PORT_EDIER_EDIE16_SHIFT (16U) /*! EDIE16 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE16_SHIFT)) & PORT_EDIER_EDIE16_MASK) #define PORT_EDIER_EDIE17_MASK (0x20000U) #define PORT_EDIER_EDIE17_SHIFT (17U) /*! EDIE17 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE17_SHIFT)) & PORT_EDIER_EDIE17_MASK) #define PORT_EDIER_EDIE18_MASK (0x40000U) #define PORT_EDIER_EDIE18_SHIFT (18U) /*! EDIE18 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE18_SHIFT)) & PORT_EDIER_EDIE18_MASK) #define PORT_EDIER_EDIE19_MASK (0x80000U) #define PORT_EDIER_EDIE19_SHIFT (19U) /*! EDIE19 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE19_SHIFT)) & PORT_EDIER_EDIE19_MASK) #define PORT_EDIER_EDIE20_MASK (0x100000U) #define PORT_EDIER_EDIE20_SHIFT (20U) /*! EDIE20 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE20_SHIFT)) & PORT_EDIER_EDIE20_MASK) #define PORT_EDIER_EDIE21_MASK (0x200000U) #define PORT_EDIER_EDIE21_SHIFT (21U) /*! EDIE21 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE21_SHIFT)) & PORT_EDIER_EDIE21_MASK) #define PORT_EDIER_EDIE22_MASK (0x400000U) #define PORT_EDIER_EDIE22_SHIFT (22U) /*! EDIE22 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE22_SHIFT)) & PORT_EDIER_EDIE22_MASK) #define PORT_EDIER_EDIE23_MASK (0x800000U) #define PORT_EDIER_EDIE23_SHIFT (23U) /*! EDIE23 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE23_SHIFT)) & PORT_EDIER_EDIE23_MASK) #define PORT_EDIER_EDIE24_MASK (0x1000000U) #define PORT_EDIER_EDIE24_SHIFT (24U) /*! EDIE24 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE24_SHIFT)) & PORT_EDIER_EDIE24_MASK) #define PORT_EDIER_EDIE25_MASK (0x2000000U) #define PORT_EDIER_EDIE25_SHIFT (25U) /*! EDIE25 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE25_SHIFT)) & PORT_EDIER_EDIE25_MASK) #define PORT_EDIER_EDIE26_MASK (0x4000000U) #define PORT_EDIER_EDIE26_SHIFT (26U) /*! EDIE26 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE26_SHIFT)) & PORT_EDIER_EDIE26_MASK) #define PORT_EDIER_EDIE27_MASK (0x8000000U) #define PORT_EDIER_EDIE27_SHIFT (27U) /*! EDIE27 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE27_SHIFT)) & PORT_EDIER_EDIE27_MASK) #define PORT_EDIER_EDIE28_MASK (0x10000000U) #define PORT_EDIER_EDIE28_SHIFT (28U) /*! EDIE28 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE28_SHIFT)) & PORT_EDIER_EDIE28_MASK) #define PORT_EDIER_EDIE29_MASK (0x20000000U) #define PORT_EDIER_EDIE29_SHIFT (29U) /*! EDIE29 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE29_SHIFT)) & PORT_EDIER_EDIE29_MASK) #define PORT_EDIER_EDIE30_MASK (0x40000000U) #define PORT_EDIER_EDIE30_SHIFT (30U) /*! EDIE30 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE30_SHIFT)) & PORT_EDIER_EDIE30_MASK) #define PORT_EDIER_EDIE31_MASK (0x80000000U) #define PORT_EDIER_EDIE31_SHIFT (31U) /*! EDIE31 - EFT Detect Interrupt Enable * 0b0..Interrupt not generated upon detection of the EFT event * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE31_SHIFT)) & PORT_EDIER_EDIE31_MASK) /*! @} */ /*! @name EDCR - EFT Detect Clear */ /*! @{ */ #define PORT_EDCR_EDHC_MASK (0x1U) #define PORT_EDCR_EDHC_SHIFT (0U) /*! EDHC - EFT Detect High Clear * 0b0..Does not clear * 0b1..Clears */ #define PORT_EDCR_EDHC(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDHC_SHIFT)) & PORT_EDCR_EDHC_MASK) #define PORT_EDCR_EDLC_MASK (0x2U) #define PORT_EDCR_EDLC_SHIFT (1U) /*! EDLC - EFT Detect Low Clear * 0b0..Does not clear * 0b1..Clears */ #define PORT_EDCR_EDLC(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDLC_SHIFT)) & PORT_EDCR_EDLC_MASK) /*! @} */ /*! @name CALIB0 - Calibration 0 */ /*! @{ */ #define PORT_CALIB0_NCAL_MASK (0x3FU) #define PORT_CALIB0_NCAL_SHIFT (0U) /*! NCAL - Calibration of NMOS Output Driver */ #define PORT_CALIB0_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK) #define PORT_CALIB0_PCAL_MASK (0x3F0000U) #define PORT_CALIB0_PCAL_SHIFT (16U) /*! PCAL - Calibration of PMOS Output Driver */ #define PORT_CALIB0_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK) /*! @} */ /*! @name CALIB1 - Calibration 1 */ /*! @{ */ #define PORT_CALIB1_NCAL_MASK (0x3FU) #define PORT_CALIB1_NCAL_SHIFT (0U) /*! NCAL - Calibration of NMOS Output Driver */ #define PORT_CALIB1_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK) #define PORT_CALIB1_PCAL_MASK (0x3F0000U) #define PORT_CALIB1_PCAL_SHIFT (16U) /*! PCAL - Calibration of PMOS Output Driver */ #define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) /*! @} */ /*! @name PCR - Pin Control 0..Pin Control 31 */ /*! @{ */ #define PORT_PCR_PS_MASK (0x1U) #define PORT_PCR_PS_SHIFT (0U) /*! PS - Pull Select * 0b0..Enables internal pulldown resistor * 0b1..Enables internal pullup resistor */ #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) #define PORT_PCR_PE_MASK (0x2U) #define PORT_PCR_PE_SHIFT (1U) /*! PE - Pull Enable * 0b0..Disables * 0b1..Enables */ #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) #define PORT_PCR_PV_MASK (0x4U) #define PORT_PCR_PV_SHIFT (2U) /*! PV - Pull Value * 0b0..Low * 0b1..High */ #define PORT_PCR_PV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK) #define PORT_PCR_SRE_MASK (0x8U) #define PORT_PCR_SRE_SHIFT (3U) /*! SRE - Slew Rate Enable * 0b0..Fast * 0b1..Slow */ #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) #define PORT_PCR_PFE_MASK (0x10U) #define PORT_PCR_PFE_SHIFT (4U) /*! PFE - Passive Filter Enable * 0b0..Disables * 0b1..Enables */ #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) #define PORT_PCR_ODE_MASK (0x20U) #define PORT_PCR_ODE_SHIFT (5U) /*! ODE - Open Drain Enable * 0b0..Disables * 0b1..Enables */ #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) #define PORT_PCR_DSE_MASK (0x40U) #define PORT_PCR_DSE_SHIFT (6U) /*! DSE - Drive Strength Enable * 0b0..Low * 0b1..High */ #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) #define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define PORT_PCR_MUX_SHIFT (8U) /*! MUX - Pin Multiplex Control * 0b0000..Alternative 0 (GPIO) * 0b0001..Alternative 1 (chip-specific) * 0b0010..Alternative 2 (chip-specific) * 0b0011..Alternative 3 (chip-specific) * 0b0100..Alternative 4 (chip-specific) * 0b0101..Alternative 5 (chip-specific) * 0b0110..Alternative 6 (chip-specific) * 0b0111..Alternative 7 (chip-specific) * 0b1000..Alternative 8 (chip-specific) * 0b1001..Alternative 9 (chip-specific) * 0b1010..Alternative 10 (chip-specific) * 0b1011..Alternative 11 (chip-specific) * 0b1100..Alternative 12 (chip-specific) * 0b1101..Alternative 13 (chip-specific) */ #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define PORT_PCR_IBE_MASK (0x1000U) #define PORT_PCR_IBE_SHIFT (12U) /*! IBE - Input Buffer Enable * 0b0..Disables * 0b1..Enables */ #define PORT_PCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK) #define PORT_PCR_INV_MASK (0x2000U) #define PORT_PCR_INV_SHIFT (13U) /*! INV - Invert Input * 0b0..Does not invert * 0b1..Inverts */ #define PORT_PCR_INV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK) #define PORT_PCR_LK_MASK (0x8000U) #define PORT_PCR_LK_SHIFT (15U) /*! LK - Lock Register * 0b0..Does not lock * 0b1..Locks */ #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) /*! @} */ /* The count of PORT_PCR */ #define PORT_PCR_COUNT (32U) /*! * @} */ /* end of group PORT_Register_Masks */ /* PORT - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral PORT0 base address */ #define PORT0_BASE (0x50116000u) /** Peripheral PORT0 base address */ #define PORT0_BASE_NS (0x40116000u) /** Peripheral PORT0 base pointer */ #define PORT0 ((PORT_Type *)PORT0_BASE) /** Peripheral PORT0 base pointer */ #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) /** Peripheral PORT1 base address */ #define PORT1_BASE (0x50117000u) /** Peripheral PORT1 base address */ #define PORT1_BASE_NS (0x40117000u) /** Peripheral PORT1 base pointer */ #define PORT1 ((PORT_Type *)PORT1_BASE) /** Peripheral PORT1 base pointer */ #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) /** Peripheral PORT2 base address */ #define PORT2_BASE (0x50118000u) /** Peripheral PORT2 base address */ #define PORT2_BASE_NS (0x40118000u) /** Peripheral PORT2 base pointer */ #define PORT2 ((PORT_Type *)PORT2_BASE) /** Peripheral PORT2 base pointer */ #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) /** Peripheral PORT3 base address */ #define PORT3_BASE (0x50119000u) /** Peripheral PORT3 base address */ #define PORT3_BASE_NS (0x40119000u) /** Peripheral PORT3 base pointer */ #define PORT3 ((PORT_Type *)PORT3_BASE) /** Peripheral PORT3 base pointer */ #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) /** Peripheral PORT4 base address */ #define PORT4_BASE (0x5011A000u) /** Peripheral PORT4 base address */ #define PORT4_BASE_NS (0x4011A000u) /** Peripheral PORT4 base pointer */ #define PORT4 ((PORT_Type *)PORT4_BASE) /** Peripheral PORT4 base pointer */ #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) /** Peripheral PORT5 base address */ #define PORT5_BASE (0x50042000u) /** Peripheral PORT5 base address */ #define PORT5_BASE_NS (0x40042000u) /** Peripheral PORT5 base pointer */ #define PORT5 ((PORT_Type *)PORT5_BASE) /** Peripheral PORT5 base pointer */ #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) /** Array initializer of PORT peripheral base addresses */ #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } /** Array initializer of PORT peripheral base addresses */ #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } #else /** Peripheral PORT0 base address */ #define PORT0_BASE (0x40116000u) /** Peripheral PORT0 base pointer */ #define PORT0 ((PORT_Type *)PORT0_BASE) /** Peripheral PORT1 base address */ #define PORT1_BASE (0x40117000u) /** Peripheral PORT1 base pointer */ #define PORT1 ((PORT_Type *)PORT1_BASE) /** Peripheral PORT2 base address */ #define PORT2_BASE (0x40118000u) /** Peripheral PORT2 base pointer */ #define PORT2 ((PORT_Type *)PORT2_BASE) /** Peripheral PORT3 base address */ #define PORT3_BASE (0x40119000u) /** Peripheral PORT3 base pointer */ #define PORT3 ((PORT_Type *)PORT3_BASE) /** Peripheral PORT4 base address */ #define PORT4_BASE (0x4011A000u) /** Peripheral PORT4 base pointer */ #define PORT4 ((PORT_Type *)PORT4_BASE) /** Peripheral PORT5 base address */ #define PORT5_BASE (0x40042000u) /** Peripheral PORT5 base pointer */ #define PORT5 ((PORT_Type *)PORT5_BASE) /** Array initializer of PORT peripheral base addresses */ #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } #endif /*! * @} */ /* end of group PORT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- POWERQUAD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer * @{ */ /** POWERQUAD - Register Layout Typedef */ typedef struct { __IO uint32_t OUTBASE; /**< Output Base, offset: 0x0 */ __IO uint32_t OUTFORMAT; /**< Output Format, offset: 0x4 */ __IO uint32_t TMPBASE; /**< Temporary Base, offset: 0x8 */ __IO uint32_t TMPFORMAT; /**< Temporary Format, offset: 0xC */ __IO uint32_t INABASE; /**< Input A Base, offset: 0x10 */ __IO uint32_t INAFORMAT; /**< Input A Format, offset: 0x14 */ __IO uint32_t INBBASE; /**< Input B Base, offset: 0x18 */ __IO uint32_t INBFORMAT; /**< Input B Format, offset: 0x1C */ uint8_t RESERVED_0[224]; __IO uint32_t CONTROL; /**< Control, offset: 0x100 */ __IO uint32_t LENGTH; /**< Length, offset: 0x104 */ __IO uint32_t CPPRE; /**< Coprocessor Prescale, offset: 0x108 */ __IO uint32_t MISC; /**< Miscellaneous, offset: 0x10C */ __IO uint32_t CURSORY; /**< Cursory, offset: 0x110 */ uint8_t RESERVED_1[108]; __IO uint32_t CORDIC_X; /**< CORDIC Input X, offset: 0x180 */ __IO uint32_t CORDIC_Y; /**< CORDIC Input Y, offset: 0x184 */ __IO uint32_t CORDIC_Z; /**< CORDIC Input Z, offset: 0x188 */ __IO uint32_t ERRSTAT; /**< Error Status, offset: 0x18C */ __IO uint32_t INTREN; /**< Interrupt Enable, offset: 0x190 */ __IO uint32_t EVENTEN; /**< Event Enable, offset: 0x194 */ __IO uint32_t INTRSTAT; /**< Interrupt Status, offset: 0x198 */ uint8_t RESERVED_2[100]; __IO uint32_t GPREG[16]; /**< General Purpose Register Bank n, array offset: 0x200, array step: 0x4 */ __IO uint32_t COMPREG[8]; /**< Compute Register Bank n, array offset: 0x240, array step: 0x4 */ } POWERQUAD_Type; /* ---------------------------------------------------------------------------- -- POWERQUAD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks * @{ */ /*! @name OUTBASE - Output Base */ /*! @{ */ #define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) /*! OUTBASE - Output Region Base Address */ #define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) /*! @} */ /*! @name OUTFORMAT - Output Format */ /*! @{ */ #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) /*! OUT_FORMATINT - Output Internal Format * 0b00..Q15 16-bit fixed-point integer * 0b01..Q31 32-bit fixed-point integer * 0b10..F32 32-bit floating-point format * 0b11.. */ #define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) /*! OUT_FORMATEXT - Output External Format * 0b00..Q15 16-bit fixed-point integer * 0b01..Q31 32-bit fixed-point integer * 0b10..F32 32-bit floating-point format * 0b11.. */ #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) #define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) #define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) /*! OUT_SCALER - 8-bit Scaling Value for Result Data */ #define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) /*! @} */ /*! @name TMPBASE - Temporary Base */ /*! @{ */ #define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) /*! TMPBASE - Base Address for the Temporary Region */ #define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) /*! @} */ /*! @name TMPFORMAT - Temporary Format */ /*! @{ */ #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) /*! TMP_FORMATINT - Temporary Internal Format * 0b00..Q15 16-bit fixed-point integer * 0b01..Q31 32-bit fixed-point integer * 0b10..F32 32-bit floating-point format * 0b11.. */ #define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) /*! TMP_FORMATEXT - Temporary External Format * 0b00..Q15 16-bit fixed-point integer * 0b01..Q31 32-bit fixed-point integer * 0b10..F32 32-bit floating-point format * 0b11.. */ #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) #define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) #define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) /*! TMP_SCALER - Scaling Value for Temporary Data. */ #define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) /*! @} */ /*! @name INABASE - Input A Base */ /*! @{ */ #define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INABASE_INABASE_SHIFT (0U) /*! INABASE - Input A Base */ #define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) /*! @} */ /*! @name INAFORMAT - Input A Format */ /*! @{ */ #define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) #define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) /*! INA_FORMATINT - Input A Internal Format * 0b00..Q15 16-bit fixed-point integer * 0b01..Q31 32-bit fixed-point integer * 0b10..F32 32-bit floating-point format * 0b11.. */ #define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) #define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) #define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) /*! INA_FORMATEXT - Input A External Format * 0b00..Q15 16-bit fixed-point integer * 0b01..Q31 32-bit fixed-point integer * 0b10..F32 32-bit floating-point format * 0b11.. */ #define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) #define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) #define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) /*! INA_SCALER - Input A Scaler Value */ #define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) /*! @} */ /*! @name INBBASE - Input B Base */ /*! @{ */ #define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) /*! INBBASE - Input B Base */ #define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) /*! @} */ /*! @name INBFORMAT - Input B Format */ /*! @{ */ #define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) #define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) /*! INB_FORMATINT - Input B Internal Format * 0b00..Q15 16-bit fixed-point integer * 0b01..Q31 32-bit fixed-point integer * 0b10..F32 32-bit floating-point format * 0b11.. */ #define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) #define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) #define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) /*! INB_FORMATEXT - Input B External Format * 0b00..Q15 16-bit fixed-point integer * 0b01..Q31 32-bit fixed-point integer * 0b10..F32 32-bit floating-point format * 0b11.. */ #define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) #define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) #define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) /*! INB_SCALER - Input B Scaler */ #define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) /*! @} */ /*! @name CONTROL - Control */ /*! @{ */ #define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) #define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) /*! DECODE_OPCODE - Decode Opcode */ #define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) #define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) #define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) /*! DECODE_MACHINE - Decode Machine * 0b0000..Coprocessor * 0b0001..Matrix engine * 0b0010..Transform engine * 0b0011..Filter engine * 0b0101..CORDIC engine * 0b0100, 0b0110-0b1111.. */ #define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) #define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) #define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) /*! INST_BUSY - Instruction Busy * 0b1..Busy * 0b0..Not busy */ #define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) /*! @} */ /*! @name LENGTH - Length */ /*! @{ */ #define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) #define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) /*! INST_LENGTH - Instruction length */ #define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) /*! @} */ /*! @name CPPRE - Coprocessor Prescale */ /*! @{ */ #define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) #define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) /*! CPPRE_IN - Prescaling Input */ #define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) #define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) #define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) /*! CPPRE_OUT - Postscaling Output */ #define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) #define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) #define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) /*! CPPRE_SAT - Saturation * 0b0..No saturation * 0b1..Forces sub-32 bit saturation */ #define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) #define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) #define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) /*! CPPRE_SAT8 - Saturation 8 * 0b0..8 bits * 0b1..16 bits */ #define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) /*! @} */ /*! @name MISC - Miscellaneous */ /*! @{ */ #define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) #define POWERQUAD_MISC_INST_MISC_SHIFT (0U) /*! INST_MISC - Scaling Factor */ #define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) /*! @} */ /*! @name CURSORY - Cursory */ /*! @{ */ #define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) #define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) /*! CURSORY - Cursory Mode * 0b0..Disable cursory mode, full floating-point accuracy (24-bit mantissa + 2 bits before rounding). * 0b1..Enable cursory Mode, 16-bit mantissa (bottom bits are zeroed for inputs and outputs of MACs). */ #define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) /*! @} */ /*! @name CORDIC_X - CORDIC Input X */ /*! @{ */ #define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) /*! CORDIC_X - CORDIC Input X */ #define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) /*! @} */ /*! @name CORDIC_Y - CORDIC Input Y */ /*! @{ */ #define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) /*! CORDIC_Y - CORDIC Input Y */ #define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) /*! @} */ /*! @name CORDIC_Z - CORDIC Input Z */ /*! @{ */ #define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) /*! CORDIC_Z - CORDIC Input Z */ #define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) /*! @} */ /*! @name ERRSTAT - Error Status */ /*! @{ */ #define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) #define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) /*! OVERFLOW - Floating-point Overflow * 0b0..No error * 0b1..Error on floating-point overflow */ #define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) #define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) #define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) /*! NAN - Floating-Point Not-a-Number (NaN) * 0b0..No error * 0b1..Error on floating-point NaN */ #define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) /*! FIXEDOVERFLOW - Fixed-point Overflow * 0b0..No error * 0b1..Error on fixed-point overflow */ #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) #define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) #define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) /*! UNDERFLOW - Underflow * 0b0..No error * 0b1..Error on underflow */ #define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) #define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) #define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) /*! BUSERROR - Bus Error * 0b0..No error * 0b1..Error on bus */ #define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) /*! @} */ /*! @name INTREN - Interrupt Enable */ /*! @{ */ #define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) #define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) /*! INTR_OFLOW - Interrupt Floating-point Overflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) #define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) #define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) /*! INTR_NAN - Interrupt Floating-point NaN * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) #define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) #define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) /*! INTR_FIXED - Interrupt on Fixed-point Overflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) #define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) #define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) /*! INTR_UFLOW - Interrupt on Underflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) #define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) #define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) /*! INTR_BERR - Interrupt on AHBM Bus Error * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) #define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) #define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) /*! INTR_COMP - Interrupt on Instruction Completion * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) /*! @} */ /*! @name EVENTEN - Event Enable */ /*! @{ */ #define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) #define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) /*! EVENT_OFLOW - Event Trigger on Floating-point Overflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ #define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) #define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) #define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) /*! EVENT_NAN - Event Trigger on Floating-Point NaN * 0b0..Disable event trigger * 0b1..Enable event trigger */ #define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) #define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) #define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) /*! EVENT_FIXED - Event Trigger on Fixed-point Overflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ #define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) #define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) #define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) /*! EVENT_UFLOW - Event Trigger on Underflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ #define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) #define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) #define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) /*! EVENT_BERR - Event Trigger on AHBM Bus Error * 0b0..Disable event trigger * 0b1..Enable event trigger */ #define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) #define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) #define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) /*! EVENT_COMP - Event Trigger on Instruction Completion * 0b0..Disable event trigger * 0b1..Enable event trigger */ #define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) /*! @} */ /*! @name INTRSTAT - Interrupt Status */ /*! @{ */ #define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) #define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) /*! INTR_STAT - Interrupt Status * 0b0..No new interrupt * 0b1..Interrupt captured */ #define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) /*! @} */ /*! @name GPREG - General Purpose Register Bank n */ /*! @{ */ #define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) #define POWERQUAD_GPREG_GPREG_SHIFT (0U) /*! GPREG - General Purpose Bank */ #define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) /*! @} */ /* The count of POWERQUAD_GPREG */ #define POWERQUAD_GPREG_COUNT (16U) /*! @name COMPREGS_COMPREG - Compute Register Bank n */ /*! @{ */ #define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) #define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) /*! COMPREG - Compute bank */ #define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) /*! @} */ /* The count of POWERQUAD_COMPREGS_COMPREG */ #define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) /*! * @} */ /* end of group POWERQUAD_Register_Masks */ /* POWERQUAD - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral POWERQUAD base address */ #define POWERQUAD_BASE (0x500BF000u) /** Peripheral POWERQUAD base address */ #define POWERQUAD_BASE_NS (0x400BF000u) /** Peripheral POWERQUAD base pointer */ #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) /** Peripheral POWERQUAD base pointer */ #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) /** Array initializer of POWERQUAD peripheral base addresses */ #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } /** Array initializer of POWERQUAD peripheral base pointers */ #define POWERQUAD_BASE_PTRS { POWERQUAD } /** Array initializer of POWERQUAD peripheral base addresses */ #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } /** Array initializer of POWERQUAD peripheral base pointers */ #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } #else /** Peripheral POWERQUAD base address */ #define POWERQUAD_BASE (0x400BF000u) /** Peripheral POWERQUAD base pointer */ #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) /** Array initializer of POWERQUAD peripheral base addresses */ #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } /** Array initializer of POWERQUAD peripheral base pointers */ #define POWERQUAD_BASE_PTRS { POWERQUAD } #endif /** Interrupt vectors for the POWERQUAD peripheral type */ #define POWERQUAD_IRQS { PQ_IRQn } /*! * @} */ /* end of group POWERQUAD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PUF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer * @{ */ /** PUF - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< Control, offset: 0x0 */ __I uint32_t ORR; /**< Operation Result, offset: 0x4 */ __IO uint32_t SR; /**< Status, offset: 0x8 */ __I uint32_t AR; /**< Allow, offset: 0xC */ __IO uint32_t IER; /**< Interrupt Enable, offset: 0x10 */ __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x14 */ __IO uint32_t ISR; /**< Interrupt Status, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t DATA_DEST; /**< Data Destination, offset: 0x20 */ __IO uint32_t DATA_SRC; /**< Data Source, offset: 0x24 */ uint8_t RESERVED_1[120]; __O uint32_t DIR; /**< Data Input, offset: 0xA0 */ uint8_t RESERVED_2[4]; __I uint32_t DOR; /**< Data Output, offset: 0xA8 */ uint8_t RESERVED_3[20]; __IO uint32_t MISC; /**< Miscellaneous, offset: 0xC0 */ uint8_t RESERVED_4[12]; __IO uint32_t IF_SR; /**< Interface Status, offset: 0xD0 */ uint8_t RESERVED_5[8]; __I uint32_t PSR; /**< PUF Score, offset: 0xDC */ __I uint32_t HW_RUC0; /**< Hardware Restrict User Context 0, offset: 0xE0 */ __I uint32_t HW_RUC1; /**< Hardware Restrict User Context 1, offset: 0xE4 */ uint8_t RESERVED_6[12]; __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ __IO uint32_t SEC_LOCK; /**< Security level lock, offset: 0x104 */ __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ uint8_t RESERVED_7[500]; __IO uint32_t SRAM_CFG; /**< SRAM Configuration, offset: 0x300 */ __I uint32_t SRAM_STATUS; /**< Status, offset: 0x304 */ uint8_t RESERVED_8[208]; __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ __O uint32_t SRAM_INT_SET_ENABLE; /**< Interrupt Enable Set, offset: 0x3DC */ __I uint32_t SRAM_INT_STATUS; /**< Interrupt Status, offset: 0x3E0 */ __I uint32_t SRAM_INT_ENABLE; /**< Interrupt Enable, offset: 0x3E4 */ __O uint32_t SRAM_INT_CLR_STATUS; /**< Interrupt Status Clear, offset: 0x3E8 */ __O uint32_t SRAM_INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ } PUF_Type; /* ---------------------------------------------------------------------------- -- PUF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PUF_Register_Masks PUF Register Masks * @{ */ /*! @name CR - Control */ /*! @{ */ #define PUF_CR_ZEROIZE_MASK (0x1U) #define PUF_CR_ZEROIZE_SHIFT (0U) /*! ZEROIZE - Zeroize operation */ #define PUF_CR_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK) #define PUF_CR_ENROLL_MASK (0x2U) #define PUF_CR_ENROLL_SHIFT (1U) /*! ENROLL - Enroll operation */ #define PUF_CR_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK) #define PUF_CR_START_MASK (0x4U) #define PUF_CR_START_SHIFT (2U) /*! START - Start operation */ #define PUF_CR_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK) #define PUF_CR_RECONSTRUCT_MASK (0x8U) #define PUF_CR_RECONSTRUCT_SHIFT (3U) /*! RECONSTRUCT - Reconstruct operation */ #define PUF_CR_RECONSTRUCT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_RECONSTRUCT_SHIFT)) & PUF_CR_RECONSTRUCT_MASK) #define PUF_CR_STOP_MASK (0x20U) #define PUF_CR_STOP_SHIFT (5U) /*! STOP - Stop operation */ #define PUF_CR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK) #define PUF_CR_GET_KEY_MASK (0x40U) #define PUF_CR_GET_KEY_SHIFT (6U) /*! GET_KEY - Get Key operation */ #define PUF_CR_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK) #define PUF_CR_UNWRAP_MASK (0x80U) #define PUF_CR_UNWRAP_SHIFT (7U) /*! UNWRAP - Unwrap operation */ #define PUF_CR_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK) #define PUF_CR_WRAP_GENERATED_RANDOM_MASK (0x100U) #define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT (8U) /*! WRAP_GENERATED_RANDOM - Wrap Generated Random operation */ #define PUF_CR_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK) #define PUF_CR_WRAP_MASK (0x200U) #define PUF_CR_WRAP_SHIFT (9U) /*! WRAP - Wrap operation */ #define PUF_CR_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK) #define PUF_CR_GENERATE_RANDOM_MASK (0x8000U) #define PUF_CR_GENERATE_RANDOM_SHIFT (15U) /*! GENERATE_RANDOM - Generate Random operation */ #define PUF_CR_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK) #define PUF_CR_TEST_MEMORY_MASK (0x40000000U) #define PUF_CR_TEST_MEMORY_SHIFT (30U) /*! TEST_MEMORY - Test memory operation */ #define PUF_CR_TEST_MEMORY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_MEMORY_SHIFT)) & PUF_CR_TEST_MEMORY_MASK) #define PUF_CR_TEST_PUF_MASK (0x80000000U) #define PUF_CR_TEST_PUF_SHIFT (31U) /*! TEST_PUF - Test PUF operation */ #define PUF_CR_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK) /*! @} */ /*! @name ORR - Operation Result */ /*! @{ */ #define PUF_ORR_RESULT_CODE_MASK (0xFFU) #define PUF_ORR_RESULT_CODE_SHIFT (0U) /*! RESULT_CODE - Result code of last operation * 0b00000000..Indicates that the last operation was successful or operation is in progress. * 0b11110000..Indicates that the AC is not for the current product/version. * 0b11110001..Indicates that the AC in the second phase is not for the current product/version. * 0b11110010..Indicates that the AC is corrupted. * 0b11110011..Indicates that the AC in the second phase is corrupted. * 0b11110100..Indicates that the authentication of the provided AC failed. * 0b11110101..Indicates that the authentication of the provided AC failed in the second phase. * 0b11110110..Indicates that the SRAM PUF quality verification fails. * 0b11110111..Indicates that the incorrect or unsupported context is provided. * 0b11111000..Indicates that a data destination was set that is not allowed according to other settings and the current PUF state. * 0b11111111..Indicates that the PUF SRAM access has failed. */ #define PUF_ORR_RESULT_CODE(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK) #define PUF_ORR_LAST_OPERATION_MASK (0xFF000000U) #define PUF_ORR_LAST_OPERATION_SHIFT (24U) /*! LAST_OPERATION - Last operation type * 0b00000000..Indicates that the operation is in progress. * 0b00000001..Indicates that the last operation was Enroll. * 0b00000010..Indicates that the last operation was Start. * 0b00000011..Indicates that the last operation was Reconstruct * 0b00000101..Indicates that the last operation was Stop. * 0b00000110..Indicates that the last operation was Get Key. * 0b00000111..Indicates that the last operation was Unwrap. * 0b00001000..Indicates that the last operation was Wrap Generated Random. * 0b00001001..Indicates that the last operation was Wrap. * 0b00001111..Indicates that the last operation was Generate Random. * 0b00011110..Indicates that the last operation was Test Memory. * 0b00011111..Indicates that the last operation was Test PUF. * 0b00100000..Indicates that the last operation was Initialization. * 0b00101111..Indicates that the last operation was Zeroize. */ #define PUF_ORR_LAST_OPERATION(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK) /*! @} */ /*! @name SR - Status */ /*! @{ */ #define PUF_SR_BUSY_MASK (0x1U) #define PUF_SR_BUSY_SHIFT (0U) /*! BUSY - Operation in progress */ #define PUF_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK) #define PUF_SR_OK_MASK (0x2U) #define PUF_SR_OK_SHIFT (1U) /*! OK - Last operation successful */ #define PUF_SR_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK) #define PUF_SR_ERROR_MASK (0x4U) #define PUF_SR_ERROR_SHIFT (2U) /*! ERROR - Last operation failed */ #define PUF_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK) #define PUF_SR_ZEROIZED_MASK (0x8U) #define PUF_SR_ZEROIZED_SHIFT (3U) /*! ZEROIZED - Zeroized or Locked state */ #define PUF_SR_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK) #define PUF_SR_REJECTED_MASK (0x10U) #define PUF_SR_REJECTED_SHIFT (4U) /*! REJECTED - Operation rejected */ #define PUF_SR_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK) #define PUF_SR_DI_REQUEST_MASK (0x20U) #define PUF_SR_DI_REQUEST_SHIFT (5U) /*! DI_REQUEST - Indicates the request for data in transfer via the DIR register */ #define PUF_SR_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK) #define PUF_SR_DO_REQUEST_MASK (0x40U) #define PUF_SR_DO_REQUEST_SHIFT (6U) /*! DO_REQUEST - Indicates the request for data out transfer via the DOR register */ #define PUF_SR_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK) /*! @} */ /*! @name AR - Allow */ /*! @{ */ #define PUF_AR_ALLOW_ENROLL_MASK (0x2U) #define PUF_AR_ALLOW_ENROLL_SHIFT (1U) /*! ALLOW_ENROLL - Enroll operation * 0b0..Indicates that the Enroll operation is not allowed * 0b1..Indicates that the Enroll operation is allowed */ #define PUF_AR_ALLOW_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK) #define PUF_AR_ALLOW_START_MASK (0x4U) #define PUF_AR_ALLOW_START_SHIFT (2U) /*! ALLOW_START - Start operation * 0b0..Indicates that the Start operation is not allowed * 0b1..Indicates that the Start operation is allowed */ #define PUF_AR_ALLOW_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK) #define PUF_AR_ALLOW_RECONSTRUCT_MASK (0x8U) #define PUF_AR_ALLOW_RECONSTRUCT_SHIFT (3U) /*! ALLOW_RECONSTRUCT - Reconstruct operation * 0b0..Indicates that the Reconstruct operation is not allowed * 0b1..Indicates that the Reconstruct operation is allowed */ #define PUF_AR_ALLOW_RECONSTRUCT(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_RECONSTRUCT_SHIFT)) & PUF_AR_ALLOW_RECONSTRUCT_MASK) #define PUF_AR_ALLOW_STOP_MASK (0x20U) #define PUF_AR_ALLOW_STOP_SHIFT (5U) /*! ALLOW_STOP - Stop operation * 0b0..Indicates that the Stop operation is not allowed * 0b1..Indicates that the Stop operation is allowed */ #define PUF_AR_ALLOW_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK) #define PUF_AR_ALLOW_GET_KEY_MASK (0x40U) #define PUF_AR_ALLOW_GET_KEY_SHIFT (6U) /*! ALLOW_GET_KEY - Get Key operation * 0b0..Indicates that the Get Key operation is not allowed * 0b1..Indicates that the Get Key operation is allowed */ #define PUF_AR_ALLOW_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK) #define PUF_AR_ALLOW_UNWRAP_MASK (0x80U) #define PUF_AR_ALLOW_UNWRAP_SHIFT (7U) /*! ALLOW_UNWRAP - Unwrap operation * 0b0..Indicates that the Unwrap operation is not allowed * 0b1..Indicates that the Unwrap operation is allowed */ #define PUF_AR_ALLOW_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK) #define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK (0x100U) #define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U) /*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation * 0b0..Indicates that the Wrap Generated Random operation is not allowed * 0b1..Indicates that the Wrap Generated Random operation is allowed */ #define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK) #define PUF_AR_ALLOW_WRAP_MASK (0x200U) #define PUF_AR_ALLOW_WRAP_SHIFT (9U) /*! ALLOW_WRAP - Wrap operation * 0b0..Indicates that the Wrap operation is not allowed * 0b1..Indicates that the Wrap operation is allowed */ #define PUF_AR_ALLOW_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK) #define PUF_AR_ALLOW_GENERATE_RANDOM_MASK (0x8000U) #define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT (15U) /*! ALLOW_GENERATE_RANDOM - Generate Random operation * 0b0..Indicates that the Generate Random operation is not allowed * 0b1..Indicates that the Generate Random operation is allowed */ #define PUF_AR_ALLOW_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK) #define PUF_AR_ALLOW_TEST_MEMORY_MASK (0x40000000U) #define PUF_AR_ALLOW_TEST_MEMORY_SHIFT (30U) /*! ALLOW_TEST_MEMORY * 0b0..Indicates that the Test Memory operation is not allowed * 0b1..Indicates that the Test Memory operation is allowed */ #define PUF_AR_ALLOW_TEST_MEMORY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_MEMORY_SHIFT)) & PUF_AR_ALLOW_TEST_MEMORY_MASK) #define PUF_AR_ALLOW_TEST_PUF_MASK (0x80000000U) #define PUF_AR_ALLOW_TEST_PUF_SHIFT (31U) /*! ALLOW_TEST_PUF - Test PUF operation * 0b0..Test PUF operation is not allowed * 0b1..Test PUF operation is allowed */ #define PUF_AR_ALLOW_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK) /*! @} */ /*! @name IER - Interrupt Enable */ /*! @{ */ #define PUF_IER_INT_EN_MASK (0x1U) #define PUF_IER_INT_EN_SHIFT (0U) /*! INT_EN - Interrupt enable * 0b0..Disables all PUF interrupts * 0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register */ #define PUF_IER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK) /*! @} */ /*! @name IMR - Interrupt Mask */ /*! @{ */ #define PUF_IMR_INT_EN_BUSY_MASK (0x1U) #define PUF_IMR_INT_EN_BUSY_SHIFT (0U) /*! INT_EN_BUSY - Busy interrupt */ #define PUF_IMR_INT_EN_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK) #define PUF_IMR_INT_EN_OK_MASK (0x2U) #define PUF_IMR_INT_EN_OK_SHIFT (1U) /*! INT_EN_OK - Ok interrupt */ #define PUF_IMR_INT_EN_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK) #define PUF_IMR_INT_EN_ERROR_MASK (0x4U) #define PUF_IMR_INT_EN_ERROR_SHIFT (2U) /*! INT_EN_ERROR - Error interrupt */ #define PUF_IMR_INT_EN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK) #define PUF_IMR_INT_EN_ZEROIZED_MASK (0x8U) #define PUF_IMR_INT_EN_ZEROIZED_SHIFT (3U) /*! INT_EN_ZEROIZED - Zeroized interrupt */ #define PUF_IMR_INT_EN_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK) #define PUF_IMR_INT_EN_REJECTED_MASK (0x10U) #define PUF_IMR_INT_EN_REJECTED_SHIFT (4U) /*! INT_EN_REJECTED - Rejected interrupt */ #define PUF_IMR_INT_EN_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK) #define PUF_IMR_INT_EN_DI_REQUEST_MASK (0x20U) #define PUF_IMR_INT_EN_DI_REQUEST_SHIFT (5U) /*! INT_EN_DI_REQUEST - Data in request interrupt */ #define PUF_IMR_INT_EN_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK) #define PUF_IMR_INT_EN_DO_REQUEST_MASK (0x40U) #define PUF_IMR_INT_EN_DO_REQUEST_SHIFT (6U) /*! INT_EN_DO_REQUEST - Data out request interrupt */ #define PUF_IMR_INT_EN_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK) /*! @} */ /*! @name ISR - Interrupt Status */ /*! @{ */ #define PUF_ISR_INT_BUSY_MASK (0x1U) #define PUF_ISR_INT_BUSY_SHIFT (0U) /*! INT_BUSY - Negative edge occurred on Busy */ #define PUF_ISR_INT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK) #define PUF_ISR_INT_OK_MASK (0x2U) #define PUF_ISR_INT_OK_SHIFT (1U) /*! INT_OK - Positive edge occurred on Ok */ #define PUF_ISR_INT_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK) #define PUF_ISR_INT_ERROR_MASK (0x4U) #define PUF_ISR_INT_ERROR_SHIFT (2U) /*! INT_ERROR - Positive edge occurred on Error */ #define PUF_ISR_INT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK) #define PUF_ISR_INT_ZEROIZED_MASK (0x8U) #define PUF_ISR_INT_ZEROIZED_SHIFT (3U) /*! INT_ZEROIZED - Positive edge occurred on Zeroized */ #define PUF_ISR_INT_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK) #define PUF_ISR_INT_REJECTED_MASK (0x10U) #define PUF_ISR_INT_REJECTED_SHIFT (4U) /*! INT_REJECTED - Positive edge occurred on Rejected */ #define PUF_ISR_INT_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK) #define PUF_ISR_INT_DI_REQUEST_MASK (0x20U) #define PUF_ISR_INT_DI_REQUEST_SHIFT (5U) /*! INT_DI_REQUEST - Positive edge occurred on di_request */ #define PUF_ISR_INT_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK) #define PUF_ISR_INT_DO_REQUEST_MASK (0x40U) #define PUF_ISR_INT_DO_REQUEST_SHIFT (6U) /*! INT_DO_REQUEST - Positive edge occurred on do_request */ #define PUF_ISR_INT_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK) /*! @} */ /*! @name DATA_DEST - Data Destination */ /*! @{ */ #define PUF_DATA_DEST_DEST_DOR_MASK (0x1U) #define PUF_DATA_DEST_DEST_DOR_SHIFT (0U) /*! DEST_DOR - Key available via the DOR register */ #define PUF_DATA_DEST_DEST_DOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_DOR_SHIFT)) & PUF_DATA_DEST_DEST_DOR_MASK) #define PUF_DATA_DEST_DEST_SO_MASK (0x2U) #define PUF_DATA_DEST_DEST_SO_SHIFT (1U) /*! DEST_SO - Key available to ELS */ #define PUF_DATA_DEST_DEST_SO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_SO_SHIFT)) & PUF_DATA_DEST_DEST_SO_MASK) /*! @} */ /*! @name DATA_SRC - Data Source */ /*! @{ */ #define PUF_DATA_SRC_SRC_DIR_MASK (0x1U) #define PUF_DATA_SRC_SRC_DIR_SHIFT (0U) /*! SRC_DIR - Data provided via the DIR register */ #define PUF_DATA_SRC_SRC_DIR(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_DIR_SHIFT)) & PUF_DATA_SRC_SRC_DIR_MASK) #define PUF_DATA_SRC_SRC_SI_MASK (0x2U) #define PUF_DATA_SRC_SRC_SI_SHIFT (1U) /*! SRC_SI - Data provided via the SI interface */ #define PUF_DATA_SRC_SRC_SI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_SI_SHIFT)) & PUF_DATA_SRC_SRC_SI_MASK) /*! @} */ /*! @name DIR - Data Input */ /*! @{ */ #define PUF_DIR_DI_MASK (0xFFFFFFFFU) #define PUF_DIR_DI_SHIFT (0U) /*! DI - Input data */ #define PUF_DIR_DI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK) /*! @} */ /*! @name DOR - Data Output */ /*! @{ */ #define PUF_DOR_DO_MASK (0xFFFFFFFFU) #define PUF_DOR_DO_SHIFT (0U) /*! DO - Output data */ #define PUF_DOR_DO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK) /*! @} */ /*! @name MISC - Miscellaneous */ /*! @{ */ #define PUF_MISC_DATA_ENDIANNESS_MASK (0x1U) #define PUF_MISC_DATA_ENDIANNESS_SHIFT (0U) /*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR: * 0b0..Little endian * 0b1..Big endian (default) */ #define PUF_MISC_DATA_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK) /*! @} */ /*! @name IF_SR - Interface Status */ /*! @{ */ #define PUF_IF_SR_APB_ERROR_MASK (0x1U) #define PUF_IF_SR_APB_ERROR_SHIFT (0U) /*! APB_ERROR - APB error */ #define PUF_IF_SR_APB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK) /*! @} */ /*! @name PSR - PUF Score */ /*! @{ */ #define PUF_PSR_PUF_SCORE_MASK (0xFU) #define PUF_PSR_PUF_SCORE_SHIFT (0U) /*! PUF_SCORE - Provides the PUF score obtained during the last Test PUF, Enroll or Start operation. */ #define PUF_PSR_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK) /*! @} */ /*! @name HW_RUC0 - Hardware Restrict User Context 0 */ /*! @{ */ #define PUF_HW_RUC0_LC_STATE_MASK (0xFFU) #define PUF_HW_RUC0_LC_STATE_SHIFT (0U) /*! LC_STATE - Life cycle state based restrictions * 0b00000011..OEM Develop * 0b00000111..OEM Develop 2 * 0b00001111..OEM In-field * 0b00011111..OEM Field return * 0b00111111..NXP Field Return/Failure Analysis * 0b11001111..In-field Locked * 0b11111111..Bricked */ #define PUF_HW_RUC0_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK) #define PUF_HW_RUC0_BOOT_STATE_MASK (0xFFFF00U) #define PUF_HW_RUC0_BOOT_STATE_SHIFT (8U) /*! BOOT_STATE - Temporal boot state */ #define PUF_HW_RUC0_BOOT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK) #define PUF_HW_RUC0_CPU0_DEBUG_MASK (0x1000000U) #define PUF_HW_RUC0_CPU0_DEBUG_SHIFT (24U) /*! CPU0_DEBUG - Disable key access when debugger is attached to CPU0 after power-up */ #define PUF_HW_RUC0_CPU0_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK) #define PUF_HW_RUC0_COOLFLUX_DEBUG_MASK (0x2000000U) #define PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT (25U) /*! COOLFLUX_DEBUG - Disable key access when debugger is attached to COOLFLUX after power-up */ #define PUF_HW_RUC0_COOLFLUX_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT)) & PUF_HW_RUC0_COOLFLUX_DEBUG_MASK) #define PUF_HW_RUC0_dsp_debug_MASK (0x4000000U) #define PUF_HW_RUC0_dsp_debug_SHIFT (26U) /*! dsp_debug - DSP debug status. */ #define PUF_HW_RUC0_dsp_debug(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_dsp_debug_SHIFT)) & PUF_HW_RUC0_dsp_debug_MASK) #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) #define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT (28U) /*! ACCESS_LEVEL - Restrict the key access based on TrustZone security level */ #define PUF_HW_RUC0_ACCESS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK) /*! @} */ /*! @name HW_RUC1 - Hardware Restrict User Context 1 */ /*! @{ */ #define PUF_HW_RUC1_APP_CTX_MASK (0xFFFFFFFFU) #define PUF_HW_RUC1_APP_CTX_SHIFT (0U) /*! APP_CTX - Application customizable context */ #define PUF_HW_RUC1_APP_CTX(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK) /*! @} */ /*! @name HW_INFO - Hardware Information */ /*! @{ */ #define PUF_HW_INFO_CONFIG_WRAP_MASK (0x1000000U) #define PUF_HW_INFO_CONFIG_WRAP_SHIFT (24U) /*! CONFIG_WRAP - Wrap configuration * 0b0..Indicates that Wrap is not included * 0b1..Indicates that Wrap is included */ #define PUF_HW_INFO_CONFIG_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK) #define PUF_HW_INFO_CONFIG_TYPE_MASK (0xF0000000U) #define PUF_HW_INFO_CONFIG_TYPE_SHIFT (28U) /*! CONFIG_TYPE - PUF configuration * 0b0001..Indicates that PUF configuration is Safe. * 0b0010..Indicates that PUF configuration is Plus. */ #define PUF_HW_INFO_CONFIG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK) /*! @} */ /*! @name HW_ID - Hardware Identifier */ /*! @{ */ #define PUF_HW_ID_HW_ID_MASK (0xFFFFFFFFU) #define PUF_HW_ID_HW_ID_SHIFT (0U) /*! HW_ID - Provides the hardware identifier */ #define PUF_HW_ID_HW_ID(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK) /*! @} */ /*! @name HW_VER - Hardware Version */ /*! @{ */ #define PUF_HW_VER_HW_REV_MASK (0xFFU) #define PUF_HW_VER_HW_REV_SHIFT (0U) /*! HW_REV - Provides the hardware version, patch part */ #define PUF_HW_VER_HW_REV(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK) #define PUF_HW_VER_HW_VERSION_MINOR_MASK (0xFF00U) #define PUF_HW_VER_HW_VERSION_MINOR_SHIFT (8U) /*! HW_VERSION_MINOR - Provides the hardware version, minor part */ #define PUF_HW_VER_HW_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK) #define PUF_HW_VER_HW_VERSION_MAJOR_MASK (0xFF0000U) #define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT (16U) /*! HW_VERSION_MAJOR - Provides the hardware version, major part */ #define PUF_HW_VER_HW_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK) /*! @} */ /*! @name CONFIG - PUF command blocking configuration */ /*! @{ */ #define PUF_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) #define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) /*! DIS_PUF_ENROLL - Disable PUF enroll command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK) #define PUF_CONFIG_DIS_PUF_START_MASK (0x4U) #define PUF_CONFIG_DIS_PUF_START_SHIFT (2U) /*! DIS_PUF_START - Disable PUF start command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK) #define PUF_CONFIG_DIS_PUF_STOP_MASK (0x20U) #define PUF_CONFIG_DIS_PUF_STOP_SHIFT (5U) /*! DIS_PUF_STOP - Disable PUF stop command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK) #define PUF_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) #define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) /*! DIS_PUF_GET_KEY - Disable PUF get key command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK) #define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) #define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) /*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) #define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) #define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) /*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) #define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) #define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) /*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK) #define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) #define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) /*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) #define PUF_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) #define PUF_CONFIG_DIS_PUF_TEST_SHIFT (31U) /*! DIS_PUF_TEST - Disable PUF test command * 0b0..Command enabled * 0b1..Command disabled */ #define PUF_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK) /*! @} */ /*! @name SEC_LOCK - Security level lock */ /*! @{ */ #define PUF_SEC_LOCK_SEC_LEVEL_MASK (0x3U) #define PUF_SEC_LOCK_SEC_LEVEL_SHIFT (0U) /*! SEC_LEVEL - Security Level * 0b00..Non-secure and non-privileged Master * 0b01..Non-secure and privileged Master * 0b10..Secure and non-privileged Master * 0b11..Secure and privileged Master */ #define PUF_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK) #define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) #define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) /*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level * 0b00..Secure and privileged Master * 0b01..Secure and non-privileged Master * 0b10..Non-secure and privileged Master * 0b11..Non-secure and non-privileged Master */ #define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) #define PUF_SEC_LOCK_PATTERN_MASK (0xFFF0U) #define PUF_SEC_LOCK_PATTERN_SHIFT (4U) /*! PATTERN - Pattern */ #define PUF_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK) /*! @} */ /*! @name APP_CTX_MASK - Application defined context mask */ /*! @{ */ #define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) #define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) /*! APP_CTX_MASK - Application defined context */ #define PUF_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK) /*! @} */ /*! @name SRAM_CFG - SRAM Configuration */ /*! @{ */ #define PUF_SRAM_CFG_ENABLE_MASK (0x1U) #define PUF_SRAM_CFG_ENABLE_SHIFT (0U) /*! ENABLE - PUF SRAM Controller activation * 0b0..Disabled * 0b1..Enabled */ #define PUF_SRAM_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK) #define PUF_SRAM_CFG_CKGATING_MASK (0x4U) #define PUF_SRAM_CFG_CKGATING_SHIFT (2U) /*! CKGATING - PUF SRAM Clock Gating control * 0b0..Disabled * 0b1..Enabled */ #define PUF_SRAM_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK) /*! @} */ /*! @name SRAM_STATUS - Status */ /*! @{ */ #define PUF_SRAM_STATUS_READY_MASK (0x1U) #define PUF_SRAM_STATUS_READY_SHIFT (0U) /*! READY - PUF SRAM Controller State */ #define PUF_SRAM_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_STATUS_READY_SHIFT)) & PUF_SRAM_STATUS_READY_MASK) /*! @} */ /*! @name SRAM_INT_CLR_ENABLE - Interrupt Enable Clear */ /*! @{ */ #define PUF_SRAM_INT_CLR_ENABLE_READY_MASK (0x1U) #define PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT (0U) /*! READY - READY Interrupt Enable clear */ #define PUF_SRAM_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_READY_MASK) #define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) #define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) /*! APB_ERR - APB_ERR Interrupt Enable clear */ #define PUF_SRAM_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK) /*! @} */ /*! @name SRAM_INT_SET_ENABLE - Interrupt Enable Set */ /*! @{ */ #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) #define PUF_SRAM_INT_SET_ENABLE_READY_SHIFT (0U) /*! READY - READY Interrupt Enable set */ #define PUF_SRAM_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK) #define PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK (0x2U) #define PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT (1U) /*! APB_ERR - APB_ERR Interrupt Enable set */ #define PUF_SRAM_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK) /*! @} */ /*! @name SRAM_INT_STATUS - Interrupt Status */ /*! @{ */ #define PUF_SRAM_INT_STATUS_READY_MASK (0x1U) #define PUF_SRAM_INT_STATUS_READY_SHIFT (0U) /*! READY - READY Interrupt Status */ #define PUF_SRAM_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_READY_SHIFT)) & PUF_SRAM_INT_STATUS_READY_MASK) #define PUF_SRAM_INT_STATUS_APB_ERR_MASK (0x2U) #define PUF_SRAM_INT_STATUS_APB_ERR_SHIFT (1U) /*! APB_ERR - APB_ERR Interrupt Status */ #define PUF_SRAM_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_STATUS_APB_ERR_MASK) /*! @} */ /*! @name SRAM_INT_ENABLE - Interrupt Enable */ /*! @{ */ #define PUF_SRAM_INT_ENABLE_READY_MASK (0x1U) #define PUF_SRAM_INT_ENABLE_READY_SHIFT (0U) /*! READY - READY Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define PUF_SRAM_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK) #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK (0x2U) #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT (1U) /*! SRAM_APB_ERR - APB_ERR Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK) /*! @} */ /*! @name SRAM_INT_CLR_STATUS - Interrupt Status Clear */ /*! @{ */ #define PUF_SRAM_INT_CLR_STATUS_READY_MASK (0x1U) #define PUF_SRAM_INT_CLR_STATUS_READY_SHIFT (0U) /*! READY - READY Interrupt Status clear */ #define PUF_SRAM_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_READY_MASK) #define PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK (0x2U) #define PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT (1U) /*! APB_ERR - APB_ERR Interrupt Status Clear * 0b0..No effect * 0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware */ #define PUF_SRAM_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK) /*! @} */ /*! @name SRAM_INT_SET_STATUS - Interrupt Status set */ /*! @{ */ #define PUF_SRAM_INT_SET_STATUS_READY_MASK (0x1U) #define PUF_SRAM_INT_SET_STATUS_READY_SHIFT (0U) /*! READY - READY Interrupt Status set */ #define PUF_SRAM_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_INT_SET_STATUS_READY_MASK) #define PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK (0x2U) #define PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT (1U) /*! APB_ERR - APB_ERR Interrupt Status Set * 0b0..No effect * 0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware */ #define PUF_SRAM_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK) /*! @} */ /*! * @} */ /* end of group PUF_Register_Masks */ /* PUF - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral PUF base address */ #define PUF_BASE (0x5002C000u) /** Peripheral PUF base address */ #define PUF_BASE_NS (0x4002C000u) /** Peripheral PUF base pointer */ #define PUF ((PUF_Type *)PUF_BASE) /** Peripheral PUF base pointer */ #define PUF_NS ((PUF_Type *)PUF_BASE_NS) /** Peripheral PUF_ALIAS1 base address */ #define PUF_ALIAS1_BASE (0x5002D000u) /** Peripheral PUF_ALIAS1 base address */ #define PUF_ALIAS1_BASE_NS (0x4002D000u) /** Peripheral PUF_ALIAS1 base pointer */ #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) /** Peripheral PUF_ALIAS1 base pointer */ #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) /** Peripheral PUF_ALIAS2 base address */ #define PUF_ALIAS2_BASE (0x5002E000u) /** Peripheral PUF_ALIAS2 base address */ #define PUF_ALIAS2_BASE_NS (0x4002E000u) /** Peripheral PUF_ALIAS2 base pointer */ #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) /** Peripheral PUF_ALIAS2 base pointer */ #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) /** Peripheral PUF_ALIAS3 base address */ #define PUF_ALIAS3_BASE (0x5002F000u) /** Peripheral PUF_ALIAS3 base address */ #define PUF_ALIAS3_BASE_NS (0x4002F000u) /** Peripheral PUF_ALIAS3 base pointer */ #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) /** Peripheral PUF_ALIAS3 base pointer */ #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) /** Array initializer of PUF peripheral base addresses */ #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } /** Array initializer of PUF peripheral base pointers */ #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } /** Array initializer of PUF peripheral base addresses */ #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } /** Array initializer of PUF peripheral base pointers */ #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } #else /** Peripheral PUF base address */ #define PUF_BASE (0x4002C000u) /** Peripheral PUF base pointer */ #define PUF ((PUF_Type *)PUF_BASE) /** Peripheral PUF_ALIAS1 base address */ #define PUF_ALIAS1_BASE (0x4002D000u) /** Peripheral PUF_ALIAS1 base pointer */ #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) /** Peripheral PUF_ALIAS2 base address */ #define PUF_ALIAS2_BASE (0x4002E000u) /** Peripheral PUF_ALIAS2 base pointer */ #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) /** Peripheral PUF_ALIAS3 base address */ #define PUF_ALIAS3_BASE (0x4002F000u) /** Peripheral PUF_ALIAS3 base pointer */ #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) /** Array initializer of PUF peripheral base addresses */ #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } /** Array initializer of PUF peripheral base pointers */ #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } #endif /*! * @} */ /* end of group PUF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PWM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer * @{ */ /** PWM - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x60 */ __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ uint8_t RESERVED_0[2]; __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ __IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ uint8_t RESERVED_1[2]; __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */ __IO uint16_t CAPTFILTA; /**< Capture PWM_A Input Filter Register, array offset: 0x5A, array step: 0x60 */ __IO uint16_t CAPTFILTB; /**< Capture PWM_B Input Filter Register, array offset: 0x5C, array step: 0x60 */ __IO uint16_t CAPTFILTX; /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */ } SM[4]; __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ } PWM_Type; /* ---------------------------------------------------------------------------- -- PWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PWM_Register_Masks PWM Register Masks * @{ */ /*! @name CNT - Counter Register */ /*! @{ */ #define PWM_CNT_CNT_MASK (0xFFFFU) #define PWM_CNT_CNT_SHIFT (0U) /*! CNT - Counter Register Bits */ #define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) /*! @} */ /* The count of PWM_CNT */ #define PWM_CNT_COUNT (4U) /*! @name INIT - Initial Count Register */ /*! @{ */ #define PWM_INIT_INIT_MASK (0xFFFFU) #define PWM_INIT_INIT_SHIFT (0U) /*! INIT - Initial Count Register Bits */ #define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) /*! @} */ /* The count of PWM_INIT */ #define PWM_INIT_COUNT (4U) /*! @name CTRL2 - Control 2 Register */ /*! @{ */ #define PWM_CTRL2_CLK_SEL_MASK (0x3U) #define PWM_CTRL2_CLK_SEL_SHIFT (0U) /*! CLK_SEL - Clock Source Select * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This * setting should not be used in submodule 0 as it forces the clock to logic 0. * 0b11..Reserved */ #define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) #define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) #define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) /*! RELOAD_SEL - Reload Source Select * 0b0..The local RELOAD signal is used to reload registers. * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used * in submodule 0 as it forces the RELOAD signal to logic 0. */ #define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) #define PWM_CTRL2_FORCE_SEL_MASK (0x38U) #define PWM_CTRL2_FORCE_SEL_SHIFT (3U) /*! FORCE_SEL - Force Select * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in * submodule 0 as it holds the FORCE OUTPUT signal to logic 0. * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should * not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. * 0b100..The local sync signal from this submodule is used to force updates. * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in * submodule0 as it holds the FORCE OUTPUT signal to logic 0. * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. */ #define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) #define PWM_CTRL2_FORCE_MASK (0x40U) #define PWM_CTRL2_FORCE_SHIFT (6U) /*! FORCE - Force Initialization */ #define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) #define PWM_CTRL2_FRCEN_MASK (0x80U) #define PWM_CTRL2_FRCEN_SHIFT (7U) /*! FRCEN - Force Enable * 0b0..Initialization from a FORCE_OUT is disabled. * 0b1..Initialization from a FORCE_OUT is enabled. */ #define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) #define PWM_CTRL2_INIT_SEL_MASK (0x300U) #define PWM_CTRL2_INIT_SEL_SHIFT (8U) /*! INIT_SEL - Initialization Control Select * 0b00..Local sync (PWM_X) causes initialization. * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as * it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload * occurs. * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. * 0b11..EXT_SYNC causes initialization. */ #define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) #define PWM_CTRL2_PWMX_INIT_MASK (0x400U) #define PWM_CTRL2_PWMX_INIT_SHIFT (10U) /*! PWMX_INIT - PWM_X Initial Value */ #define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) #define PWM_CTRL2_PWM45_INIT_MASK (0x800U) #define PWM_CTRL2_PWM45_INIT_SHIFT (11U) /*! PWM45_INIT - PWM45 Initial Value */ #define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) #define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) #define PWM_CTRL2_PWM23_INIT_SHIFT (12U) /*! PWM23_INIT - PWM23 Initial Value */ #define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) #define PWM_CTRL2_INDEP_MASK (0x2000U) #define PWM_CTRL2_INDEP_SHIFT (13U) /*! INDEP - Independent or Complementary Pair Operation * 0b0..PWM_A and PWM_B form a complementary PWM pair. * 0b1..PWM_A and PWM_B outputs are independent PWMs. */ #define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) #define PWM_CTRL2_DBGEN_MASK (0x8000U) #define PWM_CTRL2_DBGEN_SHIFT (15U) /*! DBGEN - Debug Enable */ #define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) /*! @} */ /* The count of PWM_CTRL2 */ #define PWM_CTRL2_COUNT (4U) /*! @name CTRL - Control Register */ /*! @{ */ #define PWM_CTRL_DBLEN_MASK (0x1U) #define PWM_CTRL_DBLEN_SHIFT (0U) /*! DBLEN - Double Switching Enable * 0b0..Double switching disabled. * 0b1..Double switching enabled. */ #define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) #define PWM_CTRL_DBLX_MASK (0x2U) #define PWM_CTRL_DBLX_SHIFT (1U) /*! DBLX - PWM_X Double Switching Enable * 0b0..PWM_X double pulse disabled. * 0b1..PWM_X double pulse enabled. */ #define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) #define PWM_CTRL_LDMOD_MASK (0x4U) #define PWM_CTRL_LDMOD_SHIFT (2U) /*! LDMOD - Load Mode Select * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. * In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF]. */ #define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) #define PWM_CTRL_SPLIT_MASK (0x8U) #define PWM_CTRL_SPLIT_SHIFT (3U) /*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B * 0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses. * 0b1..DBLPWM is split to PWM_A and PWM_B. */ #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) #define PWM_CTRL_PRSC_MASK (0x70U) #define PWM_CTRL_PRSC_SHIFT (4U) /*! PRSC - Prescaler * 0b000..Prescaler 1 * 0b001..Prescaler 2 * 0b010..Prescaler 4 * 0b011..Prescaler 8 * 0b100..Prescaler 16 * 0b101..Prescaler 32 * 0b110..Prescaler 64 * 0b111..Prescaler 128 */ #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) #define PWM_CTRL_COMPMODE_MASK (0x80U) #define PWM_CTRL_COMPMODE_SHIFT (7U) /*! COMPMODE - Compare Mode * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A * output that is high at the end of a period maintains this state until a match with VAL3 clears the output * in the following period. * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register * values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. */ #define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) #define PWM_CTRL_DT_MASK (0x300U) #define PWM_CTRL_DT_SHIFT (8U) /*! DT - Deadtime */ #define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) #define PWM_CTRL_FULL_MASK (0x400U) #define PWM_CTRL_FULL_SHIFT (10U) /*! FULL - Full Cycle Reload * 0b0..Full-cycle reloads disabled. * 0b1..Full-cycle reloads enabled. */ #define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) #define PWM_CTRL_HALF_MASK (0x800U) #define PWM_CTRL_HALF_SHIFT (11U) /*! HALF - Half Cycle Reload * 0b0..Half-cycle reloads disabled. * 0b1..Half-cycle reloads enabled. */ #define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) #define PWM_CTRL_LDFQ_MASK (0xF000U) #define PWM_CTRL_LDFQ_SHIFT (12U) /*! LDFQ - Load Frequency * 0b0000..Every PWM opportunity * 0b0001..Every 2 PWM opportunities * 0b0010..Every 3 PWM opportunities * 0b0011..Every 4 PWM opportunities * 0b0100..Every 5 PWM opportunities * 0b0101..Every 6 PWM opportunities * 0b0110..Every 7 PWM opportunities * 0b0111..Every 8 PWM opportunities * 0b1000..Every 9 PWM opportunities * 0b1001..Every 10 PWM opportunities * 0b1010..Every 11 PWM opportunities * 0b1011..Every 12 PWM opportunities * 0b1100..Every 13 PWM opportunities * 0b1101..Every 14 PWM opportunities * 0b1110..Every 15 PWM opportunities * 0b1111..Every 16 PWM opportunities */ #define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) /*! @} */ /* The count of PWM_CTRL */ #define PWM_CTRL_COUNT (4U) /*! @name VAL0 - Value Register 0 */ /*! @{ */ #define PWM_VAL0_VAL0_MASK (0xFFFFU) #define PWM_VAL0_VAL0_SHIFT (0U) /*! VAL0 - Value 0 */ #define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) /*! @} */ /* The count of PWM_VAL0 */ #define PWM_VAL0_COUNT (4U) /*! @name FRACVAL1 - Fractional Value Register 1 */ /*! @{ */ #define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) #define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) /*! FRACVAL1 - Fractional Value 1 */ #define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) /*! @} */ /* The count of PWM_FRACVAL1 */ #define PWM_FRACVAL1_COUNT (4U) /*! @name VAL1 - Value Register 1 */ /*! @{ */ #define PWM_VAL1_VAL1_MASK (0xFFFFU) #define PWM_VAL1_VAL1_SHIFT (0U) /*! VAL1 - Value 1 */ #define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) /*! @} */ /* The count of PWM_VAL1 */ #define PWM_VAL1_COUNT (4U) /*! @name FRACVAL2 - Fractional Value Register 2 */ /*! @{ */ #define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) #define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) /*! FRACVAL2 - Fractional Value 2 */ #define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) /*! @} */ /* The count of PWM_FRACVAL2 */ #define PWM_FRACVAL2_COUNT (4U) /*! @name VAL2 - Value Register 2 */ /*! @{ */ #define PWM_VAL2_VAL2_MASK (0xFFFFU) #define PWM_VAL2_VAL2_SHIFT (0U) /*! VAL2 - Value 2 */ #define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) /*! @} */ /* The count of PWM_VAL2 */ #define PWM_VAL2_COUNT (4U) /*! @name FRACVAL3 - Fractional Value Register 3 */ /*! @{ */ #define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) #define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) /*! FRACVAL3 - Fractional Value 3 */ #define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) /*! @} */ /* The count of PWM_FRACVAL3 */ #define PWM_FRACVAL3_COUNT (4U) /*! @name VAL3 - Value Register 3 */ /*! @{ */ #define PWM_VAL3_VAL3_MASK (0xFFFFU) #define PWM_VAL3_VAL3_SHIFT (0U) /*! VAL3 - Value 3 */ #define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) /*! @} */ /* The count of PWM_VAL3 */ #define PWM_VAL3_COUNT (4U) /*! @name FRACVAL4 - Fractional Value Register 4 */ /*! @{ */ #define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) #define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) /*! FRACVAL4 - Fractional Value 4 */ #define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) /*! @} */ /* The count of PWM_FRACVAL4 */ #define PWM_FRACVAL4_COUNT (4U) /*! @name VAL4 - Value Register 4 */ /*! @{ */ #define PWM_VAL4_VAL4_MASK (0xFFFFU) #define PWM_VAL4_VAL4_SHIFT (0U) /*! VAL4 - Value 4 */ #define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) /*! @} */ /* The count of PWM_VAL4 */ #define PWM_VAL4_COUNT (4U) /*! @name FRACVAL5 - Fractional Value Register 5 */ /*! @{ */ #define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) #define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) /*! FRACVAL5 - Fractional Value 5 */ #define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) /*! @} */ /* The count of PWM_FRACVAL5 */ #define PWM_FRACVAL5_COUNT (4U) /*! @name VAL5 - Value Register 5 */ /*! @{ */ #define PWM_VAL5_VAL5_MASK (0xFFFFU) #define PWM_VAL5_VAL5_SHIFT (0U) /*! VAL5 - Value 5 */ #define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) /*! @} */ /* The count of PWM_VAL5 */ #define PWM_VAL5_COUNT (4U) /*! @name FRCTRL - Fractional Control Register */ /*! @{ */ #define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) #define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) /*! FRAC1_EN - Fractional Cycle PWM Period Enable * 0b0..Disable fractional cycle length for the PWM period. * 0b1..Enable fractional cycle length for the PWM period. */ #define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) #define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) #define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) /*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A * 0b0..Disable fractional cycle placement for PWM_A. * 0b1..Enable fractional cycle placement for PWM_A. */ #define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) #define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) #define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) /*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B * 0b0..Disable fractional cycle placement for PWM_B. * 0b1..Enable fractional cycle placement for PWM_B. */ #define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) #define PWM_FRCTRL_TEST_MASK (0x8000U) #define PWM_FRCTRL_TEST_SHIFT (15U) /*! TEST - Test Status Bit */ #define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) /*! @} */ /* The count of PWM_FRCTRL */ #define PWM_FRCTRL_COUNT (4U) /*! @name OCTRL - Output Control Register */ /*! @{ */ #define PWM_OCTRL_PWMXFS_MASK (0x3U) #define PWM_OCTRL_PWMXFS_SHIFT (0U) /*! PWMXFS - PWM_X Fault State * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. * 0b10, 0b11..Output is put in a high-impedance state. */ #define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) #define PWM_OCTRL_PWMBFS_MASK (0xCU) #define PWM_OCTRL_PWMBFS_SHIFT (2U) /*! PWMBFS - PWM_B Fault State * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. * 0b10, 0b11..Output is put in a high-impedance state. */ #define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) #define PWM_OCTRL_PWMAFS_MASK (0x30U) #define PWM_OCTRL_PWMAFS_SHIFT (4U) /*! PWMAFS - PWM_A Fault State * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. * 0b10, 0b11..Output is put in a high-impedance state. */ #define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) #define PWM_OCTRL_POLX_MASK (0x100U) #define PWM_OCTRL_POLX_SHIFT (8U) /*! POLX - PWM_X Output Polarity * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. */ #define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) #define PWM_OCTRL_POLB_MASK (0x200U) #define PWM_OCTRL_POLB_SHIFT (9U) /*! POLB - PWM_B Output Polarity * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. */ #define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) #define PWM_OCTRL_POLA_MASK (0x400U) #define PWM_OCTRL_POLA_SHIFT (10U) /*! POLA - PWM_A Output Polarity * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. */ #define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) #define PWM_OCTRL_PWMX_IN_MASK (0x2000U) #define PWM_OCTRL_PWMX_IN_SHIFT (13U) /*! PWMX_IN - PWM_X Input */ #define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) #define PWM_OCTRL_PWMB_IN_MASK (0x4000U) #define PWM_OCTRL_PWMB_IN_SHIFT (14U) /*! PWMB_IN - PWM_B Input */ #define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) #define PWM_OCTRL_PWMA_IN_MASK (0x8000U) #define PWM_OCTRL_PWMA_IN_SHIFT (15U) /*! PWMA_IN - PWM_A Input */ #define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) /*! @} */ /* The count of PWM_OCTRL */ #define PWM_OCTRL_COUNT (4U) /*! @name STS - Status Register */ /*! @{ */ #define PWM_STS_CMPF_MASK (0x3FU) #define PWM_STS_CMPF_SHIFT (0U) /*! CMPF - Compare Flags * 0b000000..No compare event has occurred for a particular VALx value. * 0b000001..A compare event has occurred for a particular VALx value. */ #define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) #define PWM_STS_CFX0_MASK (0x40U) #define PWM_STS_CFX0_SHIFT (6U) /*! CFX0 - Capture Flag X0 */ #define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) #define PWM_STS_CFX1_MASK (0x80U) #define PWM_STS_CFX1_SHIFT (7U) /*! CFX1 - Capture Flag X1 */ #define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) #define PWM_STS_CFB0_MASK (0x100U) #define PWM_STS_CFB0_SHIFT (8U) /*! CFB0 - Capture Flag B0 */ #define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) #define PWM_STS_CFB1_MASK (0x200U) #define PWM_STS_CFB1_SHIFT (9U) /*! CFB1 - Capture Flag B1 */ #define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) #define PWM_STS_CFA0_MASK (0x400U) #define PWM_STS_CFA0_SHIFT (10U) /*! CFA0 - Capture Flag A0 */ #define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) #define PWM_STS_CFA1_MASK (0x800U) #define PWM_STS_CFA1_SHIFT (11U) /*! CFA1 - Capture Flag A1 */ #define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) #define PWM_STS_RF_MASK (0x1000U) #define PWM_STS_RF_SHIFT (12U) /*! RF - Reload Flag * 0b0..No new reload cycle since last STS[RF] clearing * 0b1..New reload cycle since last STS[RF] clearing */ #define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) #define PWM_STS_REF_MASK (0x2000U) #define PWM_STS_REF_SHIFT (13U) /*! REF - Reload Error Flag * 0b0..No reload error occurred. * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. */ #define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) #define PWM_STS_RUF_MASK (0x4000U) #define PWM_STS_RUF_SHIFT (14U) /*! RUF - Registers Updated Flag * 0b0..No register update has occurred since last reload. * 0b1..At least one of the double buffered registers has been updated since the last reload. */ #define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) /*! @} */ /* The count of PWM_STS */ #define PWM_STS_COUNT (4U) /*! @name INTEN - Interrupt Enable Register */ /*! @{ */ #define PWM_INTEN_CMPIE_MASK (0x3FU) #define PWM_INTEN_CMPIE_SHIFT (0U) /*! CMPIE - Compare Interrupt Enables * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. */ #define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) #define PWM_INTEN_CX0IE_MASK (0x40U) #define PWM_INTEN_CX0IE_SHIFT (6U) /*! CX0IE - Capture X 0 Interrupt Enable * 0b0..Interrupt request disabled for STS[CFX0]. * 0b1..Interrupt request enabled for STS[CFX0]. */ #define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) #define PWM_INTEN_CX1IE_MASK (0x80U) #define PWM_INTEN_CX1IE_SHIFT (7U) /*! CX1IE - Capture X 1 Interrupt Enable * 0b0..Interrupt request disabled for STS[CFX1]. * 0b1..Interrupt request enabled for STS[CFX1]. */ #define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) #define PWM_INTEN_CB0IE_MASK (0x100U) #define PWM_INTEN_CB0IE_SHIFT (8U) /*! CB0IE - Capture B 0 Interrupt Enable * 0b0..Interrupt request disabled for STS[CFB0]. * 0b1..Interrupt request enabled for STS[CFB0]. */ #define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) #define PWM_INTEN_CB1IE_MASK (0x200U) #define PWM_INTEN_CB1IE_SHIFT (9U) /*! CB1IE - Capture B 1 Interrupt Enable * 0b0..Interrupt request disabled for STS[CFB1]. * 0b1..Interrupt request enabled for STS[CFB1]. */ #define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) #define PWM_INTEN_CA0IE_MASK (0x400U) #define PWM_INTEN_CA0IE_SHIFT (10U) /*! CA0IE - Capture A 0 Interrupt Enable * 0b0..Interrupt request disabled for STS[CFA0]. * 0b1..Interrupt request enabled for STS[CFA0]. */ #define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) #define PWM_INTEN_CA1IE_MASK (0x800U) #define PWM_INTEN_CA1IE_SHIFT (11U) /*! CA1IE - Capture A 1 Interrupt Enable * 0b0..Interrupt request disabled for STS[CFA1] * 0b1..Interrupt request enabled for STS[CFA1] */ #define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) #define PWM_INTEN_RIE_MASK (0x1000U) #define PWM_INTEN_RIE_SHIFT (12U) /*! RIE - Reload Interrupt Enable * 0b0..STS[RF] CPU interrupt requests disabled * 0b1..STS[RF] CPU interrupt requests enabled */ #define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) #define PWM_INTEN_REIE_MASK (0x2000U) #define PWM_INTEN_REIE_SHIFT (13U) /*! REIE - Reload Error Interrupt Enable * 0b0..STS[REF] CPU interrupt requests disabled * 0b1..STS[REF] CPU interrupt requests enabled */ #define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) /*! @} */ /* The count of PWM_INTEN */ #define PWM_INTEN_COUNT (4U) /*! @name DMAEN - DMA Enable Register */ /*! @{ */ #define PWM_DMAEN_CX0DE_MASK (0x1U) #define PWM_DMAEN_CX0DE_SHIFT (0U) /*! CX0DE - Capture X0 FIFO DMA Enable */ #define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) #define PWM_DMAEN_CX1DE_MASK (0x2U) #define PWM_DMAEN_CX1DE_SHIFT (1U) /*! CX1DE - Capture X1 FIFO DMA Enable */ #define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) #define PWM_DMAEN_CB0DE_MASK (0x4U) #define PWM_DMAEN_CB0DE_SHIFT (2U) /*! CB0DE - Capture B0 FIFO DMA Enable */ #define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) #define PWM_DMAEN_CB1DE_MASK (0x8U) #define PWM_DMAEN_CB1DE_SHIFT (3U) /*! CB1DE - Capture B1 FIFO DMA Enable */ #define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) #define PWM_DMAEN_CA0DE_MASK (0x10U) #define PWM_DMAEN_CA0DE_SHIFT (4U) /*! CA0DE - Capture A0 FIFO DMA Enable */ #define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) #define PWM_DMAEN_CA1DE_MASK (0x20U) #define PWM_DMAEN_CA1DE_SHIFT (5U) /*! CA1DE - Capture A1 FIFO DMA Enable */ #define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) #define PWM_DMAEN_CAPTDE_MASK (0xC0U) #define PWM_DMAEN_CAPTDE_SHIFT (6U) /*! CAPTDE - Capture DMA Enable Source Select * 0b00..Read DMA requests disabled. * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which * watermark(s) the DMA request is sensitive. * 0b10..A local synchronization (VAL1 matches counter) sets the read DMA request. * 0b11..A local reload (STS[RF] being set) sets the read DMA request. */ #define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) #define PWM_DMAEN_FAND_MASK (0x100U) #define PWM_DMAEN_FAND_SHIFT (8U) /*! FAND - FIFO Watermark AND Control * 0b0..Selected FIFO watermarks are OR'ed together. * 0b1..Selected FIFO watermarks are AND'ed together. */ #define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) #define PWM_DMAEN_VALDE_MASK (0x200U) #define PWM_DMAEN_VALDE_SHIFT (9U) /*! VALDE - Value Registers DMA Enable * 0b0..DMA write requests disabled * 0b1..Enabled */ #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) /*! @} */ /* The count of PWM_DMAEN */ #define PWM_DMAEN_COUNT (4U) /*! @name TCTRL - Output Trigger Control Register */ /*! @{ */ #define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) #define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) /*! OUT_TRIG_EN - Output Trigger Enables * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. */ #define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) #define PWM_TCTRL_TRGFRQ_MASK (0x1000U) #define PWM_TCTRL_TRGFRQ_SHIFT (12U) /*! TRGFRQ - Trigger Frequency * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM * is not reloaded every period due to CTRL[LDFQ] being non-zero. */ #define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) #define PWM_TCTRL_PWBOT1_MASK (0x4000U) #define PWM_TCTRL_PWBOT1_SHIFT (14U) /*! PWBOT1 - Mux Output Trigger 1 Source Select * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. * 0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port. */ #define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) #define PWM_TCTRL_PWAOT0_MASK (0x8000U) #define PWM_TCTRL_PWAOT0_SHIFT (15U) /*! PWAOT0 - Mux Output Trigger 0 Source Select * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. * 0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port. */ #define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) /*! @} */ /* The count of PWM_TCTRL */ #define PWM_TCTRL_COUNT (4U) /*! @name DISMAP - Fault Disable Mapping Register 0 */ /*! @{ */ #define PWM_DISMAP_DIS0A_MASK (0xFU) #define PWM_DISMAP_DIS0A_SHIFT (0U) /*! DIS0A - PWM_A Fault Disable Mask 0 */ #define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) #define PWM_DISMAP_DIS0B_MASK (0xF0U) #define PWM_DISMAP_DIS0B_SHIFT (4U) /*! DIS0B - PWM_B Fault Disable Mask 0 */ #define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) #define PWM_DISMAP_DIS0X_MASK (0xF00U) #define PWM_DISMAP_DIS0X_SHIFT (8U) /*! DIS0X - PWM_X Fault Disable Mask 0 */ #define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) /*! @} */ /* The count of PWM_DISMAP */ #define PWM_DISMAP_COUNT (4U) /* The count of PWM_DISMAP */ #define PWM_DISMAP_COUNT2 (1U) /*! @name DTCNT0 - Deadtime Count Register 0 */ /*! @{ */ #define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) #define PWM_DTCNT0_DTCNT0_SHIFT (0U) /*! DTCNT0 - Deadtime Count Register 0 */ #define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) /*! @} */ /* The count of PWM_DTCNT0 */ #define PWM_DTCNT0_COUNT (4U) /*! @name DTCNT1 - Deadtime Count Register 1 */ /*! @{ */ #define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) #define PWM_DTCNT1_DTCNT1_SHIFT (0U) /*! DTCNT1 - Deadtime Count Register 1 */ #define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) /*! @} */ /* The count of PWM_DTCNT1 */ #define PWM_DTCNT1_COUNT (4U) /*! @name CAPTCTRLA - Capture Control A Register */ /*! @{ */ #define PWM_CAPTCTRLA_ARMA_MASK (0x1U) #define PWM_CAPTCTRLA_ARMA_SHIFT (0U) /*! ARMA - Arm A * 0b0..Input capture operation is disabled. * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. */ #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) /*! ONESHOTA - One Shot Mode A * 0b0..Free Running * 0b1..One Shot */ #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) /*! EDGA0 - Edge A 0 * 0b00..Disabled * 0b01..Capture falling edges * 0b10..Capture rising edges * 0b11..Capture any edge */ #define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) #define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) #define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) /*! EDGA1 - Edge A 1 * 0b00..Disabled * 0b01..Capture falling edges * 0b10..Capture rising edges * 0b11..Capture any edge */ #define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) #define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) /*! INP_SELA - Input Select A * 0b0..Raw PWM_A input signal selected as source. * 0b1..Edge Counter */ #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) /*! EDGCNTA_EN - Edge Counter A Enable * 0b0..Edge counter disabled and held in reset * 0b1..Edge counter enabled */ #define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) #define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) #define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) /*! CFAWM - Capture A FIFOs Water Mark */ #define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) #define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) #define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) /*! CA0CNT - Capture A0 FIFO Word Count */ #define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) #define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) #define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) /*! CA1CNT - Capture A1 FIFO Word Count */ #define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) /*! @} */ /* The count of PWM_CAPTCTRLA */ #define PWM_CAPTCTRLA_COUNT (4U) /*! @name CAPTCOMPA - Capture Compare A Register */ /*! @{ */ #define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) #define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) /*! EDGCMPA - Edge Compare A */ #define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) #define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) #define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) /*! EDGCNTA - Edge Counter A */ #define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) /*! @} */ /* The count of PWM_CAPTCOMPA */ #define PWM_CAPTCOMPA_COUNT (4U) /*! @name CAPTCTRLB - Capture Control B Register */ /*! @{ */ #define PWM_CAPTCTRLB_ARMB_MASK (0x1U) #define PWM_CAPTCTRLB_ARMB_SHIFT (0U) /*! ARMB - Arm B * 0b0..Input capture operation is disabled. * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. */ #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) /*! ONESHOTB - One Shot Mode B * 0b0..Free Running * 0b1..One Shot */ #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) /*! EDGB0 - Edge B 0 * 0b00..Disabled * 0b01..Capture falling edges * 0b10..Capture rising edges * 0b11..Capture any edge */ #define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) #define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) #define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) /*! EDGB1 - Edge B 1 * 0b00..Disabled * 0b01..Capture falling edges * 0b10..Capture rising edges * 0b11..Capture any edge */ #define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) #define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) /*! INP_SELB - Input Select B * 0b0..Raw PWM_B input signal selected as source. * 0b1..Edge Counter */ #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) /*! EDGCNTB_EN - Edge Counter B Enable * 0b0..Edge counter disabled and held in reset * 0b1..Edge counter enabled */ #define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) #define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) #define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) /*! CFBWM - Capture B FIFOs Water Mark */ #define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) #define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) #define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) /*! CB0CNT - Capture B0 FIFO Word Count */ #define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) #define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) #define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) /*! CB1CNT - Capture B1 FIFO Word Count */ #define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) /*! @} */ /* The count of PWM_CAPTCTRLB */ #define PWM_CAPTCTRLB_COUNT (4U) /*! @name CAPTCOMPB - Capture Compare B Register */ /*! @{ */ #define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) #define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) /*! EDGCMPB - Edge Compare B */ #define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) #define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) #define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) /*! EDGCNTB - Edge Counter B */ #define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) /*! @} */ /* The count of PWM_CAPTCOMPB */ #define PWM_CAPTCOMPB_COUNT (4U) /*! @name CAPTCTRLX - Capture Control X Register */ /*! @{ */ #define PWM_CAPTCTRLX_ARMX_MASK (0x1U) #define PWM_CAPTCTRLX_ARMX_SHIFT (0U) /*! ARMX - Arm X * 0b0..Input capture operation is disabled. * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. */ #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) /*! ONESHOTX - One Shot Mode Aux * 0b0..Free Running * 0b1..One Shot */ #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) /*! EDGX0 - Edge X 0 * 0b00..Disabled * 0b01..Capture falling edges * 0b10..Capture rising edges * 0b11..Capture any edge */ #define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) #define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) #define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) /*! EDGX1 - Edge X 1 * 0b00..Disabled * 0b01..Capture falling edges * 0b10..Capture rising edges * 0b11..Capture any edge */ #define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) #define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) /*! INP_SELX - Input Select X * 0b0..Raw PWM_X input signal selected as source. * 0b1..Edge Counter */ #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) /*! EDGCNTX_EN - Edge Counter X Enable * 0b0..Edge counter disabled and held in reset * 0b1..Edge counter enabled */ #define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) #define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) #define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) /*! CFXWM - Capture X FIFOs Water Mark */ #define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) #define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) #define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) /*! CX0CNT - Capture X0 FIFO Word Count */ #define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) #define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) #define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) /*! CX1CNT - Capture X1 FIFO Word Count */ #define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) /*! @} */ /* The count of PWM_CAPTCTRLX */ #define PWM_CAPTCTRLX_COUNT (4U) /*! @name CAPTCOMPX - Capture Compare X Register */ /*! @{ */ #define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) #define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) /*! EDGCMPX - Edge Compare X */ #define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) #define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) #define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) /*! EDGCNTX - Edge Counter X */ #define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) /*! @} */ /* The count of PWM_CAPTCOMPX */ #define PWM_CAPTCOMPX_COUNT (4U) /*! @name CVAL0 - Capture Value 0 Register */ /*! @{ */ #define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) #define PWM_CVAL0_CAPTVAL0_SHIFT (0U) /*! CAPTVAL0 - Capture Value 0 */ #define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) /*! @} */ /* The count of PWM_CVAL0 */ #define PWM_CVAL0_COUNT (4U) /*! @name CVAL0CYC - Capture Value 0 Cycle Register */ /*! @{ */ #define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) #define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) /*! CVAL0CYC - Capture Value 0 Cycle */ #define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) /*! @} */ /* The count of PWM_CVAL0CYC */ #define PWM_CVAL0CYC_COUNT (4U) /*! @name CVAL1 - Capture Value 1 Register */ /*! @{ */ #define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) #define PWM_CVAL1_CAPTVAL1_SHIFT (0U) /*! CAPTVAL1 - Capture Value 1 */ #define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) /*! @} */ /* The count of PWM_CVAL1 */ #define PWM_CVAL1_COUNT (4U) /*! @name CVAL1CYC - Capture Value 1 Cycle Register */ /*! @{ */ #define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) #define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) /*! CVAL1CYC - Capture Value 1 Cycle */ #define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) /*! @} */ /* The count of PWM_CVAL1CYC */ #define PWM_CVAL1CYC_COUNT (4U) /*! @name CVAL2 - Capture Value 2 Register */ /*! @{ */ #define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) #define PWM_CVAL2_CAPTVAL2_SHIFT (0U) /*! CAPTVAL2 - Capture Value 2 */ #define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) /*! @} */ /* The count of PWM_CVAL2 */ #define PWM_CVAL2_COUNT (4U) /*! @name CVAL2CYC - Capture Value 2 Cycle Register */ /*! @{ */ #define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) #define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) /*! CVAL2CYC - Capture Value 2 Cycle */ #define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) /*! @} */ /* The count of PWM_CVAL2CYC */ #define PWM_CVAL2CYC_COUNT (4U) /*! @name CVAL3 - Capture Value 3 Register */ /*! @{ */ #define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) #define PWM_CVAL3_CAPTVAL3_SHIFT (0U) /*! CAPTVAL3 - Capture Value 3 */ #define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) /*! @} */ /* The count of PWM_CVAL3 */ #define PWM_CVAL3_COUNT (4U) /*! @name CVAL3CYC - Capture Value 3 Cycle Register */ /*! @{ */ #define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) #define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) /*! CVAL3CYC - Capture Value 3 Cycle */ #define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) /*! @} */ /* The count of PWM_CVAL3CYC */ #define PWM_CVAL3CYC_COUNT (4U) /*! @name CVAL4 - Capture Value 4 Register */ /*! @{ */ #define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) #define PWM_CVAL4_CAPTVAL4_SHIFT (0U) /*! CAPTVAL4 - Capture Value 4 */ #define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) /*! @} */ /* The count of PWM_CVAL4 */ #define PWM_CVAL4_COUNT (4U) /*! @name CVAL4CYC - Capture Value 4 Cycle Register */ /*! @{ */ #define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) #define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) /*! CVAL4CYC - Capture Value 4 Cycle */ #define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) /*! @} */ /* The count of PWM_CVAL4CYC */ #define PWM_CVAL4CYC_COUNT (4U) /*! @name CVAL5 - Capture Value 5 Register */ /*! @{ */ #define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) #define PWM_CVAL5_CAPTVAL5_SHIFT (0U) /*! CAPTVAL5 - Capture Value 5 */ #define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) /*! @} */ /* The count of PWM_CVAL5 */ #define PWM_CVAL5_COUNT (4U) /*! @name CVAL5CYC - Capture Value 5 Cycle Register */ /*! @{ */ #define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) #define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) /*! CVAL5CYC - Capture Value 5 Cycle */ #define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) /*! @} */ /* The count of PWM_CVAL5CYC */ #define PWM_CVAL5CYC_COUNT (4U) /*! @name PHASEDLY - Phase Delay Register */ /*! @{ */ #define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) #define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) /*! PHASEDLY - Initial Count Register Bits */ #define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) /*! @} */ /* The count of PWM_PHASEDLY */ #define PWM_PHASEDLY_COUNT (4U) /*! @name CAPTFILTA - Capture PWM_A Input Filter Register */ /*! @{ */ #define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT (0U) /*! CAPTA_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTA_CAPTA_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK) #define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT (8U) /*! CAPTA_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTA_CAPTA_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK) /*! @} */ /* The count of PWM_CAPTFILTA */ #define PWM_CAPTFILTA_COUNT (4U) /*! @name CAPTFILTB - Capture PWM_B Input Filter Register */ /*! @{ */ #define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT (0U) /*! CAPTB_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTB_CAPTB_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK) #define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT (8U) /*! CAPTB_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTB_CAPTB_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK) /*! @} */ /* The count of PWM_CAPTFILTB */ #define PWM_CAPTFILTB_COUNT (4U) /*! @name CAPTFILTX - Capture PWM_X Input Filter Register */ /*! @{ */ #define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) /*! CAPTX_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) #define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) /*! CAPTX_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) /*! @} */ /* The count of PWM_CAPTFILTX */ #define PWM_CAPTFILTX_COUNT (4U) /*! @name OUTEN - Output Enable Register */ /*! @{ */ #define PWM_OUTEN_PWMX_EN_MASK (0xFU) #define PWM_OUTEN_PWMX_EN_SHIFT (0U) /*! PWMX_EN - PWM_X Output Enables */ #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) #define PWM_OUTEN_PWMB_EN_MASK (0xF0U) #define PWM_OUTEN_PWMB_EN_SHIFT (4U) /*! PWMB_EN - PWM_B Output Enables */ #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) #define PWM_OUTEN_PWMA_EN_MASK (0xF00U) #define PWM_OUTEN_PWMA_EN_SHIFT (8U) /*! PWMA_EN - PWM_A Output Enables */ #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) /*! @} */ /*! @name MASK - Mask Register */ /*! @{ */ #define PWM_MASK_MASKX_MASK (0xFU) #define PWM_MASK_MASKX_SHIFT (0U) /*! MASKX - PWM_X Masks */ #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) #define PWM_MASK_MASKB_MASK (0xF0U) #define PWM_MASK_MASKB_SHIFT (4U) /*! MASKB - PWM_B Masks */ #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) #define PWM_MASK_MASKA_MASK (0xF00U) #define PWM_MASK_MASKA_SHIFT (8U) /*! MASKA - PWM_A Masks */ #define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) #define PWM_MASK_UPDATE_MASK_MASK (0xF000U) #define PWM_MASK_UPDATE_MASK_SHIFT (12U) /*! UPDATE_MASK - Update Mask Bits Immediately */ #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) /*! @} */ /*! @name SWCOUT - Software Controlled Output Register */ /*! @{ */ #define PWM_SWCOUT_SM0OUT45_MASK (0x1U) #define PWM_SWCOUT_SM0OUT45_SHIFT (0U) /*! SM0OUT45 - Submodule 0 Software Controlled Output 45 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. */ #define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) #define PWM_SWCOUT_SM0OUT23_MASK (0x2U) #define PWM_SWCOUT_SM0OUT23_SHIFT (1U) /*! SM0OUT23 - Submodule 0 Software Controlled Output 23 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. */ #define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) #define PWM_SWCOUT_SM1OUT45_MASK (0x4U) #define PWM_SWCOUT_SM1OUT45_SHIFT (2U) /*! SM1OUT45 - Submodule 1 Software Controlled Output 45 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. */ #define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) #define PWM_SWCOUT_SM1OUT23_MASK (0x8U) #define PWM_SWCOUT_SM1OUT23_SHIFT (3U) /*! SM1OUT23 - Submodule 1 Software Controlled Output 23 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. */ #define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) #define PWM_SWCOUT_SM2OUT45_MASK (0x10U) #define PWM_SWCOUT_SM2OUT45_SHIFT (4U) /*! SM2OUT45 - Submodule 2 Software Controlled Output 45 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. */ #define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) #define PWM_SWCOUT_SM2OUT23_MASK (0x20U) #define PWM_SWCOUT_SM2OUT23_SHIFT (5U) /*! SM2OUT23 - Submodule 2 Software Controlled Output 23 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. */ #define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) #define PWM_SWCOUT_SM3OUT45_MASK (0x40U) #define PWM_SWCOUT_SM3OUT45_SHIFT (6U) /*! SM3OUT45 - Submodule 3 Software Controlled Output 45 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. */ #define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) #define PWM_SWCOUT_SM3OUT23_MASK (0x80U) #define PWM_SWCOUT_SM3OUT23_SHIFT (7U) /*! SM3OUT23 - Submodule 3 Software Controlled Output 23 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. */ #define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) /*! @} */ /*! @name DTSRCSEL - PWM Source Select Register */ /*! @{ */ #define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) #define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) /*! SM0SEL45 - Submodule 0 PWM45 Control Select * 0b00..Generated SM0PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. * 0b11..Reserved */ #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) #define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) #define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) /*! SM0SEL23 - Submodule 0 PWM23 Control Select * 0b00..Generated SM0PWM23 signal used by the deadtime logic. * 0b01..Inverted generated SM0PWM23 signal used by the deadtime logic. * 0b10..SWCOUT[SM0OUT23] used by the deadtime logic. * 0b11..PWM0_EXTA signal used by the deadtime logic. */ #define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) #define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) #define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) /*! SM1SEL45 - Submodule 1 PWM45 Control Select * 0b00..Generated SM1PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. * 0b11..Reserved */ #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) #define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) #define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) /*! SM1SEL23 - Submodule 1 PWM23 Control Select * 0b00..Generated SM1PWM23 signal used by the deadtime logic. * 0b01..Inverted generated SM1PWM23 signal used by the deadtime logic. * 0b10..SWCOUT[SM1OUT23] used by the deadtime logic. * 0b11..PWM1_EXTA signal used by the deadtime logic. */ #define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) #define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) #define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) /*! SM2SEL45 - Submodule 2 PWM45 Control Select * 0b00..Generated SM2PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. * 0b11..Reserved */ #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) #define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) #define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) /*! SM2SEL23 - Submodule 2 PWM23 Control Select * 0b00..Generated SM2PWM23 signal used by the deadtime logic. * 0b01..Inverted generated SM2PWM23 signal used by the deadtime logic. * 0b10..SWCOUT[SM2OUT23] used by the deadtime logic. * 0b11..PWM2_EXTA signal used by the deadtime logic. */ #define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) #define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) #define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) /*! SM3SEL45 - Submodule 3 PWM45 Control Select * 0b00..Generated SM3PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM3PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM3OUT45] used by the deadtime logic. * 0b11..Reserved */ #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) #define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) #define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) /*! SM3SEL23 - Submodule 3 PWM23 Control Select * 0b00..Generated SM3PWM23 signal used by the deadtime logic. * 0b01..Inverted generated SM3PWM23 signal used by the deadtime logic. * 0b10..SWCOUT[SM3OUT23] used by the deadtime logic. * 0b11..PWM3_EXTA signal used by the deadtime logic. */ #define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) /*! @} */ /*! @name MCTRL - Master Control Register */ /*! @{ */ #define PWM_MCTRL_LDOK_MASK (0xFU) #define PWM_MCTRL_LDOK_SHIFT (0U) /*! LDOK - Load Okay * 0b0000..Do not load new values. * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. */ #define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) #define PWM_MCTRL_CLDOK_MASK (0xF0U) #define PWM_MCTRL_CLDOK_SHIFT (4U) /*! CLDOK - Clear Load Okay */ #define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) #define PWM_MCTRL_RUN_MASK (0xF00U) #define PWM_MCTRL_RUN_SHIFT (8U) /*! RUN - Run * 0b0000..PWM counter is stopped, but PWM outputs hold the current state. * 0b0001..PWM counter is started in the corresponding submodule. */ #define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) #define PWM_MCTRL_IPOL_MASK (0xF000U) #define PWM_MCTRL_IPOL_SHIFT (12U) /*! IPOL - Current Polarity * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. */ #define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) /*! @} */ /*! @name MCTRL2 - Master Control 2 Register */ /*! @{ */ #define PWM_MCTRL2_WRPROT_MASK (0xCU) #define PWM_MCTRL2_WRPROT_SHIFT (2U) /*! WRPROT - Write protect * 0b00..Write protection off (default). * 0b01..Write protection on. * 0b10..Write protection off and locked until chip reset. * 0b11..Write protection on and locked until chip reset. */ #define PWM_MCTRL2_WRPROT(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK) #define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK (0xC0U) #define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT (6U) /*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig * 0b00..Stretch count is zero, no stretch. * 0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period. * 0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period. * 0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period. */ #define PWM_MCTRL2_STRETCH_CNT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK) /*! @} */ /*! @name FCTRL - Fault Control Register */ /*! @{ */ #define PWM_FCTRL_FIE_MASK (0xFU) #define PWM_FCTRL_FIE_SHIFT (0U) /*! FIE - Fault Interrupt Enables * 0b0000..FAULTx CPU interrupt requests disabled. * 0b0001..FAULTx CPU interrupt requests enabled. */ #define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) #define PWM_FCTRL_FSAFE_MASK (0xF0U) #define PWM_FCTRL_FSAFE_SHIFT (4U) /*! FSAFE - Fault Safety Mode * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in * DISMAPn). * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. */ #define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) #define PWM_FCTRL_FAUTO_MASK (0xF00U) #define PWM_FCTRL_FAUTO_SHIFT (8U) /*! FAUTO - Automatic Fault Clearing * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear * at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled * by FCTRL[FSAFE]. * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition * cannot be cleared. */ #define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) #define PWM_FCTRL_FLVL_MASK (0xF000U) #define PWM_FCTRL_FLVL_SHIFT (12U) /*! FLVL - Fault Level * 0b0000..A logic 0 on the fault input indicates a fault condition. * 0b0001..A logic 1 on the fault input indicates a fault condition. */ #define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) /*! @} */ /*! @name FSTS - Fault Status Register */ /*! @{ */ #define PWM_FSTS_FFLAG_MASK (0xFU) #define PWM_FSTS_FFLAG_SHIFT (0U) /*! FFLAG - Fault Flags * 0b0000..No fault on the FAULTx pin. * 0b0001..Fault on the FAULTx pin. */ #define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) #define PWM_FSTS_FFULL_MASK (0xF0U) #define PWM_FSTS_FFULL_SHIFT (4U) /*! FFULL - Full Cycle * 0b0000..PWM outputs are not re-enabled at the start of a full cycle * 0b0001..PWM outputs are re-enabled at the start of a full cycle */ #define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) #define PWM_FSTS_FFPIN_MASK (0xF00U) #define PWM_FSTS_FFPIN_SHIFT (8U) /*! FFPIN - Filtered Fault Pins */ #define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) #define PWM_FSTS_FHALF_MASK (0xF000U) #define PWM_FSTS_FHALF_SHIFT (12U) /*! FHALF - Half Cycle Fault Recovery * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). */ #define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) /*! @} */ /*! @name FFILT - Fault Filter Register */ /*! @{ */ #define PWM_FFILT_FILT_PER_MASK (0xFFU) #define PWM_FFILT_FILT_PER_SHIFT (0U) /*! FILT_PER - Fault Filter Period */ #define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) #define PWM_FFILT_FILT_CNT_MASK (0x700U) #define PWM_FFILT_FILT_CNT_SHIFT (8U) /*! FILT_CNT - Fault Filter Count */ #define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) #define PWM_FFILT_GSTR_MASK (0x8000U) #define PWM_FFILT_GSTR_SHIFT (15U) /*! GSTR - Fault Glitch Stretch Enable * 0b0..Fault input glitch stretching is disabled. * 0b1..Input fault signals are stretched to at least 2 IPBus clock cycles. */ #define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) /*! @} */ /*! @name FTST - Fault Test Register */ /*! @{ */ #define PWM_FTST_FTEST_MASK (0x1U) #define PWM_FTST_FTEST_SHIFT (0U) /*! FTEST - Fault Test * 0b0..No fault * 0b1..Cause a simulated fault */ #define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) /*! @} */ /*! @name FCTRL2 - Fault Control 2 Register */ /*! @{ */ #define PWM_FCTRL2_NOCOMB_MASK (0xFU) #define PWM_FCTRL2_NOCOMB_SHIFT (0U) /*! NOCOMB - No Combinational Path From Fault Input To PWM Output * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined * with the filtered and latched fault signals to disable the PWM outputs. * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered * and latched fault signals are used to disable the PWM outputs. */ #define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) /*! @} */ /*! * @} */ /* end of group PWM_Register_Masks */ /* PWM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral PWM0 base address */ #define PWM0_BASE (0x500CE000u) /** Peripheral PWM0 base address */ #define PWM0_BASE_NS (0x400CE000u) /** Peripheral PWM0 base pointer */ #define PWM0 ((PWM_Type *)PWM0_BASE) /** Peripheral PWM0 base pointer */ #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) /** Peripheral PWM1 base address */ #define PWM1_BASE (0x500D0000u) /** Peripheral PWM1 base address */ #define PWM1_BASE_NS (0x400D0000u) /** Peripheral PWM1 base pointer */ #define PWM1 ((PWM_Type *)PWM1_BASE) /** Peripheral PWM1 base pointer */ #define PWM1_NS ((PWM_Type *)PWM1_BASE_NS) /** Array initializer of PWM peripheral base addresses */ #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } /** Array initializer of PWM peripheral base pointers */ #define PWM_BASE_PTRS { PWM0, PWM1 } /** Array initializer of PWM peripheral base addresses */ #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS, PWM1_BASE_NS } /** Array initializer of PWM peripheral base pointers */ #define PWM_BASE_PTRS_NS { PWM0_NS, PWM1_NS } #else /** Peripheral PWM0 base address */ #define PWM0_BASE (0x400CE000u) /** Peripheral PWM0 base pointer */ #define PWM0 ((PWM_Type *)PWM0_BASE) /** Peripheral PWM1 base address */ #define PWM1_BASE (0x400D0000u) /** Peripheral PWM1 base pointer */ #define PWM1 ((PWM_Type *)PWM1_BASE) /** Array initializer of PWM peripheral base addresses */ #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } /** Array initializer of PWM peripheral base pointers */ #define PWM_BASE_PTRS { PWM0, PWM1 } #endif /** Interrupt vectors for the PWM peripheral type */ #define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } #define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } #define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } #define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } #define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } /*! * @} */ /* end of group PWM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- QDC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup QDC_Peripheral_Access_Layer QDC Peripheral Access Layer * @{ */ /** QDC - Register Layout Typedef */ typedef struct { __IO uint16_t CTRL; /**< Control, offset: 0x0 */ __IO uint16_t FILT; /**< Input Filter, offset: 0x2 */ __IO uint16_t WTR; /**< Watchdog Timeout, offset: 0x4 */ __IO uint16_t POSD; /**< Position Difference Counter, offset: 0x6 */ __I uint16_t POSDH; /**< Position Difference Hold, offset: 0x8 */ __IO uint16_t REV; /**< Revolution Counter, offset: 0xA */ __I uint16_t REVH; /**< Revolution Hold, offset: 0xC */ __IO uint16_t UPOS; /**< Upper Position Counter, offset: 0xE */ __IO uint16_t LPOS; /**< Lower Position Counter, offset: 0x10 */ __I uint16_t UPOSH; /**< Upper Position Hold, offset: 0x12 */ __I uint16_t LPOSH; /**< Lower Position Hold, offset: 0x14 */ __IO uint16_t UINIT; /**< Upper Initialization, offset: 0x16 */ __IO uint16_t LINIT; /**< Lower Initialization, offset: 0x18 */ __I uint16_t IMR; /**< Input Monitor, offset: 0x1A */ __IO uint16_t TST; /**< Test, offset: 0x1C */ __IO uint16_t CTRL2; /**< Control 2, offset: 0x1E */ __IO uint16_t UMOD; /**< Upper Modulus, offset: 0x20 */ __IO uint16_t LMOD; /**< Lower Modulus, offset: 0x22 */ __IO uint16_t UCOMP; /**< Upper Position Compare, offset: 0x24 */ __IO uint16_t LCOMP; /**< Lower Position Compare, offset: 0x26 */ __I uint16_t LASTEDGE; /**< Last Edge Time, offset: 0x28 */ __I uint16_t LASTEDGEH; /**< Last Edge Time Hold, offset: 0x2A */ __I uint16_t POSDPER; /**< Position Difference Period Counter, offset: 0x2C */ __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer, offset: 0x2E */ __I uint16_t POSDPERH; /**< Position Difference Period Hold, offset: 0x30 */ __IO uint16_t CTRL3; /**< Control 3, offset: 0x32 */ } QDC_Type; /* ---------------------------------------------------------------------------- -- QDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup QDC_Register_Masks QDC Register Masks * @{ */ /*! @name CTRL - Control */ /*! @{ */ #define QDC_CTRL_CMPIE_MASK (0x1U) #define QDC_CTRL_CMPIE_SHIFT (0U) /*! CMPIE - Compare Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIE_SHIFT)) & QDC_CTRL_CMPIE_MASK) #define QDC_CTRL_CMPIRQ_MASK (0x2U) #define QDC_CTRL_CMPIRQ_SHIFT (1U) /*! CMPIRQ - Compare Interrupt Request * 0b0..No match has occurred * 0b1..COMP match has occurred */ #define QDC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIRQ_SHIFT)) & QDC_CTRL_CMPIRQ_MASK) #define QDC_CTRL_WDE_MASK (0x4U) #define QDC_CTRL_WDE_SHIFT (2U) /*! WDE - Watchdog Enable * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_WDE_SHIFT)) & QDC_CTRL_WDE_MASK) #define QDC_CTRL_DIE_MASK (0x8U) #define QDC_CTRL_DIE_SHIFT (3U) /*! DIE - Watchdog Timeout Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIE_SHIFT)) & QDC_CTRL_DIE_MASK) #define QDC_CTRL_DIRQ_MASK (0x10U) #define QDC_CTRL_DIRQ_SHIFT (4U) /*! DIRQ - Watchdog Timeout Interrupt Request * 0b0..Not occurred * 0b1..Occurred */ #define QDC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIRQ_SHIFT)) & QDC_CTRL_DIRQ_MASK) #define QDC_CTRL_XNE_MASK (0x20U) #define QDC_CTRL_XNE_SHIFT (5U) /*! XNE - Select Positive and Negative Edge of INDEX Pulse * 0b0..Use positive edge * 0b1..Use negative edge */ #define QDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XNE_SHIFT)) & QDC_CTRL_XNE_MASK) #define QDC_CTRL_XIP_MASK (0x40U) #define QDC_CTRL_XIP_SHIFT (6U) /*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS * 0b0..Does not initialize * 0b1..Initializes */ #define QDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIP_SHIFT)) & QDC_CTRL_XIP_MASK) #define QDC_CTRL_XIE_MASK (0x80U) #define QDC_CTRL_XIE_SHIFT (7U) /*! XIE - INDEX Pulse Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIE_SHIFT)) & QDC_CTRL_XIE_MASK) #define QDC_CTRL_XIRQ_MASK (0x100U) #define QDC_CTRL_XIRQ_SHIFT (8U) /*! XIRQ - INDEX Pulse Interrupt Request * 0b0..Not occurred * 0b1..Occurred */ #define QDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIRQ_SHIFT)) & QDC_CTRL_XIRQ_MASK) #define QDC_CTRL_PH1_MASK (0x200U) #define QDC_CTRL_PH1_SHIFT (9U) /*! PH1 - Enable Signal Phase Count Mode * 0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. * 0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal. * PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical; * then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down. */ #define QDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_PH1_SHIFT)) & QDC_CTRL_PH1_MASK) #define QDC_CTRL_REV_MASK (0x400U) #define QDC_CTRL_REV_SHIFT (10U) /*! REV - Enable Reverse Direction Counting * 0b0..Counts normally * 0b1..Counts in the reverse direction */ #define QDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_REV_SHIFT)) & QDC_CTRL_REV_MASK) #define QDC_CTRL_SWIP_MASK (0x800U) #define QDC_CTRL_SWIP_SHIFT (11U) /*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS * 0b0..No action * 0b1..Initialize position counter */ #define QDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_SWIP_SHIFT)) & QDC_CTRL_SWIP_MASK) #define QDC_CTRL_HNE_MASK (0x1000U) #define QDC_CTRL_HNE_SHIFT (12U) /*! HNE - Use Negative Edge of HOME Input * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS */ #define QDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HNE_SHIFT)) & QDC_CTRL_HNE_MASK) #define QDC_CTRL_HIP_MASK (0x2000U) #define QDC_CTRL_HIP_SHIFT (13U) /*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS * 0b0..No action * 0b1..HOME signal initializes the position counter */ #define QDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIP_SHIFT)) & QDC_CTRL_HIP_MASK) #define QDC_CTRL_HIE_MASK (0x4000U) #define QDC_CTRL_HIE_SHIFT (14U) /*! HIE - HOME Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIE_SHIFT)) & QDC_CTRL_HIE_MASK) #define QDC_CTRL_HIRQ_MASK (0x8000U) #define QDC_CTRL_HIRQ_SHIFT (15U) /*! HIRQ - HOME Signal Transition Interrupt Request * 0b0..Not occurred * 0b1..Occurred */ #define QDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIRQ_SHIFT)) & QDC_CTRL_HIRQ_MASK) /*! @} */ /*! @name FILT - Input Filter */ /*! @{ */ #define QDC_FILT_FILT_PER_MASK (0xFFU) #define QDC_FILT_FILT_PER_SHIFT (0U) /*! FILT_PER - Input Filter Sample Period */ #define QDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PER_SHIFT)) & QDC_FILT_FILT_PER_MASK) #define QDC_FILT_FILT_CNT_MASK (0x700U) #define QDC_FILT_FILT_CNT_SHIFT (8U) /*! FILT_CNT - Input Filter Sample Count */ #define QDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_CNT_SHIFT)) & QDC_FILT_FILT_CNT_MASK) #define QDC_FILT_FILT_PRSC_MASK (0xE000U) #define QDC_FILT_FILT_PRSC_SHIFT (13U) /*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ #define QDC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PRSC_SHIFT)) & QDC_FILT_FILT_PRSC_MASK) /*! @} */ /*! @name WTR - Watchdog Timeout */ /*! @{ */ #define QDC_WTR_WDOG_MASK (0xFFFFU) #define QDC_WTR_WDOG_SHIFT (0U) /*! WDOG - WDOG */ #define QDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << QDC_WTR_WDOG_SHIFT)) & QDC_WTR_WDOG_MASK) /*! @} */ /*! @name POSD - Position Difference Counter */ /*! @{ */ #define QDC_POSD_POSD_MASK (0xFFFFU) #define QDC_POSD_POSD_SHIFT (0U) /*! POSD - POSD */ #define QDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSD_POSD_SHIFT)) & QDC_POSD_POSD_MASK) /*! @} */ /*! @name POSDH - Position Difference Hold */ /*! @{ */ #define QDC_POSDH_POSDH_MASK (0xFFFFU) #define QDC_POSDH_POSDH_SHIFT (0U) /*! POSDH - POSDH */ #define QDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDH_POSDH_SHIFT)) & QDC_POSDH_POSDH_MASK) /*! @} */ /*! @name REV - Revolution Counter */ /*! @{ */ #define QDC_REV_REV_MASK (0xFFFFU) #define QDC_REV_REV_SHIFT (0U) /*! REV - REV */ #define QDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_REV_REV_SHIFT)) & QDC_REV_REV_MASK) /*! @} */ /*! @name REVH - Revolution Hold */ /*! @{ */ #define QDC_REVH_REVH_MASK (0xFFFFU) #define QDC_REVH_REVH_SHIFT (0U) /*! REVH - REVH */ #define QDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << QDC_REVH_REVH_SHIFT)) & QDC_REVH_REVH_MASK) /*! @} */ /*! @name UPOS - Upper Position Counter */ /*! @{ */ #define QDC_UPOS_POS_MASK (0xFFFFU) #define QDC_UPOS_POS_SHIFT (0U) /*! POS - POS */ #define QDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOS_POS_SHIFT)) & QDC_UPOS_POS_MASK) /*! @} */ /*! @name LPOS - Lower Position Counter */ /*! @{ */ #define QDC_LPOS_POS_MASK (0xFFFFU) #define QDC_LPOS_POS_SHIFT (0U) /*! POS - POS */ #define QDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOS_POS_SHIFT)) & QDC_LPOS_POS_MASK) /*! @} */ /*! @name UPOSH - Upper Position Hold */ /*! @{ */ #define QDC_UPOSH_POSH_MASK (0xFFFFU) #define QDC_UPOSH_POSH_SHIFT (0U) /*! POSH - POSH */ #define QDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOSH_POSH_SHIFT)) & QDC_UPOSH_POSH_MASK) /*! @} */ /*! @name LPOSH - Lower Position Hold */ /*! @{ */ #define QDC_LPOSH_POSH_MASK (0xFFFFU) #define QDC_LPOSH_POSH_SHIFT (0U) /*! POSH - POSH */ #define QDC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOSH_POSH_SHIFT)) & QDC_LPOSH_POSH_MASK) /*! @} */ /*! @name UINIT - Upper Initialization */ /*! @{ */ #define QDC_UINIT_INIT_MASK (0xFFFFU) #define QDC_UINIT_INIT_SHIFT (0U) /*! INIT - INIT */ #define QDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_UINIT_INIT_SHIFT)) & QDC_UINIT_INIT_MASK) /*! @} */ /*! @name LINIT - Lower Initialization */ /*! @{ */ #define QDC_LINIT_INIT_MASK (0xFFFFU) #define QDC_LINIT_INIT_SHIFT (0U) /*! INIT - INIT */ #define QDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_LINIT_INIT_SHIFT)) & QDC_LINIT_INIT_MASK) /*! @} */ /*! @name IMR - Input Monitor */ /*! @{ */ #define QDC_IMR_HOME_MASK (0x1U) #define QDC_IMR_HOME_SHIFT (0U) /*! HOME - HOME */ #define QDC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_HOME_SHIFT)) & QDC_IMR_HOME_MASK) #define QDC_IMR_INDEX_MASK (0x2U) #define QDC_IMR_INDEX_SHIFT (1U) /*! INDEX - INDEX */ #define QDC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_INDEX_SHIFT)) & QDC_IMR_INDEX_MASK) #define QDC_IMR_PHB_MASK (0x4U) #define QDC_IMR_PHB_SHIFT (2U) /*! PHB - PHB */ #define QDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHB_SHIFT)) & QDC_IMR_PHB_MASK) #define QDC_IMR_PHA_MASK (0x8U) #define QDC_IMR_PHA_SHIFT (3U) /*! PHA - PHA */ #define QDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHA_SHIFT)) & QDC_IMR_PHA_MASK) #define QDC_IMR_FHOM_MASK (0x10U) #define QDC_IMR_FHOM_SHIFT (4U) /*! FHOM - FHOM */ #define QDC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FHOM_SHIFT)) & QDC_IMR_FHOM_MASK) #define QDC_IMR_FIND_MASK (0x20U) #define QDC_IMR_FIND_SHIFT (5U) /*! FIND - FIND */ #define QDC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FIND_SHIFT)) & QDC_IMR_FIND_MASK) #define QDC_IMR_FPHB_MASK (0x40U) #define QDC_IMR_FPHB_SHIFT (6U) /*! FPHB - FPHB */ #define QDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHB_SHIFT)) & QDC_IMR_FPHB_MASK) #define QDC_IMR_FPHA_MASK (0x80U) #define QDC_IMR_FPHA_SHIFT (7U) /*! FPHA - FPHA */ #define QDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHA_SHIFT)) & QDC_IMR_FPHA_MASK) /*! @} */ /*! @name TST - Test */ /*! @{ */ #define QDC_TST_TEST_COUNT_MASK (0xFFU) #define QDC_TST_TEST_COUNT_SHIFT (0U) /*! TEST_COUNT - TEST_COUNT */ #define QDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_COUNT_SHIFT)) & QDC_TST_TEST_COUNT_MASK) #define QDC_TST_TEST_PERIOD_MASK (0x1F00U) #define QDC_TST_TEST_PERIOD_SHIFT (8U) /*! TEST_PERIOD - TEST_PERIOD */ #define QDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_PERIOD_SHIFT)) & QDC_TST_TEST_PERIOD_MASK) #define QDC_TST_QDN_MASK (0x2000U) #define QDC_TST_QDN_SHIFT (13U) /*! QDN - Quadrature Decoder Negative Signal * 0b0..Positive quadrature decoder signal * 0b1..Negative quadrature decoder signal */ #define QDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_QDN_SHIFT)) & QDC_TST_QDN_MASK) #define QDC_TST_TCE_MASK (0x4000U) #define QDC_TST_TCE_SHIFT (14U) /*! TCE - Test Counter Enable * 0b0..Disable * 0b1..Enable */ #define QDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TCE_SHIFT)) & QDC_TST_TCE_MASK) #define QDC_TST_TEN_MASK (0x8000U) #define QDC_TST_TEN_SHIFT (15U) /*! TEN - Test Mode Enable * 0b0..Disable * 0b1..Enable */ #define QDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEN_SHIFT)) & QDC_TST_TEN_MASK) /*! @} */ /*! @name CTRL2 - Control 2 */ /*! @{ */ #define QDC_CTRL2_UPDHLD_MASK (0x1U) #define QDC_CTRL2_UPDHLD_SHIFT (0U) /*! UPDHLD - Update Hold Registers * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDHLD_SHIFT)) & QDC_CTRL2_UPDHLD_MASK) #define QDC_CTRL2_UPDPOS_MASK (0x2U) #define QDC_CTRL2_UPDPOS_SHIFT (1U) /*! UPDPOS - Update Position Registers * 0b0..No action * 0b1..Clear */ #define QDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDPOS_SHIFT)) & QDC_CTRL2_UPDPOS_MASK) #define QDC_CTRL2_MOD_MASK (0x4U) #define QDC_CTRL2_MOD_SHIFT (2U) /*! MOD - Enable Modulo Counting * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_MOD_SHIFT)) & QDC_CTRL2_MOD_MASK) #define QDC_CTRL2_DIR_MASK (0x8U) #define QDC_CTRL2_DIR_SHIFT (3U) /*! DIR - Count Direction Flag * 0b0..Down direction * 0b1..Up direction */ #define QDC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_DIR_SHIFT)) & QDC_CTRL2_DIR_MASK) #define QDC_CTRL2_RUIE_MASK (0x10U) #define QDC_CTRL2_RUIE_SHIFT (4U) /*! RUIE - Roll-under Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIE_SHIFT)) & QDC_CTRL2_RUIE_MASK) #define QDC_CTRL2_RUIRQ_MASK (0x20U) #define QDC_CTRL2_RUIRQ_SHIFT (5U) /*! RUIRQ - Roll-under Interrupt Request * 0b0..No roll-under has occurred * 0b1..Roll-under has occurred */ #define QDC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIRQ_SHIFT)) & QDC_CTRL2_RUIRQ_MASK) #define QDC_CTRL2_ROIE_MASK (0x40U) #define QDC_CTRL2_ROIE_SHIFT (6U) /*! ROIE - Roll-over Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIE_SHIFT)) & QDC_CTRL2_ROIE_MASK) #define QDC_CTRL2_ROIRQ_MASK (0x80U) #define QDC_CTRL2_ROIRQ_SHIFT (7U) /*! ROIRQ - Roll-over Interrupt Request * 0b0..Did not occur * 0b1..Occurred */ #define QDC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIRQ_SHIFT)) & QDC_CTRL2_ROIRQ_MASK) #define QDC_CTRL2_REVMOD_MASK (0x100U) #define QDC_CTRL2_REVMOD_SHIFT (8U) /*! REVMOD - Revolution Counter Modulus Enable * 0b0..Use INDEX pulse * 0b1..Use modulus counting roll-over or roll-under */ #define QDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_REVMOD_SHIFT)) & QDC_CTRL2_REVMOD_MASK) #define QDC_CTRL2_OUTCTL_MASK (0x200U) #define QDC_CTRL2_OUTCTL_SHIFT (9U) /*! OUTCTL - Output Control * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read */ #define QDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_OUTCTL_SHIFT)) & QDC_CTRL2_OUTCTL_MASK) #define QDC_CTRL2_SABIE_MASK (0x400U) #define QDC_CTRL2_SABIE_SHIFT (10U) /*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define QDC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIE_SHIFT)) & QDC_CTRL2_SABIE_MASK) #define QDC_CTRL2_SABIRQ_MASK (0x800U) #define QDC_CTRL2_SABIRQ_SHIFT (11U) /*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request * 0b0..No simultaneous change has occurred * 0b1..A simultaneous change has occurred */ #define QDC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIRQ_SHIFT)) & QDC_CTRL2_SABIRQ_MASK) #define QDC_CTRL2_INITPOS_MASK (0x1000U) #define QDC_CTRL2_INITPOS_SHIFT (12U) /*! INITPOS - Initialize Position Registers * 0b0..Don't initialize position counter * 0b1..Initialize position counter */ #define QDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_INITPOS_SHIFT)) & QDC_CTRL2_INITPOS_MASK) /*! @} */ /*! @name UMOD - Upper Modulus */ /*! @{ */ #define QDC_UMOD_MOD_MASK (0xFFFFU) #define QDC_UMOD_MOD_SHIFT (0U) /*! MOD - MOD */ #define QDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_UMOD_MOD_SHIFT)) & QDC_UMOD_MOD_MASK) /*! @} */ /*! @name LMOD - Lower Modulus */ /*! @{ */ #define QDC_LMOD_MOD_MASK (0xFFFFU) #define QDC_LMOD_MOD_SHIFT (0U) /*! MOD - MOD */ #define QDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_LMOD_MOD_SHIFT)) & QDC_LMOD_MOD_MASK) /*! @} */ /*! @name UCOMP - Upper Position Compare */ /*! @{ */ #define QDC_UCOMP_COMP_MASK (0xFFFFU) #define QDC_UCOMP_COMP_SHIFT (0U) /*! COMP - COMP */ #define QDC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_UCOMP_COMP_SHIFT)) & QDC_UCOMP_COMP_MASK) /*! @} */ /*! @name LCOMP - Lower Position Compare */ /*! @{ */ #define QDC_LCOMP_COMP_MASK (0xFFFFU) #define QDC_LCOMP_COMP_SHIFT (0U) /*! COMP - COMP */ #define QDC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_LCOMP_COMP_SHIFT)) & QDC_LCOMP_COMP_MASK) /*! @} */ /*! @name LASTEDGE - Last Edge Time */ /*! @{ */ #define QDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) #define QDC_LASTEDGE_LASTEDGE_SHIFT (0U) /*! LASTEDGE - Last Edge Time Counter */ #define QDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGE_LASTEDGE_SHIFT)) & QDC_LASTEDGE_LASTEDGE_MASK) /*! @} */ /*! @name LASTEDGEH - Last Edge Time Hold */ /*! @{ */ #define QDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) #define QDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) /*! LASTEDGEH - Last Edge Time Hold */ #define QDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGEH_LASTEDGEH_SHIFT)) & QDC_LASTEDGEH_LASTEDGEH_MASK) /*! @} */ /*! @name POSDPER - Position Difference Period Counter */ /*! @{ */ #define QDC_POSDPER_POSDPER_MASK (0xFFFFU) #define QDC_POSDPER_POSDPER_SHIFT (0U) /*! POSDPER - Position difference period */ #define QDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPER_POSDPER_SHIFT)) & QDC_POSDPER_POSDPER_MASK) /*! @} */ /*! @name POSDPERBFR - Position Difference Period Buffer */ /*! @{ */ #define QDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) #define QDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) /*! POSDPERBFR - Position difference period buffer */ #define QDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERBFR_POSDPERBFR_SHIFT)) & QDC_POSDPERBFR_POSDPERBFR_MASK) /*! @} */ /*! @name POSDPERH - Position Difference Period Hold */ /*! @{ */ #define QDC_POSDPERH_POSDPERH_MASK (0xFFFFU) #define QDC_POSDPERH_POSDPERH_SHIFT (0U) /*! POSDPERH - Position difference period hold */ #define QDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERH_POSDPERH_SHIFT)) & QDC_POSDPERH_POSDPERH_MASK) /*! @} */ /*! @name CTRL3 - Control 3 */ /*! @{ */ #define QDC_CTRL3_PMEN_MASK (0x1U) #define QDC_CTRL3_PMEN_SHIFT (0U) /*! PMEN - Period Measurement Function Enable * 0b0..Not used * 0b1..Used */ #define QDC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PMEN_SHIFT)) & QDC_CTRL3_PMEN_MASK) #define QDC_CTRL3_PRSC_MASK (0xF0U) #define QDC_CTRL3_PRSC_SHIFT (4U) /*! PRSC - Prescaler */ #define QDC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PRSC_SHIFT)) & QDC_CTRL3_PRSC_MASK) /*! @} */ /*! * @} */ /* end of group QDC_Register_Masks */ /* QDC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral QDC0 base address */ #define QDC0_BASE (0x500CF000u) /** Peripheral QDC0 base address */ #define QDC0_BASE_NS (0x400CF000u) /** Peripheral QDC0 base pointer */ #define QDC0 ((QDC_Type *)QDC0_BASE) /** Peripheral QDC0 base pointer */ #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) /** Peripheral QDC1 base address */ #define QDC1_BASE (0x500D1000u) /** Peripheral QDC1 base address */ #define QDC1_BASE_NS (0x400D1000u) /** Peripheral QDC1 base pointer */ #define QDC1 ((QDC_Type *)QDC1_BASE) /** Peripheral QDC1 base pointer */ #define QDC1_NS ((QDC_Type *)QDC1_BASE_NS) /** Array initializer of QDC peripheral base addresses */ #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } /** Array initializer of QDC peripheral base pointers */ #define QDC_BASE_PTRS { QDC0, QDC1 } /** Array initializer of QDC peripheral base addresses */ #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS, QDC1_BASE_NS } /** Array initializer of QDC peripheral base pointers */ #define QDC_BASE_PTRS_NS { QDC0_NS, QDC1_NS } #else /** Peripheral QDC0 base address */ #define QDC0_BASE (0x400CF000u) /** Peripheral QDC0 base pointer */ #define QDC0 ((QDC_Type *)QDC0_BASE) /** Peripheral QDC1 base address */ #define QDC1_BASE (0x400D1000u) /** Peripheral QDC1 base pointer */ #define QDC1 ((QDC_Type *)QDC1_BASE) /** Array initializer of QDC peripheral base addresses */ #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } /** Array initializer of QDC peripheral base pointers */ #define QDC_BASE_PTRS { QDC0, QDC1 } #endif /** Interrupt vectors for the QDC peripheral type */ #define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn } #define QDC_HOME_IRQS { QDC0_HOME_IRQn, QDC1_HOME_IRQn } #define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn, QDC1_WDG_SAB_IRQn } #define QDC_INDEX_IRQS { QDC0_IDX_IRQn, QDC1_IDX_IRQn } /*! * @} */ /* end of group QDC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RTC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer * @{ */ /** RTC - Register Layout Typedef */ typedef struct { __IO uint16_t YEARMON; /**< Year and Month Counters, offset: 0x0 */ __IO uint16_t DAYS; /**< Days and Day-of-Week Counters, offset: 0x2 */ __IO uint16_t HOURMIN; /**< Hours and Minutes Counters, offset: 0x4 */ __IO uint16_t SECONDS; /**< Seconds Counters, offset: 0x6 */ __IO uint16_t ALM_YEARMON; /**< Year and Months Alarm, offset: 0x8 */ __IO uint16_t ALM_DAYS; /**< Days Alarm, offset: 0xA */ __IO uint16_t ALM_HOURMIN; /**< Hours and Minutes Alarm, offset: 0xC */ __IO uint16_t ALM_SECONDS; /**< Seconds Alarm, offset: 0xE */ __IO uint16_t CTRL; /**< Control, offset: 0x10 */ __IO uint16_t STATUS; /**< Status, offset: 0x12 */ __IO uint16_t ISR; /**< Interrupt Status, offset: 0x14 */ __IO uint16_t IER; /**< Interrupt Enable, offset: 0x16 */ uint8_t RESERVED_0[4]; __I uint16_t RTC_TEST2; /**< Sub Second Counter, offset: 0x1C */ uint8_t RESERVED_1[4]; __IO uint16_t DST_HOUR; /**< Daylight Saving Hour, offset: 0x22 */ __IO uint16_t DST_MONTH; /**< Daylight Saving Month, offset: 0x24 */ __IO uint16_t DST_DAY; /**< Daylight Saving Day, offset: 0x26 */ __IO uint16_t COMPEN; /**< Compensation, offset: 0x28 */ uint8_t RESERVED_2[2006]; __IO uint32_t SUBSECOND_CTRL; /**< Subsecond Control, offset: 0x800 */ __I uint32_t SUBSECOND_CNT; /**< Subsecond Counter, offset: 0x804 */ uint8_t RESERVED_3[1016]; __IO uint32_t WAKE_TIMER_CTRL; /**< Wake Timer Control, offset: 0xC00 */ uint8_t RESERVED_4[8]; __IO uint32_t WAKE_TIMER_CNT; /**< Wake Timer Counter, offset: 0xC0C */ } RTC_Type; /* ---------------------------------------------------------------------------- -- RTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Register_Masks RTC Register Masks * @{ */ /*! @name YEARMON - Year and Month Counters */ /*! @{ */ #define RTC_YEARMON_MON_CNT_MASK (0xFU) #define RTC_YEARMON_MON_CNT_SHIFT (0U) /*! MON_CNT - Month Counter * 0b0000, 0b1101, 0b1110, 0b1111..Illegal Value * 0b0001..January * 0b0010..February * 0b0011..March * 0b0100..April * 0b0101..May * 0b0110..June * 0b0111..July * 0b1000..August * 0b1001..September * 0b1010..October * 0b1011..November * 0b1100..December */ #define RTC_YEARMON_MON_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK) #define RTC_YEARMON_YROFST_MASK (0xFF00U) #define RTC_YEARMON_YROFST_SHIFT (8U) /*! YROFST - Year Offset Count Value */ #define RTC_YEARMON_YROFST(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK) /*! @} */ /*! @name DAYS - Days and Day-of-Week Counters */ /*! @{ */ #define RTC_DAYS_DAY_CNT_MASK (0x1FU) #define RTC_DAYS_DAY_CNT_SHIFT (0U) /*! DAY_CNT - Days Counter Value */ #define RTC_DAYS_DAY_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK) #define RTC_DAYS_DOW_MASK (0x700U) #define RTC_DAYS_DOW_SHIFT (8U) /*! DOW - Day of Week Counter Value * 0b000..Sunday * 0b001..Monday * 0b010..Tuesday * 0b011..Wednesday * 0b100..Thursday * 0b101..Friday * 0b110..Saturday * 0b111.. */ #define RTC_DAYS_DOW(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK) /*! @} */ /*! @name HOURMIN - Hours and Minutes Counters */ /*! @{ */ #define RTC_HOURMIN_MIN_CNT_MASK (0x3FU) #define RTC_HOURMIN_MIN_CNT_SHIFT (0U) /*! MIN_CNT - Minutes Counter Value */ #define RTC_HOURMIN_MIN_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK) #define RTC_HOURMIN_HOUR_CNT_MASK (0x1F00U) #define RTC_HOURMIN_HOUR_CNT_SHIFT (8U) /*! HOUR_CNT - Hours Counter Value */ #define RTC_HOURMIN_HOUR_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK) /*! @} */ /*! @name SECONDS - Seconds Counters */ /*! @{ */ #define RTC_SECONDS_SEC_CNT_MASK (0x3FU) #define RTC_SECONDS_SEC_CNT_SHIFT (0U) /*! SEC_CNT - Seconds Counter Value */ #define RTC_SECONDS_SEC_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK) /*! @} */ /*! @name ALM_YEARMON - Year and Months Alarm */ /*! @{ */ #define RTC_ALM_YEARMON_ALM_MON_MASK (0xFU) #define RTC_ALM_YEARMON_ALM_MON_SHIFT (0U) /*! ALM_MON - Months Value for Alarm */ #define RTC_ALM_YEARMON_ALM_MON(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK) #define RTC_ALM_YEARMON_ALM_YEAR_MASK (0xFF00U) #define RTC_ALM_YEARMON_ALM_YEAR_SHIFT (8U) /*! ALM_YEAR - Year Value for Alarm */ #define RTC_ALM_YEARMON_ALM_YEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK) /*! @} */ /*! @name ALM_DAYS - Days Alarm */ /*! @{ */ #define RTC_ALM_DAYS_ALM_DAY_MASK (0x1FU) #define RTC_ALM_DAYS_ALM_DAY_SHIFT (0U) /*! ALM_DAY - Days Value for Alarm */ #define RTC_ALM_DAYS_ALM_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK) /*! @} */ /*! @name ALM_HOURMIN - Hours and Minutes Alarm */ /*! @{ */ #define RTC_ALM_HOURMIN_ALM_MIN_MASK (0x3FU) #define RTC_ALM_HOURMIN_ALM_MIN_SHIFT (0U) /*! ALM_MIN - Minutes Value for Alarm */ #define RTC_ALM_HOURMIN_ALM_MIN(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK) #define RTC_ALM_HOURMIN_ALM_HOUR_MASK (0x1F00U) #define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT (8U) /*! ALM_HOUR - Hours Value for Alarm */ #define RTC_ALM_HOURMIN_ALM_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK) /*! @} */ /*! @name ALM_SECONDS - Seconds Alarm */ /*! @{ */ #define RTC_ALM_SECONDS_ALM_SEC_MASK (0x3FU) #define RTC_ALM_SECONDS_ALM_SEC_SHIFT (0U) /*! ALM_SEC - Seconds Alarm Value */ #define RTC_ALM_SECONDS_ALM_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK) #define RTC_ALM_SECONDS_DEC_SEC_MASK (0x100U) #define RTC_ALM_SECONDS_DEC_SEC_SHIFT (8U) /*! DEC_SEC - Decrement Seconds Counter by 1. */ #define RTC_ALM_SECONDS_DEC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK) #define RTC_ALM_SECONDS_INC_SEC_MASK (0x200U) #define RTC_ALM_SECONDS_INC_SEC_SHIFT (9U) /*! INC_SEC - Increment Seconds Counter by 1. */ #define RTC_ALM_SECONDS_INC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK) /*! @} */ /*! @name CTRL - Control */ /*! @{ */ #define RTC_CTRL_FINEEN_MASK (0x1U) #define RTC_CTRL_FINEEN_SHIFT (0U) /*! FINEEN - Fine Compensation Enable * 0b1..Fine compensation is enabled. * 0b0..Fine compensation is disabled */ #define RTC_CTRL_FINEEN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK) #define RTC_CTRL_COMP_EN_MASK (0x2U) #define RTC_CTRL_COMP_EN_SHIFT (1U) /*! COMP_EN - Compensation Enable * 0b0..Coarse compensation is disabled. * 0b1..Coarse compensation is enabled. */ #define RTC_CTRL_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK) #define RTC_CTRL_ALM_MATCH_MASK (0xCU) #define RTC_CTRL_ALM_MATCH_SHIFT (2U) /*! ALM_MATCH - Alarm Match * 0b00..Only seconds, minutes, and hours matched. * 0b01..Only seconds, minutes, hours, and days matched. * 0b10..Only seconds, minutes, hours, days, and months matched. * 0b11..Only seconds, minutes, hours, days, months, and year (offset) matched. */ #define RTC_CTRL_ALM_MATCH(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK) #define RTC_CTRL_DST_EN_MASK (0x40U) #define RTC_CTRL_DST_EN_SHIFT (6U) /*! DST_EN - Daylight Saving Enable * 0b0..Disabled * 0b1..Enabled */ #define RTC_CTRL_DST_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK) #define RTC_CTRL_SWR_MASK (0x100U) #define RTC_CTRL_SWR_SHIFT (8U) /*! SWR - Software Reset * 0b0..Software Reset cleared * 0b1..Software Reset asserted */ #define RTC_CTRL_SWR(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK) #define RTC_CTRL_CLK_SEL_MASK (0x200U) #define RTC_CTRL_CLK_SEL_SHIFT (9U) /*! CLK_SEL - RTC Clock Select * 0b0..16.384 kHz clock is selected * 0b1..32.768 kHz clock is selected */ #define RTC_CTRL_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLK_SEL_SHIFT)) & RTC_CTRL_CLK_SEL_MASK) #define RTC_CTRL_CLKO_DIS_MASK (0x400U) #define RTC_CTRL_CLKO_DIS_SHIFT (10U) /*! CLKO_DIS - Clock Output Disable * 0b0..The selected clock is output to other peripherals. * 0b1..The selected clock is not output to other peripherals. */ #define RTC_CTRL_CLKO_DIS(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKO_DIS_SHIFT)) & RTC_CTRL_CLKO_DIS_MASK) #define RTC_CTRL_CLKOUT_MASK (0x6000U) #define RTC_CTRL_CLKOUT_SHIFT (13U) /*! CLKOUT - RTC Clock Output Selection * 0b00..No output clock * 0b01..Fine 1 Hz clock with both precise edges * 0b10..32.768 or 16.384 kHz clock * 0b11..Coarse 1 Hz clock with both precise edges */ #define RTC_CTRL_CLKOUT(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK) /*! @} */ /*! @name STATUS - Status */ /*! @{ */ #define RTC_STATUS_INVAL_BIT_MASK (0x1U) #define RTC_STATUS_INVAL_BIT_SHIFT (0U) /*! INVAL_BIT - Invalidate CPU Read/Write Access * 0b0..Time and date counters can be read or written. Time and date is valid. * 0b1..Time and date counter values are changing or time and date is invalid and cannot be read or written. */ #define RTC_STATUS_INVAL_BIT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK) #define RTC_STATUS_WRITE_PROT_EN_MASK (0x2U) #define RTC_STATUS_WRITE_PROT_EN_SHIFT (1U) /*! WRITE_PROT_EN - Write Protect Enable Status * 0b0..Registers are unlocked and can be accessed. * 0b1..Registers are locked and in read-only mode. */ #define RTC_STATUS_WRITE_PROT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK) #define RTC_STATUS_CMP_INT_MASK (0x20U) #define RTC_STATUS_CMP_INT_SHIFT (5U) /*! CMP_INT - Compensation Interval */ #define RTC_STATUS_CMP_INT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK) #define RTC_STATUS_WE_MASK (0xC0U) #define RTC_STATUS_WE_SHIFT (6U) /*! WE - Write Enable * 0b10..Enable Write Protection - Registers are locked. */ #define RTC_STATUS_WE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK) #define RTC_STATUS_BUS_ERR_MASK (0x100U) #define RTC_STATUS_BUS_ERR_SHIFT (8U) /*! BUS_ERR - Bus Error * 0b0..Read and write accesses are normal. * 0b1..Read or write accesses occurred when STATUS[INVAL_BIT] was asserted. */ #define RTC_STATUS_BUS_ERR(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK) #define RTC_STATUS_CMP_DONE_MASK (0x800U) #define RTC_STATUS_CMP_DONE_SHIFT (11U) /*! CMP_DONE - Compensation Done * 0b0..Compensation busy or not enabled * 0b1..Compensation completed */ #define RTC_STATUS_CMP_DONE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK) /*! @} */ /*! @name ISR - Interrupt Status */ /*! @{ */ #define RTC_ISR_ALM_IS_MASK (0x4U) #define RTC_ISR_ALM_IS_SHIFT (2U) /*! ALM_IS - Alarm Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_ALM_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK) #define RTC_ISR_DAY_IS_MASK (0x8U) #define RTC_ISR_DAY_IS_SHIFT (3U) /*! DAY_IS - Days Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_DAY_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK) #define RTC_ISR_HOUR_IS_MASK (0x10U) #define RTC_ISR_HOUR_IS_SHIFT (4U) /*! HOUR_IS - Hours Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_HOUR_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK) #define RTC_ISR_MIN_IS_MASK (0x20U) #define RTC_ISR_MIN_IS_SHIFT (5U) /*! MIN_IS - Minutes Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_MIN_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK) #define RTC_ISR_IS_1HZ_MASK (0x40U) #define RTC_ISR_IS_1HZ_SHIFT (6U) /*! IS_1HZ - 1 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK) #define RTC_ISR_IS_2HZ_MASK (0x80U) #define RTC_ISR_IS_2HZ_SHIFT (7U) /*! IS_2HZ - 2 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK) #define RTC_ISR_IS_4HZ_MASK (0x100U) #define RTC_ISR_IS_4HZ_SHIFT (8U) /*! IS_4HZ - 4 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK) #define RTC_ISR_IS_8HZ_MASK (0x200U) #define RTC_ISR_IS_8HZ_SHIFT (9U) /*! IS_8HZ - 8 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK) #define RTC_ISR_IS_16HZ_MASK (0x400U) #define RTC_ISR_IS_16HZ_SHIFT (10U) /*! IS_16HZ - 16 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK) #define RTC_ISR_IS_32HZ_MASK (0x800U) #define RTC_ISR_IS_32HZ_SHIFT (11U) /*! IS_32HZ - 32 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK) #define RTC_ISR_IS_64HZ_MASK (0x1000U) #define RTC_ISR_IS_64HZ_SHIFT (12U) /*! IS_64HZ - 64 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK) #define RTC_ISR_IS_128HZ_MASK (0x2000U) #define RTC_ISR_IS_128HZ_SHIFT (13U) /*! IS_128HZ - 128 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK) #define RTC_ISR_IS_256HZ_MASK (0x4000U) #define RTC_ISR_IS_256HZ_SHIFT (14U) /*! IS_256HZ - 256 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK) #define RTC_ISR_IS_512HZ_MASK (0x8000U) #define RTC_ISR_IS_512HZ_SHIFT (15U) /*! IS_512HZ - 512 Hz Interval Interrupt Status * 0b0..Interrupt is de-asserted. * 0b1..Interrupt is asserted. */ #define RTC_ISR_IS_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK) /*! @} */ /*! @name IER - Interrupt Enable */ /*! @{ */ #define RTC_IER_ALM_IE_MASK (0x4U) #define RTC_IER_ALM_IE_SHIFT (2U) /*! ALM_IE - Alarm Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_ALM_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK) #define RTC_IER_DAY_IE_MASK (0x8U) #define RTC_IER_DAY_IE_SHIFT (3U) /*! DAY_IE - Days Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_DAY_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK) #define RTC_IER_HOUR_IE_MASK (0x10U) #define RTC_IER_HOUR_IE_SHIFT (4U) /*! HOUR_IE - Hours Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_HOUR_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK) #define RTC_IER_MIN_IE_MASK (0x20U) #define RTC_IER_MIN_IE_SHIFT (5U) /*! MIN_IE - Minutes Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_MIN_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK) #define RTC_IER_IE_1HZ_MASK (0x40U) #define RTC_IER_IE_1HZ_SHIFT (6U) /*! IE_1HZ - 1 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK) #define RTC_IER_IE_2HZ_MASK (0x80U) #define RTC_IER_IE_2HZ_SHIFT (7U) /*! IE_2HZ - 2 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK) #define RTC_IER_IE_4HZ_MASK (0x100U) #define RTC_IER_IE_4HZ_SHIFT (8U) /*! IE_4HZ - 4 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK) #define RTC_IER_IE_8HZ_MASK (0x200U) #define RTC_IER_IE_8HZ_SHIFT (9U) /*! IE_8HZ - 8 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK) #define RTC_IER_IE_16HZ_MASK (0x400U) #define RTC_IER_IE_16HZ_SHIFT (10U) /*! IE_16HZ - 16 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK) #define RTC_IER_IE_32HZ_MASK (0x800U) #define RTC_IER_IE_32HZ_SHIFT (11U) /*! IE_32HZ - 32 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK) #define RTC_IER_IE_64HZ_MASK (0x1000U) #define RTC_IER_IE_64HZ_SHIFT (12U) /*! IE_64HZ - 64 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK) #define RTC_IER_IE_128HZ_MASK (0x2000U) #define RTC_IER_IE_128HZ_SHIFT (13U) /*! IE_128HZ - 128 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK) #define RTC_IER_IE_256HZ_MASK (0x4000U) #define RTC_IER_IE_256HZ_SHIFT (14U) /*! IE_256HZ - 256 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK) #define RTC_IER_IE_512HZ_MASK (0x8000U) #define RTC_IER_IE_512HZ_SHIFT (15U) /*! IE_512HZ - 512 Hz Interval Interrupt Enable * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define RTC_IER_IE_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK) /*! @} */ /*! @name RTC_TEST2 - Sub Second Counter */ /*! @{ */ #define RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK (0xFFFFU) #define RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT (0U) /*! SUB_SECOND_COUNT - Sub Second Counter Value */ #define RTC_RTC_TEST2_SUB_SECOND_COUNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT)) & RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK) /*! @} */ /*! @name DST_HOUR - Daylight Saving Hour */ /*! @{ */ #define RTC_DST_HOUR_DST_END_HOUR_MASK (0x1FU) #define RTC_DST_HOUR_DST_END_HOUR_SHIFT (0U) /*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value */ #define RTC_DST_HOUR_DST_END_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK) #define RTC_DST_HOUR_DST_START_HOUR_MASK (0x1F00U) #define RTC_DST_HOUR_DST_START_HOUR_SHIFT (8U) /*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value */ #define RTC_DST_HOUR_DST_START_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK) /*! @} */ /*! @name DST_MONTH - Daylight Saving Month */ /*! @{ */ #define RTC_DST_MONTH_DST_END_MONTH_MASK (0xFU) #define RTC_DST_MONTH_DST_END_MONTH_SHIFT (0U) /*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value */ #define RTC_DST_MONTH_DST_END_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK) #define RTC_DST_MONTH_DST_START_MONTH_MASK (0xF00U) #define RTC_DST_MONTH_DST_START_MONTH_SHIFT (8U) /*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value */ #define RTC_DST_MONTH_DST_START_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK) /*! @} */ /*! @name DST_DAY - Daylight Saving Day */ /*! @{ */ #define RTC_DST_DAY_DST_END_DAY_MASK (0x1FU) #define RTC_DST_DAY_DST_END_DAY_SHIFT (0U) /*! DST_END_DAY - Daylight Saving Time (DST) Day End Value */ #define RTC_DST_DAY_DST_END_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK) #define RTC_DST_DAY_DST_START_DAY_MASK (0x1F00U) #define RTC_DST_DAY_DST_START_DAY_SHIFT (8U) /*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value */ #define RTC_DST_DAY_DST_START_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK) /*! @} */ /*! @name COMPEN - Compensation */ /*! @{ */ #define RTC_COMPEN_COMPEN_VAL_MASK (0xFFFFU) #define RTC_COMPEN_COMPEN_VAL_SHIFT (0U) /*! COMPEN_VAL - Compensation Value */ #define RTC_COMPEN_COMPEN_VAL(x) (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK) /*! @} */ /*! @name SUBSECOND_CTRL - Subsecond Control */ /*! @{ */ #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U) #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U) /*! SUB_SECOND_CNT_EN - Subsecond Counter Enable * 0b0..Disable * 0b1..Enable */ #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK) /*! @} */ /*! @name SUBSECOND_CNT - Subsecond Counter */ /*! @{ */ #define RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK (0xFFFFU) #define RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT (0U) /*! SUBSECOND_CNT - Current Subsecond Counter Value */ #define RTC_SUBSECOND_CNT_SUBSECOND_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT)) & RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK) /*! @} */ /*! @name WAKE_TIMER_CTRL - Wake Timer Control */ /*! @{ */ #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) /*! WAKE_FLAG - Wake Timer Status Flag * 0b0..Not timed out * 0b1..Timed out */ #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) /*! CLR_WAKE_TIMER - Clear Wake Timer * 0b0..No effect * 0b1..Clear the wake timer counter */ #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) /*! OSC_DIV_ENA - OSC Divide Enable * 0b0..Disable * 0b1..Enable */ #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) #define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) #define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) /*! INTR_EN - Enable Interrupt * 0b0..Disable * 0b1..Enable */ #define RTC_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) /*! @} */ /*! @name WAKE_TIMER_CNT - Wake Timer Counter */ /*! @{ */ #define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) #define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) /*! WAKE_CNT - Wake Counter */ #define RTC_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK) /*! @} */ /*! * @} */ /* end of group RTC_Register_Masks */ /* RTC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral RTC0 base address */ #define RTC0_BASE (0x5004C000u) /** Peripheral RTC0 base address */ #define RTC0_BASE_NS (0x4004C000u) /** Peripheral RTC0 base pointer */ #define RTC0 ((RTC_Type *)RTC0_BASE) /** Peripheral RTC0 base pointer */ #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) /** Array initializer of RTC peripheral base addresses */ #define RTC_BASE_ADDRS { RTC0_BASE } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC0 } /** Array initializer of RTC peripheral base addresses */ #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS_NS { RTC0_NS } #else /** Peripheral RTC0 base address */ #define RTC0_BASE (0x4004C000u) /** Peripheral RTC0 base pointer */ #define RTC0 ((RTC_Type *)RTC0_BASE) /** Array initializer of RTC peripheral base addresses */ #define RTC_BASE_ADDRS { RTC0_BASE } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC0 } #endif /** Interrupt vectors for the RTC peripheral type */ #define RTC_IRQS { RTC_IRQn } /* Backward compatibility for RTC */ #define RTC RTC0 /*! * @} */ /* end of group RTC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- S50 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup S50_Peripheral_Access_Layer S50 Peripheral Access Layer * @{ */ /** S50 - Register Layout Typedef */ typedef struct { __I uint32_t ELS_STATUS; /**< Status Register, offset: 0x0 */ __IO uint32_t ELS_CTRL; /**< Control Register, offset: 0x4 */ __IO uint32_t ELS_CMDCFG0; /**< Command Configuration, offset: 0x8 */ __IO uint32_t ELS_CFG; /**< Configuration Register, offset: 0xC */ __IO uint32_t ELS_KIDX0; /**< Keystore Index 0, offset: 0x10 */ __IO uint32_t ELS_KIDX1; /**< Keystore Index 1, offset: 0x14 */ __IO uint32_t ELS_KPROPIN; /**< Key Properties Request, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t ELS_DMA_SRC0; /**< DMA Source 0, offset: 0x20 */ __IO uint32_t ELS_DMA_SRC0_LEN; /**< DMA Source 0 Length, offset: 0x24 */ __IO uint32_t ELS_DMA_SRC1; /**< DMA Source 1, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t ELS_DMA_SRC2; /**< DMA Source 2, offset: 0x30 */ __IO uint32_t ELS_DMA_SRC2_LEN; /**< DMA Source 2 Length, offset: 0x34 */ __IO uint32_t ELS_DMA_RES0; /**< DMA Result 0, offset: 0x38 */ __IO uint32_t ELS_DMA_RES0_LEN; /**< DMA Result 0 Length, offset: 0x3C */ __IO uint32_t ELS_INT_ENABLE; /**< Interrupt Enable, offset: 0x40 */ __O uint32_t ELS_INT_STATUS_CLR; /**< Interrupt Status Clear, offset: 0x44 */ __O uint32_t ELS_INT_STATUS_SET; /**< Interrupt Status Set, offset: 0x48 */ __I uint32_t ELS_ERR_STATUS; /**< Error Status, offset: 0x4C */ __O uint32_t ELS_ERR_STATUS_CLR; /**< Error Status Clear, offset: 0x50 */ __I uint32_t ELS_VERSION; /**< Version Register, offset: 0x54 */ uint8_t RESERVED_2[4]; __I uint32_t ELS_PRNG_DATOUT; /**< PRNG SW Read Out, offset: 0x5C */ __IO uint32_t ELS_CMDCRC_CTRL; /**< CRC Configuration, offset: 0x60 */ __I uint32_t ELS_CMDCRC; /**< Command CRC Value, offset: 0x64 */ __IO uint32_t ELS_SESSION_ID; /**< Session ID, offset: 0x68 */ uint8_t RESERVED_3[4]; __I uint32_t ELS_DMA_FIN_ADDR; /**< Final DMA Address, offset: 0x70 */ __IO uint32_t ELS_MASTER_ID; /**< Master ID, offset: 0x74 */ __IO uint32_t ELS_KIDX2; /**< Keystore Index 2, offset: 0x78 */ uint8_t RESERVED_4[212]; __I uint32_t ELS_KS0; /**< Status Register, offset: 0x150 */ __I uint32_t ELS_KS1; /**< Status Register, offset: 0x154 */ __I uint32_t ELS_KS2; /**< Status Register, offset: 0x158 */ __I uint32_t ELS_KS3; /**< Status Register, offset: 0x15C */ __I uint32_t ELS_KS4; /**< Status Register, offset: 0x160 */ __I uint32_t ELS_KS5; /**< Status Register, offset: 0x164 */ __I uint32_t ELS_KS6; /**< Status Register, offset: 0x168 */ __I uint32_t ELS_KS7; /**< Status Register, offset: 0x16C */ __I uint32_t ELS_KS8; /**< Status Register, offset: 0x170 */ __I uint32_t ELS_KS9; /**< Status Register, offset: 0x174 */ __I uint32_t ELS_KS10; /**< Status Register, offset: 0x178 */ __I uint32_t ELS_KS11; /**< Status Register, offset: 0x17C */ __I uint32_t ELS_KS12; /**< Status Register, offset: 0x180 */ __I uint32_t ELS_KS13; /**< Status Register, offset: 0x184 */ __I uint32_t ELS_KS14; /**< Status Register, offset: 0x188 */ __I uint32_t ELS_KS15; /**< Status Register, offset: 0x18C */ __I uint32_t ELS_KS16; /**< Status Register, offset: 0x190 */ __I uint32_t ELS_KS17; /**< Status Register, offset: 0x194 */ __I uint32_t ELS_KS18; /**< Status Register, offset: 0x198 */ __I uint32_t ELS_KS19; /**< Status Register, offset: 0x19C */ } S50_Type; /* ---------------------------------------------------------------------------- -- S50 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup S50_Register_Masks S50 Register Masks * @{ */ /*! @name ELS_STATUS - Status Register */ /*! @{ */ #define S50_ELS_STATUS_ELS_BUSY_MASK (0x1U) #define S50_ELS_STATUS_ELS_BUSY_SHIFT (0U) /*! ELS_BUSY * 0b1..Crypto sequence executing * 0b0..Crypto sequence not executing */ #define S50_ELS_STATUS_ELS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_BUSY_SHIFT)) & S50_ELS_STATUS_ELS_BUSY_MASK) #define S50_ELS_STATUS_ELS_IRQ_MASK (0x2U) #define S50_ELS_STATUS_ELS_IRQ_SHIFT (1U) /*! ELS_IRQ * 0b1..Active interrupt * 0b0..No active interrupt */ #define S50_ELS_STATUS_ELS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_IRQ_SHIFT)) & S50_ELS_STATUS_ELS_IRQ_MASK) #define S50_ELS_STATUS_ELS_ERR_MASK (0x4U) #define S50_ELS_STATUS_ELS_ERR_SHIFT (2U) /*! ELS_ERR * 0b1..Internal error detected * 0b0..Internal error not detected */ #define S50_ELS_STATUS_ELS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_ERR_SHIFT)) & S50_ELS_STATUS_ELS_ERR_MASK) #define S50_ELS_STATUS_PRNG_RDY_MASK (0x8U) #define S50_ELS_STATUS_PRNG_RDY_SHIFT (3U) /*! PRNG_RDY * 0b0..Internal PRNG not ready * 0b1..Internal PRNG ready */ #define S50_ELS_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PRNG_RDY_SHIFT)) & S50_ELS_STATUS_PRNG_RDY_MASK) #define S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK (0x30U) #define S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT (4U) /*! ECDSA_VFY_STATUS * 0b11..Invalid, Error * 0b00..No verify run * 0b01..Signature verify failed * 0b10..Signature verify passed */ #define S50_ELS_STATUS_ECDSA_VFY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK) #define S50_ELS_STATUS_PPROT_MASK (0xC0U) #define S50_ELS_STATUS_PPROT_SHIFT (6U) /*! PPROT * 0b10..Non-secure, non-privileged * 0b11..Non-secure, privileged * 0b00..Secure, non-privileged * 0b01..Secure, privileged */ #define S50_ELS_STATUS_PPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PPROT_SHIFT)) & S50_ELS_STATUS_PPROT_MASK) #define S50_ELS_STATUS_DRBG_ENT_LVL_MASK (0x300U) #define S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT (8U) /*! DRBG_ENT_LVL * 0b10..HIGH, DRBG generates random numbers of high quality entropy * 0b01..LOW, DRBG generates random numbers of low quality entropy * 0b00..NONE * 0b11..RFU, Reserved for Future Use */ #define S50_ELS_STATUS_DRBG_ENT_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_ELS_STATUS_DRBG_ENT_LVL_MASK) #define S50_ELS_STATUS_DTRNG_BUSY_MASK (0x400U) #define S50_ELS_STATUS_DTRNG_BUSY_SHIFT (10U) /*! DTRNG_BUSY * 0b1..Gathering entropy * 0b0..Not gathering entropy */ #define S50_ELS_STATUS_DTRNG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DTRNG_BUSY_SHIFT)) & S50_ELS_STATUS_DTRNG_BUSY_MASK) #define S50_ELS_STATUS_ELS_LOCKED_MASK (0x10000U) #define S50_ELS_STATUS_ELS_LOCKED_SHIFT (16U) /*! ELS_LOCKED * 0b1..Locked by master * 0b0..Not locked by master */ #define S50_ELS_STATUS_ELS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_LOCKED_SHIFT)) & S50_ELS_STATUS_ELS_LOCKED_MASK) /*! @} */ /*! @name ELS_CTRL - Control Register */ /*! @{ */ #define S50_ELS_CTRL_ELS_EN_MASK (0x1U) #define S50_ELS_CTRL_ELS_EN_SHIFT (0U) /*! ELS_EN * 0b0..Disabled * 0b1..Enabled */ #define S50_ELS_CTRL_ELS_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_EN_SHIFT)) & S50_ELS_CTRL_ELS_EN_MASK) #define S50_ELS_CTRL_ELS_START_MASK (0x2U) #define S50_ELS_CTRL_ELS_START_SHIFT (1U) #define S50_ELS_CTRL_ELS_START(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_START_SHIFT)) & S50_ELS_CTRL_ELS_START_MASK) #define S50_ELS_CTRL_ELS_RESET_MASK (0x4U) #define S50_ELS_CTRL_ELS_RESET_SHIFT (2U) #define S50_ELS_CTRL_ELS_RESET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_RESET_SHIFT)) & S50_ELS_CTRL_ELS_RESET_MASK) #define S50_ELS_CTRL_ELS_CMD_MASK (0xF8U) #define S50_ELS_CTRL_ELS_CMD_SHIFT (3U) /*! ELS_CMD - ELS Command ID */ #define S50_ELS_CTRL_ELS_CMD(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_CMD_SHIFT)) & S50_ELS_CTRL_ELS_CMD_MASK) #define S50_ELS_CTRL_BYTE_ORDER_MASK (0x100U) #define S50_ELS_CTRL_BYTE_ORDER_SHIFT (8U) /*! BYTE_ORDER * 0b1..Big endian * 0b0..Little endian */ #define S50_ELS_CTRL_BYTE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_BYTE_ORDER_SHIFT)) & S50_ELS_CTRL_BYTE_ORDER_MASK) /*! @} */ /*! @name ELS_CMDCFG0 - Command Configuration */ /*! @{ */ #define S50_ELS_CMDCFG0_CMDCFG0_MASK (0xFFFFFFFFU) #define S50_ELS_CMDCFG0_CMDCFG0_SHIFT (0U) #define S50_ELS_CMDCFG0_CMDCFG0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCFG0_CMDCFG0_SHIFT)) & S50_ELS_CMDCFG0_CMDCFG0_MASK) /*! @} */ /*! @name ELS_CFG - Configuration Register */ /*! @{ */ #define S50_ELS_CFG_ADCTRL_MASK (0x3FF0000U) #define S50_ELS_CFG_ADCTRL_SHIFT (16U) #define S50_ELS_CFG_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CFG_ADCTRL_SHIFT)) & S50_ELS_CFG_ADCTRL_MASK) /*! @} */ /*! @name ELS_KIDX0 - Keystore Index 0 */ /*! @{ */ #define S50_ELS_KIDX0_KIDX0_MASK (0x1FU) #define S50_ELS_KIDX0_KIDX0_SHIFT (0U) #define S50_ELS_KIDX0_KIDX0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX0_KIDX0_SHIFT)) & S50_ELS_KIDX0_KIDX0_MASK) /*! @} */ /*! @name ELS_KIDX1 - Keystore Index 1 */ /*! @{ */ #define S50_ELS_KIDX1_KIDX1_MASK (0x1FU) #define S50_ELS_KIDX1_KIDX1_SHIFT (0U) #define S50_ELS_KIDX1_KIDX1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX1_KIDX1_SHIFT)) & S50_ELS_KIDX1_KIDX1_MASK) /*! @} */ /*! @name ELS_KPROPIN - Key Properties Request */ /*! @{ */ #define S50_ELS_KPROPIN_KPROPIN_MASK (0xFFFFFFFFU) #define S50_ELS_KPROPIN_KPROPIN_SHIFT (0U) #define S50_ELS_KPROPIN_KPROPIN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KPROPIN_KPROPIN_SHIFT)) & S50_ELS_KPROPIN_KPROPIN_MASK) /*! @} */ /*! @name ELS_DMA_SRC0 - DMA Source 0 */ /*! @{ */ #define S50_ELS_DMA_SRC0_ADDR_SRC0_MASK (0xFFFFFFFFU) #define S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT (0U) #define S50_ELS_DMA_SRC0_ADDR_SRC0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_ELS_DMA_SRC0_ADDR_SRC0_MASK) /*! @} */ /*! @name ELS_DMA_SRC0_LEN - DMA Source 0 Length */ /*! @{ */ #define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK (0xFFFFFFFFU) #define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U) #define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK) /*! @} */ /*! @name ELS_DMA_SRC1 - DMA Source 1 */ /*! @{ */ #define S50_ELS_DMA_SRC1_ADDR_SRC1_MASK (0xFFFFFFFFU) #define S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT (0U) #define S50_ELS_DMA_SRC1_ADDR_SRC1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_ELS_DMA_SRC1_ADDR_SRC1_MASK) /*! @} */ /*! @name ELS_DMA_SRC2 - DMA Source 2 */ /*! @{ */ #define S50_ELS_DMA_SRC2_ADDR_SRC2_MASK (0xFFFFFFFFU) #define S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT (0U) #define S50_ELS_DMA_SRC2_ADDR_SRC2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_ELS_DMA_SRC2_ADDR_SRC2_MASK) /*! @} */ /*! @name ELS_DMA_SRC2_LEN - DMA Source 2 Length */ /*! @{ */ #define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK (0xFFFFFFFFU) #define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U) #define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK) /*! @} */ /*! @name ELS_DMA_RES0 - DMA Result 0 */ /*! @{ */ #define S50_ELS_DMA_RES0_ADDR_RES0_MASK (0xFFFFFFFFU) #define S50_ELS_DMA_RES0_ADDR_RES0_SHIFT (0U) #define S50_ELS_DMA_RES0_ADDR_RES0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & S50_ELS_DMA_RES0_ADDR_RES0_MASK) /*! @} */ /*! @name ELS_DMA_RES0_LEN - DMA Result 0 Length */ /*! @{ */ #define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK (0xFFFFFFFFU) #define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U) #define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK) /*! @} */ /*! @name ELS_INT_ENABLE - Interrupt Enable */ /*! @{ */ #define S50_ELS_INT_ENABLE_INT_EN_MASK (0x1U) #define S50_ELS_INT_ENABLE_INT_EN_SHIFT (0U) /*! INT_EN * 0b0..Disables * 0b1..Enables */ #define S50_ELS_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_ENABLE_INT_EN_SHIFT)) & S50_ELS_INT_ENABLE_INT_EN_MASK) /*! @} */ /*! @name ELS_INT_STATUS_CLR - Interrupt Status Clear */ /*! @{ */ #define S50_ELS_INT_STATUS_CLR_INT_CLR_MASK (0x1U) #define S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT (0U) #define S50_ELS_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_ELS_INT_STATUS_CLR_INT_CLR_MASK) /*! @} */ /*! @name ELS_INT_STATUS_SET - Interrupt Status Set */ /*! @{ */ #define S50_ELS_INT_STATUS_SET_INT_SET_MASK (0x1U) #define S50_ELS_INT_STATUS_SET_INT_SET_SHIFT (0U) #define S50_ELS_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & S50_ELS_INT_STATUS_SET_INT_SET_MASK) /*! @} */ /*! @name ELS_ERR_STATUS - Error Status */ /*! @{ */ #define S50_ELS_ERR_STATUS_BUS_ERR_MASK (0x1U) #define S50_ELS_ERR_STATUS_BUS_ERR_SHIFT (0U) /*! BUS_ERR * 0b0..No error * 0b1..Error occurred */ #define S50_ELS_ERR_STATUS_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ELS_ERR_STATUS_BUS_ERR_MASK) #define S50_ELS_ERR_STATUS_OPN_ERR_MASK (0x2U) #define S50_ELS_ERR_STATUS_OPN_ERR_SHIFT (1U) /*! OPN_ERR * 0b0..No error * 0b1..Error occurred */ #define S50_ELS_ERR_STATUS_OPN_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ELS_ERR_STATUS_OPN_ERR_MASK) #define S50_ELS_ERR_STATUS_ALG_ERR_MASK (0x4U) #define S50_ELS_ERR_STATUS_ALG_ERR_SHIFT (2U) /*! ALG_ERR * 0b0..No error * 0b1..Error occurred */ #define S50_ELS_ERR_STATUS_ALG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ALG_ERR_MASK) #define S50_ELS_ERR_STATUS_ITG_ERR_MASK (0x8U) #define S50_ELS_ERR_STATUS_ITG_ERR_SHIFT (3U) /*! ITG_ERR * 0b0..No error * 0b1..Error occurred */ #define S50_ELS_ERR_STATUS_ITG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ITG_ERR_MASK) #define S50_ELS_ERR_STATUS_FLT_ERR_MASK (0x10U) #define S50_ELS_ERR_STATUS_FLT_ERR_SHIFT (4U) /*! FLT_ERR * 0b0..No error * 0b1..Error occurred */ #define S50_ELS_ERR_STATUS_FLT_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ELS_ERR_STATUS_FLT_ERR_MASK) #define S50_ELS_ERR_STATUS_PRNG_ERR_MASK (0x20U) #define S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT (5U) /*! PRNG_ERR * 0b0..No error * 0b1..Error occurred */ #define S50_ELS_ERR_STATUS_PRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_PRNG_ERR_MASK) #define S50_ELS_ERR_STATUS_ERR_LVL_MASK (0xC0U) #define S50_ELS_ERR_STATUS_ERR_LVL_SHIFT (6U) #define S50_ELS_ERR_STATUS_ERR_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ELS_ERR_STATUS_ERR_LVL_MASK) #define S50_ELS_ERR_STATUS_DTRNG_ERR_MASK (0x100U) #define S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT (8U) /*! DTRNG_ERR * 0b0..No error * 0b1..TRNG error occurred */ #define S50_ELS_ERR_STATUS_DTRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_DTRNG_ERR_MASK) /*! @} */ /*! @name ELS_ERR_STATUS_CLR - Error Status Clear */ /*! @{ */ #define S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK (0x1U) #define S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT (0U) /*! ERR_CLR * 0b1..Clears ELS error state * 0b0..Exits ELS error state */ #define S50_ELS_ERR_STATUS_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK) /*! @} */ /*! @name ELS_VERSION - Version Register */ /*! @{ */ #define S50_ELS_VERSION_Z_MASK (0xFU) #define S50_ELS_VERSION_Z_SHIFT (0U) #define S50_ELS_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Z_SHIFT)) & S50_ELS_VERSION_Z_MASK) #define S50_ELS_VERSION_Y2_MASK (0xF0U) #define S50_ELS_VERSION_Y2_SHIFT (4U) #define S50_ELS_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y2_SHIFT)) & S50_ELS_VERSION_Y2_MASK) #define S50_ELS_VERSION_Y1_MASK (0xF00U) #define S50_ELS_VERSION_Y1_SHIFT (8U) #define S50_ELS_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y1_SHIFT)) & S50_ELS_VERSION_Y1_MASK) #define S50_ELS_VERSION_X_MASK (0xF000U) #define S50_ELS_VERSION_X_SHIFT (12U) #define S50_ELS_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_X_SHIFT)) & S50_ELS_VERSION_X_MASK) #define S50_ELS_VERSION_SW_Z_MASK (0xF0000U) #define S50_ELS_VERSION_SW_Z_SHIFT (16U) #define S50_ELS_VERSION_SW_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Z_SHIFT)) & S50_ELS_VERSION_SW_Z_MASK) #define S50_ELS_VERSION_SW_Y2_MASK (0xF00000U) #define S50_ELS_VERSION_SW_Y2_SHIFT (20U) #define S50_ELS_VERSION_SW_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y2_SHIFT)) & S50_ELS_VERSION_SW_Y2_MASK) #define S50_ELS_VERSION_SW_Y1_MASK (0xF000000U) #define S50_ELS_VERSION_SW_Y1_SHIFT (24U) #define S50_ELS_VERSION_SW_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y1_SHIFT)) & S50_ELS_VERSION_SW_Y1_MASK) #define S50_ELS_VERSION_SW_X_MASK (0xF0000000U) #define S50_ELS_VERSION_SW_X_SHIFT (28U) #define S50_ELS_VERSION_SW_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_X_SHIFT)) & S50_ELS_VERSION_SW_X_MASK) /*! @} */ /*! @name ELS_PRNG_DATOUT - PRNG SW Read Out */ /*! @{ */ #define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK (0xFFFFFFFFU) #define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT (0U) #define S50_ELS_PRNG_DATOUT_PRNG_DATOUT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK) /*! @} */ /*! @name ELS_CMDCRC_CTRL - CRC Configuration */ /*! @{ */ #define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK (0x1U) #define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT (0U) /*! CMDCRC_RST * 0b1..Resets the CRC command to its default value * 0b0..No effect */ #define S50_ELS_CMDCRC_CTRL_CMDCRC_RST(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK) #define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK (0x2U) #define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT (1U) /*! CMDCRC_EN * 0b1..Enables the CRC command. The CRC command will be updated on completion of each ELS command. * 0b0..Disables the CRC command CRC. The CRC command will not be updated on completion of each ELS command. */ #define S50_ELS_CMDCRC_CTRL_CMDCRC_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK) /*! @} */ /*! @name ELS_CMDCRC - Command CRC Value */ /*! @{ */ #define S50_ELS_CMDCRC_CMDCRC_MASK (0xFFFFFFFFU) #define S50_ELS_CMDCRC_CMDCRC_SHIFT (0U) #define S50_ELS_CMDCRC_CMDCRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CMDCRC_SHIFT)) & S50_ELS_CMDCRC_CMDCRC_MASK) /*! @} */ /*! @name ELS_SESSION_ID - Session ID */ /*! @{ */ #define S50_ELS_SESSION_ID_SESSION_ID_MASK (0xFFFFFFFFU) #define S50_ELS_SESSION_ID_SESSION_ID_SHIFT (0U) #define S50_ELS_SESSION_ID_SESSION_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_SESSION_ID_SESSION_ID_SHIFT)) & S50_ELS_SESSION_ID_SESSION_ID_MASK) /*! @} */ /*! @name ELS_DMA_FIN_ADDR - Final DMA Address */ /*! @{ */ #define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK (0xFFFFFFFFU) #define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT (0U) #define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK) /*! @} */ /*! @name ELS_MASTER_ID - Master ID */ /*! @{ */ #define S50_ELS_MASTER_ID_MASTER_ID_MASK (0x1FU) #define S50_ELS_MASTER_ID_MASTER_ID_SHIFT (0U) #define S50_ELS_MASTER_ID_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_MASTER_ID_MASTER_ID_SHIFT)) & S50_ELS_MASTER_ID_MASTER_ID_MASK) /*! @} */ /*! @name ELS_KIDX2 - Keystore Index 2 */ /*! @{ */ #define S50_ELS_KIDX2_KIDX2_MASK (0x1FU) #define S50_ELS_KIDX2_KIDX2_SHIFT (0U) #define S50_ELS_KIDX2_KIDX2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX2_KIDX2_SHIFT)) & S50_ELS_KIDX2_KIDX2_MASK) /*! @} */ /*! @name ELS_KS0 - Status Register */ /*! @{ */ #define S50_ELS_KS0_KS0_KSIZE_MASK (0x3U) #define S50_ELS_KS0_KS0_KSIZE_SHIFT (0U) /*! KS0_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS0_KS0_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KSIZE_SHIFT)) & S50_ELS_KS0_KS0_KSIZE_MASK) #define S50_ELS_KS0_KS0_KACT_MASK (0x20U) #define S50_ELS_KS0_KS0_KACT_SHIFT (5U) #define S50_ELS_KS0_KS0_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KACT_SHIFT)) & S50_ELS_KS0_KS0_KACT_MASK) #define S50_ELS_KS0_KS0_KBASE_MASK (0x40U) #define S50_ELS_KS0_KS0_KBASE_SHIFT (6U) #define S50_ELS_KS0_KS0_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KBASE_SHIFT)) & S50_ELS_KS0_KS0_KBASE_MASK) #define S50_ELS_KS0_KS0_FGP_MASK (0x80U) #define S50_ELS_KS0_KS0_FGP_SHIFT (7U) #define S50_ELS_KS0_KS0_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FGP_SHIFT)) & S50_ELS_KS0_KS0_FGP_MASK) #define S50_ELS_KS0_KS0_FRTN_MASK (0x100U) #define S50_ELS_KS0_KS0_FRTN_SHIFT (8U) #define S50_ELS_KS0_KS0_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FRTN_SHIFT)) & S50_ELS_KS0_KS0_FRTN_MASK) #define S50_ELS_KS0_KS0_FHWO_MASK (0x200U) #define S50_ELS_KS0_KS0_FHWO_SHIFT (9U) #define S50_ELS_KS0_KS0_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FHWO_SHIFT)) & S50_ELS_KS0_KS0_FHWO_MASK) #define S50_ELS_KS0_KS0_UKPUK_MASK (0x800U) #define S50_ELS_KS0_KS0_UKPUK_SHIFT (11U) #define S50_ELS_KS0_KS0_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKPUK_SHIFT)) & S50_ELS_KS0_KS0_UKPUK_MASK) #define S50_ELS_KS0_KS0_UTECDH_MASK (0x1000U) #define S50_ELS_KS0_KS0_UTECDH_SHIFT (12U) #define S50_ELS_KS0_KS0_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTECDH_SHIFT)) & S50_ELS_KS0_KS0_UTECDH_MASK) #define S50_ELS_KS0_KS0_UCMAC_MASK (0x2000U) #define S50_ELS_KS0_KS0_UCMAC_SHIFT (13U) #define S50_ELS_KS0_KS0_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCMAC_SHIFT)) & S50_ELS_KS0_KS0_UCMAC_MASK) #define S50_ELS_KS0_KS0_UKSK_MASK (0x4000U) #define S50_ELS_KS0_KS0_UKSK_SHIFT (14U) #define S50_ELS_KS0_KS0_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKSK_SHIFT)) & S50_ELS_KS0_KS0_UKSK_MASK) #define S50_ELS_KS0_KS0_URTF_MASK (0x8000U) #define S50_ELS_KS0_KS0_URTF_SHIFT (15U) #define S50_ELS_KS0_KS0_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_URTF_SHIFT)) & S50_ELS_KS0_KS0_URTF_MASK) #define S50_ELS_KS0_KS0_UCKDF_MASK (0x10000U) #define S50_ELS_KS0_KS0_UCKDF_SHIFT (16U) #define S50_ELS_KS0_KS0_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCKDF_SHIFT)) & S50_ELS_KS0_KS0_UCKDF_MASK) #define S50_ELS_KS0_KS0_UHKDF_MASK (0x20000U) #define S50_ELS_KS0_KS0_UHKDF_SHIFT (17U) #define S50_ELS_KS0_KS0_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHKDF_SHIFT)) & S50_ELS_KS0_KS0_UHKDF_MASK) #define S50_ELS_KS0_KS0_UECSG_MASK (0x40000U) #define S50_ELS_KS0_KS0_UECSG_SHIFT (18U) #define S50_ELS_KS0_KS0_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECSG_SHIFT)) & S50_ELS_KS0_KS0_UECSG_MASK) #define S50_ELS_KS0_KS0_UECDH_MASK (0x80000U) #define S50_ELS_KS0_KS0_UECDH_SHIFT (19U) #define S50_ELS_KS0_KS0_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECDH_SHIFT)) & S50_ELS_KS0_KS0_UECDH_MASK) #define S50_ELS_KS0_KS0_UAES_MASK (0x100000U) #define S50_ELS_KS0_KS0_UAES_SHIFT (20U) #define S50_ELS_KS0_KS0_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UAES_SHIFT)) & S50_ELS_KS0_KS0_UAES_MASK) #define S50_ELS_KS0_KS0_UHMAC_MASK (0x200000U) #define S50_ELS_KS0_KS0_UHMAC_SHIFT (21U) #define S50_ELS_KS0_KS0_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHMAC_SHIFT)) & S50_ELS_KS0_KS0_UHMAC_MASK) #define S50_ELS_KS0_KS0_UKWK_MASK (0x400000U) #define S50_ELS_KS0_KS0_UKWK_SHIFT (22U) #define S50_ELS_KS0_KS0_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKWK_SHIFT)) & S50_ELS_KS0_KS0_UKWK_MASK) #define S50_ELS_KS0_KS0_UKUOK_MASK (0x800000U) #define S50_ELS_KS0_KS0_UKUOK_SHIFT (23U) #define S50_ELS_KS0_KS0_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKUOK_SHIFT)) & S50_ELS_KS0_KS0_UKUOK_MASK) #define S50_ELS_KS0_KS0_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS0_KS0_UTLSPMS_SHIFT (24U) #define S50_ELS_KS0_KS0_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSPMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSPMS_MASK) #define S50_ELS_KS0_KS0_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS0_KS0_UTLSMS_SHIFT (25U) #define S50_ELS_KS0_KS0_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSMS_MASK) #define S50_ELS_KS0_KS0_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS0_KS0_UKGSRC_SHIFT (26U) #define S50_ELS_KS0_KS0_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKGSRC_SHIFT)) & S50_ELS_KS0_KS0_UKGSRC_MASK) #define S50_ELS_KS0_KS0_UHWO_MASK (0x8000000U) #define S50_ELS_KS0_KS0_UHWO_SHIFT (27U) #define S50_ELS_KS0_KS0_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHWO_SHIFT)) & S50_ELS_KS0_KS0_UHWO_MASK) #define S50_ELS_KS0_KS0_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS0_KS0_UWRPOK_SHIFT (28U) #define S50_ELS_KS0_KS0_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UWRPOK_SHIFT)) & S50_ELS_KS0_KS0_UWRPOK_MASK) #define S50_ELS_KS0_KS0_UDUK_MASK (0x20000000U) #define S50_ELS_KS0_KS0_UDUK_SHIFT (29U) #define S50_ELS_KS0_KS0_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UDUK_SHIFT)) & S50_ELS_KS0_KS0_UDUK_MASK) #define S50_ELS_KS0_KS0_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS0_KS0_UPPROT_SHIFT (30U) #define S50_ELS_KS0_KS0_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UPPROT_SHIFT)) & S50_ELS_KS0_KS0_UPPROT_MASK) /*! @} */ /*! @name ELS_KS1 - Status Register */ /*! @{ */ #define S50_ELS_KS1_KS1_KSIZE_MASK (0x3U) #define S50_ELS_KS1_KS1_KSIZE_SHIFT (0U) /*! KS1_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS1_KS1_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KSIZE_SHIFT)) & S50_ELS_KS1_KS1_KSIZE_MASK) #define S50_ELS_KS1_KS1_KACT_MASK (0x20U) #define S50_ELS_KS1_KS1_KACT_SHIFT (5U) #define S50_ELS_KS1_KS1_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KACT_SHIFT)) & S50_ELS_KS1_KS1_KACT_MASK) #define S50_ELS_KS1_KS1_KBASE_MASK (0x40U) #define S50_ELS_KS1_KS1_KBASE_SHIFT (6U) #define S50_ELS_KS1_KS1_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KBASE_SHIFT)) & S50_ELS_KS1_KS1_KBASE_MASK) #define S50_ELS_KS1_KS1_FGP_MASK (0x80U) #define S50_ELS_KS1_KS1_FGP_SHIFT (7U) #define S50_ELS_KS1_KS1_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FGP_SHIFT)) & S50_ELS_KS1_KS1_FGP_MASK) #define S50_ELS_KS1_KS1_FRTN_MASK (0x100U) #define S50_ELS_KS1_KS1_FRTN_SHIFT (8U) #define S50_ELS_KS1_KS1_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FRTN_SHIFT)) & S50_ELS_KS1_KS1_FRTN_MASK) #define S50_ELS_KS1_KS1_FHWO_MASK (0x200U) #define S50_ELS_KS1_KS1_FHWO_SHIFT (9U) #define S50_ELS_KS1_KS1_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FHWO_SHIFT)) & S50_ELS_KS1_KS1_FHWO_MASK) #define S50_ELS_KS1_KS1_UKPUK_MASK (0x800U) #define S50_ELS_KS1_KS1_UKPUK_SHIFT (11U) #define S50_ELS_KS1_KS1_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKPUK_SHIFT)) & S50_ELS_KS1_KS1_UKPUK_MASK) #define S50_ELS_KS1_KS1_UTECDH_MASK (0x1000U) #define S50_ELS_KS1_KS1_UTECDH_SHIFT (12U) #define S50_ELS_KS1_KS1_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTECDH_SHIFT)) & S50_ELS_KS1_KS1_UTECDH_MASK) #define S50_ELS_KS1_KS1_UCMAC_MASK (0x2000U) #define S50_ELS_KS1_KS1_UCMAC_SHIFT (13U) #define S50_ELS_KS1_KS1_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCMAC_SHIFT)) & S50_ELS_KS1_KS1_UCMAC_MASK) #define S50_ELS_KS1_KS1_UKSK_MASK (0x4000U) #define S50_ELS_KS1_KS1_UKSK_SHIFT (14U) #define S50_ELS_KS1_KS1_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKSK_SHIFT)) & S50_ELS_KS1_KS1_UKSK_MASK) #define S50_ELS_KS1_KS1_URTF_MASK (0x8000U) #define S50_ELS_KS1_KS1_URTF_SHIFT (15U) #define S50_ELS_KS1_KS1_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_URTF_SHIFT)) & S50_ELS_KS1_KS1_URTF_MASK) #define S50_ELS_KS1_KS1_UCKDF_MASK (0x10000U) #define S50_ELS_KS1_KS1_UCKDF_SHIFT (16U) #define S50_ELS_KS1_KS1_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCKDF_SHIFT)) & S50_ELS_KS1_KS1_UCKDF_MASK) #define S50_ELS_KS1_KS1_UHKDF_MASK (0x20000U) #define S50_ELS_KS1_KS1_UHKDF_SHIFT (17U) #define S50_ELS_KS1_KS1_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHKDF_SHIFT)) & S50_ELS_KS1_KS1_UHKDF_MASK) #define S50_ELS_KS1_KS1_UECSG_MASK (0x40000U) #define S50_ELS_KS1_KS1_UECSG_SHIFT (18U) #define S50_ELS_KS1_KS1_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECSG_SHIFT)) & S50_ELS_KS1_KS1_UECSG_MASK) #define S50_ELS_KS1_KS1_UECDH_MASK (0x80000U) #define S50_ELS_KS1_KS1_UECDH_SHIFT (19U) #define S50_ELS_KS1_KS1_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECDH_SHIFT)) & S50_ELS_KS1_KS1_UECDH_MASK) #define S50_ELS_KS1_KS1_UAES_MASK (0x100000U) #define S50_ELS_KS1_KS1_UAES_SHIFT (20U) #define S50_ELS_KS1_KS1_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UAES_SHIFT)) & S50_ELS_KS1_KS1_UAES_MASK) #define S50_ELS_KS1_KS1_UHMAC_MASK (0x200000U) #define S50_ELS_KS1_KS1_UHMAC_SHIFT (21U) #define S50_ELS_KS1_KS1_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHMAC_SHIFT)) & S50_ELS_KS1_KS1_UHMAC_MASK) #define S50_ELS_KS1_KS1_UKWK_MASK (0x400000U) #define S50_ELS_KS1_KS1_UKWK_SHIFT (22U) #define S50_ELS_KS1_KS1_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKWK_SHIFT)) & S50_ELS_KS1_KS1_UKWK_MASK) #define S50_ELS_KS1_KS1_UKUOK_MASK (0x800000U) #define S50_ELS_KS1_KS1_UKUOK_SHIFT (23U) #define S50_ELS_KS1_KS1_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKUOK_SHIFT)) & S50_ELS_KS1_KS1_UKUOK_MASK) #define S50_ELS_KS1_KS1_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS1_KS1_UTLSPMS_SHIFT (24U) #define S50_ELS_KS1_KS1_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSPMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSPMS_MASK) #define S50_ELS_KS1_KS1_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS1_KS1_UTLSMS_SHIFT (25U) #define S50_ELS_KS1_KS1_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSMS_MASK) #define S50_ELS_KS1_KS1_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS1_KS1_UKGSRC_SHIFT (26U) #define S50_ELS_KS1_KS1_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKGSRC_SHIFT)) & S50_ELS_KS1_KS1_UKGSRC_MASK) #define S50_ELS_KS1_KS1_UHWO_MASK (0x8000000U) #define S50_ELS_KS1_KS1_UHWO_SHIFT (27U) #define S50_ELS_KS1_KS1_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHWO_SHIFT)) & S50_ELS_KS1_KS1_UHWO_MASK) #define S50_ELS_KS1_KS1_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS1_KS1_UWRPOK_SHIFT (28U) #define S50_ELS_KS1_KS1_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UWRPOK_SHIFT)) & S50_ELS_KS1_KS1_UWRPOK_MASK) #define S50_ELS_KS1_KS1_UDUK_MASK (0x20000000U) #define S50_ELS_KS1_KS1_UDUK_SHIFT (29U) #define S50_ELS_KS1_KS1_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UDUK_SHIFT)) & S50_ELS_KS1_KS1_UDUK_MASK) #define S50_ELS_KS1_KS1_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS1_KS1_UPPROT_SHIFT (30U) #define S50_ELS_KS1_KS1_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UPPROT_SHIFT)) & S50_ELS_KS1_KS1_UPPROT_MASK) /*! @} */ /*! @name ELS_KS2 - Status Register */ /*! @{ */ #define S50_ELS_KS2_KS2_KSIZE_MASK (0x3U) #define S50_ELS_KS2_KS2_KSIZE_SHIFT (0U) /*! KS2_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS2_KS2_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KSIZE_SHIFT)) & S50_ELS_KS2_KS2_KSIZE_MASK) #define S50_ELS_KS2_KS2_KACT_MASK (0x20U) #define S50_ELS_KS2_KS2_KACT_SHIFT (5U) #define S50_ELS_KS2_KS2_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KACT_SHIFT)) & S50_ELS_KS2_KS2_KACT_MASK) #define S50_ELS_KS2_KS2_KBASE_MASK (0x40U) #define S50_ELS_KS2_KS2_KBASE_SHIFT (6U) #define S50_ELS_KS2_KS2_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KBASE_SHIFT)) & S50_ELS_KS2_KS2_KBASE_MASK) #define S50_ELS_KS2_KS2_FGP_MASK (0x80U) #define S50_ELS_KS2_KS2_FGP_SHIFT (7U) #define S50_ELS_KS2_KS2_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FGP_SHIFT)) & S50_ELS_KS2_KS2_FGP_MASK) #define S50_ELS_KS2_KS2_FRTN_MASK (0x100U) #define S50_ELS_KS2_KS2_FRTN_SHIFT (8U) #define S50_ELS_KS2_KS2_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FRTN_SHIFT)) & S50_ELS_KS2_KS2_FRTN_MASK) #define S50_ELS_KS2_KS2_FHWO_MASK (0x200U) #define S50_ELS_KS2_KS2_FHWO_SHIFT (9U) #define S50_ELS_KS2_KS2_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FHWO_SHIFT)) & S50_ELS_KS2_KS2_FHWO_MASK) #define S50_ELS_KS2_KS2_UKPUK_MASK (0x800U) #define S50_ELS_KS2_KS2_UKPUK_SHIFT (11U) #define S50_ELS_KS2_KS2_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKPUK_SHIFT)) & S50_ELS_KS2_KS2_UKPUK_MASK) #define S50_ELS_KS2_KS2_UTECDH_MASK (0x1000U) #define S50_ELS_KS2_KS2_UTECDH_SHIFT (12U) #define S50_ELS_KS2_KS2_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTECDH_SHIFT)) & S50_ELS_KS2_KS2_UTECDH_MASK) #define S50_ELS_KS2_KS2_UCMAC_MASK (0x2000U) #define S50_ELS_KS2_KS2_UCMAC_SHIFT (13U) #define S50_ELS_KS2_KS2_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCMAC_SHIFT)) & S50_ELS_KS2_KS2_UCMAC_MASK) #define S50_ELS_KS2_KS2_UKSK_MASK (0x4000U) #define S50_ELS_KS2_KS2_UKSK_SHIFT (14U) #define S50_ELS_KS2_KS2_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKSK_SHIFT)) & S50_ELS_KS2_KS2_UKSK_MASK) #define S50_ELS_KS2_KS2_URTF_MASK (0x8000U) #define S50_ELS_KS2_KS2_URTF_SHIFT (15U) #define S50_ELS_KS2_KS2_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_URTF_SHIFT)) & S50_ELS_KS2_KS2_URTF_MASK) #define S50_ELS_KS2_KS2_UCKDF_MASK (0x10000U) #define S50_ELS_KS2_KS2_UCKDF_SHIFT (16U) #define S50_ELS_KS2_KS2_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCKDF_SHIFT)) & S50_ELS_KS2_KS2_UCKDF_MASK) #define S50_ELS_KS2_KS2_UHKDF_MASK (0x20000U) #define S50_ELS_KS2_KS2_UHKDF_SHIFT (17U) #define S50_ELS_KS2_KS2_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHKDF_SHIFT)) & S50_ELS_KS2_KS2_UHKDF_MASK) #define S50_ELS_KS2_KS2_UECSG_MASK (0x40000U) #define S50_ELS_KS2_KS2_UECSG_SHIFT (18U) #define S50_ELS_KS2_KS2_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECSG_SHIFT)) & S50_ELS_KS2_KS2_UECSG_MASK) #define S50_ELS_KS2_KS2_UECDH_MASK (0x80000U) #define S50_ELS_KS2_KS2_UECDH_SHIFT (19U) #define S50_ELS_KS2_KS2_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECDH_SHIFT)) & S50_ELS_KS2_KS2_UECDH_MASK) #define S50_ELS_KS2_KS2_UAES_MASK (0x100000U) #define S50_ELS_KS2_KS2_UAES_SHIFT (20U) #define S50_ELS_KS2_KS2_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UAES_SHIFT)) & S50_ELS_KS2_KS2_UAES_MASK) #define S50_ELS_KS2_KS2_UHMAC_MASK (0x200000U) #define S50_ELS_KS2_KS2_UHMAC_SHIFT (21U) #define S50_ELS_KS2_KS2_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHMAC_SHIFT)) & S50_ELS_KS2_KS2_UHMAC_MASK) #define S50_ELS_KS2_KS2_UKWK_MASK (0x400000U) #define S50_ELS_KS2_KS2_UKWK_SHIFT (22U) #define S50_ELS_KS2_KS2_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKWK_SHIFT)) & S50_ELS_KS2_KS2_UKWK_MASK) #define S50_ELS_KS2_KS2_UKUOK_MASK (0x800000U) #define S50_ELS_KS2_KS2_UKUOK_SHIFT (23U) #define S50_ELS_KS2_KS2_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKUOK_SHIFT)) & S50_ELS_KS2_KS2_UKUOK_MASK) #define S50_ELS_KS2_KS2_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS2_KS2_UTLSPMS_SHIFT (24U) #define S50_ELS_KS2_KS2_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSPMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSPMS_MASK) #define S50_ELS_KS2_KS2_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS2_KS2_UTLSMS_SHIFT (25U) #define S50_ELS_KS2_KS2_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSMS_MASK) #define S50_ELS_KS2_KS2_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS2_KS2_UKGSRC_SHIFT (26U) #define S50_ELS_KS2_KS2_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKGSRC_SHIFT)) & S50_ELS_KS2_KS2_UKGSRC_MASK) #define S50_ELS_KS2_KS2_UHWO_MASK (0x8000000U) #define S50_ELS_KS2_KS2_UHWO_SHIFT (27U) #define S50_ELS_KS2_KS2_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHWO_SHIFT)) & S50_ELS_KS2_KS2_UHWO_MASK) #define S50_ELS_KS2_KS2_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS2_KS2_UWRPOK_SHIFT (28U) #define S50_ELS_KS2_KS2_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UWRPOK_SHIFT)) & S50_ELS_KS2_KS2_UWRPOK_MASK) #define S50_ELS_KS2_KS2_UDUK_MASK (0x20000000U) #define S50_ELS_KS2_KS2_UDUK_SHIFT (29U) #define S50_ELS_KS2_KS2_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UDUK_SHIFT)) & S50_ELS_KS2_KS2_UDUK_MASK) #define S50_ELS_KS2_KS2_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS2_KS2_UPPROT_SHIFT (30U) #define S50_ELS_KS2_KS2_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UPPROT_SHIFT)) & S50_ELS_KS2_KS2_UPPROT_MASK) /*! @} */ /*! @name ELS_KS3 - Status Register */ /*! @{ */ #define S50_ELS_KS3_KS3_KSIZE_MASK (0x3U) #define S50_ELS_KS3_KS3_KSIZE_SHIFT (0U) /*! KS3_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS3_KS3_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KSIZE_SHIFT)) & S50_ELS_KS3_KS3_KSIZE_MASK) #define S50_ELS_KS3_KS3_KACT_MASK (0x20U) #define S50_ELS_KS3_KS3_KACT_SHIFT (5U) #define S50_ELS_KS3_KS3_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KACT_SHIFT)) & S50_ELS_KS3_KS3_KACT_MASK) #define S50_ELS_KS3_KS3_KBASE_MASK (0x40U) #define S50_ELS_KS3_KS3_KBASE_SHIFT (6U) #define S50_ELS_KS3_KS3_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KBASE_SHIFT)) & S50_ELS_KS3_KS3_KBASE_MASK) #define S50_ELS_KS3_KS3_FGP_MASK (0x80U) #define S50_ELS_KS3_KS3_FGP_SHIFT (7U) #define S50_ELS_KS3_KS3_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FGP_SHIFT)) & S50_ELS_KS3_KS3_FGP_MASK) #define S50_ELS_KS3_KS3_FRTN_MASK (0x100U) #define S50_ELS_KS3_KS3_FRTN_SHIFT (8U) #define S50_ELS_KS3_KS3_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FRTN_SHIFT)) & S50_ELS_KS3_KS3_FRTN_MASK) #define S50_ELS_KS3_KS3_FHWO_MASK (0x200U) #define S50_ELS_KS3_KS3_FHWO_SHIFT (9U) #define S50_ELS_KS3_KS3_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FHWO_SHIFT)) & S50_ELS_KS3_KS3_FHWO_MASK) #define S50_ELS_KS3_KS3_UKPUK_MASK (0x800U) #define S50_ELS_KS3_KS3_UKPUK_SHIFT (11U) #define S50_ELS_KS3_KS3_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKPUK_SHIFT)) & S50_ELS_KS3_KS3_UKPUK_MASK) #define S50_ELS_KS3_KS3_UTECDH_MASK (0x1000U) #define S50_ELS_KS3_KS3_UTECDH_SHIFT (12U) #define S50_ELS_KS3_KS3_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTECDH_SHIFT)) & S50_ELS_KS3_KS3_UTECDH_MASK) #define S50_ELS_KS3_KS3_UCMAC_MASK (0x2000U) #define S50_ELS_KS3_KS3_UCMAC_SHIFT (13U) #define S50_ELS_KS3_KS3_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCMAC_SHIFT)) & S50_ELS_KS3_KS3_UCMAC_MASK) #define S50_ELS_KS3_KS3_UKSK_MASK (0x4000U) #define S50_ELS_KS3_KS3_UKSK_SHIFT (14U) #define S50_ELS_KS3_KS3_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKSK_SHIFT)) & S50_ELS_KS3_KS3_UKSK_MASK) #define S50_ELS_KS3_KS3_URTF_MASK (0x8000U) #define S50_ELS_KS3_KS3_URTF_SHIFT (15U) #define S50_ELS_KS3_KS3_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_URTF_SHIFT)) & S50_ELS_KS3_KS3_URTF_MASK) #define S50_ELS_KS3_KS3_UCKDF_MASK (0x10000U) #define S50_ELS_KS3_KS3_UCKDF_SHIFT (16U) #define S50_ELS_KS3_KS3_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCKDF_SHIFT)) & S50_ELS_KS3_KS3_UCKDF_MASK) #define S50_ELS_KS3_KS3_UHKDF_MASK (0x20000U) #define S50_ELS_KS3_KS3_UHKDF_SHIFT (17U) #define S50_ELS_KS3_KS3_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHKDF_SHIFT)) & S50_ELS_KS3_KS3_UHKDF_MASK) #define S50_ELS_KS3_KS3_UECSG_MASK (0x40000U) #define S50_ELS_KS3_KS3_UECSG_SHIFT (18U) #define S50_ELS_KS3_KS3_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECSG_SHIFT)) & S50_ELS_KS3_KS3_UECSG_MASK) #define S50_ELS_KS3_KS3_UECDH_MASK (0x80000U) #define S50_ELS_KS3_KS3_UECDH_SHIFT (19U) #define S50_ELS_KS3_KS3_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECDH_SHIFT)) & S50_ELS_KS3_KS3_UECDH_MASK) #define S50_ELS_KS3_KS3_UAES_MASK (0x100000U) #define S50_ELS_KS3_KS3_UAES_SHIFT (20U) #define S50_ELS_KS3_KS3_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UAES_SHIFT)) & S50_ELS_KS3_KS3_UAES_MASK) #define S50_ELS_KS3_KS3_UHMAC_MASK (0x200000U) #define S50_ELS_KS3_KS3_UHMAC_SHIFT (21U) #define S50_ELS_KS3_KS3_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHMAC_SHIFT)) & S50_ELS_KS3_KS3_UHMAC_MASK) #define S50_ELS_KS3_KS3_UKWK_MASK (0x400000U) #define S50_ELS_KS3_KS3_UKWK_SHIFT (22U) #define S50_ELS_KS3_KS3_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKWK_SHIFT)) & S50_ELS_KS3_KS3_UKWK_MASK) #define S50_ELS_KS3_KS3_UKUOK_MASK (0x800000U) #define S50_ELS_KS3_KS3_UKUOK_SHIFT (23U) #define S50_ELS_KS3_KS3_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKUOK_SHIFT)) & S50_ELS_KS3_KS3_UKUOK_MASK) #define S50_ELS_KS3_KS3_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS3_KS3_UTLSPMS_SHIFT (24U) #define S50_ELS_KS3_KS3_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSPMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSPMS_MASK) #define S50_ELS_KS3_KS3_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS3_KS3_UTLSMS_SHIFT (25U) #define S50_ELS_KS3_KS3_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSMS_MASK) #define S50_ELS_KS3_KS3_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS3_KS3_UKGSRC_SHIFT (26U) #define S50_ELS_KS3_KS3_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKGSRC_SHIFT)) & S50_ELS_KS3_KS3_UKGSRC_MASK) #define S50_ELS_KS3_KS3_UHWO_MASK (0x8000000U) #define S50_ELS_KS3_KS3_UHWO_SHIFT (27U) #define S50_ELS_KS3_KS3_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHWO_SHIFT)) & S50_ELS_KS3_KS3_UHWO_MASK) #define S50_ELS_KS3_KS3_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS3_KS3_UWRPOK_SHIFT (28U) #define S50_ELS_KS3_KS3_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UWRPOK_SHIFT)) & S50_ELS_KS3_KS3_UWRPOK_MASK) #define S50_ELS_KS3_KS3_UDUK_MASK (0x20000000U) #define S50_ELS_KS3_KS3_UDUK_SHIFT (29U) #define S50_ELS_KS3_KS3_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UDUK_SHIFT)) & S50_ELS_KS3_KS3_UDUK_MASK) #define S50_ELS_KS3_KS3_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS3_KS3_UPPROT_SHIFT (30U) #define S50_ELS_KS3_KS3_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UPPROT_SHIFT)) & S50_ELS_KS3_KS3_UPPROT_MASK) /*! @} */ /*! @name ELS_KS4 - Status Register */ /*! @{ */ #define S50_ELS_KS4_KS4_KSIZE_MASK (0x3U) #define S50_ELS_KS4_KS4_KSIZE_SHIFT (0U) /*! KS4_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS4_KS4_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KSIZE_SHIFT)) & S50_ELS_KS4_KS4_KSIZE_MASK) #define S50_ELS_KS4_KS4_KACT_MASK (0x20U) #define S50_ELS_KS4_KS4_KACT_SHIFT (5U) #define S50_ELS_KS4_KS4_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KACT_SHIFT)) & S50_ELS_KS4_KS4_KACT_MASK) #define S50_ELS_KS4_KS4_KBASE_MASK (0x40U) #define S50_ELS_KS4_KS4_KBASE_SHIFT (6U) #define S50_ELS_KS4_KS4_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KBASE_SHIFT)) & S50_ELS_KS4_KS4_KBASE_MASK) #define S50_ELS_KS4_KS4_FGP_MASK (0x80U) #define S50_ELS_KS4_KS4_FGP_SHIFT (7U) #define S50_ELS_KS4_KS4_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FGP_SHIFT)) & S50_ELS_KS4_KS4_FGP_MASK) #define S50_ELS_KS4_KS4_FRTN_MASK (0x100U) #define S50_ELS_KS4_KS4_FRTN_SHIFT (8U) #define S50_ELS_KS4_KS4_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FRTN_SHIFT)) & S50_ELS_KS4_KS4_FRTN_MASK) #define S50_ELS_KS4_KS4_FHWO_MASK (0x200U) #define S50_ELS_KS4_KS4_FHWO_SHIFT (9U) #define S50_ELS_KS4_KS4_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FHWO_SHIFT)) & S50_ELS_KS4_KS4_FHWO_MASK) #define S50_ELS_KS4_KS4_UKPUK_MASK (0x800U) #define S50_ELS_KS4_KS4_UKPUK_SHIFT (11U) #define S50_ELS_KS4_KS4_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKPUK_SHIFT)) & S50_ELS_KS4_KS4_UKPUK_MASK) #define S50_ELS_KS4_KS4_UTECDH_MASK (0x1000U) #define S50_ELS_KS4_KS4_UTECDH_SHIFT (12U) #define S50_ELS_KS4_KS4_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTECDH_SHIFT)) & S50_ELS_KS4_KS4_UTECDH_MASK) #define S50_ELS_KS4_KS4_UCMAC_MASK (0x2000U) #define S50_ELS_KS4_KS4_UCMAC_SHIFT (13U) #define S50_ELS_KS4_KS4_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCMAC_SHIFT)) & S50_ELS_KS4_KS4_UCMAC_MASK) #define S50_ELS_KS4_KS4_UKSK_MASK (0x4000U) #define S50_ELS_KS4_KS4_UKSK_SHIFT (14U) #define S50_ELS_KS4_KS4_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKSK_SHIFT)) & S50_ELS_KS4_KS4_UKSK_MASK) #define S50_ELS_KS4_KS4_URTF_MASK (0x8000U) #define S50_ELS_KS4_KS4_URTF_SHIFT (15U) #define S50_ELS_KS4_KS4_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_URTF_SHIFT)) & S50_ELS_KS4_KS4_URTF_MASK) #define S50_ELS_KS4_KS4_UCKDF_MASK (0x10000U) #define S50_ELS_KS4_KS4_UCKDF_SHIFT (16U) #define S50_ELS_KS4_KS4_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCKDF_SHIFT)) & S50_ELS_KS4_KS4_UCKDF_MASK) #define S50_ELS_KS4_KS4_UHKDF_MASK (0x20000U) #define S50_ELS_KS4_KS4_UHKDF_SHIFT (17U) #define S50_ELS_KS4_KS4_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHKDF_SHIFT)) & S50_ELS_KS4_KS4_UHKDF_MASK) #define S50_ELS_KS4_KS4_UECSG_MASK (0x40000U) #define S50_ELS_KS4_KS4_UECSG_SHIFT (18U) #define S50_ELS_KS4_KS4_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECSG_SHIFT)) & S50_ELS_KS4_KS4_UECSG_MASK) #define S50_ELS_KS4_KS4_UECDH_MASK (0x80000U) #define S50_ELS_KS4_KS4_UECDH_SHIFT (19U) #define S50_ELS_KS4_KS4_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECDH_SHIFT)) & S50_ELS_KS4_KS4_UECDH_MASK) #define S50_ELS_KS4_KS4_UAES_MASK (0x100000U) #define S50_ELS_KS4_KS4_UAES_SHIFT (20U) #define S50_ELS_KS4_KS4_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UAES_SHIFT)) & S50_ELS_KS4_KS4_UAES_MASK) #define S50_ELS_KS4_KS4_UHMAC_MASK (0x200000U) #define S50_ELS_KS4_KS4_UHMAC_SHIFT (21U) #define S50_ELS_KS4_KS4_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHMAC_SHIFT)) & S50_ELS_KS4_KS4_UHMAC_MASK) #define S50_ELS_KS4_KS4_UKWK_MASK (0x400000U) #define S50_ELS_KS4_KS4_UKWK_SHIFT (22U) #define S50_ELS_KS4_KS4_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKWK_SHIFT)) & S50_ELS_KS4_KS4_UKWK_MASK) #define S50_ELS_KS4_KS4_UKUOK_MASK (0x800000U) #define S50_ELS_KS4_KS4_UKUOK_SHIFT (23U) #define S50_ELS_KS4_KS4_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKUOK_SHIFT)) & S50_ELS_KS4_KS4_UKUOK_MASK) #define S50_ELS_KS4_KS4_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS4_KS4_UTLSPMS_SHIFT (24U) #define S50_ELS_KS4_KS4_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSPMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSPMS_MASK) #define S50_ELS_KS4_KS4_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS4_KS4_UTLSMS_SHIFT (25U) #define S50_ELS_KS4_KS4_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSMS_MASK) #define S50_ELS_KS4_KS4_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS4_KS4_UKGSRC_SHIFT (26U) #define S50_ELS_KS4_KS4_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKGSRC_SHIFT)) & S50_ELS_KS4_KS4_UKGSRC_MASK) #define S50_ELS_KS4_KS4_UHWO_MASK (0x8000000U) #define S50_ELS_KS4_KS4_UHWO_SHIFT (27U) #define S50_ELS_KS4_KS4_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHWO_SHIFT)) & S50_ELS_KS4_KS4_UHWO_MASK) #define S50_ELS_KS4_KS4_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS4_KS4_UWRPOK_SHIFT (28U) #define S50_ELS_KS4_KS4_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UWRPOK_SHIFT)) & S50_ELS_KS4_KS4_UWRPOK_MASK) #define S50_ELS_KS4_KS4_UDUK_MASK (0x20000000U) #define S50_ELS_KS4_KS4_UDUK_SHIFT (29U) #define S50_ELS_KS4_KS4_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UDUK_SHIFT)) & S50_ELS_KS4_KS4_UDUK_MASK) #define S50_ELS_KS4_KS4_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS4_KS4_UPPROT_SHIFT (30U) #define S50_ELS_KS4_KS4_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UPPROT_SHIFT)) & S50_ELS_KS4_KS4_UPPROT_MASK) /*! @} */ /*! @name ELS_KS5 - Status Register */ /*! @{ */ #define S50_ELS_KS5_KS5_KSIZE_MASK (0x3U) #define S50_ELS_KS5_KS5_KSIZE_SHIFT (0U) /*! KS5_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS5_KS5_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KSIZE_SHIFT)) & S50_ELS_KS5_KS5_KSIZE_MASK) #define S50_ELS_KS5_KS5_KACT_MASK (0x20U) #define S50_ELS_KS5_KS5_KACT_SHIFT (5U) #define S50_ELS_KS5_KS5_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KACT_SHIFT)) & S50_ELS_KS5_KS5_KACT_MASK) #define S50_ELS_KS5_KS5_KBASE_MASK (0x40U) #define S50_ELS_KS5_KS5_KBASE_SHIFT (6U) #define S50_ELS_KS5_KS5_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KBASE_SHIFT)) & S50_ELS_KS5_KS5_KBASE_MASK) #define S50_ELS_KS5_KS5_FGP_MASK (0x80U) #define S50_ELS_KS5_KS5_FGP_SHIFT (7U) #define S50_ELS_KS5_KS5_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FGP_SHIFT)) & S50_ELS_KS5_KS5_FGP_MASK) #define S50_ELS_KS5_KS5_FRTN_MASK (0x100U) #define S50_ELS_KS5_KS5_FRTN_SHIFT (8U) #define S50_ELS_KS5_KS5_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FRTN_SHIFT)) & S50_ELS_KS5_KS5_FRTN_MASK) #define S50_ELS_KS5_KS5_FHWO_MASK (0x200U) #define S50_ELS_KS5_KS5_FHWO_SHIFT (9U) #define S50_ELS_KS5_KS5_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FHWO_SHIFT)) & S50_ELS_KS5_KS5_FHWO_MASK) #define S50_ELS_KS5_KS5_UKPUK_MASK (0x800U) #define S50_ELS_KS5_KS5_UKPUK_SHIFT (11U) #define S50_ELS_KS5_KS5_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKPUK_SHIFT)) & S50_ELS_KS5_KS5_UKPUK_MASK) #define S50_ELS_KS5_KS5_UTECDH_MASK (0x1000U) #define S50_ELS_KS5_KS5_UTECDH_SHIFT (12U) #define S50_ELS_KS5_KS5_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTECDH_SHIFT)) & S50_ELS_KS5_KS5_UTECDH_MASK) #define S50_ELS_KS5_KS5_UCMAC_MASK (0x2000U) #define S50_ELS_KS5_KS5_UCMAC_SHIFT (13U) #define S50_ELS_KS5_KS5_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCMAC_SHIFT)) & S50_ELS_KS5_KS5_UCMAC_MASK) #define S50_ELS_KS5_KS5_UKSK_MASK (0x4000U) #define S50_ELS_KS5_KS5_UKSK_SHIFT (14U) #define S50_ELS_KS5_KS5_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKSK_SHIFT)) & S50_ELS_KS5_KS5_UKSK_MASK) #define S50_ELS_KS5_KS5_URTF_MASK (0x8000U) #define S50_ELS_KS5_KS5_URTF_SHIFT (15U) #define S50_ELS_KS5_KS5_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_URTF_SHIFT)) & S50_ELS_KS5_KS5_URTF_MASK) #define S50_ELS_KS5_KS5_UCKDF_MASK (0x10000U) #define S50_ELS_KS5_KS5_UCKDF_SHIFT (16U) #define S50_ELS_KS5_KS5_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCKDF_SHIFT)) & S50_ELS_KS5_KS5_UCKDF_MASK) #define S50_ELS_KS5_KS5_UHKDF_MASK (0x20000U) #define S50_ELS_KS5_KS5_UHKDF_SHIFT (17U) #define S50_ELS_KS5_KS5_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHKDF_SHIFT)) & S50_ELS_KS5_KS5_UHKDF_MASK) #define S50_ELS_KS5_KS5_UECSG_MASK (0x40000U) #define S50_ELS_KS5_KS5_UECSG_SHIFT (18U) #define S50_ELS_KS5_KS5_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECSG_SHIFT)) & S50_ELS_KS5_KS5_UECSG_MASK) #define S50_ELS_KS5_KS5_UECDH_MASK (0x80000U) #define S50_ELS_KS5_KS5_UECDH_SHIFT (19U) #define S50_ELS_KS5_KS5_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECDH_SHIFT)) & S50_ELS_KS5_KS5_UECDH_MASK) #define S50_ELS_KS5_KS5_UAES_MASK (0x100000U) #define S50_ELS_KS5_KS5_UAES_SHIFT (20U) #define S50_ELS_KS5_KS5_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UAES_SHIFT)) & S50_ELS_KS5_KS5_UAES_MASK) #define S50_ELS_KS5_KS5_UHMAC_MASK (0x200000U) #define S50_ELS_KS5_KS5_UHMAC_SHIFT (21U) #define S50_ELS_KS5_KS5_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHMAC_SHIFT)) & S50_ELS_KS5_KS5_UHMAC_MASK) #define S50_ELS_KS5_KS5_UKWK_MASK (0x400000U) #define S50_ELS_KS5_KS5_UKWK_SHIFT (22U) #define S50_ELS_KS5_KS5_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKWK_SHIFT)) & S50_ELS_KS5_KS5_UKWK_MASK) #define S50_ELS_KS5_KS5_UKUOK_MASK (0x800000U) #define S50_ELS_KS5_KS5_UKUOK_SHIFT (23U) #define S50_ELS_KS5_KS5_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKUOK_SHIFT)) & S50_ELS_KS5_KS5_UKUOK_MASK) #define S50_ELS_KS5_KS5_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS5_KS5_UTLSPMS_SHIFT (24U) #define S50_ELS_KS5_KS5_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSPMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSPMS_MASK) #define S50_ELS_KS5_KS5_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS5_KS5_UTLSMS_SHIFT (25U) #define S50_ELS_KS5_KS5_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSMS_MASK) #define S50_ELS_KS5_KS5_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS5_KS5_UKGSRC_SHIFT (26U) #define S50_ELS_KS5_KS5_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKGSRC_SHIFT)) & S50_ELS_KS5_KS5_UKGSRC_MASK) #define S50_ELS_KS5_KS5_UHWO_MASK (0x8000000U) #define S50_ELS_KS5_KS5_UHWO_SHIFT (27U) #define S50_ELS_KS5_KS5_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHWO_SHIFT)) & S50_ELS_KS5_KS5_UHWO_MASK) #define S50_ELS_KS5_KS5_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS5_KS5_UWRPOK_SHIFT (28U) #define S50_ELS_KS5_KS5_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UWRPOK_SHIFT)) & S50_ELS_KS5_KS5_UWRPOK_MASK) #define S50_ELS_KS5_KS5_UDUK_MASK (0x20000000U) #define S50_ELS_KS5_KS5_UDUK_SHIFT (29U) #define S50_ELS_KS5_KS5_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UDUK_SHIFT)) & S50_ELS_KS5_KS5_UDUK_MASK) #define S50_ELS_KS5_KS5_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS5_KS5_UPPROT_SHIFT (30U) #define S50_ELS_KS5_KS5_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UPPROT_SHIFT)) & S50_ELS_KS5_KS5_UPPROT_MASK) /*! @} */ /*! @name ELS_KS6 - Status Register */ /*! @{ */ #define S50_ELS_KS6_KS6_KSIZE_MASK (0x3U) #define S50_ELS_KS6_KS6_KSIZE_SHIFT (0U) /*! KS6_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS6_KS6_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KSIZE_SHIFT)) & S50_ELS_KS6_KS6_KSIZE_MASK) #define S50_ELS_KS6_KS6_KACT_MASK (0x20U) #define S50_ELS_KS6_KS6_KACT_SHIFT (5U) #define S50_ELS_KS6_KS6_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KACT_SHIFT)) & S50_ELS_KS6_KS6_KACT_MASK) #define S50_ELS_KS6_KS6_KBASE_MASK (0x40U) #define S50_ELS_KS6_KS6_KBASE_SHIFT (6U) #define S50_ELS_KS6_KS6_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KBASE_SHIFT)) & S50_ELS_KS6_KS6_KBASE_MASK) #define S50_ELS_KS6_KS6_FGP_MASK (0x80U) #define S50_ELS_KS6_KS6_FGP_SHIFT (7U) #define S50_ELS_KS6_KS6_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FGP_SHIFT)) & S50_ELS_KS6_KS6_FGP_MASK) #define S50_ELS_KS6_KS6_FRTN_MASK (0x100U) #define S50_ELS_KS6_KS6_FRTN_SHIFT (8U) #define S50_ELS_KS6_KS6_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FRTN_SHIFT)) & S50_ELS_KS6_KS6_FRTN_MASK) #define S50_ELS_KS6_KS6_FHWO_MASK (0x200U) #define S50_ELS_KS6_KS6_FHWO_SHIFT (9U) #define S50_ELS_KS6_KS6_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FHWO_SHIFT)) & S50_ELS_KS6_KS6_FHWO_MASK) #define S50_ELS_KS6_KS6_UKPUK_MASK (0x800U) #define S50_ELS_KS6_KS6_UKPUK_SHIFT (11U) #define S50_ELS_KS6_KS6_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKPUK_SHIFT)) & S50_ELS_KS6_KS6_UKPUK_MASK) #define S50_ELS_KS6_KS6_UTECDH_MASK (0x1000U) #define S50_ELS_KS6_KS6_UTECDH_SHIFT (12U) #define S50_ELS_KS6_KS6_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTECDH_SHIFT)) & S50_ELS_KS6_KS6_UTECDH_MASK) #define S50_ELS_KS6_KS6_UCMAC_MASK (0x2000U) #define S50_ELS_KS6_KS6_UCMAC_SHIFT (13U) #define S50_ELS_KS6_KS6_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCMAC_SHIFT)) & S50_ELS_KS6_KS6_UCMAC_MASK) #define S50_ELS_KS6_KS6_UKSK_MASK (0x4000U) #define S50_ELS_KS6_KS6_UKSK_SHIFT (14U) #define S50_ELS_KS6_KS6_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKSK_SHIFT)) & S50_ELS_KS6_KS6_UKSK_MASK) #define S50_ELS_KS6_KS6_URTF_MASK (0x8000U) #define S50_ELS_KS6_KS6_URTF_SHIFT (15U) #define S50_ELS_KS6_KS6_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_URTF_SHIFT)) & S50_ELS_KS6_KS6_URTF_MASK) #define S50_ELS_KS6_KS6_UCKDF_MASK (0x10000U) #define S50_ELS_KS6_KS6_UCKDF_SHIFT (16U) #define S50_ELS_KS6_KS6_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCKDF_SHIFT)) & S50_ELS_KS6_KS6_UCKDF_MASK) #define S50_ELS_KS6_KS6_UHKDF_MASK (0x20000U) #define S50_ELS_KS6_KS6_UHKDF_SHIFT (17U) #define S50_ELS_KS6_KS6_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHKDF_SHIFT)) & S50_ELS_KS6_KS6_UHKDF_MASK) #define S50_ELS_KS6_KS6_UECSG_MASK (0x40000U) #define S50_ELS_KS6_KS6_UECSG_SHIFT (18U) #define S50_ELS_KS6_KS6_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECSG_SHIFT)) & S50_ELS_KS6_KS6_UECSG_MASK) #define S50_ELS_KS6_KS6_UECDH_MASK (0x80000U) #define S50_ELS_KS6_KS6_UECDH_SHIFT (19U) #define S50_ELS_KS6_KS6_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECDH_SHIFT)) & S50_ELS_KS6_KS6_UECDH_MASK) #define S50_ELS_KS6_KS6_UAES_MASK (0x100000U) #define S50_ELS_KS6_KS6_UAES_SHIFT (20U) #define S50_ELS_KS6_KS6_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UAES_SHIFT)) & S50_ELS_KS6_KS6_UAES_MASK) #define S50_ELS_KS6_KS6_UHMAC_MASK (0x200000U) #define S50_ELS_KS6_KS6_UHMAC_SHIFT (21U) #define S50_ELS_KS6_KS6_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHMAC_SHIFT)) & S50_ELS_KS6_KS6_UHMAC_MASK) #define S50_ELS_KS6_KS6_UKWK_MASK (0x400000U) #define S50_ELS_KS6_KS6_UKWK_SHIFT (22U) #define S50_ELS_KS6_KS6_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKWK_SHIFT)) & S50_ELS_KS6_KS6_UKWK_MASK) #define S50_ELS_KS6_KS6_UKUOK_MASK (0x800000U) #define S50_ELS_KS6_KS6_UKUOK_SHIFT (23U) #define S50_ELS_KS6_KS6_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKUOK_SHIFT)) & S50_ELS_KS6_KS6_UKUOK_MASK) #define S50_ELS_KS6_KS6_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS6_KS6_UTLSPMS_SHIFT (24U) #define S50_ELS_KS6_KS6_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSPMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSPMS_MASK) #define S50_ELS_KS6_KS6_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS6_KS6_UTLSMS_SHIFT (25U) #define S50_ELS_KS6_KS6_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSMS_MASK) #define S50_ELS_KS6_KS6_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS6_KS6_UKGSRC_SHIFT (26U) #define S50_ELS_KS6_KS6_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKGSRC_SHIFT)) & S50_ELS_KS6_KS6_UKGSRC_MASK) #define S50_ELS_KS6_KS6_UHWO_MASK (0x8000000U) #define S50_ELS_KS6_KS6_UHWO_SHIFT (27U) #define S50_ELS_KS6_KS6_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHWO_SHIFT)) & S50_ELS_KS6_KS6_UHWO_MASK) #define S50_ELS_KS6_KS6_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS6_KS6_UWRPOK_SHIFT (28U) #define S50_ELS_KS6_KS6_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UWRPOK_SHIFT)) & S50_ELS_KS6_KS6_UWRPOK_MASK) #define S50_ELS_KS6_KS6_UDUK_MASK (0x20000000U) #define S50_ELS_KS6_KS6_UDUK_SHIFT (29U) #define S50_ELS_KS6_KS6_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UDUK_SHIFT)) & S50_ELS_KS6_KS6_UDUK_MASK) #define S50_ELS_KS6_KS6_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS6_KS6_UPPROT_SHIFT (30U) #define S50_ELS_KS6_KS6_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UPPROT_SHIFT)) & S50_ELS_KS6_KS6_UPPROT_MASK) /*! @} */ /*! @name ELS_KS7 - Status Register */ /*! @{ */ #define S50_ELS_KS7_KS7_KSIZE_MASK (0x3U) #define S50_ELS_KS7_KS7_KSIZE_SHIFT (0U) /*! KS7_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS7_KS7_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KSIZE_SHIFT)) & S50_ELS_KS7_KS7_KSIZE_MASK) #define S50_ELS_KS7_KS7_KACT_MASK (0x20U) #define S50_ELS_KS7_KS7_KACT_SHIFT (5U) #define S50_ELS_KS7_KS7_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KACT_SHIFT)) & S50_ELS_KS7_KS7_KACT_MASK) #define S50_ELS_KS7_KS7_KBASE_MASK (0x40U) #define S50_ELS_KS7_KS7_KBASE_SHIFT (6U) #define S50_ELS_KS7_KS7_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KBASE_SHIFT)) & S50_ELS_KS7_KS7_KBASE_MASK) #define S50_ELS_KS7_KS7_FGP_MASK (0x80U) #define S50_ELS_KS7_KS7_FGP_SHIFT (7U) #define S50_ELS_KS7_KS7_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FGP_SHIFT)) & S50_ELS_KS7_KS7_FGP_MASK) #define S50_ELS_KS7_KS7_FRTN_MASK (0x100U) #define S50_ELS_KS7_KS7_FRTN_SHIFT (8U) #define S50_ELS_KS7_KS7_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FRTN_SHIFT)) & S50_ELS_KS7_KS7_FRTN_MASK) #define S50_ELS_KS7_KS7_FHWO_MASK (0x200U) #define S50_ELS_KS7_KS7_FHWO_SHIFT (9U) #define S50_ELS_KS7_KS7_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FHWO_SHIFT)) & S50_ELS_KS7_KS7_FHWO_MASK) #define S50_ELS_KS7_KS7_UKPUK_MASK (0x800U) #define S50_ELS_KS7_KS7_UKPUK_SHIFT (11U) #define S50_ELS_KS7_KS7_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKPUK_SHIFT)) & S50_ELS_KS7_KS7_UKPUK_MASK) #define S50_ELS_KS7_KS7_UTECDH_MASK (0x1000U) #define S50_ELS_KS7_KS7_UTECDH_SHIFT (12U) #define S50_ELS_KS7_KS7_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTECDH_SHIFT)) & S50_ELS_KS7_KS7_UTECDH_MASK) #define S50_ELS_KS7_KS7_UCMAC_MASK (0x2000U) #define S50_ELS_KS7_KS7_UCMAC_SHIFT (13U) #define S50_ELS_KS7_KS7_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCMAC_SHIFT)) & S50_ELS_KS7_KS7_UCMAC_MASK) #define S50_ELS_KS7_KS7_UKSK_MASK (0x4000U) #define S50_ELS_KS7_KS7_UKSK_SHIFT (14U) #define S50_ELS_KS7_KS7_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKSK_SHIFT)) & S50_ELS_KS7_KS7_UKSK_MASK) #define S50_ELS_KS7_KS7_URTF_MASK (0x8000U) #define S50_ELS_KS7_KS7_URTF_SHIFT (15U) #define S50_ELS_KS7_KS7_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_URTF_SHIFT)) & S50_ELS_KS7_KS7_URTF_MASK) #define S50_ELS_KS7_KS7_UCKDF_MASK (0x10000U) #define S50_ELS_KS7_KS7_UCKDF_SHIFT (16U) #define S50_ELS_KS7_KS7_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCKDF_SHIFT)) & S50_ELS_KS7_KS7_UCKDF_MASK) #define S50_ELS_KS7_KS7_UHKDF_MASK (0x20000U) #define S50_ELS_KS7_KS7_UHKDF_SHIFT (17U) #define S50_ELS_KS7_KS7_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHKDF_SHIFT)) & S50_ELS_KS7_KS7_UHKDF_MASK) #define S50_ELS_KS7_KS7_UECSG_MASK (0x40000U) #define S50_ELS_KS7_KS7_UECSG_SHIFT (18U) #define S50_ELS_KS7_KS7_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECSG_SHIFT)) & S50_ELS_KS7_KS7_UECSG_MASK) #define S50_ELS_KS7_KS7_UECDH_MASK (0x80000U) #define S50_ELS_KS7_KS7_UECDH_SHIFT (19U) #define S50_ELS_KS7_KS7_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECDH_SHIFT)) & S50_ELS_KS7_KS7_UECDH_MASK) #define S50_ELS_KS7_KS7_UAES_MASK (0x100000U) #define S50_ELS_KS7_KS7_UAES_SHIFT (20U) #define S50_ELS_KS7_KS7_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UAES_SHIFT)) & S50_ELS_KS7_KS7_UAES_MASK) #define S50_ELS_KS7_KS7_UHMAC_MASK (0x200000U) #define S50_ELS_KS7_KS7_UHMAC_SHIFT (21U) #define S50_ELS_KS7_KS7_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHMAC_SHIFT)) & S50_ELS_KS7_KS7_UHMAC_MASK) #define S50_ELS_KS7_KS7_UKWK_MASK (0x400000U) #define S50_ELS_KS7_KS7_UKWK_SHIFT (22U) #define S50_ELS_KS7_KS7_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKWK_SHIFT)) & S50_ELS_KS7_KS7_UKWK_MASK) #define S50_ELS_KS7_KS7_UKUOK_MASK (0x800000U) #define S50_ELS_KS7_KS7_UKUOK_SHIFT (23U) #define S50_ELS_KS7_KS7_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKUOK_SHIFT)) & S50_ELS_KS7_KS7_UKUOK_MASK) #define S50_ELS_KS7_KS7_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS7_KS7_UTLSPMS_SHIFT (24U) #define S50_ELS_KS7_KS7_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSPMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSPMS_MASK) #define S50_ELS_KS7_KS7_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS7_KS7_UTLSMS_SHIFT (25U) #define S50_ELS_KS7_KS7_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSMS_MASK) #define S50_ELS_KS7_KS7_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS7_KS7_UKGSRC_SHIFT (26U) #define S50_ELS_KS7_KS7_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKGSRC_SHIFT)) & S50_ELS_KS7_KS7_UKGSRC_MASK) #define S50_ELS_KS7_KS7_UHWO_MASK (0x8000000U) #define S50_ELS_KS7_KS7_UHWO_SHIFT (27U) #define S50_ELS_KS7_KS7_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHWO_SHIFT)) & S50_ELS_KS7_KS7_UHWO_MASK) #define S50_ELS_KS7_KS7_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS7_KS7_UWRPOK_SHIFT (28U) #define S50_ELS_KS7_KS7_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UWRPOK_SHIFT)) & S50_ELS_KS7_KS7_UWRPOK_MASK) #define S50_ELS_KS7_KS7_UDUK_MASK (0x20000000U) #define S50_ELS_KS7_KS7_UDUK_SHIFT (29U) #define S50_ELS_KS7_KS7_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UDUK_SHIFT)) & S50_ELS_KS7_KS7_UDUK_MASK) #define S50_ELS_KS7_KS7_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS7_KS7_UPPROT_SHIFT (30U) #define S50_ELS_KS7_KS7_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UPPROT_SHIFT)) & S50_ELS_KS7_KS7_UPPROT_MASK) /*! @} */ /*! @name ELS_KS8 - Status Register */ /*! @{ */ #define S50_ELS_KS8_KS8_KSIZE_MASK (0x3U) #define S50_ELS_KS8_KS8_KSIZE_SHIFT (0U) /*! KS8_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS8_KS8_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KSIZE_SHIFT)) & S50_ELS_KS8_KS8_KSIZE_MASK) #define S50_ELS_KS8_KS8_KACT_MASK (0x20U) #define S50_ELS_KS8_KS8_KACT_SHIFT (5U) #define S50_ELS_KS8_KS8_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KACT_SHIFT)) & S50_ELS_KS8_KS8_KACT_MASK) #define S50_ELS_KS8_KS8_KBASE_MASK (0x40U) #define S50_ELS_KS8_KS8_KBASE_SHIFT (6U) #define S50_ELS_KS8_KS8_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KBASE_SHIFT)) & S50_ELS_KS8_KS8_KBASE_MASK) #define S50_ELS_KS8_KS8_FGP_MASK (0x80U) #define S50_ELS_KS8_KS8_FGP_SHIFT (7U) #define S50_ELS_KS8_KS8_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FGP_SHIFT)) & S50_ELS_KS8_KS8_FGP_MASK) #define S50_ELS_KS8_KS8_FRTN_MASK (0x100U) #define S50_ELS_KS8_KS8_FRTN_SHIFT (8U) #define S50_ELS_KS8_KS8_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FRTN_SHIFT)) & S50_ELS_KS8_KS8_FRTN_MASK) #define S50_ELS_KS8_KS8_FHWO_MASK (0x200U) #define S50_ELS_KS8_KS8_FHWO_SHIFT (9U) #define S50_ELS_KS8_KS8_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FHWO_SHIFT)) & S50_ELS_KS8_KS8_FHWO_MASK) #define S50_ELS_KS8_KS8_UKPUK_MASK (0x800U) #define S50_ELS_KS8_KS8_UKPUK_SHIFT (11U) #define S50_ELS_KS8_KS8_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKPUK_SHIFT)) & S50_ELS_KS8_KS8_UKPUK_MASK) #define S50_ELS_KS8_KS8_UTECDH_MASK (0x1000U) #define S50_ELS_KS8_KS8_UTECDH_SHIFT (12U) #define S50_ELS_KS8_KS8_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTECDH_SHIFT)) & S50_ELS_KS8_KS8_UTECDH_MASK) #define S50_ELS_KS8_KS8_UCMAC_MASK (0x2000U) #define S50_ELS_KS8_KS8_UCMAC_SHIFT (13U) #define S50_ELS_KS8_KS8_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCMAC_SHIFT)) & S50_ELS_KS8_KS8_UCMAC_MASK) #define S50_ELS_KS8_KS8_UKSK_MASK (0x4000U) #define S50_ELS_KS8_KS8_UKSK_SHIFT (14U) #define S50_ELS_KS8_KS8_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKSK_SHIFT)) & S50_ELS_KS8_KS8_UKSK_MASK) #define S50_ELS_KS8_KS8_URTF_MASK (0x8000U) #define S50_ELS_KS8_KS8_URTF_SHIFT (15U) #define S50_ELS_KS8_KS8_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_URTF_SHIFT)) & S50_ELS_KS8_KS8_URTF_MASK) #define S50_ELS_KS8_KS8_UCKDF_MASK (0x10000U) #define S50_ELS_KS8_KS8_UCKDF_SHIFT (16U) #define S50_ELS_KS8_KS8_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCKDF_SHIFT)) & S50_ELS_KS8_KS8_UCKDF_MASK) #define S50_ELS_KS8_KS8_UHKDF_MASK (0x20000U) #define S50_ELS_KS8_KS8_UHKDF_SHIFT (17U) #define S50_ELS_KS8_KS8_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHKDF_SHIFT)) & S50_ELS_KS8_KS8_UHKDF_MASK) #define S50_ELS_KS8_KS8_UECSG_MASK (0x40000U) #define S50_ELS_KS8_KS8_UECSG_SHIFT (18U) #define S50_ELS_KS8_KS8_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECSG_SHIFT)) & S50_ELS_KS8_KS8_UECSG_MASK) #define S50_ELS_KS8_KS8_UECDH_MASK (0x80000U) #define S50_ELS_KS8_KS8_UECDH_SHIFT (19U) #define S50_ELS_KS8_KS8_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECDH_SHIFT)) & S50_ELS_KS8_KS8_UECDH_MASK) #define S50_ELS_KS8_KS8_UAES_MASK (0x100000U) #define S50_ELS_KS8_KS8_UAES_SHIFT (20U) #define S50_ELS_KS8_KS8_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UAES_SHIFT)) & S50_ELS_KS8_KS8_UAES_MASK) #define S50_ELS_KS8_KS8_UHMAC_MASK (0x200000U) #define S50_ELS_KS8_KS8_UHMAC_SHIFT (21U) #define S50_ELS_KS8_KS8_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHMAC_SHIFT)) & S50_ELS_KS8_KS8_UHMAC_MASK) #define S50_ELS_KS8_KS8_UKWK_MASK (0x400000U) #define S50_ELS_KS8_KS8_UKWK_SHIFT (22U) #define S50_ELS_KS8_KS8_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKWK_SHIFT)) & S50_ELS_KS8_KS8_UKWK_MASK) #define S50_ELS_KS8_KS8_UKUOK_MASK (0x800000U) #define S50_ELS_KS8_KS8_UKUOK_SHIFT (23U) #define S50_ELS_KS8_KS8_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKUOK_SHIFT)) & S50_ELS_KS8_KS8_UKUOK_MASK) #define S50_ELS_KS8_KS8_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS8_KS8_UTLSPMS_SHIFT (24U) #define S50_ELS_KS8_KS8_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSPMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSPMS_MASK) #define S50_ELS_KS8_KS8_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS8_KS8_UTLSMS_SHIFT (25U) #define S50_ELS_KS8_KS8_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSMS_MASK) #define S50_ELS_KS8_KS8_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS8_KS8_UKGSRC_SHIFT (26U) #define S50_ELS_KS8_KS8_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKGSRC_SHIFT)) & S50_ELS_KS8_KS8_UKGSRC_MASK) #define S50_ELS_KS8_KS8_UHWO_MASK (0x8000000U) #define S50_ELS_KS8_KS8_UHWO_SHIFT (27U) #define S50_ELS_KS8_KS8_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHWO_SHIFT)) & S50_ELS_KS8_KS8_UHWO_MASK) #define S50_ELS_KS8_KS8_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS8_KS8_UWRPOK_SHIFT (28U) #define S50_ELS_KS8_KS8_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UWRPOK_SHIFT)) & S50_ELS_KS8_KS8_UWRPOK_MASK) #define S50_ELS_KS8_KS8_UDUK_MASK (0x20000000U) #define S50_ELS_KS8_KS8_UDUK_SHIFT (29U) #define S50_ELS_KS8_KS8_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UDUK_SHIFT)) & S50_ELS_KS8_KS8_UDUK_MASK) #define S50_ELS_KS8_KS8_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS8_KS8_UPPROT_SHIFT (30U) #define S50_ELS_KS8_KS8_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UPPROT_SHIFT)) & S50_ELS_KS8_KS8_UPPROT_MASK) /*! @} */ /*! @name ELS_KS9 - Status Register */ /*! @{ */ #define S50_ELS_KS9_KS9_KSIZE_MASK (0x3U) #define S50_ELS_KS9_KS9_KSIZE_SHIFT (0U) /*! KS9_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS9_KS9_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KSIZE_SHIFT)) & S50_ELS_KS9_KS9_KSIZE_MASK) #define S50_ELS_KS9_KS9_KACT_MASK (0x20U) #define S50_ELS_KS9_KS9_KACT_SHIFT (5U) #define S50_ELS_KS9_KS9_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KACT_SHIFT)) & S50_ELS_KS9_KS9_KACT_MASK) #define S50_ELS_KS9_KS9_KBASE_MASK (0x40U) #define S50_ELS_KS9_KS9_KBASE_SHIFT (6U) #define S50_ELS_KS9_KS9_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KBASE_SHIFT)) & S50_ELS_KS9_KS9_KBASE_MASK) #define S50_ELS_KS9_KS9_FGP_MASK (0x80U) #define S50_ELS_KS9_KS9_FGP_SHIFT (7U) #define S50_ELS_KS9_KS9_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FGP_SHIFT)) & S50_ELS_KS9_KS9_FGP_MASK) #define S50_ELS_KS9_KS9_FRTN_MASK (0x100U) #define S50_ELS_KS9_KS9_FRTN_SHIFT (8U) #define S50_ELS_KS9_KS9_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FRTN_SHIFT)) & S50_ELS_KS9_KS9_FRTN_MASK) #define S50_ELS_KS9_KS9_FHWO_MASK (0x200U) #define S50_ELS_KS9_KS9_FHWO_SHIFT (9U) #define S50_ELS_KS9_KS9_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FHWO_SHIFT)) & S50_ELS_KS9_KS9_FHWO_MASK) #define S50_ELS_KS9_KS9_UKPUK_MASK (0x800U) #define S50_ELS_KS9_KS9_UKPUK_SHIFT (11U) #define S50_ELS_KS9_KS9_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKPUK_SHIFT)) & S50_ELS_KS9_KS9_UKPUK_MASK) #define S50_ELS_KS9_KS9_UTECDH_MASK (0x1000U) #define S50_ELS_KS9_KS9_UTECDH_SHIFT (12U) #define S50_ELS_KS9_KS9_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTECDH_SHIFT)) & S50_ELS_KS9_KS9_UTECDH_MASK) #define S50_ELS_KS9_KS9_UCMAC_MASK (0x2000U) #define S50_ELS_KS9_KS9_UCMAC_SHIFT (13U) #define S50_ELS_KS9_KS9_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCMAC_SHIFT)) & S50_ELS_KS9_KS9_UCMAC_MASK) #define S50_ELS_KS9_KS9_UKSK_MASK (0x4000U) #define S50_ELS_KS9_KS9_UKSK_SHIFT (14U) #define S50_ELS_KS9_KS9_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKSK_SHIFT)) & S50_ELS_KS9_KS9_UKSK_MASK) #define S50_ELS_KS9_KS9_URTF_MASK (0x8000U) #define S50_ELS_KS9_KS9_URTF_SHIFT (15U) #define S50_ELS_KS9_KS9_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_URTF_SHIFT)) & S50_ELS_KS9_KS9_URTF_MASK) #define S50_ELS_KS9_KS9_UCKDF_MASK (0x10000U) #define S50_ELS_KS9_KS9_UCKDF_SHIFT (16U) #define S50_ELS_KS9_KS9_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCKDF_SHIFT)) & S50_ELS_KS9_KS9_UCKDF_MASK) #define S50_ELS_KS9_KS9_UHKDF_MASK (0x20000U) #define S50_ELS_KS9_KS9_UHKDF_SHIFT (17U) #define S50_ELS_KS9_KS9_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHKDF_SHIFT)) & S50_ELS_KS9_KS9_UHKDF_MASK) #define S50_ELS_KS9_KS9_UECSG_MASK (0x40000U) #define S50_ELS_KS9_KS9_UECSG_SHIFT (18U) #define S50_ELS_KS9_KS9_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECSG_SHIFT)) & S50_ELS_KS9_KS9_UECSG_MASK) #define S50_ELS_KS9_KS9_UECDH_MASK (0x80000U) #define S50_ELS_KS9_KS9_UECDH_SHIFT (19U) #define S50_ELS_KS9_KS9_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECDH_SHIFT)) & S50_ELS_KS9_KS9_UECDH_MASK) #define S50_ELS_KS9_KS9_UAES_MASK (0x100000U) #define S50_ELS_KS9_KS9_UAES_SHIFT (20U) #define S50_ELS_KS9_KS9_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UAES_SHIFT)) & S50_ELS_KS9_KS9_UAES_MASK) #define S50_ELS_KS9_KS9_UHMAC_MASK (0x200000U) #define S50_ELS_KS9_KS9_UHMAC_SHIFT (21U) #define S50_ELS_KS9_KS9_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHMAC_SHIFT)) & S50_ELS_KS9_KS9_UHMAC_MASK) #define S50_ELS_KS9_KS9_UKWK_MASK (0x400000U) #define S50_ELS_KS9_KS9_UKWK_SHIFT (22U) #define S50_ELS_KS9_KS9_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKWK_SHIFT)) & S50_ELS_KS9_KS9_UKWK_MASK) #define S50_ELS_KS9_KS9_UKUOK_MASK (0x800000U) #define S50_ELS_KS9_KS9_UKUOK_SHIFT (23U) #define S50_ELS_KS9_KS9_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKUOK_SHIFT)) & S50_ELS_KS9_KS9_UKUOK_MASK) #define S50_ELS_KS9_KS9_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS9_KS9_UTLSPMS_SHIFT (24U) #define S50_ELS_KS9_KS9_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSPMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSPMS_MASK) #define S50_ELS_KS9_KS9_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS9_KS9_UTLSMS_SHIFT (25U) #define S50_ELS_KS9_KS9_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSMS_MASK) #define S50_ELS_KS9_KS9_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS9_KS9_UKGSRC_SHIFT (26U) #define S50_ELS_KS9_KS9_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKGSRC_SHIFT)) & S50_ELS_KS9_KS9_UKGSRC_MASK) #define S50_ELS_KS9_KS9_UHWO_MASK (0x8000000U) #define S50_ELS_KS9_KS9_UHWO_SHIFT (27U) #define S50_ELS_KS9_KS9_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHWO_SHIFT)) & S50_ELS_KS9_KS9_UHWO_MASK) #define S50_ELS_KS9_KS9_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS9_KS9_UWRPOK_SHIFT (28U) #define S50_ELS_KS9_KS9_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UWRPOK_SHIFT)) & S50_ELS_KS9_KS9_UWRPOK_MASK) #define S50_ELS_KS9_KS9_UDUK_MASK (0x20000000U) #define S50_ELS_KS9_KS9_UDUK_SHIFT (29U) #define S50_ELS_KS9_KS9_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UDUK_SHIFT)) & S50_ELS_KS9_KS9_UDUK_MASK) #define S50_ELS_KS9_KS9_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS9_KS9_UPPROT_SHIFT (30U) #define S50_ELS_KS9_KS9_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UPPROT_SHIFT)) & S50_ELS_KS9_KS9_UPPROT_MASK) /*! @} */ /*! @name ELS_KS10 - Status Register */ /*! @{ */ #define S50_ELS_KS10_KS10_KSIZE_MASK (0x3U) #define S50_ELS_KS10_KS10_KSIZE_SHIFT (0U) /*! KS10_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS10_KS10_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KSIZE_SHIFT)) & S50_ELS_KS10_KS10_KSIZE_MASK) #define S50_ELS_KS10_KS10_KACT_MASK (0x20U) #define S50_ELS_KS10_KS10_KACT_SHIFT (5U) #define S50_ELS_KS10_KS10_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KACT_SHIFT)) & S50_ELS_KS10_KS10_KACT_MASK) #define S50_ELS_KS10_KS10_KBASE_MASK (0x40U) #define S50_ELS_KS10_KS10_KBASE_SHIFT (6U) #define S50_ELS_KS10_KS10_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KBASE_SHIFT)) & S50_ELS_KS10_KS10_KBASE_MASK) #define S50_ELS_KS10_KS10_FGP_MASK (0x80U) #define S50_ELS_KS10_KS10_FGP_SHIFT (7U) #define S50_ELS_KS10_KS10_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FGP_SHIFT)) & S50_ELS_KS10_KS10_FGP_MASK) #define S50_ELS_KS10_KS10_FRTN_MASK (0x100U) #define S50_ELS_KS10_KS10_FRTN_SHIFT (8U) #define S50_ELS_KS10_KS10_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FRTN_SHIFT)) & S50_ELS_KS10_KS10_FRTN_MASK) #define S50_ELS_KS10_KS10_FHWO_MASK (0x200U) #define S50_ELS_KS10_KS10_FHWO_SHIFT (9U) #define S50_ELS_KS10_KS10_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FHWO_SHIFT)) & S50_ELS_KS10_KS10_FHWO_MASK) #define S50_ELS_KS10_KS10_UKPUK_MASK (0x800U) #define S50_ELS_KS10_KS10_UKPUK_SHIFT (11U) #define S50_ELS_KS10_KS10_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKPUK_SHIFT)) & S50_ELS_KS10_KS10_UKPUK_MASK) #define S50_ELS_KS10_KS10_UTECDH_MASK (0x1000U) #define S50_ELS_KS10_KS10_UTECDH_SHIFT (12U) #define S50_ELS_KS10_KS10_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTECDH_SHIFT)) & S50_ELS_KS10_KS10_UTECDH_MASK) #define S50_ELS_KS10_KS10_UCMAC_MASK (0x2000U) #define S50_ELS_KS10_KS10_UCMAC_SHIFT (13U) #define S50_ELS_KS10_KS10_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCMAC_SHIFT)) & S50_ELS_KS10_KS10_UCMAC_MASK) #define S50_ELS_KS10_KS10_UKSK_MASK (0x4000U) #define S50_ELS_KS10_KS10_UKSK_SHIFT (14U) #define S50_ELS_KS10_KS10_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKSK_SHIFT)) & S50_ELS_KS10_KS10_UKSK_MASK) #define S50_ELS_KS10_KS10_URTF_MASK (0x8000U) #define S50_ELS_KS10_KS10_URTF_SHIFT (15U) #define S50_ELS_KS10_KS10_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_URTF_SHIFT)) & S50_ELS_KS10_KS10_URTF_MASK) #define S50_ELS_KS10_KS10_UCKDF_MASK (0x10000U) #define S50_ELS_KS10_KS10_UCKDF_SHIFT (16U) #define S50_ELS_KS10_KS10_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCKDF_SHIFT)) & S50_ELS_KS10_KS10_UCKDF_MASK) #define S50_ELS_KS10_KS10_UHKDF_MASK (0x20000U) #define S50_ELS_KS10_KS10_UHKDF_SHIFT (17U) #define S50_ELS_KS10_KS10_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHKDF_SHIFT)) & S50_ELS_KS10_KS10_UHKDF_MASK) #define S50_ELS_KS10_KS10_UECSG_MASK (0x40000U) #define S50_ELS_KS10_KS10_UECSG_SHIFT (18U) #define S50_ELS_KS10_KS10_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECSG_SHIFT)) & S50_ELS_KS10_KS10_UECSG_MASK) #define S50_ELS_KS10_KS10_UECDH_MASK (0x80000U) #define S50_ELS_KS10_KS10_UECDH_SHIFT (19U) #define S50_ELS_KS10_KS10_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECDH_SHIFT)) & S50_ELS_KS10_KS10_UECDH_MASK) #define S50_ELS_KS10_KS10_UAES_MASK (0x100000U) #define S50_ELS_KS10_KS10_UAES_SHIFT (20U) #define S50_ELS_KS10_KS10_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UAES_SHIFT)) & S50_ELS_KS10_KS10_UAES_MASK) #define S50_ELS_KS10_KS10_UHMAC_MASK (0x200000U) #define S50_ELS_KS10_KS10_UHMAC_SHIFT (21U) #define S50_ELS_KS10_KS10_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHMAC_SHIFT)) & S50_ELS_KS10_KS10_UHMAC_MASK) #define S50_ELS_KS10_KS10_UKWK_MASK (0x400000U) #define S50_ELS_KS10_KS10_UKWK_SHIFT (22U) #define S50_ELS_KS10_KS10_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKWK_SHIFT)) & S50_ELS_KS10_KS10_UKWK_MASK) #define S50_ELS_KS10_KS10_UKUOK_MASK (0x800000U) #define S50_ELS_KS10_KS10_UKUOK_SHIFT (23U) #define S50_ELS_KS10_KS10_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKUOK_SHIFT)) & S50_ELS_KS10_KS10_UKUOK_MASK) #define S50_ELS_KS10_KS10_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS10_KS10_UTLSPMS_SHIFT (24U) #define S50_ELS_KS10_KS10_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSPMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSPMS_MASK) #define S50_ELS_KS10_KS10_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS10_KS10_UTLSMS_SHIFT (25U) #define S50_ELS_KS10_KS10_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSMS_MASK) #define S50_ELS_KS10_KS10_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS10_KS10_UKGSRC_SHIFT (26U) #define S50_ELS_KS10_KS10_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKGSRC_SHIFT)) & S50_ELS_KS10_KS10_UKGSRC_MASK) #define S50_ELS_KS10_KS10_UHWO_MASK (0x8000000U) #define S50_ELS_KS10_KS10_UHWO_SHIFT (27U) #define S50_ELS_KS10_KS10_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHWO_SHIFT)) & S50_ELS_KS10_KS10_UHWO_MASK) #define S50_ELS_KS10_KS10_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS10_KS10_UWRPOK_SHIFT (28U) #define S50_ELS_KS10_KS10_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UWRPOK_SHIFT)) & S50_ELS_KS10_KS10_UWRPOK_MASK) #define S50_ELS_KS10_KS10_UDUK_MASK (0x20000000U) #define S50_ELS_KS10_KS10_UDUK_SHIFT (29U) #define S50_ELS_KS10_KS10_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UDUK_SHIFT)) & S50_ELS_KS10_KS10_UDUK_MASK) #define S50_ELS_KS10_KS10_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS10_KS10_UPPROT_SHIFT (30U) #define S50_ELS_KS10_KS10_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UPPROT_SHIFT)) & S50_ELS_KS10_KS10_UPPROT_MASK) /*! @} */ /*! @name ELS_KS11 - Status Register */ /*! @{ */ #define S50_ELS_KS11_KS11_KSIZE_MASK (0x3U) #define S50_ELS_KS11_KS11_KSIZE_SHIFT (0U) /*! KS11_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS11_KS11_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KSIZE_SHIFT)) & S50_ELS_KS11_KS11_KSIZE_MASK) #define S50_ELS_KS11_KS11_KACT_MASK (0x20U) #define S50_ELS_KS11_KS11_KACT_SHIFT (5U) #define S50_ELS_KS11_KS11_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KACT_SHIFT)) & S50_ELS_KS11_KS11_KACT_MASK) #define S50_ELS_KS11_KS11_KBASE_MASK (0x40U) #define S50_ELS_KS11_KS11_KBASE_SHIFT (6U) #define S50_ELS_KS11_KS11_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KBASE_SHIFT)) & S50_ELS_KS11_KS11_KBASE_MASK) #define S50_ELS_KS11_KS11_FGP_MASK (0x80U) #define S50_ELS_KS11_KS11_FGP_SHIFT (7U) #define S50_ELS_KS11_KS11_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FGP_SHIFT)) & S50_ELS_KS11_KS11_FGP_MASK) #define S50_ELS_KS11_KS11_FRTN_MASK (0x100U) #define S50_ELS_KS11_KS11_FRTN_SHIFT (8U) #define S50_ELS_KS11_KS11_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FRTN_SHIFT)) & S50_ELS_KS11_KS11_FRTN_MASK) #define S50_ELS_KS11_KS11_FHWO_MASK (0x200U) #define S50_ELS_KS11_KS11_FHWO_SHIFT (9U) #define S50_ELS_KS11_KS11_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FHWO_SHIFT)) & S50_ELS_KS11_KS11_FHWO_MASK) #define S50_ELS_KS11_KS11_UKPUK_MASK (0x800U) #define S50_ELS_KS11_KS11_UKPUK_SHIFT (11U) #define S50_ELS_KS11_KS11_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKPUK_SHIFT)) & S50_ELS_KS11_KS11_UKPUK_MASK) #define S50_ELS_KS11_KS11_UTECDH_MASK (0x1000U) #define S50_ELS_KS11_KS11_UTECDH_SHIFT (12U) #define S50_ELS_KS11_KS11_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTECDH_SHIFT)) & S50_ELS_KS11_KS11_UTECDH_MASK) #define S50_ELS_KS11_KS11_UCMAC_MASK (0x2000U) #define S50_ELS_KS11_KS11_UCMAC_SHIFT (13U) #define S50_ELS_KS11_KS11_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCMAC_SHIFT)) & S50_ELS_KS11_KS11_UCMAC_MASK) #define S50_ELS_KS11_KS11_UKSK_MASK (0x4000U) #define S50_ELS_KS11_KS11_UKSK_SHIFT (14U) #define S50_ELS_KS11_KS11_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKSK_SHIFT)) & S50_ELS_KS11_KS11_UKSK_MASK) #define S50_ELS_KS11_KS11_URTF_MASK (0x8000U) #define S50_ELS_KS11_KS11_URTF_SHIFT (15U) #define S50_ELS_KS11_KS11_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_URTF_SHIFT)) & S50_ELS_KS11_KS11_URTF_MASK) #define S50_ELS_KS11_KS11_UCKDF_MASK (0x10000U) #define S50_ELS_KS11_KS11_UCKDF_SHIFT (16U) #define S50_ELS_KS11_KS11_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCKDF_SHIFT)) & S50_ELS_KS11_KS11_UCKDF_MASK) #define S50_ELS_KS11_KS11_UHKDF_MASK (0x20000U) #define S50_ELS_KS11_KS11_UHKDF_SHIFT (17U) #define S50_ELS_KS11_KS11_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHKDF_SHIFT)) & S50_ELS_KS11_KS11_UHKDF_MASK) #define S50_ELS_KS11_KS11_UECSG_MASK (0x40000U) #define S50_ELS_KS11_KS11_UECSG_SHIFT (18U) #define S50_ELS_KS11_KS11_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECSG_SHIFT)) & S50_ELS_KS11_KS11_UECSG_MASK) #define S50_ELS_KS11_KS11_UECDH_MASK (0x80000U) #define S50_ELS_KS11_KS11_UECDH_SHIFT (19U) #define S50_ELS_KS11_KS11_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECDH_SHIFT)) & S50_ELS_KS11_KS11_UECDH_MASK) #define S50_ELS_KS11_KS11_UAES_MASK (0x100000U) #define S50_ELS_KS11_KS11_UAES_SHIFT (20U) #define S50_ELS_KS11_KS11_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UAES_SHIFT)) & S50_ELS_KS11_KS11_UAES_MASK) #define S50_ELS_KS11_KS11_UHMAC_MASK (0x200000U) #define S50_ELS_KS11_KS11_UHMAC_SHIFT (21U) #define S50_ELS_KS11_KS11_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHMAC_SHIFT)) & S50_ELS_KS11_KS11_UHMAC_MASK) #define S50_ELS_KS11_KS11_UKWK_MASK (0x400000U) #define S50_ELS_KS11_KS11_UKWK_SHIFT (22U) #define S50_ELS_KS11_KS11_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKWK_SHIFT)) & S50_ELS_KS11_KS11_UKWK_MASK) #define S50_ELS_KS11_KS11_UKUOK_MASK (0x800000U) #define S50_ELS_KS11_KS11_UKUOK_SHIFT (23U) #define S50_ELS_KS11_KS11_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKUOK_SHIFT)) & S50_ELS_KS11_KS11_UKUOK_MASK) #define S50_ELS_KS11_KS11_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS11_KS11_UTLSPMS_SHIFT (24U) #define S50_ELS_KS11_KS11_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSPMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSPMS_MASK) #define S50_ELS_KS11_KS11_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS11_KS11_UTLSMS_SHIFT (25U) #define S50_ELS_KS11_KS11_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSMS_MASK) #define S50_ELS_KS11_KS11_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS11_KS11_UKGSRC_SHIFT (26U) #define S50_ELS_KS11_KS11_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKGSRC_SHIFT)) & S50_ELS_KS11_KS11_UKGSRC_MASK) #define S50_ELS_KS11_KS11_UHWO_MASK (0x8000000U) #define S50_ELS_KS11_KS11_UHWO_SHIFT (27U) #define S50_ELS_KS11_KS11_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHWO_SHIFT)) & S50_ELS_KS11_KS11_UHWO_MASK) #define S50_ELS_KS11_KS11_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS11_KS11_UWRPOK_SHIFT (28U) #define S50_ELS_KS11_KS11_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UWRPOK_SHIFT)) & S50_ELS_KS11_KS11_UWRPOK_MASK) #define S50_ELS_KS11_KS11_UDUK_MASK (0x20000000U) #define S50_ELS_KS11_KS11_UDUK_SHIFT (29U) #define S50_ELS_KS11_KS11_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UDUK_SHIFT)) & S50_ELS_KS11_KS11_UDUK_MASK) #define S50_ELS_KS11_KS11_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS11_KS11_UPPROT_SHIFT (30U) #define S50_ELS_KS11_KS11_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UPPROT_SHIFT)) & S50_ELS_KS11_KS11_UPPROT_MASK) /*! @} */ /*! @name ELS_KS12 - Status Register */ /*! @{ */ #define S50_ELS_KS12_KS12_KSIZE_MASK (0x3U) #define S50_ELS_KS12_KS12_KSIZE_SHIFT (0U) /*! KS12_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS12_KS12_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KSIZE_SHIFT)) & S50_ELS_KS12_KS12_KSIZE_MASK) #define S50_ELS_KS12_KS12_KACT_MASK (0x20U) #define S50_ELS_KS12_KS12_KACT_SHIFT (5U) #define S50_ELS_KS12_KS12_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KACT_SHIFT)) & S50_ELS_KS12_KS12_KACT_MASK) #define S50_ELS_KS12_KS12_KBASE_MASK (0x40U) #define S50_ELS_KS12_KS12_KBASE_SHIFT (6U) #define S50_ELS_KS12_KS12_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KBASE_SHIFT)) & S50_ELS_KS12_KS12_KBASE_MASK) #define S50_ELS_KS12_KS12_FGP_MASK (0x80U) #define S50_ELS_KS12_KS12_FGP_SHIFT (7U) #define S50_ELS_KS12_KS12_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FGP_SHIFT)) & S50_ELS_KS12_KS12_FGP_MASK) #define S50_ELS_KS12_KS12_FRTN_MASK (0x100U) #define S50_ELS_KS12_KS12_FRTN_SHIFT (8U) #define S50_ELS_KS12_KS12_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FRTN_SHIFT)) & S50_ELS_KS12_KS12_FRTN_MASK) #define S50_ELS_KS12_KS12_FHWO_MASK (0x200U) #define S50_ELS_KS12_KS12_FHWO_SHIFT (9U) #define S50_ELS_KS12_KS12_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FHWO_SHIFT)) & S50_ELS_KS12_KS12_FHWO_MASK) #define S50_ELS_KS12_KS12_UKPUK_MASK (0x800U) #define S50_ELS_KS12_KS12_UKPUK_SHIFT (11U) #define S50_ELS_KS12_KS12_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKPUK_SHIFT)) & S50_ELS_KS12_KS12_UKPUK_MASK) #define S50_ELS_KS12_KS12_UTECDH_MASK (0x1000U) #define S50_ELS_KS12_KS12_UTECDH_SHIFT (12U) #define S50_ELS_KS12_KS12_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTECDH_SHIFT)) & S50_ELS_KS12_KS12_UTECDH_MASK) #define S50_ELS_KS12_KS12_UCMAC_MASK (0x2000U) #define S50_ELS_KS12_KS12_UCMAC_SHIFT (13U) #define S50_ELS_KS12_KS12_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCMAC_SHIFT)) & S50_ELS_KS12_KS12_UCMAC_MASK) #define S50_ELS_KS12_KS12_UKSK_MASK (0x4000U) #define S50_ELS_KS12_KS12_UKSK_SHIFT (14U) #define S50_ELS_KS12_KS12_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKSK_SHIFT)) & S50_ELS_KS12_KS12_UKSK_MASK) #define S50_ELS_KS12_KS12_URTF_MASK (0x8000U) #define S50_ELS_KS12_KS12_URTF_SHIFT (15U) #define S50_ELS_KS12_KS12_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_URTF_SHIFT)) & S50_ELS_KS12_KS12_URTF_MASK) #define S50_ELS_KS12_KS12_UCKDF_MASK (0x10000U) #define S50_ELS_KS12_KS12_UCKDF_SHIFT (16U) #define S50_ELS_KS12_KS12_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCKDF_SHIFT)) & S50_ELS_KS12_KS12_UCKDF_MASK) #define S50_ELS_KS12_KS12_UHKDF_MASK (0x20000U) #define S50_ELS_KS12_KS12_UHKDF_SHIFT (17U) #define S50_ELS_KS12_KS12_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHKDF_SHIFT)) & S50_ELS_KS12_KS12_UHKDF_MASK) #define S50_ELS_KS12_KS12_UECSG_MASK (0x40000U) #define S50_ELS_KS12_KS12_UECSG_SHIFT (18U) #define S50_ELS_KS12_KS12_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECSG_SHIFT)) & S50_ELS_KS12_KS12_UECSG_MASK) #define S50_ELS_KS12_KS12_UECDH_MASK (0x80000U) #define S50_ELS_KS12_KS12_UECDH_SHIFT (19U) #define S50_ELS_KS12_KS12_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECDH_SHIFT)) & S50_ELS_KS12_KS12_UECDH_MASK) #define S50_ELS_KS12_KS12_UAES_MASK (0x100000U) #define S50_ELS_KS12_KS12_UAES_SHIFT (20U) #define S50_ELS_KS12_KS12_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UAES_SHIFT)) & S50_ELS_KS12_KS12_UAES_MASK) #define S50_ELS_KS12_KS12_UHMAC_MASK (0x200000U) #define S50_ELS_KS12_KS12_UHMAC_SHIFT (21U) #define S50_ELS_KS12_KS12_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHMAC_SHIFT)) & S50_ELS_KS12_KS12_UHMAC_MASK) #define S50_ELS_KS12_KS12_UKWK_MASK (0x400000U) #define S50_ELS_KS12_KS12_UKWK_SHIFT (22U) #define S50_ELS_KS12_KS12_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKWK_SHIFT)) & S50_ELS_KS12_KS12_UKWK_MASK) #define S50_ELS_KS12_KS12_UKUOK_MASK (0x800000U) #define S50_ELS_KS12_KS12_UKUOK_SHIFT (23U) #define S50_ELS_KS12_KS12_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKUOK_SHIFT)) & S50_ELS_KS12_KS12_UKUOK_MASK) #define S50_ELS_KS12_KS12_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS12_KS12_UTLSPMS_SHIFT (24U) #define S50_ELS_KS12_KS12_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSPMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSPMS_MASK) #define S50_ELS_KS12_KS12_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS12_KS12_UTLSMS_SHIFT (25U) #define S50_ELS_KS12_KS12_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSMS_MASK) #define S50_ELS_KS12_KS12_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS12_KS12_UKGSRC_SHIFT (26U) #define S50_ELS_KS12_KS12_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKGSRC_SHIFT)) & S50_ELS_KS12_KS12_UKGSRC_MASK) #define S50_ELS_KS12_KS12_UHWO_MASK (0x8000000U) #define S50_ELS_KS12_KS12_UHWO_SHIFT (27U) #define S50_ELS_KS12_KS12_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHWO_SHIFT)) & S50_ELS_KS12_KS12_UHWO_MASK) #define S50_ELS_KS12_KS12_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS12_KS12_UWRPOK_SHIFT (28U) #define S50_ELS_KS12_KS12_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UWRPOK_SHIFT)) & S50_ELS_KS12_KS12_UWRPOK_MASK) #define S50_ELS_KS12_KS12_UDUK_MASK (0x20000000U) #define S50_ELS_KS12_KS12_UDUK_SHIFT (29U) #define S50_ELS_KS12_KS12_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UDUK_SHIFT)) & S50_ELS_KS12_KS12_UDUK_MASK) #define S50_ELS_KS12_KS12_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS12_KS12_UPPROT_SHIFT (30U) #define S50_ELS_KS12_KS12_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UPPROT_SHIFT)) & S50_ELS_KS12_KS12_UPPROT_MASK) /*! @} */ /*! @name ELS_KS13 - Status Register */ /*! @{ */ #define S50_ELS_KS13_KS13_KSIZE_MASK (0x3U) #define S50_ELS_KS13_KS13_KSIZE_SHIFT (0U) /*! KS13_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS13_KS13_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KSIZE_SHIFT)) & S50_ELS_KS13_KS13_KSIZE_MASK) #define S50_ELS_KS13_KS13_KACT_MASK (0x20U) #define S50_ELS_KS13_KS13_KACT_SHIFT (5U) #define S50_ELS_KS13_KS13_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KACT_SHIFT)) & S50_ELS_KS13_KS13_KACT_MASK) #define S50_ELS_KS13_KS13_KBASE_MASK (0x40U) #define S50_ELS_KS13_KS13_KBASE_SHIFT (6U) #define S50_ELS_KS13_KS13_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KBASE_SHIFT)) & S50_ELS_KS13_KS13_KBASE_MASK) #define S50_ELS_KS13_KS13_FGP_MASK (0x80U) #define S50_ELS_KS13_KS13_FGP_SHIFT (7U) #define S50_ELS_KS13_KS13_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FGP_SHIFT)) & S50_ELS_KS13_KS13_FGP_MASK) #define S50_ELS_KS13_KS13_FRTN_MASK (0x100U) #define S50_ELS_KS13_KS13_FRTN_SHIFT (8U) #define S50_ELS_KS13_KS13_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FRTN_SHIFT)) & S50_ELS_KS13_KS13_FRTN_MASK) #define S50_ELS_KS13_KS13_FHWO_MASK (0x200U) #define S50_ELS_KS13_KS13_FHWO_SHIFT (9U) #define S50_ELS_KS13_KS13_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FHWO_SHIFT)) & S50_ELS_KS13_KS13_FHWO_MASK) #define S50_ELS_KS13_KS13_UKPUK_MASK (0x800U) #define S50_ELS_KS13_KS13_UKPUK_SHIFT (11U) #define S50_ELS_KS13_KS13_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKPUK_SHIFT)) & S50_ELS_KS13_KS13_UKPUK_MASK) #define S50_ELS_KS13_KS13_UTECDH_MASK (0x1000U) #define S50_ELS_KS13_KS13_UTECDH_SHIFT (12U) #define S50_ELS_KS13_KS13_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTECDH_SHIFT)) & S50_ELS_KS13_KS13_UTECDH_MASK) #define S50_ELS_KS13_KS13_UCMAC_MASK (0x2000U) #define S50_ELS_KS13_KS13_UCMAC_SHIFT (13U) #define S50_ELS_KS13_KS13_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCMAC_SHIFT)) & S50_ELS_KS13_KS13_UCMAC_MASK) #define S50_ELS_KS13_KS13_UKSK_MASK (0x4000U) #define S50_ELS_KS13_KS13_UKSK_SHIFT (14U) #define S50_ELS_KS13_KS13_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKSK_SHIFT)) & S50_ELS_KS13_KS13_UKSK_MASK) #define S50_ELS_KS13_KS13_URTF_MASK (0x8000U) #define S50_ELS_KS13_KS13_URTF_SHIFT (15U) #define S50_ELS_KS13_KS13_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_URTF_SHIFT)) & S50_ELS_KS13_KS13_URTF_MASK) #define S50_ELS_KS13_KS13_UCKDF_MASK (0x10000U) #define S50_ELS_KS13_KS13_UCKDF_SHIFT (16U) #define S50_ELS_KS13_KS13_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCKDF_SHIFT)) & S50_ELS_KS13_KS13_UCKDF_MASK) #define S50_ELS_KS13_KS13_UHKDF_MASK (0x20000U) #define S50_ELS_KS13_KS13_UHKDF_SHIFT (17U) #define S50_ELS_KS13_KS13_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHKDF_SHIFT)) & S50_ELS_KS13_KS13_UHKDF_MASK) #define S50_ELS_KS13_KS13_UECSG_MASK (0x40000U) #define S50_ELS_KS13_KS13_UECSG_SHIFT (18U) #define S50_ELS_KS13_KS13_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECSG_SHIFT)) & S50_ELS_KS13_KS13_UECSG_MASK) #define S50_ELS_KS13_KS13_UECDH_MASK (0x80000U) #define S50_ELS_KS13_KS13_UECDH_SHIFT (19U) #define S50_ELS_KS13_KS13_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECDH_SHIFT)) & S50_ELS_KS13_KS13_UECDH_MASK) #define S50_ELS_KS13_KS13_UAES_MASK (0x100000U) #define S50_ELS_KS13_KS13_UAES_SHIFT (20U) #define S50_ELS_KS13_KS13_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UAES_SHIFT)) & S50_ELS_KS13_KS13_UAES_MASK) #define S50_ELS_KS13_KS13_UHMAC_MASK (0x200000U) #define S50_ELS_KS13_KS13_UHMAC_SHIFT (21U) #define S50_ELS_KS13_KS13_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHMAC_SHIFT)) & S50_ELS_KS13_KS13_UHMAC_MASK) #define S50_ELS_KS13_KS13_UKWK_MASK (0x400000U) #define S50_ELS_KS13_KS13_UKWK_SHIFT (22U) #define S50_ELS_KS13_KS13_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKWK_SHIFT)) & S50_ELS_KS13_KS13_UKWK_MASK) #define S50_ELS_KS13_KS13_UKUOK_MASK (0x800000U) #define S50_ELS_KS13_KS13_UKUOK_SHIFT (23U) #define S50_ELS_KS13_KS13_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKUOK_SHIFT)) & S50_ELS_KS13_KS13_UKUOK_MASK) #define S50_ELS_KS13_KS13_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS13_KS13_UTLSPMS_SHIFT (24U) #define S50_ELS_KS13_KS13_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSPMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSPMS_MASK) #define S50_ELS_KS13_KS13_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS13_KS13_UTLSMS_SHIFT (25U) #define S50_ELS_KS13_KS13_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSMS_MASK) #define S50_ELS_KS13_KS13_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS13_KS13_UKGSRC_SHIFT (26U) #define S50_ELS_KS13_KS13_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKGSRC_SHIFT)) & S50_ELS_KS13_KS13_UKGSRC_MASK) #define S50_ELS_KS13_KS13_UHWO_MASK (0x8000000U) #define S50_ELS_KS13_KS13_UHWO_SHIFT (27U) #define S50_ELS_KS13_KS13_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHWO_SHIFT)) & S50_ELS_KS13_KS13_UHWO_MASK) #define S50_ELS_KS13_KS13_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS13_KS13_UWRPOK_SHIFT (28U) #define S50_ELS_KS13_KS13_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UWRPOK_SHIFT)) & S50_ELS_KS13_KS13_UWRPOK_MASK) #define S50_ELS_KS13_KS13_UDUK_MASK (0x20000000U) #define S50_ELS_KS13_KS13_UDUK_SHIFT (29U) #define S50_ELS_KS13_KS13_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UDUK_SHIFT)) & S50_ELS_KS13_KS13_UDUK_MASK) #define S50_ELS_KS13_KS13_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS13_KS13_UPPROT_SHIFT (30U) #define S50_ELS_KS13_KS13_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UPPROT_SHIFT)) & S50_ELS_KS13_KS13_UPPROT_MASK) /*! @} */ /*! @name ELS_KS14 - Status Register */ /*! @{ */ #define S50_ELS_KS14_KS14_KSIZE_MASK (0x3U) #define S50_ELS_KS14_KS14_KSIZE_SHIFT (0U) /*! KS14_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS14_KS14_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KSIZE_SHIFT)) & S50_ELS_KS14_KS14_KSIZE_MASK) #define S50_ELS_KS14_KS14_KACT_MASK (0x20U) #define S50_ELS_KS14_KS14_KACT_SHIFT (5U) #define S50_ELS_KS14_KS14_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KACT_SHIFT)) & S50_ELS_KS14_KS14_KACT_MASK) #define S50_ELS_KS14_KS14_KBASE_MASK (0x40U) #define S50_ELS_KS14_KS14_KBASE_SHIFT (6U) #define S50_ELS_KS14_KS14_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KBASE_SHIFT)) & S50_ELS_KS14_KS14_KBASE_MASK) #define S50_ELS_KS14_KS14_FGP_MASK (0x80U) #define S50_ELS_KS14_KS14_FGP_SHIFT (7U) #define S50_ELS_KS14_KS14_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FGP_SHIFT)) & S50_ELS_KS14_KS14_FGP_MASK) #define S50_ELS_KS14_KS14_FRTN_MASK (0x100U) #define S50_ELS_KS14_KS14_FRTN_SHIFT (8U) #define S50_ELS_KS14_KS14_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FRTN_SHIFT)) & S50_ELS_KS14_KS14_FRTN_MASK) #define S50_ELS_KS14_KS14_FHWO_MASK (0x200U) #define S50_ELS_KS14_KS14_FHWO_SHIFT (9U) #define S50_ELS_KS14_KS14_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FHWO_SHIFT)) & S50_ELS_KS14_KS14_FHWO_MASK) #define S50_ELS_KS14_KS14_UKPUK_MASK (0x800U) #define S50_ELS_KS14_KS14_UKPUK_SHIFT (11U) #define S50_ELS_KS14_KS14_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKPUK_SHIFT)) & S50_ELS_KS14_KS14_UKPUK_MASK) #define S50_ELS_KS14_KS14_UTECDH_MASK (0x1000U) #define S50_ELS_KS14_KS14_UTECDH_SHIFT (12U) #define S50_ELS_KS14_KS14_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTECDH_SHIFT)) & S50_ELS_KS14_KS14_UTECDH_MASK) #define S50_ELS_KS14_KS14_UCMAC_MASK (0x2000U) #define S50_ELS_KS14_KS14_UCMAC_SHIFT (13U) #define S50_ELS_KS14_KS14_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCMAC_SHIFT)) & S50_ELS_KS14_KS14_UCMAC_MASK) #define S50_ELS_KS14_KS14_UKSK_MASK (0x4000U) #define S50_ELS_KS14_KS14_UKSK_SHIFT (14U) #define S50_ELS_KS14_KS14_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKSK_SHIFT)) & S50_ELS_KS14_KS14_UKSK_MASK) #define S50_ELS_KS14_KS14_URTF_MASK (0x8000U) #define S50_ELS_KS14_KS14_URTF_SHIFT (15U) #define S50_ELS_KS14_KS14_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_URTF_SHIFT)) & S50_ELS_KS14_KS14_URTF_MASK) #define S50_ELS_KS14_KS14_UCKDF_MASK (0x10000U) #define S50_ELS_KS14_KS14_UCKDF_SHIFT (16U) #define S50_ELS_KS14_KS14_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCKDF_SHIFT)) & S50_ELS_KS14_KS14_UCKDF_MASK) #define S50_ELS_KS14_KS14_UHKDF_MASK (0x20000U) #define S50_ELS_KS14_KS14_UHKDF_SHIFT (17U) #define S50_ELS_KS14_KS14_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHKDF_SHIFT)) & S50_ELS_KS14_KS14_UHKDF_MASK) #define S50_ELS_KS14_KS14_UECSG_MASK (0x40000U) #define S50_ELS_KS14_KS14_UECSG_SHIFT (18U) #define S50_ELS_KS14_KS14_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECSG_SHIFT)) & S50_ELS_KS14_KS14_UECSG_MASK) #define S50_ELS_KS14_KS14_UECDH_MASK (0x80000U) #define S50_ELS_KS14_KS14_UECDH_SHIFT (19U) #define S50_ELS_KS14_KS14_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECDH_SHIFT)) & S50_ELS_KS14_KS14_UECDH_MASK) #define S50_ELS_KS14_KS14_UAES_MASK (0x100000U) #define S50_ELS_KS14_KS14_UAES_SHIFT (20U) #define S50_ELS_KS14_KS14_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UAES_SHIFT)) & S50_ELS_KS14_KS14_UAES_MASK) #define S50_ELS_KS14_KS14_UHMAC_MASK (0x200000U) #define S50_ELS_KS14_KS14_UHMAC_SHIFT (21U) #define S50_ELS_KS14_KS14_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHMAC_SHIFT)) & S50_ELS_KS14_KS14_UHMAC_MASK) #define S50_ELS_KS14_KS14_UKWK_MASK (0x400000U) #define S50_ELS_KS14_KS14_UKWK_SHIFT (22U) #define S50_ELS_KS14_KS14_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKWK_SHIFT)) & S50_ELS_KS14_KS14_UKWK_MASK) #define S50_ELS_KS14_KS14_UKUOK_MASK (0x800000U) #define S50_ELS_KS14_KS14_UKUOK_SHIFT (23U) #define S50_ELS_KS14_KS14_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKUOK_SHIFT)) & S50_ELS_KS14_KS14_UKUOK_MASK) #define S50_ELS_KS14_KS14_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS14_KS14_UTLSPMS_SHIFT (24U) #define S50_ELS_KS14_KS14_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSPMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSPMS_MASK) #define S50_ELS_KS14_KS14_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS14_KS14_UTLSMS_SHIFT (25U) #define S50_ELS_KS14_KS14_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSMS_MASK) #define S50_ELS_KS14_KS14_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS14_KS14_UKGSRC_SHIFT (26U) #define S50_ELS_KS14_KS14_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKGSRC_SHIFT)) & S50_ELS_KS14_KS14_UKGSRC_MASK) #define S50_ELS_KS14_KS14_UHWO_MASK (0x8000000U) #define S50_ELS_KS14_KS14_UHWO_SHIFT (27U) #define S50_ELS_KS14_KS14_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHWO_SHIFT)) & S50_ELS_KS14_KS14_UHWO_MASK) #define S50_ELS_KS14_KS14_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS14_KS14_UWRPOK_SHIFT (28U) #define S50_ELS_KS14_KS14_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UWRPOK_SHIFT)) & S50_ELS_KS14_KS14_UWRPOK_MASK) #define S50_ELS_KS14_KS14_UDUK_MASK (0x20000000U) #define S50_ELS_KS14_KS14_UDUK_SHIFT (29U) #define S50_ELS_KS14_KS14_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UDUK_SHIFT)) & S50_ELS_KS14_KS14_UDUK_MASK) #define S50_ELS_KS14_KS14_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS14_KS14_UPPROT_SHIFT (30U) #define S50_ELS_KS14_KS14_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UPPROT_SHIFT)) & S50_ELS_KS14_KS14_UPPROT_MASK) /*! @} */ /*! @name ELS_KS15 - Status Register */ /*! @{ */ #define S50_ELS_KS15_KS15_KSIZE_MASK (0x3U) #define S50_ELS_KS15_KS15_KSIZE_SHIFT (0U) /*! KS15_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS15_KS15_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KSIZE_SHIFT)) & S50_ELS_KS15_KS15_KSIZE_MASK) #define S50_ELS_KS15_KS15_KACT_MASK (0x20U) #define S50_ELS_KS15_KS15_KACT_SHIFT (5U) #define S50_ELS_KS15_KS15_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KACT_SHIFT)) & S50_ELS_KS15_KS15_KACT_MASK) #define S50_ELS_KS15_KS15_KBASE_MASK (0x40U) #define S50_ELS_KS15_KS15_KBASE_SHIFT (6U) #define S50_ELS_KS15_KS15_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KBASE_SHIFT)) & S50_ELS_KS15_KS15_KBASE_MASK) #define S50_ELS_KS15_KS15_FGP_MASK (0x80U) #define S50_ELS_KS15_KS15_FGP_SHIFT (7U) #define S50_ELS_KS15_KS15_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FGP_SHIFT)) & S50_ELS_KS15_KS15_FGP_MASK) #define S50_ELS_KS15_KS15_FRTN_MASK (0x100U) #define S50_ELS_KS15_KS15_FRTN_SHIFT (8U) #define S50_ELS_KS15_KS15_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FRTN_SHIFT)) & S50_ELS_KS15_KS15_FRTN_MASK) #define S50_ELS_KS15_KS15_FHWO_MASK (0x200U) #define S50_ELS_KS15_KS15_FHWO_SHIFT (9U) #define S50_ELS_KS15_KS15_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FHWO_SHIFT)) & S50_ELS_KS15_KS15_FHWO_MASK) #define S50_ELS_KS15_KS15_UKPUK_MASK (0x800U) #define S50_ELS_KS15_KS15_UKPUK_SHIFT (11U) #define S50_ELS_KS15_KS15_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKPUK_SHIFT)) & S50_ELS_KS15_KS15_UKPUK_MASK) #define S50_ELS_KS15_KS15_UTECDH_MASK (0x1000U) #define S50_ELS_KS15_KS15_UTECDH_SHIFT (12U) #define S50_ELS_KS15_KS15_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTECDH_SHIFT)) & S50_ELS_KS15_KS15_UTECDH_MASK) #define S50_ELS_KS15_KS15_UCMAC_MASK (0x2000U) #define S50_ELS_KS15_KS15_UCMAC_SHIFT (13U) #define S50_ELS_KS15_KS15_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCMAC_SHIFT)) & S50_ELS_KS15_KS15_UCMAC_MASK) #define S50_ELS_KS15_KS15_UKSK_MASK (0x4000U) #define S50_ELS_KS15_KS15_UKSK_SHIFT (14U) #define S50_ELS_KS15_KS15_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKSK_SHIFT)) & S50_ELS_KS15_KS15_UKSK_MASK) #define S50_ELS_KS15_KS15_URTF_MASK (0x8000U) #define S50_ELS_KS15_KS15_URTF_SHIFT (15U) #define S50_ELS_KS15_KS15_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_URTF_SHIFT)) & S50_ELS_KS15_KS15_URTF_MASK) #define S50_ELS_KS15_KS15_UCKDF_MASK (0x10000U) #define S50_ELS_KS15_KS15_UCKDF_SHIFT (16U) #define S50_ELS_KS15_KS15_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCKDF_SHIFT)) & S50_ELS_KS15_KS15_UCKDF_MASK) #define S50_ELS_KS15_KS15_UHKDF_MASK (0x20000U) #define S50_ELS_KS15_KS15_UHKDF_SHIFT (17U) #define S50_ELS_KS15_KS15_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHKDF_SHIFT)) & S50_ELS_KS15_KS15_UHKDF_MASK) #define S50_ELS_KS15_KS15_UECSG_MASK (0x40000U) #define S50_ELS_KS15_KS15_UECSG_SHIFT (18U) #define S50_ELS_KS15_KS15_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECSG_SHIFT)) & S50_ELS_KS15_KS15_UECSG_MASK) #define S50_ELS_KS15_KS15_UECDH_MASK (0x80000U) #define S50_ELS_KS15_KS15_UECDH_SHIFT (19U) #define S50_ELS_KS15_KS15_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECDH_SHIFT)) & S50_ELS_KS15_KS15_UECDH_MASK) #define S50_ELS_KS15_KS15_UAES_MASK (0x100000U) #define S50_ELS_KS15_KS15_UAES_SHIFT (20U) #define S50_ELS_KS15_KS15_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UAES_SHIFT)) & S50_ELS_KS15_KS15_UAES_MASK) #define S50_ELS_KS15_KS15_UHMAC_MASK (0x200000U) #define S50_ELS_KS15_KS15_UHMAC_SHIFT (21U) #define S50_ELS_KS15_KS15_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHMAC_SHIFT)) & S50_ELS_KS15_KS15_UHMAC_MASK) #define S50_ELS_KS15_KS15_UKWK_MASK (0x400000U) #define S50_ELS_KS15_KS15_UKWK_SHIFT (22U) #define S50_ELS_KS15_KS15_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKWK_SHIFT)) & S50_ELS_KS15_KS15_UKWK_MASK) #define S50_ELS_KS15_KS15_UKUOK_MASK (0x800000U) #define S50_ELS_KS15_KS15_UKUOK_SHIFT (23U) #define S50_ELS_KS15_KS15_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKUOK_SHIFT)) & S50_ELS_KS15_KS15_UKUOK_MASK) #define S50_ELS_KS15_KS15_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS15_KS15_UTLSPMS_SHIFT (24U) #define S50_ELS_KS15_KS15_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSPMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSPMS_MASK) #define S50_ELS_KS15_KS15_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS15_KS15_UTLSMS_SHIFT (25U) #define S50_ELS_KS15_KS15_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSMS_MASK) #define S50_ELS_KS15_KS15_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS15_KS15_UKGSRC_SHIFT (26U) #define S50_ELS_KS15_KS15_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKGSRC_SHIFT)) & S50_ELS_KS15_KS15_UKGSRC_MASK) #define S50_ELS_KS15_KS15_UHWO_MASK (0x8000000U) #define S50_ELS_KS15_KS15_UHWO_SHIFT (27U) #define S50_ELS_KS15_KS15_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHWO_SHIFT)) & S50_ELS_KS15_KS15_UHWO_MASK) #define S50_ELS_KS15_KS15_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS15_KS15_UWRPOK_SHIFT (28U) #define S50_ELS_KS15_KS15_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UWRPOK_SHIFT)) & S50_ELS_KS15_KS15_UWRPOK_MASK) #define S50_ELS_KS15_KS15_UDUK_MASK (0x20000000U) #define S50_ELS_KS15_KS15_UDUK_SHIFT (29U) #define S50_ELS_KS15_KS15_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UDUK_SHIFT)) & S50_ELS_KS15_KS15_UDUK_MASK) #define S50_ELS_KS15_KS15_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS15_KS15_UPPROT_SHIFT (30U) #define S50_ELS_KS15_KS15_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UPPROT_SHIFT)) & S50_ELS_KS15_KS15_UPPROT_MASK) /*! @} */ /*! @name ELS_KS16 - Status Register */ /*! @{ */ #define S50_ELS_KS16_KS16_KSIZE_MASK (0x3U) #define S50_ELS_KS16_KS16_KSIZE_SHIFT (0U) /*! KS16_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS16_KS16_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KSIZE_SHIFT)) & S50_ELS_KS16_KS16_KSIZE_MASK) #define S50_ELS_KS16_KS16_KACT_MASK (0x20U) #define S50_ELS_KS16_KS16_KACT_SHIFT (5U) #define S50_ELS_KS16_KS16_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KACT_SHIFT)) & S50_ELS_KS16_KS16_KACT_MASK) #define S50_ELS_KS16_KS16_KBASE_MASK (0x40U) #define S50_ELS_KS16_KS16_KBASE_SHIFT (6U) #define S50_ELS_KS16_KS16_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KBASE_SHIFT)) & S50_ELS_KS16_KS16_KBASE_MASK) #define S50_ELS_KS16_KS16_FGP_MASK (0x80U) #define S50_ELS_KS16_KS16_FGP_SHIFT (7U) #define S50_ELS_KS16_KS16_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FGP_SHIFT)) & S50_ELS_KS16_KS16_FGP_MASK) #define S50_ELS_KS16_KS16_FRTN_MASK (0x100U) #define S50_ELS_KS16_KS16_FRTN_SHIFT (8U) #define S50_ELS_KS16_KS16_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FRTN_SHIFT)) & S50_ELS_KS16_KS16_FRTN_MASK) #define S50_ELS_KS16_KS16_FHWO_MASK (0x200U) #define S50_ELS_KS16_KS16_FHWO_SHIFT (9U) #define S50_ELS_KS16_KS16_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FHWO_SHIFT)) & S50_ELS_KS16_KS16_FHWO_MASK) #define S50_ELS_KS16_KS16_UKPUK_MASK (0x800U) #define S50_ELS_KS16_KS16_UKPUK_SHIFT (11U) #define S50_ELS_KS16_KS16_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKPUK_SHIFT)) & S50_ELS_KS16_KS16_UKPUK_MASK) #define S50_ELS_KS16_KS16_UTECDH_MASK (0x1000U) #define S50_ELS_KS16_KS16_UTECDH_SHIFT (12U) #define S50_ELS_KS16_KS16_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTECDH_SHIFT)) & S50_ELS_KS16_KS16_UTECDH_MASK) #define S50_ELS_KS16_KS16_UCMAC_MASK (0x2000U) #define S50_ELS_KS16_KS16_UCMAC_SHIFT (13U) #define S50_ELS_KS16_KS16_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCMAC_SHIFT)) & S50_ELS_KS16_KS16_UCMAC_MASK) #define S50_ELS_KS16_KS16_UKSK_MASK (0x4000U) #define S50_ELS_KS16_KS16_UKSK_SHIFT (14U) #define S50_ELS_KS16_KS16_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKSK_SHIFT)) & S50_ELS_KS16_KS16_UKSK_MASK) #define S50_ELS_KS16_KS16_URTF_MASK (0x8000U) #define S50_ELS_KS16_KS16_URTF_SHIFT (15U) #define S50_ELS_KS16_KS16_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_URTF_SHIFT)) & S50_ELS_KS16_KS16_URTF_MASK) #define S50_ELS_KS16_KS16_UCKDF_MASK (0x10000U) #define S50_ELS_KS16_KS16_UCKDF_SHIFT (16U) #define S50_ELS_KS16_KS16_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCKDF_SHIFT)) & S50_ELS_KS16_KS16_UCKDF_MASK) #define S50_ELS_KS16_KS16_UHKDF_MASK (0x20000U) #define S50_ELS_KS16_KS16_UHKDF_SHIFT (17U) #define S50_ELS_KS16_KS16_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHKDF_SHIFT)) & S50_ELS_KS16_KS16_UHKDF_MASK) #define S50_ELS_KS16_KS16_UECSG_MASK (0x40000U) #define S50_ELS_KS16_KS16_UECSG_SHIFT (18U) #define S50_ELS_KS16_KS16_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECSG_SHIFT)) & S50_ELS_KS16_KS16_UECSG_MASK) #define S50_ELS_KS16_KS16_UECDH_MASK (0x80000U) #define S50_ELS_KS16_KS16_UECDH_SHIFT (19U) #define S50_ELS_KS16_KS16_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECDH_SHIFT)) & S50_ELS_KS16_KS16_UECDH_MASK) #define S50_ELS_KS16_KS16_UAES_MASK (0x100000U) #define S50_ELS_KS16_KS16_UAES_SHIFT (20U) #define S50_ELS_KS16_KS16_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UAES_SHIFT)) & S50_ELS_KS16_KS16_UAES_MASK) #define S50_ELS_KS16_KS16_UHMAC_MASK (0x200000U) #define S50_ELS_KS16_KS16_UHMAC_SHIFT (21U) #define S50_ELS_KS16_KS16_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHMAC_SHIFT)) & S50_ELS_KS16_KS16_UHMAC_MASK) #define S50_ELS_KS16_KS16_UKWK_MASK (0x400000U) #define S50_ELS_KS16_KS16_UKWK_SHIFT (22U) #define S50_ELS_KS16_KS16_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKWK_SHIFT)) & S50_ELS_KS16_KS16_UKWK_MASK) #define S50_ELS_KS16_KS16_UKUOK_MASK (0x800000U) #define S50_ELS_KS16_KS16_UKUOK_SHIFT (23U) #define S50_ELS_KS16_KS16_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKUOK_SHIFT)) & S50_ELS_KS16_KS16_UKUOK_MASK) #define S50_ELS_KS16_KS16_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS16_KS16_UTLSPMS_SHIFT (24U) #define S50_ELS_KS16_KS16_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSPMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSPMS_MASK) #define S50_ELS_KS16_KS16_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS16_KS16_UTLSMS_SHIFT (25U) #define S50_ELS_KS16_KS16_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSMS_MASK) #define S50_ELS_KS16_KS16_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS16_KS16_UKGSRC_SHIFT (26U) #define S50_ELS_KS16_KS16_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKGSRC_SHIFT)) & S50_ELS_KS16_KS16_UKGSRC_MASK) #define S50_ELS_KS16_KS16_UHWO_MASK (0x8000000U) #define S50_ELS_KS16_KS16_UHWO_SHIFT (27U) #define S50_ELS_KS16_KS16_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHWO_SHIFT)) & S50_ELS_KS16_KS16_UHWO_MASK) #define S50_ELS_KS16_KS16_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS16_KS16_UWRPOK_SHIFT (28U) #define S50_ELS_KS16_KS16_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UWRPOK_SHIFT)) & S50_ELS_KS16_KS16_UWRPOK_MASK) #define S50_ELS_KS16_KS16_UDUK_MASK (0x20000000U) #define S50_ELS_KS16_KS16_UDUK_SHIFT (29U) #define S50_ELS_KS16_KS16_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UDUK_SHIFT)) & S50_ELS_KS16_KS16_UDUK_MASK) #define S50_ELS_KS16_KS16_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS16_KS16_UPPROT_SHIFT (30U) #define S50_ELS_KS16_KS16_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UPPROT_SHIFT)) & S50_ELS_KS16_KS16_UPPROT_MASK) /*! @} */ /*! @name ELS_KS17 - Status Register */ /*! @{ */ #define S50_ELS_KS17_KS17_KSIZE_MASK (0x3U) #define S50_ELS_KS17_KS17_KSIZE_SHIFT (0U) /*! KS17_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS17_KS17_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KSIZE_SHIFT)) & S50_ELS_KS17_KS17_KSIZE_MASK) #define S50_ELS_KS17_KS17_KACT_MASK (0x20U) #define S50_ELS_KS17_KS17_KACT_SHIFT (5U) #define S50_ELS_KS17_KS17_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KACT_SHIFT)) & S50_ELS_KS17_KS17_KACT_MASK) #define S50_ELS_KS17_KS17_KBASE_MASK (0x40U) #define S50_ELS_KS17_KS17_KBASE_SHIFT (6U) #define S50_ELS_KS17_KS17_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KBASE_SHIFT)) & S50_ELS_KS17_KS17_KBASE_MASK) #define S50_ELS_KS17_KS17_FGP_MASK (0x80U) #define S50_ELS_KS17_KS17_FGP_SHIFT (7U) #define S50_ELS_KS17_KS17_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FGP_SHIFT)) & S50_ELS_KS17_KS17_FGP_MASK) #define S50_ELS_KS17_KS17_FRTN_MASK (0x100U) #define S50_ELS_KS17_KS17_FRTN_SHIFT (8U) #define S50_ELS_KS17_KS17_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FRTN_SHIFT)) & S50_ELS_KS17_KS17_FRTN_MASK) #define S50_ELS_KS17_KS17_FHWO_MASK (0x200U) #define S50_ELS_KS17_KS17_FHWO_SHIFT (9U) #define S50_ELS_KS17_KS17_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FHWO_SHIFT)) & S50_ELS_KS17_KS17_FHWO_MASK) #define S50_ELS_KS17_KS17_UKPUK_MASK (0x800U) #define S50_ELS_KS17_KS17_UKPUK_SHIFT (11U) #define S50_ELS_KS17_KS17_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKPUK_SHIFT)) & S50_ELS_KS17_KS17_UKPUK_MASK) #define S50_ELS_KS17_KS17_UTECDH_MASK (0x1000U) #define S50_ELS_KS17_KS17_UTECDH_SHIFT (12U) #define S50_ELS_KS17_KS17_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTECDH_SHIFT)) & S50_ELS_KS17_KS17_UTECDH_MASK) #define S50_ELS_KS17_KS17_UCMAC_MASK (0x2000U) #define S50_ELS_KS17_KS17_UCMAC_SHIFT (13U) #define S50_ELS_KS17_KS17_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCMAC_SHIFT)) & S50_ELS_KS17_KS17_UCMAC_MASK) #define S50_ELS_KS17_KS17_UKSK_MASK (0x4000U) #define S50_ELS_KS17_KS17_UKSK_SHIFT (14U) #define S50_ELS_KS17_KS17_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKSK_SHIFT)) & S50_ELS_KS17_KS17_UKSK_MASK) #define S50_ELS_KS17_KS17_URTF_MASK (0x8000U) #define S50_ELS_KS17_KS17_URTF_SHIFT (15U) #define S50_ELS_KS17_KS17_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_URTF_SHIFT)) & S50_ELS_KS17_KS17_URTF_MASK) #define S50_ELS_KS17_KS17_UCKDF_MASK (0x10000U) #define S50_ELS_KS17_KS17_UCKDF_SHIFT (16U) #define S50_ELS_KS17_KS17_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCKDF_SHIFT)) & S50_ELS_KS17_KS17_UCKDF_MASK) #define S50_ELS_KS17_KS17_UHKDF_MASK (0x20000U) #define S50_ELS_KS17_KS17_UHKDF_SHIFT (17U) #define S50_ELS_KS17_KS17_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHKDF_SHIFT)) & S50_ELS_KS17_KS17_UHKDF_MASK) #define S50_ELS_KS17_KS17_UECSG_MASK (0x40000U) #define S50_ELS_KS17_KS17_UECSG_SHIFT (18U) #define S50_ELS_KS17_KS17_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECSG_SHIFT)) & S50_ELS_KS17_KS17_UECSG_MASK) #define S50_ELS_KS17_KS17_UECDH_MASK (0x80000U) #define S50_ELS_KS17_KS17_UECDH_SHIFT (19U) #define S50_ELS_KS17_KS17_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECDH_SHIFT)) & S50_ELS_KS17_KS17_UECDH_MASK) #define S50_ELS_KS17_KS17_UAES_MASK (0x100000U) #define S50_ELS_KS17_KS17_UAES_SHIFT (20U) #define S50_ELS_KS17_KS17_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UAES_SHIFT)) & S50_ELS_KS17_KS17_UAES_MASK) #define S50_ELS_KS17_KS17_UHMAC_MASK (0x200000U) #define S50_ELS_KS17_KS17_UHMAC_SHIFT (21U) #define S50_ELS_KS17_KS17_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHMAC_SHIFT)) & S50_ELS_KS17_KS17_UHMAC_MASK) #define S50_ELS_KS17_KS17_UKWK_MASK (0x400000U) #define S50_ELS_KS17_KS17_UKWK_SHIFT (22U) #define S50_ELS_KS17_KS17_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKWK_SHIFT)) & S50_ELS_KS17_KS17_UKWK_MASK) #define S50_ELS_KS17_KS17_UKUOK_MASK (0x800000U) #define S50_ELS_KS17_KS17_UKUOK_SHIFT (23U) #define S50_ELS_KS17_KS17_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKUOK_SHIFT)) & S50_ELS_KS17_KS17_UKUOK_MASK) #define S50_ELS_KS17_KS17_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS17_KS17_UTLSPMS_SHIFT (24U) #define S50_ELS_KS17_KS17_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSPMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSPMS_MASK) #define S50_ELS_KS17_KS17_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS17_KS17_UTLSMS_SHIFT (25U) #define S50_ELS_KS17_KS17_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSMS_MASK) #define S50_ELS_KS17_KS17_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS17_KS17_UKGSRC_SHIFT (26U) #define S50_ELS_KS17_KS17_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKGSRC_SHIFT)) & S50_ELS_KS17_KS17_UKGSRC_MASK) #define S50_ELS_KS17_KS17_UHWO_MASK (0x8000000U) #define S50_ELS_KS17_KS17_UHWO_SHIFT (27U) #define S50_ELS_KS17_KS17_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHWO_SHIFT)) & S50_ELS_KS17_KS17_UHWO_MASK) #define S50_ELS_KS17_KS17_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS17_KS17_UWRPOK_SHIFT (28U) #define S50_ELS_KS17_KS17_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UWRPOK_SHIFT)) & S50_ELS_KS17_KS17_UWRPOK_MASK) #define S50_ELS_KS17_KS17_UDUK_MASK (0x20000000U) #define S50_ELS_KS17_KS17_UDUK_SHIFT (29U) #define S50_ELS_KS17_KS17_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UDUK_SHIFT)) & S50_ELS_KS17_KS17_UDUK_MASK) #define S50_ELS_KS17_KS17_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS17_KS17_UPPROT_SHIFT (30U) #define S50_ELS_KS17_KS17_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UPPROT_SHIFT)) & S50_ELS_KS17_KS17_UPPROT_MASK) /*! @} */ /*! @name ELS_KS18 - Status Register */ /*! @{ */ #define S50_ELS_KS18_KS18_KSIZE_MASK (0x3U) #define S50_ELS_KS18_KS18_KSIZE_SHIFT (0U) /*! KS18_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS18_KS18_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KSIZE_SHIFT)) & S50_ELS_KS18_KS18_KSIZE_MASK) #define S50_ELS_KS18_KS18_KACT_MASK (0x20U) #define S50_ELS_KS18_KS18_KACT_SHIFT (5U) #define S50_ELS_KS18_KS18_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KACT_SHIFT)) & S50_ELS_KS18_KS18_KACT_MASK) #define S50_ELS_KS18_KS18_KBASE_MASK (0x40U) #define S50_ELS_KS18_KS18_KBASE_SHIFT (6U) #define S50_ELS_KS18_KS18_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KBASE_SHIFT)) & S50_ELS_KS18_KS18_KBASE_MASK) #define S50_ELS_KS18_KS18_FGP_MASK (0x80U) #define S50_ELS_KS18_KS18_FGP_SHIFT (7U) #define S50_ELS_KS18_KS18_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FGP_SHIFT)) & S50_ELS_KS18_KS18_FGP_MASK) #define S50_ELS_KS18_KS18_FRTN_MASK (0x100U) #define S50_ELS_KS18_KS18_FRTN_SHIFT (8U) #define S50_ELS_KS18_KS18_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FRTN_SHIFT)) & S50_ELS_KS18_KS18_FRTN_MASK) #define S50_ELS_KS18_KS18_FHWO_MASK (0x200U) #define S50_ELS_KS18_KS18_FHWO_SHIFT (9U) #define S50_ELS_KS18_KS18_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FHWO_SHIFT)) & S50_ELS_KS18_KS18_FHWO_MASK) #define S50_ELS_KS18_KS18_UKPUK_MASK (0x800U) #define S50_ELS_KS18_KS18_UKPUK_SHIFT (11U) #define S50_ELS_KS18_KS18_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKPUK_SHIFT)) & S50_ELS_KS18_KS18_UKPUK_MASK) #define S50_ELS_KS18_KS18_UTECDH_MASK (0x1000U) #define S50_ELS_KS18_KS18_UTECDH_SHIFT (12U) #define S50_ELS_KS18_KS18_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTECDH_SHIFT)) & S50_ELS_KS18_KS18_UTECDH_MASK) #define S50_ELS_KS18_KS18_UCMAC_MASK (0x2000U) #define S50_ELS_KS18_KS18_UCMAC_SHIFT (13U) #define S50_ELS_KS18_KS18_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCMAC_SHIFT)) & S50_ELS_KS18_KS18_UCMAC_MASK) #define S50_ELS_KS18_KS18_UKSK_MASK (0x4000U) #define S50_ELS_KS18_KS18_UKSK_SHIFT (14U) #define S50_ELS_KS18_KS18_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKSK_SHIFT)) & S50_ELS_KS18_KS18_UKSK_MASK) #define S50_ELS_KS18_KS18_URTF_MASK (0x8000U) #define S50_ELS_KS18_KS18_URTF_SHIFT (15U) #define S50_ELS_KS18_KS18_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_URTF_SHIFT)) & S50_ELS_KS18_KS18_URTF_MASK) #define S50_ELS_KS18_KS18_UCKDF_MASK (0x10000U) #define S50_ELS_KS18_KS18_UCKDF_SHIFT (16U) #define S50_ELS_KS18_KS18_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCKDF_SHIFT)) & S50_ELS_KS18_KS18_UCKDF_MASK) #define S50_ELS_KS18_KS18_UHKDF_MASK (0x20000U) #define S50_ELS_KS18_KS18_UHKDF_SHIFT (17U) #define S50_ELS_KS18_KS18_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHKDF_SHIFT)) & S50_ELS_KS18_KS18_UHKDF_MASK) #define S50_ELS_KS18_KS18_UECSG_MASK (0x40000U) #define S50_ELS_KS18_KS18_UECSG_SHIFT (18U) #define S50_ELS_KS18_KS18_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECSG_SHIFT)) & S50_ELS_KS18_KS18_UECSG_MASK) #define S50_ELS_KS18_KS18_UECDH_MASK (0x80000U) #define S50_ELS_KS18_KS18_UECDH_SHIFT (19U) #define S50_ELS_KS18_KS18_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECDH_SHIFT)) & S50_ELS_KS18_KS18_UECDH_MASK) #define S50_ELS_KS18_KS18_UAES_MASK (0x100000U) #define S50_ELS_KS18_KS18_UAES_SHIFT (20U) #define S50_ELS_KS18_KS18_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UAES_SHIFT)) & S50_ELS_KS18_KS18_UAES_MASK) #define S50_ELS_KS18_KS18_UHMAC_MASK (0x200000U) #define S50_ELS_KS18_KS18_UHMAC_SHIFT (21U) #define S50_ELS_KS18_KS18_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHMAC_SHIFT)) & S50_ELS_KS18_KS18_UHMAC_MASK) #define S50_ELS_KS18_KS18_UKWK_MASK (0x400000U) #define S50_ELS_KS18_KS18_UKWK_SHIFT (22U) #define S50_ELS_KS18_KS18_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKWK_SHIFT)) & S50_ELS_KS18_KS18_UKWK_MASK) #define S50_ELS_KS18_KS18_UKUOK_MASK (0x800000U) #define S50_ELS_KS18_KS18_UKUOK_SHIFT (23U) #define S50_ELS_KS18_KS18_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKUOK_SHIFT)) & S50_ELS_KS18_KS18_UKUOK_MASK) #define S50_ELS_KS18_KS18_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS18_KS18_UTLSPMS_SHIFT (24U) #define S50_ELS_KS18_KS18_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSPMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSPMS_MASK) #define S50_ELS_KS18_KS18_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS18_KS18_UTLSMS_SHIFT (25U) #define S50_ELS_KS18_KS18_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSMS_MASK) #define S50_ELS_KS18_KS18_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS18_KS18_UKGSRC_SHIFT (26U) #define S50_ELS_KS18_KS18_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKGSRC_SHIFT)) & S50_ELS_KS18_KS18_UKGSRC_MASK) #define S50_ELS_KS18_KS18_UHWO_MASK (0x8000000U) #define S50_ELS_KS18_KS18_UHWO_SHIFT (27U) #define S50_ELS_KS18_KS18_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHWO_SHIFT)) & S50_ELS_KS18_KS18_UHWO_MASK) #define S50_ELS_KS18_KS18_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS18_KS18_UWRPOK_SHIFT (28U) #define S50_ELS_KS18_KS18_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UWRPOK_SHIFT)) & S50_ELS_KS18_KS18_UWRPOK_MASK) #define S50_ELS_KS18_KS18_UDUK_MASK (0x20000000U) #define S50_ELS_KS18_KS18_UDUK_SHIFT (29U) #define S50_ELS_KS18_KS18_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UDUK_SHIFT)) & S50_ELS_KS18_KS18_UDUK_MASK) #define S50_ELS_KS18_KS18_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS18_KS18_UPPROT_SHIFT (30U) #define S50_ELS_KS18_KS18_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UPPROT_SHIFT)) & S50_ELS_KS18_KS18_UPPROT_MASK) /*! @} */ /*! @name ELS_KS19 - Status Register */ /*! @{ */ #define S50_ELS_KS19_KS19_KSIZE_MASK (0x3U) #define S50_ELS_KS19_KS19_KSIZE_SHIFT (0U) /*! KS19_KSIZE * 0b00..128 * 0b01..256 */ #define S50_ELS_KS19_KS19_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KSIZE_SHIFT)) & S50_ELS_KS19_KS19_KSIZE_MASK) #define S50_ELS_KS19_KS19_KACT_MASK (0x20U) #define S50_ELS_KS19_KS19_KACT_SHIFT (5U) #define S50_ELS_KS19_KS19_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KACT_SHIFT)) & S50_ELS_KS19_KS19_KACT_MASK) #define S50_ELS_KS19_KS19_KBASE_MASK (0x40U) #define S50_ELS_KS19_KS19_KBASE_SHIFT (6U) #define S50_ELS_KS19_KS19_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KBASE_SHIFT)) & S50_ELS_KS19_KS19_KBASE_MASK) #define S50_ELS_KS19_KS19_FGP_MASK (0x80U) #define S50_ELS_KS19_KS19_FGP_SHIFT (7U) #define S50_ELS_KS19_KS19_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FGP_SHIFT)) & S50_ELS_KS19_KS19_FGP_MASK) #define S50_ELS_KS19_KS19_FRTN_MASK (0x100U) #define S50_ELS_KS19_KS19_FRTN_SHIFT (8U) #define S50_ELS_KS19_KS19_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FRTN_SHIFT)) & S50_ELS_KS19_KS19_FRTN_MASK) #define S50_ELS_KS19_KS19_FHWO_MASK (0x200U) #define S50_ELS_KS19_KS19_FHWO_SHIFT (9U) #define S50_ELS_KS19_KS19_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FHWO_SHIFT)) & S50_ELS_KS19_KS19_FHWO_MASK) #define S50_ELS_KS19_KS19_UKPUK_MASK (0x800U) #define S50_ELS_KS19_KS19_UKPUK_SHIFT (11U) #define S50_ELS_KS19_KS19_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKPUK_SHIFT)) & S50_ELS_KS19_KS19_UKPUK_MASK) #define S50_ELS_KS19_KS19_UTECDH_MASK (0x1000U) #define S50_ELS_KS19_KS19_UTECDH_SHIFT (12U) #define S50_ELS_KS19_KS19_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTECDH_SHIFT)) & S50_ELS_KS19_KS19_UTECDH_MASK) #define S50_ELS_KS19_KS19_UCMAC_MASK (0x2000U) #define S50_ELS_KS19_KS19_UCMAC_SHIFT (13U) #define S50_ELS_KS19_KS19_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCMAC_SHIFT)) & S50_ELS_KS19_KS19_UCMAC_MASK) #define S50_ELS_KS19_KS19_UKSK_MASK (0x4000U) #define S50_ELS_KS19_KS19_UKSK_SHIFT (14U) #define S50_ELS_KS19_KS19_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKSK_SHIFT)) & S50_ELS_KS19_KS19_UKSK_MASK) #define S50_ELS_KS19_KS19_URTF_MASK (0x8000U) #define S50_ELS_KS19_KS19_URTF_SHIFT (15U) #define S50_ELS_KS19_KS19_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_URTF_SHIFT)) & S50_ELS_KS19_KS19_URTF_MASK) #define S50_ELS_KS19_KS19_UCKDF_MASK (0x10000U) #define S50_ELS_KS19_KS19_UCKDF_SHIFT (16U) #define S50_ELS_KS19_KS19_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCKDF_SHIFT)) & S50_ELS_KS19_KS19_UCKDF_MASK) #define S50_ELS_KS19_KS19_UHKDF_MASK (0x20000U) #define S50_ELS_KS19_KS19_UHKDF_SHIFT (17U) #define S50_ELS_KS19_KS19_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHKDF_SHIFT)) & S50_ELS_KS19_KS19_UHKDF_MASK) #define S50_ELS_KS19_KS19_UECSG_MASK (0x40000U) #define S50_ELS_KS19_KS19_UECSG_SHIFT (18U) #define S50_ELS_KS19_KS19_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECSG_SHIFT)) & S50_ELS_KS19_KS19_UECSG_MASK) #define S50_ELS_KS19_KS19_UECDH_MASK (0x80000U) #define S50_ELS_KS19_KS19_UECDH_SHIFT (19U) #define S50_ELS_KS19_KS19_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECDH_SHIFT)) & S50_ELS_KS19_KS19_UECDH_MASK) #define S50_ELS_KS19_KS19_UAES_MASK (0x100000U) #define S50_ELS_KS19_KS19_UAES_SHIFT (20U) #define S50_ELS_KS19_KS19_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UAES_SHIFT)) & S50_ELS_KS19_KS19_UAES_MASK) #define S50_ELS_KS19_KS19_UHMAC_MASK (0x200000U) #define S50_ELS_KS19_KS19_UHMAC_SHIFT (21U) #define S50_ELS_KS19_KS19_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHMAC_SHIFT)) & S50_ELS_KS19_KS19_UHMAC_MASK) #define S50_ELS_KS19_KS19_UKWK_MASK (0x400000U) #define S50_ELS_KS19_KS19_UKWK_SHIFT (22U) #define S50_ELS_KS19_KS19_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKWK_SHIFT)) & S50_ELS_KS19_KS19_UKWK_MASK) #define S50_ELS_KS19_KS19_UKUOK_MASK (0x800000U) #define S50_ELS_KS19_KS19_UKUOK_SHIFT (23U) #define S50_ELS_KS19_KS19_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKUOK_SHIFT)) & S50_ELS_KS19_KS19_UKUOK_MASK) #define S50_ELS_KS19_KS19_UTLSPMS_MASK (0x1000000U) #define S50_ELS_KS19_KS19_UTLSPMS_SHIFT (24U) #define S50_ELS_KS19_KS19_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSPMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSPMS_MASK) #define S50_ELS_KS19_KS19_UTLSMS_MASK (0x2000000U) #define S50_ELS_KS19_KS19_UTLSMS_SHIFT (25U) #define S50_ELS_KS19_KS19_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSMS_MASK) #define S50_ELS_KS19_KS19_UKGSRC_MASK (0x4000000U) #define S50_ELS_KS19_KS19_UKGSRC_SHIFT (26U) #define S50_ELS_KS19_KS19_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKGSRC_SHIFT)) & S50_ELS_KS19_KS19_UKGSRC_MASK) #define S50_ELS_KS19_KS19_UHWO_MASK (0x8000000U) #define S50_ELS_KS19_KS19_UHWO_SHIFT (27U) #define S50_ELS_KS19_KS19_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHWO_SHIFT)) & S50_ELS_KS19_KS19_UHWO_MASK) #define S50_ELS_KS19_KS19_UWRPOK_MASK (0x10000000U) #define S50_ELS_KS19_KS19_UWRPOK_SHIFT (28U) #define S50_ELS_KS19_KS19_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UWRPOK_SHIFT)) & S50_ELS_KS19_KS19_UWRPOK_MASK) #define S50_ELS_KS19_KS19_UDUK_MASK (0x20000000U) #define S50_ELS_KS19_KS19_UDUK_SHIFT (29U) #define S50_ELS_KS19_KS19_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UDUK_SHIFT)) & S50_ELS_KS19_KS19_UDUK_MASK) #define S50_ELS_KS19_KS19_UPPROT_MASK (0xC0000000U) #define S50_ELS_KS19_KS19_UPPROT_SHIFT (30U) #define S50_ELS_KS19_KS19_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UPPROT_SHIFT)) & S50_ELS_KS19_KS19_UPPROT_MASK) /*! @} */ /*! * @} */ /* end of group S50_Register_Masks */ /* S50 - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral ELS base address */ #define ELS_BASE (0x50054000u) /** Peripheral ELS base address */ #define ELS_BASE_NS (0x40054000u) /** Peripheral ELS base pointer */ #define ELS ((S50_Type *)ELS_BASE) /** Peripheral ELS base pointer */ #define ELS_NS ((S50_Type *)ELS_BASE_NS) /** Peripheral ELS_ALIAS1 base address */ #define ELS_ALIAS1_BASE (0x50055000u) /** Peripheral ELS_ALIAS1 base address */ #define ELS_ALIAS1_BASE_NS (0x40055000u) /** Peripheral ELS_ALIAS1 base pointer */ #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) /** Peripheral ELS_ALIAS1 base pointer */ #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) /** Peripheral ELS_ALIAS2 base address */ #define ELS_ALIAS2_BASE (0x50056000u) /** Peripheral ELS_ALIAS2 base address */ #define ELS_ALIAS2_BASE_NS (0x40056000u) /** Peripheral ELS_ALIAS2 base pointer */ #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) /** Peripheral ELS_ALIAS2 base pointer */ #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) /** Peripheral ELS_ALIAS3 base address */ #define ELS_ALIAS3_BASE (0x50057000u) /** Peripheral ELS_ALIAS3 base address */ #define ELS_ALIAS3_BASE_NS (0x40057000u) /** Peripheral ELS_ALIAS3 base pointer */ #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) /** Peripheral ELS_ALIAS3 base pointer */ #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) /** Array initializer of S50 peripheral base addresses */ #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } /** Array initializer of S50 peripheral base pointers */ #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } /** Array initializer of S50 peripheral base addresses */ #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } /** Array initializer of S50 peripheral base pointers */ #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } #else /** Peripheral ELS base address */ #define ELS_BASE (0x40054000u) /** Peripheral ELS base pointer */ #define ELS ((S50_Type *)ELS_BASE) /** Peripheral ELS_ALIAS1 base address */ #define ELS_ALIAS1_BASE (0x40055000u) /** Peripheral ELS_ALIAS1 base pointer */ #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) /** Peripheral ELS_ALIAS2 base address */ #define ELS_ALIAS2_BASE (0x40056000u) /** Peripheral ELS_ALIAS2 base pointer */ #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) /** Peripheral ELS_ALIAS3 base address */ #define ELS_ALIAS3_BASE (0x40057000u) /** Peripheral ELS_ALIAS3 base pointer */ #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) /** Array initializer of S50 peripheral base addresses */ #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } /** Array initializer of S50 peripheral base pointers */ #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } #endif /*! * @} */ /* end of group S50_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer * @{ */ /** SCG - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t TRIM_LOCK; /**< Trim Lock register, offset: 0x8 */ uint8_t RESERVED_0[4]; __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ uint8_t RESERVED_1[232]; __IO uint32_t SOSCCSR; /**< SOSC Control Status Register, offset: 0x100 */ uint8_t RESERVED_2[4]; __IO uint32_t SOSCCFG; /**< SOSC Configuration Register, offset: 0x108 */ uint8_t RESERVED_3[244]; __IO uint32_t SIRCCSR; /**< SIRC Control Status Register, offset: 0x200 */ uint8_t RESERVED_4[8]; __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration Register, offset: 0x20C */ __IO uint32_t SIRCTRIM; /**< SIRC Trim Register, offset: 0x210 */ uint8_t RESERVED_5[4]; __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status Register, offset: 0x218 */ uint8_t RESERVED_6[228]; __IO uint32_t FIRCCSR; /**< FIRC Control Status Register, offset: 0x300 */ uint8_t RESERVED_7[4]; __IO uint32_t FIRCCFG; /**< FIRC Configuration Register, offset: 0x308 */ __IO uint32_t FIRCTCFG; /**< FIRC Trim Configuration Register, offset: 0x30C */ __IO uint32_t FIRCTRIM; /**< FIRC Trim Register, offset: 0x310 */ uint8_t RESERVED_8[4]; __IO uint32_t FIRCSTAT; /**< FIRC Auto-trimming Status Register, offset: 0x318 */ uint8_t RESERVED_9[228]; __IO uint32_t ROSCCSR; /**< ROSC Control Status Register, offset: 0x400 */ uint8_t RESERVED_10[252]; __IO uint32_t APLLCSR; /**< APLL Control Status Register, offset: 0x500 */ __IO uint32_t APLLCTRL; /**< APLL Control Register, offset: 0x504 */ __I uint32_t APLLSTAT; /**< APLL Status Register, offset: 0x508 */ __IO uint32_t APLLNDIV; /**< APLL N Divider Register, offset: 0x50C */ __IO uint32_t APLLMDIV; /**< APLL M Divider Register, offset: 0x510 */ __IO uint32_t APLLPDIV; /**< APLL P Divider Register, offset: 0x514 */ __IO uint32_t APLLLOCK_CNFG; /**< APLL LOCK Configuration Register, offset: 0x518 */ uint8_t RESERVED_11[4]; __I uint32_t APLLSSCGSTAT; /**< APLL SSCG Status Register, offset: 0x520 */ __IO uint32_t APLLSSCG0; /**< APLL Spread Spectrum Control 0 Register, offset: 0x524 */ __IO uint32_t APLLSSCG1; /**< APLL Spread Spectrum Control 1 Register, offset: 0x528 */ uint8_t RESERVED_12[200]; __IO uint32_t APLL_OVRD; /**< APLL Override Register, offset: 0x5F4 */ uint8_t RESERVED_13[8]; __IO uint32_t SPLLCSR; /**< SPLL Control Status Register, offset: 0x600 */ __IO uint32_t SPLLCTRL; /**< SPLL Control Register, offset: 0x604 */ __I uint32_t SPLLSTAT; /**< SPLL Status Register, offset: 0x608 */ __IO uint32_t SPLLNDIV; /**< SPLL N Divider Register, offset: 0x60C */ __IO uint32_t SPLLMDIV; /**< SPLL M Divider Register, offset: 0x610 */ __IO uint32_t SPLLPDIV; /**< SPLL P Divider Register, offset: 0x614 */ __IO uint32_t SPLLLOCK_CNFG; /**< SPLL LOCK Configuration Register, offset: 0x618 */ uint8_t RESERVED_14[4]; __I uint32_t SPLLSSCGSTAT; /**< SPLL SSCG Status Register, offset: 0x620 */ __IO uint32_t SPLLSSCG0; /**< SPLL Spread Spectrum Control 0 Register, offset: 0x624 */ __IO uint32_t SPLLSSCG1; /**< SPLL Spread Spectrum Control 1 Register, offset: 0x628 */ uint8_t RESERVED_15[200]; __IO uint32_t SPLL_OVRD; /**< SPLL Override Register, offset: 0x6F4 */ uint8_t RESERVED_16[8]; __IO uint32_t UPLLCSR; /**< UPLL Control Status Register, offset: 0x700 */ uint8_t RESERVED_17[252]; __IO uint32_t LDOCSR; /**< LDO Control and Status Register, offset: 0x800 */ } SCG_Type; /* ---------------------------------------------------------------------------- -- SCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SCG_Register_Masks SCG Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) #define SCG_VERID_VERSION_SHIFT (0U) /*! VERSION - SCG Version Number */ #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define SCG_PARAM_SOSCCLKPRES_MASK (0x2U) #define SCG_PARAM_SOSCCLKPRES_SHIFT (1U) /*! SOSCCLKPRES - SOSC Clock Present * 0b1..SOSC clock source is present * 0b0..SOSC clock source is not present */ #define SCG_PARAM_SOSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK) #define SCG_PARAM_SIRCCLKPRES_MASK (0x4U) #define SCG_PARAM_SIRCCLKPRES_SHIFT (2U) /*! SIRCCLKPRES - SIRC Clock Present * 0b1..SIRC clock source is present * 0b0..SIRC clock source is not present */ #define SCG_PARAM_SIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK) #define SCG_PARAM_FIRCCLKPRES_MASK (0x8U) #define SCG_PARAM_FIRCCLKPRES_SHIFT (3U) /*! FIRCCLKPRES - FIRC Clock Present * 0b1..FIRC clock source is present * 0b0..FIRC clock source is not present */ #define SCG_PARAM_FIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK) #define SCG_PARAM_ROSCCLKPRES_MASK (0x10U) #define SCG_PARAM_ROSCCLKPRES_SHIFT (4U) /*! ROSCCLKPRES - ROSC Clock Present * 0b1..ROSC clock source is present * 0b0..ROSC clock source is not present */ #define SCG_PARAM_ROSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK) #define SCG_PARAM_APLLCLKPRES_MASK (0x20U) #define SCG_PARAM_APLLCLKPRES_SHIFT (5U) /*! APLLCLKPRES - APLL Clock Present * 0b1..APLL clock source is present * 0b0..APLL clock source is not present */ #define SCG_PARAM_APLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_APLLCLKPRES_SHIFT)) & SCG_PARAM_APLLCLKPRES_MASK) #define SCG_PARAM_SPLLCLKPRES_MASK (0x40U) #define SCG_PARAM_SPLLCLKPRES_SHIFT (6U) /*! SPLLCLKPRES - SPLL Clock Present * 0b1..SPLL clock source is present * 0b0..SPLL clock source is not present */ #define SCG_PARAM_SPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SPLLCLKPRES_SHIFT)) & SCG_PARAM_SPLLCLKPRES_MASK) #define SCG_PARAM_UPLLCLKPRES_MASK (0x80U) #define SCG_PARAM_UPLLCLKPRES_SHIFT (7U) /*! UPLLCLKPRES - UPLL Clock Present * 0b1..UPLL clock source is present * 0b0..UPLL clock source is not present */ #define SCG_PARAM_UPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_UPLLCLKPRES_SHIFT)) & SCG_PARAM_UPLLCLKPRES_MASK) /*! @} */ /*! @name TRIM_LOCK - Trim Lock register */ /*! @{ */ #define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK (0x1U) #define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT (0U) /*! TRIM_UNLOCK - TRIM_UNLOCK * 0b0..SCG Trim registers are locked and not writable. * 0b1..SCG Trim registers are unlocked and writable. */ #define SCG_TRIM_LOCK_TRIM_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK) #define SCG_TRIM_LOCK_IFR_DISABLE_MASK (0x2U) #define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT (1U) /*! IFR_DISABLE - IFR_DISABLE * 0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. * 0b1..IFR write access to SCG trim registers during system reset is blocked. */ #define SCG_TRIM_LOCK_IFR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK) #define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK (0xFFFF0000U) #define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT (16U) /*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */ #define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK) /*! @} */ /*! @name CSR - Clock Status Register */ /*! @{ */ #define SCG_CSR_SCS_MASK (0xF000000U) #define SCG_CSR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b0000..Reserved * 0b0001..SOSC * 0b0010..SIRC * 0b0011..FIRC * 0b0100..ROSC * 0b0101..APLL * 0b0110..SPLL * 0b0111..UPLL * 0b1000-0b1111..Reserved */ #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) /*! @} */ /*! @name RCCR - Run Clock Control Register */ /*! @{ */ #define SCG_RCCR_SCS_MASK (0xF000000U) #define SCG_RCCR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b0000..Reserved * 0b0001..SOSC * 0b0010..SIRC * 0b0011..FIRC * 0b0100..ROSC * 0b0101..APLL * 0b0110..SPLL * 0b0111..UPLL * 0b1000-0b1111..Reserved */ #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) /*! @} */ /*! @name SOSCCSR - SOSC Control Status Register */ /*! @{ */ #define SCG_SOSCCSR_SOSCEN_MASK (0x1U) #define SCG_SOSCCSR_SOSCEN_SHIFT (0U) /*! SOSCEN - SOSC Enable * 0b0..SOSC is disabled * 0b1..SOSC is enabled */ #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) #define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) #define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) /*! SOSCSTEN - SOSC Stop Enable * 0b0..SOSC is disabled in Deep Sleep mode * 0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set */ #define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) #define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) #define SCG_SOSCCSR_SOSCCM_SHIFT (16U) /*! SOSCCM - SOSC Clock Monitor Enable * 0b0..SOSC Clock Monitor is disabled * 0b1..SOSC Clock Monitor is enabled */ #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) #define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) #define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) /*! SOSCCMRE - SOSC Clock Monitor Reset Enable * 0b0..Clock monitor generates an interrupt when an error is detected * 0b1..Clock monitor generates a reset when an error is detected */ #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) #define SCG_SOSCCSR_LK_MASK (0x800000U) #define SCG_SOSCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..This Control Status Register can be written * 0b1..This Control Status Register cannot be written */ #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) #define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) /*! SOSCVLD - SOSC Valid * 0b0..SOSC is not enabled or clock is not valid * 0b1..SOSC is enabled and output clock is valid */ #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) #define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) #define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) /*! SOSCSEL - SOSC Selected * 0b0..SOSC is not the system clock source * 0b1..SOSC is the system clock source */ #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) #define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) #define SCG_SOSCCSR_SOSCERR_SHIFT (26U) /*! SOSCERR - SOSC Clock Error * 0b0..SOSC Clock Monitor is disabled or has not detected an error * 0b1..SOSC Clock Monitor is enabled and detected an error */ #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) #define SCG_SOSCCSR_SOSCVLD_IE_MASK (0x40000000U) #define SCG_SOSCCSR_SOSCVLD_IE_SHIFT (30U) /*! SOSCVLD_IE - SOSC Valid Interrupt Enable * 0b0..SOSCVLD interrupt is not enabled * 0b1..SOSCVLD interrupt is enabled */ #define SCG_SOSCCSR_SOSCVLD_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK) /*! @} */ /*! @name SOSCCFG - SOSC Configuration Register */ /*! @{ */ #define SCG_SOSCCFG_EREFS_MASK (0x4U) #define SCG_SOSCCFG_EREFS_SHIFT (2U) /*! EREFS - External Reference Select * 0b0..External reference clock selected. LDO can be disabled in this case. * 0b1..Internal crystal oscillator of OSC selected. */ #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) #define SCG_SOSCCFG_RANGE_MASK (0x30U) #define SCG_SOSCCFG_RANGE_SHIFT (4U) /*! RANGE - SOSC Range Select * 0b00..Frequency range select of 16-20 MHz. * 0b01..Frequency range select of 20-30 MHz. * 0b10..Frequency range select of 30-50 MHz. * 0b11..Frequency range select of 50-66 MHz. */ #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) /*! @} */ /*! @name SIRCCSR - SIRC Control Status Register */ /*! @{ */ #define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) #define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) /*! SIRCSTEN - SIRC Stop Enable * 0b0..SIRC is disabled in Deep Sleep mode * 0b1..SIRC is enabled in Deep Sleep mode */ #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) #define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK (0x20U) #define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT (5U) /*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable * 0b0..SIRC clock to peripherals is disabled * 0b1..SIRC clock to peripherals is enabled */ #define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) #define SCG_SIRCCSR_SIRCTREN_MASK (0x100U) #define SCG_SIRCCSR_SIRCTREN_SHIFT (8U) /*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) * 0b0..Disables trimming SIRC to an external clock source * 0b1..Enables trimming SIRC to an external clock source */ #define SCG_SIRCCSR_SIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK) #define SCG_SIRCCSR_SIRCTRUP_MASK (0x200U) #define SCG_SIRCCSR_SIRCTRUP_SHIFT (9U) /*! SIRCTRUP - SIRC Trim Update * 0b0..Disables SIRC trimming updates * 0b1..Enables SIRC trimming updates */ #define SCG_SIRCCSR_SIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK) #define SCG_SIRCCSR_TRIM_LOCK_MASK (0x400U) #define SCG_SIRCCSR_TRIM_LOCK_SHIFT (10U) /*! TRIM_LOCK - SIRC TRIM LOCK * 0b0..SIRC auto trim not locked to target frequency range * 0b1..SIRC auto trim locked to target frequency range */ #define SCG_SIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK) #define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) #define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) /*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass * 0b0..SIRC coarse auto-trim is not bypassed * 0b1..SIRC coarse auto-trim is bypassed */ #define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK) #define SCG_SIRCCSR_LK_MASK (0x800000U) #define SCG_SIRCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written * 0b1..Control Status Register cannot be written */ #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) #define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) /*! SIRCVLD - SIRC Valid * 0b0..SIRC is not enabled or clock is not valid * 0b1..SIRC is enabled and output clock is valid */ #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) #define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) #define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) /*! SIRCSEL - SIRC Selected * 0b0..SIRC is not the system clock source * 0b1..SIRC is the system clock source */ #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) #define SCG_SIRCCSR_SIRCERR_MASK (0x4000000U) #define SCG_SIRCCSR_SIRCERR_SHIFT (26U) /*! SIRCERR - SIRC Clock Error * 0b0..Error not detected with the SIRC trimming * 0b1..Error detected with the SIRC trimming */ #define SCG_SIRCCSR_SIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK) #define SCG_SIRCCSR_SIRCERR_IE_MASK (0x8000000U) #define SCG_SIRCCSR_SIRCERR_IE_SHIFT (27U) /*! SIRCERR_IE - SIRC Clock Error Interrupt Enable * 0b0..SIRCERR interrupt is not enabled * 0b1..SIRCERR interrupt is enabled */ #define SCG_SIRCCSR_SIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK) /*! @} */ /*! @name SIRCTCFG - SIRC Trim Configuration Register */ /*! @{ */ #define SCG_SIRCTCFG_TRIMSRC_MASK (0x3U) #define SCG_SIRCTCFG_TRIMSRC_SHIFT (0U) /*! TRIMSRC - Trim Source * 0b00..Reserved * 0b01..Reserved * 0b10..SOSC * 0b11..ROSC (32.768 kHz) */ #define SCG_SIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK) #define SCG_SIRCTCFG_TRIMDIV_MASK (0x7F0000U) #define SCG_SIRCTCFG_TRIMDIV_SHIFT (16U) /*! TRIMDIV - SIRC Trim Predivider */ #define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) /*! @} */ /*! @name SIRCTRIM - SIRC Trim Register */ /*! @{ */ #define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) #define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) /*! CCOTRIM - CCO Trim */ #define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) #define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) #define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) /*! CLTRIM - CL Trim */ #define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) #define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) #define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) /*! TCTRIM - Trim Temp */ #define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) #define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) #define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) #define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) /*! @} */ /*! @name SIRCSTAT - SIRC Auto-trimming Status Register */ /*! @{ */ #define SCG_SIRCSTAT_CCOTRIM_MASK (0x3FU) #define SCG_SIRCSTAT_CCOTRIM_SHIFT (0U) /*! CCOTRIM - CCO Trim */ #define SCG_SIRCSTAT_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK) #define SCG_SIRCSTAT_CLTRIM_MASK (0x3F00U) #define SCG_SIRCSTAT_CLTRIM_SHIFT (8U) /*! CLTRIM - CL Trim */ #define SCG_SIRCSTAT_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK) /*! @} */ /*! @name FIRCCSR - FIRC Control Status Register */ /*! @{ */ #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) #define SCG_FIRCCSR_FIRCEN_SHIFT (0U) /*! FIRCEN - FIRC Enable * 0b0..FIRC is disabled * 0b1..FIRC is enabled */ #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) #define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) #define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) /*! FIRCSTEN - FIRC Stop Enable * 0b0..FIRC is disabled in Deep Sleep mode * 0b1..FIRC is enabled in Deep Sleep mode */ #define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) #define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK (0x10U) #define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT (4U) /*! FIRC_SCLK_PERIPH_EN - FIRC 48 MHz Clock to peripherals Enable * 0b0..FIRC 48 MHz to peripherals is disabled * 0b1..FIRC 48 MHz to peripherals is enabled */ #define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) #define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK (0x20U) #define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT (5U) /*! FIRC_FCLK_PERIPH_EN - FIRC 144 MHz Clock to peripherals Enable * 0b0..FIRC 144 MHz to peripherals is disabled * 0b1..FIRC 144 MHz to peripherals is enabled */ #define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) #define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) #define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) /*! FIRCTREN - FIRC 144 MHz Trim Enable (FIRCCFG[RANGE]=1) * 0b0..Disables trimming FIRC to an external clock source * 0b1..Enables trimming FIRC to an external clock source */ #define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) #define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) #define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) /*! FIRCTRUP - FIRC Trim Update * 0b0..Disables FIRC trimming updates * 0b1..Enables FIRC trimming updates */ #define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) #define SCG_FIRCCSR_TRIM_LOCK_MASK (0x400U) #define SCG_FIRCCSR_TRIM_LOCK_SHIFT (10U) /*! TRIM_LOCK - FIRC TRIM LOCK * 0b0..FIRC auto trim not locked to target frequency range * 0b1..FIRC auto trim locked to target frequency range */ #define SCG_FIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_TRIM_LOCK_SHIFT)) & SCG_FIRCCSR_TRIM_LOCK_MASK) #define SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) #define SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) /*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass * 0b0..FIRC coarse auto trim is not bypassed * 0b1..FIRC coarse auto trim is bypassed */ #define SCG_FIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK) #define SCG_FIRCCSR_LK_MASK (0x800000U) #define SCG_FIRCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written * 0b1..Control Status Register cannot be written */ #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) #define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) #define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) /*! FIRCVLD - FIRC Valid status * 0b0..FIRC is not enabled or clock is not valid. * 0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. */ #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) #define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) /*! FIRCSEL - FIRC Selected * 0b0..FIRC is not the system clock source * 0b1..FIRC is the system clock source */ #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) #define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) #define SCG_FIRCCSR_FIRCERR_SHIFT (26U) /*! FIRCERR - FIRC Clock Error * 0b0..Error not detected with the FIRC trimming * 0b1..Error detected with the FIRC trimming */ #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) #define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) #define SCG_FIRCCSR_FIRCERR_IE_SHIFT (27U) /*! FIRCERR_IE - FIRC Clock Error Interrupt Enable * 0b0..FIRCERR interrupt is not enabled * 0b1..FIRCERR interrupt is enabled */ #define SCG_FIRCCSR_FIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK) #define SCG_FIRCCSR_FIRCACC_IE_MASK (0x40000000U) #define SCG_FIRCCSR_FIRCACC_IE_SHIFT (30U) /*! FIRCACC_IE - FIRC Accurate Interrupt Enable * 0b0..FIRCACC interrupt is not enabled * 0b1..FIRCACC interrupt is enabled */ #define SCG_FIRCCSR_FIRCACC_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK) #define SCG_FIRCCSR_FIRCACC_MASK (0x80000000U) #define SCG_FIRCCSR_FIRCACC_SHIFT (31U) /*! FIRCACC - FIRC Frequency Accurate * 0b0..FIRC is not enabled or clock is not accurate. * 0b1..FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of 144 MHz * (RANGE=1) or 1365 clock cycles of 48 MHz(RANGE=0) from the FIRC analog. */ #define SCG_FIRCCSR_FIRCACC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK) /*! @} */ /*! @name FIRCCFG - FIRC Configuration Register */ /*! @{ */ #define SCG_FIRCCFG_RANGE_MASK (0x1U) #define SCG_FIRCCFG_RANGE_SHIFT (0U) /*! RANGE - Frequency Range * 0b0..48 MHz FIRC clock selected * 0b1..144 MHz FIRC clock selected */ #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) /*! @} */ /*! @name FIRCTCFG - FIRC Trim Configuration Register */ /*! @{ */ #define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) #define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) /*! TRIMSRC - Trim Source * 0b00..USB0 Start of Frame (1 kHz). This option does not use TRIMDIV * 0b01..Reserved * 0b10..SOSC * 0b11..ROSC */ #define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) #define SCG_FIRCTCFG_TRIMDIV_MASK (0x7F0000U) #define SCG_FIRCTCFG_TRIMDIV_SHIFT (16U) /*! TRIMDIV - FIRC Trim Predivider */ #define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) /*! @} */ /*! @name FIRCTRIM - FIRC Trim Register */ /*! @{ */ #define SCG_FIRCTRIM_TRIMFINE_MASK (0xFFU) #define SCG_FIRCTRIM_TRIMFINE_SHIFT (0U) /*! TRIMFINE - Trim Fine */ #define SCG_FIRCTRIM_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK) #define SCG_FIRCTRIM_TRIMCOAR_MASK (0x3F00U) #define SCG_FIRCTRIM_TRIMCOAR_SHIFT (8U) /*! TRIMCOAR - Trim Coarse */ #define SCG_FIRCTRIM_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK) #define SCG_FIRCTRIM_TRIMTEMP_MASK (0x30000U) #define SCG_FIRCTRIM_TRIMTEMP_SHIFT (16U) /*! TRIMTEMP - Trim Temperature */ #define SCG_FIRCTRIM_TRIMTEMP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP_MASK) #define SCG_FIRCTRIM_TRIMSTART_MASK (0x3F000000U) #define SCG_FIRCTRIM_TRIMSTART_SHIFT (24U) /*! TRIMSTART - Trim Start */ #define SCG_FIRCTRIM_TRIMSTART(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK) /*! @} */ /*! @name FIRCSTAT - FIRC Auto-trimming Status Register */ /*! @{ */ #define SCG_FIRCSTAT_TRIMFINE_MASK (0xFFU) #define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) /*! TRIMFINE - Trim Fine */ #define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) #define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) #define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) /*! TRIMCOAR - Trim Coarse */ #define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) /*! @} */ /*! @name ROSCCSR - ROSC Control Status Register */ /*! @{ */ #define SCG_ROSCCSR_ROSCCM_MASK (0x10000U) #define SCG_ROSCCSR_ROSCCM_SHIFT (16U) /*! ROSCCM - ROSC Clock Monitor * 0b0..ROSC clock monitor is disabled * 0b1..ROSC clock monitor is enabled */ #define SCG_ROSCCSR_ROSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK) #define SCG_ROSCCSR_ROSCCMRE_MASK (0x20000U) #define SCG_ROSCCSR_ROSCCMRE_SHIFT (17U) /*! ROSCCMRE - ROSC Clock Monitor Reset Enable * 0b0..Clock monitor generates an interrupt when an error is detected * 0b1..Clock monitor generates a reset when an error is detected */ #define SCG_ROSCCSR_ROSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK) #define SCG_ROSCCSR_LK_MASK (0x800000U) #define SCG_ROSCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written * 0b1..Control Status Register cannot be written */ #define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) #define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) #define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) /*! ROSCVLD - ROSC Valid * 0b0..ROSC is not enabled or clock is not valid * 0b1..ROSC is enabled and output clock is valid */ #define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) #define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) #define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) /*! ROSCSEL - ROSC Selected * 0b0..ROSC is not the system clock source * 0b1..ROSC is the system clock source */ #define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) #define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) #define SCG_ROSCCSR_ROSCERR_SHIFT (26U) /*! ROSCERR - ROSC Clock Error * 0b0..ROSC Clock Monitor is disabled or has not detected an error * 0b1..ROSC Clock Monitor is enabled and detected an RTC loss of clock error */ #define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) /*! @} */ /*! @name APLLCSR - APLL Control Status Register */ /*! @{ */ #define SCG_APLLCSR_APLLPWREN_MASK (0x1U) #define SCG_APLLCSR_APLLPWREN_SHIFT (0U) /*! APLLPWREN - APLL Power Enable * 0b0..APLL clock is powered off * 0b1..APLL clock is powered on */ #define SCG_APLLCSR_APLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLPWREN_SHIFT)) & SCG_APLLCSR_APLLPWREN_MASK) #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) #define SCG_APLLCSR_APLLCLKEN_SHIFT (1U) /*! APLLCLKEN - APLL Clock Enable * 0b0..APLL clock is disabled * 0b1..APLL clock is enabled */ #define SCG_APLLCSR_APLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK) #define SCG_APLLCSR_APLLSTEN_MASK (0x4U) #define SCG_APLLCSR_APLLSTEN_SHIFT (2U) /*! APLLSTEN - APLL Stop Enable * 0b0..APLL is disabled in Deep Sleep mode * 0b1..APLL is enabled in Deep Sleep mode */ #define SCG_APLLCSR_APLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSTEN_SHIFT)) & SCG_APLLCSR_APLLSTEN_MASK) #define SCG_APLLCSR_APLLCM_MASK (0x10000U) #define SCG_APLLCSR_APLLCM_SHIFT (16U) /*! APLLCM - APLL Clock Monitor * 0b0..APLL Clock Monitor is disabled * 0b1..APLL Clock Monitor is enabled */ #define SCG_APLLCSR_APLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCM_SHIFT)) & SCG_APLLCSR_APLLCM_MASK) #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) #define SCG_APLLCSR_APLLCMRE_SHIFT (17U) /*! APLLCMRE - APLL Clock Monitor Reset Enable * 0b0..Clock monitor generates an interrupt when an error is detected * 0b1..Clock monitor generates a reset when an error is detected */ #define SCG_APLLCSR_APLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK) #define SCG_APLLCSR_LK_MASK (0x800000U) #define SCG_APLLCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written * 0b1..Control Status Register cannot be written */ #define SCG_APLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_LK_SHIFT)) & SCG_APLLCSR_LK_MASK) #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) #define SCG_APLLCSR_APLL_LOCK_SHIFT (24U) /*! APLL_LOCK - APLL LOCK * 0b0..APLL is not powered on or not locked * 0b1..APLL is locked */ #define SCG_APLLCSR_APLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK) #define SCG_APLLCSR_APLLSEL_MASK (0x2000000U) #define SCG_APLLCSR_APLLSEL_SHIFT (25U) /*! APLLSEL - APLL Selected * 0b0..APLL is not the system clock source * 0b1..APLL is the system clock source */ #define SCG_APLLCSR_APLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSEL_SHIFT)) & SCG_APLLCSR_APLLSEL_MASK) #define SCG_APLLCSR_APLLERR_MASK (0x4000000U) #define SCG_APLLCSR_APLLERR_SHIFT (26U) /*! APLLERR - APLL Clock Error * 0b0..APLL Clock Monitor is disabled or has not detected an error * 0b1..APLL Clock Monitor is enabled and detected an error */ #define SCG_APLLCSR_APLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLERR_SHIFT)) & SCG_APLLCSR_APLLERR_MASK) #define SCG_APLLCSR_APLL_LOCK_IE_MASK (0x40000000U) #define SCG_APLLCSR_APLL_LOCK_IE_SHIFT (30U) /*! APLL_LOCK_IE - APLL LOCK Interrupt Enable * 0b0..APLL_LOCK interrupt is not enabled * 0b1..APLL_LOCK interrupt is enabled */ #define SCG_APLLCSR_APLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_IE_SHIFT)) & SCG_APLLCSR_APLL_LOCK_IE_MASK) /*! @} */ /*! @name APLLCTRL - APLL Control Register */ /*! @{ */ #define SCG_APLLCTRL_SELR_MASK (0xFU) #define SCG_APLLCTRL_SELR_SHIFT (0U) /*! SELR - Bandwidth select R (resistor) value. */ #define SCG_APLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELR_SHIFT)) & SCG_APLLCTRL_SELR_MASK) #define SCG_APLLCTRL_SELI_MASK (0x3F0U) #define SCG_APLLCTRL_SELI_SHIFT (4U) /*! SELI - Bandwidth select I (integration) value. */ #define SCG_APLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELI_SHIFT)) & SCG_APLLCTRL_SELI_MASK) #define SCG_APLLCTRL_SELP_MASK (0x7C00U) #define SCG_APLLCTRL_SELP_SHIFT (10U) /*! SELP - Bandwidth select P (proportional) value. */ #define SCG_APLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELP_SHIFT)) & SCG_APLLCTRL_SELP_MASK) #define SCG_APLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) #define SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) /*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider * 0b0..Use the divide-by-2 divider in the postdivider * 0b1..Bypass of the divide-by-2 divider in the postdivider */ #define SCG_APLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) #define SCG_APLLCTRL_LIMUPOFF_MASK (0x20000U) #define SCG_APLLCTRL_LIMUPOFF_SHIFT (17U) /*! LIMUPOFF - Up Limiter * 0b0..Application set to non-Spectrum and Fractional applications. * 0b1..Application set to Spectrum and Fractional applications. */ #define SCG_APLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_LIMUPOFF_SHIFT)) & SCG_APLLCTRL_LIMUPOFF_MASK) #define SCG_APLLCTRL_BANDDIRECT_MASK (0x40000U) #define SCG_APLLCTRL_BANDDIRECT_SHIFT (18U) /*! BANDDIRECT - Control of the bandwidth of the PLL. * 0b0..The bandwidth is changed synchronously with the feedback-divider * 0b1..Modifies the bandwidth of the PLL directly */ #define SCG_APLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BANDDIRECT_SHIFT)) & SCG_APLLCTRL_BANDDIRECT_MASK) #define SCG_APLLCTRL_BYPASSPREDIV_MASK (0x80000U) #define SCG_APLLCTRL_BYPASSPREDIV_SHIFT (19U) /*! BYPASSPREDIV - Bypass of the predivider * 0b0..Use the predivider. * 0b1..Bypass of the predivider. */ #define SCG_APLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPREDIV_MASK) #define SCG_APLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) #define SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT (20U) /*! BYPASSPOSTDIV - Bypass of the postdivider * 0b0..Use the postdivider. * 0b1..Bypass of the postdivider */ #define SCG_APLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) #define SCG_APLLCTRL_SOURCE_MASK (0x6000000U) #define SCG_APLLCTRL_SOURCE_SHIFT (25U) /*! SOURCE - Clock Source * 0b00..SOSC * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. * 0b10..Reserved * 0b11..No clock */ #define SCG_APLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SOURCE_SHIFT)) & SCG_APLLCTRL_SOURCE_MASK) /*! @} */ /*! @name APLLSTAT - APLL Status Register */ /*! @{ */ #define SCG_APLLSTAT_NDIVACK_MASK (0x2U) #define SCG_APLLSTAT_NDIVACK_SHIFT (1U) /*! NDIVACK - Predivider(N) ratio change acknowledge. * 0b0..The predivider (N) ratio change is not accepted by the analog PLL * 0b1..The predivider (N) ratio change is accepted by the analog PLL */ #define SCG_APLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_NDIVACK_SHIFT)) & SCG_APLLSTAT_NDIVACK_MASK) #define SCG_APLLSTAT_MDIVACK_MASK (0x4U) #define SCG_APLLSTAT_MDIVACK_SHIFT (2U) /*! MDIVACK - Feedback(M) divider ratio change acknowledge. * 0b0..The feedback (M) ratio change is not accepted by the analog PLL * 0b1..The feedback (M) ratio change is accepted by the analog PLL */ #define SCG_APLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_MDIVACK_SHIFT)) & SCG_APLLSTAT_MDIVACK_MASK) #define SCG_APLLSTAT_PDIVACK_MASK (0x8U) #define SCG_APLLSTAT_PDIVACK_SHIFT (3U) /*! PDIVACK - Postdivider(P) ratio change acknowledge. * 0b0..The postdivider (P) ratio change is not accepted by the analog PLL * 0b1..The postdivider (P) ratio change is accepted by the analog PLL */ #define SCG_APLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_PDIVACK_SHIFT)) & SCG_APLLSTAT_PDIVACK_MASK) /*! @} */ /*! @name APLLNDIV - APLL N Divider Register */ /*! @{ */ #define SCG_APLLNDIV_NDIV_MASK (0xFFU) #define SCG_APLLNDIV_NDIV_SHIFT (0U) /*! NDIV - Predivider divider ratio (N-divider). */ #define SCG_APLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NDIV_SHIFT)) & SCG_APLLNDIV_NDIV_MASK) #define SCG_APLLNDIV_NREQ_MASK (0x80000000U) #define SCG_APLLNDIV_NREQ_SHIFT (31U) /*! NREQ - Predivider ratio change request. * 0b0..Predivider ratio change is not requested * 0b1..Predivider ratio change is requested */ #define SCG_APLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NREQ_SHIFT)) & SCG_APLLNDIV_NREQ_MASK) /*! @} */ /*! @name APLLMDIV - APLL M Divider Register */ /*! @{ */ #define SCG_APLLMDIV_MDIV_MASK (0xFFFFU) #define SCG_APLLMDIV_MDIV_SHIFT (0U) /*! MDIV - Feedback divider divider ratio (M-divider). */ #define SCG_APLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MDIV_SHIFT)) & SCG_APLLMDIV_MDIV_MASK) #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) #define SCG_APLLMDIV_MREQ_SHIFT (31U) /*! MREQ - Feedback ratio change request. * 0b0..Feedback ratio change is not requested * 0b1..Feedback ratio change is requested */ #define SCG_APLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK) /*! @} */ /*! @name APLLPDIV - APLL P Divider Register */ /*! @{ */ #define SCG_APLLPDIV_PDIV_MASK (0x1FU) #define SCG_APLLPDIV_PDIV_SHIFT (0U) /*! PDIV - Postdivider divider ratio (P-divider) */ #define SCG_APLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PDIV_SHIFT)) & SCG_APLLPDIV_PDIV_MASK) #define SCG_APLLPDIV_PREQ_MASK (0x80000000U) #define SCG_APLLPDIV_PREQ_SHIFT (31U) /*! PREQ - Postdivider ratio change request * 0b0..Postdivider ratio change is not requested * 0b1..Postdivider ratio change is requested */ #define SCG_APLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PREQ_SHIFT)) & SCG_APLLPDIV_PREQ_MASK) /*! @} */ /*! @name APLLLOCK_CNFG - APLL LOCK Configuration Register */ /*! @{ */ #define SCG_APLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) #define SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) /*! LOCK_TIME - Configures the number of reference clocks to count before APLL is considered locked. */ #define SCG_APLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_APLLLOCK_CNFG_LOCK_TIME_MASK) /*! @} */ /*! @name APLLSSCGSTAT - APLL SSCG Status Register */ /*! @{ */ #define SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) #define SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) /*! SS_MDIV_ACK - SS_MDIV change acknowledge * 0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL * 0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL */ #define SCG_APLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK) /*! @} */ /*! @name APLLSSCG0 - APLL Spread Spectrum Control 0 Register */ /*! @{ */ #define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) #define SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT (0U) /*! SS_MDIV_LSB - SS_MDIV */ #define SCG_APLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK) /*! @} */ /*! @name APLLSSCG1 - APLL Spread Spectrum Control 1 Register */ /*! @{ */ #define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) #define SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT (0U) /*! SS_MDIV_MSB - SS_MDIV[32] */ #define SCG_APLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) #define SCG_APLLSSCG1_SS_MDIV_REQ_MASK (0x2U) #define SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT (1U) /*! SS_MDIV_REQ - SS_MDIV[32:0] change request. * 0b0..SS_MDIV change is not requested * 0b1..SS_MDIV change is requested */ #define SCG_APLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_REQ_MASK) #define SCG_APLLSSCG1_MF_MASK (0x1CU) #define SCG_APLLSSCG1_MF_SHIFT (2U) /*! MF - Modulation Frequency Control */ #define SCG_APLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MF_SHIFT)) & SCG_APLLSSCG1_MF_MASK) #define SCG_APLLSSCG1_MR_MASK (0xE0U) #define SCG_APLLSSCG1_MR_SHIFT (5U) /*! MR - Modulation Depth Control */ #define SCG_APLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MR_SHIFT)) & SCG_APLLSSCG1_MR_MASK) #define SCG_APLLSSCG1_MC_MASK (0x300U) #define SCG_APLLSSCG1_MC_SHIFT (8U) /*! MC - Modulation Waveform Control * 0b00..MC[1:0] no compensation * 0b11..MC[1:0] maximum compensation */ #define SCG_APLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MC_SHIFT)) & SCG_APLLSSCG1_MC_MASK) #define SCG_APLLSSCG1_DITHER_MASK (0x400U) #define SCG_APLLSSCG1_DITHER_SHIFT (10U) /*! DITHER - Dither Enable * 0b0..Dither is not enabled * 0b1..Dither is enabled */ #define SCG_APLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_DITHER_SHIFT)) & SCG_APLLSSCG1_DITHER_MASK) #define SCG_APLLSSCG1_SEL_SS_MDIV_MASK (0x800U) #define SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT (11U) /*! SEL_SS_MDIV - SS_MDIV select. * 0b0..Feedback divider ratio is MDIV[15:0] * 0b1..Feedback divider ratio is SS_MDIV[32:0] */ #define SCG_APLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) #define SCG_APLLSSCG1_SS_PD_MASK (0x80000000U) #define SCG_APLLSSCG1_SS_PD_SHIFT (31U) /*! SS_PD - SSCG Power Down * 0b0..SSCG is powered on * 0b1..SSCG is powered off */ #define SCG_APLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_PD_SHIFT)) & SCG_APLLSSCG1_SS_PD_MASK) /*! @} */ /*! @name APLL_OVRD - APLL Override Register */ /*! @{ */ #define SCG_APLL_OVRD_APLLPWREN_OVRD_MASK (0x1U) #define SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT (0U) /*! APLLPWREN_OVRD - APLL Power Enable Override if APLL_OVRD_EN=1 * 0b0..APLL clock is powered off * 0b1..APLL clock is powered on */ #define SCG_APLL_OVRD_APLLPWREN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLPWREN_OVRD_MASK) #define SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK (0x2U) #define SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT (1U) /*! APLLCLKEN_OVRD - APLL Clock Enable Override if APLL_OVRD_EN=1 * 0b0..APLL clock is disabled * 0b1..APLL clock is enabled */ #define SCG_APLL_OVRD_APLLCLKEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK) #define SCG_APLL_OVRD_APLL_OVRD_EN_MASK (0x80000000U) #define SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT (31U) /*! APLL_OVRD_EN - APLL Override Enable * 0b0..APLL override is disabled * 0b1..APLL override is enabled */ #define SCG_APLL_OVRD_APLL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT)) & SCG_APLL_OVRD_APLL_OVRD_EN_MASK) /*! @} */ /*! @name SPLLCSR - SPLL Control Status Register */ /*! @{ */ #define SCG_SPLLCSR_SPLLPWREN_MASK (0x1U) #define SCG_SPLLCSR_SPLLPWREN_SHIFT (0U) /*! SPLLPWREN - SPLL Power Enable * 0b0..SPLL clock is powered off * 0b1..SPLL clock is powered on */ #define SCG_SPLLCSR_SPLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLPWREN_SHIFT)) & SCG_SPLLCSR_SPLLPWREN_MASK) #define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) #define SCG_SPLLCSR_SPLLCLKEN_SHIFT (1U) /*! SPLLCLKEN - SPLL Clock Enable * 0b0..SPLL clock is disabled * 0b1..SPLL clock is enabled */ #define SCG_SPLLCSR_SPLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK) #define SCG_SPLLCSR_SPLLSTEN_MASK (0x4U) #define SCG_SPLLCSR_SPLLSTEN_SHIFT (2U) /*! SPLLSTEN - SPLL Stop Enable * 0b0..SPLL is disabled in Deep Sleep mode * 0b1..SPLL is enabled in Deep Sleep mode */ #define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK) #define SCG_SPLLCSR_SPLLCM_MASK (0x10000U) #define SCG_SPLLCSR_SPLLCM_SHIFT (16U) /*! SPLLCM - SPLL Clock Monitor * 0b0..SPLL Clock Monitor is disabled * 0b1..SPLL Clock Monitor is enabled */ #define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK) #define SCG_SPLLCSR_SPLLCMRE_MASK (0x20000U) #define SCG_SPLLCSR_SPLLCMRE_SHIFT (17U) /*! SPLLCMRE - SPLL Clock Monitor Reset Enable * 0b0..Clock monitor generates an interrupt when an error is detected * 0b1..Clock monitor generates a reset when an error is detected */ #define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK) #define SCG_SPLLCSR_LK_MASK (0x800000U) #define SCG_SPLLCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written * 0b1..Control Status Register cannot be written */ #define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK) #define SCG_SPLLCSR_SPLL_LOCK_MASK (0x1000000U) #define SCG_SPLLCSR_SPLL_LOCK_SHIFT (24U) /*! SPLL_LOCK - SPLL LOCK * 0b0..SPLL is not powered on or not locked * 0b1..SPLL is locked */ #define SCG_SPLLCSR_SPLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_MASK) #define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U) #define SCG_SPLLCSR_SPLLSEL_SHIFT (25U) /*! SPLLSEL - SPLL Selected * 0b0..SPLL is not the system clock source * 0b1..SPLL is the system clock source */ #define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK) #define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U) #define SCG_SPLLCSR_SPLLERR_SHIFT (26U) /*! SPLLERR - SPLL Clock Error * 0b0..SPLL Clock Monitor is disabled or has not detected an error * 0b1..SPLL Clock Monitor is enabled and detected an error */ #define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK) #define SCG_SPLLCSR_SPLL_LOCK_IE_MASK (0x40000000U) #define SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT (30U) /*! SPLL_LOCK_IE - SPLL LOCK Interrupt Enable * 0b0..SPLL_LOCK interrupt is not enabled * 0b1..SPLL_LOCK interrupt is enabled */ #define SCG_SPLLCSR_SPLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_IE_MASK) /*! @} */ /*! @name SPLLCTRL - SPLL Control Register */ /*! @{ */ #define SCG_SPLLCTRL_SELR_MASK (0xFU) #define SCG_SPLLCTRL_SELR_SHIFT (0U) /*! SELR - Bandwidth select R (resistor) value. */ #define SCG_SPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK) #define SCG_SPLLCTRL_SELI_MASK (0x3F0U) #define SCG_SPLLCTRL_SELI_SHIFT (4U) /*! SELI - Bandwidth select I (integration) value. */ #define SCG_SPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELI_SHIFT)) & SCG_SPLLCTRL_SELI_MASK) #define SCG_SPLLCTRL_SELP_MASK (0x7C00U) #define SCG_SPLLCTRL_SELP_SHIFT (10U) /*! SELP - Bandwidth select P (proportional) value. */ #define SCG_SPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELP_SHIFT)) & SCG_SPLLCTRL_SELP_MASK) #define SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) #define SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) /*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider * 0b0..Use the divide-by-2 divider in the postdivider. * 0b1..Bypass of the divide-by-2 divider in the postdivider */ #define SCG_SPLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) #define SCG_SPLLCTRL_LIMUPOFF_MASK (0x20000U) #define SCG_SPLLCTRL_LIMUPOFF_SHIFT (17U) /*! LIMUPOFF - Up Limiter. * 0b0..Application set to non-Spectrum and Fractional applications. * 0b1..Application set to Spectrum and Fractional applications. */ #define SCG_SPLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_LIMUPOFF_SHIFT)) & SCG_SPLLCTRL_LIMUPOFF_MASK) #define SCG_SPLLCTRL_BANDDIRECT_MASK (0x40000U) #define SCG_SPLLCTRL_BANDDIRECT_SHIFT (18U) /*! BANDDIRECT - Control of the bandwidth of the PLL. * 0b0..The bandwidth is changed synchronously with the feedback-divider * 0b1..Modifies the bandwidth of the PLL directly */ #define SCG_SPLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BANDDIRECT_SHIFT)) & SCG_SPLLCTRL_BANDDIRECT_MASK) #define SCG_SPLLCTRL_BYPASSPREDIV_MASK (0x80000U) #define SCG_SPLLCTRL_BYPASSPREDIV_SHIFT (19U) /*! BYPASSPREDIV - Bypass of the predivider. * 0b0..Use the predivider * 0b1..Bypass of the predivider */ #define SCG_SPLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPREDIV_MASK) #define SCG_SPLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) #define SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT (20U) /*! BYPASSPOSTDIV - Bypass of the postdivider. * 0b0..Use the postdivider * 0b1..Bypass of the postdivider */ #define SCG_SPLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) #define SCG_SPLLCTRL_SOURCE_MASK (0x6000000U) #define SCG_SPLLCTRL_SOURCE_SHIFT (25U) /*! SOURCE - Clock Source * 0b00..SOSC * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. * 0b10..Reserved * 0b11..No clock */ #define SCG_SPLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SOURCE_SHIFT)) & SCG_SPLLCTRL_SOURCE_MASK) /*! @} */ /*! @name SPLLSTAT - SPLL Status Register */ /*! @{ */ #define SCG_SPLLSTAT_NDIVACK_MASK (0x2U) #define SCG_SPLLSTAT_NDIVACK_SHIFT (1U) /*! NDIVACK - Predivider (N) ratio change acknowledge * 0b0..The predivider (N) ratio change is not accepted by the analog PLL. * 0b1..The predivider (N) ratio change is accepted by the analog PLL. */ #define SCG_SPLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_NDIVACK_SHIFT)) & SCG_SPLLSTAT_NDIVACK_MASK) #define SCG_SPLLSTAT_MDIVACK_MASK (0x4U) #define SCG_SPLLSTAT_MDIVACK_SHIFT (2U) /*! MDIVACK - Feedback (M) divider ratio change acknowledge * 0b0..The feedback (M) ratio change is not accepted by the analog PLL. * 0b1..The feedback (M) ratio change is accepted by the analog PLL. */ #define SCG_SPLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_MDIVACK_SHIFT)) & SCG_SPLLSTAT_MDIVACK_MASK) #define SCG_SPLLSTAT_PDIVACK_MASK (0x8U) #define SCG_SPLLSTAT_PDIVACK_SHIFT (3U) /*! PDIVACK - Postdivider (P) ratio change acknowledge * 0b0..The postdivider (P) ratio change is not accepted by the analog PLL * 0b1..The postdivider (P) ratio change is accepted by the analog PLL */ #define SCG_SPLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_PDIVACK_SHIFT)) & SCG_SPLLSTAT_PDIVACK_MASK) /*! @} */ /*! @name SPLLNDIV - SPLL N Divider Register */ /*! @{ */ #define SCG_SPLLNDIV_NDIV_MASK (0xFFU) #define SCG_SPLLNDIV_NDIV_SHIFT (0U) /*! NDIV - Predivider divider ratio (N-divider). */ #define SCG_SPLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NDIV_SHIFT)) & SCG_SPLLNDIV_NDIV_MASK) #define SCG_SPLLNDIV_NREQ_MASK (0x80000000U) #define SCG_SPLLNDIV_NREQ_SHIFT (31U) /*! NREQ - Predivider ratio change request. * 0b0..Predivider ratio change is not requested * 0b1..Predivider ratio change is requested */ #define SCG_SPLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NREQ_SHIFT)) & SCG_SPLLNDIV_NREQ_MASK) /*! @} */ /*! @name SPLLMDIV - SPLL M Divider Register */ /*! @{ */ #define SCG_SPLLMDIV_MDIV_MASK (0xFFFFU) #define SCG_SPLLMDIV_MDIV_SHIFT (0U) /*! MDIV - Feedback divider divider ratio (M-divider). */ #define SCG_SPLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MDIV_SHIFT)) & SCG_SPLLMDIV_MDIV_MASK) #define SCG_SPLLMDIV_MREQ_MASK (0x80000000U) #define SCG_SPLLMDIV_MREQ_SHIFT (31U) /*! MREQ - Feedback ratio change request. * 0b0..Feedback ratio change is not requested * 0b1..Feedback ratio change is requested */ #define SCG_SPLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MREQ_SHIFT)) & SCG_SPLLMDIV_MREQ_MASK) /*! @} */ /*! @name SPLLPDIV - SPLL P Divider Register */ /*! @{ */ #define SCG_SPLLPDIV_PDIV_MASK (0x1FU) #define SCG_SPLLPDIV_PDIV_SHIFT (0U) /*! PDIV - Postdivider divider ratio (P-divider) */ #define SCG_SPLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PDIV_SHIFT)) & SCG_SPLLPDIV_PDIV_MASK) #define SCG_SPLLPDIV_PREQ_MASK (0x80000000U) #define SCG_SPLLPDIV_PREQ_SHIFT (31U) /*! PREQ - Postdivider ratio change request * 0b0..Postdivider ratio change is not requested * 0b1..Postdivider ratio change is requested */ #define SCG_SPLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PREQ_SHIFT)) & SCG_SPLLPDIV_PREQ_MASK) /*! @} */ /*! @name SPLLLOCK_CNFG - SPLL LOCK Configuration Register */ /*! @{ */ #define SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) #define SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) /*! LOCK_TIME - Configures the number of reference clocks to count before SPLL is considered locked. */ #define SCG_SPLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK) /*! @} */ /*! @name SPLLSSCGSTAT - SPLL SSCG Status Register */ /*! @{ */ #define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) #define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) /*! SS_MDIV_ACK - SS_MDIV change acknowledge * 0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL * 0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL */ #define SCG_SPLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK) /*! @} */ /*! @name SPLLSSCG0 - SPLL Spread Spectrum Control 0 Register */ /*! @{ */ #define SCG_SPLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) #define SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT (0U) /*! SS_MDIV_LSB - SS_MDIV[31:0] */ #define SCG_SPLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_SPLLSSCG0_SS_MDIV_LSB_MASK) /*! @} */ /*! @name SPLLSSCG1 - SPLL Spread Spectrum Control 1 Register */ /*! @{ */ #define SCG_SPLLSSCG1_SS_MDIV_MSB_MASK (0x1U) #define SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT (0U) /*! SS_MDIV_MSB - SS_MDIV[32] */ #define SCG_SPLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) #define SCG_SPLLSSCG1_SS_MDIV_REQ_MASK (0x2U) #define SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT (1U) /*! SS_MDIV_REQ - SS_MDIV[32:0] change request. * 0b0..SS_MDIV change is not requested * 0b1..SS_MDIV change is requested */ #define SCG_SPLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_REQ_MASK) #define SCG_SPLLSSCG1_MF_MASK (0x1CU) #define SCG_SPLLSSCG1_MF_SHIFT (2U) /*! MF - Modulation Frequency Control */ #define SCG_SPLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MF_SHIFT)) & SCG_SPLLSSCG1_MF_MASK) #define SCG_SPLLSSCG1_MR_MASK (0xE0U) #define SCG_SPLLSSCG1_MR_SHIFT (5U) /*! MR - Modulation Depth Control */ #define SCG_SPLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MR_SHIFT)) & SCG_SPLLSSCG1_MR_MASK) #define SCG_SPLLSSCG1_MC_MASK (0x300U) #define SCG_SPLLSSCG1_MC_SHIFT (8U) /*! MC - Modulation Waveform Control * 0b00..MC[1:0] no compensation * 0b11..MC[1:0] maximum compensation */ #define SCG_SPLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MC_SHIFT)) & SCG_SPLLSSCG1_MC_MASK) #define SCG_SPLLSSCG1_DITHER_MASK (0x400U) #define SCG_SPLLSSCG1_DITHER_SHIFT (10U) /*! DITHER - Dither Enable * 0b0..Dither is not enabled * 0b1..Dither is enabled */ #define SCG_SPLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_DITHER_SHIFT)) & SCG_SPLLSSCG1_DITHER_MASK) #define SCG_SPLLSSCG1_SEL_SS_MDIV_MASK (0x800U) #define SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT (11U) /*! SEL_SS_MDIV - SS_MDIV select. * 0b0..Feedback divider ratio is MDIV[15:0] * 0b1..Feedback divider ratio is SS_MDIV[32:0] */ #define SCG_SPLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) #define SCG_SPLLSSCG1_SS_PD_MASK (0x80000000U) #define SCG_SPLLSSCG1_SS_PD_SHIFT (31U) /*! SS_PD - SSCG Power Down * 0b0..SSCG is powered on * 0b1..SSCG is powered off */ #define SCG_SPLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_PD_SHIFT)) & SCG_SPLLSSCG1_SS_PD_MASK) /*! @} */ /*! @name SPLL_OVRD - SPLL Override Register */ /*! @{ */ #define SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK (0x1U) #define SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT (0U) /*! SPLLPWREN_OVRD - SPLL Power Enable Override if SPLL_OVRD_EN=1 * 0b0..SPLL clock is powered off * 0b1..SPLL clock is powered on */ #define SCG_SPLL_OVRD_SPLLPWREN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK) #define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK (0x2U) #define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT (1U) /*! SPLLCLKEN_OVRD - SPLL Clock Enable Override if SPLL_OVRD_EN=1 * 0b0..SPLL clock is disabled * 0b1..SPLL clock is enabled */ #define SCG_SPLL_OVRD_SPLLCLKEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK) #define SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK (0x80000000U) #define SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT (31U) /*! SPLL_OVRD_EN - SPLL Override Enable * 0b0..SPLL override is disabled * 0b1..SPLL override is enabled */ #define SCG_SPLL_OVRD_SPLL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT)) & SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK) /*! @} */ /*! @name UPLLCSR - UPLL Control Status Register */ /*! @{ */ #define SCG_UPLLCSR_UPLLCM_MASK (0x10000U) #define SCG_UPLLCSR_UPLLCM_SHIFT (16U) /*! UPLLCM - UPLL Clock Monitor * 0b0..UPLL Clock Monitor is disabled * 0b1..UPLL Clock Monitor is enabled */ #define SCG_UPLLCSR_UPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCM_SHIFT)) & SCG_UPLLCSR_UPLLCM_MASK) #define SCG_UPLLCSR_UPLLCMRE_MASK (0x20000U) #define SCG_UPLLCSR_UPLLCMRE_SHIFT (17U) /*! UPLLCMRE - UPLL Clock Monitor Reset Enable * 0b0..Clock monitor generates an interrupt when an error is detected * 0b1..Clock monitor generates a reset when an error is detected */ #define SCG_UPLLCSR_UPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCMRE_SHIFT)) & SCG_UPLLCSR_UPLLCMRE_MASK) #define SCG_UPLLCSR_LK_MASK (0x800000U) #define SCG_UPLLCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written * 0b1..Control Status Register cannot be written */ #define SCG_UPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_LK_SHIFT)) & SCG_UPLLCSR_LK_MASK) #define SCG_UPLLCSR_UPLLVLD_MASK (0x1000000U) #define SCG_UPLLCSR_UPLLVLD_SHIFT (24U) /*! UPLLVLD - UPLL Valid * 0b0..UPLL is not enabled or clock is not valid * 0b1..UPLL is enabled and output clock is valid */ #define SCG_UPLLCSR_UPLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVLD_SHIFT)) & SCG_UPLLCSR_UPLLVLD_MASK) #define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) #define SCG_UPLLCSR_UPLLSEL_SHIFT (25U) /*! UPLLSEL - UPLL Selected * 0b0..UPLL is not the system clock source * 0b1..UPLL is the system clock source */ #define SCG_UPLLCSR_UPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK) #define SCG_UPLLCSR_UPLLERR_MASK (0x4000000U) #define SCG_UPLLCSR_UPLLERR_SHIFT (26U) /*! UPLLERR - UPLL Clock Error * 0b0..UPLL Clock Monitor is disabled or has not detected an error * 0b1..UPLL Clock Monitor is enabled and detected an error */ #define SCG_UPLLCSR_UPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLERR_SHIFT)) & SCG_UPLLCSR_UPLLERR_MASK) /*! @} */ /*! @name LDOCSR - LDO Control and Status Register */ /*! @{ */ #define SCG_LDOCSR_LDOEN_MASK (0x1U) #define SCG_LDOCSR_LDOEN_SHIFT (0U) /*! LDOEN - LDO Enable * 0b0..LDO is disabled * 0b1..LDO is enabled */ #define SCG_LDOCSR_LDOEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOEN_SHIFT)) & SCG_LDOCSR_LDOEN_MASK) #define SCG_LDOCSR_VOUT_SEL_MASK (0xEU) #define SCG_LDOCSR_VOUT_SEL_SHIFT (1U) /*! VOUT_SEL - LDO output voltage select * 0b000..VOUT = 1V * 0b001..VOUT = 1V * 0b010..VOUT = 1V * 0b011..VOUT = 1.05V * 0b100..VOUT = 1.1V * 0b101..VOUT = 1.15V * 0b110..VOUT = 1.2V * 0b111..VOUT = 1.25V */ #define SCG_LDOCSR_VOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_SEL_SHIFT)) & SCG_LDOCSR_VOUT_SEL_MASK) #define SCG_LDOCSR_LDOBYPASS_MASK (0x10U) #define SCG_LDOCSR_LDOBYPASS_SHIFT (4U) /*! LDOBYPASS - LDO Bypass * 0b0..LDO is not bypassed * 0b1..LDO is bypassed */ #define SCG_LDOCSR_LDOBYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOBYPASS_SHIFT)) & SCG_LDOCSR_LDOBYPASS_MASK) #define SCG_LDOCSR_VOUT_OK_MASK (0x80000000U) #define SCG_LDOCSR_VOUT_OK_SHIFT (31U) /*! VOUT_OK - LDO VOUT OK Inform. * 0b0..LDO output VOUT is not OK * 0b1..LDO output VOUT is OK */ #define SCG_LDOCSR_VOUT_OK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK) /*! @} */ /*! * @} */ /* end of group SCG_Register_Masks */ /* SCG - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral SCG0 base address */ #define SCG0_BASE (0x50044000u) /** Peripheral SCG0 base address */ #define SCG0_BASE_NS (0x40044000u) /** Peripheral SCG0 base pointer */ #define SCG0 ((SCG_Type *)SCG0_BASE) /** Peripheral SCG0 base pointer */ #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) /** Array initializer of SCG peripheral base addresses */ #define SCG_BASE_ADDRS { SCG0_BASE } /** Array initializer of SCG peripheral base pointers */ #define SCG_BASE_PTRS { SCG0 } /** Array initializer of SCG peripheral base addresses */ #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } /** Array initializer of SCG peripheral base pointers */ #define SCG_BASE_PTRS_NS { SCG0_NS } #else /** Peripheral SCG0 base address */ #define SCG0_BASE (0x40044000u) /** Peripheral SCG0 base pointer */ #define SCG0 ((SCG_Type *)SCG0_BASE) /** Array initializer of SCG peripheral base addresses */ #define SCG_BASE_ADDRS { SCG0_BASE } /** Array initializer of SCG peripheral base pointers */ #define SCG_BASE_PTRS { SCG0 } #endif /*! * @} */ /* end of group SCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SCT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer * @{ */ /** SCT - Register Layout Typedef */ typedef struct { __IO uint32_t CONFIG; /**< SCT Configuration, offset: 0x0 */ union { /* offset: 0x4 */ struct { /* offset: 0x4 */ __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ } CTRL_ACCESS16BIT; __IO uint32_t CTRL; /**< SCT Control, offset: 0x4 */ }; union { /* offset: 0x8 */ struct { /* offset: 0x8 */ __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ } LIMIT_ACCESS16BIT; __IO uint32_t LIMIT; /**< SCT Limit Event Select, offset: 0x8 */ }; union { /* offset: 0xC */ struct { /* offset: 0xC */ __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ } HALT_ACCESS16BIT; __IO uint32_t HALT; /**< Halt Event Select, offset: 0xC */ }; union { /* offset: 0x10 */ struct { /* offset: 0x10 */ __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ } STOP_ACCESS16BIT; __IO uint32_t STOP; /**< Stop Event Select, offset: 0x10 */ }; union { /* offset: 0x14 */ struct { /* offset: 0x14 */ __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ } START_ACCESS16BIT; __IO uint32_t START; /**< Start Event Select, offset: 0x14 */ }; __IO uint32_t DITHER; /**< Dither Condition, offset: 0x18 */ uint8_t RESERVED_0[36]; union { /* offset: 0x40 */ struct { /* offset: 0x40 */ __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ } COUNT_ACCESS16BIT; __IO uint32_t COUNT; /**< Counter Value, offset: 0x40 */ }; union { /* offset: 0x44 */ struct { /* offset: 0x44 */ __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ } STATE_ACCESS16BIT; __IO uint32_t STATE; /**< State Variable, offset: 0x44 */ }; __I uint32_t INPUT; /**< Input State, offset: 0x48 */ union { /* offset: 0x4C */ struct { /* offset: 0x4C */ __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ } REGMODE_ACCESS16BIT; __IO uint32_t REGMODE; /**< Match and Capture Register Mode, offset: 0x4C */ }; __IO uint32_t OUTPUT; /**< Output State, offset: 0x50 */ __IO uint32_t OUTPUTDIRCTRL; /**< Output Counter Direction Control, offset: 0x54 */ __IO uint32_t RES; /**< Output Conflict Resolution, offset: 0x58 */ __IO uint32_t DMAREQ0; /**< DMA Request 0, offset: 0x5C */ __IO uint32_t DMAREQ1; /**< DMA Request 1, offset: 0x60 */ uint8_t RESERVED_1[140]; __IO uint32_t EVEN; /**< Event Interrupt Enable, offset: 0xF0 */ __IO uint32_t EVFLAG; /**< Event Flag, offset: 0xF4 */ __IO uint32_t CONEN; /**< Conflict Interrupt Enable, offset: 0xF8 */ __IO uint32_t CONFLAG; /**< Conflict Flag, offset: 0xFC */ union { /* offset: 0x100 */ union { /* offset: 0x100, array step: 0x4 */ struct { /* offset: 0x100, array step: 0x4 */ __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ } CAP_ACCESS16BIT[16]; __IO uint32_t CAP[16]; /**< Capture Value, array offset: 0x100, array step: 0x4 */ }; union { /* offset: 0x100, array step: 0x4 */ struct { /* offset: 0x100, array step: 0x4 */ __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ } MATCH_ACCESS16BIT[16]; __IO uint32_t MATCH[16]; /**< Match Value, array offset: 0x100, array step: 0x4 */ }; }; __IO uint32_t FRACMAT[6]; /**< Fractional Match, array offset: 0x140, array step: 0x4 */ uint8_t RESERVED_2[168]; union { /* offset: 0x200 */ union { /* offset: 0x200, array step: 0x4 */ struct { /* offset: 0x200, array step: 0x4 */ __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ } CAPCTRL_ACCESS16BIT[16]; __IO uint32_t CAPCTRL[16]; /**< Capture Control, array offset: 0x200, array step: 0x4 */ }; union { /* offset: 0x200, array step: 0x4 */ struct { /* offset: 0x200, array step: 0x4 */ __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ } MATCHREL_ACCESS16BIT[16]; __IO uint32_t MATCHREL[16]; /**< Match Reload Value, array offset: 0x200, array step: 0x4 */ }; }; __IO uint32_t FRACMATREL[6]; /**< Fractional Match Reload, array offset: 0x240, array step: 0x4 */ uint8_t RESERVED_3[168]; struct { /* offset: 0x300, array step: 0x8 */ __IO uint32_t STATE; /**< Event n State, array offset: 0x300, array step: 0x8 */ __IO uint32_t CTRL; /**< Event n Control, array offset: 0x304, array step: 0x8 */ } EV[16]; uint8_t RESERVED_4[384]; struct { /* offset: 0x500, array step: 0x8 */ __IO uint32_t SET; /**< Output n Set, array offset: 0x500, array step: 0x8 */ __IO uint32_t CLR; /**< Output n Clear, array offset: 0x504, array step: 0x8 */ } OUT[10]; } SCT_Type; /* ---------------------------------------------------------------------------- -- SCT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SCT_Register_Masks SCT Register Masks * @{ */ /*! @name CONFIG - SCT Configuration */ /*! @{ */ #define SCT_CONFIG_UNIFY_MASK (0x1U) #define SCT_CONFIG_UNIFY_SHIFT (0U) /*! UNIFY - SCT Operation * 0b0..Dual counters, COUNTER_L and COUNTER_H * 0b1..Unified counter */ #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) #define SCT_CONFIG_CLKMODE_MASK (0x6U) #define SCT_CONFIG_CLKMODE_SHIFT (1U) /*! CLKMODE - SCT Clock Mode * 0b00..System Clock mode * 0b01..Sampled System Clock mode * 0b10..SCT Input Clock mode * 0b11..Asynchronous mode */ #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) #define SCT_CONFIG_CKSEL_MASK (0x78U) #define SCT_CONFIG_CKSEL_SHIFT (3U) /*! CKSEL - SCT Clock Select * 0b0000..Rising edges on input 0 * 0b0001..Falling edges on input 0 * 0b0010..Rising edges on input 1 * 0b0011..Falling edges on input 1 * 0b0100..Rising edges on input 2 * 0b0101..Falling edges on input 2 * 0b0110..Rising edges on input 3 * 0b0111..Falling edges on input 3 * 0b1000..Rising edges on input 4 * 0b1001..Falling edges on input 4 * 0b1010..Rising edges on input 5 * 0b1011..Falling edges on input 5 * 0b1100..Rising edges on input 6 * 0b1101..Falling edges on input 6 * 0b1110..Rising edges on input 7 * 0b1111..Falling edges on input 7 */ #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) #define SCT_CONFIG_NORELOAD_L_MASK (0x80U) #define SCT_CONFIG_NORELOAD_L_SHIFT (7U) /*! NORELOAD_L - No Reload Lower Match * 0b0..Reloaded * 0b1..Not reloaded */ #define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) #define SCT_CONFIG_NORELOAD_H_MASK (0x100U) #define SCT_CONFIG_NORELOAD_H_SHIFT (8U) /*! NORELOAD_H - No Reload Higher Match * 0b0..Reloaded * 0b1..Not reloaded */ #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) #define SCT_CONFIG_INSYNC_MASK (0x1FE00U) #define SCT_CONFIG_INSYNC_SHIFT (9U) /*! INSYNC - Input Synchronization */ #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) /*! AUTOLIMIT_L - Auto Limit Lower * 0b0..Disables * 0b1..Enables */ #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) /*! AUTOLIMIT_H - Auto Limit Higher * 0b0..Disables * 0b1..Enables */ #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) /*! @} */ /*! @name CTRLL - SCT_CTRLL register */ /*! @{ */ #define SCT_CTRLL_DOWN_L_MASK (0x1U) #define SCT_CTRLL_DOWN_L_SHIFT (0U) /*! DOWN_L - Down Counter Low * 0b0..Up * 0b1..Down */ #define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) #define SCT_CTRLL_STOP_L_MASK (0x2U) #define SCT_CTRLL_STOP_L_SHIFT (1U) /*! STOP_L - Stop Counter Low * 0b0..Disabled * 0b1..Enabled */ #define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) #define SCT_CTRLL_HALT_L_MASK (0x4U) #define SCT_CTRLL_HALT_L_SHIFT (2U) /*! HALT_L - Halt Counter Low * 0b0..Disabled * 0b1..Enabled */ #define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) #define SCT_CTRLL_CLRCTR_L_MASK (0x8U) #define SCT_CTRLL_CLRCTR_L_SHIFT (3U) /*! CLRCTR_L - Clear Counter Low */ #define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) #define SCT_CTRLL_BIDIR_L_MASK (0x10U) #define SCT_CTRLL_BIDIR_L_SHIFT (4U) /*! BIDIR_L - Bidirectional Select Low * 0b0..Up * 0b1..Up-down */ #define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) #define SCT_CTRLL_PRE_L_MASK (0x1FE0U) #define SCT_CTRLL_PRE_L_SHIFT (5U) /*! PRE_L - Prescaler for Low Counter */ #define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) /*! @} */ /*! @name CTRLH - SCT_CTRLH register */ /*! @{ */ #define SCT_CTRLH_DOWN_H_MASK (0x1U) #define SCT_CTRLH_DOWN_H_SHIFT (0U) /*! DOWN_H - Down Counter High * 0b0..Up * 0b1..Down */ #define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) #define SCT_CTRLH_STOP_H_MASK (0x2U) #define SCT_CTRLH_STOP_H_SHIFT (1U) /*! STOP_H - Stop Counter High * 0b0..Disabled * 0b1..Enabled */ #define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) #define SCT_CTRLH_HALT_H_MASK (0x4U) #define SCT_CTRLH_HALT_H_SHIFT (2U) /*! HALT_H - Halt Counter High * 0b0..Disable * 0b1..Enable */ #define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) #define SCT_CTRLH_CLRCTR_H_MASK (0x8U) #define SCT_CTRLH_CLRCTR_H_SHIFT (3U) /*! CLRCTR_H - Clear Counter High */ #define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) #define SCT_CTRLH_BIDIR_H_MASK (0x10U) #define SCT_CTRLH_BIDIR_H_SHIFT (4U) /*! BIDIR_H - Bidirectional Select High * 0b0..Up * 0b1..Up-down */ #define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) #define SCT_CTRLH_PRE_H_MASK (0x1FE0U) #define SCT_CTRLH_PRE_H_SHIFT (5U) /*! PRE_H - Prescaler for High Counter */ #define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) /*! @} */ /*! @name CTRL - SCT Control */ /*! @{ */ #define SCT_CTRL_DOWN_L_MASK (0x1U) #define SCT_CTRL_DOWN_L_SHIFT (0U) /*! DOWN_L - Down Counter Low * 0b0..Up * 0b1..Down */ #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) #define SCT_CTRL_STOP_L_MASK (0x2U) #define SCT_CTRL_STOP_L_SHIFT (1U) /*! STOP_L - Stop Counter Low * 0b0..Disabled * 0b1..Enabled */ #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) #define SCT_CTRL_HALT_L_MASK (0x4U) #define SCT_CTRL_HALT_L_SHIFT (2U) /*! HALT_L - Halt Counter Low * 0b0..Disabled * 0b1..Enabled */ #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) #define SCT_CTRL_CLRCTR_L_MASK (0x8U) #define SCT_CTRL_CLRCTR_L_SHIFT (3U) /*! CLRCTR_L - Clear Counter Low */ #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) #define SCT_CTRL_BIDIR_L_MASK (0x10U) #define SCT_CTRL_BIDIR_L_SHIFT (4U) /*! BIDIR_L - Bidirectional Select Low * 0b0..Up * 0b1..Up-down */ #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) #define SCT_CTRL_PRE_L_MASK (0x1FE0U) #define SCT_CTRL_PRE_L_SHIFT (5U) /*! PRE_L - Prescaler for Low Counter */ #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) #define SCT_CTRL_DOWN_H_MASK (0x10000U) #define SCT_CTRL_DOWN_H_SHIFT (16U) /*! DOWN_H - Down Counter High * 0b0..Up * 0b1..Down */ #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) #define SCT_CTRL_STOP_H_MASK (0x20000U) #define SCT_CTRL_STOP_H_SHIFT (17U) /*! STOP_H - Stop Counter High * 0b0..Disabled * 0b1..Enabled */ #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) #define SCT_CTRL_HALT_H_MASK (0x40000U) #define SCT_CTRL_HALT_H_SHIFT (18U) /*! HALT_H - Halt Counter High * 0b0..Disable * 0b1..Enable */ #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) #define SCT_CTRL_CLRCTR_H_MASK (0x80000U) #define SCT_CTRL_CLRCTR_H_SHIFT (19U) /*! CLRCTR_H - Clear Counter High */ #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) #define SCT_CTRL_BIDIR_H_MASK (0x100000U) #define SCT_CTRL_BIDIR_H_SHIFT (20U) /*! BIDIR_H - Bidirectional Select High * 0b0..Up * 0b1..Up-down */ #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) #define SCT_CTRL_PRE_H_SHIFT (21U) /*! PRE_H - Prescaler for High Counter */ #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) /*! @} */ /*! @name LIMITL - SCT_LIMITL register */ /*! @{ */ #define SCT_LIMITL_LIMITL_MASK (0xFFFFU) #define SCT_LIMITL_LIMITL_SHIFT (0U) #define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) /*! @} */ /*! @name LIMITH - SCT_LIMITH register */ /*! @{ */ #define SCT_LIMITH_LIMITH_MASK (0xFFFFU) #define SCT_LIMITH_LIMITH_SHIFT (0U) #define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) /*! @} */ /*! @name LIMIT - SCT Limit Event Select */ /*! @{ */ #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) /*! LIMMSK_L - Limit Event Counter Low */ #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) /*! LIMMSK_H - Limit Event Counter High */ #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) /*! @} */ /*! @name HALTL - SCT_HALTL register */ /*! @{ */ #define SCT_HALTL_HALTL_MASK (0xFFFFU) #define SCT_HALTL_HALTL_SHIFT (0U) #define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) /*! @} */ /*! @name HALTH - SCT_HALTH register */ /*! @{ */ #define SCT_HALTH_HALTH_MASK (0xFFFFU) #define SCT_HALTH_HALTH_SHIFT (0U) #define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) /*! @} */ /*! @name HALT - Halt Event Select */ /*! @{ */ #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) #define SCT_HALT_HALTMSK_L_SHIFT (0U) /*! HALTMSK_L - Halt Event Low */ #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) #define SCT_HALT_HALTMSK_H_SHIFT (16U) /*! HALTMSK_H - Halt Event High */ #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) /*! @} */ /*! @name STOPL - SCT_STOPL register */ /*! @{ */ #define SCT_STOPL_STOPL_MASK (0xFFFFU) #define SCT_STOPL_STOPL_SHIFT (0U) #define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) /*! @} */ /*! @name STOPH - SCT_STOPH register */ /*! @{ */ #define SCT_STOPH_STOPH_MASK (0xFFFFU) #define SCT_STOPH_STOPH_SHIFT (0U) #define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) /*! @} */ /*! @name STOP - Stop Event Select */ /*! @{ */ #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) #define SCT_STOP_STOPMSK_L_SHIFT (0U) /*! STOPMSK_L - Stop Event Low */ #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) #define SCT_STOP_STOPMSK_H_SHIFT (16U) /*! STOPMSK_H - Stop Event High */ #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) /*! @} */ /*! @name STARTL - SCT_STARTL register */ /*! @{ */ #define SCT_STARTL_STARTL_MASK (0xFFFFU) #define SCT_STARTL_STARTL_SHIFT (0U) #define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) /*! @} */ /*! @name STARTH - SCT_STARTH register */ /*! @{ */ #define SCT_STARTH_STARTH_MASK (0xFFFFU) #define SCT_STARTH_STARTH_SHIFT (0U) #define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) /*! @} */ /*! @name START - Start Event Select */ /*! @{ */ #define SCT_START_STARTMSK_L_MASK (0xFFFFU) #define SCT_START_STARTMSK_L_SHIFT (0U) /*! STARTMSK_L - Start Event Low */ #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) #define SCT_START_STARTMSK_H_SHIFT (16U) /*! STARTMSK_H - Start Event High */ #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) /*! @} */ /*! @name DITHER - Dither Condition */ /*! @{ */ #define SCT_DITHER_DITHER_L_MASK (0xFFFFU) #define SCT_DITHER_DITHER_L_SHIFT (0U) /*! DITHER_L - Dither Low */ #define SCT_DITHER_DITHER_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_L_SHIFT)) & SCT_DITHER_DITHER_L_MASK) #define SCT_DITHER_DITHER_H_MASK (0xFFFF0000U) #define SCT_DITHER_DITHER_H_SHIFT (16U) /*! DITHER_H - Dither High */ #define SCT_DITHER_DITHER_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_H_SHIFT)) & SCT_DITHER_DITHER_H_MASK) /*! @} */ /*! @name COUNTL - SCT_COUNTL register */ /*! @{ */ #define SCT_COUNTL_COUNTL_MASK (0xFFFFU) #define SCT_COUNTL_COUNTL_SHIFT (0U) #define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) /*! @} */ /*! @name COUNTH - SCT_COUNTH register */ /*! @{ */ #define SCT_COUNTH_COUNTH_MASK (0xFFFFU) #define SCT_COUNTH_COUNTH_SHIFT (0U) #define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) /*! @} */ /*! @name COUNT - Counter Value */ /*! @{ */ #define SCT_COUNT_CTR_L_MASK (0xFFFFU) #define SCT_COUNT_CTR_L_SHIFT (0U) /*! CTR_L - Counter Low */ #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) #define SCT_COUNT_CTR_H_SHIFT (16U) /*! CTR_H - Counter High */ #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) /*! @} */ /*! @name STATEL - SCT_STATEL register */ /*! @{ */ #define SCT_STATEL_STATEL_MASK (0xFFFFU) #define SCT_STATEL_STATEL_SHIFT (0U) #define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) /*! @} */ /*! @name STATEH - SCT_STATEH register */ /*! @{ */ #define SCT_STATEH_STATEH_MASK (0xFFFFU) #define SCT_STATEH_STATEH_SHIFT (0U) #define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) /*! @} */ /*! @name STATE - State Variable */ /*! @{ */ #define SCT_STATE_STATE_L_MASK (0x1FU) #define SCT_STATE_STATE_L_SHIFT (0U) /*! STATE_L - State Variable Low */ #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) #define SCT_STATE_STATE_H_MASK (0x1F0000U) #define SCT_STATE_STATE_H_SHIFT (16U) /*! STATE_H - State Variable High */ #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) /*! @} */ /*! @name INPUT - Input State */ /*! @{ */ #define SCT_INPUT_AIN0_MASK (0x1U) #define SCT_INPUT_AIN0_SHIFT (0U) /*! AIN0 - Input 0 state */ #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) #define SCT_INPUT_AIN1_MASK (0x2U) #define SCT_INPUT_AIN1_SHIFT (1U) /*! AIN1 - Input 1 state */ #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) #define SCT_INPUT_AIN2_MASK (0x4U) #define SCT_INPUT_AIN2_SHIFT (2U) /*! AIN2 - Input 2 state */ #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) #define SCT_INPUT_AIN3_MASK (0x8U) #define SCT_INPUT_AIN3_SHIFT (3U) /*! AIN3 - Input 3 state */ #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) #define SCT_INPUT_AIN4_MASK (0x10U) #define SCT_INPUT_AIN4_SHIFT (4U) /*! AIN4 - Input 4 state */ #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) #define SCT_INPUT_AIN5_MASK (0x20U) #define SCT_INPUT_AIN5_SHIFT (5U) /*! AIN5 - Input 5 state */ #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) #define SCT_INPUT_AIN6_MASK (0x40U) #define SCT_INPUT_AIN6_SHIFT (6U) /*! AIN6 - Input 6 state */ #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) #define SCT_INPUT_AIN7_MASK (0x80U) #define SCT_INPUT_AIN7_SHIFT (7U) /*! AIN7 - Input 7 state */ #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) #define SCT_INPUT_AIN8_MASK (0x100U) #define SCT_INPUT_AIN8_SHIFT (8U) /*! AIN8 - Input 8 state */ #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) #define SCT_INPUT_AIN9_MASK (0x200U) #define SCT_INPUT_AIN9_SHIFT (9U) /*! AIN9 - Input 9 state */ #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) #define SCT_INPUT_AIN10_MASK (0x400U) #define SCT_INPUT_AIN10_SHIFT (10U) /*! AIN10 - Input 10 state */ #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) #define SCT_INPUT_AIN11_MASK (0x800U) #define SCT_INPUT_AIN11_SHIFT (11U) /*! AIN11 - Input 11 state */ #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) #define SCT_INPUT_AIN12_MASK (0x1000U) #define SCT_INPUT_AIN12_SHIFT (12U) /*! AIN12 - Input 12 state */ #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) #define SCT_INPUT_AIN13_MASK (0x2000U) #define SCT_INPUT_AIN13_SHIFT (13U) /*! AIN13 - Input 13 state */ #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) #define SCT_INPUT_AIN14_MASK (0x4000U) #define SCT_INPUT_AIN14_SHIFT (14U) /*! AIN14 - Input 14 state */ #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) #define SCT_INPUT_AIN15_MASK (0x8000U) #define SCT_INPUT_AIN15_SHIFT (15U) /*! AIN15 - Input 15 state */ #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) #define SCT_INPUT_SIN0_MASK (0x10000U) #define SCT_INPUT_SIN0_SHIFT (16U) /*! SIN0 - Input 0 state */ #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) #define SCT_INPUT_SIN1_MASK (0x20000U) #define SCT_INPUT_SIN1_SHIFT (17U) /*! SIN1 - Input 1 state */ #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) #define SCT_INPUT_SIN2_MASK (0x40000U) #define SCT_INPUT_SIN2_SHIFT (18U) /*! SIN2 - Input 2 state */ #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) #define SCT_INPUT_SIN3_MASK (0x80000U) #define SCT_INPUT_SIN3_SHIFT (19U) /*! SIN3 - Input 3 state */ #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) #define SCT_INPUT_SIN4_MASK (0x100000U) #define SCT_INPUT_SIN4_SHIFT (20U) /*! SIN4 - Input 4 state */ #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) #define SCT_INPUT_SIN5_MASK (0x200000U) #define SCT_INPUT_SIN5_SHIFT (21U) /*! SIN5 - Input 5 state */ #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) #define SCT_INPUT_SIN6_MASK (0x400000U) #define SCT_INPUT_SIN6_SHIFT (22U) /*! SIN6 - Input 6 state */ #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) #define SCT_INPUT_SIN7_MASK (0x800000U) #define SCT_INPUT_SIN7_SHIFT (23U) /*! SIN7 - Input 7 state */ #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) #define SCT_INPUT_SIN8_MASK (0x1000000U) #define SCT_INPUT_SIN8_SHIFT (24U) /*! SIN8 - Input 8 state */ #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) #define SCT_INPUT_SIN9_MASK (0x2000000U) #define SCT_INPUT_SIN9_SHIFT (25U) /*! SIN9 - Input 9 state */ #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) #define SCT_INPUT_SIN10_MASK (0x4000000U) #define SCT_INPUT_SIN10_SHIFT (26U) /*! SIN10 - Input 10 state */ #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) #define SCT_INPUT_SIN11_MASK (0x8000000U) #define SCT_INPUT_SIN11_SHIFT (27U) /*! SIN11 - Input 11 state */ #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) #define SCT_INPUT_SIN12_MASK (0x10000000U) #define SCT_INPUT_SIN12_SHIFT (28U) /*! SIN12 - Input 12 state */ #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) #define SCT_INPUT_SIN13_MASK (0x20000000U) #define SCT_INPUT_SIN13_SHIFT (29U) /*! SIN13 - Input 13 state */ #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) #define SCT_INPUT_SIN14_MASK (0x40000000U) #define SCT_INPUT_SIN14_SHIFT (30U) /*! SIN14 - Input 14 state */ #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) #define SCT_INPUT_SIN15_MASK (0x80000000U) #define SCT_INPUT_SIN15_SHIFT (31U) /*! SIN15 - Input 15 state */ #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) /*! @} */ /*! @name REGMODEL - SCT_REGMODEL register */ /*! @{ */ #define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) #define SCT_REGMODEL_REGMODEL_SHIFT (0U) /*! REGMODEL * 0b0..Match * 0b1..Capture */ #define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) #define SCT_REGMODEL_REGMOD_L_MASK (0xFFFFU) #define SCT_REGMODEL_REGMOD_L_SHIFT (0U) #define SCT_REGMODEL_REGMOD_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_L_SHIFT)) & SCT_REGMODEL_REGMOD_L_MASK) #define SCT_REGMODEL_REGMOD_H_MASK (0xFFFF0000U) #define SCT_REGMODEL_REGMOD_H_SHIFT (16U) #define SCT_REGMODEL_REGMOD_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_H_SHIFT)) & SCT_REGMODEL_REGMOD_H_MASK) /*! @} */ /*! @name REGMODEH - SCT_REGMODEH register */ /*! @{ */ #define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) #define SCT_REGMODEH_REGMODEH_SHIFT (0U) /*! REGMODEH * 0b0..Match * 0b1..Capture */ #define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) #define SCT_REGMODEH_REGMOD_L_MASK (0xFFFFU) #define SCT_REGMODEH_REGMOD_L_SHIFT (0U) #define SCT_REGMODEH_REGMOD_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_L_SHIFT)) & SCT_REGMODEH_REGMOD_L_MASK) #define SCT_REGMODEH_REGMOD_H_MASK (0xFFFF0000U) #define SCT_REGMODEH_REGMOD_H_SHIFT (16U) #define SCT_REGMODEH_REGMOD_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_H_SHIFT)) & SCT_REGMODEH_REGMOD_H_MASK) /*! @} */ /*! @name REGMODE - Match and Capture Register Mode */ /*! @{ */ #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) #define SCT_REGMODE_REGMOD_L_SHIFT (0U) #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) #define SCT_REGMODE_REGMOD_L0_MASK (0x1U) #define SCT_REGMODE_REGMOD_L0_SHIFT (0U) /*! REGMOD_L0 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L0(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK) #define SCT_REGMODE_REGMOD_L1_MASK (0x2U) #define SCT_REGMODE_REGMOD_L1_SHIFT (1U) /*! REGMOD_L1 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L1(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK) #define SCT_REGMODE_REGMOD_L2_MASK (0x4U) #define SCT_REGMODE_REGMOD_L2_SHIFT (2U) /*! REGMOD_L2 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L2(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK) #define SCT_REGMODE_REGMOD_L3_MASK (0x8U) #define SCT_REGMODE_REGMOD_L3_SHIFT (3U) /*! REGMOD_L3 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L3(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK) #define SCT_REGMODE_REGMOD_L4_MASK (0x10U) #define SCT_REGMODE_REGMOD_L4_SHIFT (4U) /*! REGMOD_L4 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L4(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK) #define SCT_REGMODE_REGMOD_L5_MASK (0x20U) #define SCT_REGMODE_REGMOD_L5_SHIFT (5U) /*! REGMOD_L5 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L5(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK) #define SCT_REGMODE_REGMOD_L6_MASK (0x40U) #define SCT_REGMODE_REGMOD_L6_SHIFT (6U) /*! REGMOD_L6 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L6(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK) #define SCT_REGMODE_REGMOD_L7_MASK (0x80U) #define SCT_REGMODE_REGMOD_L7_SHIFT (7U) /*! REGMOD_L7 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L7(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK) #define SCT_REGMODE_REGMOD_L8_MASK (0x100U) #define SCT_REGMODE_REGMOD_L8_SHIFT (8U) /*! REGMOD_L8 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L8(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK) #define SCT_REGMODE_REGMOD_L9_MASK (0x200U) #define SCT_REGMODE_REGMOD_L9_SHIFT (9U) /*! REGMOD_L9 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L9(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK) #define SCT_REGMODE_REGMOD_L10_MASK (0x400U) #define SCT_REGMODE_REGMOD_L10_SHIFT (10U) /*! REGMOD_L10 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L10(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK) #define SCT_REGMODE_REGMOD_L11_MASK (0x800U) #define SCT_REGMODE_REGMOD_L11_SHIFT (11U) /*! REGMOD_L11 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L11(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK) #define SCT_REGMODE_REGMOD_L12_MASK (0x1000U) #define SCT_REGMODE_REGMOD_L12_SHIFT (12U) /*! REGMOD_L12 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L12(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK) #define SCT_REGMODE_REGMOD_L13_MASK (0x2000U) #define SCT_REGMODE_REGMOD_L13_SHIFT (13U) /*! REGMOD_L13 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L13(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK) #define SCT_REGMODE_REGMOD_L14_MASK (0x4000U) #define SCT_REGMODE_REGMOD_L14_SHIFT (14U) /*! REGMOD_L14 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L14(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK) #define SCT_REGMODE_REGMOD_L15_MASK (0x8000U) #define SCT_REGMODE_REGMOD_L15_SHIFT (15U) /*! REGMOD_L15 - Register Mode Low * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_L15(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK) #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) #define SCT_REGMODE_REGMOD_H_SHIFT (16U) #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) #define SCT_REGMODE_REGMOD_H0_MASK (0x10000U) #define SCT_REGMODE_REGMOD_H0_SHIFT (16U) /*! REGMOD_H0 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H0(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK) #define SCT_REGMODE_REGMOD_H1_MASK (0x20000U) #define SCT_REGMODE_REGMOD_H1_SHIFT (17U) /*! REGMOD_H1 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H1(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK) #define SCT_REGMODE_REGMOD_H2_MASK (0x40000U) #define SCT_REGMODE_REGMOD_H2_SHIFT (18U) /*! REGMOD_H2 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H2(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK) #define SCT_REGMODE_REGMOD_H3_MASK (0x80000U) #define SCT_REGMODE_REGMOD_H3_SHIFT (19U) /*! REGMOD_H3 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H3(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK) #define SCT_REGMODE_REGMOD_H4_MASK (0x100000U) #define SCT_REGMODE_REGMOD_H4_SHIFT (20U) /*! REGMOD_H4 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H4(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK) #define SCT_REGMODE_REGMOD_H5_MASK (0x200000U) #define SCT_REGMODE_REGMOD_H5_SHIFT (21U) /*! REGMOD_H5 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H5(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK) #define SCT_REGMODE_REGMOD_H6_MASK (0x400000U) #define SCT_REGMODE_REGMOD_H6_SHIFT (22U) /*! REGMOD_H6 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H6(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK) #define SCT_REGMODE_REGMOD_H7_MASK (0x800000U) #define SCT_REGMODE_REGMOD_H7_SHIFT (23U) /*! REGMOD_H7 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H7(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK) #define SCT_REGMODE_REGMOD_H8_MASK (0x1000000U) #define SCT_REGMODE_REGMOD_H8_SHIFT (24U) /*! REGMOD_H8 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H8(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK) #define SCT_REGMODE_REGMOD_H9_MASK (0x2000000U) #define SCT_REGMODE_REGMOD_H9_SHIFT (25U) /*! REGMOD_H9 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H9(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK) #define SCT_REGMODE_REGMOD_H10_MASK (0x4000000U) #define SCT_REGMODE_REGMOD_H10_SHIFT (26U) /*! REGMOD_H10 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H10(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK) #define SCT_REGMODE_REGMOD_H11_MASK (0x8000000U) #define SCT_REGMODE_REGMOD_H11_SHIFT (27U) /*! REGMOD_H11 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H11(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK) #define SCT_REGMODE_REGMOD_H12_MASK (0x10000000U) #define SCT_REGMODE_REGMOD_H12_SHIFT (28U) /*! REGMOD_H12 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H12(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK) #define SCT_REGMODE_REGMOD_H13_MASK (0x20000000U) #define SCT_REGMODE_REGMOD_H13_SHIFT (29U) /*! REGMOD_H13 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H13(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK) #define SCT_REGMODE_REGMOD_H14_MASK (0x40000000U) #define SCT_REGMODE_REGMOD_H14_SHIFT (30U) /*! REGMOD_H14 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H14(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK) #define SCT_REGMODE_REGMOD_H15_MASK (0x80000000U) #define SCT_REGMODE_REGMOD_H15_SHIFT (31U) /*! REGMOD_H15 - Register Mode High * 0b0..Match * 0b1..Capture */ #define SCT_REGMODE_REGMOD_H15(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK) /*! @} */ /*! @name OUTPUT - Output State */ /*! @{ */ #define SCT_OUTPUT_OUT0_MASK (0x1U) #define SCT_OUTPUT_OUT0_SHIFT (0U) /*! OUT0 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK) #define SCT_OUTPUT_OUT1_MASK (0x2U) #define SCT_OUTPUT_OUT1_SHIFT (1U) /*! OUT1 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK) #define SCT_OUTPUT_OUT2_MASK (0x4U) #define SCT_OUTPUT_OUT2_SHIFT (2U) /*! OUT2 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK) #define SCT_OUTPUT_OUT3_MASK (0x8U) #define SCT_OUTPUT_OUT3_SHIFT (3U) /*! OUT3 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK) #define SCT_OUTPUT_OUT4_MASK (0x10U) #define SCT_OUTPUT_OUT4_SHIFT (4U) /*! OUT4 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK) #define SCT_OUTPUT_OUT5_MASK (0x20U) #define SCT_OUTPUT_OUT5_SHIFT (5U) /*! OUT5 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK) #define SCT_OUTPUT_OUT6_MASK (0x40U) #define SCT_OUTPUT_OUT6_SHIFT (6U) /*! OUT6 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK) #define SCT_OUTPUT_OUT7_MASK (0x80U) #define SCT_OUTPUT_OUT7_SHIFT (7U) /*! OUT7 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK) #define SCT_OUTPUT_OUT8_MASK (0x100U) #define SCT_OUTPUT_OUT8_SHIFT (8U) /*! OUT8 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK) #define SCT_OUTPUT_OUT9_MASK (0x200U) #define SCT_OUTPUT_OUT9_SHIFT (9U) /*! OUT9 - Output Low and High * 0b0..Forces the corresponding output low * 0b1..Forces the corresponding output high */ #define SCT_OUTPUT_OUT9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK) /*! @} */ /*! @name OUTPUTDIRCTRL - Output Counter Direction Control */ /*! @{ */ #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) /*! SETCLR0 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) /*! SETCLR1 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) /*! SETCLR2 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) /*! SETCLR3 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) /*! SETCLR4 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) /*! SETCLR5 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) /*! SETCLR6 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) /*! SETCLR7 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) /*! SETCLR8 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) /*! SETCLR9 - Set and Clear Operation on Output * 0b00..Not dependent on the direction of any counter * 0b01..Reversed when counter L or the unified counter is counting down * 0b10..Reversed when counter H is counting down (do not use this value when CONFIG[UNIFY] = 1) * 0b11..Reserved (do not program this value) */ #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) /*! @} */ /*! @name RES - Output Conflict Resolution */ /*! @{ */ #define SCT_RES_O0RES_MASK (0x3U) #define SCT_RES_O0RES_SHIFT (0U) /*! O0RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) #define SCT_RES_O1RES_MASK (0xCU) #define SCT_RES_O1RES_SHIFT (2U) /*! O1RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) #define SCT_RES_O2RES_MASK (0x30U) #define SCT_RES_O2RES_SHIFT (4U) /*! O2RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) #define SCT_RES_O3RES_MASK (0xC0U) #define SCT_RES_O3RES_SHIFT (6U) /*! O3RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) #define SCT_RES_O4RES_MASK (0x300U) #define SCT_RES_O4RES_SHIFT (8U) /*! O4RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) #define SCT_RES_O5RES_MASK (0xC00U) #define SCT_RES_O5RES_SHIFT (10U) /*! O5RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) #define SCT_RES_O6RES_MASK (0x3000U) #define SCT_RES_O6RES_SHIFT (12U) /*! O6RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) #define SCT_RES_O7RES_MASK (0xC000U) #define SCT_RES_O7RES_SHIFT (14U) /*! O7RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) #define SCT_RES_O8RES_MASK (0x30000U) #define SCT_RES_O8RES_SHIFT (16U) /*! O8RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) #define SCT_RES_O9RES_MASK (0xC0000U) #define SCT_RES_O9RES_SHIFT (18U) /*! O9RES - Output Resolution * 0b00..No change * 0b01..Set output (or clear, based on OUTPUTDIRCTRL[SETCLRn]) * 0b10..Clear output (or set, based on OUTPUTDIRCTRL[SETCLRn]) * 0b11..Toggle output */ #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) /*! @} */ /*! @name DMAREQ0 - DMA Request 0 */ /*! @{ */ #define SCT_DMAREQ0_DEV_0_MASK (0x1U) #define SCT_DMAREQ0_DEV_0_SHIFT (0U) /*! DEV_0 - DMA Request Event */ #define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) #define SCT_DMAREQ0_DEV_1_MASK (0x2U) #define SCT_DMAREQ0_DEV_1_SHIFT (1U) /*! DEV_1 - DMA Request Event */ #define SCT_DMAREQ0_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK) #define SCT_DMAREQ0_DEV_2_MASK (0x4U) #define SCT_DMAREQ0_DEV_2_SHIFT (2U) /*! DEV_2 - DMA Request Event */ #define SCT_DMAREQ0_DEV_2(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK) #define SCT_DMAREQ0_DEV_3_MASK (0x8U) #define SCT_DMAREQ0_DEV_3_SHIFT (3U) /*! DEV_3 - DMA Request Event */ #define SCT_DMAREQ0_DEV_3(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK) #define SCT_DMAREQ0_DEV_4_MASK (0x10U) #define SCT_DMAREQ0_DEV_4_SHIFT (4U) /*! DEV_4 - DMA Request Event */ #define SCT_DMAREQ0_DEV_4(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK) #define SCT_DMAREQ0_DEV_5_MASK (0x20U) #define SCT_DMAREQ0_DEV_5_SHIFT (5U) /*! DEV_5 - DMA Request Event */ #define SCT_DMAREQ0_DEV_5(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK) #define SCT_DMAREQ0_DEV_6_MASK (0x40U) #define SCT_DMAREQ0_DEV_6_SHIFT (6U) /*! DEV_6 - DMA Request Event */ #define SCT_DMAREQ0_DEV_6(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK) #define SCT_DMAREQ0_DEV_7_MASK (0x80U) #define SCT_DMAREQ0_DEV_7_SHIFT (7U) /*! DEV_7 - DMA Request Event */ #define SCT_DMAREQ0_DEV_7(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK) #define SCT_DMAREQ0_DEV_8_MASK (0x100U) #define SCT_DMAREQ0_DEV_8_SHIFT (8U) /*! DEV_8 - DMA Request Event */ #define SCT_DMAREQ0_DEV_8(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK) #define SCT_DMAREQ0_DEV_9_MASK (0x200U) #define SCT_DMAREQ0_DEV_9_SHIFT (9U) /*! DEV_9 - DMA Request Event */ #define SCT_DMAREQ0_DEV_9(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK) #define SCT_DMAREQ0_DEV_10_MASK (0x400U) #define SCT_DMAREQ0_DEV_10_SHIFT (10U) /*! DEV_10 - DMA Request Event */ #define SCT_DMAREQ0_DEV_10(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK) #define SCT_DMAREQ0_DEV_11_MASK (0x800U) #define SCT_DMAREQ0_DEV_11_SHIFT (11U) /*! DEV_11 - DMA Request Event */ #define SCT_DMAREQ0_DEV_11(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK) #define SCT_DMAREQ0_DEV_12_MASK (0x1000U) #define SCT_DMAREQ0_DEV_12_SHIFT (12U) /*! DEV_12 - DMA Request Event */ #define SCT_DMAREQ0_DEV_12(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK) #define SCT_DMAREQ0_DEV_13_MASK (0x2000U) #define SCT_DMAREQ0_DEV_13_SHIFT (13U) /*! DEV_13 - DMA Request Event */ #define SCT_DMAREQ0_DEV_13(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK) #define SCT_DMAREQ0_DEV_14_MASK (0x4000U) #define SCT_DMAREQ0_DEV_14_SHIFT (14U) /*! DEV_14 - DMA Request Event */ #define SCT_DMAREQ0_DEV_14(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK) #define SCT_DMAREQ0_DEV_15_MASK (0x8000U) #define SCT_DMAREQ0_DEV_15_SHIFT (15U) /*! DEV_15 - DMA Request Event */ #define SCT_DMAREQ0_DEV_15(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK) #define SCT_DMAREQ0_DRL0_MASK (0x40000000U) #define SCT_DMAREQ0_DRL0_SHIFT (30U) /*! DRL0 - DMA Request Low 0 */ #define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) #define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) #define SCT_DMAREQ0_DRQ0_SHIFT (31U) /*! DRQ0 - DMA Request 0 State */ #define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) /*! @} */ /*! @name DMAREQ1 - DMA Request 1 */ /*! @{ */ #define SCT_DMAREQ1_DEV_0_MASK (0x1U) #define SCT_DMAREQ1_DEV_0_SHIFT (0U) /*! DEV_0 - DMA Request Event */ #define SCT_DMAREQ1_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK) #define SCT_DMAREQ1_DEV_1_MASK (0x2U) #define SCT_DMAREQ1_DEV_1_SHIFT (1U) /*! DEV_1 - DMA Request Event */ #define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) #define SCT_DMAREQ1_DEV_2_MASK (0x4U) #define SCT_DMAREQ1_DEV_2_SHIFT (2U) /*! DEV_2 - DMA Request Event */ #define SCT_DMAREQ1_DEV_2(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK) #define SCT_DMAREQ1_DEV_3_MASK (0x8U) #define SCT_DMAREQ1_DEV_3_SHIFT (3U) /*! DEV_3 - DMA Request Event */ #define SCT_DMAREQ1_DEV_3(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK) #define SCT_DMAREQ1_DEV_4_MASK (0x10U) #define SCT_DMAREQ1_DEV_4_SHIFT (4U) /*! DEV_4 - DMA Request Event */ #define SCT_DMAREQ1_DEV_4(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK) #define SCT_DMAREQ1_DEV_5_MASK (0x20U) #define SCT_DMAREQ1_DEV_5_SHIFT (5U) /*! DEV_5 - DMA Request Event */ #define SCT_DMAREQ1_DEV_5(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK) #define SCT_DMAREQ1_DEV_6_MASK (0x40U) #define SCT_DMAREQ1_DEV_6_SHIFT (6U) /*! DEV_6 - DMA Request Event */ #define SCT_DMAREQ1_DEV_6(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK) #define SCT_DMAREQ1_DEV_7_MASK (0x80U) #define SCT_DMAREQ1_DEV_7_SHIFT (7U) /*! DEV_7 - DMA Request Event */ #define SCT_DMAREQ1_DEV_7(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK) #define SCT_DMAREQ1_DEV_8_MASK (0x100U) #define SCT_DMAREQ1_DEV_8_SHIFT (8U) /*! DEV_8 - DMA Request Event */ #define SCT_DMAREQ1_DEV_8(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK) #define SCT_DMAREQ1_DEV_9_MASK (0x200U) #define SCT_DMAREQ1_DEV_9_SHIFT (9U) /*! DEV_9 - DMA Request Event */ #define SCT_DMAREQ1_DEV_9(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK) #define SCT_DMAREQ1_DEV_10_MASK (0x400U) #define SCT_DMAREQ1_DEV_10_SHIFT (10U) /*! DEV_10 - DMA Request Event */ #define SCT_DMAREQ1_DEV_10(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK) #define SCT_DMAREQ1_DEV_11_MASK (0x800U) #define SCT_DMAREQ1_DEV_11_SHIFT (11U) /*! DEV_11 - DMA Request Event */ #define SCT_DMAREQ1_DEV_11(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK) #define SCT_DMAREQ1_DEV_12_MASK (0x1000U) #define SCT_DMAREQ1_DEV_12_SHIFT (12U) /*! DEV_12 - DMA Request Event */ #define SCT_DMAREQ1_DEV_12(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK) #define SCT_DMAREQ1_DEV_13_MASK (0x2000U) #define SCT_DMAREQ1_DEV_13_SHIFT (13U) /*! DEV_13 - DMA Request Event */ #define SCT_DMAREQ1_DEV_13(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK) #define SCT_DMAREQ1_DEV_14_MASK (0x4000U) #define SCT_DMAREQ1_DEV_14_SHIFT (14U) /*! DEV_14 - DMA Request Event */ #define SCT_DMAREQ1_DEV_14(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK) #define SCT_DMAREQ1_DEV_15_MASK (0x8000U) #define SCT_DMAREQ1_DEV_15_SHIFT (15U) /*! DEV_15 - DMA Request Event */ #define SCT_DMAREQ1_DEV_15(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK) #define SCT_DMAREQ1_DRL1_MASK (0x40000000U) #define SCT_DMAREQ1_DRL1_SHIFT (30U) /*! DRL1 - DMA Request Low 1 */ #define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) #define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) #define SCT_DMAREQ1_DRQ1_SHIFT (31U) /*! DRQ1 - DMA Request 1 State */ #define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) /*! @} */ /*! @name EVEN - Event Interrupt Enable */ /*! @{ */ #define SCT_EVEN_IEN0_MASK (0x1U) #define SCT_EVEN_IEN0_SHIFT (0U) /*! IEN0 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK) #define SCT_EVEN_IEN1_MASK (0x2U) #define SCT_EVEN_IEN1_SHIFT (1U) /*! IEN1 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK) #define SCT_EVEN_IEN2_MASK (0x4U) #define SCT_EVEN_IEN2_SHIFT (2U) /*! IEN2 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK) #define SCT_EVEN_IEN3_MASK (0x8U) #define SCT_EVEN_IEN3_SHIFT (3U) /*! IEN3 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK) #define SCT_EVEN_IEN4_MASK (0x10U) #define SCT_EVEN_IEN4_SHIFT (4U) /*! IEN4 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK) #define SCT_EVEN_IEN5_MASK (0x20U) #define SCT_EVEN_IEN5_SHIFT (5U) /*! IEN5 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK) #define SCT_EVEN_IEN6_MASK (0x40U) #define SCT_EVEN_IEN6_SHIFT (6U) /*! IEN6 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK) #define SCT_EVEN_IEN7_MASK (0x80U) #define SCT_EVEN_IEN7_SHIFT (7U) /*! IEN7 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK) #define SCT_EVEN_IEN8_MASK (0x100U) #define SCT_EVEN_IEN8_SHIFT (8U) /*! IEN8 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK) #define SCT_EVEN_IEN9_MASK (0x200U) #define SCT_EVEN_IEN9_SHIFT (9U) /*! IEN9 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK) #define SCT_EVEN_IEN10_MASK (0x400U) #define SCT_EVEN_IEN10_SHIFT (10U) /*! IEN10 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK) #define SCT_EVEN_IEN11_MASK (0x800U) #define SCT_EVEN_IEN11_SHIFT (11U) /*! IEN11 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK) #define SCT_EVEN_IEN12_MASK (0x1000U) #define SCT_EVEN_IEN12_SHIFT (12U) /*! IEN12 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK) #define SCT_EVEN_IEN13_MASK (0x2000U) #define SCT_EVEN_IEN13_SHIFT (13U) /*! IEN13 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK) #define SCT_EVEN_IEN14_MASK (0x4000U) #define SCT_EVEN_IEN14_SHIFT (14U) /*! IEN14 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK) #define SCT_EVEN_IEN15_MASK (0x8000U) #define SCT_EVEN_IEN15_SHIFT (15U) /*! IEN15 - Event Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SCT_EVEN_IEN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK) /*! @} */ /*! @name EVFLAG - Event Flag */ /*! @{ */ #define SCT_EVFLAG_FLAG0_MASK (0x1U) #define SCT_EVFLAG_FLAG0_SHIFT (0U) /*! FLAG0 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK) #define SCT_EVFLAG_FLAG1_MASK (0x2U) #define SCT_EVFLAG_FLAG1_SHIFT (1U) /*! FLAG1 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK) #define SCT_EVFLAG_FLAG2_MASK (0x4U) #define SCT_EVFLAG_FLAG2_SHIFT (2U) /*! FLAG2 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK) #define SCT_EVFLAG_FLAG3_MASK (0x8U) #define SCT_EVFLAG_FLAG3_SHIFT (3U) /*! FLAG3 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK) #define SCT_EVFLAG_FLAG4_MASK (0x10U) #define SCT_EVFLAG_FLAG4_SHIFT (4U) /*! FLAG4 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK) #define SCT_EVFLAG_FLAG5_MASK (0x20U) #define SCT_EVFLAG_FLAG5_SHIFT (5U) /*! FLAG5 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK) #define SCT_EVFLAG_FLAG6_MASK (0x40U) #define SCT_EVFLAG_FLAG6_SHIFT (6U) /*! FLAG6 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK) #define SCT_EVFLAG_FLAG7_MASK (0x80U) #define SCT_EVFLAG_FLAG7_SHIFT (7U) /*! FLAG7 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK) #define SCT_EVFLAG_FLAG8_MASK (0x100U) #define SCT_EVFLAG_FLAG8_SHIFT (8U) /*! FLAG8 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG8(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK) #define SCT_EVFLAG_FLAG9_MASK (0x200U) #define SCT_EVFLAG_FLAG9_SHIFT (9U) /*! FLAG9 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG9(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK) #define SCT_EVFLAG_FLAG10_MASK (0x400U) #define SCT_EVFLAG_FLAG10_SHIFT (10U) /*! FLAG10 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG10(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK) #define SCT_EVFLAG_FLAG11_MASK (0x800U) #define SCT_EVFLAG_FLAG11_SHIFT (11U) /*! FLAG11 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG11(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK) #define SCT_EVFLAG_FLAG12_MASK (0x1000U) #define SCT_EVFLAG_FLAG12_SHIFT (12U) /*! FLAG12 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG12(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK) #define SCT_EVFLAG_FLAG13_MASK (0x2000U) #define SCT_EVFLAG_FLAG13_SHIFT (13U) /*! FLAG13 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG13(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK) #define SCT_EVFLAG_FLAG14_MASK (0x4000U) #define SCT_EVFLAG_FLAG14_SHIFT (14U) /*! FLAG14 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG14(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK) #define SCT_EVFLAG_FLAG15_MASK (0x8000U) #define SCT_EVFLAG_FLAG15_SHIFT (15U) /*! FLAG15 - Event Flag * 0b0..No flag * 0b1..Event n flag */ #define SCT_EVFLAG_FLAG15(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK) /*! @} */ /*! @name CONEN - Conflict Interrupt Enable */ /*! @{ */ #define SCT_CONEN_NCEN0_MASK (0x1U) #define SCT_CONEN_NCEN0_SHIFT (0U) /*! NCEN0 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK) #define SCT_CONEN_NCEN1_MASK (0x2U) #define SCT_CONEN_NCEN1_SHIFT (1U) /*! NCEN1 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK) #define SCT_CONEN_NCEN2_MASK (0x4U) #define SCT_CONEN_NCEN2_SHIFT (2U) /*! NCEN2 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK) #define SCT_CONEN_NCEN3_MASK (0x8U) #define SCT_CONEN_NCEN3_SHIFT (3U) /*! NCEN3 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK) #define SCT_CONEN_NCEN4_MASK (0x10U) #define SCT_CONEN_NCEN4_SHIFT (4U) /*! NCEN4 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK) #define SCT_CONEN_NCEN5_MASK (0x20U) #define SCT_CONEN_NCEN5_SHIFT (5U) /*! NCEN5 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK) #define SCT_CONEN_NCEN6_MASK (0x40U) #define SCT_CONEN_NCEN6_SHIFT (6U) /*! NCEN6 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK) #define SCT_CONEN_NCEN7_MASK (0x80U) #define SCT_CONEN_NCEN7_SHIFT (7U) /*! NCEN7 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK) #define SCT_CONEN_NCEN8_MASK (0x100U) #define SCT_CONEN_NCEN8_SHIFT (8U) /*! NCEN8 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK) #define SCT_CONEN_NCEN9_MASK (0x200U) #define SCT_CONEN_NCEN9_SHIFT (9U) /*! NCEN9 - No Change Conflict Event and Interrupt Enable * 0b0..No interrupt * 0b1..Interrupt */ #define SCT_CONEN_NCEN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK) /*! @} */ /*! @name CONFLAG - Conflict Flag */ /*! @{ */ #define SCT_CONFLAG_NCFLAG0_MASK (0x1U) #define SCT_CONFLAG_NCFLAG0_SHIFT (0U) /*! NCFLAG0 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG0(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK) #define SCT_CONFLAG_NCFLAG1_MASK (0x2U) #define SCT_CONFLAG_NCFLAG1_SHIFT (1U) /*! NCFLAG1 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG1(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK) #define SCT_CONFLAG_NCFLAG2_MASK (0x4U) #define SCT_CONFLAG_NCFLAG2_SHIFT (2U) /*! NCFLAG2 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG2(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK) #define SCT_CONFLAG_NCFLAG3_MASK (0x8U) #define SCT_CONFLAG_NCFLAG3_SHIFT (3U) /*! NCFLAG3 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG3(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK) #define SCT_CONFLAG_NCFLAG4_MASK (0x10U) #define SCT_CONFLAG_NCFLAG4_SHIFT (4U) /*! NCFLAG4 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG4(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK) #define SCT_CONFLAG_NCFLAG5_MASK (0x20U) #define SCT_CONFLAG_NCFLAG5_SHIFT (5U) /*! NCFLAG5 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG5(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK) #define SCT_CONFLAG_NCFLAG6_MASK (0x40U) #define SCT_CONFLAG_NCFLAG6_SHIFT (6U) /*! NCFLAG6 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG6(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK) #define SCT_CONFLAG_NCFLAG7_MASK (0x80U) #define SCT_CONFLAG_NCFLAG7_SHIFT (7U) /*! NCFLAG7 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG7(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK) #define SCT_CONFLAG_NCFLAG8_MASK (0x100U) #define SCT_CONFLAG_NCFLAG8_SHIFT (8U) /*! NCFLAG8 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG8(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK) #define SCT_CONFLAG_NCFLAG9_MASK (0x200U) #define SCT_CONFLAG_NCFLAG9_SHIFT (9U) /*! NCFLAG9 - No Change Conflict Event Flag * 0b0..Did not occur * 0b1..Occurred */ #define SCT_CONFLAG_NCFLAG9(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK) #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) #define SCT_CONFLAG_BUSERRL_SHIFT (30U) /*! BUSERRL - Bus Error Low or Unified */ #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) #define SCT_CONFLAG_BUSERRH_SHIFT (31U) /*! BUSERRH - Bus Error High */ #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) /*! @} */ /*! @name CAPL - SCT_CAPL register */ /*! @{ */ #define SCT_CAPL_CAPL_MASK (0xFFFFU) #define SCT_CAPL_CAPL_SHIFT (0U) #define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) /*! @} */ /* The count of SCT_CAPL */ #define SCT_CAPL_COUNT (16U) /*! @name CAPH - SCT_CAPH register */ /*! @{ */ #define SCT_CAPH_CAPH_MASK (0xFFFFU) #define SCT_CAPH_CAPH_SHIFT (0U) #define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) /*! @} */ /* The count of SCT_CAPH */ #define SCT_CAPH_COUNT (16U) /*! @name CAP - Capture Value */ /*! @{ */ #define SCT_CAP_CAPn_L_MASK (0xFFFFU) #define SCT_CAP_CAPn_L_SHIFT (0U) /*! CAPn_L - Capture Low */ #define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) #define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) #define SCT_CAP_CAPn_H_SHIFT (16U) /*! CAPn_H - Capture High */ #define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) /*! @} */ /* The count of SCT_CAP */ #define SCT_CAP_COUNT (16U) /*! @name MATCHL - SCT_MATCHL register */ /*! @{ */ #define SCT_MATCHL_MATCHL_MASK (0xFFFFU) #define SCT_MATCHL_MATCHL_SHIFT (0U) #define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) /*! @} */ /* The count of SCT_MATCHL */ #define SCT_MATCHL_COUNT (16U) /*! @name MATCHH - SCT_MATCHH register */ /*! @{ */ #define SCT_MATCHH_MATCHH_MASK (0xFFFFU) #define SCT_MATCHH_MATCHH_SHIFT (0U) #define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) /*! @} */ /* The count of SCT_MATCHH */ #define SCT_MATCHH_COUNT (16U) /*! @name MATCH - Match Value */ /*! @{ */ #define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) #define SCT_MATCH_MATCHn_L_SHIFT (0U) /*! MATCHn_L - Match Low */ #define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) #define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) #define SCT_MATCH_MATCHn_H_SHIFT (16U) /*! MATCHn_H - Match High */ #define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) /*! @} */ /* The count of SCT_MATCH */ #define SCT_MATCH_COUNT (16U) /*! @name FRACMAT - Fractional Match */ /*! @{ */ #define SCT_FRACMAT_FRACMAT_L_MASK (0xFU) #define SCT_FRACMAT_FRACMAT_L_SHIFT (0U) /*! FRACMAT_L - Fractional Match Low */ #define SCT_FRACMAT_FRACMAT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_L_SHIFT)) & SCT_FRACMAT_FRACMAT_L_MASK) #define SCT_FRACMAT_FRACMAT_H_MASK (0xF0000U) #define SCT_FRACMAT_FRACMAT_H_SHIFT (16U) /*! FRACMAT_H - Fractional Match High */ #define SCT_FRACMAT_FRACMAT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_H_SHIFT)) & SCT_FRACMAT_FRACMAT_H_MASK) /*! @} */ /* The count of SCT_FRACMAT */ #define SCT_FRACMAT_COUNT (6U) /*! @name CAPCTRLL - SCT_CAPCTRLL register */ /*! @{ */ #define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) #define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) #define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) /*! @} */ /* The count of SCT_CAPCTRLL */ #define SCT_CAPCTRLL_COUNT (16U) /*! @name CAPCTRLH - SCT_CAPCTRLH register */ /*! @{ */ #define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) #define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) #define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) /*! @} */ /* The count of SCT_CAPCTRLH */ #define SCT_CAPCTRLH_COUNT (16U) /*! @name SCTCAPCTRL_CAPCTRL - Capture Control */ /*! @{ */ #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT (0U) /*! CAPCONn_L - Capture Control Low */ #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK) #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT (16U) /*! CAPCONn_H - Capture Control High */ #define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK) /*! @} */ /* The count of SCT_SCTCAPCTRL_CAPCTRL */ #define SCT_SCTCAPCTRL_CAPCTRL_COUNT (16U) /*! @name MATCHRELL - SCT_MATCHRELL register */ /*! @{ */ #define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) #define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) #define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) /*! @} */ /* The count of SCT_MATCHRELL */ #define SCT_MATCHRELL_COUNT (16U) /*! @name MATCHRELH - SCT_MATCHRELH register */ /*! @{ */ #define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) #define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) #define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) /*! @} */ /* The count of SCT_MATCHRELH */ #define SCT_MATCHRELH_COUNT (16U) /*! @name MATCHREL - Match Reload Value */ /*! @{ */ #define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) #define SCT_MATCHREL_RELOADn_L_SHIFT (0U) /*! RELOADn_L - Reload Low */ #define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) #define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) #define SCT_MATCHREL_RELOADn_H_SHIFT (16U) /*! RELOADn_H - Reload High */ #define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) /*! @} */ /* The count of SCT_MATCHREL */ #define SCT_MATCHREL_COUNT (16U) /*! @name FRACMATREL - Fractional Match Reload */ /*! @{ */ #define SCT_FRACMATREL_RELFRAC_L_MASK (0xFU) #define SCT_FRACMATREL_RELFRAC_L_SHIFT (0U) /*! RELFRAC_L - Reload Fractional Match Low */ #define SCT_FRACMATREL_RELFRAC_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_L_SHIFT)) & SCT_FRACMATREL_RELFRAC_L_MASK) #define SCT_FRACMATREL_RELFRAC_H_MASK (0xF0000U) #define SCT_FRACMATREL_RELFRAC_H_SHIFT (16U) /*! RELFRAC_H - Reload Fractional Match High */ #define SCT_FRACMATREL_RELFRAC_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_H_SHIFT)) & SCT_FRACMATREL_RELFRAC_H_MASK) /*! @} */ /* The count of SCT_FRACMATREL */ #define SCT_FRACMATREL_COUNT (6U) /*! @name EV_STATE - Event n State */ /*! @{ */ #define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFFFFFU) #define SCT_EV_STATE_STATEMSKn_SHIFT (0U) /*! STATEMSKn - Event State Mask */ #define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) /*! @} */ /* The count of SCT_EV_STATE */ #define SCT_EV_STATE_COUNT (16U) /*! @name EV_CTRL - Event n Control */ /*! @{ */ #define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) #define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) /*! MATCHSEL - Match Select */ #define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) #define SCT_EV_CTRL_HEVENT_MASK (0x10U) #define SCT_EV_CTRL_HEVENT_SHIFT (4U) /*! HEVENT - High Event * 0b0..Low counter (selects the L state and the L match register that the MATCHSEL field specifies) * 0b1..High counter (selects the H state and the H match register that the MATCHSEL field specifies) */ #define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) #define SCT_EV_CTRL_OUTSEL_MASK (0x20U) #define SCT_EV_CTRL_OUTSEL_SHIFT (5U) /*! OUTSEL - Input and Output Select * 0b0..Inputs * 0b1..Outputs */ #define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) #define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) #define SCT_EV_CTRL_IOSEL_SHIFT (6U) /*! IOSEL - Input or Output Signal Select */ #define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) #define SCT_EV_CTRL_IOCOND_MASK (0xC00U) #define SCT_EV_CTRL_IOCOND_SHIFT (10U) /*! IOCOND - Input or Output Condition * 0b00..Low * 0b01..Rise * 0b10..Fall * 0b11..High */ #define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) #define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) #define SCT_EV_CTRL_COMBMODE_SHIFT (12U) /*! COMBMODE - Combination Mode * 0b00..OR (the event occurs when either the specified match or I/O condition occurs) * 0b01..MATCH (uses the specified match only) * 0b10..IO (uses the specified I/O condition only) * 0b11..AND (the event occurs when the specified match and I/O condition occur simultaneously) */ #define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) #define SCT_EV_CTRL_STATELD_MASK (0x4000U) #define SCT_EV_CTRL_STATELD_SHIFT (14U) /*! STATELD - State Load * 0b0..Value of STATEV added to that of STATE (the carry out is ignored) * 0b1..Value of STATEV loaded into that of STATE */ #define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) #define SCT_EV_CTRL_STATEV_MASK (0xF8000U) #define SCT_EV_CTRL_STATEV_SHIFT (15U) /*! STATEV - State Value */ #define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) #define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) #define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) /*! MATCHMEM - Match Mem */ #define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) #define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) #define SCT_EV_CTRL_DIRECTION_SHIFT (21U) /*! DIRECTION - Direction * 0b00..Direction independent (event triggered regardless of the count direction) * 0b01..Counting up (event triggered only during up-counting when CTRL[BIDIR] = 1) * 0b10..Counting down (event triggered only during down-counting when CTRL[BIDIR] = 1) * 0b11..Reserved */ #define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) /*! @} */ /* The count of SCT_EV_CTRL */ #define SCT_EV_CTRL_COUNT (16U) /*! @name OUT_SET - Output n Set */ /*! @{ */ #define SCT_OUT_SET_SET_MASK (0xFFFFU) #define SCT_OUT_SET_SET_SHIFT (0U) /*! SET - Set Output */ #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) /*! @} */ /* The count of SCT_OUT_SET */ #define SCT_OUT_SET_COUNT (10U) /*! @name OUT_CLR - Output n Clear */ /*! @{ */ #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) #define SCT_OUT_CLR_CLR_SHIFT (0U) /*! CLR - Clear Output */ #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) /*! @} */ /* The count of SCT_OUT_CLR */ #define SCT_OUT_CLR_COUNT (10U) /*! * @} */ /* end of group SCT_Register_Masks */ /* SCT - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral SCT0 base address */ #define SCT0_BASE (0x50091000u) /** Peripheral SCT0 base address */ #define SCT0_BASE_NS (0x40091000u) /** Peripheral SCT0 base pointer */ #define SCT0 ((SCT_Type *)SCT0_BASE) /** Peripheral SCT0 base pointer */ #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) /** Array initializer of SCT peripheral base addresses */ #define SCT_BASE_ADDRS { SCT0_BASE } /** Array initializer of SCT peripheral base pointers */ #define SCT_BASE_PTRS { SCT0 } /** Array initializer of SCT peripheral base addresses */ #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } /** Array initializer of SCT peripheral base pointers */ #define SCT_BASE_PTRS_NS { SCT0_NS } #else /** Peripheral SCT0 base address */ #define SCT0_BASE (0x40091000u) /** Peripheral SCT0 base pointer */ #define SCT0 ((SCT_Type *)SCT0_BASE) /** Array initializer of SCT peripheral base addresses */ #define SCT_BASE_ADDRS { SCT0_BASE } /** Array initializer of SCT peripheral base pointers */ #define SCT_BASE_PTRS { SCT0 } #endif /** Interrupt vectors for the SCT peripheral type */ #define SCT_IRQS { SCT0_IRQn } /*! * @} */ /* end of group SCT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SEMA42 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer * @{ */ /** SEMA42 - Register Layout Typedef */ typedef struct { __IO uint8_t GATE3; /**< Gate, offset: 0x0 */ __IO uint8_t GATE2; /**< Gate, offset: 0x1 */ __IO uint8_t GATE1; /**< Gate, offset: 0x2 */ __IO uint8_t GATE0; /**< Gate, offset: 0x3 */ __IO uint8_t GATE7; /**< Gate, offset: 0x4 */ __IO uint8_t GATE6; /**< Gate, offset: 0x5 */ __IO uint8_t GATE5; /**< Gate, offset: 0x6 */ __IO uint8_t GATE4; /**< Gate, offset: 0x7 */ __IO uint8_t GATE11; /**< Gate, offset: 0x8 */ __IO uint8_t GATE10; /**< Gate, offset: 0x9 */ __IO uint8_t GATE9; /**< Gate, offset: 0xA */ __IO uint8_t GATE8; /**< Gate, offset: 0xB */ __IO uint8_t GATE15; /**< Gate, offset: 0xC */ __IO uint8_t GATE14; /**< Gate, offset: 0xD */ __IO uint8_t GATE13; /**< Gate, offset: 0xE */ __IO uint8_t GATE12; /**< Gate, offset: 0xF */ uint8_t RESERVED_0[50]; union { /* offset: 0x42 */ __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ }; } SEMA42_Type; /* ---------------------------------------------------------------------------- -- SEMA42 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks * @{ */ /*! @name GATE3 - Gate */ /*! @{ */ #define SEMA42_GATE3_GTFSM_MASK (0xFU) #define SEMA42_GATE3_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK) /*! @} */ /*! @name GATE2 - Gate */ /*! @{ */ #define SEMA42_GATE2_GTFSM_MASK (0xFU) #define SEMA42_GATE2_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK) /*! @} */ /*! @name GATE1 - Gate */ /*! @{ */ #define SEMA42_GATE1_GTFSM_MASK (0xFU) #define SEMA42_GATE1_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK) /*! @} */ /*! @name GATE0 - Gate */ /*! @{ */ #define SEMA42_GATE0_GTFSM_MASK (0xFU) #define SEMA42_GATE0_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK) /*! @} */ /*! @name GATE7 - Gate */ /*! @{ */ #define SEMA42_GATE7_GTFSM_MASK (0xFU) #define SEMA42_GATE7_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK) /*! @} */ /*! @name GATE6 - Gate */ /*! @{ */ #define SEMA42_GATE6_GTFSM_MASK (0xFU) #define SEMA42_GATE6_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK) /*! @} */ /*! @name GATE5 - Gate */ /*! @{ */ #define SEMA42_GATE5_GTFSM_MASK (0xFU) #define SEMA42_GATE5_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK) /*! @} */ /*! @name GATE4 - Gate */ /*! @{ */ #define SEMA42_GATE4_GTFSM_MASK (0xFU) #define SEMA42_GATE4_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK) /*! @} */ /*! @name GATE11 - Gate */ /*! @{ */ #define SEMA42_GATE11_GTFSM_MASK (0xFU) #define SEMA42_GATE11_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK) /*! @} */ /*! @name GATE10 - Gate */ /*! @{ */ #define SEMA42_GATE10_GTFSM_MASK (0xFU) #define SEMA42_GATE10_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK) /*! @} */ /*! @name GATE9 - Gate */ /*! @{ */ #define SEMA42_GATE9_GTFSM_MASK (0xFU) #define SEMA42_GATE9_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK) /*! @} */ /*! @name GATE8 - Gate */ /*! @{ */ #define SEMA42_GATE8_GTFSM_MASK (0xFU) #define SEMA42_GATE8_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK) /*! @} */ /*! @name GATE15 - Gate */ /*! @{ */ #define SEMA42_GATE15_GTFSM_MASK (0xFU) #define SEMA42_GATE15_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK) /*! @} */ /*! @name GATE14 - Gate */ /*! @{ */ #define SEMA42_GATE14_GTFSM_MASK (0xFU) #define SEMA42_GATE14_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK) /*! @} */ /*! @name GATE13 - Gate */ /*! @{ */ #define SEMA42_GATE13_GTFSM_MASK (0xFU) #define SEMA42_GATE13_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK) /*! @} */ /*! @name GATE12 - Gate */ /*! @{ */ #define SEMA42_GATE12_GTFSM_MASK (0xFU) #define SEMA42_GATE12_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) /*! @} */ /*! @name RSTGT_R - Reset Gate Read */ /*! @{ */ #define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) #define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset Gate Number */ #define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) #define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) #define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) /*! RSTGMS - Reset Gate Domain */ #define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) #define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) #define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) /*! RSTGSM - Reset Gate Finite State Machine * 0b00..Idle, waiting for the first data pattern write. * 0b01..Waiting for the second data pattern write * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, * this machine returns to the idle (waiting for first data pattern write) state. * 0b11..This state encoding is never used and therefore reserved. */ #define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) /*! @} */ /*! @name RSTGT_W - Reset Gate Write */ /*! @{ */ #define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) #define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset Gate Number */ #define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) #define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) #define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) /*! RSTGDP - Reset Gate Data Pattern */ #define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) /*! @} */ /*! * @} */ /* end of group SEMA42_Register_Masks */ /* SEMA42 - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral SEMA42_0 base address */ #define SEMA42_0_BASE (0x500B1000u) /** Peripheral SEMA42_0 base address */ #define SEMA42_0_BASE_NS (0x400B1000u) /** Peripheral SEMA42_0 base pointer */ #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) /** Peripheral SEMA42_0 base pointer */ #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) /** Array initializer of SEMA42 peripheral base addresses */ #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } /** Array initializer of SEMA42 peripheral base pointers */ #define SEMA42_BASE_PTRS { SEMA42_0 } /** Array initializer of SEMA42 peripheral base addresses */ #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } /** Array initializer of SEMA42 peripheral base pointers */ #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } #else /** Peripheral SEMA42_0 base address */ #define SEMA42_0_BASE (0x400B1000u) /** Peripheral SEMA42_0 base pointer */ #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) /** Array initializer of SEMA42 peripheral base addresses */ #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } /** Array initializer of SEMA42 peripheral base pointers */ #define SEMA42_BASE_PTRS { SEMA42_0 } #endif /*! * @} */ /* end of group SEMA42_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SINC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SINC_Peripheral_Access_Layer SINC Peripheral Access Layer * @{ */ /** SINC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAMETER; /**< Parameters, offset: 0x4 */ __IO uint32_t MCR; /**< Main Control, offset: 0x8 */ __IO uint32_t NIE; /**< Normal Interrupt Enable, offset: 0xC */ __IO uint32_t EIE; /**< Error Interrupt Enable, offset: 0x10 */ __IO uint32_t FIFOIE; /**< FIFO And CAD Error Interrupt Enable, offset: 0x14 */ __IO uint32_t NIS; /**< Normal Interrupt Status, offset: 0x18 */ __IO uint32_t EIS; /**< Error Interrupt Status, offset: 0x1C */ __IO uint32_t FIFOIS; /**< FIFO And CAD Error Interrupt Status, offset: 0x20 */ __I uint32_t SR; /**< Status, offset: 0x24 */ uint8_t RESERVED_0[16]; struct { /* offset: 0x38, array step: 0x30 */ __IO uint32_t CCR; /**< Channel 0 Control..Channel 4 Control, array offset: 0x38, array step: 0x30 */ __IO uint32_t CDR; /**< Channel 0 Data Rate..Channel 4 Data Rate, array offset: 0x3C, array step: 0x30 */ __IO uint32_t CCFR; /**< Channel 0 Configuration..Channel 4 Configuration, array offset: 0x40, array step: 0x30 */ __IO uint32_t CPROT; /**< Channel 0 Protection..Channel 4 Protection, array offset: 0x44, array step: 0x30 */ __IO uint32_t CBIAS; /**< Channel 0 Bias..Channel 4 Bias, array offset: 0x48, array step: 0x30 */ __IO uint32_t CLOLMT; /**< Channel 0 Low Limit..Channel 4 Low Limit, array offset: 0x4C, array step: 0x30 */ __IO uint32_t CHILMT; /**< Channel 0 High Limit..Channel 4 High Limit, array offset: 0x50, array step: 0x30 */ __I uint32_t CRDATA; /**< Channel 0 Result Data..Channel 4 Result Data, array offset: 0x54, array step: 0x30 */ __IO uint32_t CMPDATA; /**< Channel 0 Multipurpose Data..Channel 4 Multipurpose Data, array offset: 0x58, array step: 0x30 */ __IO uint32_t CACFR; /**< Channel 0 Advanced Configuration..Channel 4 Advanced Configuration, array offset: 0x5C, array step: 0x30 */ __IO uint32_t CSR; /**< Channel 0 Status..Channel 4 Status, array offset: 0x60, array step: 0x30 */ __I uint32_t CDBGR; /**< Channel 0 Debug..Channel 4 Debug, array offset: 0x64, array step: 0x30 */ } CHANNEL[5]; } SINC_Type; /* ---------------------------------------------------------------------------- -- SINC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SINC_Register_Masks SINC Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define SINC_VERID_FEATURE_MASK (0xFFFFU) #define SINC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Code */ #define SINC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SINC_VERID_FEATURE_SHIFT)) & SINC_VERID_FEATURE_MASK) #define SINC_VERID_MINOR_MASK (0xFF0000U) #define SINC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number * 0b00000000..x.0 * *.. */ #define SINC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SINC_VERID_MINOR_SHIFT)) & SINC_VERID_MINOR_MASK) #define SINC_VERID_MAJOR_MASK (0xFF000000U) #define SINC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number * 0b00000001..1.x * 0b00000010..2.x * *.. */ #define SINC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SINC_VERID_MAJOR_SHIFT)) & SINC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAMETER - Parameters */ /*! @{ */ #define SINC_PARAMETER_FIFO_DEPTH_MASK (0x1FU) #define SINC_PARAMETER_FIFO_DEPTH_SHIFT (0U) /*! FIFO_DEPTH - FIFO Depth */ #define SINC_PARAMETER_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << SINC_PARAMETER_FIFO_DEPTH_SHIFT)) & SINC_PARAMETER_FIFO_DEPTH_MASK) #define SINC_PARAMETER_FLT_NUM_MASK (0xF00U) #define SINC_PARAMETER_FLT_NUM_SHIFT (8U) /*! FLT_NUM - Filter Channel Number */ #define SINC_PARAMETER_FLT_NUM(x) (((uint32_t)(((uint32_t)(x)) << SINC_PARAMETER_FLT_NUM_SHIFT)) & SINC_PARAMETER_FLT_NUM_MASK) #define SINC_PARAMETER_PF_ORD_SEL_MASK (0x180000U) #define SINC_PARAMETER_PF_ORD_SEL_SHIFT (19U) /*! PF_ORD_SEL - PF Order Select * 0b10..3 * 0b11..2 * *.. */ #define SINC_PARAMETER_PF_ORD_SEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_PARAMETER_PF_ORD_SEL_SHIFT)) & SINC_PARAMETER_PF_ORD_SEL_MASK) /*! @} */ /*! @name MCR - Main Control */ /*! @{ */ #define SINC_MCR_STRIG0_MASK (0x1U) #define SINC_MCR_STRIG0_SHIFT (0U) /*! STRIG0 - Software Trigger For Channel 0 * 0b0..No effect * 0b1..Trigger */ #define SINC_MCR_STRIG0(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG0_SHIFT)) & SINC_MCR_STRIG0_MASK) #define SINC_MCR_STRIG1_MASK (0x2U) #define SINC_MCR_STRIG1_SHIFT (1U) /*! STRIG1 - Software Trigger For Channel 1 * 0b0..No effect * 0b1..Trigger */ #define SINC_MCR_STRIG1(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG1_SHIFT)) & SINC_MCR_STRIG1_MASK) #define SINC_MCR_STRIG2_MASK (0x4U) #define SINC_MCR_STRIG2_SHIFT (2U) /*! STRIG2 - Software Trigger For Channel 2 * 0b0..No effect * 0b1..Trigger */ #define SINC_MCR_STRIG2(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG2_SHIFT)) & SINC_MCR_STRIG2_MASK) #define SINC_MCR_STRIG3_MASK (0x8U) #define SINC_MCR_STRIG3_SHIFT (3U) /*! STRIG3 - Software Trigger For Channel 3 * 0b0..No effect * 0b1..Trigger */ #define SINC_MCR_STRIG3(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG3_SHIFT)) & SINC_MCR_STRIG3_MASK) #define SINC_MCR_STRIG4_MASK (0x10U) #define SINC_MCR_STRIG4_SHIFT (4U) /*! STRIG4 - Software Trigger For Channel 4 * 0b0..No effect * 0b1..Trigger */ #define SINC_MCR_STRIG4(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_STRIG4_SHIFT)) & SINC_MCR_STRIG4_MASK) #define SINC_MCR_DOZEN_MASK (0x400U) #define SINC_MCR_DOZEN_SHIFT (10U) /*! DOZEN - Doze Or Stop Enable * 0b0..Enables * 0b1..Disables */ #define SINC_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_DOZEN_SHIFT)) & SINC_MCR_DOZEN_MASK) #define SINC_MCR_RST_MASK (0x2000U) #define SINC_MCR_RST_SHIFT (13U) /*! RST - Software Reset * 0b0..Do not reset * 0b1..Reset */ #define SINC_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_RST_SHIFT)) & SINC_MCR_RST_MASK) #define SINC_MCR_MEN_MASK (0x8000U) #define SINC_MCR_MEN_SHIFT (15U) /*! MEN - Master Enable * 0b0..Disables * 0b1..Enables */ #define SINC_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MEN_SHIFT)) & SINC_MCR_MEN_MASK) #define SINC_MCR_MCLKDIV_MASK (0xFF0000U) #define SINC_MCR_MCLKDIV_SHIFT (16U) /*! MCLKDIV - Modulator Clock Divider * 0b00000000..Prohibited * *..Added to 1 to specify the clock divider */ #define SINC_MCR_MCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MCLKDIV_SHIFT)) & SINC_MCR_MCLKDIV_MASK) #define SINC_MCR_PRESCALE_MASK (0x6000000U) #define SINC_MCR_PRESCALE_SHIFT (25U) /*! PRESCALE - Prescale Before Clock Divider * 0b00..No prescale * 0b01..2 * 0b10..4 * 0b11..8 */ #define SINC_MCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_PRESCALE_SHIFT)) & SINC_MCR_PRESCALE_MASK) #define SINC_MCR_MCLK0DIS_MASK (0x8000000U) #define SINC_MCR_MCLK0DIS_SHIFT (27U) /*! MCLK0DIS - Disable Modulator Clock 0 Output * 0b0..Enabled when MEN = 1 * 0b1..Disabled regardless of MEN value */ #define SINC_MCR_MCLK0DIS(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MCLK0DIS_SHIFT)) & SINC_MCR_MCLK0DIS_MASK) #define SINC_MCR_MCLK1DIS_MASK (0x10000000U) #define SINC_MCR_MCLK1DIS_SHIFT (28U) /*! MCLK1DIS - Disable Modulator Clock 1 Output * 0b0..Enabled when MEN = 1 * 0b1..Disabled regardless of MEN value */ #define SINC_MCR_MCLK1DIS(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MCLK1DIS_SHIFT)) & SINC_MCR_MCLK1DIS_MASK) #define SINC_MCR_MCLK2DIS_MASK (0x20000000U) #define SINC_MCR_MCLK2DIS_SHIFT (29U) /*! MCLK2DIS - Disable Modulator Clock 2 Output * 0b0..Enabled when MEN = 1 * 0b1..Disabled regardless of MEN value */ #define SINC_MCR_MCLK2DIS(x) (((uint32_t)(((uint32_t)(x)) << SINC_MCR_MCLK2DIS_SHIFT)) & SINC_MCR_MCLK2DIS_MASK) /*! @} */ /*! @name NIE - Normal Interrupt Enable */ /*! @{ */ #define SINC_NIE_COCIE0_MASK (0x1U) #define SINC_NIE_COCIE0_SHIFT (0U) /*! COCIE0 - Conversion Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_COCIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE0_SHIFT)) & SINC_NIE_COCIE0_MASK) #define SINC_NIE_COCIE1_MASK (0x2U) #define SINC_NIE_COCIE1_SHIFT (1U) /*! COCIE1 - Conversion Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_COCIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE1_SHIFT)) & SINC_NIE_COCIE1_MASK) #define SINC_NIE_COCIE2_MASK (0x4U) #define SINC_NIE_COCIE2_SHIFT (2U) /*! COCIE2 - Conversion Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_COCIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE2_SHIFT)) & SINC_NIE_COCIE2_MASK) #define SINC_NIE_COCIE3_MASK (0x8U) #define SINC_NIE_COCIE3_SHIFT (3U) /*! COCIE3 - Conversion Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_COCIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE3_SHIFT)) & SINC_NIE_COCIE3_MASK) #define SINC_NIE_COCIE4_MASK (0x10U) #define SINC_NIE_COCIE4_SHIFT (4U) /*! COCIE4 - Conversion Complete Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_COCIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_COCIE4_SHIFT)) & SINC_NIE_COCIE4_MASK) #define SINC_NIE_CHFIE0_MASK (0x100U) #define SINC_NIE_CHFIE0_SHIFT (8U) /*! CHFIE0 - Data Output Ready Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_CHFIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE0_SHIFT)) & SINC_NIE_CHFIE0_MASK) #define SINC_NIE_CHFIE1_MASK (0x200U) #define SINC_NIE_CHFIE1_SHIFT (9U) /*! CHFIE1 - Data Output Ready Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_CHFIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE1_SHIFT)) & SINC_NIE_CHFIE1_MASK) #define SINC_NIE_CHFIE2_MASK (0x400U) #define SINC_NIE_CHFIE2_SHIFT (10U) /*! CHFIE2 - Data Output Ready Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_CHFIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE2_SHIFT)) & SINC_NIE_CHFIE2_MASK) #define SINC_NIE_CHFIE3_MASK (0x800U) #define SINC_NIE_CHFIE3_SHIFT (11U) /*! CHFIE3 - Data Output Ready Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_CHFIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE3_SHIFT)) & SINC_NIE_CHFIE3_MASK) #define SINC_NIE_CHFIE4_MASK (0x1000U) #define SINC_NIE_CHFIE4_SHIFT (12U) /*! CHFIE4 - Data Output Ready Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_CHFIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_CHFIE4_SHIFT)) & SINC_NIE_CHFIE4_MASK) #define SINC_NIE_ZCDIE0_MASK (0x10000U) #define SINC_NIE_ZCDIE0_SHIFT (16U) /*! ZCDIE0 - Zero Cross Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_ZCDIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE0_SHIFT)) & SINC_NIE_ZCDIE0_MASK) #define SINC_NIE_ZCDIE1_MASK (0x20000U) #define SINC_NIE_ZCDIE1_SHIFT (17U) /*! ZCDIE1 - Zero Cross Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_ZCDIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE1_SHIFT)) & SINC_NIE_ZCDIE1_MASK) #define SINC_NIE_ZCDIE2_MASK (0x40000U) #define SINC_NIE_ZCDIE2_SHIFT (18U) /*! ZCDIE2 - Zero Cross Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_ZCDIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE2_SHIFT)) & SINC_NIE_ZCDIE2_MASK) #define SINC_NIE_ZCDIE3_MASK (0x80000U) #define SINC_NIE_ZCDIE3_SHIFT (19U) /*! ZCDIE3 - Zero Cross Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_ZCDIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE3_SHIFT)) & SINC_NIE_ZCDIE3_MASK) #define SINC_NIE_ZCDIE4_MASK (0x100000U) #define SINC_NIE_ZCDIE4_SHIFT (20U) /*! ZCDIE4 - Zero Cross Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_NIE_ZCDIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIE_ZCDIE4_SHIFT)) & SINC_NIE_ZCDIE4_MASK) /*! @} */ /*! @name EIE - Error Interrupt Enable */ /*! @{ */ #define SINC_EIE_SCDIE0_MASK (0x1U) #define SINC_EIE_SCDIE0_SHIFT (0U) /*! SCDIE0 - Short Circuit Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_SCDIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE0_SHIFT)) & SINC_EIE_SCDIE0_MASK) #define SINC_EIE_SCDIE1_MASK (0x2U) #define SINC_EIE_SCDIE1_SHIFT (1U) /*! SCDIE1 - Short Circuit Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_SCDIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE1_SHIFT)) & SINC_EIE_SCDIE1_MASK) #define SINC_EIE_SCDIE2_MASK (0x4U) #define SINC_EIE_SCDIE2_SHIFT (2U) /*! SCDIE2 - Short Circuit Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_SCDIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE2_SHIFT)) & SINC_EIE_SCDIE2_MASK) #define SINC_EIE_SCDIE3_MASK (0x8U) #define SINC_EIE_SCDIE3_SHIFT (3U) /*! SCDIE3 - Short Circuit Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_SCDIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE3_SHIFT)) & SINC_EIE_SCDIE3_MASK) #define SINC_EIE_SCDIE4_MASK (0x10U) #define SINC_EIE_SCDIE4_SHIFT (4U) /*! SCDIE4 - Short Circuit Detected Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_SCDIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_SCDIE4_SHIFT)) & SINC_EIE_SCDIE4_MASK) #define SINC_EIE_WLMTIE0_MASK (0x100U) #define SINC_EIE_WLMTIE0_SHIFT (8U) /*! WLMTIE0 - Window Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_WLMTIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE0_SHIFT)) & SINC_EIE_WLMTIE0_MASK) #define SINC_EIE_WLMTIE1_MASK (0x200U) #define SINC_EIE_WLMTIE1_SHIFT (9U) /*! WLMTIE1 - Window Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_WLMTIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE1_SHIFT)) & SINC_EIE_WLMTIE1_MASK) #define SINC_EIE_WLMTIE2_MASK (0x400U) #define SINC_EIE_WLMTIE2_SHIFT (10U) /*! WLMTIE2 - Window Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_WLMTIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE2_SHIFT)) & SINC_EIE_WLMTIE2_MASK) #define SINC_EIE_WLMTIE3_MASK (0x800U) #define SINC_EIE_WLMTIE3_SHIFT (11U) /*! WLMTIE3 - Window Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_WLMTIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE3_SHIFT)) & SINC_EIE_WLMTIE3_MASK) #define SINC_EIE_WLMTIE4_MASK (0x1000U) #define SINC_EIE_WLMTIE4_SHIFT (12U) /*! WLMTIE4 - Window Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_WLMTIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_WLMTIE4_SHIFT)) & SINC_EIE_WLMTIE4_MASK) #define SINC_EIE_LLMTIE0_MASK (0x10000U) #define SINC_EIE_LLMTIE0_SHIFT (16U) /*! LLMTIE0 - Low Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_LLMTIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE0_SHIFT)) & SINC_EIE_LLMTIE0_MASK) #define SINC_EIE_LLMTIE1_MASK (0x20000U) #define SINC_EIE_LLMTIE1_SHIFT (17U) /*! LLMTIE1 - Low Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_LLMTIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE1_SHIFT)) & SINC_EIE_LLMTIE1_MASK) #define SINC_EIE_LLMTIE2_MASK (0x40000U) #define SINC_EIE_LLMTIE2_SHIFT (18U) /*! LLMTIE2 - Low Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_LLMTIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE2_SHIFT)) & SINC_EIE_LLMTIE2_MASK) #define SINC_EIE_LLMTIE3_MASK (0x80000U) #define SINC_EIE_LLMTIE3_SHIFT (19U) /*! LLMTIE3 - Low Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_LLMTIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE3_SHIFT)) & SINC_EIE_LLMTIE3_MASK) #define SINC_EIE_LLMTIE4_MASK (0x100000U) #define SINC_EIE_LLMTIE4_SHIFT (20U) /*! LLMTIE4 - Low Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_LLMTIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_LLMTIE4_SHIFT)) & SINC_EIE_LLMTIE4_MASK) #define SINC_EIE_HLMTIE0_MASK (0x1000000U) #define SINC_EIE_HLMTIE0_SHIFT (24U) /*! HLMTIE0 - High Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_HLMTIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE0_SHIFT)) & SINC_EIE_HLMTIE0_MASK) #define SINC_EIE_HLMTIE1_MASK (0x2000000U) #define SINC_EIE_HLMTIE1_SHIFT (25U) /*! HLMTIE1 - High Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_HLMTIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE1_SHIFT)) & SINC_EIE_HLMTIE1_MASK) #define SINC_EIE_HLMTIE2_MASK (0x4000000U) #define SINC_EIE_HLMTIE2_SHIFT (26U) /*! HLMTIE2 - High Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_HLMTIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE2_SHIFT)) & SINC_EIE_HLMTIE2_MASK) #define SINC_EIE_HLMTIE3_MASK (0x8000000U) #define SINC_EIE_HLMTIE3_SHIFT (27U) /*! HLMTIE3 - High Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_HLMTIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE3_SHIFT)) & SINC_EIE_HLMTIE3_MASK) #define SINC_EIE_HLMTIE4_MASK (0x10000000U) #define SINC_EIE_HLMTIE4_SHIFT (28U) /*! HLMTIE4 - High Limit Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_EIE_HLMTIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIE_HLMTIE4_SHIFT)) & SINC_EIE_HLMTIE4_MASK) /*! @} */ /*! @name FIFOIE - FIFO And CAD Error Interrupt Enable */ /*! @{ */ #define SINC_FIFOIE_FUNFIE0_MASK (0x1U) #define SINC_FIFOIE_FUNFIE0_SHIFT (0U) /*! FUNFIE0 - FIFO Underflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FUNFIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE0_SHIFT)) & SINC_FIFOIE_FUNFIE0_MASK) #define SINC_FIFOIE_FUNFIE1_MASK (0x2U) #define SINC_FIFOIE_FUNFIE1_SHIFT (1U) /*! FUNFIE1 - FIFO Underflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FUNFIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE1_SHIFT)) & SINC_FIFOIE_FUNFIE1_MASK) #define SINC_FIFOIE_FUNFIE2_MASK (0x4U) #define SINC_FIFOIE_FUNFIE2_SHIFT (2U) /*! FUNFIE2 - FIFO Underflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FUNFIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE2_SHIFT)) & SINC_FIFOIE_FUNFIE2_MASK) #define SINC_FIFOIE_FUNFIE3_MASK (0x8U) #define SINC_FIFOIE_FUNFIE3_SHIFT (3U) /*! FUNFIE3 - FIFO Underflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FUNFIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE3_SHIFT)) & SINC_FIFOIE_FUNFIE3_MASK) #define SINC_FIFOIE_FUNFIE4_MASK (0x10U) #define SINC_FIFOIE_FUNFIE4_SHIFT (4U) /*! FUNFIE4 - FIFO Underflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FUNFIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FUNFIE4_SHIFT)) & SINC_FIFOIE_FUNFIE4_MASK) #define SINC_FIFOIE_FOVFIE0_MASK (0x100U) #define SINC_FIFOIE_FOVFIE0_SHIFT (8U) /*! FOVFIE0 - FIFO Overflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FOVFIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE0_SHIFT)) & SINC_FIFOIE_FOVFIE0_MASK) #define SINC_FIFOIE_FOVFIE1_MASK (0x200U) #define SINC_FIFOIE_FOVFIE1_SHIFT (9U) /*! FOVFIE1 - FIFO Overflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FOVFIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE1_SHIFT)) & SINC_FIFOIE_FOVFIE1_MASK) #define SINC_FIFOIE_FOVFIE2_MASK (0x400U) #define SINC_FIFOIE_FOVFIE2_SHIFT (10U) /*! FOVFIE2 - FIFO Overflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FOVFIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE2_SHIFT)) & SINC_FIFOIE_FOVFIE2_MASK) #define SINC_FIFOIE_FOVFIE3_MASK (0x800U) #define SINC_FIFOIE_FOVFIE3_SHIFT (11U) /*! FOVFIE3 - FIFO Overflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FOVFIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE3_SHIFT)) & SINC_FIFOIE_FOVFIE3_MASK) #define SINC_FIFOIE_FOVFIE4_MASK (0x1000U) #define SINC_FIFOIE_FOVFIE4_SHIFT (12U) /*! FOVFIE4 - FIFO Overflow Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_FOVFIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_FOVFIE4_SHIFT)) & SINC_FIFOIE_FOVFIE4_MASK) #define SINC_FIFOIE_CADIE0_MASK (0x10000U) #define SINC_FIFOIE_CADIE0_SHIFT (16U) /*! CADIE0 - Clock Absence Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_CADIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE0_SHIFT)) & SINC_FIFOIE_CADIE0_MASK) #define SINC_FIFOIE_CADIE1_MASK (0x20000U) #define SINC_FIFOIE_CADIE1_SHIFT (17U) /*! CADIE1 - Clock Absence Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_CADIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE1_SHIFT)) & SINC_FIFOIE_CADIE1_MASK) #define SINC_FIFOIE_CADIE2_MASK (0x40000U) #define SINC_FIFOIE_CADIE2_SHIFT (18U) /*! CADIE2 - Clock Absence Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_CADIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE2_SHIFT)) & SINC_FIFOIE_CADIE2_MASK) #define SINC_FIFOIE_CADIE3_MASK (0x80000U) #define SINC_FIFOIE_CADIE3_SHIFT (19U) /*! CADIE3 - Clock Absence Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_CADIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE3_SHIFT)) & SINC_FIFOIE_CADIE3_MASK) #define SINC_FIFOIE_CADIE4_MASK (0x100000U) #define SINC_FIFOIE_CADIE4_SHIFT (20U) /*! CADIE4 - Clock Absence Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_CADIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_CADIE4_SHIFT)) & SINC_FIFOIE_CADIE4_MASK) #define SINC_FIFOIE_SATIE0_MASK (0x1000000U) #define SINC_FIFOIE_SATIE0_SHIFT (24U) /*! SATIE0 - Saturation Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_SATIE0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE0_SHIFT)) & SINC_FIFOIE_SATIE0_MASK) #define SINC_FIFOIE_SATIE1_MASK (0x2000000U) #define SINC_FIFOIE_SATIE1_SHIFT (25U) /*! SATIE1 - Saturation Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_SATIE1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE1_SHIFT)) & SINC_FIFOIE_SATIE1_MASK) #define SINC_FIFOIE_SATIE2_MASK (0x4000000U) #define SINC_FIFOIE_SATIE2_SHIFT (26U) /*! SATIE2 - Saturation Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_SATIE2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE2_SHIFT)) & SINC_FIFOIE_SATIE2_MASK) #define SINC_FIFOIE_SATIE3_MASK (0x8000000U) #define SINC_FIFOIE_SATIE3_SHIFT (27U) /*! SATIE3 - Saturation Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_SATIE3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE3_SHIFT)) & SINC_FIFOIE_SATIE3_MASK) #define SINC_FIFOIE_SATIE4_MASK (0x10000000U) #define SINC_FIFOIE_SATIE4_SHIFT (28U) /*! SATIE4 - Saturation Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define SINC_FIFOIE_SATIE4(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIE_SATIE4_SHIFT)) & SINC_FIFOIE_SATIE4_MASK) /*! @} */ /*! @name NIS - Normal Interrupt Status */ /*! @{ */ #define SINC_NIS_COC0_MASK (0x1U) #define SINC_NIS_COC0_SHIFT (0U) /*! COC0 - Conversion Complete Flag * 0b0..Not finished; data not available * 0b1..Finished; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_COC0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC0_SHIFT)) & SINC_NIS_COC0_MASK) #define SINC_NIS_COC1_MASK (0x2U) #define SINC_NIS_COC1_SHIFT (1U) /*! COC1 - Conversion Complete Flag * 0b0..Not finished; data not available * 0b1..Finished; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_COC1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC1_SHIFT)) & SINC_NIS_COC1_MASK) #define SINC_NIS_COC2_MASK (0x4U) #define SINC_NIS_COC2_SHIFT (2U) /*! COC2 - Conversion Complete Flag * 0b0..Not finished; data not available * 0b1..Finished; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_COC2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC2_SHIFT)) & SINC_NIS_COC2_MASK) #define SINC_NIS_COC3_MASK (0x8U) #define SINC_NIS_COC3_SHIFT (3U) /*! COC3 - Conversion Complete Flag * 0b0..Not finished; data not available * 0b1..Finished; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_COC3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC3_SHIFT)) & SINC_NIS_COC3_MASK) #define SINC_NIS_COC4_MASK (0x10U) #define SINC_NIS_COC4_SHIFT (4U) /*! COC4 - Conversion Complete Flag * 0b0..Not finished; data not available * 0b1..Finished; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_COC4(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC4_SHIFT)) & SINC_NIS_COC4_MASK) #define SINC_NIS_CHF0_MASK (0x100U) #define SINC_NIS_CHF0_SHIFT (8U) /*! CHF0 - Data Output Ready Flag * 0b0..No overflow; data not available * 0b1..Overflow; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_CHF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF0_SHIFT)) & SINC_NIS_CHF0_MASK) #define SINC_NIS_CHF1_MASK (0x200U) #define SINC_NIS_CHF1_SHIFT (9U) /*! CHF1 - Data Output Ready Flag * 0b0..No overflow; data not available * 0b1..Overflow; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_CHF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF1_SHIFT)) & SINC_NIS_CHF1_MASK) #define SINC_NIS_CHF2_MASK (0x400U) #define SINC_NIS_CHF2_SHIFT (10U) /*! CHF2 - Data Output Ready Flag * 0b0..No overflow; data not available * 0b1..Overflow; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_CHF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF2_SHIFT)) & SINC_NIS_CHF2_MASK) #define SINC_NIS_CHF3_MASK (0x800U) #define SINC_NIS_CHF3_SHIFT (11U) /*! CHF3 - Data Output Ready Flag * 0b0..No overflow; data not available * 0b1..Overflow; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_CHF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF3_SHIFT)) & SINC_NIS_CHF3_MASK) #define SINC_NIS_CHF4_MASK (0x1000U) #define SINC_NIS_CHF4_SHIFT (12U) /*! CHF4 - Data Output Ready Flag * 0b0..No overflow; data not available * 0b1..Overflow; data available * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_CHF4(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF4_SHIFT)) & SINC_NIS_CHF4_MASK) #define SINC_NIS_ZCD0_MASK (0x10000U) #define SINC_NIS_ZCD0_SHIFT (16U) /*! ZCD0 - Zero Cross Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_ZCD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD0_SHIFT)) & SINC_NIS_ZCD0_MASK) #define SINC_NIS_ZCD1_MASK (0x20000U) #define SINC_NIS_ZCD1_SHIFT (17U) /*! ZCD1 - Zero Cross Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_ZCD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD1_SHIFT)) & SINC_NIS_ZCD1_MASK) #define SINC_NIS_ZCD2_MASK (0x40000U) #define SINC_NIS_ZCD2_SHIFT (18U) /*! ZCD2 - Zero Cross Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_ZCD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD2_SHIFT)) & SINC_NIS_ZCD2_MASK) #define SINC_NIS_ZCD3_MASK (0x80000U) #define SINC_NIS_ZCD3_SHIFT (19U) /*! ZCD3 - Zero Cross Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_ZCD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD3_SHIFT)) & SINC_NIS_ZCD3_MASK) #define SINC_NIS_ZCD4_MASK (0x100000U) #define SINC_NIS_ZCD4_SHIFT (20U) /*! ZCD4 - Zero Cross Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_NIS_ZCD4(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD4_SHIFT)) & SINC_NIS_ZCD4_MASK) /*! @} */ /*! @name EIS - Error Interrupt Status */ /*! @{ */ #define SINC_EIS_SCD0_MASK (0x1U) #define SINC_EIS_SCD0_SHIFT (0U) /*! SCD0 - Short Circuit Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_SCD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD0_SHIFT)) & SINC_EIS_SCD0_MASK) #define SINC_EIS_SCD1_MASK (0x2U) #define SINC_EIS_SCD1_SHIFT (1U) /*! SCD1 - Short Circuit Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_SCD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD1_SHIFT)) & SINC_EIS_SCD1_MASK) #define SINC_EIS_SCD2_MASK (0x4U) #define SINC_EIS_SCD2_SHIFT (2U) /*! SCD2 - Short Circuit Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_SCD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD2_SHIFT)) & SINC_EIS_SCD2_MASK) #define SINC_EIS_SCD3_MASK (0x8U) #define SINC_EIS_SCD3_SHIFT (3U) /*! SCD3 - Short Circuit Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_SCD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD3_SHIFT)) & SINC_EIS_SCD3_MASK) #define SINC_EIS_SCD4_MASK (0x10U) #define SINC_EIS_SCD4_SHIFT (4U) /*! SCD4 - Short Circuit Detected Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_SCD4(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD4_SHIFT)) & SINC_EIS_SCD4_MASK) #define SINC_EIS_WLMT0_MASK (0x100U) #define SINC_EIS_WLMT0_SHIFT (8U) /*! WLMT0 - Window Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_WLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT0_SHIFT)) & SINC_EIS_WLMT0_MASK) #define SINC_EIS_WLMT1_MASK (0x200U) #define SINC_EIS_WLMT1_SHIFT (9U) /*! WLMT1 - Window Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_WLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT1_SHIFT)) & SINC_EIS_WLMT1_MASK) #define SINC_EIS_WLMT2_MASK (0x400U) #define SINC_EIS_WLMT2_SHIFT (10U) /*! WLMT2 - Window Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_WLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT2_SHIFT)) & SINC_EIS_WLMT2_MASK) #define SINC_EIS_WLMT3_MASK (0x800U) #define SINC_EIS_WLMT3_SHIFT (11U) /*! WLMT3 - Window Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_WLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT3_SHIFT)) & SINC_EIS_WLMT3_MASK) #define SINC_EIS_WLMT4_MASK (0x1000U) #define SINC_EIS_WLMT4_SHIFT (12U) /*! WLMT4 - Window Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_WLMT4(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT4_SHIFT)) & SINC_EIS_WLMT4_MASK) #define SINC_EIS_LLMT0_MASK (0x10000U) #define SINC_EIS_LLMT0_SHIFT (16U) /*! LLMT0 - Low Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_LLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT0_SHIFT)) & SINC_EIS_LLMT0_MASK) #define SINC_EIS_LLMT1_MASK (0x20000U) #define SINC_EIS_LLMT1_SHIFT (17U) /*! LLMT1 - Low Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_LLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT1_SHIFT)) & SINC_EIS_LLMT1_MASK) #define SINC_EIS_LLMT2_MASK (0x40000U) #define SINC_EIS_LLMT2_SHIFT (18U) /*! LLMT2 - Low Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_LLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT2_SHIFT)) & SINC_EIS_LLMT2_MASK) #define SINC_EIS_LLMT3_MASK (0x80000U) #define SINC_EIS_LLMT3_SHIFT (19U) /*! LLMT3 - Low Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_LLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT3_SHIFT)) & SINC_EIS_LLMT3_MASK) #define SINC_EIS_LLMT4_MASK (0x100000U) #define SINC_EIS_LLMT4_SHIFT (20U) /*! LLMT4 - Low Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_LLMT4(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT4_SHIFT)) & SINC_EIS_LLMT4_MASK) #define SINC_EIS_HLMT0_MASK (0x1000000U) #define SINC_EIS_HLMT0_SHIFT (24U) /*! HLMT0 - High Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_HLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT0_SHIFT)) & SINC_EIS_HLMT0_MASK) #define SINC_EIS_HLMT1_MASK (0x2000000U) #define SINC_EIS_HLMT1_SHIFT (25U) /*! HLMT1 - High Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_HLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT1_SHIFT)) & SINC_EIS_HLMT1_MASK) #define SINC_EIS_HLMT2_MASK (0x4000000U) #define SINC_EIS_HLMT2_SHIFT (26U) /*! HLMT2 - High Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_HLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT2_SHIFT)) & SINC_EIS_HLMT2_MASK) #define SINC_EIS_HLMT3_MASK (0x8000000U) #define SINC_EIS_HLMT3_SHIFT (27U) /*! HLMT3 - High Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_HLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT3_SHIFT)) & SINC_EIS_HLMT3_MASK) #define SINC_EIS_HLMT4_MASK (0x10000000U) #define SINC_EIS_HLMT4_SHIFT (28U) /*! HLMT4 - High Limit Flag * 0b0..Not exceeded * 0b1..Exceeded * 0b0..No effect * 0b1..Clear the flag */ #define SINC_EIS_HLMT4(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT4_SHIFT)) & SINC_EIS_HLMT4_MASK) /*! @} */ /*! @name FIFOIS - FIFO And CAD Error Interrupt Status */ /*! @{ */ #define SINC_FIFOIS_FUNF0_MASK (0x1U) #define SINC_FIFOIS_FUNF0_SHIFT (0U) /*! FUNF0 - FIFO Underflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FUNF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF0_SHIFT)) & SINC_FIFOIS_FUNF0_MASK) #define SINC_FIFOIS_FUNF1_MASK (0x2U) #define SINC_FIFOIS_FUNF1_SHIFT (1U) /*! FUNF1 - FIFO Underflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FUNF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF1_SHIFT)) & SINC_FIFOIS_FUNF1_MASK) #define SINC_FIFOIS_FUNF2_MASK (0x4U) #define SINC_FIFOIS_FUNF2_SHIFT (2U) /*! FUNF2 - FIFO Underflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FUNF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF2_SHIFT)) & SINC_FIFOIS_FUNF2_MASK) #define SINC_FIFOIS_FUNF3_MASK (0x8U) #define SINC_FIFOIS_FUNF3_SHIFT (3U) /*! FUNF3 - FIFO Underflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FUNF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF3_SHIFT)) & SINC_FIFOIS_FUNF3_MASK) #define SINC_FIFOIS_FUNF4_MASK (0x10U) #define SINC_FIFOIS_FUNF4_SHIFT (4U) /*! FUNF4 - FIFO Underflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FUNF4(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF4_SHIFT)) & SINC_FIFOIS_FUNF4_MASK) #define SINC_FIFOIS_FOVF0_MASK (0x100U) #define SINC_FIFOIS_FOVF0_SHIFT (8U) /*! FOVF0 - FIFO Overflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FOVF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF0_SHIFT)) & SINC_FIFOIS_FOVF0_MASK) #define SINC_FIFOIS_FOVF1_MASK (0x200U) #define SINC_FIFOIS_FOVF1_SHIFT (9U) /*! FOVF1 - FIFO Overflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FOVF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF1_SHIFT)) & SINC_FIFOIS_FOVF1_MASK) #define SINC_FIFOIS_FOVF2_MASK (0x400U) #define SINC_FIFOIS_FOVF2_SHIFT (10U) /*! FOVF2 - FIFO Overflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FOVF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF2_SHIFT)) & SINC_FIFOIS_FOVF2_MASK) #define SINC_FIFOIS_FOVF3_MASK (0x800U) #define SINC_FIFOIS_FOVF3_SHIFT (11U) /*! FOVF3 - FIFO Overflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FOVF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF3_SHIFT)) & SINC_FIFOIS_FOVF3_MASK) #define SINC_FIFOIS_FOVF4_MASK (0x1000U) #define SINC_FIFOIS_FOVF4_SHIFT (12U) /*! FOVF4 - FIFO Overflow Flag * 0b0..Did not occur * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_FOVF4(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF4_SHIFT)) & SINC_FIFOIS_FOVF4_MASK) #define SINC_FIFOIS_CAD0_MASK (0x10000U) #define SINC_FIFOIS_CAD0_SHIFT (16U) /*! CAD0 - Clock Absence Flag * 0b0..Clock present * 0b1..Clock absent * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_CAD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD0_SHIFT)) & SINC_FIFOIS_CAD0_MASK) #define SINC_FIFOIS_CAD1_MASK (0x20000U) #define SINC_FIFOIS_CAD1_SHIFT (17U) /*! CAD1 - Clock Absence Flag * 0b0..Clock present * 0b1..Clock absent * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_CAD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD1_SHIFT)) & SINC_FIFOIS_CAD1_MASK) #define SINC_FIFOIS_CAD2_MASK (0x40000U) #define SINC_FIFOIS_CAD2_SHIFT (18U) /*! CAD2 - Clock Absence Flag * 0b0..Clock present * 0b1..Clock absent * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_CAD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD2_SHIFT)) & SINC_FIFOIS_CAD2_MASK) #define SINC_FIFOIS_CAD3_MASK (0x80000U) #define SINC_FIFOIS_CAD3_SHIFT (19U) /*! CAD3 - Clock Absence Flag * 0b0..Clock present * 0b1..Clock absent * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_CAD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD3_SHIFT)) & SINC_FIFOIS_CAD3_MASK) #define SINC_FIFOIS_CAD4_MASK (0x100000U) #define SINC_FIFOIS_CAD4_SHIFT (20U) /*! CAD4 - Clock Absence Flag * 0b0..Clock present * 0b1..Clock absent * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_CAD4(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD4_SHIFT)) & SINC_FIFOIS_CAD4_MASK) #define SINC_FIFOIS_SAT0_MASK (0x1000000U) #define SINC_FIFOIS_SAT0_SHIFT (24U) /*! SAT0 - Saturation Flag * 0b0..Not saturated * 0b1..Saturated * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_SAT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT0_SHIFT)) & SINC_FIFOIS_SAT0_MASK) #define SINC_FIFOIS_SAT1_MASK (0x2000000U) #define SINC_FIFOIS_SAT1_SHIFT (25U) /*! SAT1 - Saturation Flag * 0b0..Not saturated * 0b1..Saturated * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_SAT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT1_SHIFT)) & SINC_FIFOIS_SAT1_MASK) #define SINC_FIFOIS_SAT2_MASK (0x4000000U) #define SINC_FIFOIS_SAT2_SHIFT (26U) /*! SAT2 - Saturation Flag * 0b0..Not saturated * 0b1..Saturated * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_SAT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT2_SHIFT)) & SINC_FIFOIS_SAT2_MASK) #define SINC_FIFOIS_SAT3_MASK (0x8000000U) #define SINC_FIFOIS_SAT3_SHIFT (27U) /*! SAT3 - Saturation Flag * 0b0..Not saturated * 0b1..Saturated * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_SAT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT3_SHIFT)) & SINC_FIFOIS_SAT3_MASK) #define SINC_FIFOIS_SAT4_MASK (0x10000000U) #define SINC_FIFOIS_SAT4_SHIFT (28U) /*! SAT4 - Saturation Flag * 0b0..Not saturated * 0b1..Saturated * 0b0..No effect * 0b1..Clear the flag */ #define SINC_FIFOIS_SAT4(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT4_SHIFT)) & SINC_FIFOIS_SAT4_MASK) /*! @} */ /*! @name SR - Status */ /*! @{ */ #define SINC_SR_CIP0_MASK (0x1U) #define SINC_SR_CIP0_SHIFT (0U) /*! CIP0 - Conversion In Progress * 0b0..Not in progress * 0b1..In progress */ #define SINC_SR_CIP0(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP0_SHIFT)) & SINC_SR_CIP0_MASK) #define SINC_SR_CIP1_MASK (0x2U) #define SINC_SR_CIP1_SHIFT (1U) /*! CIP1 - Conversion In Progress * 0b0..Not in progress * 0b1..In progress */ #define SINC_SR_CIP1(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP1_SHIFT)) & SINC_SR_CIP1_MASK) #define SINC_SR_CIP2_MASK (0x4U) #define SINC_SR_CIP2_SHIFT (2U) /*! CIP2 - Conversion In Progress * 0b0..Not in progress * 0b1..In progress */ #define SINC_SR_CIP2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP2_SHIFT)) & SINC_SR_CIP2_MASK) #define SINC_SR_CIP3_MASK (0x8U) #define SINC_SR_CIP3_SHIFT (3U) /*! CIP3 - Conversion In Progress * 0b0..Not in progress * 0b1..In progress */ #define SINC_SR_CIP3(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP3_SHIFT)) & SINC_SR_CIP3_MASK) #define SINC_SR_CIP4_MASK (0x10U) #define SINC_SR_CIP4_SHIFT (4U) /*! CIP4 - Conversion In Progress * 0b0..Not in progress * 0b1..In progress */ #define SINC_SR_CIP4(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CIP4_SHIFT)) & SINC_SR_CIP4_MASK) #define SINC_SR_CHRDY0_MASK (0x100U) #define SINC_SR_CHRDY0_SHIFT (8U) /*! CHRDY0 - Channel Ready For Conversion * 0b0..Not ready * 0b1..Ready */ #define SINC_SR_CHRDY0(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY0_SHIFT)) & SINC_SR_CHRDY0_MASK) #define SINC_SR_CHRDY1_MASK (0x200U) #define SINC_SR_CHRDY1_SHIFT (9U) /*! CHRDY1 - Channel Ready For Conversion * 0b0..Not ready * 0b1..Ready */ #define SINC_SR_CHRDY1(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY1_SHIFT)) & SINC_SR_CHRDY1_MASK) #define SINC_SR_CHRDY2_MASK (0x400U) #define SINC_SR_CHRDY2_SHIFT (10U) /*! CHRDY2 - Channel Ready For Conversion * 0b0..Not ready * 0b1..Ready */ #define SINC_SR_CHRDY2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY2_SHIFT)) & SINC_SR_CHRDY2_MASK) #define SINC_SR_CHRDY3_MASK (0x800U) #define SINC_SR_CHRDY3_SHIFT (11U) /*! CHRDY3 - Channel Ready For Conversion * 0b0..Not ready * 0b1..Ready */ #define SINC_SR_CHRDY3(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY3_SHIFT)) & SINC_SR_CHRDY3_MASK) #define SINC_SR_CHRDY4_MASK (0x1000U) #define SINC_SR_CHRDY4_SHIFT (12U) /*! CHRDY4 - Channel Ready For Conversion * 0b0..Not ready * 0b1..Ready */ #define SINC_SR_CHRDY4(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_CHRDY4_SHIFT)) & SINC_SR_CHRDY4_MASK) #define SINC_SR_FIFOEMPTY0_MASK (0x10000U) #define SINC_SR_FIFOEMPTY0_SHIFT (16U) /*! FIFOEMPTY0 - FIFO Empty * 0b0..Not empty * 0b1..Empty */ #define SINC_SR_FIFOEMPTY0(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY0_SHIFT)) & SINC_SR_FIFOEMPTY0_MASK) #define SINC_SR_FIFOEMPTY1_MASK (0x20000U) #define SINC_SR_FIFOEMPTY1_SHIFT (17U) /*! FIFOEMPTY1 - FIFO Empty * 0b0..Not empty * 0b1..Empty */ #define SINC_SR_FIFOEMPTY1(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY1_SHIFT)) & SINC_SR_FIFOEMPTY1_MASK) #define SINC_SR_FIFOEMPTY2_MASK (0x40000U) #define SINC_SR_FIFOEMPTY2_SHIFT (18U) /*! FIFOEMPTY2 - FIFO Empty * 0b0..Not empty * 0b1..Empty */ #define SINC_SR_FIFOEMPTY2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY2_SHIFT)) & SINC_SR_FIFOEMPTY2_MASK) #define SINC_SR_FIFOEMPTY3_MASK (0x80000U) #define SINC_SR_FIFOEMPTY3_SHIFT (19U) /*! FIFOEMPTY3 - FIFO Empty * 0b0..Not empty * 0b1..Empty */ #define SINC_SR_FIFOEMPTY3(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY3_SHIFT)) & SINC_SR_FIFOEMPTY3_MASK) #define SINC_SR_FIFOEMPTY4_MASK (0x100000U) #define SINC_SR_FIFOEMPTY4_SHIFT (20U) /*! FIFOEMPTY4 - FIFO Empty * 0b0..Not empty * 0b1..Empty */ #define SINC_SR_FIFOEMPTY4(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_FIFOEMPTY4_SHIFT)) & SINC_SR_FIFOEMPTY4_MASK) #define SINC_SR_MCLKRDY0_MASK (0x1000000U) #define SINC_SR_MCLKRDY0_SHIFT (24U) /*! MCLKRDY0 - Modulator Clock 0 Ready * 0b0..Not ready * 0b1..Ready */ #define SINC_SR_MCLKRDY0(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_MCLKRDY0_SHIFT)) & SINC_SR_MCLKRDY0_MASK) #define SINC_SR_MCLKRDY1_MASK (0x2000000U) #define SINC_SR_MCLKRDY1_SHIFT (25U) /*! MCLKRDY1 - Modulator Clock 1 Ready * 0b0..Not ready * 0b1..Ready */ #define SINC_SR_MCLKRDY1(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_MCLKRDY1_SHIFT)) & SINC_SR_MCLKRDY1_MASK) #define SINC_SR_MCLKRDY2_MASK (0x4000000U) #define SINC_SR_MCLKRDY2_SHIFT (26U) /*! MCLKRDY2 - Modulator Clock 2 Ready * 0b0..Not ready * 0b1..Ready */ #define SINC_SR_MCLKRDY2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_MCLKRDY2_SHIFT)) & SINC_SR_MCLKRDY2_MASK) /*! @} */ /*! @name CCR - Channel 0 Control..Channel 4 Control */ /*! @{ */ #define SINC_CCR_CHEN_MASK (0x1U) #define SINC_CCR_CHEN_SHIFT (0U) /*! CHEN - Channel Enable * 0b0..Disables * 0b1..Enables */ #define SINC_CCR_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CHEN_SHIFT)) & SINC_CCR_CHEN_MASK) #define SINC_CCR_PFEN_MASK (0x2U) #define SINC_CCR_PFEN_SHIFT (1U) /*! PFEN - PF Enable * 0b0..Disables * 0b1..Enables */ #define SINC_CCR_PFEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_PFEN_SHIFT)) & SINC_CCR_PFEN_MASK) #define SINC_CCR_DMAEN_MASK (0x8U) #define SINC_CCR_DMAEN_SHIFT (3U) /*! DMAEN - DMA Enable * 0b0..Disables * 0b1..Enables */ #define SINC_CCR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_DMAEN_SHIFT)) & SINC_CCR_DMAEN_MASK) #define SINC_CCR_SCDEN_MASK (0x100U) #define SINC_CCR_SCDEN_SHIFT (8U) /*! SCDEN - Short Circuit Detect Enable * 0b0..Disables * 0b1..Enables */ #define SINC_CCR_SCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_SCDEN_SHIFT)) & SINC_CCR_SCDEN_MASK) #define SINC_CCR_CADEN_MASK (0x200U) #define SINC_CCR_CADEN_SHIFT (9U) /*! CADEN - Clock Absence Detect Enable * 0b0..Disables * 0b1..Enables */ #define SINC_CCR_CADEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK) #define SINC_CCR_ZCDEN_MASK (0x1000U) #define SINC_CCR_ZCDEN_SHIFT (12U) /*! ZCDEN - Zero Cross Detect Enable * 0b0..Disables * 0b1..Enables */ #define SINC_CCR_ZCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_ZCDEN_SHIFT)) & SINC_CCR_ZCDEN_MASK) #define SINC_CCR_LMTEN_MASK (0x2000U) #define SINC_CCR_LMTEN_SHIFT (13U) /*! LMTEN - Limit Enable * 0b0..Disables * 0b1..Enables */ #define SINC_CCR_LMTEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_LMTEN_SHIFT)) & SINC_CCR_LMTEN_MASK) #define SINC_CCR_FIFOEN_MASK (0x4000U) #define SINC_CCR_FIFOEN_SHIFT (14U) /*! FIFOEN - FIFO Enable * 0b0..Disables * 0b1..Enables */ #define SINC_CCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_FIFOEN_SHIFT)) & SINC_CCR_FIFOEN_MASK) #define SINC_CCR_DBGSEL_MASK (0xF00000U) #define SINC_CCR_DBGSEL_SHIFT (20U) /*! DBGSEL - Debug Output Selection * 0b0000..Final data from the PF (24 bits) * 0b0001..Offset data (24 bits) * 0b0010..Shifted data from the PF (24 bits) * 0b0011..DC remover (HPF) data (32 bits) * 0b0100..Raw data from the PF's CIC filter * 0b0110..Historical data from SCD * 0b0111..Data from the Manchester decoder * 0b1000..Data from CAD * 0b1001..Number of available entries in the FIFO * 0b1010..Status of the parallel or serial data converter * *.. */ #define SINC_CCR_DBGSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_DBGSEL_SHIFT)) & SINC_CCR_DBGSEL_MASK) /*! @} */ /* The count of SINC_CCR */ #define SINC_CCR_COUNT (5U) /*! @name CDR - Channel 0 Data Rate..Channel 4 Data Rate */ /*! @{ */ #define SINC_CDR_PFOSR_MASK (0x7FFU) #define SINC_CDR_PFOSR_SHIFT (0U) /*! PFOSR - PF OSR */ #define SINC_CDR_PFOSR(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFOSR_SHIFT)) & SINC_CDR_PFOSR_MASK) #define SINC_CDR_PFORD_MASK (0x1800U) #define SINC_CDR_PFORD_SHIFT (11U) /*! PFORD - PF Order * 0b00..FastSinc * 0b01..First order * 0b10..Second order * 0b11..Third order */ #define SINC_CDR_PFORD(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFORD_SHIFT)) & SINC_CDR_PFORD_MASK) #define SINC_CDR_PFCM_MASK (0xC000U) #define SINC_CDR_PFCM_SHIFT (14U) /*! PFCM - PF Conversion Mode * 0b00..Single * 0b01..Continuous * 0b10..Always * 0b11..Fixed number */ #define SINC_CDR_PFCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFCM_SHIFT)) & SINC_CDR_PFCM_MASK) /*! @} */ /* The count of SINC_CDR */ #define SINC_CDR_COUNT (5U) /*! @name CCFR - Channel 0 Configuration..Channel 4 Configuration */ /*! @{ */ #define SINC_CCFR_PFSFT_MASK (0x1FU) #define SINC_CCFR_PFSFT_SHIFT (0U) /*! PFSFT - PF Shift */ #define SINC_CCFR_PFSFT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_PFSFT_SHIFT)) & SINC_CCFR_PFSFT_MASK) #define SINC_CCFR_RDFMT_MASK (0x40U) #define SINC_CCFR_RDFMT_SHIFT (6U) /*! RDFMT - Result Data Format * 0b0..Left justified, signed * 0b1..Left justified, unsigned */ #define SINC_CCFR_RDFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_RDFMT_SHIFT)) & SINC_CCFR_RDFMT_MASK) #define SINC_CCFR_FIFOWMK_MASK (0x1C00U) #define SINC_CCFR_FIFOWMK_SHIFT (10U) /*! FIFOWMK - FIFO Watermark */ #define SINC_CCFR_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_FIFOWMK_SHIFT)) & SINC_CCFR_FIFOWMK_MASK) #define SINC_CCFR_IBFMT_MASK (0x30000U) #define SINC_CCFR_IBFMT_SHIFT (16U) /*! IBFMT - Input Bit Format * 0b00..External bitstream from the MBIT[n] signal * 0b01..External Manchester code; ICESEL selects the rise or fall decoder * 0b10..Internal 16-bit parallel data from MPDATA * 0b11..Internal 32-bit serial data from MPDATA */ #define SINC_CCFR_IBFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_IBFMT_SHIFT)) & SINC_CCFR_IBFMT_MASK) #define SINC_CCFR_ICSEL_MASK (0x1C0000U) #define SINC_CCFR_ICSEL_SHIFT (18U) /*! ICSEL - Input Clock Select * 0b000..MCLK_OUT0 with internal routeback * 0b001..MCLK_OUT1 with internal routeback * 0b010..MCLK_OUT2 with internal routeback * 0b011..External modulator clock dedicated to this channel * 0b111..Grouped clock shared with an adjacent channel; the adjacent channel's ICSEL field determines the input clock * *.. */ #define SINC_CCFR_ICSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ICSEL_SHIFT)) & SINC_CCFR_ICSEL_MASK) #define SINC_CCFR_ICESEL_MASK (0xE00000U) #define SINC_CCFR_ICESEL_SHIFT (21U) /*! ICESEL - Input Clock Edge Select * 0b001..Positive edge * 0b010..Negative edge * 0b011..Both edges * 0b100..Every other odd positive edge * 0b101..Every other even positive edge * 0b110..Every other odd negative edge * 0b111..Every other even negative edge * *.. */ #define SINC_CCFR_ICESEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ICESEL_SHIFT)) & SINC_CCFR_ICESEL_MASK) #define SINC_CCFR_ITSEL_MASK (0x3000000U) #define SINC_CCFR_ITSEL_SHIFT (24U) /*! ITSEL - Input Trigger Select * 0b00..Software * 0b01..Hardware trigger dedicated to the channel * 0b11..Grouped trigger shared with an adjacent channel; the adjacent channel's ITSEL field determines the trigger * *.. */ #define SINC_CCFR_ITSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ITSEL_SHIFT)) & SINC_CCFR_ITSEL_MASK) #define SINC_CCFR_IBSEL_MASK (0xC000000U) #define SINC_CCFR_IBSEL_SHIFT (26U) /*! IBSEL - Input Bit Select * 0b00..External bitstream from the MBIT[n] signal * 0b01..Alternate internal bitstream from the INP[n] signal * 0b11..Grouped bitstream shared with an adjacent channel; the adjacent channel's IBSEL field determines the input * *.. */ #define SINC_CCFR_IBSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_IBSEL_SHIFT)) & SINC_CCFR_IBSEL_MASK) #define SINC_CCFR_ITLVL_MASK (0x10000000U) #define SINC_CCFR_ITLVL_SHIFT (28U) /*! ITLVL - Input Trigger Level Type * 0b0..Edge * 0b1..Level */ #define SINC_CCFR_ITLVL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ITLVL_SHIFT)) & SINC_CCFR_ITLVL_MASK) #define SINC_CCFR_ZCOP_MASK (0xC0000000U) #define SINC_CCFR_ZCOP_SHIFT (30U) /*! ZCOP - Zero Cross Option * 0b00..Both rise and fall * 0b10..Rise * 0b01..Fall * *.. */ #define SINC_CCFR_ZCOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ZCOP_SHIFT)) & SINC_CCFR_ZCOP_MASK) /*! @} */ /* The count of SINC_CCFR */ #define SINC_CCFR_COUNT (5U) /*! @name CPROT - Channel 0 Protection..Channel 4 Protection */ /*! @{ */ #define SINC_CPROT_SCDLMT_MASK (0xFFU) #define SINC_CPROT_SCDLMT_SHIFT (0U) /*! SCDLMT - SCD Limit Threshold * 0b00000000-0b00000001..Disables SCD * *..Threshold value */ #define SINC_CPROT_SCDLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDLMT_SHIFT)) & SINC_CPROT_SCDLMT_MASK) #define SINC_CPROT_SCDCM_MASK (0x800U) #define SINC_CPROT_SCDCM_SHIFT (11U) /*! SCDCM - SCD Conversion Mode * 0b0..Constantly when CnCR[CHEN] = MCR[MEN] = 1 * 0b1..Only when the PF is performing a conversion */ #define SINC_CPROT_SCDCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDCM_SHIFT)) & SINC_CPROT_SCDCM_MASK) #define SINC_CPROT_SCDOP_MASK (0x3000U) #define SINC_CPROT_SCDOP_SHIFT (12U) /*! SCDOP - SCD Option * 0b00..Both 0 and 1 * 0b01..Only 1 * 0b10..Only 0 * 0b11.. */ #define SINC_CPROT_SCDOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDOP_SHIFT)) & SINC_CPROT_SCDOP_MASK) #define SINC_CPROT_LMTOP_MASK (0xC000U) #define SINC_CPROT_LMTOP_SHIFT (14U) /*! LMTOP - Limit Detection Option * 0b00..Both high and low limits * 0b01..High limit * 0b10..Low limit * 0b11..Windowed value */ #define SINC_CPROT_LMTOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_LMTOP_SHIFT)) & SINC_CPROT_LMTOP_MASK) #define SINC_CPROT_CADLMT_MASK (0xF0000U) #define SINC_CPROT_CADLMT_SHIFT (16U) /*! CADLMT - CAD Limit Threshold * 0b0000..Disables CAD * *..Threshold value */ #define SINC_CPROT_CADLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_CADLMT_SHIFT)) & SINC_CPROT_CADLMT_MASK) #define SINC_CPROT_CADBK_MASK (0x4000000U) #define SINC_CPROT_CADBK_SHIFT (26U) /*! CADBK - CAD Break Signal * 0b0..Disables * 0b1..Enables */ #define SINC_CPROT_CADBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_CADBK_SHIFT)) & SINC_CPROT_CADBK_MASK) #define SINC_CPROT_SCDBK_MASK (0x8000000U) #define SINC_CPROT_SCDBK_SHIFT (27U) /*! SCDBK - SCD Break Signal * 0b0..Disables * 0b1..Enables */ #define SINC_CPROT_SCDBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDBK_SHIFT)) & SINC_CPROT_SCDBK_MASK) #define SINC_CPROT_LLMTBK_MASK (0x20000000U) #define SINC_CPROT_LLMTBK_SHIFT (29U) /*! LLMTBK - Low Limit Break Signal * 0b0..Disables * 0b1..Enables */ #define SINC_CPROT_LLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_LLMTBK_SHIFT)) & SINC_CPROT_LLMTBK_MASK) #define SINC_CPROT_WLMTBK_MASK (0x40000000U) #define SINC_CPROT_WLMTBK_SHIFT (30U) /*! WLMTBK - Window Limit Break Signal * 0b0..Disables * 0b1..Enables */ #define SINC_CPROT_WLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_WLMTBK_SHIFT)) & SINC_CPROT_WLMTBK_MASK) #define SINC_CPROT_HLMTBK_MASK (0x80000000U) #define SINC_CPROT_HLMTBK_SHIFT (31U) /*! HLMTBK - High Limit Break Signal * 0b0..Disables * 0b1..Enables */ #define SINC_CPROT_HLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_HLMTBK_SHIFT)) & SINC_CPROT_HLMTBK_MASK) /*! @} */ /* The count of SINC_CPROT */ #define SINC_CPROT_COUNT (5U) /*! @name CBIAS - Channel 0 Bias..Channel 4 Bias */ /*! @{ */ #define SINC_CBIAS_BIAS_MASK (0xFFFFFF00U) #define SINC_CBIAS_BIAS_SHIFT (8U) /*! BIAS - Bias Value */ #define SINC_CBIAS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CBIAS_BIAS_SHIFT)) & SINC_CBIAS_BIAS_MASK) /*! @} */ /* The count of SINC_CBIAS */ #define SINC_CBIAS_COUNT (5U) /*! @name CLOLMT - Channel 0 Low Limit..Channel 4 Low Limit */ /*! @{ */ #define SINC_CLOLMT_LOLMT_MASK (0xFFFFFF00U) #define SINC_CLOLMT_LOLMT_SHIFT (8U) /*! LOLMT - Low Limit Threshold */ #define SINC_CLOLMT_LOLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CLOLMT_LOLMT_SHIFT)) & SINC_CLOLMT_LOLMT_MASK) /*! @} */ /* The count of SINC_CLOLMT */ #define SINC_CLOLMT_COUNT (5U) /*! @name CHILMT - Channel 0 High Limit..Channel 4 High Limit */ /*! @{ */ #define SINC_CHILMT_HILMT_MASK (0xFFFFFF00U) #define SINC_CHILMT_HILMT_SHIFT (8U) /*! HILMT - High Limit Threshold */ #define SINC_CHILMT_HILMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHILMT_HILMT_SHIFT)) & SINC_CHILMT_HILMT_MASK) /*! @} */ /* The count of SINC_CHILMT */ #define SINC_CHILMT_COUNT (5U) /*! @name CRDATA - Channel 0 Result Data..Channel 4 Result Data */ /*! @{ */ #define SINC_CRDATA_RDATA_MASK (0xFFFFFF00U) #define SINC_CRDATA_RDATA_SHIFT (8U) /*! RDATA - Result Data */ #define SINC_CRDATA_RDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CRDATA_RDATA_SHIFT)) & SINC_CRDATA_RDATA_MASK) /*! @} */ /* The count of SINC_CRDATA */ #define SINC_CRDATA_COUNT (5U) /*! @name CMPDATA - Channel 0 Multipurpose Data..Channel 4 Multipurpose Data */ /*! @{ */ #define SINC_CMPDATA_MPDATA_MASK (0xFFFFFFFFU) #define SINC_CMPDATA_MPDATA_SHIFT (0U) /*! MPDATA - Multipurpose Data */ #define SINC_CMPDATA_MPDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CMPDATA_MPDATA_SHIFT)) & SINC_CMPDATA_MPDATA_MASK) /*! @} */ /* The count of SINC_CMPDATA */ #define SINC_CMPDATA_COUNT (5U) /*! @name CACFR - Channel 0 Advanced Configuration..Channel 4 Advanced Configuration */ /*! @{ */ #define SINC_CACFR_ADMASEL_MASK (0xF000U) #define SINC_CACFR_ADMASEL_SHIFT (12U) /*! ADMASEL - Alternate DMA Source Selection * 0b0000..Alternate DMA disabled * 0b0001..PF conversion complete * 0b0010..PF data output ready * 0b0011..Zero crossing detected * 0b0100..Short circuit detected * 0b0101..Window limit detected * 0b0110..Low limit detected * 0b0111..High limit * 0b1000..FIFO underflow * 0b1001..FIFO overflow * 0b1010..Clock absence * 0b1011..Saturation */ #define SINC_CACFR_ADMASEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_ADMASEL_SHIFT)) & SINC_CACFR_ADMASEL_MASK) #define SINC_CACFR_HPFA_MASK (0xF0000U) #define SINC_CACFR_HPFA_SHIFT (16U) /*! HPFA - HPF DC Remover Alpha Coefficient */ #define SINC_CACFR_HPFA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_HPFA_SHIFT)) & SINC_CACFR_HPFA_MASK) #define SINC_CACFR_IBDLY_MASK (0xF00000U) #define SINC_CACFR_IBDLY_SHIFT (20U) /*! IBDLY - Input Modulator Bitstream Delay * 0b0000..Disabled * *..Delay in clock cycles */ #define SINC_CACFR_IBDLY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_IBDLY_SHIFT)) & SINC_CACFR_IBDLY_MASK) /*! @} */ /* The count of SINC_CACFR */ #define SINC_CACFR_COUNT (5U) /*! @name CSR - Channel 0 Status..Channel 4 Status */ /*! @{ */ #define SINC_CSR_FIFOAVIL_MASK (0x1FU) #define SINC_CSR_FIFOAVIL_SHIFT (0U) /*! FIFOAVIL - FIFO Available Data */ #define SINC_CSR_FIFOAVIL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_FIFOAVIL_SHIFT)) & SINC_CSR_FIFOAVIL_MASK) #define SINC_CSR_PSRDY_MASK (0x80U) #define SINC_CSR_PSRDY_SHIFT (7U) /*! PSRDY - Parallel or Serial Data Ready * 0b0..Not ready * 0b1..Ready */ #define SINC_CSR_PSRDY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_PSRDY_SHIFT)) & SINC_CSR_PSRDY_MASK) #define SINC_CSR_PFSAT_MASK (0x100U) #define SINC_CSR_PFSAT_SHIFT (8U) /*! PFSAT - Primary CIC Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ #define SINC_CSR_PFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_PFSAT_SHIFT)) & SINC_CSR_PFSAT_MASK) #define SINC_CSR_HPFSAT_MASK (0x200U) #define SINC_CSR_HPFSAT_SHIFT (9U) /*! HPFSAT - HPF Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ #define SINC_CSR_HPFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_HPFSAT_SHIFT)) & SINC_CSR_HPFSAT_MASK) #define SINC_CSR_SFTSAT_MASK (0x400U) #define SINC_CSR_SFTSAT_SHIFT (10U) /*! SFTSAT - Shift Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ #define SINC_CSR_SFTSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_SFTSAT_SHIFT)) & SINC_CSR_SFTSAT_MASK) #define SINC_CSR_BIASSAT_MASK (0x800U) #define SINC_CSR_BIASSAT_SHIFT (11U) /*! BIASSAT - Bias Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ #define SINC_CSR_BIASSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_BIASSAT_SHIFT)) & SINC_CSR_BIASSAT_MASK) #define SINC_CSR_RDRS_MASK (0x1000U) #define SINC_CSR_RDRS_SHIFT (12U) /*! RDRS - Result Data Direct Read Status * 0b0..Valid * 0b1..Invalid */ #define SINC_CSR_RDRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_RDRS_SHIFT)) & SINC_CSR_RDRS_MASK) #define SINC_CSR_SRDS_MASK (0x2000U) #define SINC_CSR_SRDS_SHIFT (13U) /*! SRDS - Start Read Debug Data Sync * 0b0..Data valid * 0b1..Procedure in progress * 0b0..No effect * 0b1..Starts the procedure */ #define SINC_CSR_SRDS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_SRDS_SHIFT)) & SINC_CSR_SRDS_MASK) #define SINC_CSR_DBGRS_MASK (0xC000U) #define SINC_CSR_DBGRS_SHIFT (14U) /*! DBGRS - Debug Data Read Status * 0b00..Valid * 0b01-0b11..Invalid */ #define SINC_CSR_DBGRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_DBGRS_SHIFT)) & SINC_CSR_DBGRS_MASK) #define SINC_CSR_CNUM_MASK (0x7F0000U) #define SINC_CSR_CNUM_SHIFT (16U) /*! CNUM - Number Of Conversions */ #define SINC_CSR_CNUM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_CNUM_SHIFT)) & SINC_CSR_CNUM_MASK) #define SINC_CSR_CNUM_OV_MASK (0x800000U) #define SINC_CSR_CNUM_OV_SHIFT (23U) /*! CNUM_OV - Overflow In Number Of Conversions * 0b0..No overflow * 0b1..Overflow */ #define SINC_CSR_CNUM_OV(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_CNUM_OV_SHIFT)) & SINC_CSR_CNUM_OV_MASK) /*! @} */ /* The count of SINC_CSR */ #define SINC_CSR_COUNT (5U) /*! @name CDBGR - Channel 0 Debug..Channel 4 Debug */ /*! @{ */ #define SINC_CDBGR_DBGDATA_MASK (0xFFFFFFFFU) #define SINC_CDBGR_DBGDATA_SHIFT (0U) /*! DBGDATA - Debug Data */ #define SINC_CDBGR_DBGDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDBGR_DBGDATA_SHIFT)) & SINC_CDBGR_DBGDATA_MASK) /*! @} */ /* The count of SINC_CDBGR */ #define SINC_CDBGR_COUNT (5U) /*! * @} */ /* end of group SINC_Register_Masks */ /* SINC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral SINC0 base address */ #define SINC0_BASE (0x50108000u) /** Peripheral SINC0 base address */ #define SINC0_BASE_NS (0x40108000u) /** Peripheral SINC0 base pointer */ #define SINC0 ((SINC_Type *)SINC0_BASE) /** Peripheral SINC0 base pointer */ #define SINC0_NS ((SINC_Type *)SINC0_BASE_NS) /** Array initializer of SINC peripheral base addresses */ #define SINC_BASE_ADDRS { SINC0_BASE } /** Array initializer of SINC peripheral base pointers */ #define SINC_BASE_PTRS { SINC0 } /** Array initializer of SINC peripheral base addresses */ #define SINC_BASE_ADDRS_NS { SINC0_BASE_NS } /** Array initializer of SINC peripheral base pointers */ #define SINC_BASE_PTRS_NS { SINC0_NS } #else /** Peripheral SINC0 base address */ #define SINC0_BASE (0x40108000u) /** Peripheral SINC0 base pointer */ #define SINC0 ((SINC_Type *)SINC0_BASE) /** Array initializer of SINC peripheral base addresses */ #define SINC_BASE_ADDRS { SINC0_BASE } /** Array initializer of SINC peripheral base pointers */ #define SINC_BASE_PTRS { SINC0 } #endif /*! * @} */ /* end of group SINC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SMARTDMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SMARTDMA_Peripheral_Access_Layer SMARTDMA Peripheral Access Layer * @{ */ /** SMARTDMA - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[32]; __IO uint32_t BOOTADR; /**< Boot Address, offset: 0x20 */ __IO uint32_t CTRL; /**< Control, offset: 0x24 */ __I uint32_t PC; /**< Program Counter, offset: 0x28 */ __I uint32_t SP; /**< Stack Pointer, offset: 0x2C */ __IO uint32_t BREAK_ADDR; /**< Breakpoint Address, offset: 0x30 */ __IO uint32_t BREAK_VECT; /**< Breakpoint Vector, offset: 0x34 */ __IO uint32_t EMER_VECT; /**< Emergency Vector, offset: 0x38 */ __IO uint32_t EMER_SEL; /**< Emergency Select, offset: 0x3C */ __IO uint32_t ARM2EZH; /**< ARM to EZH Interrupt Control, offset: 0x40 */ __IO uint32_t EZH2ARM; /**< EZH to ARM Trigger, offset: 0x44 */ __IO uint32_t PENDTRAP; /**< Pending Trap Control, offset: 0x48 */ } SMARTDMA_Type; /* ---------------------------------------------------------------------------- -- SMARTDMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SMARTDMA_Register_Masks SMARTDMA Register Masks * @{ */ /*! @name BOOTADR - Boot Address */ /*! @{ */ #define SMARTDMA_BOOTADR_ADDR_MASK (0xFFFFFFFCU) #define SMARTDMA_BOOTADR_ADDR_SHIFT (2U) /*! ADDR - 32-bit boot address, the boot address should be 4-byte aligned. */ #define SMARTDMA_BOOTADR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BOOTADR_ADDR_SHIFT)) & SMARTDMA_BOOTADR_ADDR_MASK) /*! @} */ /*! @name CTRL - Control */ /*! @{ */ #define SMARTDMA_CTRL_START_MASK (0x1U) #define SMARTDMA_CTRL_START_SHIFT (0U) /*! START - Start Bit Ignition */ #define SMARTDMA_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_START_SHIFT)) & SMARTDMA_CTRL_START_MASK) #define SMARTDMA_CTRL_EXF_MASK (0x2U) #define SMARTDMA_CTRL_EXF_SHIFT (1U) /*! EXF - External Flag */ #define SMARTDMA_CTRL_EXF(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_EXF_SHIFT)) & SMARTDMA_CTRL_EXF_MASK) #define SMARTDMA_CTRL_ERRDIS_MASK (0x4U) #define SMARTDMA_CTRL_ERRDIS_SHIFT (2U) /*! ERRDIS - Error Disable */ #define SMARTDMA_CTRL_ERRDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_ERRDIS_SHIFT)) & SMARTDMA_CTRL_ERRDIS_MASK) #define SMARTDMA_CTRL_BUFEN_MASK (0x8U) #define SMARTDMA_CTRL_BUFEN_SHIFT (3U) /*! BUFEN - Buffer Enable */ #define SMARTDMA_CTRL_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_BUFEN_SHIFT)) & SMARTDMA_CTRL_BUFEN_MASK) #define SMARTDMA_CTRL_SYNCEN_MASK (0x10U) #define SMARTDMA_CTRL_SYNCEN_SHIFT (4U) /*! SYNCEN - Sync Enable */ #define SMARTDMA_CTRL_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_SYNCEN_SHIFT)) & SMARTDMA_CTRL_SYNCEN_MASK) #define SMARTDMA_CTRL_WKEY_MASK (0xFFFF0000U) #define SMARTDMA_CTRL_WKEY_SHIFT (16U) /*! WKEY - Write Key */ #define SMARTDMA_CTRL_WKEY(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_WKEY_SHIFT)) & SMARTDMA_CTRL_WKEY_MASK) /*! @} */ /*! @name PC - Program Counter */ /*! @{ */ #define SMARTDMA_PC_PC_MASK (0xFFFFFFFFU) #define SMARTDMA_PC_PC_SHIFT (0U) /*! PC - Program Counter */ #define SMARTDMA_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PC_PC_SHIFT)) & SMARTDMA_PC_PC_MASK) /*! @} */ /*! @name SP - Stack Pointer */ /*! @{ */ #define SMARTDMA_SP_SP_MASK (0xFFFFFFFFU) #define SMARTDMA_SP_SP_SHIFT (0U) /*! SP - Stack Pointer */ #define SMARTDMA_SP_SP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_SP_SP_SHIFT)) & SMARTDMA_SP_SP_MASK) /*! @} */ /*! @name BREAK_ADDR - Breakpoint Address */ /*! @{ */ #define SMARTDMA_BREAK_ADDR_ADDR_MASK (0xFFFFFFFCU) #define SMARTDMA_BREAK_ADDR_ADDR_SHIFT (2U) /*! ADDR - 32-bit address to swap to EZHB_BREAK_VECT location */ #define SMARTDMA_BREAK_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_ADDR_ADDR_SHIFT)) & SMARTDMA_BREAK_ADDR_ADDR_MASK) /*! @} */ /*! @name BREAK_VECT - Breakpoint Vector */ /*! @{ */ #define SMARTDMA_BREAK_VECT_VEC_MASK (0xFFFFFFFCU) #define SMARTDMA_BREAK_VECT_VEC_SHIFT (2U) /*! VEC - Vector address of user debug routine. */ #define SMARTDMA_BREAK_VECT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_VECT_VEC_SHIFT)) & SMARTDMA_BREAK_VECT_VEC_MASK) /*! @} */ /*! @name EMER_VECT - Emergency Vector */ /*! @{ */ #define SMARTDMA_EMER_VECT_VEC_MASK (0xFFFFFFFCU) #define SMARTDMA_EMER_VECT_VEC_SHIFT (2U) /*! VEC - Vector address of emergency code routine */ #define SMARTDMA_EMER_VECT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_VECT_VEC_SHIFT)) & SMARTDMA_EMER_VECT_VEC_MASK) /*! @} */ /*! @name EMER_SEL - Emergency Select */ /*! @{ */ #define SMARTDMA_EMER_SEL_EN_MASK (0x100U) #define SMARTDMA_EMER_SEL_EN_SHIFT (8U) /*! EN - Emergency code routine */ #define SMARTDMA_EMER_SEL_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_EN_SHIFT)) & SMARTDMA_EMER_SEL_EN_MASK) #define SMARTDMA_EMER_SEL_RQ_MASK (0x200U) #define SMARTDMA_EMER_SEL_RQ_SHIFT (9U) /*! RQ - Software emergency request */ #define SMARTDMA_EMER_SEL_RQ(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_RQ_SHIFT)) & SMARTDMA_EMER_SEL_RQ_MASK) /*! @} */ /*! @name ARM2EZH - ARM to EZH Interrupt Control */ /*! @{ */ #define SMARTDMA_ARM2EZH_IE_MASK (0x3U) #define SMARTDMA_ARM2EZH_IE_SHIFT (0U) /*! IE - Interrupt Enable */ #define SMARTDMA_ARM2EZH_IE(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_IE_SHIFT)) & SMARTDMA_ARM2EZH_IE_MASK) #define SMARTDMA_ARM2EZH_GP_MASK (0xFFFFFFFCU) #define SMARTDMA_ARM2EZH_GP_SHIFT (2U) /*! GP - General purpose register bits */ #define SMARTDMA_ARM2EZH_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_GP_SHIFT)) & SMARTDMA_ARM2EZH_GP_MASK) /*! @} */ /*! @name EZH2ARM - EZH to ARM Trigger */ /*! @{ */ #define SMARTDMA_EZH2ARM_GP_MASK (0xFFFFFFFFU) #define SMARTDMA_EZH2ARM_GP_SHIFT (0U) /*! GP - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH [1:0] == 2h */ #define SMARTDMA_EZH2ARM_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EZH2ARM_GP_SHIFT)) & SMARTDMA_EZH2ARM_GP_MASK) /*! @} */ /*! @name PENDTRAP - Pending Trap Control */ /*! @{ */ #define SMARTDMA_PENDTRAP_STATUS_MASK (0xFFU) #define SMARTDMA_PENDTRAP_STATUS_SHIFT (0U) /*! STATUS - Status Flag or Pending Trap Request */ #define SMARTDMA_PENDTRAP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_STATUS_SHIFT)) & SMARTDMA_PENDTRAP_STATUS_MASK) #define SMARTDMA_PENDTRAP_POL_MASK (0xFF00U) #define SMARTDMA_PENDTRAP_POL_SHIFT (8U) /*! POL - Polarity */ #define SMARTDMA_PENDTRAP_POL(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_POL_SHIFT)) & SMARTDMA_PENDTRAP_POL_MASK) #define SMARTDMA_PENDTRAP_EN_MASK (0xFF0000U) #define SMARTDMA_PENDTRAP_EN_SHIFT (16U) /*! EN - Enable Pending Trap */ #define SMARTDMA_PENDTRAP_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_EN_SHIFT)) & SMARTDMA_PENDTRAP_EN_MASK) /*! @} */ /*! * @} */ /* end of group SMARTDMA_Register_Masks */ /* SMARTDMA - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral SMARTDMA0 base address */ #define SMARTDMA0_BASE (0x50033000u) /** Peripheral SMARTDMA0 base address */ #define SMARTDMA0_BASE_NS (0x40033000u) /** Peripheral SMARTDMA0 base pointer */ #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) /** Peripheral SMARTDMA0 base pointer */ #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) /** Array initializer of SMARTDMA peripheral base addresses */ #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } /** Array initializer of SMARTDMA peripheral base pointers */ #define SMARTDMA_BASE_PTRS { SMARTDMA0 } /** Array initializer of SMARTDMA peripheral base addresses */ #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } /** Array initializer of SMARTDMA peripheral base pointers */ #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } #else /** Peripheral SMARTDMA0 base address */ #define SMARTDMA0_BASE (0x40033000u) /** Peripheral SMARTDMA0 base pointer */ #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) /** Array initializer of SMARTDMA peripheral base addresses */ #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } /** Array initializer of SMARTDMA peripheral base pointers */ #define SMARTDMA_BASE_PTRS { SMARTDMA0 } #endif /*! * @} */ /* end of group SMARTDMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SPC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer * @{ */ /** SPC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t SC; /**< Status Control, offset: 0x10 */ __IO uint32_t CNTRL; /**< SPC Regulator Control, offset: 0x14 */ uint8_t RESERVED_1[4]; __IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1C */ uint8_t RESERVED_2[16]; __IO uint32_t PD_STATUS[2]; /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */ uint8_t RESERVED_3[8]; __IO uint32_t SRAMCTL; /**< SRAM Control, offset: 0x40 */ uint8_t RESERVED_4[188]; __IO uint32_t ACTIVE_CFG; /**< Active Power Mode Configuration, offset: 0x100 */ __IO uint32_t ACTIVE_CFG1; /**< Active Power Mode Configuration 1, offset: 0x104 */ __IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x108 */ __IO uint32_t LP_CFG1; /**< Low Power Mode Configuration 1, offset: 0x10C */ uint8_t RESERVED_5[16]; __IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */ __IO uint32_t ACTIVE_VDELAY; /**< Active Voltage Trim Delay, offset: 0x124 */ uint8_t RESERVED_6[8]; __IO uint32_t VD_STAT; /**< Voltage Detect Status, offset: 0x130 */ __IO uint32_t VD_CORE_CFG; /**< Core Voltage Detect Configuration, offset: 0x134 */ __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ __IO uint32_t VD_IO_CFG; /**< IO Voltage Detect Configuration, offset: 0x13C */ __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ __IO uint32_t GLITCH_DETECT_SC; /**< Glitch Detect Status Control, offset: 0x144 */ uint8_t RESERVED_7[440]; __IO uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ uint8_t RESERVED_8[252]; __IO uint32_t SYSLDO_CFG; /**< LDO_SYS Configuration, offset: 0x400 */ uint8_t RESERVED_9[252]; __IO uint32_t DCDC_CFG; /**< DCDC Configuration, offset: 0x500 */ __IO uint32_t DCDC_BURST_CFG; /**< DCDC Burst Configuration, offset: 0x504 */ } SPC_Type; /* ---------------------------------------------------------------------------- -- SPC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPC_Register_Masks SPC Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define SPC_VERID_FEATURE_MASK (0xFFFFU) #define SPC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features * *.. */ #define SPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK) #define SPC_VERID_MINOR_MASK (0xFF0000U) #define SPC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define SPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK) #define SPC_VERID_MAJOR_MASK (0xFF000000U) #define SPC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define SPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK) /*! @} */ /*! @name SC - Status Control */ /*! @{ */ #define SPC_SC_BUSY_MASK (0x1U) #define SPC_SC_BUSY_SHIFT (0U) /*! BUSY - SPC Busy Status Flag * 0b0..Not busy * 0b1..Busy */ #define SPC_SC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK) #define SPC_SC_SPC_LP_REQ_MASK (0x2U) #define SPC_SC_SPC_LP_REQ_SHIFT (1U) /*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag * 0b0..SPC is in Active or Sleep mode; the ACTIVE_CFG register has control * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register * 0b0..No effect * 0b1..Clear the flag */ #define SPC_SC_SPC_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK) #define SPC_SC_SPC_LP_MODE_MASK (0xF0U) #define SPC_SC_SPC_LP_MODE_SHIFT (4U) /*! SPC_LP_MODE - Power Domain Low-Power Mode Request * 0b0000..Sleep mode with system clock running * 0b0001..DSLEEP with system clock off * 0b0010..PDOWN with system clock off * 0b0100.. * 0b1000..DPDOWN with system clock off */ #define SPC_SC_SPC_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK) #define SPC_SC_ISO_CLR_MASK (0x30000U) #define SPC_SC_ISO_CLR_SHIFT (16U) /*! ISO_CLR - Isolation Clear Flags */ #define SPC_SC_ISO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK) /*! @} */ /*! @name CNTRL - SPC Regulator Control */ /*! @{ */ #define SPC_CNTRL_CORELDO_EN_MASK (0x1U) #define SPC_CNTRL_CORELDO_EN_SHIFT (0U) /*! CORELDO_EN - LDO_CORE Regulator Enable * 0b0..Disable * 0b1..Enable */ #define SPC_CNTRL_CORELDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK) #define SPC_CNTRL_SYSLDO_EN_MASK (0x2U) #define SPC_CNTRL_SYSLDO_EN_SHIFT (1U) /*! SYSLDO_EN - LDO_SYS Regulator Enable * 0b0..Disable * 0b1..Enable */ #define SPC_CNTRL_SYSLDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_SYSLDO_EN_SHIFT)) & SPC_CNTRL_SYSLDO_EN_MASK) #define SPC_CNTRL_DCDC_EN_MASK (0x4U) #define SPC_CNTRL_DCDC_EN_SHIFT (2U) /*! DCDC_EN - DCDC_CORE Regulator Enable * 0b0..Disable * 0b1..Enable */ #define SPC_CNTRL_DCDC_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_DCDC_EN_SHIFT)) & SPC_CNTRL_DCDC_EN_MASK) /*! @} */ /*! @name LPREQ_CFG - Low-Power Request Configuration */ /*! @{ */ #define SPC_LPREQ_CFG_LPREQOE_MASK (0x1U) #define SPC_LPREQ_CFG_LPREQOE_SHIFT (0U) /*! LPREQOE - Low-Power Request Output Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LPREQ_CFG_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK) #define SPC_LPREQ_CFG_LPREQPOL_MASK (0x2U) #define SPC_LPREQ_CFG_LPREQPOL_SHIFT (1U) /*! LPREQPOL - Low-Power Request Output Pin Polarity Control * 0b0..High * 0b1..Low */ #define SPC_LPREQ_CFG_LPREQPOL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK) #define SPC_LPREQ_CFG_LPREQOV_MASK (0xCU) #define SPC_LPREQ_CFG_LPREQOV_SHIFT (2U) /*! LPREQOV - Low-Power Request Output Override * 0b00..Not forced * 0b01.. * 0b10..Forced low (ignore LPREQPOL settings) * 0b11..Forced high (ignore LPREQPOL settings) */ #define SPC_LPREQ_CFG_LPREQOV(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK) /*! @} */ /*! @name PD_STATUS - SPC Power Domain Mode Status */ /*! @{ */ #define SPC_PD_STATUS_PWR_REQ_STATUS_MASK (0x1U) #define SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT (0U) /*! PWR_REQ_STATUS - Power Request Status Flag * 0b0..Did not request * 0b1..Requested */ #define SPC_PD_STATUS_PWR_REQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT)) & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) #define SPC_PD_STATUS_PD_LP_REQ_MASK (0x10U) #define SPC_PD_STATUS_PD_LP_REQ_SHIFT (4U) /*! PD_LP_REQ - Power Domain Low Power Request Flag * 0b0..Did not request * 0b1..Requested */ #define SPC_PD_STATUS_PD_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK) #define SPC_PD_STATUS_LP_MODE_MASK (0xF00U) #define SPC_PD_STATUS_LP_MODE_SHIFT (8U) /*! LP_MODE - Power Domain Low Power Mode Request * 0b0000..SLEEP with system clock running * 0b0001..DSLEEP with system clock off * 0b0010..PDOWN with system clock off * 0b0100.. * 0b1000..DPDOWN with system clock off */ #define SPC_PD_STATUS_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK) /*! @} */ /* The count of SPC_PD_STATUS */ #define SPC_PD_STATUS_COUNT (2U) /*! @name SRAMCTL - SRAM Control */ /*! @{ */ #define SPC_SRAMCTL_VSM_MASK (0x3U) #define SPC_SRAMCTL_VSM_SHIFT (0U) /*! VSM - Voltage Select Margin * 0b00.. * 0b01..1.0 V * 0b10..1.1 V * 0b11.. */ #define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) #define SPC_SRAMCTL_REQ_MASK (0x40000000U) #define SPC_SRAMCTL_REQ_SHIFT (30U) /*! REQ - SRAM Voltage Update Request * 0b0..Do not request * 0b1..Request */ #define SPC_SRAMCTL_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK) #define SPC_SRAMCTL_ACK_MASK (0x80000000U) #define SPC_SRAMCTL_ACK_SHIFT (31U) /*! ACK - SRAM Voltage Update Request Acknowledge * 0b0..Not acknowledged * 0b1..Acknowledged */ #define SPC_SRAMCTL_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK) /*! @} */ /*! @name ACTIVE_CFG - Active Power Mode Configuration */ /*! @{ */ #define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK (0x1U) #define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT (0U) /*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength * 0b0..Low * 0b1..Normal */ #define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level * 0b00.. * 0b01..Regulate to mid voltage (1.0 V) * 0b10..Regulate to normal voltage (1.1 V) * 0b11..Regulate to overdrive voltage (1.2 V) */ #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) #define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK (0x10U) #define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT (4U) /*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength * 0b0..Low * 0b1..Normal */ #define SPC_ACTIVE_CFG_SYSLDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) #define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK (0x40U) #define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT (6U) /*! SYSLDO_VDD_LVL - LDO_SYS VDD Regulator Voltage Level * 0b0..Normal voltage (1.8 V) * 0b1..Overdrive voltage (2.5 V) */ #define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) #define SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK (0x300U) #define SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT (8U) /*! DCDC_VDD_DS - DCDC VDD Drive Strength * 0b01..Low * 0b10..Normal * *.. */ #define SPC_ACTIVE_CFG_DCDC_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) #define SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level * 0b00..Reserved * 0b01..Midvoltage (1.0 V) * 0b10..Normal voltage (1.1 V) * 0b11..Overdrive voltage (1.2 V) */ #define SPC_ACTIVE_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) /*! GLITCH_DETECT_DISABLE - Glitch Detect Disable * 0b0..Low Voltage Glitch Detect enabled * 0b1..Low Voltage Glitch Detect disabled */ #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) #define SPC_ACTIVE_CFG_LPBUFF_EN_MASK (0x40000U) #define SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT (18U) /*! LPBUFF_EN - CMP Bandgap Buffer Enable * 0b0..Disable * 0b1..Enable */ #define SPC_ACTIVE_CFG_LPBUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT)) & SPC_ACTIVE_CFG_LPBUFF_EN_MASK) #define SPC_ACTIVE_CFG_BGMODE_MASK (0x300000U) #define SPC_ACTIVE_CFG_BGMODE_SHIFT (20U) /*! BGMODE - Bandgap Mode * 0b00..Bandgap disabled * 0b01..Bandgap enabled, buffer disabled * 0b10..Bandgap enabled, buffer enabled * 0b11.. */ #define SPC_ACTIVE_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK) #define SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK (0x800000U) #define SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT (23U) /*! VDD_VD_DISABLE - VDD Voltage Detect Disable * 0b0..Enable * 0b1..Disable */ #define SPC_ACTIVE_CFG_VDD_VD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK) #define SPC_ACTIVE_CFG_CORE_LVDE_MASK (0x1000000U) #define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT (24U) /*! CORE_LVDE - Core Low-Voltage Detection Enable * 0b0..Disable * 0b1..Enable */ #define SPC_ACTIVE_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK) #define SPC_ACTIVE_CFG_SYS_LVDE_MASK (0x2000000U) #define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT (25U) /*! SYS_LVDE - System Low-Voltage Detection Enable * 0b0..Disable * 0b1..Enable */ #define SPC_ACTIVE_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK) #define SPC_ACTIVE_CFG_IO_LVDE_MASK (0x4000000U) #define SPC_ACTIVE_CFG_IO_LVDE_SHIFT (26U) /*! IO_LVDE - IO Low-Voltage Detection Enable * 0b0..Disable * 0b1..Enable */ #define SPC_ACTIVE_CFG_IO_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_LVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_LVDE_MASK) #define SPC_ACTIVE_CFG_CORE_HVDE_MASK (0x8000000U) #define SPC_ACTIVE_CFG_CORE_HVDE_SHIFT (27U) /*! CORE_HVDE - Core High-Voltage Detection Enable * 0b0..Disable * 0b1..Enable */ #define SPC_ACTIVE_CFG_CORE_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_HVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_HVDE_MASK) #define SPC_ACTIVE_CFG_SYS_HVDE_MASK (0x10000000U) #define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT (28U) /*! SYS_HVDE - System High-Voltage Detection Enable * 0b0..Disable * 0b1..Enable */ #define SPC_ACTIVE_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) #define SPC_ACTIVE_CFG_IO_HVDE_MASK (0x20000000U) #define SPC_ACTIVE_CFG_IO_HVDE_SHIFT (29U) /*! IO_HVDE - IO High-Voltage Detection Enable * 0b0..Disable * 0b1..Enable */ #define SPC_ACTIVE_CFG_IO_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_HVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_HVDE_MASK) /*! @} */ /*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */ /*! @{ */ #define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) #define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT (0U) /*! SOC_CNTRL - Active Config Chip Control */ #define SPC_ACTIVE_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK) /*! @} */ /*! @name LP_CFG - Low-Power Mode Configuration */ /*! @{ */ #define SPC_LP_CFG_CORELDO_VDD_DS_MASK (0x1U) #define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT (0U) /*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength * 0b0..Low * 0b1..Normal */ #define SPC_LP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK) #define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) #define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level * 0b00..Retention voltage * 0b01..Mid voltage (1.0 V) * 0b10..Normal voltage (1.1 V) * 0b11..Overdrive voltage (1.2 V) */ #define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) #define SPC_LP_CFG_SYSLDO_VDD_DS_MASK (0x10U) #define SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT (4U) /*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength * 0b0..Low * 0b1..Normal */ #define SPC_LP_CFG_SYSLDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) #define SPC_LP_CFG_DCDC_VDD_DS_MASK (0x300U) #define SPC_LP_CFG_DCDC_VDD_DS_SHIFT (8U) /*! DCDC_VDD_DS - DCDC VDD Drive Strength * 0b00..Pulse refresh * 0b01..Low * 0b10..Normal * 0b11.. */ #define SPC_LP_CFG_DCDC_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_DS_SHIFT)) & SPC_LP_CFG_DCDC_VDD_DS_MASK) #define SPC_LP_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level * 0b00..Retention voltage (0.7 V) * 0b01..Mid voltage (1.0 V) * 0b10..Normal voltage (1.1 V) * 0b11..Overdrive voltage (1.2 V) */ #define SPC_LP_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_LP_CFG_DCDC_VDD_LVL_MASK) #define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) #define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) /*! GLITCH_DETECT_DISABLE - Glitch Detect Disable * 0b0..Enable * 0b1..Disable */ #define SPC_LP_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) #define SPC_LP_CFG_COREVDD_IVS_EN_MASK (0x20000U) #define SPC_LP_CFG_COREVDD_IVS_EN_SHIFT (17U) /*! COREVDD_IVS_EN - CORE VDD Internal Voltage Scaling (IVS) Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LP_CFG_COREVDD_IVS_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_COREVDD_IVS_EN_SHIFT)) & SPC_LP_CFG_COREVDD_IVS_EN_MASK) #define SPC_LP_CFG_LPBUFF_EN_MASK (0x40000U) #define SPC_LP_CFG_LPBUFF_EN_SHIFT (18U) /*! LPBUFF_EN - CMP Bandgap Buffer Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LP_CFG_LPBUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LPBUFF_EN_SHIFT)) & SPC_LP_CFG_LPBUFF_EN_MASK) #define SPC_LP_CFG_BGMODE_MASK (0x300000U) #define SPC_LP_CFG_BGMODE_SHIFT (20U) /*! BGMODE - Bandgap Mode * 0b00..Bandgap disabled * 0b01..Bandgap enabled, buffer disabled * 0b10..Bandgap enabled, buffer enabled * 0b11.. */ #define SPC_LP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK) #define SPC_LP_CFG_LP_IREFEN_MASK (0x800000U) #define SPC_LP_CFG_LP_IREFEN_SHIFT (23U) /*! LP_IREFEN - Low-Power IREF Enable * 0b0..Disable for power saving in Deep Power Down mode * 0b1..Enable */ #define SPC_LP_CFG_LP_IREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK) #define SPC_LP_CFG_CORE_LVDE_MASK (0x1000000U) #define SPC_LP_CFG_CORE_LVDE_SHIFT (24U) /*! CORE_LVDE - Core Low Voltage Detect Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK) #define SPC_LP_CFG_SYS_LVDE_MASK (0x2000000U) #define SPC_LP_CFG_SYS_LVDE_SHIFT (25U) /*! SYS_LVDE - System Low Voltage Detect Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK) #define SPC_LP_CFG_IO_LVDE_MASK (0x4000000U) #define SPC_LP_CFG_IO_LVDE_SHIFT (26U) /*! IO_LVDE - IO Low Voltage Detect Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LP_CFG_IO_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_LVDE_SHIFT)) & SPC_LP_CFG_IO_LVDE_MASK) #define SPC_LP_CFG_CORE_HVDE_MASK (0x8000000U) #define SPC_LP_CFG_CORE_HVDE_SHIFT (27U) /*! CORE_HVDE - Core High Voltage Detect Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LP_CFG_CORE_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_HVDE_SHIFT)) & SPC_LP_CFG_CORE_HVDE_MASK) #define SPC_LP_CFG_SYS_HVDE_MASK (0x10000000U) #define SPC_LP_CFG_SYS_HVDE_SHIFT (28U) /*! SYS_HVDE - System High Voltage Detect Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK) #define SPC_LP_CFG_IO_HVDE_MASK (0x20000000U) #define SPC_LP_CFG_IO_HVDE_SHIFT (29U) /*! IO_HVDE - IO High Voltage Detect Enable * 0b0..Disable * 0b1..Enable */ #define SPC_LP_CFG_IO_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_HVDE_SHIFT)) & SPC_LP_CFG_IO_HVDE_MASK) /*! @} */ /*! @name LP_CFG1 - Low Power Mode Configuration 1 */ /*! @{ */ #define SPC_LP_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) #define SPC_LP_CFG1_SOC_CNTRL_SHIFT (0U) /*! SOC_CNTRL - Low-Power Configuration Chip Control */ #define SPC_LP_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK) /*! @} */ /*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */ /*! @{ */ #define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK (0xFFFFU) #define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT (0U) /*! LPWKUP_DELAY - Low-Power Wake-Up Delay */ #define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK) /*! @} */ /*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */ /*! @{ */ #define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK (0xFFFFU) #define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT (0U) /*! ACTIVE_VDELAY - Active Voltage Delay */ #define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK) /*! @} */ /*! @name VD_STAT - Voltage Detect Status */ /*! @{ */ #define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) #define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) /*! COREVDD_LVDF - Core Low-Voltage Detect Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect * 0b1..Clear the flag */ #define SPC_VD_STAT_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK) #define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) #define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) /*! SYSVDD_LVDF - System Low-Voltage Detect Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect * 0b1..Clear the flag */ #define SPC_VD_STAT_SYSVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK) #define SPC_VD_STAT_IOVDD_LVDF_MASK (0x4U) #define SPC_VD_STAT_IOVDD_LVDF_SHIFT (2U) /*! IOVDD_LVDF - IO VDD LVD Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect * 0b1..Clear the flag */ #define SPC_VD_STAT_IOVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_LVDF_SHIFT)) & SPC_VD_STAT_IOVDD_LVDF_MASK) #define SPC_VD_STAT_COREVDD_HVDF_MASK (0x10U) #define SPC_VD_STAT_COREVDD_HVDF_SHIFT (4U) /*! COREVDD_HVDF - Core VDD HVD Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect * 0b1..Clear the flag */ #define SPC_VD_STAT_COREVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_HVDF_SHIFT)) & SPC_VD_STAT_COREVDD_HVDF_MASK) #define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) #define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) /*! SYSVDD_HVDF - System HVD Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect * 0b1..Clear the flag */ #define SPC_VD_STAT_SYSVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK) #define SPC_VD_STAT_IOVDD_HVDF_MASK (0x40U) #define SPC_VD_STAT_IOVDD_HVDF_SHIFT (6U) /*! IOVDD_HVDF - IO VDD HVD Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect * 0b1..Clear the flag */ #define SPC_VD_STAT_IOVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_HVDF_SHIFT)) & SPC_VD_STAT_IOVDD_HVDF_MASK) /*! @} */ /*! @name VD_CORE_CFG - Core Voltage Detect Configuration */ /*! @{ */ #define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) #define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) /*! LVDRE - Core LVD Reset Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_CORE_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK) #define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) #define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) /*! LVDIE - Core LVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_CORE_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK) #define SPC_VD_CORE_CFG_HVDRE_MASK (0x4U) #define SPC_VD_CORE_CFG_HVDRE_SHIFT (2U) /*! HVDRE - Core VDD HVD Reset Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_CORE_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDRE_SHIFT)) & SPC_VD_CORE_CFG_HVDRE_MASK) #define SPC_VD_CORE_CFG_HVDIE_MASK (0x8U) #define SPC_VD_CORE_CFG_HVDIE_SHIFT (3U) /*! HVDIE - Core VDD HVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_CORE_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDIE_SHIFT)) & SPC_VD_CORE_CFG_HVDIE_MASK) #define SPC_VD_CORE_CFG_LOCK_MASK (0x10000U) #define SPC_VD_CORE_CFG_LOCK_SHIFT (16U) /*! LOCK - Core Voltage Detect Reset Enable Lock * 0b0..Allow * 0b1..Deny */ #define SPC_VD_CORE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK) /*! @} */ /*! @name VD_SYS_CFG - System Voltage Detect Configuration */ /*! @{ */ #define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) #define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) /*! LVDRE - System LVD Reset Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_SYS_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK) #define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) #define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) /*! LVDIE - System LVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_SYS_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK) #define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) #define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) /*! HVDRE - System HVD Reset Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_SYS_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK) #define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) #define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) /*! HVDIE - System HVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) #define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) #define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) /*! LOCK - System Voltage Detect Reset Enable Lock * 0b0..Allow * 0b1..Deny */ #define SPC_VD_SYS_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK) /*! @} */ /*! @name VD_IO_CFG - IO Voltage Detect Configuration */ /*! @{ */ #define SPC_VD_IO_CFG_LVDRE_MASK (0x1U) #define SPC_VD_IO_CFG_LVDRE_SHIFT (0U) /*! LVDRE - IO VDD LVD Reset Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_IO_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDRE_SHIFT)) & SPC_VD_IO_CFG_LVDRE_MASK) #define SPC_VD_IO_CFG_LVDIE_MASK (0x2U) #define SPC_VD_IO_CFG_LVDIE_SHIFT (1U) /*! LVDIE - IO VDD LVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_IO_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDIE_SHIFT)) & SPC_VD_IO_CFG_LVDIE_MASK) #define SPC_VD_IO_CFG_HVDRE_MASK (0x4U) #define SPC_VD_IO_CFG_HVDRE_SHIFT (2U) /*! HVDRE - IO VDD HVD Reset Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_IO_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDRE_SHIFT)) & SPC_VD_IO_CFG_HVDRE_MASK) #define SPC_VD_IO_CFG_HVDIE_MASK (0x8U) #define SPC_VD_IO_CFG_HVDIE_SHIFT (3U) /*! HVDIE - IO VDD HVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_IO_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDIE_SHIFT)) & SPC_VD_IO_CFG_HVDIE_MASK) #define SPC_VD_IO_CFG_LVSEL_MASK (0x100U) #define SPC_VD_IO_CFG_LVSEL_SHIFT (8U) /*! LVSEL - IO VDD Low-Voltage Level Select * 0b0..High range * 0b1..Low range */ #define SPC_VD_IO_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVSEL_SHIFT)) & SPC_VD_IO_CFG_LVSEL_MASK) #define SPC_VD_IO_CFG_LOCK_MASK (0x10000U) #define SPC_VD_IO_CFG_LOCK_SHIFT (16U) /*! LOCK - IO Voltage Detect Reset Enable Lock * 0b0..Allow * 0b1..Deny */ #define SPC_VD_IO_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LOCK_SHIFT)) & SPC_VD_IO_CFG_LOCK_MASK) /*! @} */ /*! @name EVD_CFG - External Voltage Domain Configuration */ /*! @{ */ #define SPC_EVD_CFG_EVDISO_MASK (0x3FU) #define SPC_EVD_CFG_EVDISO_SHIFT (0U) /*! EVDISO - External Voltage Domain Isolation */ #define SPC_EVD_CFG_EVDISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK) #define SPC_EVD_CFG_EVDLPISO_MASK (0x3F00U) #define SPC_EVD_CFG_EVDLPISO_SHIFT (8U) /*! EVDLPISO - External Voltage Domain Low-Power Isolation */ #define SPC_EVD_CFG_EVDLPISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK) #define SPC_EVD_CFG_EVDSTAT_MASK (0x3F0000U) #define SPC_EVD_CFG_EVDSTAT_SHIFT (16U) /*! EVDSTAT - External Voltage Domain Status */ #define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) /*! @} */ /*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */ /*! @{ */ #define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) #define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) /*! CNT_SELECT - Counter Select * 0b00..0 * 0b01..1 * 0b10..2 * 0b11..3 */ #define SPC_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK) #define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) #define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) /*! TIMEOUT - Timeout */ #define SPC_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK) #define SPC_GLITCH_DETECT_SC_RE_MASK (0x40U) #define SPC_GLITCH_DETECT_SC_RE_SHIFT (6U) /*! RE - Glitch Detect Reset Enable * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset */ #define SPC_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK) #define SPC_GLITCH_DETECT_SC_IE_MASK (0x80U) #define SPC_GLITCH_DETECT_SC_IE_SHIFT (7U) /*! IE - Glitch Detect Interrupt Enable * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling) * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt */ #define SPC_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK) #define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) #define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) /*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */ #define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) #define SPC_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) #define SPC_GLITCH_DETECT_SC_LOCK_SHIFT (16U) /*! LOCK - Glitch Detect Reset Enable Lock Bit * 0b0..Writes to RE are allowed. * 0b1..Writes to RE are ignored. */ #define SPC_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK) /*! @} */ /*! @name CORELDO_CFG - LDO_CORE Configuration */ /*! @{ */ #define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK (0x10000U) #define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT (16U) /*! DPDOWN_PULLDOWN_DISABLE - LDO_CORE Deep Power Down Pulldown Disable * 0b0..LDO_CORE pulldown in Deep Power Down not disabled * 0b1..LDO_CORE pulldown in Deep Power Down disabled */ #define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT)) & SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK) /*! @} */ /*! @name SYSLDO_CFG - LDO_SYS Configuration */ /*! @{ */ #define SPC_SYSLDO_CFG_ISINKEN_MASK (0x1U) #define SPC_SYSLDO_CFG_ISINKEN_SHIFT (0U) /*! ISINKEN - Current Sink Enable * 0b0..Disable * 0b1..Enable */ #define SPC_SYSLDO_CFG_ISINKEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_SYSLDO_CFG_ISINKEN_SHIFT)) & SPC_SYSLDO_CFG_ISINKEN_MASK) /*! @} */ /*! @name DCDC_CFG - DCDC Configuration */ /*! @{ */ #define SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK (0x1U) #define SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT (0U) /*! FREQ_CNTRL_ON - DCDC Burst Frequency Control Enable * 0b0..Disable * 0b1..Enable */ #define SPC_DCDC_CFG_FREQ_CNTRL_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK) #define SPC_DCDC_CFG_FREQ_CNTRL_MASK (0x3F00U) #define SPC_DCDC_CFG_FREQ_CNTRL_SHIFT (8U) /*! FREQ_CNTRL - DCDC Burst Frequency Control */ #define SPC_DCDC_CFG_FREQ_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_MASK) #define SPC_DCDC_CFG_BLEED_EN_MASK (0x80000U) #define SPC_DCDC_CFG_BLEED_EN_SHIFT (19U) /*! BLEED_EN - DCDC Bleed Enable * 0b0..Do not add * 0b1..Add */ #define SPC_DCDC_CFG_BLEED_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_BLEED_EN_SHIFT)) & SPC_DCDC_CFG_BLEED_EN_MASK) /*! @} */ /*! @name DCDC_BURST_CFG - DCDC Burst Configuration */ /*! @{ */ #define SPC_DCDC_BURST_CFG_BURST_REQ_MASK (0x1U) #define SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT (0U) /*! BURST_REQ - Software Burst Request * 0b0..Do not generate * 0b1..Generate */ #define SPC_DCDC_BURST_CFG_BURST_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_REQ_MASK) #define SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK (0x2U) #define SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT (1U) /*! EXT_BURST_EN - External Burst Request Enable * 0b0..Disable * 0b1..Enable */ #define SPC_DCDC_BURST_CFG_EXT_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT)) & SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK) #define SPC_DCDC_BURST_CFG_BURST_ACK_MASK (0x8U) #define SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT (3U) /*! BURST_ACK - Burst Acknowledge Flag * 0b0..Did not complete * 0b1..Completed * 0b0..No effect * 0b1..Clear the flag */ #define SPC_DCDC_BURST_CFG_BURST_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) #define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK (0xFFFF0000U) #define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT (16U) /*! PULSE_REFRESH_CNT - Refresh Count Value */ #define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT)) & SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK) /*! @} */ /*! * @} */ /* end of group SPC_Register_Masks */ /* SPC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral SPC0 base address */ #define SPC0_BASE (0x50045000u) /** Peripheral SPC0 base address */ #define SPC0_BASE_NS (0x40045000u) /** Peripheral SPC0 base pointer */ #define SPC0 ((SPC_Type *)SPC0_BASE) /** Peripheral SPC0 base pointer */ #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) /** Array initializer of SPC peripheral base addresses */ #define SPC_BASE_ADDRS { SPC0_BASE } /** Array initializer of SPC peripheral base pointers */ #define SPC_BASE_PTRS { SPC0 } /** Array initializer of SPC peripheral base addresses */ #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } /** Array initializer of SPC peripheral base pointers */ #define SPC_BASE_PTRS_NS { SPC0_NS } #else /** Peripheral SPC0 base address */ #define SPC0_BASE (0x40045000u) /** Peripheral SPC0 base pointer */ #define SPC0 ((SPC_Type *)SPC0_BASE) /** Array initializer of SPC peripheral base addresses */ #define SPC_BASE_ADDRS { SPC0_BASE } /** Array initializer of SPC peripheral base pointers */ #define SPC_BASE_PTRS { SPC0 } #endif /*! * @} */ /* end of group SPC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SYSCON Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer * @{ */ /** SYSCON - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[16]; __IO uint32_t AHBMATPRIO; /**< AHB Matrix Priority Control, offset: 0x10 */ uint8_t RESERVED_1[36]; __IO uint32_t CPU0STCKCAL; /**< Secure CPU0 System Tick Calibration, offset: 0x38 */ __IO uint32_t CPU0NSTCKCAL; /**< Non-Secure CPU0 System Tick Calibration, offset: 0x3C */ __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ uint8_t RESERVED_2[4]; __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ uint8_t RESERVED_3[180]; __IO uint32_t PRESETCTRL0; /**< Peripheral Reset Control 0, offset: 0x100 */ __IO uint32_t PRESETCTRL1; /**< Peripheral Reset Control 1, offset: 0x104 */ __IO uint32_t PRESETCTRL2; /**< Peripheral Reset Control 2, offset: 0x108 */ __IO uint32_t PRESETCTRL3; /**< Peripheral Reset Control 3, offset: 0x10C */ uint8_t RESERVED_4[16]; __O uint32_t PRESETCTRLSET[4]; /**< Peripheral Reset Control Set, array offset: 0x120, array step: 0x4 */ uint8_t RESERVED_5[16]; __O uint32_t PRESETCTRLCLR[4]; /**< Peripheral Reset Control Clear, array offset: 0x140, array step: 0x4 */ uint8_t RESERVED_6[176]; __IO uint32_t AHBCLKCTRL0; /**< AHB Clock Control 0, offset: 0x200 */ __IO uint32_t AHBCLKCTRL1; /**< AHB Clock Control 1, offset: 0x204 */ __IO uint32_t AHBCLKCTRL2; /**< AHB Clock Control 2, offset: 0x208 */ __IO uint32_t AHBCLKCTRL3; /**< AHB Clock Control 3, offset: 0x20C */ uint8_t RESERVED_7[16]; __O uint32_t AHBCLKCTRLSET[4]; /**< AHB Clock Control Set, array offset: 0x220, array step: 0x4 */ uint8_t RESERVED_8[16]; __O uint32_t AHBCLKCTRLCLR[4]; /**< AHB Clock Control Clear, array offset: 0x240, array step: 0x4 */ uint8_t RESERVED_9[16]; __IO uint32_t SYSTICKCLKSEL0; /**< CPU0 System Tick Timer Source Select, offset: 0x260 */ __IO uint32_t SYSTICKCLKSEL1; /**< CPU1 System Tick Timer Source Select, offset: 0x264 */ __IO uint32_t TRACECLKSEL; /**< Trace Clock Source Select, offset: 0x268 */ __IO uint32_t CTIMERCLKSEL[5]; /**< CTIMER Clock Source Select, array offset: 0x26C, array step: 0x4 */ uint8_t RESERVED_10[8]; __IO uint32_t CLKOUTSEL; /**< CLKOUT Clock Source Select, offset: 0x288 */ uint8_t RESERVED_11[24]; __IO uint32_t ADC0CLKSEL; /**< ADC0 Clock Source Select, offset: 0x2A4 */ __IO uint32_t USB0CLKSEL; /**< USB-FS Clock Source Select, offset: 0x2A8 */ uint8_t RESERVED_12[4]; __IO uint32_t FCCLKSEL[10]; /**< LP_FLEXCOMM Clock Source Select for Fractional Rate Divider, array offset: 0x2B0, array step: 0x4 */ uint8_t RESERVED_13[24]; __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM Clock Source Select, offset: 0x2F0 */ uint8_t RESERVED_14[12]; __IO uint32_t SYSTICKCLKDIV[2]; /**< CPU0 System Tick Timer Divider..CPU1 System Tick Timer Divider, array offset: 0x300, array step: 0x4 */ __IO uint32_t TRACECLKDIV; /**< TRACE Clock Divider, offset: 0x308 */ uint8_t RESERVED_15[68]; __IO uint32_t TSICLKSEL; /**< TSI Function Clock Source Select, offset: 0x350 */ uint8_t RESERVED_16[12]; __IO uint32_t SINCFILTCLKSEL; /**< SINC FILTER Function Clock Source Select, offset: 0x360 */ uint8_t RESERVED_17[20]; __IO uint32_t SLOWCLKDIV; /**< SLOW_CLK Clock Divider, offset: 0x378 */ __IO uint32_t TSICLKDIV; /**< TSI Function Clock Divider, offset: 0x37C */ __IO uint32_t AHBCLKDIV; /**< System Clock Divider, offset: 0x380 */ __IO uint32_t CLKOUTDIV; /**< CLKOUT Clock Divider, offset: 0x384 */ __IO uint32_t FROHFDIV; /**< FRO_HF_DIV Clock Divider, offset: 0x388 */ __IO uint32_t WDT0CLKDIV; /**< WDT0 Clock Divider, offset: 0x38C */ uint8_t RESERVED_18[4]; __IO uint32_t ADC0CLKDIV; /**< ADC0 Clock Divider, offset: 0x394 */ __IO uint32_t USB0CLKDIV; /**< USB-FS Clock Divider, offset: 0x398 */ uint8_t RESERVED_19[24]; __IO uint32_t SCTCLKDIV; /**< SCT/PWM Clock Divider, offset: 0x3B4 */ uint8_t RESERVED_20[12]; __IO uint32_t PLLCLKDIV; /**< PLL Clock Divider, offset: 0x3C4 */ uint8_t RESERVED_21[8]; __IO uint32_t CTIMERCLKDIV[5]; /**< CTimer Clock Divider, array offset: 0x3D0, array step: 0x4 */ __IO uint32_t PLL1CLK0DIV; /**< PLL1 Clock 0 Divider, offset: 0x3E4 */ __IO uint32_t PLL1CLK1DIV; /**< PLL1 Clock 1 Divider, offset: 0x3E8 */ uint8_t RESERVED_22[4]; __IO uint32_t UTICKCLKDIV; /**< UTICK Clock Divider, offset: 0x3F0 */ __IO uint32_t CLKOUT_FRGCTRL; /**< CLKOUT FRG Control, offset: 0x3F4 */ uint8_t RESERVED_23[4]; __IO uint32_t CLKUNLOCK; /**< Clock Configuration Unlock, offset: 0x3FC */ __IO uint32_t NVM_CTRL; /**< NVM Control, offset: 0x400 */ __IO uint32_t ROMCR; /**< ROM Wait State, offset: 0x404 */ uint8_t RESERVED_24[12]; __IO uint32_t SMARTDMAINT; /**< SmartDMA Interrupt Hijack, offset: 0x414 */ uint8_t RESERVED_25[76]; __IO uint32_t ADC1CLKSEL; /**< ADC1 Clock Source Select, offset: 0x464 */ __IO uint32_t ADC1CLKDIV; /**< ADC1 Clock Divider, offset: 0x468 */ uint8_t RESERVED_26[4]; __IO uint32_t RAM_INTERLEAVE; /**< Control PKC RAM Interleave Access, offset: 0x470 */ uint8_t RESERVED_27[28]; struct { /* offset: 0x490, array step: 0x8 */ __IO uint32_t CLKSEL; /**< DAC0 Functional Clock Selection..DAC2 Functional Clock Selection, array offset: 0x490, array step: 0x8 */ __IO uint32_t CLKDIV; /**< DAC0 functional clock divider..DAC2 functional clock divider, array offset: 0x494, array step: 0x8 */ } DAC[3]; __IO uint32_t FLEXSPICLKSEL; /**< FlexSPI Clock Selection, offset: 0x4A8 */ __IO uint32_t FLEXSPICLKDIV; /**< FlexSPI Clock Divider, offset: 0x4AC */ uint8_t RESERVED_28[124]; __IO uint32_t PLLCLKDIVSEL; /**< PLL Clock Divider Clock Selection, offset: 0x52C */ __IO uint32_t I3C0FCLKSEL; /**< I3C0 Functional Clock Selection, offset: 0x530 */ __IO uint32_t I3C0FCLKSTCSEL; /**< I3C0 FCLK_STC Clock Selection, offset: 0x534 */ __IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ __IO uint32_t I3C0FCLKSDIV; /**< I3C0 FCLK Slow Clock Divider, offset: 0x53C */ __IO uint32_t I3C0FCLKDIV; /**< I3C0 Functional Clock FCLK Divider, offset: 0x540 */ __IO uint32_t I3C0FCLKSSEL; /**< I3C0 FCLK Slow Selection, offset: 0x544 */ __IO uint32_t MICFILFCLKSEL; /**< MICFIL Clock Selection, offset: 0x548 */ __IO uint32_t MICFILFCLKDIV; /**< MICFIL Clock Division, offset: 0x54C */ uint8_t RESERVED_29[8]; __IO uint32_t USDHCCLKSEL; /**< uSDHC Clock Selection, offset: 0x558 */ __IO uint32_t USDHCCLKDIV; /**< uSDHC Function Clock Divider, offset: 0x55C */ __IO uint32_t FLEXIOCLKSEL; /**< FLEXIO Clock Selection, offset: 0x560 */ __IO uint32_t FLEXIOCLKDIV; /**< FLEXIO Function Clock Divider, offset: 0x564 */ uint8_t RESERVED_30[56]; __IO uint32_t FLEXCAN0CLKSEL; /**< FLEXCAN0 Clock Selection, offset: 0x5A0 */ __IO uint32_t FLEXCAN0CLKDIV; /**< FLEXCAN0 Function Clock Divider, offset: 0x5A4 */ __IO uint32_t FLEXCAN1CLKSEL; /**< FLEXCAN1 Clock Selection, offset: 0x5A8 */ __IO uint32_t FLEXCAN1CLKDIV; /**< FLEXCAN1 Function Clock Divider, offset: 0x5AC */ __IO uint32_t ENETRMIICLKSEL; /**< Ethernet RMII Clock Selection, offset: 0x5B0 */ __IO uint32_t ENETRMIICLKDIV; /**< Ethernet RMII Function Clock Divider, offset: 0x5B4 */ __IO uint32_t ENETPTPREFCLKSEL; /**< Ethernet PTP REF Clock Selection, offset: 0x5B8 */ __IO uint32_t ENETPTPREFCLKDIV; /**< Ethernet PTP REF Function Clock Divider, offset: 0x5BC */ __IO uint32_t ENET_PHY_INTF_SEL; /**< Ethernet PHY Interface Select, offset: 0x5C0 */ __IO uint32_t ENET_SBD_FLOW_CTRL; /**< Sideband Flow Control, offset: 0x5C4 */ uint8_t RESERVED_31[12]; __IO uint32_t EWM0CLKSEL; /**< EWM0 Clock Selection, offset: 0x5D4 */ __IO uint32_t WDT1CLKSEL; /**< WDT1 Clock Selection, offset: 0x5D8 */ __IO uint32_t WDT1CLKDIV; /**< WDT1 Function Clock Divider, offset: 0x5DC */ __IO uint32_t OSTIMERCLKSEL; /**< OSTIMER Clock Selection, offset: 0x5E0 */ uint8_t RESERVED_32[12]; __IO uint32_t CMP0FCLKSEL; /**< CMP0 Function Clock Selection, offset: 0x5F0 */ __IO uint32_t CMP0FCLKDIV; /**< CMP0 Function Clock Divider, offset: 0x5F4 */ __IO uint32_t CMP0RRCLKSEL; /**< CMP0 Round Robin Clock Selection, offset: 0x5F8 */ __IO uint32_t CMP0RRCLKDIV; /**< CMP0 Round Robin Clock Divider, offset: 0x5FC */ __IO uint32_t CMP1FCLKSEL; /**< CMP1 Function Clock Selection, offset: 0x600 */ __IO uint32_t CMP1FCLKDIV; /**< CMP1 Function Clock Divider, offset: 0x604 */ __IO uint32_t CMP1RRCLKSEL; /**< CMP1 Round Robin Clock Source Select, offset: 0x608 */ __IO uint32_t CMP1RRCLKDIV; /**< CMP1 Round Robin Clock Division, offset: 0x60C */ __IO uint32_t CMP2FCLKSEL; /**< CMP2 Function Clock Source Select, offset: 0x610 */ __IO uint32_t CMP2FCLKDIV; /**< CMP2 Function Clock Division, offset: 0x614 */ __IO uint32_t CMP2RRCLKSEL; /**< CMP2 Round Robin Clock Source Select, offset: 0x618 */ __IO uint32_t CMP2RRCLKDIV; /**< CMP2 Round Robin Clock Division, offset: 0x61C */ uint8_t RESERVED_33[480]; __IO uint32_t CPUCTRL; /**< CPU Control for Multiple Processors, offset: 0x800 */ __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ uint8_t RESERVED_34[4]; __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ uint8_t RESERVED_35[20]; __IO uint32_t LPCAC_CTRL; /**< LPCAC Control, offset: 0x824 */ uint8_t RESERVED_36[40]; __IO uint32_t FLEXCOMMCLKDIV[10]; /**< LP_FLEXCOMM Clock Divider, array offset: 0x850, array step: 0x4 */ __IO uint32_t UTICKCLKSEL; /**< UTICK Function Clock Source Select, offset: 0x878 */ uint8_t RESERVED_37[4]; __IO uint32_t SAI0CLKSEL; /**< SAI0 Function Clock Source Select, offset: 0x880 */ __IO uint32_t SAI1CLKSEL; /**< SAI1 Function Clock Source Select, offset: 0x884 */ __IO uint32_t SAI0CLKDIV; /**< SAI0 Function Clock Division, offset: 0x888 */ __IO uint32_t SAI1CLKDIV; /**< SAI1 Function Clock Division, offset: 0x88C */ __IO uint32_t EMVSIM0CLKSEL; /**< EMVSIM0 Clock Source Select, offset: 0x890 */ __IO uint32_t EMVSIM1CLKSEL; /**< EMVSIM1 Clock Source Select, offset: 0x894 */ __IO uint32_t EMVSIM0CLKDIV; /**< EMVSIM0 Function Clock Division, offset: 0x898 */ __IO uint32_t EMVSIM1CLKDIV; /**< EMVSIM1 Function Clock Division, offset: 0x89C */ uint8_t RESERVED_38[176]; __IO uint32_t KEY_RETAIN_CTRL; /**< Key Retain Control, offset: 0x950 */ uint8_t RESERVED_39[12]; __IO uint32_t REF_CLK_CTRL; /**< FRO 48MHz Reference Clock Control, offset: 0x960 */ __O uint32_t REF_CLK_CTRL_SET; /**< FRO 48MHz Reference Clock Control Set, offset: 0x964 */ __O uint32_t REF_CLK_CTRL_CLR; /**< FRO 48MHz Reference Clock Control Clear, offset: 0x968 */ __IO uint32_t GDET_CTRL[2]; /**< GDET Control Register, array offset: 0x96C, array step: 0x4 */ __IO uint32_t ELS_ASSET_PROT; /**< ELS Asset Protection Register, offset: 0x974 */ __IO uint32_t ELS_LOCK_CTRL; /**< ELS Lock Control, offset: 0x978 */ __IO uint32_t ELS_LOCK_CTRL_DP; /**< ELS Lock Control DP, offset: 0x97C */ __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0x980 */ __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0x984 */ __IO uint32_t ELS_TEMPORAL_STATE; /**< ELS Temporal State, offset: 0x988 */ __IO uint32_t ELS_KDF_MASK; /**< Key Derivation Function Mask, offset: 0x98C */ uint8_t RESERVED_40[64]; __I uint32_t ELS_AS_CFG0; /**< ELS AS Configuration, offset: 0x9D0 */ __I uint32_t ELS_AS_CFG1; /**< ELS AS Configuration1, offset: 0x9D4 */ __I uint32_t ELS_AS_CFG2; /**< ELS AS Configuration2, offset: 0x9D8 */ __I uint32_t ELS_AS_CFG3; /**< ELS AS Configuration3, offset: 0x9DC */ __I uint32_t ELS_AS_ST0; /**< ELS AS State Register, offset: 0x9E0 */ __I uint32_t ELS_AS_ST1; /**< ELS AS State1, offset: 0x9E4 */ __I uint32_t ELS_AS_BOOT_LOG0; /**< Boot state captured during boot: Main ROM log, offset: 0x9E8 */ __I uint32_t ELS_AS_BOOT_LOG1; /**< Boot state captured during boot: Library log, offset: 0x9EC */ __I uint32_t ELS_AS_BOOT_LOG2; /**< Boot state captured during boot: Hardware status signals log, offset: 0x9F0 */ __I uint32_t ELS_AS_BOOT_LOG3; /**< Boot state captured during boot: Security log, offset: 0x9F4 */ __I uint32_t ELS_AS_FLAG0; /**< ELS AS Flag0, offset: 0x9F8 */ __I uint32_t ELS_AS_FLAG1; /**< ELS AS Flag1, offset: 0x9FC */ uint8_t RESERVED_41[24]; __IO uint32_t CLOCK_CTRL; /**< Clock Control, offset: 0xA18 */ uint8_t RESERVED_42[276]; __IO uint32_t I3C1FCLKSEL; /**< I3C1 Functional Clock Selection, offset: 0xB30 */ __IO uint32_t I3C1FCLKSTCSEL; /**< Selects the I3C1 Time Control clock, offset: 0xB34 */ __IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ __IO uint32_t I3C1FCLKSDIV; /**< I3C1 FCLK Slow clock Divider, offset: 0xB3C */ __IO uint32_t I3C1FCLKDIV; /**< I3C1 Functional Clock FCLK Divider, offset: 0xB40 */ __IO uint32_t I3C1FCLKSSEL; /**< I3C1 FCLK Slow Selection, offset: 0xB44 */ uint8_t RESERVED_43[8]; __IO uint32_t ETB_STATUS; /**< ETB Counter Status Register, offset: 0xB50 */ __IO uint32_t ETB_COUNTER_CTRL; /**< ETB Counter Control Register, offset: 0xB54 */ __IO uint32_t ETB_COUNTER_RELOAD; /**< ETB Counter Reload Register, offset: 0xB58 */ __I uint32_t ETB_COUNTER_VALUE; /**< ETB Counter Value Register, offset: 0xB5C */ __IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter Gray code_gray[31:0], offset: 0xB60 */ __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray code_gray[41:32], offset: 0xB64 */ __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ uint8_t RESERVED_44[660]; __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control Automatic Clock Gating, offset: 0xE04 */ uint8_t RESERVED_45[36]; __IO uint32_t AUTOCLKGATEOVERRIDEC; /**< Control Automatic Clock Gating C, offset: 0xE2C */ uint8_t RESERVED_46[8]; __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0xE38 */ __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0xE3C */ __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0xE40 */ __IO uint32_t ECC_ENABLE_CTRL; /**< RAM ECC Enable Control, offset: 0xE44 */ uint8_t RESERVED_47[344]; __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ uint8_t RESERVED_48[8]; __IO uint32_t SWD_ACCESS_CPU[2]; /**< CPU0 Software Debug Access..CPU1 Software Debug Access, array offset: 0xFB4, array step: 0x4 */ uint8_t RESERVED_49[4]; __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ __IO uint32_t SWD_ACCESS_DSP; /**< DSP Software Debug Access, offset: 0xFC4 */ uint8_t RESERVED_50[40]; __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ __I uint32_t DIEID; /**< Chip Revision ID and Number, offset: 0xFFC */ } SYSCON_Type; /* ---------------------------------------------------------------------------- -- SYSCON Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SYSCON_Register_Masks SYSCON Register Masks * @{ */ /*! @name AHBMATPRIO - AHB Matrix Priority Control */ /*! @{ */ #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) /*! PRI_CPU0_CBUS - CPU0 C-AHB bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) /*! PRI_CPU0_SBUS - CPU0 S-AHB bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D_MASK (0x30U) #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D_SHIFT (4U) /*! PRI_CPU1_SBUS_SmartDMA_D - CPU1 S-AHB/SmartDMA-D bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SmartDMA_D_MASK) #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I_MASK (0xC0U) #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I_SHIFT (6U) /*! PRI_CPU1_CBUS_SmartDMA_I - CPU1 C-AHB/SmartDMA-I bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SmartDMA_I_MASK) #define SYSCON_AHBMATPRIO_DMA0_MASK (0x300U) #define SYSCON_AHBMATPRIO_DMA0_SHIFT (8U) /*! DMA0 - DMA0 controller bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK) #define SYSCON_AHBMATPRIO_DMA1_MASK (0xC00U) #define SYSCON_AHBMATPRIO_DMA1_SHIFT (10U) /*! DMA1 - DMA1 controller bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA1_SHIFT)) & SYSCON_AHBMATPRIO_DMA1_MASK) #define SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK (0x3000U) #define SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT (12U) /*! PRI_PKC_ELS - PKC and ELS bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_PKC_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK) #define SYSCON_AHBMATPRIO_PRI_NPU_PQ_MASK (0xC000U) #define SYSCON_AHBMATPRIO_PRI_NPU_PQ_SHIFT (14U) /*! PRI_NPU_PQ - NPU O bus and Powerquad bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_NPU_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_NPU_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_NPU_PQ_MASK) #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_I_MASK (0x30000U) #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_I_SHIFT (16U) /*! PRI_COOLFLUX_I - CoolFlux I bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_COOLFLUX_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_COOLFLUX_I_MASK) #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_X_MASK (0xC0000U) #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_X_SHIFT (18U) /*! PRI_COOLFLUX_X - CoolFlux X bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_COOLFLUX_X_SHIFT)) & SYSCON_AHBMATPRIO_PRI_COOLFLUX_X_MASK) #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI_MASK (0x300000U) #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI_SHIFT (20U) /*! PRI_COOLFLUX_Y_ESPI - CoolFlux Y bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI_SHIFT)) & SYSCON_AHBMATPRIO_PRI_COOLFLUX_Y_ESPI_MASK) #define SYSCON_AHBMATPRIO_PRI_NPU_D_MASK (0xC00000U) #define SYSCON_AHBMATPRIO_PRI_NPU_D_SHIFT (22U) /*! PRI_NPU_D - NPU D bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_NPU_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_NPU_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_NPU_D_MASK) #define SYSCON_AHBMATPRIO_PRI_USB_FS_ENET_MASK (0x3000000U) #define SYSCON_AHBMATPRIO_PRI_USB_FS_ENET_SHIFT (24U) /*! PRI_USB_FS_ENET - USB-FS and ENET bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_USB_FS_ENET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_ENET_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_ENET_MASK) #define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC000000U) #define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (26U) /*! PRI_USB_HS - USB-HS bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) #define SYSCON_AHBMATPRIO_PRI_USDHC_MASK (0x30000000U) #define SYSCON_AHBMATPRIO_PRI_USDHC_SHIFT (28U) /*! PRI_USDHC - USDHC bus master priority level * 0b00..level 0 * 0b01..level 1 * 0b10..level 2 * 0b11..level 3 */ #define SYSCON_AHBMATPRIO_PRI_USDHC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USDHC_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USDHC_MASK) /*! @} */ /*! @name CPU0STCKCAL - Secure CPU0 System Tick Calibration */ /*! @{ */ #define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) #define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) /*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the * value reads as zero, the calibration value is not known. */ #define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) #define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) /*! SKEW - Whether the TENMS value is exact. * 0b0..TENMS value is exact * 0b1..TENMS value is not exact or not given */ #define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) #define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) /*! NOREF - Whether the device provides a reference clock to the processor. * 0b0..Reference clock is provided * 0b1..No reference clock is provided */ #define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) /*! @} */ /*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */ /*! @{ */ #define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) #define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) /*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the * value reads as zero, the calibration value is not known. */ #define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) #define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) /*! SKEW - Indicates whether the TENMS value is exact. * 0b0..TENMS value is exact * 0b1..TENMS value is not exact or not given */ #define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) #define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) /*! NOREF - Indicates whether the device provides a reference clock to the processor. * 0b0..Reference clock is provided * 0b1..No reference clock is provided */ #define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) /*! @} */ /*! @name CPU1STCKCAL - System tick calibration for CPU1 */ /*! @{ */ #define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) #define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) /*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the * value reads as zero, the calibration value is not known. */ #define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) #define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) /*! SKEW - Indicates whether the TENMS value is exact. * 0b0..TENMS value is exact * 0b1..TENMS value is not exact or not given */ #define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) #define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) /*! NOREF - Indicates whether the device provides a reference clock to the processor. * 0b0..Reference clock is provided * 0b1..No reference clock is provided */ #define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) /*! @} */ /*! @name NMISRC - NMI Source Select */ /*! @{ */ #define SYSCON_NMISRC_IRQCPU0_MASK (0xFFU) #define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) /*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */ #define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) #define SYSCON_NMISRC_IRQCPU1_MASK (0xFF00U) #define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) /*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU1, if enabled by NMIENCPU1. */ #define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) #define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) #define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) /*! NMIENCPU1 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. * 0b1..Enable. * 0b0..Disable. */ #define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) #define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) #define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) /*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. * 0b1..Enable. * 0b0..Disable. */ #define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) /*! @} */ /*! @name PRESETCTRL0 - Peripheral Reset Control 0 */ /*! @{ */ #define SYSCON_PRESETCTRL0_FMU_RST_MASK (0x200U) #define SYSCON_PRESETCTRL0_FMU_RST_SHIFT (9U) /*! FMU_RST - Flash management unit reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_FMU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMU_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMU_RST_MASK) #define SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK (0x800U) #define SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT (11U) /*! FLEXSPI_RST - FlexSPI reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_FLEXSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK) #define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x1000U) #define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (12U) /*! MUX_RST - INPUTMUX reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) #define SYSCON_PRESETCTRL0_PORT0_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL0_PORT0_RST_SHIFT (13U) /*! PORT0_RST - PORT0 controller reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_PORT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT0_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT0_RST_MASK) #define SYSCON_PRESETCTRL0_PORT1_RST_MASK (0x4000U) #define SYSCON_PRESETCTRL0_PORT1_RST_SHIFT (14U) /*! PORT1_RST - PORT1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_PORT1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT1_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT1_RST_MASK) #define SYSCON_PRESETCTRL0_PORT2_RST_MASK (0x8000U) #define SYSCON_PRESETCTRL0_PORT2_RST_SHIFT (15U) /*! PORT2_RST - PORT2 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_PORT2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT2_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT2_RST_MASK) #define SYSCON_PRESETCTRL0_PORT3_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL0_PORT3_RST_SHIFT (16U) /*! PORT3_RST - PORT3 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_PORT3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT3_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT3_RST_MASK) #define SYSCON_PRESETCTRL0_PORT4_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL0_PORT4_RST_SHIFT (17U) /*! PORT4_RST - PORT4 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_PORT4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT4_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT4_RST_MASK) #define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (19U) /*! GPIO0_RST - GPIO0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) #define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (20U) /*! GPIO1_RST - GPIO1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) #define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x200000U) #define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (21U) /*! GPIO2_RST - GPIO2 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) #define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (22U) /*! GPIO3_RST - GPIO3 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) #define SYSCON_PRESETCTRL0_GPIO4_RST_MASK (0x800000U) #define SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT (23U) /*! GPIO4_RST - GPIO4 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO4_RST_MASK) #define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x2000000U) #define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (25U) /*! PINT_RST - PINT reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) #define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x4000000U) #define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (26U) /*! DMA0_RST - DMA0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) #define SYSCON_PRESETCTRL0_CRC_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL0_CRC_RST_SHIFT (27U) /*! CRC_RST - CRC reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRC_RST_MASK) #define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x80000000U) #define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (31U) /*! MAILBOX_RST - Inter-CPU communication Mailbox reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) /*! @} */ /*! @name PRESETCTRL1 - Peripheral Reset Control 1 */ /*! @{ */ #define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) #define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) /*! MRT_RST - MRT reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) #define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) #define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) /*! OSTIMER_RST - OS Event Timer reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) #define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) #define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) /*! SCT_RST - SCT reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) #define SYSCON_PRESETCTRL1_ADC0_RST_MASK (0x8U) #define SYSCON_PRESETCTRL1_ADC0_RST_SHIFT (3U) /*! ADC0_RST - ADC0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC0_RST_MASK) #define SYSCON_PRESETCTRL1_ADC1_RST_MASK (0x10U) #define SYSCON_PRESETCTRL1_ADC1_RST_SHIFT (4U) /*! ADC1_RST - ADC1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_ADC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC1_RST_MASK) #define SYSCON_PRESETCTRL1_DAC0_RST_MASK (0x20U) #define SYSCON_PRESETCTRL1_DAC0_RST_SHIFT (5U) /*! DAC0_RST - DAC0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_DAC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_DAC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_DAC0_RST_MASK) #define SYSCON_PRESETCTRL1_RTC_RST_MASK (0x40U) #define SYSCON_PRESETCTRL1_RTC_RST_SHIFT (6U) /*! RTC_RST - RTC reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL1_RTC_RST_MASK) #define SYSCON_PRESETCTRL1_EVSIM0_RST_MASK (0x100U) #define SYSCON_PRESETCTRL1_EVSIM0_RST_SHIFT (8U) /*! EVSIM0_RST - EVSIM0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_EVSIM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EVSIM0_RST_SHIFT)) & SYSCON_PRESETCTRL1_EVSIM0_RST_MASK) #define SYSCON_PRESETCTRL1_EVSIM1_RST_MASK (0x200U) #define SYSCON_PRESETCTRL1_EVSIM1_RST_SHIFT (9U) /*! EVSIM1_RST - EVSIM1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_EVSIM1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EVSIM1_RST_SHIFT)) & SYSCON_PRESETCTRL1_EVSIM1_RST_MASK) #define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) #define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) /*! UTICK_RST - UTICK reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) #define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) #define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) /*! FC0_RST - LP_FLEXCOMM0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) #define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) #define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) /*! FC1_RST - LP_FLEXCOMM1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) #define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) /*! FC2_RST - LP_FLEXCOMM2 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) #define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) #define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) /*! FC3_RST - LP_FLEXCOMM3 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) #define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) #define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) /*! FC4_RST - LP_FLEXCOMM4 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) #define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) /*! FC5_RST - LP_FLEXCOMM5 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) #define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) /*! FC6_RST - LP_FLEXCOMM6 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) #define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) #define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) /*! FC7_RST - LP_FLEXCOMM7 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) #define SYSCON_PRESETCTRL1_FC8_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL1_FC8_RST_SHIFT (19U) /*! FC8_RST - LP_FLEXCOMM8 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC8_RST_MASK) #define SYSCON_PRESETCTRL1_FC9_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL1_FC9_RST_SHIFT (20U) /*! FC9_RST - LP_FLEXCOMM9 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC9_RST_MASK) #define SYSCON_PRESETCTRL1_MICFIL_RST_MASK (0x200000U) #define SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT (21U) /*! MICFIL_RST - MICFIL reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_MICFIL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT)) & SYSCON_PRESETCTRL1_MICFIL_RST_MASK) #define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) /*! TIMER2_RST - CTIMER2 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) #define SYSCON_PRESETCTRL1_USB0_FS_DCD_RST_MASK (0x1000000U) #define SYSCON_PRESETCTRL1_USB0_FS_DCD_RST_SHIFT (24U) /*! USB0_FS_DCD_RST - USB FS DCD reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_USB0_FS_DCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_FS_DCD_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_FS_DCD_RST_MASK) #define SYSCON_PRESETCTRL1_USB0_FS_RST_MASK (0x2000000U) #define SYSCON_PRESETCTRL1_USB0_FS_RST_SHIFT (25U) /*! USB0_FS_RST - USB FS reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_USB0_FS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_FS_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_FS_RST_MASK) #define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) #define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) /*! TIMER0_RST - CTIMER0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) #define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) /*! TIMER1_RST - CTIMER1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) #define SYSCON_PRESETCTRL1_SmartDMA_RST_MASK (0x80000000U) #define SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT (31U) /*! SmartDMA_RST - SmartDMA reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL1_SmartDMA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT)) & SYSCON_PRESETCTRL1_SmartDMA_RST_MASK) /*! @} */ /*! @name PRESETCTRL2 - Peripheral Reset Control 2 */ /*! @{ */ #define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) #define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) /*! DMA1_RST - DMA1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) #define SYSCON_PRESETCTRL2_ENET_RST_MASK (0x4U) #define SYSCON_PRESETCTRL2_ENET_RST_SHIFT (2U) /*! ENET_RST - Ethernet reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_ENET_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ENET_RST_SHIFT)) & SYSCON_PRESETCTRL2_ENET_RST_MASK) #define SYSCON_PRESETCTRL2_USDHC_RST_MASK (0x8U) #define SYSCON_PRESETCTRL2_USDHC_RST_SHIFT (3U) /*! USDHC_RST - uSDHC reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_USDHC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USDHC_RST_SHIFT)) & SYSCON_PRESETCTRL2_USDHC_RST_MASK) #define SYSCON_PRESETCTRL2_FLEXIO_RST_MASK (0x10U) #define SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT (4U) /*! FLEXIO_RST - FLEXIO reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_FLEXIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXIO_RST_MASK) #define SYSCON_PRESETCTRL2_SAI0_RST_MASK (0x20U) #define SYSCON_PRESETCTRL2_SAI0_RST_SHIFT (5U) /*! SAI0_RST - SAI0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_SAI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI0_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI0_RST_MASK) #define SYSCON_PRESETCTRL2_SAI1_RST_MASK (0x40U) #define SYSCON_PRESETCTRL2_SAI1_RST_SHIFT (6U) /*! SAI1_RST - SAI1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_SAI1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI1_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI1_RST_MASK) #define SYSCON_PRESETCTRL2_TRO_RST_MASK (0x80U) #define SYSCON_PRESETCTRL2_TRO_RST_SHIFT (7U) /*! TRO_RST - TRO reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_TRO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TRO_RST_SHIFT)) & SYSCON_PRESETCTRL2_TRO_RST_MASK) #define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) #define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) /*! FREQME_RST - FREQME reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) #define SYSCON_PRESETCTRL2_TRNG_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL2_TRNG_RST_SHIFT (13U) /*! TRNG_RST - TRNG reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_TRNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TRNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_TRNG_RST_MASK) #define SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK (0x4000U) #define SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT (14U) /*! FLEXCAN0_RST - CAN0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_FLEXCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK) #define SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK (0x8000U) #define SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT (15U) /*! FLEXCAN1_RST - CAN1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_FLEXCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK) #define SYSCON_PRESETCTRL2_USB_HS_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT (16U) /*! USB_HS_RST - USB HS reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_USB_HS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_RST_MASK) #define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT (17U) /*! USB_HS_PHY_RST - USB HS PHY reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_USB_HS_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK) #define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) /*! PQ_RST - PowerQuad reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) #define SYSCON_PRESETCTRL2_PLU_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL2_PLU_RST_SHIFT (20U) /*! PLU_RST - PLU reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_PLU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLU_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLU_RST_MASK) #define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) #define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) /*! TIMER3_RST - CTIMER3 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) #define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) /*! TIMER4_RST - CTIMER4 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) #define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) #define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) /*! PUF_RST - PUF reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) #define SYSCON_PRESETCTRL2_PKC_RST_MASK (0x1000000U) #define SYSCON_PRESETCTRL2_PKC_RST_SHIFT (24U) /*! PKC_RST - PKC reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_PKC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PKC_RST_SHIFT)) & SYSCON_PRESETCTRL2_PKC_RST_MASK) #define SYSCON_PRESETCTRL2_SM3_RST_MASK (0x40000000U) #define SYSCON_PRESETCTRL2_SM3_RST_SHIFT (30U) /*! SM3_RST - SM3 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL2_SM3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SM3_RST_SHIFT)) & SYSCON_PRESETCTRL2_SM3_RST_MASK) /*! @} */ /*! @name PRESETCTRL3 - Peripheral Reset Control 3 */ /*! @{ */ #define SYSCON_PRESETCTRL3_I3C0_RST_MASK (0x1U) #define SYSCON_PRESETCTRL3_I3C0_RST_SHIFT (0U) /*! I3C0_RST - I3C0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_I3C0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C0_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C0_RST_MASK) #define SYSCON_PRESETCTRL3_I3C1_RST_MASK (0x2U) #define SYSCON_PRESETCTRL3_I3C1_RST_SHIFT (1U) /*! I3C1_RST - I3C1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_I3C1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C1_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C1_RST_MASK) #define SYSCON_PRESETCTRL3_SINC_RST_MASK (0x4U) #define SYSCON_PRESETCTRL3_SINC_RST_SHIFT (2U) /*! SINC_RST - SINC reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_SINC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_SINC_RST_SHIFT)) & SYSCON_PRESETCTRL3_SINC_RST_MASK) #define SYSCON_PRESETCTRL3_COOLFLUX_RST_MASK (0x8U) #define SYSCON_PRESETCTRL3_COOLFLUX_RST_SHIFT (3U) /*! COOLFLUX_RST - CoolFlux reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_COOLFLUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_COOLFLUX_RST_SHIFT)) & SYSCON_PRESETCTRL3_COOLFLUX_RST_MASK) #define SYSCON_PRESETCTRL3_QDC0_RST_MASK (0x10U) #define SYSCON_PRESETCTRL3_QDC0_RST_SHIFT (4U) /*! QDC0_RST - QDC0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_QDC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC0_RST_MASK) #define SYSCON_PRESETCTRL3_QDC1_RST_MASK (0x20U) #define SYSCON_PRESETCTRL3_QDC1_RST_SHIFT (5U) /*! QDC1_RST - QDC1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_QDC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC1_RST_MASK) #define SYSCON_PRESETCTRL3_PWM0_RST_MASK (0x40U) #define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT (6U) /*! PWM0_RST - PWM0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_PWM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM0_RST_MASK) #define SYSCON_PRESETCTRL3_PWM1_RST_MASK (0x80U) #define SYSCON_PRESETCTRL3_PWM1_RST_SHIFT (7U) /*! PWM1_RST - PWM1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_PWM1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM1_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM1_RST_MASK) #define SYSCON_PRESETCTRL3_AOI0_RST_MASK (0x100U) #define SYSCON_PRESETCTRL3_AOI0_RST_SHIFT (8U) /*! AOI0_RST - AOI0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_AOI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI0_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI0_RST_MASK) #define SYSCON_PRESETCTRL3_DAC1_RST_MASK (0x800U) #define SYSCON_PRESETCTRL3_DAC1_RST_SHIFT (11U) /*! DAC1_RST - DAC1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_DAC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC1_RST_MASK) #define SYSCON_PRESETCTRL3_DAC2_RST_MASK (0x1000U) #define SYSCON_PRESETCTRL3_DAC2_RST_SHIFT (12U) /*! DAC2_RST - DAC2 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_DAC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC2_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC2_RST_MASK) #define SYSCON_PRESETCTRL3_OPAMP0_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT (13U) /*! OPAMP0_RST - OPAMP0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_OPAMP0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP0_RST_MASK) #define SYSCON_PRESETCTRL3_OPAMP1_RST_MASK (0x4000U) #define SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT (14U) /*! OPAMP1_RST - OPAMP1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_OPAMP1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP1_RST_MASK) #define SYSCON_PRESETCTRL3_OPAMP2_RST_MASK (0x8000U) #define SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT (15U) /*! OPAMP2_RST - OPAMP2 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_OPAMP2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP2_RST_MASK) #define SYSCON_PRESETCTRL3_CMP2_RST_MASK (0x40000U) #define SYSCON_PRESETCTRL3_CMP2_RST_SHIFT (18U) /*! CMP2_RST - CMP2 reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_CMP2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_CMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_CMP2_RST_MASK) #define SYSCON_PRESETCTRL3_VREF_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL3_VREF_RST_SHIFT (19U) /*! VREF_RST - VREF reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_VREF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_VREF_RST_SHIFT)) & SYSCON_PRESETCTRL3_VREF_RST_MASK) #define SYSCON_PRESETCTRL3_COOLFLUX_APB_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL3_COOLFLUX_APB_RST_SHIFT (20U) /*! COOLFLUX_APB_RST - CoolFlux APB reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_COOLFLUX_APB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_COOLFLUX_APB_RST_SHIFT)) & SYSCON_PRESETCTRL3_COOLFLUX_APB_RST_MASK) #define SYSCON_PRESETCTRL3_NPU_RST_MASK (0x200000U) #define SYSCON_PRESETCTRL3_NPU_RST_SHIFT (21U) /*! NPU_RST - NPU reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_NPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_NPU_RST_SHIFT)) & SYSCON_PRESETCTRL3_NPU_RST_MASK) #define SYSCON_PRESETCTRL3_TSI_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL3_TSI_RST_SHIFT (22U) /*! TSI_RST - TSI reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_TSI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_TSI_RST_SHIFT)) & SYSCON_PRESETCTRL3_TSI_RST_MASK) #define SYSCON_PRESETCTRL3_EWM_RST_MASK (0x800000U) #define SYSCON_PRESETCTRL3_EWM_RST_SHIFT (23U) /*! EWM_RST - EWM reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_EWM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EWM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EWM_RST_MASK) #define SYSCON_PRESETCTRL3_EIM_RST_MASK (0x1000000U) #define SYSCON_PRESETCTRL3_EIM_RST_SHIFT (24U) /*! EIM_RST - EIM reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_EIM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EIM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EIM_RST_MASK) #define SYSCON_PRESETCTRL3_SEMA42_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL3_SEMA42_RST_SHIFT (27U) /*! SEMA42_RST - Semaphore reset control * 0b1..Block is reset * 0b0..Block is not reset */ #define SYSCON_PRESETCTRL3_SEMA42_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_SEMA42_RST_SHIFT)) & SYSCON_PRESETCTRL3_SEMA42_RST_MASK) /*! @} */ /*! @name PRESETCTRLSET - Peripheral Reset Control Set */ /*! @{ */ #define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) /*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */ #define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) /*! @} */ /* The count of SYSCON_PRESETCTRLSET */ #define SYSCON_PRESETCTRLSET_COUNT (4U) /*! @name PRESETCTRLCLR - Peripheral Reset Control Clear */ /*! @{ */ #define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) /*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */ #define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) /*! @} */ /* The count of SYSCON_PRESETCTRLCLR */ #define SYSCON_PRESETCTRLCLR_COUNT (4U) /*! @name AHBCLKCTRL0 - AHB Clock Control 0 */ /*! @{ */ #define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) #define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) /*! ROM - Enables the clock for the ROM * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) #define SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK (0x4U) #define SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT (2U) /*! RAMB_CTRL - Enables the clock for the RAMB Controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_RAMB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK) #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT (3U) /*! RAMC_CTRL - Enables the clock for the RAMC Controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_RAMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK) #define SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK (0x10U) #define SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT (4U) /*! RAMD_CTRL - Enables the clock for the RAMD Controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_RAMD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK) #define SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK (0x20U) #define SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT (5U) /*! RAME_CTRL - Enables the clock for the RAME Controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_RAME_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK) #define SYSCON_AHBCLKCTRL0_RAMF_CTRL_MASK (0x40U) #define SYSCON_AHBCLKCTRL0_RAMF_CTRL_SHIFT (6U) /*! RAMF_CTRL - Enables the clock for the RAMF Controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_RAMF_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMF_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMF_CTRL_MASK) #define SYSCON_AHBCLKCTRL0_RAMG_CTRL_MASK (0x80U) #define SYSCON_AHBCLKCTRL0_RAMG_CTRL_SHIFT (7U) /*! RAMG_CTRL - Enables the clock for the RAMG Controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_RAMG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMG_CTRL_MASK) #define SYSCON_AHBCLKCTRL0_RAMH_CTRL_MASK (0x100U) #define SYSCON_AHBCLKCTRL0_RAMH_CTRL_SHIFT (8U) /*! RAMH_CTRL - Enables the clock for the RAMH Controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_RAMH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMH_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMH_CTRL_MASK) #define SYSCON_AHBCLKCTRL0_FMU_MASK (0x200U) #define SYSCON_AHBCLKCTRL0_FMU_SHIFT (9U) /*! FMU - Enables the clock for the Flash Management Unit * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_FMU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMU_SHIFT)) & SYSCON_AHBCLKCTRL0_FMU_MASK) #define SYSCON_AHBCLKCTRL0_FMC_MASK (0x400U) #define SYSCON_AHBCLKCTRL0_FMC_SHIFT (10U) /*! FMC - Enables the clock for the Flash Memory Controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) #define SYSCON_AHBCLKCTRL0_FLEXSPI_MASK (0x800U) #define SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT (11U) /*! FLEXSPI - Enables the clock for FlexSPI * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT)) & SYSCON_AHBCLKCTRL0_FLEXSPI_MASK) #define SYSCON_AHBCLKCTRL0_MUX_MASK (0x1000U) #define SYSCON_AHBCLKCTRL0_MUX_SHIFT (12U) /*! MUX - Enables the clock for INPUTMUX * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) #define SYSCON_AHBCLKCTRL0_PORT0_MASK (0x2000U) #define SYSCON_AHBCLKCTRL0_PORT0_SHIFT (13U) /*! PORT0 - Enables the clock for PORT0 controller * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT0_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT0_MASK) #define SYSCON_AHBCLKCTRL0_PORT1_MASK (0x4000U) #define SYSCON_AHBCLKCTRL0_PORT1_SHIFT (14U) /*! PORT1 - Enables the clock for PORT1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT1_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT1_MASK) #define SYSCON_AHBCLKCTRL0_PORT2_MASK (0x8000U) #define SYSCON_AHBCLKCTRL0_PORT2_SHIFT (15U) /*! PORT2 - Enables the clock for PORT2 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT2_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT2_MASK) #define SYSCON_AHBCLKCTRL0_PORT3_MASK (0x10000U) #define SYSCON_AHBCLKCTRL0_PORT3_SHIFT (16U) /*! PORT3 - Enables the clock for PORT3 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_PORT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT3_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT3_MASK) #define SYSCON_AHBCLKCTRL0_PORT4_MASK (0x20000U) #define SYSCON_AHBCLKCTRL0_PORT4_SHIFT (17U) /*! PORT4 - Enables the clock for PORT4 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_PORT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT4_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT4_MASK) #define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x80000U) #define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (19U) /*! GPIO0 - Enables the clock for GPIO0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) #define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x100000U) #define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (20U) /*! GPIO1 - Enables the clock for GPIO1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) #define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x200000U) #define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (21U) /*! GPIO2 - Enables the clock for GPIO2 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) #define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x400000U) #define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (22U) /*! GPIO3 - Enables the clock for GPIO3 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) #define SYSCON_AHBCLKCTRL0_GPIO4_MASK (0x800000U) #define SYSCON_AHBCLKCTRL0_GPIO4_SHIFT (23U) /*! GPIO4 - Enables the clock for GPIO4 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO4_MASK) #define SYSCON_AHBCLKCTRL0_PINT_MASK (0x2000000U) #define SYSCON_AHBCLKCTRL0_PINT_SHIFT (25U) /*! PINT - Enables the clock for PINT * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) #define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (26U) /*! DMA0 - Enables the clock for DMA0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) #define SYSCON_AHBCLKCTRL0_CRC_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL0_CRC_SHIFT (27U) /*! CRC - Enables the clock for CRC * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRC_SHIFT)) & SYSCON_AHBCLKCTRL0_CRC_MASK) #define SYSCON_AHBCLKCTRL0_WWDT0_MASK (0x10000000U) #define SYSCON_AHBCLKCTRL0_WWDT0_SHIFT (28U) /*! WWDT0 - Enables the clock for WWDT0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT0_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT0_MASK) #define SYSCON_AHBCLKCTRL0_WWDT1_MASK (0x20000000U) #define SYSCON_AHBCLKCTRL0_WWDT1_SHIFT (29U) /*! WWDT1 - Enables the clock for WWDT1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT1_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT1_MASK) #define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x80000000U) #define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (31U) /*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) /*! @} */ /*! @name AHBCLKCTRL1 - AHB Clock Control 1 */ /*! @{ */ #define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) #define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) /*! MRT - Enables the clock for MRT * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) #define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) #define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) /*! OSTIMER - Enables the clock for the OS Event Timer * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) #define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) #define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) /*! SCT - Enables the clock for SCT * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) #define SYSCON_AHBCLKCTRL1_ADC0_MASK (0x8U) #define SYSCON_AHBCLKCTRL1_ADC0_SHIFT (3U) /*! ADC0 - Enables the clock for ADC0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC0_MASK) #define SYSCON_AHBCLKCTRL1_ADC1_MASK (0x10U) #define SYSCON_AHBCLKCTRL1_ADC1_SHIFT (4U) /*! ADC1 - Enables the clock for ADC1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC1_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC1_MASK) #define SYSCON_AHBCLKCTRL1_DAC0_MASK (0x20U) #define SYSCON_AHBCLKCTRL1_DAC0_SHIFT (5U) /*! DAC0 - Enables the clock for DAC0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_DAC0_SHIFT)) & SYSCON_AHBCLKCTRL1_DAC0_MASK) #define SYSCON_AHBCLKCTRL1_RTC_MASK (0x40U) #define SYSCON_AHBCLKCTRL1_RTC_SHIFT (6U) /*! RTC - Enables the clock for RTC * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_RTC_SHIFT)) & SYSCON_AHBCLKCTRL1_RTC_MASK) #define SYSCON_AHBCLKCTRL1_EVSIM0_MASK (0x100U) #define SYSCON_AHBCLKCTRL1_EVSIM0_SHIFT (8U) /*! EVSIM0 - Enables the clock for EVSIM0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_EVSIM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EVSIM0_SHIFT)) & SYSCON_AHBCLKCTRL1_EVSIM0_MASK) #define SYSCON_AHBCLKCTRL1_EVSIM1_MASK (0x200U) #define SYSCON_AHBCLKCTRL1_EVSIM1_SHIFT (9U) /*! EVSIM1 - Enables the clock for EVSIM1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_EVSIM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EVSIM1_SHIFT)) & SYSCON_AHBCLKCTRL1_EVSIM1_MASK) #define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) #define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) /*! UTICK - Enables the clock for UTICK * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) #define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) #define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) /*! FC0 - Enables the clock for LP_FLEXCOMM0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) #define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) #define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) /*! FC1 - Enables the clock for LP_FLEXCOMM1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) #define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) #define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) /*! FC2 - Enables the clock for LP_FLEXCOMM2 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) #define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) #define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) /*! FC3 - Enables the clock for LP_FLEXCOMM3 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) #define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) #define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) /*! FC4 - Enables the clock for LP_FLEXCOMM4 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) #define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) #define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) /*! FC5 - Enables the clock for LP_FLEXCOMM5 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) #define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) #define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) /*! FC6 - Enables the clock for LP_FLEXCOMM6 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) #define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) #define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) /*! FC7 - Enables the clock for LP_FLEXCOMM7 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) #define SYSCON_AHBCLKCTRL1_FC8_MASK (0x80000U) #define SYSCON_AHBCLKCTRL1_FC8_SHIFT (19U) /*! FC8 - Enables the clock for LP_FLEXCOMM8 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC8_SHIFT)) & SYSCON_AHBCLKCTRL1_FC8_MASK) #define SYSCON_AHBCLKCTRL1_FC9_MASK (0x100000U) #define SYSCON_AHBCLKCTRL1_FC9_SHIFT (20U) /*! FC9 - Enables the clock for LP_FLEXCOMM9 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_FC9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC9_SHIFT)) & SYSCON_AHBCLKCTRL1_FC9_MASK) #define SYSCON_AHBCLKCTRL1_MICFIL_MASK (0x200000U) #define SYSCON_AHBCLKCTRL1_MICFIL_SHIFT (21U) /*! MICFIL - Enables the clock for MICFIL * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_MICFIL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MICFIL_SHIFT)) & SYSCON_AHBCLKCTRL1_MICFIL_MASK) #define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) #define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) /*! TIMER2 - Enables the clock for CTIMER2 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) #define SYSCON_AHBCLKCTRL1_USB0_FS_DCD_MASK (0x1000000U) #define SYSCON_AHBCLKCTRL1_USB0_FS_DCD_SHIFT (24U) /*! USB0_FS_DCD - Enables the clock for USB-FS DCD * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_USB0_FS_DCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_FS_DCD_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_FS_DCD_MASK) #define SYSCON_AHBCLKCTRL1_USB0_FS_MASK (0x2000000U) #define SYSCON_AHBCLKCTRL1_USB0_FS_SHIFT (25U) /*! USB0_FS - Enables the clock for USB-FS * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_USB0_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_FS_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_FS_MASK) #define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) /*! TIMER0 - Enables the clock for CTIMER0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) #define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) /*! TIMER1 - Enables the clock for CTIMER1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) #define SYSCON_AHBCLKCTRL1_PKC_RAM_MASK (0x20000000U) #define SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT (29U) /*! PKC_RAM - Enables the clock for PKC RAM * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT)) & SYSCON_AHBCLKCTRL1_PKC_RAM_MASK) #define SYSCON_AHBCLKCTRL1_SmartDMA_MASK (0x80000000U) #define SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT (31U) /*! SmartDMA - Enables the clock for SmartDMA * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL1_SmartDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT)) & SYSCON_AHBCLKCTRL1_SmartDMA_MASK) /*! @} */ /*! @name AHBCLKCTRL2 - AHB Clock Control 2 */ /*! @{ */ #define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) #define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) /*! DMA1 - Enables the clock for DMA1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) #define SYSCON_AHBCLKCTRL2_ENET_MASK (0x4U) #define SYSCON_AHBCLKCTRL2_ENET_SHIFT (2U) /*! ENET - Enables the clock for Ethernet * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ENET_SHIFT)) & SYSCON_AHBCLKCTRL2_ENET_MASK) #define SYSCON_AHBCLKCTRL2_uSDHC_MASK (0x8U) #define SYSCON_AHBCLKCTRL2_uSDHC_SHIFT (3U) /*! uSDHC - Enables the clock for uSDHC * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_uSDHC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_uSDHC_SHIFT)) & SYSCON_AHBCLKCTRL2_uSDHC_MASK) #define SYSCON_AHBCLKCTRL2_FLEXIO_MASK (0x10U) #define SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT (4U) /*! FLEXIO - Enables the clock for Flexio * 0b1..Enable clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXIO_MASK) #define SYSCON_AHBCLKCTRL2_SAI0_MASK (0x20U) #define SYSCON_AHBCLKCTRL2_SAI0_SHIFT (5U) /*! SAI0 - Enables the clock for SAI0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_SAI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI0_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI0_MASK) #define SYSCON_AHBCLKCTRL2_SAI1_MASK (0x40U) #define SYSCON_AHBCLKCTRL2_SAI1_SHIFT (6U) /*! SAI1 - Enables the clock for SAI1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_SAI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI1_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI1_MASK) #define SYSCON_AHBCLKCTRL2_TRO_MASK (0x80U) #define SYSCON_AHBCLKCTRL2_TRO_SHIFT (7U) /*! TRO - Enables the clock for TRO * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_TRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TRO_SHIFT)) & SYSCON_AHBCLKCTRL2_TRO_MASK) #define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) #define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) /*! FREQME - Enables the clock for the Frequency meter * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) #define SYSCON_AHBCLKCTRL2_TRNG_MASK (0x2000U) #define SYSCON_AHBCLKCTRL2_TRNG_SHIFT (13U) /*! TRNG - Enables the clock for TRNG * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_TRNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TRNG_SHIFT)) & SYSCON_AHBCLKCTRL2_TRNG_MASK) #define SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK (0x4000U) #define SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT (14U) /*! FLEXCAN0 - Enables the clock for FLEXCAN0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK) #define SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK (0x8000U) #define SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT (15U) /*! FLEXCAN1 - Enables the clock for FLEXCAN1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK) #define SYSCON_AHBCLKCTRL2_USB_HS_MASK (0x10000U) #define SYSCON_AHBCLKCTRL2_USB_HS_SHIFT (16U) /*! USB_HS - Enables the clock for USB HS * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_MASK) #define SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK (0x20000U) #define SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT (17U) /*! USB_HS_PHY - Enables the clock for USB HS PHY * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_USB_HS_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK) #define SYSCON_AHBCLKCTRL2_ELS_MASK (0x40000U) #define SYSCON_AHBCLKCTRL2_ELS_SHIFT (18U) /*! ELS - Enables the clock for ELS * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ELS_SHIFT)) & SYSCON_AHBCLKCTRL2_ELS_MASK) #define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) #define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) /*! PQ - Enables the clock for Powerquad * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) #define SYSCON_AHBCLKCTRL2_PLU_LUT_MASK (0x100000U) #define SYSCON_AHBCLKCTRL2_PLU_LUT_SHIFT (20U) /*! PLU_LUT - Enables the clock for PLU_LUT * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_PLU_LUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLU_LUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLU_LUT_MASK) #define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) #define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) /*! TIMER3 - Enables the clock for CTIMER3 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) #define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) #define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) /*! TIMER4 - Enables the clock for CTIMER4 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) #define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) #define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) /*! PUF - Enables the clock for PUF * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) #define SYSCON_AHBCLKCTRL2_PKC_MASK (0x1000000U) #define SYSCON_AHBCLKCTRL2_PKC_SHIFT (24U) /*! PKC - Enables the clock for PKC * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PKC_SHIFT)) & SYSCON_AHBCLKCTRL2_PKC_MASK) #define SYSCON_AHBCLKCTRL2_SCG_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL2_SCG_SHIFT (26U) /*! SCG - Enables the clock for SCG * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_SCG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SCG_SHIFT)) & SYSCON_AHBCLKCTRL2_SCG_MASK) #define SYSCON_AHBCLKCTRL2_GDET_MASK (0x20000000U) #define SYSCON_AHBCLKCTRL2_GDET_SHIFT (29U) /*! GDET - Enables the clock for GDET0 and GDET1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GDET_SHIFT)) & SYSCON_AHBCLKCTRL2_GDET_MASK) #define SYSCON_AHBCLKCTRL2_SM3_MASK (0x40000000U) #define SYSCON_AHBCLKCTRL2_SM3_SHIFT (30U) /*! SM3 - Enables the clock for SM3 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL2_SM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SM3_SHIFT)) & SYSCON_AHBCLKCTRL2_SM3_MASK) /*! @} */ /*! @name AHBCLKCTRL3 - AHB Clock Control 3 */ /*! @{ */ #define SYSCON_AHBCLKCTRL3_I3C0_MASK (0x1U) #define SYSCON_AHBCLKCTRL3_I3C0_SHIFT (0U) /*! I3C0 - Enables the clock for I3C0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C0_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C0_MASK) #define SYSCON_AHBCLKCTRL3_I3C1_MASK (0x2U) #define SYSCON_AHBCLKCTRL3_I3C1_SHIFT (1U) /*! I3C1 - Enables the clock for I3C1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_I3C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C1_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C1_MASK) #define SYSCON_AHBCLKCTRL3_SINC_MASK (0x4U) #define SYSCON_AHBCLKCTRL3_SINC_SHIFT (2U) /*! SINC - Enables the clock for SINC * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_SINC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_SINC_SHIFT)) & SYSCON_AHBCLKCTRL3_SINC_MASK) #define SYSCON_AHBCLKCTRL3_COOLFLUX_MASK (0x8U) #define SYSCON_AHBCLKCTRL3_COOLFLUX_SHIFT (3U) /*! COOLFLUX - Enables the clock for CoolFlux * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_COOLFLUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_COOLFLUX_SHIFT)) & SYSCON_AHBCLKCTRL3_COOLFLUX_MASK) #define SYSCON_AHBCLKCTRL3_QDC0_MASK (0x10U) #define SYSCON_AHBCLKCTRL3_QDC0_SHIFT (4U) /*! QDC0 - Enables the clock for QDC0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_QDC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC0_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC0_MASK) #define SYSCON_AHBCLKCTRL3_QDC1_MASK (0x20U) #define SYSCON_AHBCLKCTRL3_QDC1_SHIFT (5U) /*! QDC1 - Enables the clock for QDC1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_QDC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC1_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC1_MASK) #define SYSCON_AHBCLKCTRL3_PWM0_MASK (0x40U) #define SYSCON_AHBCLKCTRL3_PWM0_SHIFT (6U) /*! PWM0 - Enables the clock for PWM0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_PWM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM0_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM0_MASK) #define SYSCON_AHBCLKCTRL3_PWM1_MASK (0x80U) #define SYSCON_AHBCLKCTRL3_PWM1_SHIFT (7U) /*! PWM1 - Enables the clock for PWM1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM1_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM1_MASK) #define SYSCON_AHBCLKCTRL3_EVTG_MASK (0x100U) #define SYSCON_AHBCLKCTRL3_EVTG_SHIFT (8U) /*! EVTG - Enables the clock for EVTG * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_EVTG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EVTG_SHIFT)) & SYSCON_AHBCLKCTRL3_EVTG_MASK) #define SYSCON_AHBCLKCTRL3_DAC1_MASK (0x800U) #define SYSCON_AHBCLKCTRL3_DAC1_SHIFT (11U) /*! DAC1 - Enables the clock for DAC1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC1_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC1_MASK) #define SYSCON_AHBCLKCTRL3_DAC2_MASK (0x1000U) #define SYSCON_AHBCLKCTRL3_DAC2_SHIFT (12U) /*! DAC2 - Enables the clock for DAC2 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_DAC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC2_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC2_MASK) #define SYSCON_AHBCLKCTRL3_OPAMP0_MASK (0x2000U) #define SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT (13U) /*! OPAMP0 - Enables the clock for OPAMP0 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP0_MASK) #define SYSCON_AHBCLKCTRL3_OPAMP1_MASK (0x4000U) #define SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT (14U) /*! OPAMP1 - Enables the clock for OPAMP1 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP1_MASK) #define SYSCON_AHBCLKCTRL3_OPAMP2_MASK (0x8000U) #define SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT (15U) /*! OPAMP2 - Enables the clock for OPAMP2 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP2_MASK) #define SYSCON_AHBCLKCTRL3_CMP2_MASK (0x40000U) #define SYSCON_AHBCLKCTRL3_CMP2_SHIFT (18U) /*! CMP2 - Enables the clock for CMP2 * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_CMP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_CMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_CMP2_MASK) #define SYSCON_AHBCLKCTRL3_VREF_MASK (0x80000U) #define SYSCON_AHBCLKCTRL3_VREF_SHIFT (19U) /*! VREF - Enables the clock for VREF * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_VREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_VREF_SHIFT)) & SYSCON_AHBCLKCTRL3_VREF_MASK) #define SYSCON_AHBCLKCTRL3_COOLFLUX_APB_MASK (0x100000U) #define SYSCON_AHBCLKCTRL3_COOLFLUX_APB_SHIFT (20U) /*! COOLFLUX_APB - Enables the clock for CoolFlux APB * 0b1..Enables clock (CoolFlux needs to be properly programmed before the clock enabled.) * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_COOLFLUX_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_COOLFLUX_APB_SHIFT)) & SYSCON_AHBCLKCTRL3_COOLFLUX_APB_MASK) #define SYSCON_AHBCLKCTRL3_NPU_MASK (0x200000U) #define SYSCON_AHBCLKCTRL3_NPU_SHIFT (21U) /*! NPU - Enables the clock for NPU * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_NPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_NPU_SHIFT)) & SYSCON_AHBCLKCTRL3_NPU_MASK) #define SYSCON_AHBCLKCTRL3_TSI_MASK (0x400000U) #define SYSCON_AHBCLKCTRL3_TSI_SHIFT (22U) /*! TSI - Enables the clock for TSI * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_TSI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_TSI_SHIFT)) & SYSCON_AHBCLKCTRL3_TSI_MASK) #define SYSCON_AHBCLKCTRL3_EWM_MASK (0x800000U) #define SYSCON_AHBCLKCTRL3_EWM_SHIFT (23U) /*! EWM - Enables the clock for EWM * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_EWM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EWM_SHIFT)) & SYSCON_AHBCLKCTRL3_EWM_MASK) #define SYSCON_AHBCLKCTRL3_EIM_MASK (0x1000000U) #define SYSCON_AHBCLKCTRL3_EIM_SHIFT (24U) /*! EIM - Enables the clock for EIM * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_EIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EIM_SHIFT)) & SYSCON_AHBCLKCTRL3_EIM_MASK) #define SYSCON_AHBCLKCTRL3_ERM_MASK (0x2000000U) #define SYSCON_AHBCLKCTRL3_ERM_SHIFT (25U) /*! ERM - Enables the clock for ERM * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_ERM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ERM_SHIFT)) & SYSCON_AHBCLKCTRL3_ERM_MASK) #define SYSCON_AHBCLKCTRL3_INTM_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL3_INTM_SHIFT (26U) /*! INTM - Enables the clock for INTM * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_INTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_INTM_SHIFT)) & SYSCON_AHBCLKCTRL3_INTM_MASK) #define SYSCON_AHBCLKCTRL3_SEMA42_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL3_SEMA42_SHIFT (27U) /*! SEMA42 - Enables the clock for Semaphore * 0b1..Enables clock * 0b0..Disables clock */ #define SYSCON_AHBCLKCTRL3_SEMA42(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_SEMA42_SHIFT)) & SYSCON_AHBCLKCTRL3_SEMA42_MASK) /*! @} */ /*! @name AHBCLKCTRLSET - AHB Clock Control Set */ /*! @{ */ #define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) /*! DATA - Data array value */ #define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) /*! @} */ /* The count of SYSCON_AHBCLKCTRLSET */ #define SYSCON_AHBCLKCTRLSET_COUNT (4U) /*! @name AHBCLKCTRLCLR - AHB Clock Control Clear */ /*! @{ */ #define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) /*! DATA - Data array value */ #define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) /*! @} */ /* The count of SYSCON_AHBCLKCTRLCLR */ #define SYSCON_AHBCLKCTRLCLR_COUNT (4U) /*! @name SYSTICKCLKSEL0 - CPU0 System Tick Timer Source Select */ /*! @{ */ #define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) #define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) /*! SEL - Selects the System Tick Timer for CPU0 source * 0b000..SYSTICKCLKDIV0 output * 0b001..Clk 1 MHz clock * 0b010..LP Oscillator clock * 0b011..No clock * 0b100..No clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) /*! @} */ /*! @name SYSTICKCLKSEL1 - CPU1 System Tick Timer Source Select */ /*! @{ */ #define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) #define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) /*! SEL - Selects the System Tick Timer for CPU1 source. * 0b000..SYSTICKCLKDIV1 output * 0b001..Clk 1 MHz clock * 0b010..LP Oscillator clock * 0b011..No clock * 0b100..No clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) /*! @} */ /*! @name TRACECLKSEL - Trace Clock Source Select */ /*! @{ */ #define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) #define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the trace clock source. * 0b000..TRACECLKDIV output * 0b001..Clk 1 MHz clock * 0b010..LP Oscillator clock * 0b011..No clock * 0b100..No clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) /*! @} */ /*! @name CTIMERCLKSEL - CTIMER Clock Source Select */ /*! @{ */ #define SYSCON_CTIMERCLKSEL_SEL_MASK (0xFU) #define SYSCON_CTIMERCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the CTIMER clock source. * 0b0000..FRO_1M clock * 0b0001..PLL0 clock * 0b0010..PLL1_clk0 clock * 0b0011..FRO_HF clock * 0b0100..FRO 12MHz clock * 0b0101..SAI0 MCLK IN clock * 0b0110..LP Oscillator clock * 0b0111..No clock * 0b1000..SAI1 MCLK IN clock * 0b1001..SAI0 TX_BCLK clock * 0b1010..SAI0 RX_BCLK clock * 0b1011..SAI1 TX_BCLK clock * 0b1100..SAI1 RX_BCLK clock * 0b1101..No clock * 0b1110..No clock * 0b1111..No clock */ #define SYSCON_CTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL_SEL_MASK) /*! @} */ /* The count of SYSCON_CTIMERCLKSEL */ #define SYSCON_CTIMERCLKSEL_COUNT (5U) /*! @name CLKOUTSEL - CLKOUT Clock Source Select */ /*! @{ */ #define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) #define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) /*! SEL - Selects the CLKOUT clock source. * 0b0000..Main clock (main_clk) * 0b0001..PLL0 clock (pll0_clk) * 0b0010..CLKIN clock (clk_in) * 0b0011..FRO_HF clock (fro_hf) * 0b0100..FRO 12 MHz clock (fro_12m) * 0b0101..PLL1_clk0 clock (pll1_clk) * 0b0110..LP Oscillator clock (lp_osc) * 0b0111..USB PLL clock (usb_pll_clk) * 0b1000..No clock * 0b1001..No clock * 0b1010..No clock * 0b1011..No clock * 0b1100..No clock * 0b1101..No clock * 0b1110..No clock * 0b1111..No clock */ #define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) /*! @} */ /*! @name ADC0CLKSEL - ADC0 Clock Source Select */ /*! @{ */ #define SYSCON_ADC0CLKSEL_SEL_MASK (0x7U) #define SYSCON_ADC0CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the ADC0 clock source. * 0b000..No clock * 0b001..PLL0 clock * 0b010..FRO_HF clock * 0b011..FRO 12 MHz clock * 0b100..Clk_in * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_ADC0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKSEL_SEL_SHIFT)) & SYSCON_ADC0CLKSEL_SEL_MASK) /*! @} */ /*! @name USB0CLKSEL - USB-FS Clock Source Select */ /*! @{ */ #define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) #define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the USB-FS clock source. * 0b000..No clock * 0b001..PLL0 clock * 0b010..No clock * 0b011..Clk 48 MHz clock * 0b100..Clk_in * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) /*! @} */ /*! @name FCCLKSEL - LP_FLEXCOMM Clock Source Select for Fractional Rate Divider */ /*! @{ */ #define SYSCON_FCCLKSEL_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the LP_FLEXCOMM clock source for Fractional Rate Divider. * 0b000..No clock * 0b001..PLL divided clock * 0b010..FRO 12 MHz clock * 0b011..fro_hf_div clock * 0b100..clk_1m clock * 0b101..USB PLL clock * 0b110..LP Oscillator clock * 0b111..No clock */ #define SYSCON_FCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL_SEL_SHIFT)) & SYSCON_FCCLKSEL_SEL_MASK) /*! @} */ /* The count of SYSCON_FCCLKSEL */ #define SYSCON_FCCLKSEL_COUNT (10U) /*! @name SCTCLKSEL - SCTimer/PWM Clock Source Select */ /*! @{ */ #define SYSCON_SCTCLKSEL_SEL_MASK (0xFU) #define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the SCTimer/PWM clock source. * 0b0000..No clock * 0b0001..PLL0 clock * 0b0010..CLKIN clock * 0b0011..FRO_HF clock * 0b0100..PLL1_clk0 clock * 0b0101..SAI0 MCLK_IN clock * 0b0110..USB PLL clock * 0b0111..No clock * 0b1000..SAI1 MCLK_IN clock * 0b1001..No clock * 0b1010..No clock * 0b1011..No clock * 0b1100..No clock * 0b1101..No clock * 0b1110..No clock * 0b1111..No clock */ #define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) /*! @} */ /*! @name SYSTICKCLKDIV - CPU0 System Tick Timer Divider..CPU1 System Tick Timer Divider */ /*! @{ */ #define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) #define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset. * 0b0..Divider is not reset */ #define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) #define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) #define SYSCON_SYSTICKCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_SYSTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_SYSTICKCLKDIV_UNSTAB_MASK) /*! @} */ /* The count of SYSCON_SYSTICKCLKDIV */ #define SYSCON_SYSTICKCLKDIV_COUNT (2U) /*! @name TRACECLKDIV - TRACE Clock Divider */ /*! @{ */ #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) #define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) #define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) #define SYSCON_TRACECLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_TRACECLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_TRACECLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_UNSTAB_SHIFT)) & SYSCON_TRACECLKDIV_UNSTAB_MASK) /*! @} */ /*! @name TSICLKSEL - TSI Function Clock Source Select */ /*! @{ */ #define SYSCON_TSICLKSEL_SEL_MASK (0x7U) #define SYSCON_TSICLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the TSI function clock source. * 0b000..No clock * 0b001..No clock * 0b010..clk_in * 0b011..No clock * 0b100..FRO_12Mhz clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_TSICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKSEL_SEL_SHIFT)) & SYSCON_TSICLKSEL_SEL_MASK) /*! @} */ /*! @name SINCFILTCLKSEL - SINC FILTER Function Clock Source Select */ /*! @{ */ #define SYSCON_SINCFILTCLKSEL_SEL_MASK (0x7U) #define SYSCON_SINCFILTCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the SINC FILTER function clock source. * 0b000..No clock * 0b001..PLL0 clock * 0b010..clk_in * 0b011..FRO_HF clock * 0b100..FRO_12Mhz clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_SINCFILTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SINCFILTCLKSEL_SEL_SHIFT)) & SYSCON_SINCFILTCLKSEL_SEL_MASK) /*! @} */ /*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */ /*! @{ */ #define SYSCON_SLOWCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SLOWCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_SLOWCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK) #define SYSCON_SLOWCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SLOWCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_SLOWCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK) #define SYSCON_SLOWCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_SLOWCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name TSICLKDIV - TSI Function Clock Divider */ /*! @{ */ #define SYSCON_TSICLKDIV_DIV_MASK (0xFFU) #define SYSCON_TSICLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value: */ #define SYSCON_TSICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKDIV_DIV_SHIFT)) & SYSCON_TSICLKDIV_DIV_MASK) #define SYSCON_TSICLKDIV_RESET_MASK (0x20000000U) #define SYSCON_TSICLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_TSICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKDIV_RESET_SHIFT)) & SYSCON_TSICLKDIV_RESET_MASK) #define SYSCON_TSICLKDIV_HALT_MASK (0x40000000U) #define SYSCON_TSICLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_TSICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKDIV_HALT_SHIFT)) & SYSCON_TSICLKDIV_HALT_MASK) #define SYSCON_TSICLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_TSICLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_TSICLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TSICLKDIV_UNSTAB_SHIFT)) & SYSCON_TSICLKDIV_UNSTAB_MASK) /*! @} */ /*! @name AHBCLKDIV - System Clock Divider */ /*! @{ */ #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) #define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CLKOUTDIV - CLKOUT Clock Divider */ /*! @{ */ #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) #define SYSCON_CLKOUTDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_CLKOUTDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_CLKOUTDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_UNSTAB_SHIFT)) & SYSCON_CLKOUTDIV_UNSTAB_MASK) /*! @} */ /*! @name FROHFDIV - FRO_HF_DIV Clock Divider */ /*! @{ */ #define SYSCON_FROHFDIV_DIV_MASK (0xFFU) #define SYSCON_FROHFDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) #define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) #define SYSCON_FROHFDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running, this bit is set to 0 when the register is written. */ #define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) #define SYSCON_FROHFDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_FROHFDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_FROHFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK) /*! @} */ /*! @name WDT0CLKDIV - WDT0 Clock Divider */ /*! @{ */ #define SYSCON_WDT0CLKDIV_DIV_MASK (0x3FU) #define SYSCON_WDT0CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_WDT0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_DIV_SHIFT)) & SYSCON_WDT0CLKDIV_DIV_MASK) #define SYSCON_WDT0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_WDT0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_WDT0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_RESET_SHIFT)) & SYSCON_WDT0CLKDIV_RESET_MASK) #define SYSCON_WDT0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_WDT0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_WDT0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_HALT_SHIFT)) & SYSCON_WDT0CLKDIV_HALT_MASK) #define SYSCON_WDT0CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_WDT0CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_WDT0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT0CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name ADC0CLKDIV - ADC0 Clock Divider */ /*! @{ */ #define SYSCON_ADC0CLKDIV_DIV_MASK (0x7U) #define SYSCON_ADC0CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_ADC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_DIV_SHIFT)) & SYSCON_ADC0CLKDIV_DIV_MASK) #define SYSCON_ADC0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_ADC0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_ADC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_RESET_SHIFT)) & SYSCON_ADC0CLKDIV_RESET_MASK) #define SYSCON_ADC0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_ADC0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_ADC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_HALT_SHIFT)) & SYSCON_ADC0CLKDIV_HALT_MASK) #define SYSCON_ADC0CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_ADC0CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_ADC0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC0CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name USB0CLKDIV - USB-FS Clock Divider */ /*! @{ */ #define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) #define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) #define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) #define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) #define SYSCON_USB0CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_USB0CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_USB0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_UNSTAB_SHIFT)) & SYSCON_USB0CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name SCTCLKDIV - SCT/PWM Clock Divider */ /*! @{ */ #define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) #define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) #define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) #define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) #define SYSCON_SCTCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_SCTCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_SCTCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_UNSTAB_SHIFT)) & SYSCON_SCTCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name PLLCLKDIV - PLL Clock Divider */ /*! @{ */ #define SYSCON_PLLCLKDIV_DIV_MASK (0xFFU) #define SYSCON_PLLCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_PLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_DIV_SHIFT)) & SYSCON_PLLCLKDIV_DIV_MASK) #define SYSCON_PLLCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_PLLCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_PLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_RESET_SHIFT)) & SYSCON_PLLCLKDIV_RESET_MASK) #define SYSCON_PLLCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_PLLCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_PLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_HALT_SHIFT)) & SYSCON_PLLCLKDIV_HALT_MASK) #define SYSCON_PLLCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_PLLCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_PLLCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_UNSTAB_SHIFT)) & SYSCON_PLLCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CTIMERXCLKDIV_CTIMERCLKDIV - CTimer Clock Divider */ /*! @{ */ #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK (0xFFU) #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK) #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK) #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b0..Divider clock is running * 0b1..Divider clock has stopped */ #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK) #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b0..Stable divider clock * 0b1..Unstable clock frequency */ #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK) /*! @} */ /* The count of SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV */ #define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_COUNT (5U) /*! @name PLL1CLK0DIV - PLL1 Clock 0 Divider */ /*! @{ */ #define SYSCON_PLL1CLK0DIV_DIV_MASK (0xFFU) #define SYSCON_PLL1CLK0DIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_PLL1CLK0DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_DIV_SHIFT)) & SYSCON_PLL1CLK0DIV_DIV_MASK) #define SYSCON_PLL1CLK0DIV_RESET_MASK (0x20000000U) #define SYSCON_PLL1CLK0DIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_PLL1CLK0DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_RESET_SHIFT)) & SYSCON_PLL1CLK0DIV_RESET_MASK) #define SYSCON_PLL1CLK0DIV_HALT_MASK (0x40000000U) #define SYSCON_PLL1CLK0DIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_PLL1CLK0DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_HALT_SHIFT)) & SYSCON_PLL1CLK0DIV_HALT_MASK) #define SYSCON_PLL1CLK0DIV_UNSTAB_MASK (0x80000000U) #define SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_PLL1CLK0DIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK0DIV_UNSTAB_MASK) /*! @} */ /*! @name PLL1CLK1DIV - PLL1 Clock 1 Divider */ /*! @{ */ #define SYSCON_PLL1CLK1DIV_DIV_MASK (0xFFU) #define SYSCON_PLL1CLK1DIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_PLL1CLK1DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_DIV_SHIFT)) & SYSCON_PLL1CLK1DIV_DIV_MASK) #define SYSCON_PLL1CLK1DIV_RESET_MASK (0x20000000U) #define SYSCON_PLL1CLK1DIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_PLL1CLK1DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_RESET_SHIFT)) & SYSCON_PLL1CLK1DIV_RESET_MASK) #define SYSCON_PLL1CLK1DIV_HALT_MASK (0x40000000U) #define SYSCON_PLL1CLK1DIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_PLL1CLK1DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_HALT_SHIFT)) & SYSCON_PLL1CLK1DIV_HALT_MASK) #define SYSCON_PLL1CLK1DIV_UNSTAB_MASK (0x80000000U) #define SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_PLL1CLK1DIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK1DIV_UNSTAB_MASK) /*! @} */ /*! @name UTICKCLKDIV - UTICK Clock Divider */ /*! @{ */ #define SYSCON_UTICKCLKDIV_DIV_MASK (0x3FU) #define SYSCON_UTICKCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_UTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_DIV_SHIFT)) & SYSCON_UTICKCLKDIV_DIV_MASK) #define SYSCON_UTICKCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_UTICKCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_UTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_RESET_SHIFT)) & SYSCON_UTICKCLKDIV_RESET_MASK) #define SYSCON_UTICKCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_UTICKCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_UTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_HALT_SHIFT)) & SYSCON_UTICKCLKDIV_HALT_MASK) #define SYSCON_UTICKCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_UTICKCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_UTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_UTICKCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CLKOUT_FRGCTRL - CLKOUT FRG Control */ /*! @{ */ #define SYSCON_CLKOUT_FRGCTRL_DIV_MASK (0xFFU) #define SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT (0U) /*! DIV - Divider value */ #define SYSCON_CLKOUT_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_DIV_MASK) #define SYSCON_CLKOUT_FRGCTRL_MULT_MASK (0xFF00U) #define SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT (8U) /*! MULT - Numerator value */ #define SYSCON_CLKOUT_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_MULT_MASK) /*! @} */ /*! @name CLKUNLOCK - Clock Configuration Unlock */ /*! @{ */ #define SYSCON_CLKUNLOCK_UNLOCK_MASK (0x1U) #define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) /*! UNLOCK - Controls clock configuration registers access (for example, xxxDIV, xxxSEL) * 0b1..Freezes all clock configuration registers update * 0b0..Updates are allowed to all clock configuration registers */ #define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) /*! @} */ /*! @name NVM_CTRL - NVM Control */ /*! @{ */ #define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK (0x1U) #define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT (0U) /*! DIS_FLASH_SPEC - Flash speculation control * 0b0..Enables flash speculation * 0b1..Disables flash speculation */ #define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK) #define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK (0x2U) #define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT (1U) /*! DIS_DATA_SPEC - Flash data speculation control * 0b0..Enables data speculation * 0b1..Disables data speculation */ #define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK) #define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK (0x4U) #define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT (2U) /*! DIS_FLASH_CACHE - Flash cache control * 0b0..Enables flash cache * 0b1..Disables flash cache */ #define SYSCON_NVM_CTRL_DIS_FLASH_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK) #define SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK (0x8U) #define SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT (3U) /*! DIS_FLASH_INST - Flash instruction cache control * 0b0..Enables flash instruction cache when DIS_FLASH_CACHE=0 * 0b1..Disables flash instruction cache */ #define SYSCON_NVM_CTRL_DIS_FLASH_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK) #define SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK (0x10U) #define SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT (4U) /*! DIS_FLASH_DATA - Flash data cache control * 0b0..Enables flash data cache when DIS_FLASH_CACHE=0 * 0b1..Disables flash data cache */ #define SYSCON_NVM_CTRL_DIS_FLASH_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK) #define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK (0x20U) #define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT (5U) /*! CLR_FLASH_CACHE - Clear flash cache control * 0b0..No clear flash cache * 0b1..Clears flash cache */ #define SYSCON_NVM_CTRL_CLR_FLASH_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK) #define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK (0x400U) #define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT (10U) /*! FLASH_STALL_EN - FLASH stall on busy control * 0b0..No stall on FLASH busy * 0b1..Stall on FLASH busy */ #define SYSCON_NVM_CTRL_FLASH_STALL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK) #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U) #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U) /*! DIS_MBECC_ERR_INST * 0b0..Enables bus error on multi-bit ECC error for instruction * 0b1..Disables bus error on multi-bit ECC error for instruction */ #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK) #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U) #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U) /*! DIS_MBECC_ERR_DATA * 0b0..Enables bus error on multi-bit ECC error for data * 0b1..Disables bus error on multi-bit ECC error for data */ #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK) /*! @} */ /*! @name ROMCR - ROM Wait State */ /*! @{ */ #define SYSCON_ROMCR_ROM_WAIT_MASK (0x1U) #define SYSCON_ROMCR_ROM_WAIT_SHIFT (0U) /*! ROM_WAIT - ROM waiting Arm core and other masters for one cycle * 0b0..Disabled * 0b1..Enabled */ #define SYSCON_ROMCR_ROM_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK) /*! @} */ /*! @name SMARTDMAINT - SmartDMA Interrupt Hijack */ /*! @{ */ #define SYSCON_SMARTDMAINT_INT0_MASK (0x1U) #define SYSCON_SMARTDMAINT_INT0_SHIFT (0U) /*! INT0 - SmartDMA hijack NVIC IRQ1 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT0_SHIFT)) & SYSCON_SMARTDMAINT_INT0_MASK) #define SYSCON_SMARTDMAINT_INT1_MASK (0x2U) #define SYSCON_SMARTDMAINT_INT1_SHIFT (1U) /*! INT1 - SmartDMA hijack NVIC IRQ17 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT1_SHIFT)) & SYSCON_SMARTDMAINT_INT1_MASK) #define SYSCON_SMARTDMAINT_INT2_MASK (0x4U) #define SYSCON_SMARTDMAINT_INT2_SHIFT (2U) /*! INT2 - SmartDMA hijack NVIC IRQ18 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT2_SHIFT)) & SYSCON_SMARTDMAINT_INT2_MASK) #define SYSCON_SMARTDMAINT_INT3_MASK (0x8U) #define SYSCON_SMARTDMAINT_INT3_SHIFT (3U) /*! INT3 - SmartDMA hijack NVIC IRQ29 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT3_SHIFT)) & SYSCON_SMARTDMAINT_INT3_MASK) #define SYSCON_SMARTDMAINT_INT4_MASK (0x10U) #define SYSCON_SMARTDMAINT_INT4_SHIFT (4U) /*! INT4 - SmartDMA hijack NVIC IRQ30 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT4_SHIFT)) & SYSCON_SMARTDMAINT_INT4_MASK) #define SYSCON_SMARTDMAINT_INT5_MASK (0x20U) #define SYSCON_SMARTDMAINT_INT5_SHIFT (5U) /*! INT5 - SmartDMA hijack NVIC IRQ31 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT5_SHIFT)) & SYSCON_SMARTDMAINT_INT5_MASK) #define SYSCON_SMARTDMAINT_INT6_MASK (0x40U) #define SYSCON_SMARTDMAINT_INT6_SHIFT (6U) /*! INT6 - SmartDMA hijack NVIC IRQ32 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT6_SHIFT)) & SYSCON_SMARTDMAINT_INT6_MASK) #define SYSCON_SMARTDMAINT_INT7_MASK (0x80U) #define SYSCON_SMARTDMAINT_INT7_SHIFT (7U) /*! INT7 - SmartDMA hijack NVIC IRQ33 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT7_SHIFT)) & SYSCON_SMARTDMAINT_INT7_MASK) #define SYSCON_SMARTDMAINT_INT8_MASK (0x100U) #define SYSCON_SMARTDMAINT_INT8_SHIFT (8U) /*! INT8 - SmartDMA hijack NVIC IRQ34 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT8_SHIFT)) & SYSCON_SMARTDMAINT_INT8_MASK) #define SYSCON_SMARTDMAINT_INT9_MASK (0x200U) #define SYSCON_SMARTDMAINT_INT9_SHIFT (9U) /*! INT9 - SmartDMA hijack NVIC IRQ35 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT9_SHIFT)) & SYSCON_SMARTDMAINT_INT9_MASK) #define SYSCON_SMARTDMAINT_INT10_MASK (0x400U) #define SYSCON_SMARTDMAINT_INT10_SHIFT (10U) /*! INT10 - SmartDMA hijack NVIC IRQ36 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT10_SHIFT)) & SYSCON_SMARTDMAINT_INT10_MASK) #define SYSCON_SMARTDMAINT_INT11_MASK (0x800U) #define SYSCON_SMARTDMAINT_INT11_SHIFT (11U) /*! INT11 - SmartDMA hijack NVIC IRQ37 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT11(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT11_SHIFT)) & SYSCON_SMARTDMAINT_INT11_MASK) #define SYSCON_SMARTDMAINT_INT12_MASK (0x1000U) #define SYSCON_SMARTDMAINT_INT12_SHIFT (12U) /*! INT12 - SmartDMA hijack NVIC IRQ38 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT12(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT12_SHIFT)) & SYSCON_SMARTDMAINT_INT12_MASK) #define SYSCON_SMARTDMAINT_INT13_MASK (0x2000U) #define SYSCON_SMARTDMAINT_INT13_SHIFT (13U) /*! INT13 - SmartDMA hijack NVIC IRQ39 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT13(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT13_SHIFT)) & SYSCON_SMARTDMAINT_INT13_MASK) #define SYSCON_SMARTDMAINT_INT14_MASK (0x4000U) #define SYSCON_SMARTDMAINT_INT14_SHIFT (14U) /*! INT14 - SmartDMA hijack NVIC IRQ40 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT14(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT14_SHIFT)) & SYSCON_SMARTDMAINT_INT14_MASK) #define SYSCON_SMARTDMAINT_INT15_MASK (0x8000U) #define SYSCON_SMARTDMAINT_INT15_SHIFT (15U) /*! INT15 - SmartDMA hijack NVIC IRQ41 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT15(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT15_SHIFT)) & SYSCON_SMARTDMAINT_INT15_MASK) #define SYSCON_SMARTDMAINT_INT16_MASK (0x10000U) #define SYSCON_SMARTDMAINT_INT16_SHIFT (16U) /*! INT16 - SmartDMA hijack NVIC IRQ42 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT16_SHIFT)) & SYSCON_SMARTDMAINT_INT16_MASK) #define SYSCON_SMARTDMAINT_INT17_MASK (0x20000U) #define SYSCON_SMARTDMAINT_INT17_SHIFT (17U) /*! INT17 - SmartDMA hijack NVIC IRQ45 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT17(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT17_SHIFT)) & SYSCON_SMARTDMAINT_INT17_MASK) #define SYSCON_SMARTDMAINT_INT18_MASK (0x40000U) #define SYSCON_SMARTDMAINT_INT18_SHIFT (18U) /*! INT18 - SmartDMA hijack NVIC IRQ47 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT18(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT18_SHIFT)) & SYSCON_SMARTDMAINT_INT18_MASK) #define SYSCON_SMARTDMAINT_INT19_MASK (0x80000U) #define SYSCON_SMARTDMAINT_INT19_SHIFT (19U) /*! INT19 - SmartDMA hijack NVIC IRQ50 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT19(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT19_SHIFT)) & SYSCON_SMARTDMAINT_INT19_MASK) #define SYSCON_SMARTDMAINT_INT20_MASK (0x100000U) #define SYSCON_SMARTDMAINT_INT20_SHIFT (20U) /*! INT20 - SmartDMA hijack NVIC IRQ51 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT20(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT20_SHIFT)) & SYSCON_SMARTDMAINT_INT20_MASK) #define SYSCON_SMARTDMAINT_INT21_MASK (0x200000U) #define SYSCON_SMARTDMAINT_INT21_SHIFT (21U) /*! INT21 - SmartDMA hijack NVIC IRQ66 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT21(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT21_SHIFT)) & SYSCON_SMARTDMAINT_INT21_MASK) #define SYSCON_SMARTDMAINT_INT22_MASK (0x400000U) #define SYSCON_SMARTDMAINT_INT22_SHIFT (22U) /*! INT22 - SmartDMA hijack NVIC IRQ67 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT22(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT22_SHIFT)) & SYSCON_SMARTDMAINT_INT22_MASK) #define SYSCON_SMARTDMAINT_INT23_MASK (0x800000U) #define SYSCON_SMARTDMAINT_INT23_SHIFT (23U) /*! INT23 - SmartDMA hijack NVIC IRQ77 * 0b0..Disable * 0b1..Enable */ #define SYSCON_SMARTDMAINT_INT23(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT23_SHIFT)) & SYSCON_SMARTDMAINT_INT23_MASK) /*! @} */ /*! @name ADC1CLKSEL - ADC1 Clock Source Select */ /*! @{ */ #define SYSCON_ADC1CLKSEL_SEL_MASK (0x7U) #define SYSCON_ADC1CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the ADC1 clock source * 0b000..No clock * 0b001..PLL0 clock * 0b010..FRO_HF clock * 0b011..FRO 12 MHz clock * 0b100..Clk_in clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_ADC1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKSEL_SEL_SHIFT)) & SYSCON_ADC1CLKSEL_SEL_MASK) /*! @} */ /*! @name ADC1CLKDIV - ADC1 Clock Divider */ /*! @{ */ #define SYSCON_ADC1CLKDIV_DIV_MASK (0x7U) #define SYSCON_ADC1CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_ADC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_DIV_SHIFT)) & SYSCON_ADC1CLKDIV_DIV_MASK) #define SYSCON_ADC1CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_ADC1CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_ADC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_RESET_SHIFT)) & SYSCON_ADC1CLKDIV_RESET_MASK) #define SYSCON_ADC1CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_ADC1CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_ADC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_HALT_SHIFT)) & SYSCON_ADC1CLKDIV_HALT_MASK) #define SYSCON_ADC1CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_ADC1CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_ADC1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC1CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name RAM_INTERLEAVE - Control PKC RAM Interleave Access */ /*! @{ */ #define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK (0x1U) #define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT (0U) /*! INTERLEAVE - Controls PKC RAM access for PKC RAM 0 and PKC RAM 1 * 0b1..RAM access to PKC RAM 0 and PKC RAM 1 is interleaved. This setting is need for PKC L0 memory access. * 0b0..RAM access to PKC RAM 0 and PKC RAM 1 is consecutive. */ #define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK) /*! @} */ /*! @name DAC_CLKSEL - DAC0 Functional Clock Selection..DAC2 Functional Clock Selection */ /*! @{ */ #define SYSCON_DAC_CLKSEL_SEL_MASK (0x7U) #define SYSCON_DAC_CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the DAC clock source * 0b000..No clock * 0b001..PLL0 clock * 0b010..Clk_in * 0b011..FRO_HF * 0b100..FRO_12M * 0b101..PLL1_clk0 clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_DAC_CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKSEL_SEL_SHIFT)) & SYSCON_DAC_CLKSEL_SEL_MASK) /*! @} */ /* The count of SYSCON_DAC_CLKSEL */ #define SYSCON_DAC_CLKSEL_COUNT (3U) /*! @name DAC_CLKDIV - DAC0 functional clock divider..DAC2 functional clock divider */ /*! @{ */ #define SYSCON_DAC_CLKDIV_DIV_MASK (0x7U) #define SYSCON_DAC_CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_DAC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_DIV_SHIFT)) & SYSCON_DAC_CLKDIV_DIV_MASK) #define SYSCON_DAC_CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_DAC_CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_DAC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_RESET_SHIFT)) & SYSCON_DAC_CLKDIV_RESET_MASK) #define SYSCON_DAC_CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_DAC_CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_DAC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_HALT_SHIFT)) & SYSCON_DAC_CLKDIV_HALT_MASK) #define SYSCON_DAC_CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_DAC_CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_DAC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_UNSTAB_SHIFT)) & SYSCON_DAC_CLKDIV_UNSTAB_MASK) /*! @} */ /* The count of SYSCON_DAC_CLKDIV */ #define SYSCON_DAC_CLKDIV_COUNT (3U) /*! @name FLEXSPICLKSEL - FlexSPI Clock Selection */ /*! @{ */ #define SYSCON_FLEXSPICLKSEL_SEL_MASK (0xFU) #define SYSCON_FLEXSPICLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the FlexSPI clock * 0b0000..No clock * 0b0001..PLL0 clock * 0b0010..No clock * 0b0011..FRO_HF * 0b0100..No clock * 0b0101..pll1_clock * 0b0110..USB PLL clock * 0b0111..No clock * 0b1000..No clock * 0b1001..No clock * 0b1010..No clock * 0b1011..No clock * 0b1100..No clock * 0b1101..No clock * 0b1110..No clock * 0b1111..No clock */ #define SYSCON_FLEXSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKSEL_SEL_SHIFT)) & SYSCON_FLEXSPICLKSEL_SEL_MASK) /*! @} */ /*! @name FLEXSPICLKDIV - FlexSPI Clock Divider */ /*! @{ */ #define SYSCON_FLEXSPICLKDIV_DIV_MASK (0x7U) #define SYSCON_FLEXSPICLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_FLEXSPICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_DIV_SHIFT)) & SYSCON_FLEXSPICLKDIV_DIV_MASK) #define SYSCON_FLEXSPICLKDIV_RESET_MASK (0x20000000U) #define SYSCON_FLEXSPICLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_FLEXSPICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_RESET_SHIFT)) & SYSCON_FLEXSPICLKDIV_RESET_MASK) #define SYSCON_FLEXSPICLKDIV_HALT_MASK (0x40000000U) #define SYSCON_FLEXSPICLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_FLEXSPICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_HALT_SHIFT)) & SYSCON_FLEXSPICLKDIV_HALT_MASK) #define SYSCON_FLEXSPICLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_FLEXSPICLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXSPICLKDIV_UNSTAB_MASK) /*! @} */ /*! @name PLLCLKDIVSEL - PLL Clock Divider Clock Selection */ /*! @{ */ #define SYSCON_PLLCLKDIVSEL_SEL_MASK (0x7U) #define SYSCON_PLLCLKDIVSEL_SEL_SHIFT (0U) /*! SEL - Selects the PLL Clock Divider source clock * 0b000..PLL0 clock * 0b001..pll1_clk0 * 0b010..No clock * 0b011..No clock * 0b100..No clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_PLLCLKDIVSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIVSEL_SEL_SHIFT)) & SYSCON_PLLCLKDIVSEL_SEL_MASK) /*! @} */ /*! @name I3C0FCLKSEL - I3C0 Functional Clock Selection */ /*! @{ */ #define SYSCON_I3C0FCLKSEL_SEL_MASK (0x7U) #define SYSCON_I3C0FCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the I3C0 clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..No clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_I3C0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSEL_SEL_MASK) /*! @} */ /*! @name I3C0FCLKSTCSEL - I3C0 FCLK_STC Clock Selection */ /*! @{ */ #define SYSCON_I3C0FCLKSTCSEL_SEL_MASK (0x7U) #define SYSCON_I3C0FCLKSTCSEL_SEL_SHIFT (0U) /*! SEL - Selects the I3C0 Time Control clock * 0b000..I3C0 functional clock I3C0FCLK * 0b001..FRO_1M clock * 0b010..No clock * 0b011..No clock * 0b100..No clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_I3C0FCLKSTCSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSTCSEL_SEL_MASK) /*! @} */ /*! @name I3C0FCLKSTCDIV - I3C0 FCLK_STC Clock Divider */ /*! @{ */ #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) #define SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_I3C0FCLKSTCDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) #define SYSCON_I3C0FCLKSTCDIV_RESET_MASK (0x20000000U) #define SYSCON_I3C0FCLKSTCDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_I3C0FCLKSTCDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_RESET_MASK) #define SYSCON_I3C0FCLKSTCDIV_HALT_MASK (0x40000000U) #define SYSCON_I3C0FCLKSTCDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_I3C0FCLKSTCDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_HALT_MASK) #define SYSCON_I3C0FCLKSTCDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_I3C0FCLKSTCDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_I3C0FCLKSTCDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_UNSTAB_MASK) /*! @} */ /*! @name I3C0FCLKSDIV - I3C0 FCLK Slow Clock Divider */ /*! @{ */ #define SYSCON_I3C0FCLKSDIV_DIV_MASK (0xFFU) #define SYSCON_I3C0FCLKSDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_I3C0FCLKSDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSDIV_DIV_MASK) #define SYSCON_I3C0FCLKSDIV_RESET_MASK (0x20000000U) #define SYSCON_I3C0FCLKSDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_I3C0FCLKSDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKSDIV_RESET_MASK) #define SYSCON_I3C0FCLKSDIV_HALT_MASK (0x40000000U) #define SYSCON_I3C0FCLKSDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_I3C0FCLKSDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKSDIV_HALT_MASK) #define SYSCON_I3C0FCLKSDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_I3C0FCLKSDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_I3C0FCLKSDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKSDIV_UNSTAB_MASK) /*! @} */ /*! @name I3C0FCLKDIV - I3C0 Functional Clock FCLK Divider */ /*! @{ */ #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) #define SYSCON_I3C0FCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_I3C0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK) #define SYSCON_I3C0FCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_I3C0FCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_I3C0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKDIV_RESET_MASK) #define SYSCON_I3C0FCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_I3C0FCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_I3C0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKDIV_HALT_MASK) #define SYSCON_I3C0FCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_I3C0FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name I3C0FCLKSSEL - I3C0 FCLK Slow Selection */ /*! @{ */ #define SYSCON_I3C0FCLKSSEL_SEL_MASK (0x7U) #define SYSCON_I3C0FCLKSSEL_SEL_SHIFT (0U) /*! SEL - Selects the I3C FCLK Slow clock * 0b000..FRO_1M clock * 0b001..No clock * 0b010..No clock * 0b011..No clock * 0b100..No clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_I3C0FCLKSSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSSEL_SEL_MASK) /*! @} */ /*! @name MICFILFCLKSEL - MICFIL Clock Selection */ /*! @{ */ #define SYSCON_MICFILFCLKSEL_SEL_MASK (0xFU) #define SYSCON_MICFILFCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the MICFIL clock * 0b0000..FRO_12M clock * 0b0001..PLL0 clock * 0b0010..CLKIN clock * 0b0011..FRO_HF clock * 0b0100..PLL1_clk0 clock * 0b0101..SAI0_MCLK clock * 0b0110..USB PLL clock * 0b0111..No clock * 0b1000..SAI1_MCLK clock * 0b1001..No clock * 0b1010..No clock * 0b1011..No clock * 0b1100..No clock * 0b1101..No clock * 0b1110..No clock * 0b1111..No clock */ #define SYSCON_MICFILFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKSEL_SEL_SHIFT)) & SYSCON_MICFILFCLKSEL_SEL_MASK) /*! @} */ /*! @name MICFILFCLKDIV - MICFIL Clock Division */ /*! @{ */ #define SYSCON_MICFILFCLKDIV_DIV_MASK (0x7U) #define SYSCON_MICFILFCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_MICFILFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_DIV_SHIFT)) & SYSCON_MICFILFCLKDIV_DIV_MASK) #define SYSCON_MICFILFCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_MICFILFCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_MICFILFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_RESET_SHIFT)) & SYSCON_MICFILFCLKDIV_RESET_MASK) #define SYSCON_MICFILFCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_MICFILFCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_MICFILFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_HALT_SHIFT)) & SYSCON_MICFILFCLKDIV_HALT_MASK) #define SYSCON_MICFILFCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_MICFILFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT)) & SYSCON_MICFILFCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name USDHCCLKSEL - uSDHC Clock Selection */ /*! @{ */ #define SYSCON_USDHCCLKSEL_SEL_MASK (0x7U) #define SYSCON_USDHCCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the uSDHC clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..FRO_12M clock * 0b101..pll1_clk1 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_USDHCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKSEL_SEL_SHIFT)) & SYSCON_USDHCCLKSEL_SEL_MASK) /*! @} */ /*! @name USDHCCLKDIV - uSDHC Function Clock Divider */ /*! @{ */ #define SYSCON_USDHCCLKDIV_DIV_MASK (0xFFU) #define SYSCON_USDHCCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_USDHCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKDIV_DIV_SHIFT)) & SYSCON_USDHCCLKDIV_DIV_MASK) #define SYSCON_USDHCCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_USDHCCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_USDHCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKDIV_RESET_SHIFT)) & SYSCON_USDHCCLKDIV_RESET_MASK) #define SYSCON_USDHCCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_USDHCCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_USDHCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKDIV_HALT_SHIFT)) & SYSCON_USDHCCLKDIV_HALT_MASK) #define SYSCON_USDHCCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_USDHCCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_USDHCCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USDHCCLKDIV_UNSTAB_SHIFT)) & SYSCON_USDHCCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name FLEXIOCLKSEL - FLEXIO Clock Selection */ /*! @{ */ #define SYSCON_FLEXIOCLKSEL_SEL_MASK (0x7U) #define SYSCON_FLEXIOCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the FLEXIO clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..FRO_12M clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_FLEXIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKSEL_SEL_SHIFT)) & SYSCON_FLEXIOCLKSEL_SEL_MASK) /*! @} */ /*! @name FLEXIOCLKDIV - FLEXIO Function Clock Divider */ /*! @{ */ #define SYSCON_FLEXIOCLKDIV_DIV_MASK (0xFFU) #define SYSCON_FLEXIOCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_FLEXIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_DIV_SHIFT)) & SYSCON_FLEXIOCLKDIV_DIV_MASK) #define SYSCON_FLEXIOCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_FLEXIOCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_FLEXIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_RESET_SHIFT)) & SYSCON_FLEXIOCLKDIV_RESET_MASK) #define SYSCON_FLEXIOCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_FLEXIOCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_FLEXIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_HALT_SHIFT)) & SYSCON_FLEXIOCLKDIV_HALT_MASK) #define SYSCON_FLEXIOCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_FLEXIOCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXIOCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name FLEXCAN0CLKSEL - FLEXCAN0 Clock Selection */ /*! @{ */ #define SYSCON_FLEXCAN0CLKSEL_SEL_MASK (0x7U) #define SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the FLEXCAN0 clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..No clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_FLEXCAN0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN0CLKSEL_SEL_MASK) /*! @} */ /*! @name FLEXCAN0CLKDIV - FLEXCAN0 Function Clock Divider */ /*! @{ */ #define SYSCON_FLEXCAN0CLKDIV_DIV_MASK (0xFFU) #define SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_FLEXCAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_DIV_MASK) #define SYSCON_FLEXCAN0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_FLEXCAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_RESET_MASK) #define SYSCON_FLEXCAN0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_FLEXCAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_HALT_MASK) #define SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_FLEXCAN0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name FLEXCAN1CLKSEL - FLEXCAN1 Clock Selection */ /*! @{ */ #define SYSCON_FLEXCAN1CLKSEL_SEL_MASK (0x7U) #define SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the FLEXCAN1 clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..No clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_FLEXCAN1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN1CLKSEL_SEL_MASK) /*! @} */ /*! @name FLEXCAN1CLKDIV - FLEXCAN1 Function Clock Divider */ /*! @{ */ #define SYSCON_FLEXCAN1CLKDIV_DIV_MASK (0xFFU) #define SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_FLEXCAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_DIV_MASK) #define SYSCON_FLEXCAN1CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_FLEXCAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_RESET_MASK) #define SYSCON_FLEXCAN1CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_FLEXCAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_HALT_MASK) #define SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_FLEXCAN1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name ENETRMIICLKSEL - Ethernet RMII Clock Selection */ /*! @{ */ #define SYSCON_ENETRMIICLKSEL_SEL_MASK (0x7U) #define SYSCON_ENETRMIICLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the Ethernet RMII clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..No clock * 0b100..No clock * 0b101..PLL1_clk0 clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_ENETRMIICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKSEL_SEL_SHIFT)) & SYSCON_ENETRMIICLKSEL_SEL_MASK) /*! @} */ /*! @name ENETRMIICLKDIV - Ethernet RMII Function Clock Divider */ /*! @{ */ #define SYSCON_ENETRMIICLKDIV_DIV_MASK (0xFFU) #define SYSCON_ENETRMIICLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_ENETRMIICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKDIV_DIV_SHIFT)) & SYSCON_ENETRMIICLKDIV_DIV_MASK) #define SYSCON_ENETRMIICLKDIV_RESET_MASK (0x20000000U) #define SYSCON_ENETRMIICLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_ENETRMIICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKDIV_RESET_SHIFT)) & SYSCON_ENETRMIICLKDIV_RESET_MASK) #define SYSCON_ENETRMIICLKDIV_HALT_MASK (0x40000000U) #define SYSCON_ENETRMIICLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_ENETRMIICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKDIV_HALT_SHIFT)) & SYSCON_ENETRMIICLKDIV_HALT_MASK) #define SYSCON_ENETRMIICLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_ENETRMIICLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_ENETRMIICLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETRMIICLKDIV_UNSTAB_SHIFT)) & SYSCON_ENETRMIICLKDIV_UNSTAB_MASK) /*! @} */ /*! @name ENETPTPREFCLKSEL - Ethernet PTP REF Clock Selection */ /*! @{ */ #define SYSCON_ENETPTPREFCLKSEL_SEL_MASK (0x7U) #define SYSCON_ENETPTPREFCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the Ethernet PTP REF clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..No clock * 0b100..enet0_tx_clk clock * 0b101..pll1_clk1 clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_ENETPTPREFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKSEL_SEL_SHIFT)) & SYSCON_ENETPTPREFCLKSEL_SEL_MASK) /*! @} */ /*! @name ENETPTPREFCLKDIV - Ethernet PTP REF Function Clock Divider */ /*! @{ */ #define SYSCON_ENETPTPREFCLKDIV_DIV_MASK (0xFFU) #define SYSCON_ENETPTPREFCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_ENETPTPREFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKDIV_DIV_SHIFT)) & SYSCON_ENETPTPREFCLKDIV_DIV_MASK) #define SYSCON_ENETPTPREFCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_ENETPTPREFCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_ENETPTPREFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKDIV_RESET_SHIFT)) & SYSCON_ENETPTPREFCLKDIV_RESET_MASK) #define SYSCON_ENETPTPREFCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_ENETPTPREFCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_ENETPTPREFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKDIV_HALT_SHIFT)) & SYSCON_ENETPTPREFCLKDIV_HALT_MASK) #define SYSCON_ENETPTPREFCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_ENETPTPREFCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_ENETPTPREFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENETPTPREFCLKDIV_UNSTAB_SHIFT)) & SYSCON_ENETPTPREFCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name ENET_PHY_INTF_SEL - Ethernet PHY Interface Select */ /*! @{ */ #define SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK (0x4U) #define SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_SHIFT (2U) /*! PHY_SEL - Selects the PHY interface * 0b1..Selects RMII PHY Interface * 0b0..Selects MII PHY Interface */ #define SYSCON_ENET_PHY_INTF_SEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_SHIFT)) & SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK) /*! @} */ /*! @name ENET_SBD_FLOW_CTRL - Sideband Flow Control */ /*! @{ */ #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0_MASK (0x1U) #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0_SHIFT (0U) /*! SEL_ch0 - Sideband Flow Control for channel0 * 0b1..Trigger flow control * 0b0..No trigger flow control */ #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0_SHIFT)) & SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch0_MASK) #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1_MASK (0x2U) #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1_SHIFT (1U) /*! SEL_ch1 - Sideband Flow Control for channel1 * 0b1..Trigger flow control * 0b0..No trigger flow control */ #define SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1_SHIFT)) & SYSCON_ENET_SBD_FLOW_CTRL_SEL_ch1_MASK) /*! @} */ /*! @name EWM0CLKSEL - EWM0 Clock Selection */ /*! @{ */ #define SYSCON_EWM0CLKSEL_SEL_MASK (0x1U) #define SYSCON_EWM0CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the EWM0 clock * 0b0..clk_16k[2] * 0b1..xtal32k[2] */ #define SYSCON_EWM0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EWM0CLKSEL_SEL_SHIFT)) & SYSCON_EWM0CLKSEL_SEL_MASK) /*! @} */ /*! @name WDT1CLKSEL - WDT1 Clock Selection */ /*! @{ */ #define SYSCON_WDT1CLKSEL_SEL_MASK (0x3U) #define SYSCON_WDT1CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the WDT1 clock * 0b00..FRO16K clock 2 * 0b01..fro_hf_div clock * 0b10..clk_1m clock * 0b11..clk_1m clock */ #define SYSCON_WDT1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKSEL_SEL_SHIFT)) & SYSCON_WDT1CLKSEL_SEL_MASK) /*! @} */ /*! @name WDT1CLKDIV - WDT1 Function Clock Divider */ /*! @{ */ #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) #define SYSCON_WDT1CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_WDT1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK) #define SYSCON_WDT1CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_WDT1CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_WDT1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_RESET_SHIFT)) & SYSCON_WDT1CLKDIV_RESET_MASK) #define SYSCON_WDT1CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_WDT1CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_WDT1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_HALT_SHIFT)) & SYSCON_WDT1CLKDIV_HALT_MASK) #define SYSCON_WDT1CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_WDT1CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_WDT1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT1CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name OSTIMERCLKSEL - OSTIMER Clock Selection */ /*! @{ */ #define SYSCON_OSTIMERCLKSEL_SEL_MASK (0x3U) #define SYSCON_OSTIMERCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the OS Event Timer clock * 0b00..clk_16k[2] * 0b01..xtal32k[2] * 0b10..clk_1m clock * 0b11..No clock */ #define SYSCON_OSTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_OSTIMERCLKSEL_SEL_SHIFT)) & SYSCON_OSTIMERCLKSEL_SEL_MASK) /*! @} */ /*! @name CMP0FCLKSEL - CMP0 Function Clock Selection */ /*! @{ */ #define SYSCON_CMP0FCLKSEL_SEL_MASK (0x7U) #define SYSCON_CMP0FCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the CMP0 function clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..FRO_HF clock * 0b011..FRO_12M clock * 0b100..CLKIN clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_CMP0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKSEL_SEL_SHIFT)) & SYSCON_CMP0FCLKSEL_SEL_MASK) /*! @} */ /*! @name CMP0FCLKDIV - CMP0 Function Clock Divider */ /*! @{ */ #define SYSCON_CMP0FCLKDIV_DIV_MASK (0xFU) #define SYSCON_CMP0FCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_CMP0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_DIV_SHIFT)) & SYSCON_CMP0FCLKDIV_DIV_MASK) #define SYSCON_CMP0FCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_CMP0FCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_CMP0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_RESET_SHIFT)) & SYSCON_CMP0FCLKDIV_RESET_MASK) #define SYSCON_CMP0FCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_CMP0FCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_CMP0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_HALT_SHIFT)) & SYSCON_CMP0FCLKDIV_HALT_MASK) #define SYSCON_CMP0FCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_CMP0FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0FCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CMP0RRCLKSEL - CMP0 Round Robin Clock Selection */ /*! @{ */ #define SYSCON_CMP0RRCLKSEL_SEL_MASK (0x7U) #define SYSCON_CMP0RRCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the CMP0 round robin clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..FRO_HF clock * 0b011..FRO_12M clock * 0b100..CLKIN clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_CMP0RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP0RRCLKSEL_SEL_MASK) /*! @} */ /*! @name CMP0RRCLKDIV - CMP0 Round Robin Clock Divider */ /*! @{ */ #define SYSCON_CMP0RRCLKDIV_DIV_MASK (0xFU) #define SYSCON_CMP0RRCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_CMP0RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP0RRCLKDIV_DIV_MASK) #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_CMP0RRCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_CMP0RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK) #define SYSCON_CMP0RRCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_CMP0RRCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_CMP0RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP0RRCLKDIV_HALT_MASK) #define SYSCON_CMP0RRCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_CMP0RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0RRCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CMP1FCLKSEL - CMP1 Function Clock Selection */ /*! @{ */ #define SYSCON_CMP1FCLKSEL_SEL_MASK (0x7U) #define SYSCON_CMP1FCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the CMP1 function clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..FRO_HF clock * 0b011..FRO_12M clock * 0b100..CLKIN clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_CMP1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKSEL_SEL_SHIFT)) & SYSCON_CMP1FCLKSEL_SEL_MASK) /*! @} */ /*! @name CMP1FCLKDIV - CMP1 Function Clock Divider */ /*! @{ */ #define SYSCON_CMP1FCLKDIV_DIV_MASK (0xFU) #define SYSCON_CMP1FCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_CMP1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_DIV_SHIFT)) & SYSCON_CMP1FCLKDIV_DIV_MASK) #define SYSCON_CMP1FCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_CMP1FCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_CMP1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_RESET_SHIFT)) & SYSCON_CMP1FCLKDIV_RESET_MASK) #define SYSCON_CMP1FCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_CMP1FCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_CMP1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_HALT_SHIFT)) & SYSCON_CMP1FCLKDIV_HALT_MASK) #define SYSCON_CMP1FCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_CMP1FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1FCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CMP1RRCLKSEL - CMP1 Round Robin Clock Source Select */ /*! @{ */ #define SYSCON_CMP1RRCLKSEL_SEL_MASK (0x7U) #define SYSCON_CMP1RRCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the CMP1 round robin clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..FRO_HF clock * 0b011..FRO_12M clock * 0b100..CLKIN clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_CMP1RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP1RRCLKSEL_SEL_MASK) /*! @} */ /*! @name CMP1RRCLKDIV - CMP1 Round Robin Clock Division */ /*! @{ */ #define SYSCON_CMP1RRCLKDIV_DIV_MASK (0xFU) #define SYSCON_CMP1RRCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_CMP1RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP1RRCLKDIV_DIV_MASK) #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_CMP1RRCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_CMP1RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK) #define SYSCON_CMP1RRCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_CMP1RRCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_CMP1RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP1RRCLKDIV_HALT_MASK) #define SYSCON_CMP1RRCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_CMP1RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1RRCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CMP2FCLKSEL - CMP2 Function Clock Source Select */ /*! @{ */ #define SYSCON_CMP2FCLKSEL_SEL_MASK (0x7U) #define SYSCON_CMP2FCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the CMP2 function clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..FRO_HF clock * 0b011..FRO_12M clock * 0b100..CLKIN clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_CMP2FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKSEL_SEL_SHIFT)) & SYSCON_CMP2FCLKSEL_SEL_MASK) /*! @} */ /*! @name CMP2FCLKDIV - CMP2 Function Clock Division */ /*! @{ */ #define SYSCON_CMP2FCLKDIV_DIV_MASK (0xFU) #define SYSCON_CMP2FCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_CMP2FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKDIV_DIV_SHIFT)) & SYSCON_CMP2FCLKDIV_DIV_MASK) #define SYSCON_CMP2FCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_CMP2FCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_CMP2FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKDIV_RESET_SHIFT)) & SYSCON_CMP2FCLKDIV_RESET_MASK) #define SYSCON_CMP2FCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_CMP2FCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_CMP2FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKDIV_HALT_SHIFT)) & SYSCON_CMP2FCLKDIV_HALT_MASK) #define SYSCON_CMP2FCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_CMP2FCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_CMP2FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP2FCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CMP2RRCLKSEL - CMP2 Round Robin Clock Source Select */ /*! @{ */ #define SYSCON_CMP2RRCLKSEL_SEL_MASK (0x7U) #define SYSCON_CMP2RRCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the CMP2 round robin clock * 0b000..No clock * 0b001..PLL0 clock * 0b010..FRO_HF clock * 0b011..FRO_12M clock * 0b100..CLKIN clock * 0b101..PLL1_clk0 clock0 * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_CMP2RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP2RRCLKSEL_SEL_MASK) /*! @} */ /*! @name CMP2RRCLKDIV - CMP2 Round Robin Clock Division */ /*! @{ */ #define SYSCON_CMP2RRCLKDIV_DIV_MASK (0xFU) #define SYSCON_CMP2RRCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_CMP2RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP2RRCLKDIV_DIV_MASK) #define SYSCON_CMP2RRCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_CMP2RRCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_CMP2RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP2RRCLKDIV_RESET_MASK) #define SYSCON_CMP2RRCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_CMP2RRCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_CMP2RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP2RRCLKDIV_HALT_MASK) #define SYSCON_CMP2RRCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_CMP2RRCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_CMP2RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP2RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP2RRCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name CPUCTRL - CPU Control for Multiple Processors */ /*! @{ */ #define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) #define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) /*! CPU1CLKEN - Enables the CPU1 clock * 0b1..The CPU1 clock is enabled * 0b0..The CPU1 clock is not enabled */ #define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) #define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) #define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) /*! CPU1RSTEN - CPU1 reset * 0b1..The CPU1 is reset. * 0b0..The CPU1 is not reset. */ #define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) #define SYSCON_CPUCTRL_PROT_MASK (0xFFFF0000U) #define SYSCON_CPUCTRL_PROT_SHIFT (16U) /*! PROT - Write Protect * 0b1100000011000100..For write operation to have an effect. */ #define SYSCON_CPUCTRL_PROT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_PROT_SHIFT)) & SYSCON_CPUCTRL_PROT_MASK) /*! @} */ /*! @name CPBOOT - Coprocessor Boot Address */ /*! @{ */ #define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFF80U) #define SYSCON_CPBOOT_CPBOOT_SHIFT (7U) /*! CPBOOT - Coprocessor Boot VTOR Address [31:7] for CPU1 */ #define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) /*! @} */ /*! @name CPUSTAT - CPU Status */ /*! @{ */ #define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) #define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) /*! CPU0SLEEPING - CPU0 sleeping state * 0b1..CPU is sleeping * 0b0..CPU is not sleeping */ #define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) #define SYSCON_CPUSTAT_CPU1SLEEPING_MASK (0x2U) #define SYSCON_CPUSTAT_CPU1SLEEPING_SHIFT (1U) /*! CPU1SLEEPING - CPU1 sleeping state * 0b1..CPU is sleeping * 0b0..CPU is not sleeping */ #define SYSCON_CPUSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU1SLEEPING_MASK) #define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) #define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) /*! CPU0LOCKUP - CPU0 lockup state * 0b1..CPU is in lockup * 0b0..CPU is not in lockup */ #define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) #define SYSCON_CPUSTAT_CPU1LOCKUP_MASK (0x8U) #define SYSCON_CPUSTAT_CPU1LOCKUP_SHIFT (3U) /*! CPU1LOCKUP - CPU1 lockup state * 0b1..CPU is in lockup * 0b0..CPU is not in lockup */ #define SYSCON_CPUSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU1LOCKUP_MASK) /*! @} */ /*! @name LPCAC_CTRL - LPCAC Control */ /*! @{ */ #define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) #define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) /*! DIS_LPCAC - Disables/enables the cache function. * 0b0..Enabled * 0b1..Disabled */ #define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) #define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) #define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) /*! CLR_LPCAC - Clears the cache function. * 0b0..Unclears the cache * 0b1..Clears the cache */ #define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) #define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) #define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) /*! FRC_NO_ALLOC - Forces no allocation. * 0b0..Forces allocation * 0b1..Forces no allocation */ #define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) #define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK (0x8U) #define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT (3U) /*! PARITY_MISS_EN - Enables parity miss. * 0b0..Disabled * 0b1..Enables parity, miss on parity error */ #define SYSCON_LPCAC_CTRL_PARITY_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK) #define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK (0x10U) #define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT (4U) /*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer. * 0b1..Disables write through buffer * 0b0..Enables write through buffer */ #define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK) #define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK (0x20U) #define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT (5U) /*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer. * 0b1..Write buffer enabled when transaction is cacheable and bufferable * 0b0..Write buffer enabled when transaction is bufferable. */ #define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK) #define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK (0x40U) #define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT (6U) /*! PARITY_FAULT_EN - Enable parity error report. * 0b1..Enables parity error report * 0b0..Disables parity error report */ #define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK) #define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK (0x80U) #define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT (7U) /*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control * 0b1..Enabled. * 0b0..Disabled. */ #define SYSCON_LPCAC_CTRL_LPCAC_XOM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK) /*! @} */ /*! @name FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV - LP_FLEXCOMM Clock Divider */ /*! @{ */ #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK (0xFFU) #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK) #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK) #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK) #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK) /*! @} */ /* The count of SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV */ #define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_COUNT (10U) /*! @name UTICKCLKSEL - UTICK Function Clock Source Select */ /*! @{ */ #define SYSCON_UTICKCLKSEL_SEL_MASK (0x3U) #define SYSCON_UTICKCLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the clock source * 0b00..clk_in * 0b01..xtal32k[2] * 0b10..clk_1m clock * 0b11..No clock */ #define SYSCON_UTICKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKSEL_SEL_SHIFT)) & SYSCON_UTICKCLKSEL_SEL_MASK) /*! @} */ /*! @name SAI0CLKSEL - SAI0 Function Clock Source Select */ /*! @{ */ #define SYSCON_SAI0CLKSEL_SEL_MASK (0x7U) #define SYSCON_SAI0CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the clock source * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..PLL1_CLK0 clock * 0b101..No clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_SAI0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKSEL_SEL_SHIFT)) & SYSCON_SAI0CLKSEL_SEL_MASK) /*! @} */ /*! @name SAI1CLKSEL - SAI1 Function Clock Source Select */ /*! @{ */ #define SYSCON_SAI1CLKSEL_SEL_MASK (0x7U) #define SYSCON_SAI1CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the clock source * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..PLL1_CLK0 clock * 0b101..No clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_SAI1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKSEL_SEL_SHIFT)) & SYSCON_SAI1CLKSEL_SEL_MASK) /*! @} */ /*! @name SAI0CLKDIV - SAI0 Function Clock Division */ /*! @{ */ #define SYSCON_SAI0CLKDIV_DIV_MASK (0x7U) #define SYSCON_SAI0CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_SAI0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_DIV_SHIFT)) & SYSCON_SAI0CLKDIV_DIV_MASK) #define SYSCON_SAI0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SAI0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_SAI0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_RESET_SHIFT)) & SYSCON_SAI0CLKDIV_RESET_MASK) #define SYSCON_SAI0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SAI0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_SAI0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_HALT_SHIFT)) & SYSCON_SAI0CLKDIV_HALT_MASK) #define SYSCON_SAI0CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_SAI0CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_SAI0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI0CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name SAI1CLKDIV - SAI1 Function Clock Division */ /*! @{ */ #define SYSCON_SAI1CLKDIV_DIV_MASK (0x7U) #define SYSCON_SAI1CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_SAI1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_DIV_SHIFT)) & SYSCON_SAI1CLKDIV_DIV_MASK) #define SYSCON_SAI1CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SAI1CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_SAI1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_RESET_SHIFT)) & SYSCON_SAI1CLKDIV_RESET_MASK) #define SYSCON_SAI1CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SAI1CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_SAI1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_HALT_SHIFT)) & SYSCON_SAI1CLKDIV_HALT_MASK) #define SYSCON_SAI1CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_SAI1CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_SAI1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI1CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name EMVSIM0CLKSEL - EMVSIM0 Clock Source Select */ /*! @{ */ #define SYSCON_EMVSIM0CLKSEL_SEL_MASK (0x7U) #define SYSCON_EMVSIM0CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the EMVSIM0 function clock source * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..FRO_12M clock * 0b101..PLL1_clk0 clock0 * 0b110..No clock * 0b111..No clock */ #define SYSCON_EMVSIM0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKSEL_SEL_SHIFT)) & SYSCON_EMVSIM0CLKSEL_SEL_MASK) /*! @} */ /*! @name EMVSIM1CLKSEL - EMVSIM1 Clock Source Select */ /*! @{ */ #define SYSCON_EMVSIM1CLKSEL_SEL_MASK (0x7U) #define SYSCON_EMVSIM1CLKSEL_SEL_SHIFT (0U) /*! SEL - Selects the EMVSIM1 function clock source * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..FRO_12M clock * 0b101..PLL1_clk0 clock0 * 0b110..No clock * 0b111..No clock */ #define SYSCON_EMVSIM1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKSEL_SEL_SHIFT)) & SYSCON_EMVSIM1CLKSEL_SEL_MASK) /*! @} */ /*! @name EMVSIM0CLKDIV - EMVSIM0 Function Clock Division */ /*! @{ */ #define SYSCON_EMVSIM0CLKDIV_DIV_MASK (0x7U) #define SYSCON_EMVSIM0CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_EMVSIM0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM0CLKDIV_DIV_MASK) #define SYSCON_EMVSIM0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_EMVSIM0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_EMVSIM0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKDIV_RESET_SHIFT)) & SYSCON_EMVSIM0CLKDIV_RESET_MASK) #define SYSCON_EMVSIM0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_EMVSIM0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_EMVSIM0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKDIV_HALT_SHIFT)) & SYSCON_EMVSIM0CLKDIV_HALT_MASK) #define SYSCON_EMVSIM0CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_EMVSIM0CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_EMVSIM0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM0CLKDIV_UNSTAB_SHIFT)) & SYSCON_EMVSIM0CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name EMVSIM1CLKDIV - EMVSIM1 Function Clock Division */ /*! @{ */ #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) #define SYSCON_EMVSIM1CLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_EMVSIM1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK) #define SYSCON_EMVSIM1CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_EMVSIM1CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_EMVSIM1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_RESET_SHIFT)) & SYSCON_EMVSIM1CLKDIV_RESET_MASK) #define SYSCON_EMVSIM1CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_EMVSIM1CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_EMVSIM1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_HALT_SHIFT)) & SYSCON_EMVSIM1CLKDIV_HALT_MASK) #define SYSCON_EMVSIM1CLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_EMVSIM1CLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_EMVSIM1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_UNSTAB_SHIFT)) & SYSCON_EMVSIM1CLKDIV_UNSTAB_MASK) /*! @} */ /*! @name KEY_RETAIN_CTRL - Key Retain Control */ /*! @{ */ #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK (0x1U) #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT (0U) /*! KEY_RETAIN_VALID - Indicates if the PUF key has been retained in the VBAT domain and has not * been reset or otherwise invalidated by software. * 0b0..PUF key is not retained in VBAT domain. * 0b1..PUF key is retained in VBAT domain. */ #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK) #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK (0x2U) #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT (1U) /*! KEY_RETAIN_DONE - Indicates the successful completion of the key_save or key_load routine. Once * set, to clear the key_retain_done flag, both key_save and key_load should be cleared by * software. * 0b0..Key save / load sequence has not completed. * 0b1..Key save / load sequence has completed. */ #define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK) #define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK (0x10000U) #define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT (16U) /*! KEY_SAVE * 0b0..Key save sequence is disabled. * 0b1..Key save sequence is enabled. */ #define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK) #define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK (0x20000U) #define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT (17U) /*! KEY_LOAD * 0b0..Key load sequence is disabled. * 0b1..Key load sequence is enabled. */ #define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK) /*! @} */ /*! @name REF_CLK_CTRL - FRO 48MHz Reference Clock Control */ /*! @{ */ #define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK (0x1U) #define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT (0U) /*! GDET_REFCLK_EN - GDET reference clock enable bit * 0b1..Enabled * 0b0..Disabled. */ #define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK) #define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK (0x2U) #define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT (1U) /*! TRNG_REFCLK_EN - ELS TRNG reference clock enable bit * 0b1..Enabled * 0b0..Disabled. */ #define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK) /*! @} */ /*! @name REF_CLK_CTRL_SET - FRO 48MHz Reference Clock Control Set */ /*! @{ */ #define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK (0x1U) #define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT (0U) /*! GDET_REFCLK_EN_SET - GDET reference clock enable set bit * 0b1..Set to 1 * 0b0..No effect. */ #define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK) #define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK (0x2U) #define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT (1U) /*! TRNG_REFCLK_EN_SET - ELS TRNG reference clock enable set bit * 0b1..Set to 1 * 0b0..No effect. */ #define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK) /*! @} */ /*! @name REF_CLK_CTRL_CLR - FRO 48MHz Reference Clock Control Clear */ /*! @{ */ #define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK (0x1U) #define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT (0U) /*! GDET_REFCLK_EN_CLR - GDET reference clock enable clear bit * 0b1..Set to 0 * 0b0..No effect. */ #define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK) #define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK (0x2U) #define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT (1U) /*! TRNG_REFCLK_EN_CLR - ELS TRNG reference clock enable clear bit * 0b1..Set to 0 * 0b0..No effect. */ #define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK) /*! @} */ /*! @name GDETX_CTRL_GDET_CTRL - GDET Control Register */ /*! @{ */ #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK (0x1U) #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT (0U) /*! GDET_EVTCNT_CLR - Controls the GDET clean event counter * 0b1..Clears event counter * 0b0..Event counter not cleared */ #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK) #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK (0x2U) #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT (1U) /*! GDET_ERR_CLR - Clears GDET error status * 0b1..Clears error status * 0b0..Error status not cleared */ #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK) #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK (0xCU) #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT (2U) /*! GDET_ISO_SW - GDET isolation control * 0b10..Isolation is enabled. When both GDET0_CTRL/GDET1_CTRL GDET_ISO_SW are "10", isolation_on is asserted. * 0b00..Isolation is disabled * 0b01..Isolation is disabled * 0b11..Isolation is disabled */ #define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK) #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK (0xFF00U) #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT (8U) /*! EVENT_CNT - Event count value */ #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK) #define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK (0x10000U) #define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT (16U) /*! POS_SYNC - Positive glitch detected * 0b1..Positive glitch detected * 0b0..Positive glitch not detected */ #define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK) #define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK (0x20000U) #define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT (17U) /*! NEG_SYNC - Negative glitch detected * 0b1..Negative glitch detected * 0b0..Negative glitch not detected */ #define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK) #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK (0x40000U) #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT (18U) /*! EVENT_CLR_FLAG - Event counter cleared * 0b1..Event counter cleared * 0b0..Event counter not cleared */ #define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK) /*! @} */ /* The count of SYSCON_GDETX_CTRL_GDET_CTRL */ #define SYSCON_GDETX_CTRL_GDET_CTRL_COUNT (2U) /*! @name ELS_ASSET_PROT - ELS Asset Protection Register */ /*! @{ */ #define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK (0x3U) #define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT (0U) /*! ASSET_PROTECTION - ELS asset protection. This field controls the asset protection port to the * ELS module. Refer to the ELS chapter in the SRM for more details. * 0b00..ELS asset is protected * 0b10..ELS asset is protected * 0b11..ELS asset is protected * 0b01..ELS asset is not protected */ #define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT)) & SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK) /*! @} */ /*! @name ELS_LOCK_CTRL - ELS Lock Control */ /*! @{ */ #define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK (0x3U) #define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT (0U) /*! LOCK_CTRL - ELS Lock Control */ #define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT)) & SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK) /*! @} */ /*! @name ELS_LOCK_CTRL_DP - ELS Lock Control DP */ /*! @{ */ #define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK (0x3U) #define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT (0U) /*! LOCK_CTRL_DP - Refer to ELS_LOCK_CTRL[1:0] */ #define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT)) & SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK) /*! @} */ /*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ /*! @{ */ #define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU) #define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U) /*! OTP_LC_STATE - OTP life cycle state */ #define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK) /*! @} */ /*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */ /*! @{ */ #define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU) #define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U) /*! OTP_LC_STATE_DP - OTP life cycle state */ #define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK) /*! @} */ /*! @name ELS_TEMPORAL_STATE - ELS Temporal State */ /*! @{ */ #define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU) #define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U) /*! TEMPORAL_STATE - Temporal state */ #define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK) /*! @} */ /*! @name ELS_KDF_MASK - Key Derivation Function Mask */ /*! @{ */ #define SYSCON_ELS_KDF_MASK_KDF_MASK_MASK (0xFFFFFFFFU) #define SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT (0U) /*! KDF_MASK - Key derivation function mask */ #define SYSCON_ELS_KDF_MASK_KDF_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON_ELS_KDF_MASK_KDF_MASK_MASK) /*! @} */ /*! @name ELS_AS_CFG0 - ELS AS Configuration */ /*! @{ */ #define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK (0xFFU) #define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT (0U) /*! CFG_LC_STATE - LC state configuration bit */ #define SYSCON_ELS_AS_CFG0_CFG_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK) #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK (0x200U) #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT (9U) /*! CFG_LVD_CORE_RESET_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD reset are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK (0x800U) #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT (11U) /*! CFG_LVD_CORE_IRQ_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD IRQ are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK (0x1000U) #define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT (12U) /*! CFG_WDT0_ENABLED - When WatchDog Timer 0 is activated, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK (0x2000U) #define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT (13U) /*! CFG_CWDT0_ENABLED - When Code WatchDog Timer 0 is activated, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK (0x4000U) #define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT (14U) /*! CFG_ELS_GDET_ENABLED - When either GDET is enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK (0x8000U) #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT (15U) /*! CFG_ANA_GDET_RESET_ENABLED - When SPC analog glitch detect reset is enabled, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK (0x10000U) #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT (16U) /*! CFG_ANA_GDET_IRQ_ENABLED - When SPC analog glitch detect IRQ is enabled, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK (0x20000U) #define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT (17U) /*! CFG_TAMPER_DET_ENABLED - When tamper detector is enabled in TDET, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK (0x40000U) #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT (18U) /*! CFG_LVD_VSYS_RESET_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD reset are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK (0x80000U) #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT (19U) /*! CFG_LVD_VDDIO_RESET_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD reset are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK (0x100000U) #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT (20U) /*! CFG_LVD_VSYS_IRQ_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD irq are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK (0x200000U) #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT (21U) /*! CFG_LVD_VDDIO_IRQ_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD irq are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK (0x400000U) #define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT (22U) /*! CFG_WDT1_ENABLED - When WatchDog Timer 1 is activated, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK (0x800000U) #define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT (23U) /*! CFG_CWDT1_ENABLED - When Code WatchDog Timer 1 is activated, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK (0x1000000U) #define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT (24U) /*! CFG_TEMPTAMPER_DET_ENABLED - When temperature tamper detector is enabled in VBAT, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK (0x2000000U) #define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT (25U) /*! CFG_VOLTAMPER_DET_ENABLED - When voltage tamper detector is enabled in VBAT, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK (0x4000000U) #define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT (26U) /*! CFG_LHTTAMPER_DET_ENABLED - When light tamper detector is enabled in VBAT, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK (0x8000000U) #define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT (27U) /*! CFG_CLKTAMPER_DET_ENABLED - When clk tamper detector is enabled in VBAT, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK (0x10000000U) #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT (28U) /*! CFG_QK_DISABLE_ENROLL - When QK PUF "qk_disable_enroll" input is driven 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK) #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK (0x20000000U) #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT (29U) /*! CFG_QK_DISABLE_WRAP - When QK PUF "qk_disable_wrap" input is driven 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK) /*! @} */ /*! @name ELS_AS_CFG1 - ELS AS Configuration1 */ /*! @{ */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK (0x2U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT (1U) /*! CFG_SEC_DIS_STRICT_MODE - When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE * bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this * bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK (0x4U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT (2U) /*! CFG_SEC_DIS_VIOL_ABORT - When the DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and * MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK (0x8U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT (3U) /*! CFG_SEC_ENA_NS_PRIV_CHK - When the ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and * MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK (0x10U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT (4U) /*! CFG_SEC_ENA_S_PRIV_CHK - When the ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG * on the AHB secure controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK (0x20U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT (5U) /*! CFG_SEC_ENA_SEC_CHK - When the ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG * on the AHB secure controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK (0x40U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT (6U) /*! CFG_SEC_IDAU_ALLNS - When the IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB * secure controller are equal to 01, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK (0x100U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT (8U) /*! CFG_SEC_LOCK_NS_MPU - When the LOCK_NS_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK (0x200U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT (9U) /*! CFG_SEC_LOCK_NS_VTOR - When the LOCK_NS_VTOR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK (0x400U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT (10U) /*! CFG_SEC_LOCK_S_MPU - When the LOCK_S_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK (0x800U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT (11U) /*! CFG_SEC_LOCK_S_VTAIRCR - When the LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on the AHB secure * controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK (0x1000U) #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT (12U) /*! CFG_SEC_LOCK_SAU - When the LOCK_SAU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ #define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK) #define SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK (0x1FE000U) #define SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT (13U) /*! METAL_VERSION - metal version */ #define SYSCON_ELS_AS_CFG1_METAL_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK) #define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK (0x1E00000U) #define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT (21U) /*! ROM_PATCH_VERSION - ROM patch version */ #define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK) #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK (0x4000000U) #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT (26U) /*! CFG_HVD_CORE_RESET_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD reset are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK (0x8000000U) #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT (27U) /*! CFG_HVD_CORE_IRQ_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD IRQ are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK) #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK (0x10000000U) #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT (28U) /*! CFG_HVD_VSYS_RESET_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD reset are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK (0x20000000U) #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT (29U) /*! CFG_HVD_VDDIO_RESET_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD reset are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK) #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK (0x40000000U) #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT (30U) /*! CFG_HVD_VSYS_IRQ_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD irq are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK) #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK (0x80000000U) #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT (31U) /*! CFG_HVD_VDDIO_IRQ_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD irq are enabled, this bit indicates state 1. */ #define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK) /*! @} */ /*! @name ELS_AS_CFG2 - ELS AS Configuration2 */ /*! @{ */ #define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK (0xFFFFFFFFU) #define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT (0U) /*! CFG_ELS_CMD_EN - ELS configuration command enable bit */ #define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT)) & SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK) /*! @} */ /*! @name ELS_AS_CFG3 - ELS AS Configuration3 */ /*! @{ */ #define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK (0xFFFFFFFFU) #define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT (0U) /*! DEVICE_TYPE - Device type identification data */ #define SYSCON_ELS_AS_CFG3_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT)) & SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK) /*! @} */ /*! @name ELS_AS_ST0 - ELS AS State Register */ /*! @{ */ #define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU) #define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U) /*! ST_TEMPORAL_STATE - TEMPORAL_STATE[3:0] in the ELS_TEMPORAL_STATE register reflects this register */ #define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK) #define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK (0x10U) #define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT (4U) /*! ST_CPU0_DBGEN - When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK) #define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK (0x20U) #define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT (5U) /*! ST_CPU0_NIDEN - When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK) #define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK (0x40U) #define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT (6U) /*! ST_CPU0_SPIDEN - When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK) #define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK (0x80U) #define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT (7U) /*! ST_CPU0_SPNIDEN - When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK) #define SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN_MASK (0x100U) #define SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN_SHIFT (8U) /*! ST_CPU1_DBGEN - When CPU1 (CM33) "deben" input is state 1, this bit indicates state 1. */ #define SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU1_DBGEN_MASK) #define SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN_MASK (0x200U) #define SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN_SHIFT (9U) /*! ST_CPU1_NIDEN - When CPU1 (CM33) "niden" input is state 1, this bit indicates state 1. */ #define SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU1_NIDEN_MASK) #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK (0x400U) #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT (10U) /*! ST_DAP_ENABLE_CPU0 - When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK) #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1_MASK (0x800U) #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1_SHIFT (11U) /*! ST_DAP_ENABLE_CPU1 - When DAP to AP1 for CPU1 (CM33) debug access is allowed, this bit indicates state 1. */ #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU1_MASK) #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP_MASK (0x1000U) #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP_SHIFT (12U) /*! ST_DAP_ENABLE_DSP - When DAP to AP3 for DSP (CoolFlux) debug access is allowed, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_DSP_MASK) #define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK (0x4000U) #define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT (14U) /*! ST_ALLOW_TEST_ACCESS - When JTAG TAP access is allowed, this bit indicates state 1. */ #define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT)) & SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK) #define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK (0x8000U) #define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT (15U) /*! ST_XO32K_FAILED - When XO32K oscillation fail flag is state 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK) #define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK (0x10000U) #define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT (16U) /*! ST_XO40M_FAILED - When XO40M oscillation fail flag is state 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK) #define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK (0x20000U) #define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT (17U) /*! ST_IFR_LOAD_FAILED - When IFR load fail flag is state 1, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK) #define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK (0x3C0000U) #define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT (18U) /*! ST_GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG is state of 4-bit Glitch Ripple Counter output. */ #define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT)) & SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK) /*! @} */ /*! @name ELS_AS_ST1 - ELS AS State1 */ /*! @{ */ #define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK (0xFU) #define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT (0U) /*! ST_QK_PUF_SCORE - These register bits indicate the state of "qk_puf_score[3:0]" outputs from QK PUF block */ #define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK) #define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK (0x10U) #define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT (4U) /*! ST_QK_ZEROIZED - This register bit indicates the state of "qk_zeroized" output from QK PUF block */ #define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK) #define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U) #define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U) /*! ST_MAIN_CLK_IS_EXT - When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1 */ #define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK) #define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK (0xC0U) #define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT (6U) /*! ST_DCDC_VOUT - VOUT[1:0] setting on DCDC0 register in SPC block will reflect to this register. Default is 1.0V */ #define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK) #define SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK (0x300U) #define SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT (8U) /*! ST_DCDC_DS - DCDC drive strength setting. Default is normal drive. */ #define SYSCON_ELS_AS_ST1_ST_DCDC_DS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK) #define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK (0xC00U) #define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT (10U) /*! ST_BOOT_MODE - ISP pin status during boot. By default ISP pin is pulled up. If want to enter ISP * mode during boot, ISP pin should be pull down when out of reset. */ #define SYSCON_ELS_AS_ST1_ST_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK) #define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK (0xF000U) #define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT (12U) /*! ST_BOOT_RETRY_CNT - BOOT_RETRY_CNT[3:0] in the ELS_BOOT_RETRY_CNT register reflects this register */ #define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK) #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK (0x30000U) #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT (16U) /*! ST_LDO_CORE_VOUT - VOUT[1:0] setting on LDO Core register in SPC block will reflect to this register. Default is 1.0V */ #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK) #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK (0xC0000U) #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT (18U) /*! ST_LDO_CORE_DS - LDO_CORE drive strength setting. Default is normal drive. */ #define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK) /*! @} */ /*! @name ELS_AS_BOOT_LOG0 - Boot state captured during boot: Main ROM log */ /*! @{ */ #define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK (0xFU) #define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT (0U) /*! BOOT_IMAGE - Boot image source used during this boot. * 0b0000..Internal flash image 0 * 0b0001..Internal flash image 1 * 0b0010..FlexSPI flash image 0 * 0b0011..FlexSPI flash image 1 * 0b0100..Recovery SPI flash image * 0b0101..Serial boot image (write-memory and execute ISP command used) * 0b0110..Receive SB3 containing SB_JUMP command is used. * 0b0111..Customer SBL/recovery image (Bank1 IFR0). * 0b1000..NXP MAD recovery image (Bank1 IFR0). * 0b1001..NXP ROM extension (NMPA - Bank0 IFR0). * 0b1010..Reserved. * 0b1011..Reserved. * 0b1100..Reserved. * 0b1101..Reserved. * 0b1110..Reserved. * 0b1111..Reserved. */ #define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK (0x10U) #define SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT (4U) /*! CMAC - CMAC verify is used instead of ECDSA verify on this boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK (0x40U) #define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT (6U) /*! ECDSA - ECDSA P-384 verification is done on this boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_ECDSA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK (0x80U) #define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT (7U) /*! OFF_CHIP - Off-chip Prince is enabled during boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK (0x100U) #define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT (8U) /*! ON_CHIP - On-chip Prince is enabled during boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK (0x200U) #define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT (9U) /*! CDI_CSR - CDI based device keys are derived for CSR harvesting on this boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK (0x400U) #define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT (10U) /*! CDI_DICE - CDI per DICE specification is computed on this boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK (0x800U) #define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT (11U) /*! TRUSTZONE - TrustZone preset data is loaded during this boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK (0x1000U) #define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT (12U) /*! DEBUG_AUTH - Debug authentication done in this session prior to boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK (0x2000U) #define SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT (13U) /*! ITRC - ITRC zeroize event is handled in this session of boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK (0x4000U) #define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT (14U) /*! DIG_GDET - Digital glitch detector is enabled during boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK (0x8000U) #define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT (15U) /*! ANA_GDET - Analog glitch detector is enabled during boot. */ #define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK (0x10000U) #define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT (16U) /*! DEEP_PD - Boot from deep-power down state. */ #define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK (0xF000000U) #define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT (24U) /*! LOW_POWER - Last low-power mode value. ROM copies SPC_LP_MODE field from SPC->SC[7:4]. */ #define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK) #define SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK (0x80000000U) #define SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT (31U) /*! ISP - ISP pin state at boot time. ROM copies CMC->MR0[0]. */ #define SYSCON_ELS_AS_BOOT_LOG0_ISP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK) /*! @} */ /*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: Library log */ /*! @{ */ #define SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK (0x3U) #define SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT (0U) /*! RoTK - RoTK index used for this boot. */ #define SYSCON_ELS_AS_BOOT_LOG1_RoTK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK) #define SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK (0x3FCU) #define SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT (2U) /*! FIPS - FIPS self-test is executed and PASS during this boot. When a bit is set, means self-test * is executed and it FAILS. When a bit is clear, means corresponding self-test is executed and * PASS or it is not executed. */ #define SYSCON_ELS_AS_BOOT_LOG1_FIPS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK) #define SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK (0xC00U) #define SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT (10U) /*! SB3 - SB3 type (valid after nboot_sb3_load_manifest()). * 0b00..customer fw load/update file. * 0b01..NXP Provisioning FW. * 0b10..ELS signed OEM Provisioning FW. */ #define SYSCON_ELS_AS_BOOT_LOG1_SB3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK) /*! @} */ /*! @name ELS_AS_BOOT_LOG2 - Boot state captured during boot: Hardware status signals log */ /*! @{ */ #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK (0x3FU) #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT (0U) /*! CMC_SRS0 - CMC->SRS[5:0] */ #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK) #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK (0xC0U) #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT (6U) /*! VBAT_STATUS0 - VBAT->STATUSA[1:0] | ~VBAT->STATUSB[1:0] */ #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK) #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK (0x1FF00U) #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT (8U) /*! CMC_SRS1 - CMC->SRS[16:8] */ #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK) #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK (0xFC0000U) #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT (18U) /*! VBAT_STATUS1 - VBAT->STATUSA[11:6] | ~VBAT->STATUSB[11:6] */ #define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK) #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK (0xFF000000U) #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT (24U) /*! CMC_SRS2 - CMC->SRS[31:24] */ #define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK) /*! @} */ /*! @name ELS_AS_BOOT_LOG3 - Boot state captured during boot: Security log */ /*! @{ */ #define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK (0xFFU) #define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT (0U) /*! ERR_AUTH_FAIL_COUNT - CFPA->ERR_AUTH_FAIL_COUNT[7:0] */ #define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK) #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK (0xFF00U) #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT (8U) /*! ERR_ITRC_COUNT - CFPA->ERR_ITRC_COUNT[7:0] */ #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK) /*! @} */ /*! @name ELS_AS_FLAG0 - ELS AS Flag0 */ /*! @{ */ #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U) #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U) /*! FLAG_AP_ENABLE_CPU0 - This flag bit is set as 1 when DAP enables AP0 for CPU0 (CM33) debug * access. The register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_MASK (0x2U) #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_SHIFT (1U) /*! FLAG_AP_ENABLE_CPU1 - This flag bit is set as 1 when DAP enables AP1 for CPU1 (CM33) debug * access. The register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU1_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP_MASK (0x4U) #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP_SHIFT (2U) /*! FLAG_AP_ENABLE_DSP - This flag bit is set as 1 when DAP enables AP3 for DSP (CoolFlux) debug * access. The register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_DSP_MASK) #define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK (0x8U) #define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT (3U) /*! EFUSE_ATTACK_DETECT - OTPC can output attack_detect signal when it detects attack when load * shadow registers. The output will be cleared by reset. ELS_AS_FLAG is reset by PoR, so the status * can be recorded. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT)) & SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK (0x20U) #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT (5U) /*! FLAG_LVD_CORE_OCCURED - This flag register is set 1 when VDD_CORE LVD event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK (0x100U) #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT (8U) /*! FLAG_WDT0_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 reset is enabled and * reset event is triggered. This register is cleared 0 by AO domain POR. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK (0x200U) #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT (9U) /*! FLAG_CWDT0_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 reset is enabled * and reset event is triggered. This register is cleared 0 by AO domain POR. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK (0x400U) #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT (10U) /*! FLAG_WDT0_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 IRQ is enabled and IRQ * event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK (0x800U) #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT (11U) /*! FLAG_CWDT0_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 IRQ is enabled and * IRQ event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK (0x1000U) #define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT (12U) /*! FLAG_QK_ERROR - This flag bit is set as 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK (0x2000U) #define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT (13U) /*! FLAG_ELS_GLITCH_DETECTED - This flag bit is set as 1 when GDET error is flagged. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK (0x4000U) #define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT (14U) /*! FLAG_ANA_GLITCH_DETECTED - This flag bit is set as 1 when ANALOG GDET error is flagged in SYSCON * block. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK (0x8000U) #define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT (15U) /*! FLAG_TAMPER_EVENT_DETECTED - This flag bit is set as 1 when tamper event is flagged from TDET. * This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is * cleared by software. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK (0x10000U) #define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT (16U) /*! FLAG_FLASH_ECC_INVALID - This flag bit is set as 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK (0x20000U) #define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT (17U) /*! FLAG_SEC_VIOL_IRQ_OCURRED - This flag bit is set as 1 when security violation is indicated from FLASH sub-system or AHB bus matrix. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x40000U) #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (18U) /*! FLAG_CPU0_NS_C_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure code * transactions. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x80000U) #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (19U) /*! FLAG_CPU0_NS_D_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure data * transactions. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK (0x100000U) #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT (20U) /*! FLAG_LVD_VSYS_OCCURED - This flag register is set 1 when VDD_SYS LVD event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK (0x200000U) #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT (21U) /*! FLAG_LVD_VDDIO_OCCURED - This flag register is set 1 when VDD LVD event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK (0x400000U) #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT (22U) /*! FLAG_WDT1_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 reset is enabled and * reset event is triggered. This register is cleared 0 by AO domain POR. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK (0x800000U) #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT (23U) /*! FLAG_CWDT1_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 reset is enabled * and reset event is triggered. This register is cleared 0 by AO domain POR. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK (0x1000000U) #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT (24U) /*! FLAG_WDT1_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 IRQ is enabled and IRQ * event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK (0x2000000U) #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT (25U) /*! FLAG_CWDT1_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 IRQ is enabled and * IRQ event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK (0x4000000U) #define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT (26U) /*! FLAG_TEMPTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when temperature temper IRQ is * enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK (0x8000000U) #define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT (27U) /*! FLAG_VOLTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when voltage temper IRQ is enabled * and IRQ event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK (0x10000000U) #define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT (28U) /*! FLAG_LHTTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when light temper IRQ is enabled and * IRQ event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK (0x20000000U) #define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT (29U) /*! FLAG_CLKTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when clock temper IRQ is enabled and * IRQ event is triggered. This register is cleared 0 by PMC reset event. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK) /*! @} */ /*! @name ELS_AS_FLAG1 - ELS AS Flag1 */ /*! @{ */ #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK (0x20000000U) #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT (29U) /*! FLAG_HVD_CORE_OCCURED - This flag bit is set as 1 when HVD from VDD_CORE power domain is triggered. * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK (0x40000000U) #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT (30U) /*! FLAG_HVD_VSYS_OCCURED - This flag bit is set as 1 when HVD from VDD_SYS power domain is triggered * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK) #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK (0x80000000U) #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT (31U) /*! FLAG_HVD_VDDIO_OCCURED - This flag bit is set as 1 when HVD from VDD power domain is triggered * 0b1..Triggered * 0b0..Not Triggered */ #define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK) /*! @} */ /*! @name CLOCK_CTRL - Clock Control */ /*! @{ */ #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK (0x2U) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT (1U) /*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTMR0/1 modules. * 0b1..Clock is enabled * 0b0..Clock is not enabled */ #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK) #define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK (0x4U) #define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT (2U) /*! FRO1MHZ_ENA - Enables the FRO_1MHz clock for RTC module and for UTICK * 0b1..Clock is enabled * 0b0..Clock is not enabled */ #define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK) #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK (0x8U) #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT (3U) /*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTMR0/1, and Frequency Measurement modules * 0b1..Clock is enabled * 0b0..Clock is not enabled */ #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK) #define SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK (0x10U) #define SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT (4U) /*! FRO_HF_ENA - Enables FRO HF clock for the Frequency Measure module * 0b1..Clock is enabled * 0b0..Clock is not enabled */ #define SYSCON_CLOCK_CTRL_FRO_HF_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) /*! CLKIN_ENA - Enables clk_in clock for MICFIL, CAN0/1, I3C0/1, SAI0/1, clkout. * 0b1..Clock is enabled * 0b0..Clock is not enabled */ #define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) /*! FRO1MHZ_CLK_ENA - Enables FRO_1MHz clock for clock muxing in clock gen * 0b1..Clock is enabled * 0b0..Clock is not enabled */ #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) /*! PLU_DEGLITCH_CLK_ENA - Enables clocks FRO_1MHz and FRO_12MHz for PLU deglitching. * 0b1..Clock is enabled * 0b0..Clock is not enabled */ #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) /*! @} */ /*! @name I3C1FCLKSEL - I3C1 Functional Clock Selection */ /*! @{ */ #define SYSCON_I3C1FCLKSEL_SEL_MASK (0x7U) #define SYSCON_I3C1FCLKSEL_SEL_SHIFT (0U) /*! SEL - I3C1 clock select * 0b000..No clock * 0b001..PLL0 clock * 0b010..CLKIN clock * 0b011..FRO_HF clock * 0b100..No clock * 0b101..PLL1_clk0 clock * 0b110..USB PLL clock * 0b111..No clock */ #define SYSCON_I3C1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSEL_SEL_MASK) /*! @} */ /*! @name I3C1FCLKSTCSEL - Selects the I3C1 Time Control clock */ /*! @{ */ #define SYSCON_I3C1FCLKSTCSEL_SEL_MASK (0x7U) #define SYSCON_I3C1FCLKSTCSEL_SEL_SHIFT (0U) /*! SEL - I3C1 FCLK_STC clock select * 0b000..I3C1 functional clock I3C1FCLK * 0b001..FRO_1M clock * 0b010..No clock * 0b011..No clock * 0b100..No clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_I3C1FCLKSTCSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSTCSEL_SEL_MASK) /*! @} */ /*! @name I3C1FCLKSTCDIV - I3C1 FCLK_STC Clock Divider */ /*! @{ */ #define SYSCON_I3C1FCLKSTCDIV_DIV_MASK (0xFFU) #define SYSCON_I3C1FCLKSTCDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_I3C1FCLKSTCDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKSTCDIV_DIV_MASK) #define SYSCON_I3C1FCLKSTCDIV_RESET_MASK (0x20000000U) #define SYSCON_I3C1FCLKSTCDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_I3C1FCLKSTCDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKSTCDIV_RESET_MASK) #define SYSCON_I3C1FCLKSTCDIV_HALT_MASK (0x40000000U) #define SYSCON_I3C1FCLKSTCDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_I3C1FCLKSTCDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKSTCDIV_HALT_MASK) #define SYSCON_I3C1FCLKSTCDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_I3C1FCLKSTCDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_I3C1FCLKSTCDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSTCDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKSTCDIV_UNSTAB_MASK) /*! @} */ /*! @name I3C1FCLKSDIV - I3C1 FCLK Slow clock Divider */ /*! @{ */ #define SYSCON_I3C1FCLKSDIV_DIV_MASK (0xFFU) #define SYSCON_I3C1FCLKSDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_I3C1FCLKSDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKSDIV_DIV_MASK) #define SYSCON_I3C1FCLKSDIV_RESET_MASK (0x20000000U) #define SYSCON_I3C1FCLKSDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_I3C1FCLKSDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKSDIV_RESET_MASK) #define SYSCON_I3C1FCLKSDIV_HALT_MASK (0x40000000U) #define SYSCON_I3C1FCLKSDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_I3C1FCLKSDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKSDIV_HALT_MASK) #define SYSCON_I3C1FCLKSDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_I3C1FCLKSDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_I3C1FCLKSDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKSDIV_UNSTAB_MASK) /*! @} */ /*! @name I3C1FCLKDIV - I3C1 Functional Clock FCLK Divider */ /*! @{ */ #define SYSCON_I3C1FCLKDIV_DIV_MASK (0xFFU) #define SYSCON_I3C1FCLKDIV_DIV_SHIFT (0U) /*! DIV - Clock divider value */ #define SYSCON_I3C1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKDIV_DIV_MASK) #define SYSCON_I3C1FCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_I3C1FCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter * 0b1..Divider is reset * 0b0..Divider is not reset */ #define SYSCON_I3C1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKDIV_RESET_MASK) #define SYSCON_I3C1FCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_I3C1FCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter * 0b1..Divider clock is stopped * 0b0..Divider clock is running */ #define SYSCON_I3C1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKDIV_HALT_MASK) #define SYSCON_I3C1FCLKDIV_UNSTAB_MASK (0x80000000U) #define SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT (31U) /*! UNSTAB - Divider status flag * 0b1..Clock frequency is not stable * 0b0..Divider clock is stable */ #define SYSCON_I3C1FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKDIV_UNSTAB_MASK) /*! @} */ /*! @name I3C1FCLKSSEL - I3C1 FCLK Slow Selection */ /*! @{ */ #define SYSCON_I3C1FCLKSSEL_SEL_MASK (0x7U) #define SYSCON_I3C1FCLKSSEL_SEL_SHIFT (0U) /*! SEL - I3C1 FCLK Slow Clock Select * 0b000..FRO_1M clock * 0b001..No clock * 0b010..No clock * 0b011..No clock * 0b100..No clock * 0b101..No clock * 0b110..No clock * 0b111..No clock */ #define SYSCON_I3C1FCLKSSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSSEL_SEL_MASK) /*! @} */ /*! @name ETB_STATUS - ETB Counter Status Register */ /*! @{ */ #define SYSCON_ETB_STATUS_IRQ_MASK (0x2U) #define SYSCON_ETB_STATUS_IRQ_SHIFT (1U) /*! IRQ - ETB Interrupt * 0b1..ETB interrupt is asserted when ETB count expires. Write 1 to clear it. * 0b0..ETB interrupt is not asserted */ #define SYSCON_ETB_STATUS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_STATUS_IRQ_SHIFT)) & SYSCON_ETB_STATUS_IRQ_MASK) #define SYSCON_ETB_STATUS_NMI_MASK (0x4U) #define SYSCON_ETB_STATUS_NMI_SHIFT (2U) /*! NMI - ETB NMI * 0b1..ETB NMI is asserted. Write 1 to clear it. * 0b0..ETB NMI is not asserted */ #define SYSCON_ETB_STATUS_NMI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_STATUS_NMI_SHIFT)) & SYSCON_ETB_STATUS_NMI_MASK) #define SYSCON_ETB_STATUS_DBG_HALT_REQ_MASK (0x8U) #define SYSCON_ETB_STATUS_DBG_HALT_REQ_SHIFT (3U) /*! DBG_HALT_REQ - Debug halt request * 0b1..The debug halt request signal is asserted when the ETB count expires * 0b0..The debug halt request signal is not asserted */ #define SYSCON_ETB_STATUS_DBG_HALT_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_STATUS_DBG_HALT_REQ_SHIFT)) & SYSCON_ETB_STATUS_DBG_HALT_REQ_MASK) /*! @} */ /*! @name ETB_COUNTER_CTRL - ETB Counter Control Register */ /*! @{ */ #define SYSCON_ETB_COUNTER_CTRL_CNTEN_MASK (0x1U) #define SYSCON_ETB_COUNTER_CTRL_CNTEN_SHIFT (0U) /*! CNTEN - Enables the ETB counter * 0b1..ETB counter is enabled * 0b0..ETB counter is disabled */ #define SYSCON_ETB_COUNTER_CTRL_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_CTRL_CNTEN_SHIFT)) & SYSCON_ETB_COUNTER_CTRL_CNTEN_MASK) #define SYSCON_ETB_COUNTER_CTRL_RSPT_MASK (0x6U) #define SYSCON_ETB_COUNTER_CTRL_RSPT_SHIFT (1U) /*! RSPT - Response Type * 0b11..Generates a debug halt when the ETB count expires via CPU0 CTICHIN[2] * 0b10..Generates an NMI interrupt when the ETB count expires * 0b01..Generates a normal interrupt when the ETB count expires * 0b00..No response when the ETB count expires */ #define SYSCON_ETB_COUNTER_CTRL_RSPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_CTRL_RSPT_SHIFT)) & SYSCON_ETB_COUNTER_CTRL_RSPT_MASK) #define SYSCON_ETB_COUNTER_CTRL_RLRQ_MASK (0x8U) #define SYSCON_ETB_COUNTER_CTRL_RLRQ_SHIFT (3U) /*! RLRQ - Reload request * 0b1..Clears pending debug halt, NMI, or IRQ interrupt requests * 0b0..No effect */ #define SYSCON_ETB_COUNTER_CTRL_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_CTRL_RLRQ_SHIFT)) & SYSCON_ETB_COUNTER_CTRL_RLRQ_MASK) /*! @} */ /*! @name ETB_COUNTER_RELOAD - ETB Counter Reload Register */ /*! @{ */ #define SYSCON_ETB_COUNTER_RELOAD_RELOAD_MASK (0x7FFU) #define SYSCON_ETB_COUNTER_RELOAD_RELOAD_SHIFT (0U) /*! RELOAD - Byte count reload value */ #define SYSCON_ETB_COUNTER_RELOAD_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_RELOAD_RELOAD_SHIFT)) & SYSCON_ETB_COUNTER_RELOAD_RELOAD_MASK) /*! @} */ /*! @name ETB_COUNTER_VALUE - ETB Counter Value Register */ /*! @{ */ #define SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE_MASK (0x7FFU) #define SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - Byte count counter value */ #define SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE_SHIFT)) & SYSCON_ETB_COUNTER_VALUE_COUNTER_VALUE_MASK) /*! @} */ /*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray code_gray[31:0] */ /*! @{ */ #define SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK (0xFFFFFFFFU) #define SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT (0U) /*! code_gray_31_0 - Gray code [31:0] */ #define SYSCON_GRAY_CODE_LSB_code_gray_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK) /*! @} */ /*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray code_gray[41:32] */ /*! @{ */ #define SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK (0x3FFU) #define SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT (0U) /*! code_gray_41_32 - Gray code [41:32] */ #define SYSCON_GRAY_CODE_MSB_code_gray_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK) /*! @} */ /*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */ /*! @{ */ #define SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK (0xFFFFFFFFU) #define SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT (0U) /*! code_bin_31_0 - Binary code [31:0] */ #define SYSCON_BINARY_CODE_LSB_code_bin_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK) /*! @} */ /*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */ /*! @{ */ #define SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK (0x3FFU) #define SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT (0U) /*! code_bin_41_32 - Binary code [41:32] */ #define SYSCON_BINARY_CODE_MSB_code_bin_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK) /*! @} */ /*! @name AUTOCLKGATEOVERRIDE - Control Automatic Clock Gating */ /*! @{ */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK (0x4U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT (2U) /*! RAMB_CTRL - Controls automatic clock gating for the RAMB Controller * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK (0x8U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT (3U) /*! RAMC_CTRL - Controls automatic clock gating for the RAMC Controller * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK (0x10U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT (4U) /*! RAMD_CTRL - Controls automatic clock gating for the RAMD Controller * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK) #define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK (0x20U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT (5U) /*! RAME_CTRL - Controls automatic clock gating for the RAMD Controller. * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL_MASK (0x40U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL_SHIFT (6U) /*! RAMF_CTRL - Controls automatic clock gating for the RAMF Controller * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMF_CTRL_MASK) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL_MASK (0x80U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL_SHIFT (7U) /*! RAMG_CTRL - Controls automatic clock gating for the RAMG Controller * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMG_CTRL_MASK) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL_MASK (0x100U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL_SHIFT (8U) /*! RAMH_CTRL - Controls automatic clock gating for the RAMG Controller * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMH_CTRL_MASK) /*! @} */ /*! @name AUTOCLKGATEOVERRIDEC - Control Automatic Clock Gating C */ /*! @{ */ #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK (0x40000000U) #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT (30U) /*! RAMX - Controls automatic clock gating of the RAMX controller * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK) #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK (0x80000000U) #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT (31U) /*! RAMA - Controls automatic clock gating of the RAMA controller * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). * 0b0..Automatic clock gating is not overridden */ #define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK) /*! @} */ /*! @name PWM0SUBCTL - PWM0 Submodule Control */ /*! @{ */ #define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) #define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) /*! CLK0_EN - Enables PWM0 SUB Clock0 */ #define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) #define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) #define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) /*! CLK1_EN - Enables PWM0 SUB Clock1 */ #define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) #define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) #define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) /*! CLK2_EN - Enables PWM0 SUB Clock2 */ #define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) #define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) #define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) /*! CLK3_EN - Enables PWM0 SUB Clock3 */ #define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) #define SYSCON_PWM0SUBCTL_DMAVALM0_MASK (0x1000U) #define SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT (12U) /*! DMAVALM0 - PWM0 submodule 0 DMA compare value done mask */ #define SYSCON_PWM0SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM0_MASK) #define SYSCON_PWM0SUBCTL_DMAVALM1_MASK (0x2000U) #define SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT (13U) /*! DMAVALM1 - PWM0 submodule 1 DMA compare value done mask */ #define SYSCON_PWM0SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM1_MASK) #define SYSCON_PWM0SUBCTL_DMAVALM2_MASK (0x4000U) #define SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT (14U) /*! DMAVALM2 - PWM0 submodule 2 DMA compare value done mask */ #define SYSCON_PWM0SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM2_MASK) #define SYSCON_PWM0SUBCTL_DMAVALM3_MASK (0x8000U) #define SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT (15U) /*! DMAVALM3 - PWM0 submodule 3 DMA compare value done mask */ #define SYSCON_PWM0SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM3_MASK) /*! @} */ /*! @name PWM1SUBCTL - PWM1 Submodule Control */ /*! @{ */ #define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) #define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) /*! CLK0_EN - Enables PWM1 SUB Clock0 */ #define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) #define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) #define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) /*! CLK1_EN - Enables PWM1 SUB Clock1 */ #define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) #define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) #define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) /*! CLK2_EN - Enables PWM1 SUB Clock2 */ #define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) #define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) #define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) /*! CLK3_EN - Enables PWM1 SUB Clock3 */ #define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) #define SYSCON_PWM1SUBCTL_DMAVALM0_MASK (0x1000U) #define SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT (12U) /*! DMAVALM0 - PWM1 submodule 0 DMA compare value done mask */ #define SYSCON_PWM1SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM0_MASK) #define SYSCON_PWM1SUBCTL_DMAVALM1_MASK (0x2000U) #define SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT (13U) /*! DMAVALM1 - PWM1 submodule 1 DMA compare value done mask */ #define SYSCON_PWM1SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM1_MASK) #define SYSCON_PWM1SUBCTL_DMAVALM2_MASK (0x4000U) #define SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT (14U) /*! DMAVALM2 - PWM1 submodule 2 DMA compare value done mask */ #define SYSCON_PWM1SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM2_MASK) #define SYSCON_PWM1SUBCTL_DMAVALM3_MASK (0x8000U) #define SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT (15U) /*! DMAVALM3 - PWM1 submodule 3 DMA compare value done mask */ #define SYSCON_PWM1SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM3_MASK) /*! @} */ /*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */ /*! @{ */ #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) /*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock * 0b1..Enable * 0b0..Disable */ #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) /*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock * 0b1..Enable * 0b0..Disable */ #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) /*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock * 0b1..Enable * 0b0..Disable */ #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U) /*! CTIMER3_CLK_EN - Enables the CTIMER3 function clock * 0b1..Enable * 0b0..Disable */ #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U) #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U) /*! CTIMER4_CLK_EN - Enables the CTIMER4 function clock * 0b1..Enable * 0b0..Disable */ #define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK) /*! @} */ /*! @name ECC_ENABLE_CTRL - RAM ECC Enable Control */ /*! @{ */ #define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK (0x1U) #define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT (0U) /*! RAMA_ECC_ENABLE - RAMA ECC enable * 0b1..ECC is enabled * 0b0..ECC is disabled */ #define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK) #define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK (0x2U) #define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT (1U) /*! RAMB_RAMX_ECC_ENABLE - RAMB and RAMX ECC enable * 0b1..ECC is enabled * 0b0..ECC is disabled */ #define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK) #define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK (0x4U) #define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT (2U) /*! RAMD_RAMC_ECC_ENABLE - RAMD and RAMC ECC enable * 0b1..ECC is enabled * 0b0..ECC is disabled */ #define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK) #define SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE_MASK (0x8U) #define SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE_SHIFT (3U) /*! RAMF_RAME_ECC_ENABLE - RAMF and RAME ECC enable * 0b1..ECC is enabled * 0b0..ECC is disabled */ #define SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMF_RAME_ECC_ENABLE_MASK) /*! @} */ /*! @name DEBUG_LOCK_EN - Control Write Access to Security */ /*! @{ */ #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) /*! LOCK_ALL - Controls write access to the security registers * 0b1010..Enables write access to all registers * 0b0000..Any other value than b1010: disables write access to all registers */ #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) /*! @} */ /*! @name DEBUG_FEATURES - Cortex Debug Features Control */ /*! @{ */ #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) /*! CPU0_DBGEN - CPU0 invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) /*! CPU0_NIDEN - CPU0 non-invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) /*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) /*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) /*! CPU1_DBGEN - CPU1 invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) /*! CPU1_NIDEN - CPU1 non-invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) #define SYSCON_DEBUG_FEATURES_DSP_DBGDEN_MASK (0x3000U) #define SYSCON_DEBUG_FEATURES_DSP_DBGDEN_SHIFT (12U) /*! DSP_DBGDEN - DSP invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_DSP_DBGDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DSP_DBGDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DSP_DBGDEN_MASK) /*! @} */ /*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */ /*! @{ */ #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) /*! CPU0_DBGEN - CPU0 invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) /*! CPU0_NIDEN - CPU0 non-invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) /*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) /*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) /*! CPU1_DBGEN - CPU1 invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) /*! CPU1_NIDEN - CPU1 non-invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) #define SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN_MASK (0x3000U) #define SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN_SHIFT (12U) /*! DSP_DBGEN - DSP invasive debug control * 0b01..Disables debug * 0b10..Enables debug */ #define SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_DSP_DBGEN_MASK) /*! @} */ /*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access..CPU1 Software Debug Access */ /*! @{ */ #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT (0U) /*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678 * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5. */ #define SYSCON_SWD_ACCESS_CPU_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK) /*! @} */ /* The count of SYSCON_SWD_ACCESS_CPU */ #define SYSCON_SWD_ACCESS_CPU_COUNT (2U) /*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */ /*! @{ */ #define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) #define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) /*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential * Beacon and Authentication Beacon) to the application code. */ #define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) /*! @} */ /*! @name SWD_ACCESS_DSP - DSP Software Debug Access */ /*! @{ */ #define SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK (0xFFFFFFFFU) #define SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT (0U) /*! SEC_CODE - DSP SWD-AP: 0x12345678 * 0b00010010001101000101011001111000..Value to write to enable DSP SWD access. Reading back register is read as 0xA. * 0b00000000000000000000000000000000..DSP DAP is not allowed. Reading back register is read as 0x5. */ #define SYSCON_SWD_ACCESS_DSP_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK) /*! @} */ /*! @name JTAG_ID - JTAG Chip ID */ /*! @{ */ #define SYSCON_JTAG_ID_JTAG_ID_MASK (0xFFFFFFFFU) #define SYSCON_JTAG_ID_JTAG_ID_SHIFT (0U) /*! JTAG_ID - Indicates the device ID */ #define SYSCON_JTAG_ID_JTAG_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK) /*! @} */ /*! @name DEVICE_TYPE - Device Type */ /*! @{ */ #define SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK (0xFFFFFFFFU) #define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT (0U) /*! DEVICE_TYPE - Indicates DEVICE TYPE. */ #define SYSCON_DEVICE_TYPE_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK) /*! @} */ /*! @name DEVICE_ID0 - Device ID */ /*! @{ */ #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) /*! ROM_REV_MINOR - ROM revision. */ #define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) /*! @} */ /*! @name DIEID - Chip Revision ID and Number */ /*! @{ */ #define SYSCON_DIEID_MINOR_REVISION_MASK (0xFU) #define SYSCON_DIEID_MINOR_REVISION_SHIFT (0U) /*! MINOR_REVISION - Chip minor revision */ #define SYSCON_DIEID_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MINOR_REVISION_SHIFT)) & SYSCON_DIEID_MINOR_REVISION_MASK) #define SYSCON_DIEID_MAJOR_REVISION_MASK (0xF0U) #define SYSCON_DIEID_MAJOR_REVISION_SHIFT (4U) /*! MAJOR_REVISION - Chip major revision */ #define SYSCON_DIEID_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MAJOR_REVISION_SHIFT)) & SYSCON_DIEID_MAJOR_REVISION_MASK) #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF00U) #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (8U) /*! MCO_NUM_IN_DIE_ID - Chip number */ #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) /*! @} */ /*! * @} */ /* end of group SYSCON_Register_Masks */ /* SYSCON - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral SYSCON0 base address */ #define SYSCON0_BASE (0x50000000u) /** Peripheral SYSCON0 base address */ #define SYSCON0_BASE_NS (0x40000000u) /** Peripheral SYSCON0 base pointer */ #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) /** Peripheral SYSCON0 base pointer */ #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) /** Array initializer of SYSCON peripheral base addresses */ #define SYSCON_BASE_ADDRS { SYSCON0_BASE } /** Array initializer of SYSCON peripheral base pointers */ #define SYSCON_BASE_PTRS { SYSCON0 } /** Array initializer of SYSCON peripheral base addresses */ #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } /** Array initializer of SYSCON peripheral base pointers */ #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } #else /** Peripheral SYSCON0 base address */ #define SYSCON0_BASE (0x40000000u) /** Peripheral SYSCON0 base pointer */ #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) /** Array initializer of SYSCON peripheral base addresses */ #define SYSCON_BASE_ADDRS { SYSCON0_BASE } /** Array initializer of SYSCON peripheral base pointers */ #define SYSCON_BASE_PTRS { SYSCON0 } #endif /* Backward compatibility */ #define SYSCON SYSCON0 /*! * @} */ /* end of group SYSCON_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SYSPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer * @{ */ /** SYSPM - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x30 */ __IO uint32_t PMCR; /**< Performance Monitor Control, array offset: 0x0, array step: 0x30 */ uint8_t RESERVED_0[20]; struct { /* offset: 0x18, array step: index*0x30, index2*0x8 */ __I uint8_t HI; /**< Performance Monitor Event Counter, array offset: 0x18, array step: index*0x30, index2*0x8 */ uint8_t RESERVED_0[3]; __I uint32_t LO; /**< Performance Monitor Event Counter, array offset: 0x1C, array step: index*0x30, index2*0x8 */ } PMECTR[3]; } PMCR[1]; } SYSPM_Type; /* ---------------------------------------------------------------------------- -- SYSPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SYSPM_Register_Masks SYSPM Register Masks * @{ */ /*! @name PMCR - Performance Monitor Control */ /*! @{ */ #define SYSPM_PMCR_MENB_MASK (0x1U) #define SYSPM_PMCR_MENB_SHIFT (0U) /*! MENB - Module Is Enabled * 0b0..Disabled * 0b1..Enabled */ #define SYSPM_PMCR_MENB(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK) #define SYSPM_PMCR_SSC_MASK (0xEU) #define SYSPM_PMCR_SSC_SHIFT (1U) /*! SSC - Start and Stop Control * 0b000..Idle or no-op * 0b001..Local stop * 0b010, 0b011..Local start * 0b100.. * 0b101.. * 0b110, 0b111.. */ #define SYSPM_PMCR_SSC(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK) #define SYSPM_PMCR_CMODE_MASK (0x30U) #define SYSPM_PMCR_CMODE_SHIFT (4U) /*! CMODE - Count Mode * 0b00..Counted in both User and Privileged modes * 0b01.. * 0b10..Counted only in User mode * 0b11..Counted only in Privileged mode */ #define SYSPM_PMCR_CMODE(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK) #define SYSPM_PMCR_RECTR1_MASK (0x100U) #define SYSPM_PMCR_RECTR1_SHIFT (8U) /*! RECTR1 - Reset Event Counter 1 * 0b0..Run normally * 0b1..Reset */ #define SYSPM_PMCR_RECTR1(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK) #define SYSPM_PMCR_RECTR2_MASK (0x200U) #define SYSPM_PMCR_RECTR2_SHIFT (9U) /*! RECTR2 - Reset Event Counter 2 * 0b0..Run normally * 0b1..Reset */ #define SYSPM_PMCR_RECTR2(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK) #define SYSPM_PMCR_RECTR3_MASK (0x400U) #define SYSPM_PMCR_RECTR3_SHIFT (10U) /*! RECTR3 - Reset Event Counter 3 * 0b0..Run normally * 0b1..Reset */ #define SYSPM_PMCR_RECTR3(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK) #define SYSPM_PMCR_SELEVT1_MASK (0x3F800U) #define SYSPM_PMCR_SELEVT1_SHIFT (11U) /*! SELEVT1 - Select Event 1 */ #define SYSPM_PMCR_SELEVT1(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK) #define SYSPM_PMCR_SELEVT2_MASK (0x1FC0000U) #define SYSPM_PMCR_SELEVT2_SHIFT (18U) /*! SELEVT2 - Select Event 2 */ #define SYSPM_PMCR_SELEVT2(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK) #define SYSPM_PMCR_SELEVT3_MASK (0xFE000000U) #define SYSPM_PMCR_SELEVT3_SHIFT (25U) /*! SELEVT3 - Select Event 3 */ #define SYSPM_PMCR_SELEVT3(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK) /*! @} */ /* The count of SYSPM_PMCR */ #define SYSPM_PMCR_COUNT (1U) /*! @name PMCR_PMECTR_HI - Performance Monitor Event Counter */ /*! @{ */ #define SYSPM_PMCR_PMECTR_HI_ECTR_MASK (0xFFU) #define SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT (0U) /*! ECTR - Event Counter */ #define SYSPM_PMCR_PMECTR_HI_ECTR(x) (((uint8_t)(((uint8_t)(x)) << SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_HI_ECTR_MASK) /*! @} */ /* The count of SYSPM_PMCR_PMECTR_HI */ #define SYSPM_PMCR_PMECTR_HI_COUNT (1U) /* The count of SYSPM_PMCR_PMECTR_HI */ #define SYSPM_PMCR_PMECTR_HI_COUNT2 (3U) /*! @name PMCR_PMECTR_LO - Performance Monitor Event Counter */ /*! @{ */ #define SYSPM_PMCR_PMECTR_LO_ECTR_MASK (0xFFFFFFFFU) #define SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT (0U) /*! ECTR - Event Counter */ #define SYSPM_PMCR_PMECTR_LO_ECTR(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_LO_ECTR_MASK) /*! @} */ /* The count of SYSPM_PMCR_PMECTR_LO */ #define SYSPM_PMCR_PMECTR_LO_COUNT (1U) /* The count of SYSPM_PMCR_PMECTR_LO */ #define SYSPM_PMCR_PMECTR_LO_COUNT2 (3U) /*! * @} */ /* end of group SYSPM_Register_Masks */ /* SYSPM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral CMX_PERFMON0 base address */ #define CMX_PERFMON0_BASE (0x500C1000u) /** Peripheral CMX_PERFMON0 base address */ #define CMX_PERFMON0_BASE_NS (0x400C1000u) /** Peripheral CMX_PERFMON0 base pointer */ #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) /** Peripheral CMX_PERFMON0 base pointer */ #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) /** Peripheral CMX_PERFMON1 base address */ #define CMX_PERFMON1_BASE (0x500C2000u) /** Peripheral CMX_PERFMON1 base address */ #define CMX_PERFMON1_BASE_NS (0x400C2000u) /** Peripheral CMX_PERFMON1 base pointer */ #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) /** Peripheral CMX_PERFMON1 base pointer */ #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) /** Array initializer of SYSPM peripheral base addresses */ #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } /** Array initializer of SYSPM peripheral base pointers */ #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } /** Array initializer of SYSPM peripheral base addresses */ #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } /** Array initializer of SYSPM peripheral base pointers */ #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } #else /** Peripheral CMX_PERFMON0 base address */ #define CMX_PERFMON0_BASE (0x400C1000u) /** Peripheral CMX_PERFMON0 base pointer */ #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) /** Peripheral CMX_PERFMON1 base address */ #define CMX_PERFMON1_BASE (0x400C2000u) /** Peripheral CMX_PERFMON1 base pointer */ #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) /** Array initializer of SYSPM peripheral base addresses */ #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } /** Array initializer of SYSPM peripheral base pointers */ #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } #endif /*! * @} */ /* end of group SYSPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TRDC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer * @{ */ /** TRDC - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x1CC */ __IO uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1CC, index2*0x4 */ __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10, array step: 0x1CC */ __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x14, array step: 0x1CC */ __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x18, array step: 0x1CC */ __O uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1C, array step: 0x1CC */ __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1CC, index2*0x4 */ __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1CC, index2*0x4 */ uint8_t RESERVED_0[224]; __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x140, array step: index*0x1CC, index2*0x4 */ uint8_t RESERVED_1[56]; __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1CC, index2*0x4 */ uint8_t RESERVED_2[28]; __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1A0, array step: index*0x1CC, index2*0x4 */ uint8_t RESERVED_3[4]; __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1CC, index2*0x4 */ uint8_t RESERVED_4[28]; __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1C8, array step: index*0x1CC, index2*0x4 */ } MBC_INDEX[1]; } TRDC_Type; /* ---------------------------------------------------------------------------- -- TRDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TRDC_Register_Masks TRDC Register Masks * @{ */ /*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) /*! NBLKS - Number of blocks in this memory */ #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) /*! SIZE_LOG2 - Log2 size per block */ #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) /*! CLRE - Clear Error */ #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) /* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ #define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) /*! @name MBC_INDEX_MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) /*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK) #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) /*! MEM_SEL - Memory Select */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) /*! DID_SEL0 - DID Select * 0b0..No effect. * 0b1..Selects NSE bits for this domain. */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK (0x80000000U) #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT (31U) /*! AI - Auto Increment * 0b0..No effect. * 0b1..Add 1 to the WNDX field after the register write. */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_COUNT (1U) /*! @name MBC_INDEX_MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) #define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) /*! W1SET - Write-1 Set */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_SET */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_COUNT (1U) /*! @name MBC_INDEX_MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) /*! W1CLR - Write-1 Clear */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_COUNT (1U) /*! @name MBC_INDEX_MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) /*! MEMSEL - Memory Select */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) /*! DID_SEL0 - DID Select * 0b0..No effect. * 0b1..Clear all NSE bits for this domain. */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL */ #define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_COUNT (1U) /*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) /*! NUX - NonsecureUser Execute * 0b0..Execute access is not allowed in Nonsecure User mode. * 0b1..Execute access is allowed in Nonsecure User mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) /*! NUW - NonsecureUser Write * 0b0..Write access is not allowed in Nonsecure User mode. * 0b1..Write access is allowed in Nonsecure User mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) /*! NUR - NonsecureUser Read * 0b0..Read access is not allowed in Nonsecure User mode. * 0b1..Read access is allowed in Nonsecure User mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) /*! NPX - NonsecurePriv Execute * 0b0..Execute access is not allowed in Nonsecure Privilege mode. * 0b1..Execute access is allowed in Nonsecure Privilege mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) /*! NPW - NonsecurePriv Write * 0b0..Write access is not allowed in Nonsecure Privilege mode. * 0b1..Write access is allowed in Nonsecure Privilege mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) /*! NPR - NonsecurePriv Read * 0b0..Read access is not allowed in Nonsecure Privilege mode. * 0b1..Read access is allowed in Nonsecure Privilege mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) /*! SUX - SecureUser Execute * 0b0..Execute access is not allowed in Secure User mode. * 0b1..Execute access is allowed in Secure User mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) /*! SUW - SecureUser Write * 0b0..Write access is not allowed in Secure User mode. * 0b1..Write access is allowed in Secure User mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) /*! SUR - SecureUser Read * 0b0..Read access is not allowed in Secure User mode. * 0b1..Read access is allowed in Secure User mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) /*! SPX - SecurePriv Execute * 0b0..Execute access is not allowed in Secure Privilege mode. * 0b1..Execute access is allowed in Secure Privilege mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) /*! SPW - SecurePriv Write * 0b0..Write access is not allowed in Secure Privilege mode. * 0b1..Write access is allowed in Secure Privilege mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) /*! SPR - SecurePriv Read * 0b0..Read access is not allowed in Secure Privilege mode. * 0b1..Read access is allowed in Secure Privilege mode. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) /*! LK - LOCK * 0b0..This register is not locked and can be altered. * 0b1..This register is locked and cannot be altered. */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) /* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ #define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) /*! MBACSEL0 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) /*! NSE0 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) /*! MBACSEL1 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) /*! NSE1 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) /*! MBACSEL2 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) /*! NSE2 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) /*! MBACSEL3 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) /*! NSE3 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) /*! MBACSEL4 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) /*! NSE4 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) /*! MBACSEL5 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) /*! NSE5 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) /*! MBACSEL6 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) /*! NSE6 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) /*! MBACSEL7 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) /*! NSE7 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (8U) /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (1U) /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U) /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) /*! MBACSEL0 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) /*! NSE0 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) /*! MBACSEL1 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) /*! NSE1 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) /*! MBACSEL2 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) /*! NSE2 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) /*! MBACSEL3 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) /*! NSE3 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) /*! MBACSEL4 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) /*! NSE4 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) /*! MBACSEL5 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) /*! NSE5 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) /*! MBACSEL6 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) /*! NSE6 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) /*! MBACSEL7 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) /*! NSE7 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (1U) /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) /*! MBACSEL0 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) /*! NSE0 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) /*! MBACSEL1 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) /*! NSE1 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) /*! MBACSEL2 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) /*! NSE2 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) /*! MBACSEL3 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) /*! NSE3 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) /*! MBACSEL4 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) /*! NSE4 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) /*! MBACSEL5 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) /*! NSE5 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) /*! MBACSEL6 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) /*! NSE6 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) /*! MBACSEL7 - Memory Block Access Control Select for block B * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) /*! NSE7 - NonSecure Enable for block B * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) /*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) /*! @} */ /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (1U) /* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ #define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U) /*! * @} */ /* end of group TRDC_Register_Masks */ /* TRDC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral TRDC base address */ #define TRDC_BASE (0x500C7000u) /** Peripheral TRDC base address */ #define TRDC_BASE_NS (0x400C7000u) /** Peripheral TRDC base pointer */ #define TRDC ((TRDC_Type *)TRDC_BASE) /** Peripheral TRDC base pointer */ #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) /** Array initializer of TRDC peripheral base addresses */ #define TRDC_BASE_ADDRS { TRDC_BASE } /** Array initializer of TRDC peripheral base pointers */ #define TRDC_BASE_PTRS { TRDC } /** Array initializer of TRDC peripheral base addresses */ #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } /** Array initializer of TRDC peripheral base pointers */ #define TRDC_BASE_PTRS_NS { TRDC_NS } #else /** Peripheral TRDC base address */ #define TRDC_BASE (0x400C7000u) /** Peripheral TRDC base pointer */ #define TRDC ((TRDC_Type *)TRDC_BASE) /** Array initializer of TRDC peripheral base addresses */ #define TRDC_BASE_ADDRS { TRDC_BASE } /** Array initializer of TRDC peripheral base pointers */ #define TRDC_BASE_PTRS { TRDC } #endif #define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} #define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} #define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} #define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} #define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} #define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} #define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} #define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} #define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} #define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} /*! * @} */ /* end of group TRDC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TSI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer * @{ */ /** TSI - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ __IO uint32_t CONFIG_MUTUAL; /**< TSI CONFIG (TSI_CONFIG) for Mutual-Capacitor, offset: 0x0 */ __IO uint32_t CONFIG; /**< TSI CONFIG (TSI_CONFIG) for Self-Capacitor, offset: 0x0 */ }; __IO uint32_t TSHD; /**< TSI Threshold, offset: 0x4 */ __IO uint32_t GENCS; /**< TSI General Control and Status, offset: 0x8 */ __IO uint32_t MUL; /**< TSI Mutual-Capacitance, offset: 0xC */ __IO uint32_t SINC; /**< TSI SINC Filter, offset: 0x10 */ __IO uint32_t SSC0; /**< TSI SSC 0, offset: 0x14 */ __IO uint32_t SSC1; /**< TSI SSC 1, offset: 0x18 */ __IO uint32_t SSC2; /**< TSI SSC 2, offset: 0x1C */ __IO uint32_t BASELINE; /**< TSI Baseline, offset: 0x20 */ __IO uint32_t CHMERGE; /**< TSI Channel Merge, offset: 0x24 */ __IO uint32_t SHIELD; /**< TSI Shield, offset: 0x28 */ uint8_t RESERVED_0[212]; __IO uint32_t DATA; /**< TSI Data and Status, offset: 0x100 */ uint8_t RESERVED_1[4]; __IO uint32_t MISC; /**< TSI Miscellaneous, offset: 0x108 */ __IO uint32_t TRIG; /**< TSI AUTO TRIG, offset: 0x10C */ } TSI_Type; /* ---------------------------------------------------------------------------- -- TSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TSI_Register_Masks TSI Register Masks * @{ */ /*! @name CONFIG_MUTUAL - TSI CONFIG (TSI_CONFIG) for Mutual-Capacitor */ /*! @{ */ #define TSI_CONFIG_MUTUAL_MODE_MASK (0x1U) #define TSI_CONFIG_MUTUAL_MODE_SHIFT (0U) /*! MODE - Mode * 0b0..Self capacitance * 0b1..Mutual capacitance */ #define TSI_CONFIG_MUTUAL_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_MODE_SHIFT)) & TSI_CONFIG_MUTUAL_MODE_MASK) #define TSI_CONFIG_MUTUAL_M_NMIRROR_MASK (0x6U) #define TSI_CONFIG_MUTUAL_M_NMIRROR_SHIFT (1U) /*! M_NMIRROR - NMOS Current Mirror * 0b00..m = 1 * 0b01..m = 2 * 0b10..m = 3 * 0b11..m = 4 */ #define TSI_CONFIG_MUTUAL_M_NMIRROR(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_NMIRROR_SHIFT)) & TSI_CONFIG_MUTUAL_M_NMIRROR_MASK) #define TSI_CONFIG_MUTUAL_M_PMIRRORR_MASK (0x18U) #define TSI_CONFIG_MUTUAL_M_PMIRRORR_SHIFT (3U) /*! M_PMIRRORR - PMOS Current Mirror on Right Side * 0b00..m = 1 * 0b01..m = 2 * 0b10..m = 3 * 0b11..m = 4 */ #define TSI_CONFIG_MUTUAL_M_PMIRRORR(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_PMIRRORR_SHIFT)) & TSI_CONFIG_MUTUAL_M_PMIRRORR_MASK) #define TSI_CONFIG_MUTUAL_M_PMIRRORL_MASK (0xE0U) #define TSI_CONFIG_MUTUAL_M_PMIRRORL_SHIFT (5U) /*! M_PMIRRORL - PMOS Current Mirror on Left Side * 0b000..m = 4 * 0b001..m = 8 * 0b010..m = 12 * 0b011..m = 16 * 0b100..m = 20 * 0b101..m = 24 * 0b110..m = 28 * 0b111..m = 32 */ #define TSI_CONFIG_MUTUAL_M_PMIRRORL(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_PMIRRORL_SHIFT)) & TSI_CONFIG_MUTUAL_M_PMIRRORL_MASK) #define TSI_CONFIG_MUTUAL_M_SEL_RX_MASK (0x1F00U) #define TSI_CONFIG_MUTUAL_M_SEL_RX_SHIFT (8U) /*! M_SEL_RX - Mutual-Capacitance RX Channel Selection * 0b00000..TSI[8] * 0b00001..TSI[9] * 0b00010..TSI[10] * 0b00011..TSI[11] * 0b00100..TSI[12] * 0b00101..TSI[13] * 0b00110..TSI[14] * 0b00111..TSI[15] * 0b01000..TSI[16] * 0b01001..TSI[17] * 0b01010..TSI[18] * 0b01011..TSI[19] * 0b01100..TSI[20] * 0b01101..TSI[21] * 0b01110..TSI[22] * 0b01111..TSI[23] * 0b10000..TSI[24] */ #define TSI_CONFIG_MUTUAL_M_SEL_RX(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_SEL_RX_SHIFT)) & TSI_CONFIG_MUTUAL_M_SEL_RX_MASK) #define TSI_CONFIG_MUTUAL_M_SEL_TX_MASK (0xE000U) #define TSI_CONFIG_MUTUAL_M_SEL_TX_SHIFT (13U) /*! M_SEL_TX - Mutual-Capacitance TX Channel Selection * 0b000..TSI[0] * 0b001..TSI[1] * 0b010..TSI[2] * 0b011..TSI[3] * 0b100..TSI[4] * 0b101..TSI[5] * 0b110..TSI[6] * 0b111..TSI[7] */ #define TSI_CONFIG_MUTUAL_M_SEL_TX(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_SEL_TX_SHIFT)) & TSI_CONFIG_MUTUAL_M_SEL_TX_MASK) #define TSI_CONFIG_MUTUAL_M_CNT_EN_MASK (0x10000U) #define TSI_CONFIG_MUTUAL_M_CNT_EN_SHIFT (16U) /*! M_CNT_EN - Mutual-Capacitance Counter Enable * 0b0..Disables * 0b1..Enables */ #define TSI_CONFIG_MUTUAL_M_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_CNT_EN_SHIFT)) & TSI_CONFIG_MUTUAL_M_CNT_EN_MASK) #define TSI_CONFIG_MUTUAL_M_TX_PD_EN_MASK (0x20000U) #define TSI_CONFIG_MUTUAL_M_TX_PD_EN_SHIFT (17U) /*! M_TX_PD_EN - Mutual-Capacitance TX Pulldown Enable * 0b0..Disables * 0b1..Enables */ #define TSI_CONFIG_MUTUAL_M_TX_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_TX_PD_EN_SHIFT)) & TSI_CONFIG_MUTUAL_M_TX_PD_EN_MASK) #define TSI_CONFIG_MUTUAL_M_SEN_BOOST_MASK (0x7C0000U) #define TSI_CONFIG_MUTUAL_M_SEN_BOOST_SHIFT (18U) /*! M_SEN_BOOST - Mutual-Capacitance Sensitivity Boost * 0b00000..0 uA * 0b00001..2 uA * 0b00010..4 uA * 0b00011..6 uA * 0b00100..8 uA * 0b00101..10 uA * 0b00110..12 uA * 0b00111..14 uA * 0b1xxxx..2 * n uA * 0b11111..62 uA */ #define TSI_CONFIG_MUTUAL_M_SEN_BOOST(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_SEN_BOOST_SHIFT)) & TSI_CONFIG_MUTUAL_M_SEN_BOOST_MASK) #define TSI_CONFIG_MUTUAL_M_PRE_RES_MASK (0x1C000000U) #define TSI_CONFIG_MUTUAL_M_PRE_RES_SHIFT (26U) /*! M_PRE_RES - Mutual-Capacitance Precharge Resistor * 0b000..1 kΩ * 0b001..2 kΩ * 0b010..3 kΩ * 0b011..4 kΩ * 0b100..5 kΩ * 0b101..6 kΩ * 0b110..7 kΩ * 0b111..8 kΩ */ #define TSI_CONFIG_MUTUAL_M_PRE_RES(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_PRE_RES_SHIFT)) & TSI_CONFIG_MUTUAL_M_PRE_RES_MASK) #define TSI_CONFIG_MUTUAL_M_PRE_CURRENT_MASK (0xE0000000U) #define TSI_CONFIG_MUTUAL_M_PRE_CURRENT_SHIFT (29U) /*! M_PRE_CURRENT - Mutual-Capacitance Precharge Current * 0b000..1 uA * 0b001..2 uA * 0b010..3 uA * 0b011..4 uA * 0b100..5 uA * 0b101..6 uA * 0b110..7 uA * 0b111..8 uA */ #define TSI_CONFIG_MUTUAL_M_PRE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MUTUAL_M_PRE_CURRENT_SHIFT)) & TSI_CONFIG_MUTUAL_M_PRE_CURRENT_MASK) /*! @} */ /*! @name CONFIG - TSI CONFIG (TSI_CONFIG) for Self-Capacitor */ /*! @{ */ #define TSI_CONFIG_MODE_MASK (0x1U) #define TSI_CONFIG_MODE_SHIFT (0U) /*! MODE - Mode * 0b0..Self capacitance * 0b1..Mutual capacitance */ #define TSI_CONFIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_MODE_SHIFT)) & TSI_CONFIG_MODE_MASK) #define TSI_CONFIG_TSICH_MASK (0x3EU) #define TSI_CONFIG_TSICH_SHIFT (1U) /*! TSICH - TSI Channel * 0b00000..Channel 0 * 0b00001..Channel 1 * 0b00010..Channel 2 * 0b00011..Channel 3 * 0b00100..Channel 4 * 0b00101..Channel 5 * 0b00110..Channel 6 * 0b00111..Channel 7 * 0b01000..Channel 8 * 0b01001..Channel 9 * 0b01010..Channel 10 * 0b01011..Channel 11 * 0b01100..Channel 12 * 0b01101..Channel 13 * 0b01110..Channel 14 * 0b01111..Channel 15 * 0b10000..Channel 16 * 0b10001..Channel 17 * 0b10010..Channel 18 * 0b10011..Channel 19 * 0b10100..Channel 20 * 0b10101..Channel 21 * 0b10110..Channel 22 * 0b10111..Channel 23 * 0b11000..Channel 24 */ #define TSI_CONFIG_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_TSICH_SHIFT)) & TSI_CONFIG_TSICH_MASK) #define TSI_CONFIG_S_NOISE_MASK (0x80000U) #define TSI_CONFIG_S_NOISE_SHIFT (19U) /*! S_NOISE - Self-Capacitance Noise Cancelation * 0b0..Disables * 0b1..Enables */ #define TSI_CONFIG_S_NOISE(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_NOISE_SHIFT)) & TSI_CONFIG_S_NOISE_MASK) #define TSI_CONFIG_S_XCH_MASK (0x700000U) #define TSI_CONFIG_S_XCH_SHIFT (20U) /*! S_XCH - Self-Capacitance Charge Current Multiple * 0b000..1 / 16 * 0b001..1 / 8 * 0b010..1 / 4 * 0b011..1 / 2 */ #define TSI_CONFIG_S_XCH(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_XCH_SHIFT)) & TSI_CONFIG_S_XCH_MASK) #define TSI_CONFIG_S_XIN_MASK (0x800000U) #define TSI_CONFIG_S_XIN_SHIFT (23U) /*! S_XIN - Self-Capacitance Input Current Multiple * 0b0..1 / 8 * 0b1..1 / 4 */ #define TSI_CONFIG_S_XIN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_XIN_SHIFT)) & TSI_CONFIG_S_XIN_MASK) #define TSI_CONFIG_S_CTRIM_MASK (0x7000000U) #define TSI_CONFIG_S_CTRIM_SHIFT (24U) /*! S_CTRIM - Capacitor Trim Setting * 0b000..2.5 pF * 0b001..5.0 pF * 0b010..7.5 pF * 0b011..10 pF * 0b100..12.5 pF * 0b101..15.0 pF * 0b110..17.5 pF * 0b111..20 pF */ #define TSI_CONFIG_S_CTRIM(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_CTRIM_SHIFT)) & TSI_CONFIG_S_CTRIM_MASK) #define TSI_CONFIG_S_SEN_MASK (0x8000000U) #define TSI_CONFIG_S_SEN_SHIFT (27U) /*! S_SEN - Self-Capacitance Sensitivity Boost * 0b0..Disables * 0b1..Enables */ #define TSI_CONFIG_S_SEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_SEN_SHIFT)) & TSI_CONFIG_S_SEN_MASK) #define TSI_CONFIG_S_XDN_MASK (0x70000000U) #define TSI_CONFIG_S_XDN_SHIFT (28U) /*! S_XDN - Self-Capacitance Discharge Current Multiple * 0b000..1 / 16 * 0b001..1 / 8 * 0b010..1 / 4 * 0b011..1 / 2 */ #define TSI_CONFIG_S_XDN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_XDN_SHIFT)) & TSI_CONFIG_S_XDN_MASK) #define TSI_CONFIG_S_XIN_ADD_MASK (0x80000000U) #define TSI_CONFIG_S_XIN_ADD_SHIFT (31U) /*! S_XIN_ADD - S_XIN Adjust Ratio * 0b0..Disables; S_XIN = 0 for 1 / 4, S_XIN = 1 for 1 / 8 * 0b1..Enables; S_XIN = 0 for 1 / 8, S_XIN = 1 for 1 / 16 */ #define TSI_CONFIG_S_XIN_ADD(x) (((uint32_t)(((uint32_t)(x)) << TSI_CONFIG_S_XIN_ADD_SHIFT)) & TSI_CONFIG_S_XIN_ADD_MASK) /*! @} */ /*! @name TSHD - TSI Threshold */ /*! @{ */ #define TSI_TSHD_THRESL_MASK (0xFFFFU) #define TSI_TSHD_THRESL_SHIFT (0U) /*! THRESL - TSI Wakeup Channel Low Threshold */ #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK) #define TSI_TSHD_THRESH_MASK (0xFFFF0000U) #define TSI_TSHD_THRESH_SHIFT (16U) /*! THRESH - TSI Wakeup Channel High Threshold */ #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK) /*! @} */ /*! @name GENCS - TSI General Control and Status */ /*! @{ */ #define TSI_GENCS_DMAEN_EOS_MASK (0x1U) #define TSI_GENCS_DMAEN_EOS_SHIFT (0U) /*! DMAEN_EOS - In-Progress DMA Transfer Request Enable * 0b0..Disables * 0b1..Enables */ #define TSI_GENCS_DMAEN_EOS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DMAEN_EOS_SHIFT)) & TSI_GENCS_DMAEN_EOS_MASK) #define TSI_GENCS_DMAEN_OUTRG_MASK (0x4U) #define TSI_GENCS_DMAEN_OUTRG_SHIFT (2U) /*! DMAEN_OUTRG - Out-of-Range DMA Transfer Request Enable * 0b0..Disables * 0b1..Enables */ #define TSI_GENCS_DMAEN_OUTRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DMAEN_OUTRG_SHIFT)) & TSI_GENCS_DMAEN_OUTRG_MASK) #define TSI_GENCS_STM_MASK (0x8U) #define TSI_GENCS_STM_SHIFT (3U) /*! STM - Scan Trigger Mode * 0b0..Software trigger scan * 0b1..Hardware trigger scan */ #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) #define TSI_GENCS_STPE_MASK (0x10U) #define TSI_GENCS_STPE_SHIFT (4U) /*! STPE - TSI Stop Enable * 0b0..Disables * 0b1..Enables */ #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) #define TSI_GENCS_TSIEN_MASK (0x20U) #define TSI_GENCS_TSIEN_SHIFT (5U) /*! TSIEN - TSI Enable * 0b0..Disables * 0b1..Enables */ #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) #define TSI_GENCS_SWTS_MASK (0x80U) #define TSI_GENCS_SWTS_SHIFT (7U) /*! SWTS - Software Trigger Start * 0b0..No effect * 0b1..Takes effect */ #define TSI_GENCS_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SWTS_SHIFT)) & TSI_GENCS_SWTS_MASK) #define TSI_GENCS_CTRIM_FINE_MASK (0xE00U) #define TSI_GENCS_CTRIM_FINE_SHIFT (9U) /*! CTRIM_FINE - Capacitor Fine Trim * 0b000..0.3125 pF * 0b001..0.625 pF * 0b010..0.3125 * 3 pF * 0b011..0.3125 * 4 pF * 0b100..0.3125 * 5 pF * 0b101..0.3125 * 6 pF * 0b110..2.1875 pF * 0b111..2.5 pF */ #define TSI_GENCS_CTRIM_FINE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CTRIM_FINE_SHIFT)) & TSI_GENCS_CTRIM_FINE_MASK) #define TSI_GENCS_DVOLT_MASK (0x7000U) #define TSI_GENCS_DVOLT_SHIFT (12U) /*! DVOLT - Delta Voltage * 0b000..Vm = 0.6 V, Vp = 1.7 V * 0b001..Vm = 0.6 V, Vp = 1.9 V * 0b010..Vm = 0.6 V, Vp = 2.1 V * 0b011..Vm = 0.6 V, Vp = 2.3 V * 0b100..Vm = 0.6 V, Vp = 2.5 V * 0b101..Vm = 0.6 V, Vp = 2.7 V */ #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK) #define TSI_GENCS_DEBOUNCE_MASK (0x1F0000U) #define TSI_GENCS_DEBOUNCE_SHIFT (16U) /*! DEBOUNCE - Debounce * 0b00000..1 * 0b00001..2 * 0b1xxxx..n * 0b11111..31 */ #define TSI_GENCS_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DEBOUNCE_SHIFT)) & TSI_GENCS_DEBOUNCE_MASK) #define TSI_GENCS_S_PROX_EN_MASK (0x400000U) #define TSI_GENCS_S_PROX_EN_SHIFT (22U) /*! S_PROX_EN - Proximity Enable Signal * 0b0..Disables * 0b1..Enables */ #define TSI_GENCS_S_PROX_EN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_S_PROX_EN_SHIFT)) & TSI_GENCS_S_PROX_EN_MASK) #define TSI_GENCS_SETCLK_MASK (0x7000000U) #define TSI_GENCS_SETCLK_SHIFT (24U) /*! SETCLK - Set Clock * 0b000..27.37 MHz * 0b001..22.23 MHz * 0b010..18.73 MHz * 0b011..16.65 MHz * 0b100..14.27 MHz * 0b101..12.73 MHz * 0b110..11.49 MHz * 0b111..10.46 MHz */ #define TSI_GENCS_SETCLK(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SETCLK_SHIFT)) & TSI_GENCS_SETCLK_MASK) #define TSI_GENCS_ESOR_MASK (0x8000000U) #define TSI_GENCS_ESOR_SHIFT (27U) /*! ESOR - End-of-Scan Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) #define TSI_GENCS_OUTRG_EN_MASK (0x40000000U) #define TSI_GENCS_OUTRG_EN_SHIFT (30U) /*! OUTRG_EN - Out-of-Range Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define TSI_GENCS_OUTRG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRG_EN_SHIFT)) & TSI_GENCS_OUTRG_EN_MASK) /*! @} */ /*! @name MUL - TSI Mutual-Capacitance */ /*! @{ */ #define TSI_MUL_M_VPRE_CHOOSE_MASK (0x2U) #define TSI_MUL_M_VPRE_CHOOSE_SHIFT (1U) /*! M_VPRE_CHOOSE - Mutual-Capacitance Prevoltage * 0b0..Internal 1.2 V * 0b1..External 1.2 V from PMC */ #define TSI_MUL_M_VPRE_CHOOSE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_VPRE_CHOOSE_SHIFT)) & TSI_MUL_M_VPRE_CHOOSE_MASK) #define TSI_MUL_M_MODE_MASK (0x4U) #define TSI_MUL_M_MODE_SHIFT (2U) /*! M_MODE - Mutual-Capacitance Mode * 0b0..- 5 V ~ + 5 V * 0b1..0 V ~ + 5 V */ #define TSI_MUL_M_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_MODE_SHIFT)) & TSI_MUL_M_MODE_MASK) #define TSI_MUL_M_TRIM_CAP_MASK (0x18U) #define TSI_MUL_M_TRIM_CAP_SHIFT (3U) /*! M_TRIM_CAP - Mutual-Capacitance Trim Cap * 0b00..0 pF * 0b01..10 pF * 0b10..10 pF * 0b11..20 pF */ #define TSI_MUL_M_TRIM_CAP(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_TRIM_CAP_SHIFT)) & TSI_MUL_M_TRIM_CAP_MASK) #define TSI_MUL_M_TX_USED_MASK (0x1FE0U) #define TSI_MUL_M_TX_USED_SHIFT (5U) /*! M_TX_USED - Mutual-Capacitance TX Used * 0b00000000..GPIO * 0b00000001..Mutual capacitance */ #define TSI_MUL_M_TX_USED(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_TX_USED_SHIFT)) & TSI_MUL_M_TX_USED_MASK) #define TSI_MUL_M_TRIM_MASK (0xFFFF0000U) #define TSI_MUL_M_TRIM_SHIFT (16U) /*! M_TRIM - Mutual-Capacitance Trim */ #define TSI_MUL_M_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL_M_TRIM_SHIFT)) & TSI_MUL_M_TRIM_MASK) /*! @} */ /*! @name SINC - TSI SINC Filter */ /*! @{ */ #define TSI_SINC_SSC_CONTROL_OUT_MASK (0x1U) #define TSI_SINC_SSC_CONTROL_OUT_SHIFT (0U) /*! SSC_CONTROL_OUT - SSC Output Control * 0b0..0 * 0b1..1 */ #define TSI_SINC_SSC_CONTROL_OUT(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SSC_CONTROL_OUT_SHIFT)) & TSI_SINC_SSC_CONTROL_OUT_MASK) #define TSI_SINC_SINC_VALID_MASK (0x2U) #define TSI_SINC_SINC_VALID_SHIFT (1U) /*! SINC_VALID - SINC Valid * 0b0..Disabled * 0b1..Enabled */ #define TSI_SINC_SINC_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SINC_VALID_SHIFT)) & TSI_SINC_SINC_VALID_MASK) #define TSI_SINC_SINC_OVERFLOW_FLAG_MASK (0x4U) #define TSI_SINC_SINC_OVERFLOW_FLAG_SHIFT (2U) /*! SINC_OVERFLOW_FLAG - SINC Overflow Flag * 0b0..No overflow * 0b1..Overflow */ #define TSI_SINC_SINC_OVERFLOW_FLAG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SINC_OVERFLOW_FLAG_SHIFT)) & TSI_SINC_SINC_OVERFLOW_FLAG_MASK) #define TSI_SINC_SWITCH_ENABLE_MASK (0x8U) #define TSI_SINC_SWITCH_ENABLE_SHIFT (3U) /*! SWITCH_ENABLE - Switch Enable * 0b0..Disabled * 0b1..Enabled */ #define TSI_SINC_SWITCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SWITCH_ENABLE_SHIFT)) & TSI_SINC_SWITCH_ENABLE_MASK) #define TSI_SINC_DECIMATION_MASK (0x1F0000U) #define TSI_SINC_DECIMATION_SHIFT (16U) /*! DECIMATION - Decimation * 0b00000..1 * 0b00001..2 * 0b00010..3 * 0b00011..4 * 0b00100..5 * 0b00101..6 * 0b00110..7 * 0b00111..8 * 0b01000..9 * 0b01001..10 * 0b01010..11 * 0b01011..12 * 0b01100..13 * 0b01101..14 * 0b01110..15 * 0b01111..16 * 0b10000..17 * 0b10001..18 * 0b10010..19 * 0b10011..20 * 0b10100..21 * 0b10101..22 * 0b10110..23 * 0b10111..24 * 0b11000..25 * 0b11001..26 * 0b11010..27 * 0b11011..28 * 0b11100..29 * 0b11101..30 * 0b11110..31 * 0b11111..32 */ #define TSI_SINC_DECIMATION(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_DECIMATION_SHIFT)) & TSI_SINC_DECIMATION_MASK) #define TSI_SINC_ORDER_MASK (0x200000U) #define TSI_SINC_ORDER_SHIFT (21U) /*! ORDER - Order * 0b0..Order 1 * 0b1..Order 2 */ #define TSI_SINC_ORDER(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_ORDER_SHIFT)) & TSI_SINC_ORDER_MASK) #define TSI_SINC_CUTOFF_MASK (0xF000000U) #define TSI_SINC_CUTOFF_SHIFT (24U) /*! CUTOFF - Cutoff * 0b0000..div = 1 * 0b0001..div = 2 * 0b0010..div = 4 * 0b0011..div = 8 * 0b0100..div = 16 * 0b0101..div = 32 * 0b0110..div = 64 * 0b0111..div = 128 * 0b1000..Do not use * 0b1001..Do not use * 0b1010..Do not use * 0b1011..Do not use * 0b1100..Do not use * 0b1101..Do not use * 0b1110..Do not use * 0b1111..Do not use */ #define TSI_SINC_CUTOFF(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_CUTOFF_SHIFT)) & TSI_SINC_CUTOFF_MASK) /*! @} */ /*! @name SSC0 - TSI SSC 0 */ /*! @{ */ #define TSI_SSC0_SSC_PRESCALE_NUM_MASK (0xFFU) #define TSI_SSC0_SSC_PRESCALE_NUM_SHIFT (0U) /*! SSC_PRESCALE_NUM - SSC Prescale Number * 0b00000000..div = 1 * 0b00000001..div = 2 * 0b00000011..div = 4 * 0b00000111..div = 8 * 0b00001111..div = 16 * 0b00011111..div = 32 * 0b00111111..div = 64 * 0b01111111..div = 128 * 0b11111111..div = 256 */ #define TSI_SSC0_SSC_PRESCALE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_PRESCALE_NUM_SHIFT)) & TSI_SSC0_SSC_PRESCALE_NUM_MASK) #define TSI_SSC0_BASE_NOCHARGE_NUM_MASK (0xF0000U) #define TSI_SSC0_BASE_NOCHARGE_NUM_SHIFT (16U) /*! BASE_NOCHARGE_NUM - Base Nocharge Number * 0b0000..1 * 0b0001..2 * 0b0010..3 * 0b0011..4 * 0b0100..5 * 0b0101..6 * 0b0110..7 * 0b0111..8 * 0b1000..9 * 0b1001..10 * 0b1010..11 * 0b1011..12 * 0b1100..13 * 0b1101..14 * 0b1110..15 * 0b1111..16 */ #define TSI_SSC0_BASE_NOCHARGE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_BASE_NOCHARGE_NUM_SHIFT)) & TSI_SSC0_BASE_NOCHARGE_NUM_MASK) #define TSI_SSC0_CHARGE_NUM_MASK (0xF00000U) #define TSI_SSC0_CHARGE_NUM_SHIFT (20U) /*! CHARGE_NUM - Charge Number * 0b0000..1 * 0b0001..2 * 0b0010..3 * 0b0011..4 * 0b0100..5 * 0b0101..6 * 0b0110..7 * 0b0111..8 * 0b1000..9 * 0b1001..10 * 0b1010..11 * 0b1011..12 * 0b1100..13 * 0b1101..14 * 0b1110..15 * 0b1111..16 */ #define TSI_SSC0_CHARGE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_CHARGE_NUM_SHIFT)) & TSI_SSC0_CHARGE_NUM_MASK) #define TSI_SSC0_SSC_CONTROL_REVERSE_MASK (0x1000000U) #define TSI_SSC0_SSC_CONTROL_REVERSE_SHIFT (24U) /*! SSC_CONTROL_REVERSE - SSC Control Reverse * 0b0..Polarity retained * 0b1..Polarity reversed */ #define TSI_SSC0_SSC_CONTROL_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_CONTROL_REVERSE_SHIFT)) & TSI_SSC0_SSC_CONTROL_REVERSE_MASK) #define TSI_SSC0_SSC_MODE_MASK (0x6000000U) #define TSI_SSC0_SSC_MODE_SHIFT (25U) /*! SSC_MODE - SSC Mode * 0b00..PRBS mode * 0b01..Up-Down Counter mode * 0b10..Disables SSC function * 0b11..Do not use */ #define TSI_SSC0_SSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_MODE_SHIFT)) & TSI_SSC0_SSC_MODE_MASK) #define TSI_SSC0_PRBS_OUTSEL_MASK (0xF0000000U) #define TSI_SSC0_PRBS_OUTSEL_SHIFT (28U) /*! PRBS_OUTSEL - PRBS Output Selection * 0b0000..Do not use * 0b0001..Do not use * 0b0010..2 * 0b0011..3 * 0b0100..4 * 0b0101..5 * 0b0110..6 * 0b0111..7 * 0b1000..8 * 0b1001..9 * 0b1010..10 * 0b1011..11 * 0b1100..12 * 0b1101..13 * 0b1110..14 * 0b1111..15 */ #define TSI_SSC0_PRBS_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_PRBS_OUTSEL_SHIFT)) & TSI_SSC0_PRBS_OUTSEL_MASK) /*! @} */ /*! @name SSC1 - TSI SSC 1 */ /*! @{ */ #define TSI_SSC1_PRBS_SEED_LO_MASK (0xFFU) #define TSI_SSC1_PRBS_SEED_LO_SHIFT (0U) /*! PRBS_SEED_LO - PRBS Low Seed */ #define TSI_SSC1_PRBS_SEED_LO(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_SEED_LO_SHIFT)) & TSI_SSC1_PRBS_SEED_LO_MASK) #define TSI_SSC1_PRBS_SEED_HI_MASK (0xFF00U) #define TSI_SSC1_PRBS_SEED_HI_SHIFT (8U) /*! PRBS_SEED_HI - PRBS High Seed */ #define TSI_SSC1_PRBS_SEED_HI(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_SEED_HI_SHIFT)) & TSI_SSC1_PRBS_SEED_HI_MASK) #define TSI_SSC1_PRBS_WEIGHT_LO_MASK (0xFF0000U) #define TSI_SSC1_PRBS_WEIGHT_LO_SHIFT (16U) /*! PRBS_WEIGHT_LO - PRBS Low Weight */ #define TSI_SSC1_PRBS_WEIGHT_LO(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_WEIGHT_LO_SHIFT)) & TSI_SSC1_PRBS_WEIGHT_LO_MASK) #define TSI_SSC1_PRBS_WEIGHT_HI_MASK (0xFF000000U) #define TSI_SSC1_PRBS_WEIGHT_HI_SHIFT (24U) /*! PRBS_WEIGHT_HI - PRBS High Weight */ #define TSI_SSC1_PRBS_WEIGHT_HI(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_WEIGHT_HI_SHIFT)) & TSI_SSC1_PRBS_WEIGHT_HI_MASK) /*! @} */ /*! @name SSC2 - TSI SSC 2 */ /*! @{ */ #define TSI_SSC2_MOVE_REPEAT_NUM_MASK (0x1FU) #define TSI_SSC2_MOVE_REPEAT_NUM_SHIFT (0U) /*! MOVE_REPEAT_NUM - Move Repeat Number * 0b00000..1 * 0b00001..2 * 0b00010..3 * 0b00011..4 * 0b00100..5 * 0b00101..6 * 0b00110..7 */ #define TSI_SSC2_MOVE_REPEAT_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_REPEAT_NUM_SHIFT)) & TSI_SSC2_MOVE_REPEAT_NUM_MASK) #define TSI_SSC2_MOVE_STEPS_NUM_MASK (0x700U) #define TSI_SSC2_MOVE_STEPS_NUM_SHIFT (8U) /*! MOVE_STEPS_NUM - Move Steps Number * 0b000..0 * 0b001..1 * 0b010..2 * 0b011..3 * 0b100..4 * 0b101..5 * 0b110..6 * 0b111..7 */ #define TSI_SSC2_MOVE_STEPS_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_STEPS_NUM_SHIFT)) & TSI_SSC2_MOVE_STEPS_NUM_MASK) #define TSI_SSC2_MOVE_NOCHARGE_MAX_MASK (0x3F0000U) #define TSI_SSC2_MOVE_NOCHARGE_MAX_SHIFT (16U) /*! MOVE_NOCHARGE_MAX - Move Nocharge Maximum */ #define TSI_SSC2_MOVE_NOCHARGE_MAX(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_NOCHARGE_MAX_SHIFT)) & TSI_SSC2_MOVE_NOCHARGE_MAX_MASK) #define TSI_SSC2_MOVE_NOCHARGE_MIN_MASK (0xF0000000U) #define TSI_SSC2_MOVE_NOCHARGE_MIN_SHIFT (28U) /*! MOVE_NOCHARGE_MIN - Move Nocharge Minimum * 0b0000..(1 + SSC0[BASE_NOCHARGE_NUM]) * 0b0001..(2 + SSC0[BASE_NOCHARGE_NUM]) * 0b0010..(3 + SSC0[BASE_NOCHARGE_NUM]) * 0b0011..(4 + SSC0[BASE_NOCHARGE_NUM]) * 0b0100..(5 + SSC0[BASE_NOCHARGE_NUM]) * 0b0101..(6 + SSC0[BASE_NOCHARGE_NUM]) * 0b0110..(7 + SSC0[BASE_NOCHARGE_NUM]) * 0b0111..(8 + SSC0[BASE_NOCHARGE_NUM]) * 0b1000..(9 + SSC0[BASE_NOCHARGE_NUM]) * 0b1001..(10 + SSC0[BASE_NOCHARGE_NUM]) * 0b1010..(11 + SSC0[BASE_NOCHARGE_NUM]) * 0b1011..(12 + SSC0[BASE_NOCHARGE_NUM]) * 0b1100..(13 + SSC0[BASE_NOCHARGE_NUM]) * 0b1101..(14 + SSC0[BASE_NOCHARGE_NUM]) * 0b1110..(15 + SSC0[BASE_NOCHARGE_NUM]) * 0b1111..(16 + SSC0[BASE_NOCHARGE_NUM]) */ #define TSI_SSC2_MOVE_NOCHARGE_MIN(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_NOCHARGE_MIN_SHIFT)) & TSI_SSC2_MOVE_NOCHARGE_MIN_MASK) /*! @} */ /*! @name BASELINE - TSI Baseline */ /*! @{ */ #define TSI_BASELINE_BASELINE_MASK (0xFFFFU) #define TSI_BASELINE_BASELINE_SHIFT (0U) /*! BASELINE - Baseline */ #define TSI_BASELINE_BASELINE(x) (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_BASELINE_SHIFT)) & TSI_BASELINE_BASELINE_MASK) #define TSI_BASELINE_BASE_TRACE_DEBOUNCE_MASK (0xF0000U) #define TSI_BASELINE_BASE_TRACE_DEBOUNCE_SHIFT (16U) /*! BASE_TRACE_DEBOUNCE - Base Trace Debounce * 0b0000..0 * 0b0001..1 / 16 * 0b0010..2 / 16 * 0b0011..3 / 16 * 0b1xxx..n / 16 * 0b1111..15 / 16 */ #define TSI_BASELINE_BASE_TRACE_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_BASE_TRACE_DEBOUNCE_SHIFT)) & TSI_BASELINE_BASE_TRACE_DEBOUNCE_MASK) #define TSI_BASELINE_BASE_TRACE_EN_MASK (0x100000U) #define TSI_BASELINE_BASE_TRACE_EN_SHIFT (20U) /*! BASE_TRACE_EN - Baseline Trace Enable */ #define TSI_BASELINE_BASE_TRACE_EN(x) (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_BASE_TRACE_EN_SHIFT)) & TSI_BASELINE_BASE_TRACE_EN_MASK) #define TSI_BASELINE_THESHOLD_RATIO_MASK (0x70000000U) #define TSI_BASELINE_THESHOLD_RATIO_SHIFT (28U) /*! THESHOLD_RATIO - Threshold Ratio * 0b000..thresholdh = (baseline + counter) / 2 and thresholdl = (baseline - counter) / 2 * 0b001..thresholdh = (baseline + counter) / 4 and thresholdl = (baseline - counter) / 4 * 0b010..thresholdh = (baseline + counter) / 8 and thresholdl = (baseline - counter) / 8 * 0b011..thresholdh = (baseline + counter) / 16 and thresholdl = (baseline - counter) / 16 * 0b100..thresholdh = (baseline + counter) / 32 and thresholdl = (baseline - counter) / 32 * 0b101..thresholdh = (baseline + counter) / 64 and thresholdl = (baseline - counter) / 64 * 0b110..thresholdh = (baseline + counter) / 128 and thresholdl = (baseline - counter) / 128 * 0b111..thresholdh = (baseline + counter) / 256 and thresholdl = (baseline - counter) / 256 */ #define TSI_BASELINE_THESHOLD_RATIO(x) (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_THESHOLD_RATIO_SHIFT)) & TSI_BASELINE_THESHOLD_RATIO_MASK) #define TSI_BASELINE_THRESHOLD_TRACE_EN_MASK (0x80000000U) #define TSI_BASELINE_THRESHOLD_TRACE_EN_SHIFT (31U) /*! THRESHOLD_TRACE_EN - Threshold Trace Enable * 0b0..Disables * 0b1..Enables */ #define TSI_BASELINE_THRESHOLD_TRACE_EN(x) (((uint32_t)(((uint32_t)(x)) << TSI_BASELINE_THRESHOLD_TRACE_EN_SHIFT)) & TSI_BASELINE_THRESHOLD_TRACE_EN_MASK) /*! @} */ /*! @name CHMERGE - TSI Channel Merge */ /*! @{ */ #define TSI_CHMERGE_CHANNEL_ENABLE_MASK (0x1FFFFFFU) #define TSI_CHMERGE_CHANNEL_ENABLE_SHIFT (0U) /*! CHANNEL_ENABLE - Channel Enable * 0b0000000000000000000000000..Channel not chosen for proximity pad * 0b0000000000000000000000001..Channel chosen for proximity pad */ #define TSI_CHMERGE_CHANNEL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TSI_CHMERGE_CHANNEL_ENABLE_SHIFT)) & TSI_CHMERGE_CHANNEL_ENABLE_MASK) /*! @} */ /*! @name SHIELD - TSI Shield */ /*! @{ */ #define TSI_SHIELD_SHIELD_ENABLE_MASK (0xFU) #define TSI_SHIELD_SHIELD_ENABLE_SHIFT (0U) /*! SHIELD_ENABLE - Shield Enable * 0b0000..Disables * 0b0001..Enables */ #define TSI_SHIELD_SHIELD_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SHIELD_SHIELD_ENABLE_SHIFT)) & TSI_SHIELD_SHIELD_ENABLE_MASK) #define TSI_SHIELD_M_SEN_RES_MASK (0x7E000000U) #define TSI_SHIELD_M_SEN_RES_SHIFT (25U) /*! M_SEN_RES - Mutual-Capacitance Sensitivity Resistor * 0b000000..10 kΩ * 0b000001..10 kΩ + (2.5 / 3) kΩ (just for auto-calibration) * 0b000010..12.5 kΩ (default) * 0b001110..25 kΩ */ #define TSI_SHIELD_M_SEN_RES(x) (((uint32_t)(((uint32_t)(x)) << TSI_SHIELD_M_SEN_RES_SHIFT)) & TSI_SHIELD_M_SEN_RES_MASK) /*! @} */ /*! @name DATA - TSI Data and Status */ /*! @{ */ #define TSI_DATA_TSICNT_MASK (0xFFFFU) #define TSI_DATA_TSICNT_SHIFT (0U) /*! TSICNT - TSI Conversion Counter Value */ #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK) #define TSI_DATA_EOSF_MASK (0x8000000U) #define TSI_DATA_EOSF_SHIFT (27U) /*! EOSF - End-of-Scan Flag */ #define TSI_DATA_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_EOSF_SHIFT)) & TSI_DATA_EOSF_MASK) #define TSI_DATA_OVERRUNF_MASK (0x20000000U) #define TSI_DATA_OVERRUNF_SHIFT (29U) /*! OVERRUNF - Overrun Flag * 0b0..No * 0b1..Yes */ #define TSI_DATA_OVERRUNF(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_OVERRUNF_SHIFT)) & TSI_DATA_OVERRUNF_MASK) #define TSI_DATA_OUTRGF_MASK (0x40000000U) #define TSI_DATA_OUTRGF_SHIFT (30U) /*! OUTRGF - Out-of-Range Flag */ #define TSI_DATA_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_OUTRGF_SHIFT)) & TSI_DATA_OUTRGF_MASK) /*! @} */ /*! @name MISC - TSI Miscellaneous */ /*! @{ */ #define TSI_MISC_OSC_CLK_SEL_MASK (0x80000U) #define TSI_MISC_OSC_CLK_SEL_SHIFT (19U) /*! OSC_CLK_SEL - Oscillator Clock Select * 0b0..Analog oscillator * 0b1..Chip */ #define TSI_MISC_OSC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << TSI_MISC_OSC_CLK_SEL_SHIFT)) & TSI_MISC_OSC_CLK_SEL_MASK) #define TSI_MISC_TEST_FINGER_MASK (0x700000U) #define TSI_MISC_TEST_FINGER_SHIFT (20U) /*! TEST_FINGER - Test Finger * 0b000..Finger capacitor is 148 pF * 0b001..Finger capacitor is 296 pF * 0b010..Finger capacitor is 444 pF * 0b011..Finger capacitor is 592 pF * 0b100..Finger capacitor is 740 pF * 0b101..Finger capacitor is 888 pF * 0b110..Finger capacitor is 1036 pF * 0b111..Finger capacitor is 1184 pF */ #define TSI_MISC_TEST_FINGER(x) (((uint32_t)(((uint32_t)(x)) << TSI_MISC_TEST_FINGER_SHIFT)) & TSI_MISC_TEST_FINGER_MASK) #define TSI_MISC_TEST_FINGER_EN_MASK (0x800000U) #define TSI_MISC_TEST_FINGER_EN_SHIFT (23U) /*! TEST_FINGER_EN - Test Finger Function Enable Signals * 0b0..Disables * 0b1..Enables */ #define TSI_MISC_TEST_FINGER_EN(x) (((uint32_t)(((uint32_t)(x)) << TSI_MISC_TEST_FINGER_EN_SHIFT)) & TSI_MISC_TEST_FINGER_EN_MASK) #define TSI_MISC_CLKDIVIDER_MASK (0x1F000000U) #define TSI_MISC_CLKDIVIDER_SHIFT (24U) /*! CLKDIVIDER - TSI Clock Divider */ #define TSI_MISC_CLKDIVIDER(x) (((uint32_t)(((uint32_t)(x)) << TSI_MISC_CLKDIVIDER_SHIFT)) & TSI_MISC_CLKDIVIDER_MASK) /*! @} */ /*! @name TRIG - TSI AUTO TRIG */ /*! @{ */ #define TSI_TRIG_TRIG_PERIOD_COUNTER_MASK (0xFFFFFU) #define TSI_TRIG_TRIG_PERIOD_COUNTER_SHIFT (0U) /*! TRIG_PERIOD_COUNTER - Trigger Period Counter */ #define TSI_TRIG_TRIG_PERIOD_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << TSI_TRIG_TRIG_PERIOD_COUNTER_SHIFT)) & TSI_TRIG_TRIG_PERIOD_COUNTER_MASK) #define TSI_TRIG_TRIG_CLK_DIVIDER_MASK (0x1F000000U) #define TSI_TRIG_TRIG_CLK_DIVIDER_SHIFT (24U) /*! TRIG_CLK_DIVIDER - Trigger Clock Divider * 0b00000..No divider * 0b00001..Divided by 2 * 0b00010..Divided by 3 * 0b00011..Divided by 4 * 0b1xxxx..Divided by n */ #define TSI_TRIG_TRIG_CLK_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << TSI_TRIG_TRIG_CLK_DIVIDER_SHIFT)) & TSI_TRIG_TRIG_CLK_DIVIDER_MASK) #define TSI_TRIG_TRIG_EN_MASK (0x40000000U) #define TSI_TRIG_TRIG_EN_SHIFT (30U) /*! TRIG_EN - Trigger Enable * 0b0..Disabled * 0b1..Enabled */ #define TSI_TRIG_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSI_TRIG_TRIG_EN_SHIFT)) & TSI_TRIG_TRIG_EN_MASK) #define TSI_TRIG_TRIG_CLK_SEL_MASK (0x80000000U) #define TSI_TRIG_TRIG_CLK_SEL_SHIFT (31U) /*! TRIG_CLK_SEL - Trigger Clock Select * 0b0..32 k clock * 0b1..clksoc */ #define TSI_TRIG_TRIG_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TRIG_TRIG_CLK_SEL_SHIFT)) & TSI_TRIG_TRIG_CLK_SEL_MASK) /*! @} */ /*! * @} */ /* end of group TSI_Register_Masks */ /* TSI - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral TSI0 base address */ #define TSI0_BASE (0x50050000u) /** Peripheral TSI0 base address */ #define TSI0_BASE_NS (0x40050000u) /** Peripheral TSI0 base pointer */ #define TSI0 ((TSI_Type *)TSI0_BASE) /** Peripheral TSI0 base pointer */ #define TSI0_NS ((TSI_Type *)TSI0_BASE_NS) /** Array initializer of TSI peripheral base addresses */ #define TSI_BASE_ADDRS { TSI0_BASE } /** Array initializer of TSI peripheral base pointers */ #define TSI_BASE_PTRS { TSI0 } /** Array initializer of TSI peripheral base addresses */ #define TSI_BASE_ADDRS_NS { TSI0_BASE_NS } /** Array initializer of TSI peripheral base pointers */ #define TSI_BASE_PTRS_NS { TSI0_NS } #else /** Peripheral TSI0 base address */ #define TSI0_BASE (0x40050000u) /** Peripheral TSI0 base pointer */ #define TSI0 ((TSI_Type *)TSI0_BASE) /** Array initializer of TSI peripheral base addresses */ #define TSI_BASE_ADDRS { TSI0_BASE } /** Array initializer of TSI peripheral base pointers */ #define TSI_BASE_PTRS { TSI0 } #endif /*! * @} */ /* end of group TSI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer * @{ */ /** USB - Register Layout Typedef */ typedef struct { __I uint8_t PERID; /**< Peripheral ID, offset: 0x0 */ uint8_t RESERVED_0[3]; __I uint8_t IDCOMP; /**< Peripheral ID Complement, offset: 0x4 */ uint8_t RESERVED_1[3]; __I uint8_t REV; /**< Peripheral Revision, offset: 0x8 */ uint8_t RESERVED_2[3]; __I uint8_t ADDINFO; /**< Peripheral Additional Information, offset: 0xC */ uint8_t RESERVED_3[3]; __IO uint8_t OTGISTAT; /**< OTG Interrupt Status, offset: 0x10 */ uint8_t RESERVED_4[3]; __IO uint8_t OTGICR; /**< OTG Interrupt Control, offset: 0x14 */ uint8_t RESERVED_5[3]; __I uint8_t OTGSTAT; /**< OTG Status, offset: 0x18 */ uint8_t RESERVED_6[3]; __IO uint8_t OTGCTL; /**< OTG Control, offset: 0x1C */ uint8_t RESERVED_7[99]; __IO uint8_t ISTAT; /**< Interrupt Status, offset: 0x80 */ uint8_t RESERVED_8[3]; __IO uint8_t INTEN; /**< Interrupt Enable, offset: 0x84 */ uint8_t RESERVED_9[3]; __IO uint8_t ERRSTAT; /**< Error Interrupt Status, offset: 0x88 */ uint8_t RESERVED_10[3]; __IO uint8_t ERREN; /**< Error Interrupt Enable, offset: 0x8C */ uint8_t RESERVED_11[3]; __I uint8_t STAT; /**< Status, offset: 0x90 */ uint8_t RESERVED_12[3]; __IO uint8_t CTL; /**< Control, offset: 0x94 */ uint8_t RESERVED_13[3]; __IO uint8_t ADDR; /**< Address, offset: 0x98 */ uint8_t RESERVED_14[3]; __IO uint8_t BDTPAGE1; /**< BDT Page 1, offset: 0x9C */ uint8_t RESERVED_15[3]; __I uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ uint8_t RESERVED_16[3]; __I uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ uint8_t RESERVED_17[3]; __IO uint8_t TOKEN; /**< Token, offset: 0xA8 */ uint8_t RESERVED_18[3]; __IO uint8_t SOFTHLD; /**< SOF Threshold, offset: 0xAC */ uint8_t RESERVED_19[3]; __IO uint8_t BDTPAGE2; /**< BDT Page 2, offset: 0xB0 */ uint8_t RESERVED_20[3]; __IO uint8_t BDTPAGE3; /**< BDT Page 3, offset: 0xB4 */ uint8_t RESERVED_21[11]; struct { /* offset: 0xC0, array step: 0x4 */ __IO uint8_t ENDPT; /**< Endpoint Control, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_0[3]; } ENDPOINT[16]; __IO uint8_t USBCTRL; /**< USB Control, offset: 0x100 */ uint8_t RESERVED_22[3]; __I uint8_t OBSERVE; /**< USB OTG Observe, offset: 0x104 */ uint8_t RESERVED_23[3]; __IO uint8_t CONTROL; /**< USB OTG Control, offset: 0x108 */ uint8_t RESERVED_24[3]; __IO uint8_t USBTRC0; /**< USB Transceiver Control 0, offset: 0x10C */ uint8_t RESERVED_25[7]; __IO uint8_t USBFRMADJUST; /**< Frame Adjust, offset: 0x114 */ uint8_t RESERVED_26[15]; __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive Mode Control, offset: 0x124 */ uint8_t RESERVED_27[3]; __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive Mode Wakeup Control, offset: 0x128 */ uint8_t RESERVED_28[3]; __IO uint8_t MISCCTRL; /**< Miscellaneous Control, offset: 0x12C */ uint8_t RESERVED_29[3]; __IO uint8_t STALL_IL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction, offset: 0x130 */ uint8_t RESERVED_30[3]; __IO uint8_t STALL_IH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction, offset: 0x134 */ uint8_t RESERVED_31[3]; __IO uint8_t STALL_OL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction, offset: 0x138 */ uint8_t RESERVED_32[3]; __IO uint8_t STALL_OH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction, offset: 0x13C */ uint8_t RESERVED_33[3]; __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock Recovery Control, offset: 0x140 */ uint8_t RESERVED_34[3]; __IO uint8_t CLK_RECOVER_IRC_EN; /**< FIRC Oscillator Enable, offset: 0x144 */ uint8_t RESERVED_35[15]; __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock Recovery Combined Interrupt Enable, offset: 0x154 */ uint8_t RESERVED_36[7]; __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock Recovery Separated Interrupt Status, offset: 0x15C */ } USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /*! @name PERID - Peripheral ID */ /*! @{ */ #define USB_PERID_ID_MASK (0x3FU) #define USB_PERID_ID_SHIFT (0U) /*! ID - Peripheral Identification */ #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) /*! @} */ /*! @name IDCOMP - Peripheral ID Complement */ /*! @{ */ #define USB_IDCOMP_NID_MASK (0x3FU) #define USB_IDCOMP_NID_SHIFT (0U) /*! NID - Negative Peripheral ID */ #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) /*! @} */ /*! @name REV - Peripheral Revision */ /*! @{ */ #define USB_REV_REV_MASK (0xFFU) #define USB_REV_REV_SHIFT (0U) /*! REV - Revision */ #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) /*! @} */ /*! @name ADDINFO - Peripheral Additional Information */ /*! @{ */ #define USB_ADDINFO_IEHOST_MASK (0x1U) #define USB_ADDINFO_IEHOST_SHIFT (0U) /*! IEHOST - Host Mode Enable * 0b0..Disabled * 0b1..Enabled */ #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) /*! @} */ /*! @name OTGISTAT - OTG Interrupt Status */ /*! @{ */ #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) /*! LINE_STATE_CHG - Line State Change Interrupt Flag * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) #define USB_OTGISTAT_ONEMSEC_MASK (0x40U) #define USB_OTGISTAT_ONEMSEC_SHIFT (6U) /*! ONEMSEC - One Millisecond Timer Timeout Flag * 0b0..Not timed out * 0b1..Timed out * 0b0..No effect * 0b1..Clear the flag */ #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) /*! @} */ /*! @name OTGICR - OTG Interrupt Control */ /*! @{ */ #define USB_OTGICR_LINESTATEEN_MASK (0x20U) #define USB_OTGICR_LINESTATEEN_SHIFT (5U) /*! LINESTATEEN - Line State Change Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) #define USB_OTGICR_ONEMSECEN_MASK (0x40U) #define USB_OTGICR_ONEMSECEN_SHIFT (6U) /*! ONEMSECEN - 1-Millisecond Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) /*! @} */ /*! @name OTGSTAT - OTG Status */ /*! @{ */ #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) /*! LINESTATESTABLE - Line State Stable * 0b0..Unstable * 0b1..Stable */ #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) #define USB_OTGSTAT_ONEMSEC_MASK (0x40U) #define USB_OTGSTAT_ONEMSEC_SHIFT (6U) /*! ONEMSEC - Reserved for 1 ms count */ #define USB_OTGSTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSEC_SHIFT)) & USB_OTGSTAT_ONEMSEC_MASK) /*! @} */ /*! @name OTGCTL - OTG Control */ /*! @{ */ #define USB_OTGCTL_OTGEN_MASK (0x4U) #define USB_OTGCTL_OTGEN_SHIFT (2U) /*! OTGEN - On-The-Go Pullup and Pulldown Resistor Enable * 0b0..If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup * resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged. * 0b1..Uses the pullup and pulldown controls in this register. */ #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) #define USB_OTGCTL_DMLOW_MASK (0x10U) #define USB_OTGCTL_DMLOW_SHIFT (4U) /*! DMLOW - D- Data Line Pulldown Resistor Enable * 0b0..Disable * 0b1..Enable */ #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) #define USB_OTGCTL_DPLOW_MASK (0x20U) #define USB_OTGCTL_DPLOW_SHIFT (5U) /*! DPLOW - D+ Data Line pulldown Resistor Enable * 0b0..Disable * 0b1..Enable */ #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) #define USB_OTGCTL_DPHIGH_MASK (0x80U) #define USB_OTGCTL_DPHIGH_SHIFT (7U) /*! DPHIGH - D+ Data Line Pullup Resistor Enable * 0b0..Disable * 0b1..Enable */ #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) /*! @} */ /*! @name ISTAT - Interrupt Status */ /*! @{ */ #define USB_ISTAT_USBRST_MASK (0x1U) #define USB_ISTAT_USBRST_SHIFT (0U) /*! USBRST - USB Reset Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) #define USB_ISTAT_ERROR_MASK (0x2U) #define USB_ISTAT_ERROR_SHIFT (1U) /*! ERROR - Error Flag * 0b0..Error did not occur * 0b1..Error occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) #define USB_ISTAT_SOFTOK_MASK (0x4U) #define USB_ISTAT_SOFTOK_SHIFT (2U) /*! SOFTOK - Start Of Frame (SOF) Token Flag * 0b0..Did not receive * 0b1..Received * 0b0..No effect * 0b1..Clear the flag */ #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) #define USB_ISTAT_TOKDNE_MASK (0x8U) #define USB_ISTAT_TOKDNE_SHIFT (3U) /*! TOKDNE - Current Token Processing Flag * 0b0..Not processed * 0b1..Processed * 0b0..No effect * 0b1..Clear the flag */ #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) #define USB_ISTAT_SLEEP_MASK (0x10U) #define USB_ISTAT_SLEEP_SHIFT (4U) /*! SLEEP - Sleep Flag * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) #define USB_ISTAT_RESUME_MASK (0x20U) #define USB_ISTAT_RESUME_SHIFT (5U) /*! RESUME - Resume Flag * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) #define USB_ISTAT_ATTACH_MASK (0x40U) #define USB_ISTAT_ATTACH_SHIFT (6U) /*! ATTACH - Attach Interrupt Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) #define USB_ISTAT_STALL_MASK (0x80U) #define USB_ISTAT_STALL_SHIFT (7U) /*! STALL - Stall Interrupt Flag * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable */ /*! @{ */ #define USB_INTEN_USBRSTEN_MASK (0x1U) #define USB_INTEN_USBRSTEN_SHIFT (0U) /*! USBRSTEN - USBRST Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) #define USB_INTEN_ERROREN_MASK (0x2U) #define USB_INTEN_ERROREN_SHIFT (1U) /*! ERROREN - ERROR Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) #define USB_INTEN_SOFTOKEN_MASK (0x4U) #define USB_INTEN_SOFTOKEN_SHIFT (2U) /*! SOFTOKEN - SOFTOK Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) #define USB_INTEN_TOKDNEEN_MASK (0x8U) #define USB_INTEN_TOKDNEEN_SHIFT (3U) /*! TOKDNEEN - TOKDNE Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) #define USB_INTEN_SLEEPEN_MASK (0x10U) #define USB_INTEN_SLEEPEN_SHIFT (4U) /*! SLEEPEN - SLEEP Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) #define USB_INTEN_RESUMEEN_MASK (0x20U) #define USB_INTEN_RESUMEEN_SHIFT (5U) /*! RESUMEEN - RESUME Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) #define USB_INTEN_ATTACHEN_MASK (0x40U) #define USB_INTEN_ATTACHEN_SHIFT (6U) /*! ATTACHEN - ATTACH Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) #define USB_INTEN_STALLEN_MASK (0x80U) #define USB_INTEN_STALLEN_SHIFT (7U) /*! STALLEN - STALL Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) /*! @} */ /*! @name ERRSTAT - Error Interrupt Status */ /*! @{ */ #define USB_ERRSTAT_PIDERR_MASK (0x1U) #define USB_ERRSTAT_PIDERR_SHIFT (0U) /*! PIDERR - PID Error Flag * 0b0..Did not fail * 0b1..Failed * 0b0..No effect * 0b1..Clear the flag */ #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) #define USB_ERRSTAT_CRC5EOF_MASK (0x2U) #define USB_ERRSTAT_CRC5EOF_SHIFT (1U) /*! CRC5EOF - CRC5 Error or End of Frame Error Flag * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) #define USB_ERRSTAT_CRC16_MASK (0x4U) #define USB_ERRSTAT_CRC16_SHIFT (2U) /*! CRC16 - CRC16 Error Flag * 0b0..Not rejected * 0b1..Rejected * 0b0..No effect * 0b1..Clear the flag */ #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) #define USB_ERRSTAT_DFN8_MASK (0x8U) #define USB_ERRSTAT_DFN8_SHIFT (3U) /*! DFN8 - Data Field Not 8 Bits Flag * 0b0..Integer number of bytes * 0b1..Not an integer number of bytes * 0b0..No effect * 0b1..Clear the flag */ #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) #define USB_ERRSTAT_BTOERR_MASK (0x10U) #define USB_ERRSTAT_BTOERR_SHIFT (4U) /*! BTOERR - Bus Turnaround Timeout Error Flag * 0b0..Not timed out * 0b1..Timed out * 0b0..No effect * 0b1..Clear the flag */ #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) #define USB_ERRSTAT_DMAERR_MASK (0x20U) #define USB_ERRSTAT_DMAERR_SHIFT (5U) /*! DMAERR - DMA Access Error Flag * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) #define USB_ERRSTAT_OWNERR_MASK (0x40U) #define USB_ERRSTAT_OWNERR_SHIFT (6U) /*! OWNERR - BD Unavailable Error Flag * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) #define USB_ERRSTAT_BTSERR_MASK (0x80U) #define USB_ERRSTAT_BTSERR_SHIFT (7U) /*! BTSERR - Bit Stuff Error Flag * 0b0..Packet not rejected due to the error * 0b1..Packet rejected due to the error * 0b0..No effect * 0b1..Clear the flag */ #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) /*! @} */ /*! @name ERREN - Error Interrupt Enable */ /*! @{ */ #define USB_ERREN_PIDERREN_MASK (0x1U) #define USB_ERREN_PIDERREN_SHIFT (0U) /*! PIDERREN - PIDERR Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) #define USB_ERREN_CRC5EOFEN_MASK (0x2U) #define USB_ERREN_CRC5EOFEN_SHIFT (1U) /*! CRC5EOFEN - CRC5/EOF Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) #define USB_ERREN_CRC16EN_MASK (0x4U) #define USB_ERREN_CRC16EN_SHIFT (2U) /*! CRC16EN - CRC16 Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) #define USB_ERREN_DFN8EN_MASK (0x8U) #define USB_ERREN_DFN8EN_SHIFT (3U) /*! DFN8EN - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) #define USB_ERREN_BTOERREN_MASK (0x10U) #define USB_ERREN_BTOERREN_SHIFT (4U) /*! BTOERREN - BTOERR (Bus Timeout Error) Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) #define USB_ERREN_DMAERREN_MASK (0x20U) #define USB_ERREN_DMAERREN_SHIFT (5U) /*! DMAERREN - DMAERR Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) #define USB_ERREN_OWNERREN_MASK (0x40U) #define USB_ERREN_OWNERREN_SHIFT (6U) /*! OWNERREN - OWNERR Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) #define USB_ERREN_BTSERREN_MASK (0x80U) #define USB_ERREN_BTSERREN_SHIFT (7U) /*! BTSERREN - BTSERR (Bit Stuff Error) Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) /*! @} */ /*! @name STAT - Status */ /*! @{ */ #define USB_STAT_ODD_MASK (0x4U) #define USB_STAT_ODD_SHIFT (2U) /*! ODD - Odd Bank * 0b0..Not in the odd bank * 0b1..In the odd bank */ #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) #define USB_STAT_TX_MASK (0x8U) #define USB_STAT_TX_SHIFT (3U) /*! TX - Transmit Indicator * 0b0..Receive * 0b1..Transmit */ #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) #define USB_STAT_ENDP_MASK (0xF0U) #define USB_STAT_ENDP_SHIFT (4U) /*! ENDP - Endpoint address */ #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) /*! @} */ /*! @name CTL - Control */ /*! @{ */ #define USB_CTL_USBENSOFEN_MASK (0x1U) #define USB_CTL_USBENSOFEN_SHIFT (0U) /*! USBENSOFEN - USB Enable * 0b0..Disable * 0b1..Enable */ #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) #define USB_CTL_ODDRST_MASK (0x2U) #define USB_CTL_ODDRST_SHIFT (1U) /*! ODDRST - Odd Reset */ #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) #define USB_CTL_RESUME_MASK (0x4U) #define USB_CTL_RESUME_SHIFT (2U) /*! RESUME - Resume */ #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) #define USB_CTL_HOSTMODEEN_MASK (0x8U) #define USB_CTL_HOSTMODEEN_SHIFT (3U) /*! HOSTMODEEN - Host Mode Enable * 0b0..USBFS operates in Device mode. * 0b1..USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor. */ #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) #define USB_CTL_RESET_MASK (0x10U) #define USB_CTL_RESET_SHIFT (4U) /*! RESET - Reset Signaling Enable * 0b0..Disable * 0b1..Enable */ #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) /*! TXSUSPENDTOKENBUSY - TXD Suspend And Token Busy */ #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) #define USB_CTL_SE0_MASK (0x40U) #define USB_CTL_SE0_SHIFT (6U) /*! SE0 - Live USB Single-Ended Zero signal */ #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) #define USB_CTL_JSTATE_MASK (0x80U) #define USB_CTL_JSTATE_SHIFT (7U) /*! JSTATE - Live USB Differential Receiver JSTATE Signal */ #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) /*! @} */ /*! @name ADDR - Address */ /*! @{ */ #define USB_ADDR_ADDR_MASK (0x7FU) #define USB_ADDR_ADDR_SHIFT (0U) /*! ADDR - USB Address */ #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) #define USB_ADDR_LSEN_MASK (0x80U) #define USB_ADDR_LSEN_SHIFT (7U) /*! LSEN - Low Speed Enable */ #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) /*! @} */ /*! @name BDTPAGE1 - BDT Page 1 */ /*! @{ */ #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) #define USB_BDTPAGE1_BDTBA_SHIFT (1U) /*! BDTBA - BDT Base Address */ #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) /*! @} */ /*! @name FRMNUML - Frame Number Register Low */ /*! @{ */ #define USB_FRMNUML_FRM_MASK (0xFFU) #define USB_FRMNUML_FRM_SHIFT (0U) /*! FRM - Frame Number, Bits 0-7 */ #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) /*! @} */ /*! @name FRMNUMH - Frame Number Register High */ /*! @{ */ #define USB_FRMNUMH_FRM_MASK (0x7U) #define USB_FRMNUMH_FRM_SHIFT (0U) /*! FRM - Frame Number, Bits 8-10 */ #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) /*! @} */ /*! @name TOKEN - Token */ /*! @{ */ #define USB_TOKEN_TOKENENDPT_MASK (0xFU) #define USB_TOKEN_TOKENENDPT_SHIFT (0U) /*! TOKENENDPT - Token Endpoint Address */ #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) #define USB_TOKEN_TOKENPID_MASK (0xF0U) #define USB_TOKEN_TOKENPID_SHIFT (4U) /*! TOKENPID - Token Type * 0b0001..OUT token. USBFS performs an OUT (TX) transaction. * 0b1001..IN token. USBFS performs an IN (RX) transaction. * 0b1101..SETUP token. USBFS performs a SETUP (TX) transaction */ #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) /*! @} */ /*! @name SOFTHLD - SOF Threshold */ /*! @{ */ #define USB_SOFTHLD_CNT_MASK (0xFFU) #define USB_SOFTHLD_CNT_SHIFT (0U) /*! CNT - SOF Count Threshold */ #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) /*! @} */ /*! @name BDTPAGE2 - BDT Page 2 */ /*! @{ */ #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) #define USB_BDTPAGE2_BDTBA_SHIFT (0U) /*! BDTBA - BDT Base Address */ #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) /*! @} */ /*! @name BDTPAGE3 - BDT Page 3 */ /*! @{ */ #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) #define USB_BDTPAGE3_BDTBA_SHIFT (0U) /*! BDTBA - BDT Base Address */ #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) /*! @} */ /*! @name ENDPT - Endpoint Control */ /*! @{ */ #define USB_ENDPT_EPHSHK_MASK (0x1U) #define USB_ENDPT_EPHSHK_SHIFT (0U) /*! EPHSHK - Endpoint Handshaking Enable */ #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) #define USB_ENDPT_EPSTALL_MASK (0x2U) #define USB_ENDPT_EPSTALL_SHIFT (1U) /*! EPSTALL - Endpoint Stalled */ #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) #define USB_ENDPT_EPTXEN_MASK (0x4U) #define USB_ENDPT_EPTXEN_SHIFT (2U) /*! EPTXEN - Endpoint for TX transfers enable */ #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) #define USB_ENDPT_EPRXEN_MASK (0x8U) #define USB_ENDPT_EPRXEN_SHIFT (3U) /*! EPRXEN - Endpoint for RX transfers enable */ #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) #define USB_ENDPT_EPCTLDIS_MASK (0x10U) #define USB_ENDPT_EPCTLDIS_SHIFT (4U) /*! EPCTLDIS - Control Transfer Disable * 0b0..Enable * 0b1..Disable */ #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) #define USB_ENDPT_RETRYDIS_MASK (0x40U) #define USB_ENDPT_RETRYDIS_SHIFT (6U) /*! RETRYDIS - Retry Disable * 0b0..Retried NAK'ed transactions in hardware. * 0b1..Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK * PID, and the TOKEN_DNE interrupt becomes 1. */ #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) /*! HOSTWOHUB - Host Without A Hub * 0b0..Connected using a hub (USBFS generates PRE_PID as required) * 0b1..Connected directly to host without a hub, or was used to attach */ #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) /*! @} */ /* The count of USB_ENDPT */ #define USB_ENDPT_COUNT (16U) /*! @name USBCTRL - USB Control */ /*! @{ */ #define USB_USBCTRL_DPDM_LANE_REVERSE_MASK (0x4U) #define USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT (2U) /*! DPDM_LANE_REVERSE - DP and DM Lane Reversal Control * 0b0..Standard USB DP and DM package pin assignment * 0b1..Reverse roles of USB DP and DM package pins */ #define USB_USBCTRL_DPDM_LANE_REVERSE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT)) & USB_USBCTRL_DPDM_LANE_REVERSE_MASK) #define USB_USBCTRL_HOST_LS_EOP_MASK (0x8U) #define USB_USBCTRL_HOST_LS_EOP_SHIFT (3U) /*! HOST_LS_EOP - Host-Mode-Only Low-Speed Device EOP Signaling * 0b0..Full-speed device or a low-speed device through a hub * 0b1..Directly-connected low-speed device */ #define USB_USBCTRL_HOST_LS_EOP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_HOST_LS_EOP_SHIFT)) & USB_USBCTRL_HOST_LS_EOP_MASK) #define USB_USBCTRL_UARTSEL_MASK (0x10U) #define USB_USBCTRL_UARTSEL_SHIFT (4U) /*! UARTSEL - UART Select * 0b0..USB DP and DM external package pins are used for USB signaling. * 0b1..USB DP and DM external package pins are used for UART signaling. */ #define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) #define USB_USBCTRL_UARTCHLS_MASK (0x20U) #define USB_USBCTRL_UARTCHLS_SHIFT (5U) /*! UARTCHLS - UART Signal Channel Select * 0b0..USB DP and DM signals are used as UART TX/RX. * 0b1..USB DP and DM signals are used as UART RX/TX. */ #define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) #define USB_USBCTRL_PDE_MASK (0x40U) #define USB_USBCTRL_PDE_SHIFT (6U) /*! PDE - Pulldown Enable * 0b0..Disable on D+ and D- * 0b1..Enable on D+ and D- */ #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) #define USB_USBCTRL_SUSP_MASK (0x80U) #define USB_USBCTRL_SUSP_SHIFT (7U) /*! SUSP - Suspend * 0b0..Not in Suspend state * 0b1..In Suspend state */ #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) /*! @} */ /*! @name OBSERVE - USB OTG Observe */ /*! @{ */ #define USB_OBSERVE_DMPD_MASK (0x10U) #define USB_OBSERVE_DMPD_SHIFT (4U) /*! DMPD - D- Pulldown * 0b0..Disabled * 0b1..Enabled */ #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) #define USB_OBSERVE_DPPD_MASK (0x40U) #define USB_OBSERVE_DPPD_SHIFT (6U) /*! DPPD - D+ Pulldown * 0b0..Disabled * 0b1..Enabled */ #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) #define USB_OBSERVE_DPPU_MASK (0x80U) #define USB_OBSERVE_DPPU_SHIFT (7U) /*! DPPU - D+ Pullup * 0b0..Disabled * 0b1..Enabled */ #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) /*! @} */ /*! @name CONTROL - USB OTG Control */ /*! @{ */ #define USB_CONTROL_VBUS_SOURCE_SEL_MASK (0x1U) #define USB_CONTROL_VBUS_SOURCE_SEL_SHIFT (0U) /*! VBUS_SOURCE_SEL - VBUS Monitoring Source Select * 0b0..Reserved * 0b1..Resistive divider attached to a GPIO pin */ #define USB_CONTROL_VBUS_SOURCE_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_VBUS_SOURCE_SEL_SHIFT)) & USB_CONTROL_VBUS_SOURCE_SEL_MASK) #define USB_CONTROL_SESS_VLD_MASK (0x2U) #define USB_CONTROL_SESS_VLD_SHIFT (1U) /*! SESS_VLD - VBUS Session Valid status * 0b1..Above * 0b0..Below */ #define USB_CONTROL_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_SESS_VLD_SHIFT)) & USB_CONTROL_SESS_VLD_MASK) #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) /*! DPPULLUPNONOTG - DP Pullup in Non-OTG Device Mode * 0b0..Disable * 0b1..Enabled */ #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) /*! @} */ /*! @name USBTRC0 - USB Transceiver Control 0 */ /*! @{ */ #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) /*! USB_RESUME_INT - USB Asynchronous Interrupt * 0b0..Not generated * 0b1..Generated because of the USB asynchronous interrupt */ #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) #define USB_USBTRC0_SYNC_DET_MASK (0x2U) #define USB_USBTRC0_SYNC_DET_SHIFT (1U) /*! SYNC_DET - Synchronous USB Interrupt Detect * 0b0..Not detected * 0b1..Detected */ #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) /*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */ #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) #define USB_USBTRC0_VREDG_DET_MASK (0x8U) #define USB_USBTRC0_VREDG_DET_SHIFT (3U) /*! VREDG_DET - VREGIN Rising Edge Interrupt Detect * 0b0..Not detected * 0b1..Detected */ #define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) #define USB_USBTRC0_VFEDG_DET_MASK (0x10U) #define USB_USBTRC0_VFEDG_DET_SHIFT (4U) /*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect * 0b0..Not detected * 0b1..Detected */ #define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) #define USB_USBTRC0_USBRESMEN_MASK (0x20U) #define USB_USBTRC0_USBRESMEN_SHIFT (5U) /*! USBRESMEN - Asynchronous Resume Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) #define USB_USBTRC0_VREGIN_STS_MASK (0x40U) #define USB_USBTRC0_VREGIN_STS_SHIFT (6U) /*! VREGIN_STS - VREGIN Status */ #define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK) #define USB_USBTRC0_USBRESET_MASK (0x80U) #define USB_USBTRC0_USBRESET_SHIFT (7U) /*! USBRESET - USB Reset * 0b0..Normal USBFS operation * 0b1..Returns USBFS to its reset state */ #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) /*! @} */ /*! @name USBFRMADJUST - Frame Adjust */ /*! @{ */ #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) #define USB_USBFRMADJUST_ADJ_SHIFT (0U) /*! ADJ - Frame Adjustment */ #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) /*! @} */ /*! @name KEEP_ALIVE_CTRL - Keep Alive Mode Control */ /*! @{ */ #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) /*! KEEP_ALIVE_EN - Keep Alive Mode Enable * 0b0..Everything remains same as before. * 0b1..USB shall enter USB_KEEP_ALIVE mode after asserting ipg_stop. */ #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) /*! OWN_OVERRD_EN - OWN Bit Override Enable */ #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U) #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U) /*! STOP_ACK_DLY_EN - Stop Acknowledge Delay Enable * 0b0..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer. * 0b1..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer. */ #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK) #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK (0x8U) #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT (3U) /*! WAKE_REQ_EN - Wakeup Request Enable * 0b0..Disable * 0b1..Enable */ #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) /*! WAKE_INT_EN - Wakeup Interrupt Enable */ #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK (0x40U) #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U) /*! KEEP_ALIVE_STS - Keep Alive Status * 0b0..Not in Keep Alive mode * 0b1..In Keep Alive mode */ #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK) #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) /*! WAKE_INT_STS - Wakeup Interrupt Status Flag * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) /*! @} */ /*! @name KEEP_ALIVE_WKCTRL - Keep Alive Mode Wakeup Control */ /*! @{ */ #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) /*! WAKE_ON_THIS - Token PID for the wakeup request * 0b0001..Wake up after receiving OUT or SETUP token packet. * 0b1101..Wake up after receiving SETUP token packet. All other values are reserved. */ #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) /*! WAKE_ENDPT - Endpoint address for the wakeup request */ #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) /*! @} */ /*! @name MISCCTRL - Miscellaneous Control */ /*! @{ */ #define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) #define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) /*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode * 0b0..When the byte-times SOF threshold is reached * 0b1..When 8 byte-times SOF threshold is reached or overstepped */ #define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) #define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) #define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) /*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select * 0b0..According to the SOF threshold value * 0b1..When the SOF counter reaches 0 */ #define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) #define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) #define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) /*! OWNERRISODIS - OWN Error Detect for ISO IN and ISO OUT Disable * 0b0..Enable * 0b1..Disable */ #define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) #define USB_MISCCTRL_VREDG_EN_MASK (0x8U) #define USB_MISCCTRL_VREDG_EN_SHIFT (3U) /*! VREDG_EN - VREGIN Rising Edge Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) #define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) #define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) /*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) #define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) #define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) /*! STL_ADJ_EN - USB Peripheral Mode Stall Adjust Enable * 0b0..If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls. * 0b1..If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls. */ #define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) /*! @} */ /*! @name STALL_IL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction */ /*! @{ */ #define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) #define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) /*! STALL_I_DIS0 - Disable Endpoint 0 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) #define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) #define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) /*! STALL_I_DIS1 - Disable Endpoint 1 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) #define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) #define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) /*! STALL_I_DIS2 - Disable Endpoint 2 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) #define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) #define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) /*! STALL_I_DIS3 - Disable Endpoint 3 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) #define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) #define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) /*! STALL_I_DIS4 - Disable Endpoint 4 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) #define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) #define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) /*! STALL_I_DIS5 - Disable Endpoint 5 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) #define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) #define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) /*! STALL_I_DIS6 - Disable Endpoint 6 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) #define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) #define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) /*! STALL_I_DIS7 - Disable Endpoint 7 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) /*! @} */ /*! @name STALL_IH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction */ /*! @{ */ #define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) #define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) /*! STALL_I_DIS8 - Disable Endpoint 8 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) #define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) #define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) /*! STALL_I_DIS9 - Disable Endpoint 9 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) #define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) #define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) /*! STALL_I_DIS10 - Disable Endpoint 10 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) #define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) #define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) /*! STALL_I_DIS11 - Disable Endpoint 11 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) #define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) #define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) /*! STALL_I_DIS12 - Disable Endpoint 12 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) #define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) #define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) /*! STALL_I_DIS13 - Disable Endpoint 13 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) #define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) #define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) /*! STALL_I_DIS14 - Disable Endpoint 14 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) #define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) #define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) /*! STALL_I_DIS15 - Disable Endpoint 15 IN Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) /*! @} */ /*! @name STALL_OL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction */ /*! @{ */ #define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) #define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) /*! STALL_O_DIS0 - Disable Endpoint 0 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) #define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) #define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) /*! STALL_O_DIS1 - Disable Endpoint 1 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) #define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) #define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) /*! STALL_O_DIS2 - Disable Endpoint 2 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) #define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) #define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) /*! STALL_O_DIS3 - Disable Endpoint 3 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) #define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) #define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) /*! STALL_O_DIS4 - Disable Endpoint 4 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) #define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) #define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) /*! STALL_O_DIS5 - Disable Endpoint 5 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) #define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) #define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) /*! STALL_O_DIS6 - Disable Endpoint 6 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) #define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) #define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) /*! STALL_O_DIS7 - Disable Endpoint 7 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) /*! @} */ /*! @name STALL_OH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction */ /*! @{ */ #define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) #define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) /*! STALL_O_DIS8 - Disable Endpoint 8 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) #define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) #define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) /*! STALL_O_DIS9 - Disable Endpoint 9 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) #define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) #define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) /*! STALL_O_DIS10 - Disable Endpoint 10 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) #define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) #define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) /*! STALL_O_DIS11 - Disable Endpoint 11 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) #define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) #define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) /*! STALL_O_DIS12 - Disable endpoint 12 OUT direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) #define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) #define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) /*! STALL_O_DIS13 - Disable Endpoint 13 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) #define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) #define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) /*! STALL_O_DIS14 - Disable Endpoint 14 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) #define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) #define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) /*! STALL_O_DIS15 - Disable Endpoint 15 OUT Direction * 0b0..Enable * 0b1..Disable */ #define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) /*! @} */ /*! @name CLK_RECOVER_CTRL - USB Clock Recovery Control */ /*! @{ */ #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK (0x8U) #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT (3U) /*! TRIM_INIT_VAL_SEL - Selects the source for the initial FIRC trim fine value used after a reset. * 0b0..Mid-scale * 0b1..IFR */ #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT)) & USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK) #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) /*! RESTART_IFRTRIM_EN - Restart from IFR Trim Value * 0b0..Trim fine adjustment always works based on the previous updated trim fine value. * 0b1..Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable. */ #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) /*! RESET_RESUME_ROUGH_EN - Reset or Resume to Rough Phase Enable * 0b0..Always works in tracking phase after the first time rough phase, to track transition. * 0b1..Go back to rough stage whenever a bus reset or bus resume occurs. */ #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) /*! CLOCK_RECOVER_EN - Crystal-Less USB Enable * 0b0..Disable * 0b1..Enable */ #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) /*! @} */ /*! @name CLK_RECOVER_IRC_EN - FIRC Oscillator Enable */ /*! @{ */ #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) /*! IRC_EN - Fast IRC enable * 0b0..Disable * 0b1..Enable */ #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) /*! @} */ /*! @name CLK_RECOVER_INT_EN - Clock Recovery Combined Interrupt Enable */ /*! @{ */ #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) /*! OVF_ERROR_EN - Overflow error interrupt enable * 0b0..The interrupt is masked * 0b1..The interrupt is enabled */ #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) /*! @} */ /*! @name CLK_RECOVER_INT_STATUS - Clock Recovery Separated Interrupt Status */ /*! @{ */ #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) /*! OVF_ERROR - Overflow Error Interrupt Status Flag * 0b0..Interrupt did not occur * 0b1..Unmasked interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) /*! @} */ /*! * @} */ /* end of group USB_Register_Masks */ /* USB - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral USBFS0 base address */ #define USBFS0_BASE (0x500DD000u) /** Peripheral USBFS0 base address */ #define USBFS0_BASE_NS (0x400DD000u) /** Peripheral USBFS0 base pointer */ #define USBFS0 ((USB_Type *)USBFS0_BASE) /** Peripheral USBFS0 base pointer */ #define USBFS0_NS ((USB_Type *)USBFS0_BASE_NS) /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS { USBFS0_BASE } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS { USBFS0 } /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS_NS { USBFS0_BASE_NS } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS_NS { USBFS0_NS } #else /** Peripheral USBFS0 base address */ #define USBFS0_BASE (0x400DD000u) /** Peripheral USBFS0 base pointer */ #define USBFS0 ((USB_Type *)USBFS0_BASE) /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS { USBFS0_BASE } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS { USBFS0 } #endif /** Interrupt vectors for the USB peripheral type */ #define USB_IRQS { USB0_FS_IRQn } /* Backward compatibility */ #define USBFS_IRQS USB_IRQS #define USBFS_IRQHandler USB0_FS_IRQHandler /*! * @} */ /* end of group USB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBDCD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer * @{ */ /** USBDCD - Register Layout Typedef */ typedef struct { __IO uint32_t CONTROL; /**< Control, offset: 0x0 */ __IO uint32_t CLOCK; /**< Clock, offset: 0x4 */ __I uint32_t STATUS; /**< Status, offset: 0x8 */ __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override, offset: 0xC */ __IO uint32_t TIMER0; /**< TIMER0, offset: 0x10 */ __IO uint32_t TIMER1; /**< TIMER1, offset: 0x14 */ union { /* offset: 0x18 */ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11, offset: 0x18 */ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12, offset: 0x18 */ }; } USBDCD_Type; /* ---------------------------------------------------------------------------- -- USBDCD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBDCD_Register_Masks USBDCD Register Masks * @{ */ /*! @name CONTROL - Control */ /*! @{ */ #define USBDCD_CONTROL_IACK_MASK (0x1U) #define USBDCD_CONTROL_IACK_SHIFT (0U) /*! IACK - Interrupt Acknowledge * 0b0..Do not clear the interrupt. * 0b1..Clear the IF field (interrupt flag). */ #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) #define USBDCD_CONTROL_IF_MASK (0x100U) #define USBDCD_CONTROL_IF_SHIFT (8U) /*! IF - Interrupt Flag * 0b0..No interrupt is pending. * 0b1..An interrupt is pending. */ #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) #define USBDCD_CONTROL_IE_MASK (0x10000U) #define USBDCD_CONTROL_IE_SHIFT (16U) /*! IE - Interrupt Enable * 0b0..Disable interrupts to the system. * 0b1..Enable interrupts to the system. */ #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) #define USBDCD_CONTROL_BC12_MASK (0x20000U) #define USBDCD_CONTROL_BC12_SHIFT (17U) /*! BC12 - Battery Charging Revision 1.2 Compatibility * 0b0..Compatible with BC1.1 * 0b1..Compatible with BC1.2 (default) */ #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK) #define USBDCD_CONTROL_START_MASK (0x1000000U) #define USBDCD_CONTROL_START_SHIFT (24U) /*! START - Start Change Detection Sequence * 0b0..Do not start the sequence. Writes of this value have no effect. * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. */ #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) #define USBDCD_CONTROL_SR_MASK (0x2000000U) #define USBDCD_CONTROL_SR_SHIFT (25U) /*! SR - Software Reset * 0b0..Do not perform a software reset. * 0b1..Perform a software reset. */ #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) /*! @} */ /*! @name CLOCK - Clock */ /*! @{ */ #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed * 0b0..kHz Speed (between 4 kHz and 1023 kHz) * 0b1..MHz Speed (between 1 MHz and 1023 MHz) */ #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */ #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) /*! @} */ /*! @name STATUS - Status */ /*! @{ */ #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) #define USBDCD_STATUS_SEQ_RES_SHIFT (16U) /*! SEQ_RES - Charger Detection Sequence Results * 0b00..No results to report. * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. * 0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached * to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The * charger type detection has completed.) * 0b11..Attached to a DCP. */ #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) /*! SEQ_STAT - Charger Detection Sequence Status * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. * 0b01..Data pin contact detection is complete. * 0b10..Charging port detection is complete. * 0b11..Charger type detection is complete. */ #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) #define USBDCD_STATUS_ERR_MASK (0x100000U) #define USBDCD_STATUS_ERR_SHIFT (20U) /*! ERR - Error Flag * 0b0..No sequence errors. * 0b1..Error in the detection sequence. */ #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) #define USBDCD_STATUS_TO_MASK (0x200000U) #define USBDCD_STATUS_TO_SHIFT (21U) /*! TO - Timeout Flag * 0b0..The detection sequence is not running for over 1 s. * 0b1..It is over 1 s since the data pin contact was detected and debounced. */ #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) #define USBDCD_STATUS_ACTIVE_MASK (0x400000U) #define USBDCD_STATUS_ACTIVE_SHIFT (22U) /*! ACTIVE - Active Status Indicator * 0b0..The sequence is not running. * 0b1..The sequence is running. */ #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) /*! @} */ /*! @name SIGNAL_OVERRIDE - Signal Override */ /*! @{ */ #define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x7U) #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) /*! PS - Phase Selection * 0b000..No overrides. Field must remain at this value during normal USB data communication to prevent * unexpected conditions on USB_DP and USB_DM pins. (Default) * 0b001..Reserved, not for customer use. * 0b010..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. * 0b011..Reserved, not for customer use. * 0b100..Enables VDM_SRC voltage source only. * 0b101..Reserved, not for customer use. * 0b110..Reserved, not for customer use. * 0b111..Reserved, not for customer use. */ #define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK) /*! @} */ /*! @name TIMER0 - TIMER0 */ /*! @{ */ #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) #define USBDCD_TIMER0_TUNITCON_SHIFT (0U) /*! TUNITCON - Unit Connection Timer Elapse (in ms) */ #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) /*! TSEQ_INIT - Sequence Initiation Time * 0b0000000000-0b1111111111..0 ms - 1023 ms */ #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) /*! @} */ /*! @name TIMER1 - TIMER1 */ /*! @{ */ #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) /*! TVDPSRC_ON - Time Period Comparator Enabled * 0b0000000001-0b1111111111..1 ms - 1023 ms */ #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) /*! TDCD_DBNC - Time Period to Debounce D+ Signal * 0b0000000001-0b1111111111..1 ms - 1023 ms */ #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) /*! @} */ /*! @name TIMER2_BC11 - TIMER2_BC11 */ /*! @{ */ #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) /*! CHECK_DM - Time Before Check of D- Line * 0b0001-0b1111..1 ms - 15 ms */ #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup * 0b0000000001-0b1111111111..1 ms - 1023 ms */ #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) /*! @} */ /*! @name TIMER2_BC12 - TIMER2_BC12 */ /*! @{ */ #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) /*! TVDMSRC_ON - TVDMSRC_ON * 0b0000000000-0b0000101000..0 ms - 40 ms */ #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD * 0b0000000001-0b1111111111..1 ms - 1023 ms */ #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) /*! @} */ /*! * @} */ /* end of group USBDCD_Register_Masks */ /* USBDCD - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral USBDCD0 base address */ #define USBDCD0_BASE (0x500DC000u) /** Peripheral USBDCD0 base address */ #define USBDCD0_BASE_NS (0x400DC000u) /** Peripheral USBDCD0 base pointer */ #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) /** Peripheral USBDCD0 base pointer */ #define USBDCD0_NS ((USBDCD_Type *)USBDCD0_BASE_NS) /** Array initializer of USBDCD peripheral base addresses */ #define USBDCD_BASE_ADDRS { USBDCD0_BASE } /** Array initializer of USBDCD peripheral base pointers */ #define USBDCD_BASE_PTRS { USBDCD0 } /** Array initializer of USBDCD peripheral base addresses */ #define USBDCD_BASE_ADDRS_NS { USBDCD0_BASE_NS } /** Array initializer of USBDCD peripheral base pointers */ #define USBDCD_BASE_PTRS_NS { USBDCD0_NS } #else /** Peripheral USBDCD0 base address */ #define USBDCD0_BASE (0x400DC000u) /** Peripheral USBDCD0 base pointer */ #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) /** Array initializer of USBDCD peripheral base addresses */ #define USBDCD_BASE_ADDRS { USBDCD0_BASE } /** Array initializer of USBDCD peripheral base pointers */ #define USBDCD_BASE_PTRS { USBDCD0 } #endif /** Interrupt vectors for the USBDCD peripheral type */ #define USBDCD_IRQS { USB0_DCD_IRQn } /*! * @} */ /* end of group USBDCD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBHS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer * @{ */ /** USBHS - Register Layout Typedef */ typedef struct { __I uint32_t ID; /**< Identification, offset: 0x0 */ __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ uint8_t RESERVED_0[104]; __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ uint8_t RESERVED_1[108]; __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ uint8_t RESERVED_2[1]; __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ uint8_t RESERVED_3[20]; __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ uint8_t RESERVED_4[2]; __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ uint8_t RESERVED_5[24]; __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ uint8_t RESERVED_6[4]; union { /* offset: 0x154 */ __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ }; union { /* offset: 0x158 */ __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ }; uint8_t RESERVED_7[4]; __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ uint8_t RESERVED_8[16]; __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ uint8_t RESERVED_9[28]; __IO uint32_t OTGSC; /**< On-The-Go Status & Control, offset: 0x1A4 */ __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ __IO uint32_t ENDPTCTRL0; /**< Endpoint Control 0, offset: 0x1C0 */ __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ } USBHS_Type; /* ---------------------------------------------------------------------------- -- USBHS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBHS_Register_Masks USBHS Register Masks * @{ */ /*! @name ID - Identification */ /*! @{ */ #define USBHS_ID_ID_MASK (0x3FU) #define USBHS_ID_ID_SHIFT (0U) /*! ID - Configuration Number */ #define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK) #define USBHS_ID_NID_MASK (0x3F00U) #define USBHS_ID_NID_SHIFT (8U) /*! NID - Complement Version of ID */ #define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK) #define USBHS_ID_REVISION_MASK (0xFF0000U) #define USBHS_ID_REVISION_SHIFT (16U) /*! REVISION - Revision Number of the Controller Core */ #define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK) /*! @} */ /*! @name HWGENERAL - Hardware General */ /*! @{ */ #define USBHS_HWGENERAL_PHYW_MASK (0x30U) #define USBHS_HWGENERAL_PHYW_SHIFT (4U) /*! PHYW - Data width of the transceiver connected to the controller core * 0b00..8 bit wide data bus (Software non-programmable) * 0b01..16 bit wide data bus (Software non-programmable) * 0b10..Reset to 8 bit wide data bus (Software programmable) * 0b11..Reset to 16 bit wide data bus (Software programmable) */ #define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK) #define USBHS_HWGENERAL_PHYM_MASK (0x1C0U) #define USBHS_HWGENERAL_PHYM_SHIFT (6U) /*! PHYM - Transceiver Type * 0b000..UTMI/UMTI+ * 0b001..ULPI DDR * 0b010..ULPI * 0b011..Serial Only * 0b100..Software programmable - reset to UTMI/UTMI+ * 0b101..Software programmable - reset to ULPI DDR * 0b110..Software programmable - reset to ULPI * 0b111..Software programmable - reset to Serial */ #define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK) #define USBHS_HWGENERAL_SM_MASK (0x600U) #define USBHS_HWGENERAL_SM_SHIFT (9U) /*! SM - Serial interface mode capability * 0b00..No Serial Engine, always use parallel signalling * 0b01..Serial Engine present, always use serial signalling for FS/LS * 0b10..Software programmable - Reset to use parallel signalling for FS/LS * 0b11..Software programmable - Reset to use serial signalling for FS/LS */ #define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK) /*! @} */ /*! @name HWHOST - Host Hardware Parameters */ /*! @{ */ #define USBHS_HWHOST_HC_MASK (0x1U) #define USBHS_HWHOST_HC_SHIFT (0U) /*! HC - Host Capable * 0b1..Supported * 0b0..Not supported */ #define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK) #define USBHS_HWHOST_NPORT_MASK (0xEU) #define USBHS_HWHOST_NPORT_SHIFT (1U) /*! NPORT - The Number of downstream ports supported by the host controller is (NPORT+1) */ #define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK) /*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ /*! @{ */ #define USBHS_HWDEVICE_DC_MASK (0x1U) #define USBHS_HWDEVICE_DC_SHIFT (0U) /*! DC - Device Capable * 0b1..Supported * 0b0..Not supported */ #define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK) #define USBHS_HWDEVICE_DEVEP_MASK (0x3EU) #define USBHS_HWDEVICE_DEVEP_SHIFT (1U) /*! DEVEP - Device Endpoint Number */ #define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK) /*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ /*! @{ */ #define USBHS_HWTXBUF_TXBURST_MASK (0xFFU) #define USBHS_HWTXBUF_TXBURST_SHIFT (0U) /*! TXBURST - Default burst size for memory to TX buffer transfer */ #define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK) #define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U) /*! TXCHANADD - TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes */ #define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK) /*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ /*! @{ */ #define USBHS_HWRXBUF_RXBURST_MASK (0xFFU) #define USBHS_HWRXBUF_RXBURST_SHIFT (0U) /*! RXBURST - Default burst size for memory to RX buffer transfer */ #define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK) #define USBHS_HWRXBUF_RXADD_MASK (0xFF00U) #define USBHS_HWRXBUF_RXADD_SHIFT (8U) /*! RXADD - Buffer total size for all receive endpoints is (2^RXADD) */ #define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK) /*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ /*! @{ */ #define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U) /*! GPTLD - General Purpose Timer Load Value */ #define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ /*! @{ */ #define USBHS_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USBHS_GPTIMER0CTRL_GPTCNT_SHIFT (0U) /*! GPTCNT - General Purpose Timer Counter */ #define USBHS_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTRL_GPTCNT_MASK) #define USBHS_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USBHS_GPTIMER0CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE - General Purpose Timer Mode * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USBHS_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER0CTRL_GPTMODE_MASK) #define USBHS_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USBHS_GPTIMER0CTRL_GPTRST_SHIFT (30U) /*! GPTRST - General Purpose Timer Reset * 0b0..No action * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD */ #define USBHS_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRST_MASK) #define USBHS_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USBHS_GPTIMER0CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN - General Purpose Timer Run * 0b0..Stop counting * 0b1..Run */ #define USBHS_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRUN_MASK) /*! @} */ /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ /*! @{ */ #define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U) /*! GPTLD - General Purpose Timer Load Value */ #define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ /*! @{ */ #define USBHS_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USBHS_GPTIMER1CTRL_GPTCNT_SHIFT (0U) /*! GPTCNT - General Purpose Timer Counter */ #define USBHS_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTRL_GPTCNT_MASK) #define USBHS_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USBHS_GPTIMER1CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE - General Purpose Timer Mode * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USBHS_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER1CTRL_GPTMODE_MASK) #define USBHS_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USBHS_GPTIMER1CTRL_GPTRST_SHIFT (30U) /*! GPTRST - General Purpose Timer Reset * 0b0..No action * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD */ #define USBHS_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRST_MASK) #define USBHS_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USBHS_GPTIMER1CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN - General Purpose Timer Run * 0b0..Stop counting * 0b1..Run */ #define USBHS_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRUN_MASK) /*! @} */ /*! @name SBUSCFG - System Bus Config */ /*! @{ */ #define USBHS_SBUSCFG_AHBBRST_MASK (0x7U) #define USBHS_SBUSCFG_AHBBRST_SHIFT (0U) /*! AHBBRST - AHB master interface Burst configuration * 0b000..Incremental burst of unspecified length only * 0b001..INCR4 burst, then single transfer * 0b010..INCR8 burst, INCR4 burst, then single transfer * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer * 0b100..Reserved, don't use * 0b101..INCR4 burst, then incremental burst of unspecified length * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length */ #define USBHS_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_SBUSCFG_AHBBRST_SHIFT)) & USBHS_SBUSCFG_AHBBRST_MASK) /*! @} */ /*! @name CAPLENGTH - Capability Registers Length */ /*! @{ */ #define USBHS_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USBHS_CAPLENGTH_CAPLENGTH_SHIFT (0U) /*! CAPLENGTH - These bits are used as an offset to add to register base to find the beginning of * the Operational Register. Default value is '40h'. */ #define USBHS_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USBHS_CAPLENGTH_CAPLENGTH_SHIFT)) & USBHS_CAPLENGTH_CAPLENGTH_MASK) /*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ /*! @{ */ #define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USBHS_HCIVERSION_HCIVERSION_SHIFT (0U) /*! HCIVERSION - Host Controller Interface Version Number */ #define USBHS_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK) /*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ /*! @{ */ #define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU) #define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U) /*! N_PORTS - Number of Downstream Ports */ #define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK) #define USBHS_HCSPARAMS_PPC_MASK (0x10U) #define USBHS_HCSPARAMS_PPC_SHIFT (4U) /*! PPC - Port Power Control */ #define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK) #define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U) #define USBHS_HCSPARAMS_N_PCC_SHIFT (8U) /*! N_PCC - Number of Ports per Companion Controller */ #define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK) #define USBHS_HCSPARAMS_N_CC_MASK (0xF000U) #define USBHS_HCSPARAMS_N_CC_SHIFT (12U) /*! N_CC - Number of Companion Controller * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported */ #define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK) #define USBHS_HCSPARAMS_PI_MASK (0x10000U) #define USBHS_HCSPARAMS_PI_SHIFT (16U) /*! PI - Port Indicators (P INDICATOR) */ #define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK) #define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U) #define USBHS_HCSPARAMS_N_PTT_SHIFT (20U) /*! N_PTT - Number of Ports per Transaction Translator */ #define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK) #define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U) #define USBHS_HCSPARAMS_N_TT_SHIFT (24U) /*! N_TT - Number of Transaction Translators */ #define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK) /*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ /*! @{ */ #define USBHS_HCCPARAMS_ADC_MASK (0x1U) #define USBHS_HCCPARAMS_ADC_SHIFT (0U) /*! ADC - 64-bit Addressing Capability */ #define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK) #define USBHS_HCCPARAMS_PFL_MASK (0x2U) #define USBHS_HCCPARAMS_PFL_SHIFT (1U) /*! PFL - Programmable Frame List Flag */ #define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK) #define USBHS_HCCPARAMS_ASP_MASK (0x4U) #define USBHS_HCCPARAMS_ASP_SHIFT (2U) /*! ASP - Asynchronous Schedule Park Capability */ #define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK) #define USBHS_HCCPARAMS_IST_MASK (0xF0U) #define USBHS_HCCPARAMS_IST_SHIFT (4U) /*! IST - Isochronous Scheduling Threshold */ #define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK) #define USBHS_HCCPARAMS_EECP_MASK (0xFF00U) #define USBHS_HCCPARAMS_EECP_SHIFT (8U) /*! EECP - EHCI Extended Capabilities Pointer */ #define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK) /*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ /*! @{ */ #define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U) /*! DCIVERSION - Device Controller Interface Version Number */ #define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK) /*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ /*! @{ */ #define USBHS_DCCPARAMS_DEN_MASK (0x1FU) #define USBHS_DCCPARAMS_DEN_SHIFT (0U) /*! DEN - Device Endpoint Number */ #define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK) #define USBHS_DCCPARAMS_DC_MASK (0x80U) #define USBHS_DCCPARAMS_DC_SHIFT (7U) /*! DC - Device Capable */ #define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK) #define USBHS_DCCPARAMS_HC_MASK (0x100U) #define USBHS_DCCPARAMS_HC_SHIFT (8U) /*! HC - Host Capable */ #define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK) /*! @} */ /*! @name USBCMD - USB Command */ /*! @{ */ #define USBHS_USBCMD_RS_MASK (0x1U) #define USBHS_USBCMD_RS_SHIFT (0U) /*! RS - Run/Stop * 0b0..Stop * 0b1..Run */ #define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK) #define USBHS_USBCMD_RST_MASK (0x2U) #define USBHS_USBCMD_RST_SHIFT (1U) /*! RST - Controller Reset */ #define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK) #define USBHS_USBCMD_FS_1_MASK (0xCU) #define USBHS_USBCMD_FS_1_SHIFT (2U) /*! FS_1 - Frame List Size */ #define USBHS_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_1_SHIFT)) & USBHS_USBCMD_FS_1_MASK) #define USBHS_USBCMD_PSE_MASK (0x10U) #define USBHS_USBCMD_PSE_SHIFT (4U) /*! PSE - Periodic Schedule Enable * 0b0..Do not process the Periodic Schedule * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule */ #define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK) #define USBHS_USBCMD_ASE_MASK (0x20U) #define USBHS_USBCMD_ASE_SHIFT (5U) /*! ASE - Asynchronous Schedule Enable * 0b0..Do not process the Asynchronous Schedule * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule */ #define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK) #define USBHS_USBCMD_IAA_MASK (0x40U) #define USBHS_USBCMD_IAA_SHIFT (6U) /*! IAA - Interrupt on Async Advance Doorbell */ #define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK) #define USBHS_USBCMD_ASP_MASK (0x300U) #define USBHS_USBCMD_ASP_SHIFT (8U) /*! ASP - Asynchronous Schedule Park Mode Count */ #define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK) #define USBHS_USBCMD_ASPE_MASK (0x800U) #define USBHS_USBCMD_ASPE_SHIFT (11U) /*! ASPE - Asynchronous Schedule Park Mode Enable */ #define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK) #define USBHS_USBCMD_SUTW_MASK (0x2000U) #define USBHS_USBCMD_SUTW_SHIFT (13U) /*! SUTW - Setup TripWire [device mode only] */ #define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK) #define USBHS_USBCMD_ATDTW_MASK (0x4000U) #define USBHS_USBCMD_ATDTW_SHIFT (14U) /*! ATDTW - Add dTD TripWire[device mode only] */ #define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK) #define USBHS_USBCMD_FS_2_MASK (0x8000U) #define USBHS_USBCMD_FS_2_SHIFT (15U) /*! FS_2 - Frame List Size [host mode only] */ #define USBHS_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_2_SHIFT)) & USBHS_USBCMD_FS_2_MASK) #define USBHS_USBCMD_ITC_MASK (0xFF0000U) #define USBHS_USBCMD_ITC_SHIFT (16U) /*! ITC - Interrupt Threshold Control * 0b00000000..Immediate (no threshold) * 0b00000001..1 micro-frame * 0b00000010..2 micro-frames * 0b00000100..4 micro-frames * 0b00001000..8 micro-frames * 0b00010000..16 micro-frames * 0b00100000..32 micro-frames * 0b01000000..64 micro-frames */ #define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK) /*! @} */ /*! @name USBSTS - USB Status */ /*! @{ */ #define USBHS_USBSTS_UI_MASK (0x1U) #define USBHS_USBSTS_UI_SHIFT (0U) /*! UI - USB Interrupt (USBINT) */ #define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK) #define USBHS_USBSTS_UEI_MASK (0x2U) #define USBHS_USBSTS_UEI_SHIFT (1U) /*! UEI - USB Error Interrupt (USBERRINT) */ #define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK) #define USBHS_USBSTS_PCI_MASK (0x4U) #define USBHS_USBSTS_PCI_SHIFT (2U) /*! PCI - Port Change Detect */ #define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK) #define USBHS_USBSTS_FRI_MASK (0x8U) #define USBHS_USBSTS_FRI_SHIFT (3U) /*! FRI - Frame List Rollover */ #define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK) #define USBHS_USBSTS_SEI_MASK (0x10U) #define USBHS_USBSTS_SEI_SHIFT (4U) /*! SEI - System Error */ #define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK) #define USBHS_USBSTS_AAI_MASK (0x20U) #define USBHS_USBSTS_AAI_SHIFT (5U) /*! AAI - Interrupt on Async Advance */ #define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK) #define USBHS_USBSTS_URI_MASK (0x40U) #define USBHS_USBSTS_URI_SHIFT (6U) /*! URI - USB Reset Received */ #define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK) #define USBHS_USBSTS_SRI_MASK (0x80U) #define USBHS_USBSTS_SRI_SHIFT (7U) /*! SRI - SOF Received */ #define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK) #define USBHS_USBSTS_SLI_MASK (0x100U) #define USBHS_USBSTS_SLI_SHIFT (8U) /*! SLI - DCSuspend */ #define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK) #define USBHS_USBSTS_ULPII_MASK (0x400U) #define USBHS_USBSTS_ULPII_SHIFT (10U) /*! ULPII - ULPI Interrupt */ #define USBHS_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_ULPII_SHIFT)) & USBHS_USBSTS_ULPII_MASK) #define USBHS_USBSTS_HCH_MASK (0x1000U) #define USBHS_USBSTS_HCH_SHIFT (12U) /*! HCH - HCHaIted */ #define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK) #define USBHS_USBSTS_RCL_MASK (0x2000U) #define USBHS_USBSTS_RCL_SHIFT (13U) /*! RCL - Reclamation */ #define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK) #define USBHS_USBSTS_PS_MASK (0x4000U) #define USBHS_USBSTS_PS_SHIFT (14U) /*! PS - Periodic Schedule Status */ #define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK) #define USBHS_USBSTS_AS_MASK (0x8000U) #define USBHS_USBSTS_AS_SHIFT (15U) /*! AS - Asynchronous Schedule Status */ #define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK) #define USBHS_USBSTS_NAKI_MASK (0x10000U) #define USBHS_USBSTS_NAKI_SHIFT (16U) /*! NAKI - NAK Interrupt Bit */ #define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK) #define USBHS_USBSTS_TI0_MASK (0x1000000U) #define USBHS_USBSTS_TI0_SHIFT (24U) /*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) */ #define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK) #define USBHS_USBSTS_TI1_MASK (0x2000000U) #define USBHS_USBSTS_TI1_SHIFT (25U) /*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) */ #define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK) /*! @} */ /*! @name USBINTR - Interrupt Enable */ /*! @{ */ #define USBHS_USBINTR_UE_MASK (0x1U) #define USBHS_USBINTR_UE_SHIFT (0U) /*! UE - USB Interrupt Enable */ #define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK) #define USBHS_USBINTR_UEE_MASK (0x2U) #define USBHS_USBINTR_UEE_SHIFT (1U) /*! UEE - USB Error Interrupt Enable */ #define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK) #define USBHS_USBINTR_PCE_MASK (0x4U) #define USBHS_USBINTR_PCE_SHIFT (2U) /*! PCE - Port Change Detect Interrupt Enable */ #define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK) #define USBHS_USBINTR_FRE_MASK (0x8U) #define USBHS_USBINTR_FRE_SHIFT (3U) /*! FRE - Frame List Rollover Interrupt Enable */ #define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK) #define USBHS_USBINTR_SEE_MASK (0x10U) #define USBHS_USBINTR_SEE_SHIFT (4U) /*! SEE - System Error Interrupt Enable */ #define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK) #define USBHS_USBINTR_AAE_MASK (0x20U) #define USBHS_USBINTR_AAE_SHIFT (5U) /*! AAE - Async Advance Interrupt Enable */ #define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK) #define USBHS_USBINTR_URE_MASK (0x40U) #define USBHS_USBINTR_URE_SHIFT (6U) /*! URE - USB Reset Interrupt Enable */ #define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK) #define USBHS_USBINTR_SRE_MASK (0x80U) #define USBHS_USBINTR_SRE_SHIFT (7U) /*! SRE - SOF Received Interrupt Enable */ #define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK) #define USBHS_USBINTR_SLE_MASK (0x100U) #define USBHS_USBINTR_SLE_SHIFT (8U) /*! SLE - Sleep Interrupt Enable */ #define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK) #define USBHS_USBINTR_NAKE_MASK (0x10000U) #define USBHS_USBINTR_NAKE_SHIFT (16U) /*! NAKE - NAK Interrupt Enable */ #define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK) #define USBHS_USBINTR_UAIE_MASK (0x40000U) #define USBHS_USBINTR_UAIE_SHIFT (18U) /*! UAIE - USB Host Asynchronous Interrupt Enable */ #define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK) #define USBHS_USBINTR_UPIE_MASK (0x80000U) #define USBHS_USBINTR_UPIE_SHIFT (19U) /*! UPIE - USB Host Periodic Interrupt Enable */ #define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK) #define USBHS_USBINTR_TIE0_MASK (0x1000000U) #define USBHS_USBINTR_TIE0_SHIFT (24U) /*! TIE0 - General Purpose Timer #0 Interrupt Enable */ #define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK) #define USBHS_USBINTR_TIE1_MASK (0x2000000U) #define USBHS_USBINTR_TIE1_SHIFT (25U) /*! TIE1 - General Purpose Timer #1 Interrupt Enable */ #define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK) /*! @} */ /*! @name FRINDEX - USB Frame Index */ /*! @{ */ #define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USBHS_FRINDEX_FRINDEX_SHIFT (0U) /*! FRINDEX - Frame Index * 0b00000000000000..(1024) 12 * 0b00000000000001..(512) 11 * 0b00000000000010..(256) 10 * 0b00000000000011..(128) 9 * 0b00000000000100..(64) 8 * 0b00000000000101..(32) 7 * 0b00000000000110..(16) 6 * 0b00000000000111..(8) 5 */ #define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK) /*! @} */ /*! @name DEVICEADDR - Device Address */ /*! @{ */ #define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USBHS_DEVICEADDR_USBADRA_SHIFT (24U) /*! USBADRA - Device Address Advance */ #define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK) #define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USBHS_DEVICEADDR_USBADR_SHIFT (25U) /*! USBADR - Device Address */ #define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK) /*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ /*! @{ */ #define USBHS_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USBHS_PERIODICLISTBASE_BASEADR_SHIFT (12U) /*! BASEADR - Base Address (Low) */ #define USBHS_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_BASEADR_SHIFT)) & USBHS_PERIODICLISTBASE_BASEADR_MASK) /*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ /*! @{ */ #define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U) /*! ASYBASE - Link Pointer Low (LPL) */ #define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK) /*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ /*! @{ */ #define USBHS_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USBHS_ENDPTLISTADDR_EPBASE_SHIFT (11U) /*! EPBASE - Endpoint List Pointer (Low) */ #define USBHS_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTLISTADDR_EPBASE_SHIFT)) & USBHS_ENDPTLISTADDR_EPBASE_MASK) /*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ /*! @{ */ #define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U) /*! RXPBURST - Programmable RX Burst Size */ #define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK) #define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U) #define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U) /*! TXPBURST - Programmable TX Burst Size */ #define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK) /*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ /*! @{ */ #define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU) #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U) /*! TXSCHOH - Scheduler Overhead */ #define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK) #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) /*! TXSCHHEALTH - Scheduler Health Counter */ #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK) #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) /*! TXFIFOTHRES - FIFO Burst Threshold */ #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK) /*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ /*! @{ */ #define USBHS_ENDPTNAK_EPRN_MASK (0xFFU) #define USBHS_ENDPTNAK_EPRN_SHIFT (0U) /*! EPRN - RX Endpoint NAK */ #define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK) #define USBHS_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USBHS_ENDPTNAK_EPTN_SHIFT (16U) /*! EPTN - TX Endpoint NAK */ #define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK) /*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ /*! @{ */ #define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U) /*! EPRNE - RX Endpoint NAK Enable */ #define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK) #define USBHS_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U) /*! EPTNE - TX Endpoint NAK Enable */ #define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK) /*! @} */ /*! @name CONFIGFLAG - Configure Flag */ /*! @{ */ #define USBHS_CONFIGFLAG_CF_MASK (0x1U) #define USBHS_CONFIGFLAG_CF_SHIFT (0U) /*! CF - Configure Flag * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller * 0b1..Port routing control logic default-routes all ports to this host controller */ #define USBHS_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USBHS_CONFIGFLAG_CF_SHIFT)) & USBHS_CONFIGFLAG_CF_MASK) /*! @} */ /*! @name PORTSC1 - Port Status & Control */ /*! @{ */ #define USBHS_PORTSC1_CCS_MASK (0x1U) #define USBHS_PORTSC1_CCS_SHIFT (0U) /*! CCS - Current Connect Status * 0b0..In Host mode: No device is present. In Device mode: Not attached * 0b1..In Host mode: Device is present on port. In Device mode: Attached */ #define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK) #define USBHS_PORTSC1_CSC_MASK (0x2U) #define USBHS_PORTSC1_CSC_SHIFT (1U) /*! CSC - Connect Status Change * 0b0..No change * 0b1..Change in current connect status */ #define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK) #define USBHS_PORTSC1_PE_MASK (0x4U) #define USBHS_PORTSC1_PE_SHIFT (2U) /*! PE - Port Enabled/Disabled * 0b0..Disable * 0b1..Enable */ #define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK) #define USBHS_PORTSC1_PEC_MASK (0x8U) #define USBHS_PORTSC1_PEC_SHIFT (3U) /*! PEC - Port Enable/Disable Change * 0b0..No change * 0b1..Port enabled/disabled status has changed */ #define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK) #define USBHS_PORTSC1_OCA_MASK (0x10U) #define USBHS_PORTSC1_OCA_SHIFT (4U) /*! OCA - Over-Current Active * 0b1..This port currently has an over-current condition * 0b0..This port does not have an over-current condition */ #define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK) #define USBHS_PORTSC1_OCC_MASK (0x20U) #define USBHS_PORTSC1_OCC_SHIFT (5U) /*! OCC - Over-current Change */ #define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK) #define USBHS_PORTSC1_FPR_MASK (0x40U) #define USBHS_PORTSC1_FPR_SHIFT (6U) /*! FPR - Force Port Resume * 0b0..No resume (K-state) detected/driven on port * 0b1..Resume detected/driven on port */ #define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK) #define USBHS_PORTSC1_SUSP_MASK (0x80U) #define USBHS_PORTSC1_SUSP_SHIFT (7U) /*! SUSP - Suspend * 0b0..Port not in suspend state * 0b1..Port in suspend state */ #define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK) #define USBHS_PORTSC1_PR_MASK (0x100U) #define USBHS_PORTSC1_PR_SHIFT (8U) /*! PR - Port Reset * 0b0..Port is not in reset * 0b1..Port is in reset */ #define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK) #define USBHS_PORTSC1_HSP_MASK (0x200U) #define USBHS_PORTSC1_HSP_SHIFT (9U) /*! HSP - High-Speed Port */ #define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK) #define USBHS_PORTSC1_LS_MASK (0xC00U) #define USBHS_PORTSC1_LS_SHIFT (10U) /*! LS - Line Status * 0b00..SE0 * 0b10..J-state * 0b01..K-state * 0b11..Undefined */ #define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK) #define USBHS_PORTSC1_PP_MASK (0x1000U) #define USBHS_PORTSC1_PP_SHIFT (12U) /*! PP - Port Power */ #define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK) #define USBHS_PORTSC1_PO_MASK (0x2000U) #define USBHS_PORTSC1_PO_SHIFT (13U) /*! PO - Port Owner */ #define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK) #define USBHS_PORTSC1_PIC_MASK (0xC000U) #define USBHS_PORTSC1_PIC_SHIFT (14U) /*! PIC - Port Indicator Control * 0b00..Port indicators are off * 0b01..Amber * 0b10..Green * 0b11..Undefined */ #define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK) #define USBHS_PORTSC1_PTC_MASK (0xF0000U) #define USBHS_PORTSC1_PTC_SHIFT (16U) /*! PTC - Port Test Control * 0b0000..TEST_MODE_DISABLE * 0b0001..J_STATE * 0b0010..K_STATE * 0b0011..SE0 (host) / NAK (device) * 0b0100..Packet * 0b0101..FORCE_ENABLE_HS * 0b0110..FORCE_ENABLE_FS * 0b0111..FORCE_ENABLE_LS * 0b1000-0b1111..Reserved */ #define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK) #define USBHS_PORTSC1_WKCN_MASK (0x100000U) #define USBHS_PORTSC1_WKCN_SHIFT (20U) /*! WKCN - Wake on Connect Enable (WKCNNT_E) */ #define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK) #define USBHS_PORTSC1_WKDC_MASK (0x200000U) #define USBHS_PORTSC1_WKDC_SHIFT (21U) /*! WKDC - Wake on Disconnect Enable (WKDSCNNT_E) */ #define USBHS_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDC_SHIFT)) & USBHS_PORTSC1_WKDC_MASK) #define USBHS_PORTSC1_WKOC_MASK (0x400000U) #define USBHS_PORTSC1_WKOC_SHIFT (22U) /*! WKOC - Wake on Over-current Enable (WKOC_E) */ #define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK) #define USBHS_PORTSC1_PHCD_MASK (0x800000U) #define USBHS_PORTSC1_PHCD_SHIFT (23U) /*! PHCD - PHY Low Power Suspend - Clock Disable (PLPSCD) * 0b1..Disable PHY clock * 0b0..Enable PHY clock */ #define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK) #define USBHS_PORTSC1_PFSC_MASK (0x1000000U) #define USBHS_PORTSC1_PFSC_SHIFT (24U) /*! PFSC - Port Force Full Speed Connect * 0b1..Forced to full speed * 0b0..Normal operation */ #define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK) #define USBHS_PORTSC1_PTS_2_MASK (0x2000000U) #define USBHS_PORTSC1_PTS_2_SHIFT (25U) /*! PTS_2 - Parallel Transceiver Select */ #define USBHS_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_2_SHIFT)) & USBHS_PORTSC1_PTS_2_MASK) #define USBHS_PORTSC1_PSPD_MASK (0xC000000U) #define USBHS_PORTSC1_PSPD_SHIFT (26U) /*! PSPD - Port Speed * 0b00..Full Speed * 0b01..Low Speed * 0b10..High Speed * 0b11..Undefined */ #define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK) #define USBHS_PORTSC1_PTW_MASK (0x10000000U) #define USBHS_PORTSC1_PTW_SHIFT (28U) /*! PTW - Parallel Transceiver Width - Read/Write * 0b0..Select the 8-bit UTMI interface [60 MHz] * 0b1..Select the 16-bit UTMI interface [30 MHz] */ #define USBHS_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTW_SHIFT)) & USBHS_PORTSC1_PTW_MASK) #define USBHS_PORTSC1_STS_MASK (0x20000000U) #define USBHS_PORTSC1_STS_SHIFT (29U) /*! STS - Serial Transceiver Select * 0b0..Parallel Interface signals is selected * 0b1..Serial Interface Engine is selected */ #define USBHS_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_STS_SHIFT)) & USBHS_PORTSC1_STS_MASK) #define USBHS_PORTSC1_PTS_1_MASK (0xC0000000U) #define USBHS_PORTSC1_PTS_1_SHIFT (30U) /*! PTS_1 - Parallel Transceiver Select */ #define USBHS_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_1_SHIFT)) & USBHS_PORTSC1_PTS_1_MASK) /*! @} */ /*! @name OTGSC - On-The-Go Status & Control */ /*! @{ */ #define USBHS_OTGSC_VD_MASK (0x1U) #define USBHS_OTGSC_VD_SHIFT (0U) /*! VD - VBUS Discharge */ #define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK) #define USBHS_OTGSC_VC_MASK (0x2U) #define USBHS_OTGSC_VC_SHIFT (1U) /*! VC - VBUS Charge */ #define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK) #define USBHS_OTGSC_OT_MASK (0x8U) #define USBHS_OTGSC_OT_SHIFT (3U) /*! OT - OTG Termination */ #define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK) #define USBHS_OTGSC_DP_MASK (0x10U) #define USBHS_OTGSC_DP_SHIFT (4U) /*! DP - Data Pulsing */ #define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK) #define USBHS_OTGSC_IDPU_MASK (0x20U) #define USBHS_OTGSC_IDPU_SHIFT (5U) /*! IDPU - ID Pullup * 0b0..Off * 0b1..On */ #define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK) #define USBHS_OTGSC_ID_MASK (0x100U) #define USBHS_OTGSC_ID_SHIFT (8U) /*! ID - USB ID * 0b0..A device * 0b1..B device */ #define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK) #define USBHS_OTGSC_AVV_MASK (0x200U) #define USBHS_OTGSC_AVV_SHIFT (9U) /*! AVV - A VBus Valid */ #define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK) #define USBHS_OTGSC_ASV_MASK (0x400U) #define USBHS_OTGSC_ASV_SHIFT (10U) /*! ASV - A Session Valid */ #define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK) #define USBHS_OTGSC_BSV_MASK (0x800U) #define USBHS_OTGSC_BSV_SHIFT (11U) /*! BSV - B Session Valid */ #define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK) #define USBHS_OTGSC_BSE_MASK (0x1000U) #define USBHS_OTGSC_BSE_SHIFT (12U) /*! BSE - B Session End */ #define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK) #define USBHS_OTGSC_TOG_1MS_MASK (0x2000U) #define USBHS_OTGSC_TOG_1MS_SHIFT (13U) /*! TOG_1MS - 1 Millisecond Timer Toggle */ #define USBHS_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_TOG_1MS_SHIFT)) & USBHS_OTGSC_TOG_1MS_MASK) #define USBHS_OTGSC_DPS_MASK (0x4000U) #define USBHS_OTGSC_DPS_SHIFT (14U) /*! DPS - Data Bus Pulsing Status */ #define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK) #define USBHS_OTGSC_IDIS_MASK (0x10000U) #define USBHS_OTGSC_IDIS_SHIFT (16U) /*! IDIS - USB ID Interrupt Status */ #define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK) #define USBHS_OTGSC_AVVIS_MASK (0x20000U) #define USBHS_OTGSC_AVVIS_SHIFT (17U) /*! AVVIS - A VBus Valid Interrupt Status */ #define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK) #define USBHS_OTGSC_ASVIS_MASK (0x40000U) #define USBHS_OTGSC_ASVIS_SHIFT (18U) /*! ASVIS - A Session Valid Interrupt Status */ #define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK) #define USBHS_OTGSC_BSVIS_MASK (0x80000U) #define USBHS_OTGSC_BSVIS_SHIFT (19U) /*! BSVIS - B Session Valid Interrupt Status */ #define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK) #define USBHS_OTGSC_BSEIS_MASK (0x100000U) #define USBHS_OTGSC_BSEIS_SHIFT (20U) /*! BSEIS - B Session End Interrupt Status */ #define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK) #define USBHS_OTGSC_STATUS_1MS_MASK (0x200000U) #define USBHS_OTGSC_STATUS_1MS_SHIFT (21U) /*! STATUS_1MS - 1 Millisecond Timer Interrupt Status */ #define USBHS_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_STATUS_1MS_SHIFT)) & USBHS_OTGSC_STATUS_1MS_MASK) #define USBHS_OTGSC_DPIS_MASK (0x400000U) #define USBHS_OTGSC_DPIS_SHIFT (22U) /*! DPIS - Data Pulse Interrupt Status */ #define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK) #define USBHS_OTGSC_IDIE_MASK (0x1000000U) #define USBHS_OTGSC_IDIE_SHIFT (24U) /*! IDIE - USB ID Interrupt Enable */ #define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK) #define USBHS_OTGSC_AVVIE_MASK (0x2000000U) #define USBHS_OTGSC_AVVIE_SHIFT (25U) /*! AVVIE - A VBus Valid Interrupt Enable */ #define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK) #define USBHS_OTGSC_ASVIE_MASK (0x4000000U) #define USBHS_OTGSC_ASVIE_SHIFT (26U) /*! ASVIE - A Session Valid Interrupt Enable */ #define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK) #define USBHS_OTGSC_BSVIE_MASK (0x8000000U) #define USBHS_OTGSC_BSVIE_SHIFT (27U) /*! BSVIE - B Session Valid Interrupt Enable */ #define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK) #define USBHS_OTGSC_BSEIE_MASK (0x10000000U) #define USBHS_OTGSC_BSEIE_SHIFT (28U) /*! BSEIE - B Session End Interrupt Enable */ #define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK) #define USBHS_OTGSC_EN_1MS_MASK (0x20000000U) #define USBHS_OTGSC_EN_1MS_SHIFT (29U) /*! EN_1MS - 1 Millisecond Timer Interrupt Enable */ #define USBHS_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_EN_1MS_SHIFT)) & USBHS_OTGSC_EN_1MS_MASK) #define USBHS_OTGSC_DPIE_MASK (0x40000000U) #define USBHS_OTGSC_DPIE_SHIFT (30U) /*! DPIE - Data Pulse Interrupt Enable */ #define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK) /*! @} */ /*! @name USBMODE - USB Device Mode */ /*! @{ */ #define USBHS_USBMODE_CM_MASK (0x3U) #define USBHS_USBMODE_CM_SHIFT (0U) /*! CM - Controller Mode * 0b00..Idle [Default for combination host/device] * 0b01..Reserved * 0b10..Device Controller [Default for device only controller] * 0b11..Host Controller [Default for host only controller] */ #define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK) #define USBHS_USBMODE_ES_MASK (0x4U) #define USBHS_USBMODE_ES_SHIFT (2U) /*! ES - Endian Select * 0b0..Little Endian * 0b1..Big Endian */ #define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK) #define USBHS_USBMODE_SLOM_MASK (0x8U) #define USBHS_USBMODE_SLOM_SHIFT (3U) /*! SLOM - Setup Lockout Mode * 0b0..Setup Lockouts On (default); * 0b1..Setup Lockouts Off */ #define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK) #define USBHS_USBMODE_SDIS_MASK (0x10U) #define USBHS_USBMODE_SDIS_SHIFT (4U) /*! SDIS - Stream Disable Mode * 0b0..Inactive * 0b1..Active */ #define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK) /*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ /*! @{ */ #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) /*! ENDPTSETUPSTAT - Setup Endpoint Status */ #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ /*! @{ */ #define USBHS_ENDPTPRIME_PERB_MASK (0xFFU) #define USBHS_ENDPTPRIME_PERB_SHIFT (0U) /*! PERB - Prime Endpoint Receive Buffer */ #define USBHS_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PERB_SHIFT)) & USBHS_ENDPTPRIME_PERB_MASK) #define USBHS_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USBHS_ENDPTPRIME_PETB_SHIFT (16U) /*! PETB - Prime Endpoint Transmit Buffer */ #define USBHS_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PETB_SHIFT)) & USBHS_ENDPTPRIME_PETB_MASK) /*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ /*! @{ */ #define USBHS_ENDPTFLUSH_FERB_MASK (0xFFU) #define USBHS_ENDPTFLUSH_FERB_SHIFT (0U) /*! FERB - Flush Endpoint Receive Buffer */ #define USBHS_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FERB_SHIFT)) & USBHS_ENDPTFLUSH_FERB_MASK) #define USBHS_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USBHS_ENDPTFLUSH_FETB_SHIFT (16U) /*! FETB - Flush Endpoint Transmit Buffer */ #define USBHS_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FETB_SHIFT)) & USBHS_ENDPTFLUSH_FETB_MASK) /*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ /*! @{ */ #define USBHS_ENDPTSTAT_ERBR_MASK (0xFFU) #define USBHS_ENDPTSTAT_ERBR_SHIFT (0U) /*! ERBR - Endpoint Receive Buffer Ready */ #define USBHS_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ERBR_SHIFT)) & USBHS_ENDPTSTAT_ERBR_MASK) #define USBHS_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USBHS_ENDPTSTAT_ETBR_SHIFT (16U) /*! ETBR - Endpoint Transmit Buffer Ready */ #define USBHS_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ETBR_SHIFT)) & USBHS_ENDPTSTAT_ETBR_MASK) /*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ /*! @{ */ #define USBHS_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USBHS_ENDPTCOMPLETE_ERCE_SHIFT (0U) /*! ERCE - Endpoint Receive Complete Event */ #define USBHS_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ERCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ERCE_MASK) #define USBHS_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USBHS_ENDPTCOMPLETE_ETCE_SHIFT (16U) /*! ETCE - Endpoint Transmit Complete Event */ #define USBHS_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ETCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ /*! @name ENDPTCTRL0 - Endpoint Control 0 */ /*! @{ */ #define USBHS_ENDPTCTRL0_RXS_MASK (0x1U) #define USBHS_ENDPTCTRL0_RXS_SHIFT (0U) /*! RXS - RX Endpoint Stall * 0b0..Endpoint OK * 0b1..Endpoint stalled */ #define USBHS_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXS_SHIFT)) & USBHS_ENDPTCTRL0_RXS_MASK) #define USBHS_ENDPTCTRL0_RXT_MASK (0xCU) #define USBHS_ENDPTCTRL0_RXT_SHIFT (2U) /*! RXT - RX Endpoint Type * 0b00..Control */ #define USBHS_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXT_SHIFT)) & USBHS_ENDPTCTRL0_RXT_MASK) #define USBHS_ENDPTCTRL0_RXE_MASK (0x80U) #define USBHS_ENDPTCTRL0_RXE_SHIFT (7U) /*! RXE - RX Endpoint Enable * 0b0..Disabled * 0b1..Enabled */ #define USBHS_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXE_SHIFT)) & USBHS_ENDPTCTRL0_RXE_MASK) #define USBHS_ENDPTCTRL0_TXS_MASK (0x10000U) #define USBHS_ENDPTCTRL0_TXS_SHIFT (16U) /*! TXS - TX Endpoint Stall * 0b0..Endpoint OK * 0b1..Endpoint stalled */ #define USBHS_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXS_SHIFT)) & USBHS_ENDPTCTRL0_TXS_MASK) #define USBHS_ENDPTCTRL0_TXT_MASK (0xC0000U) #define USBHS_ENDPTCTRL0_TXT_SHIFT (18U) /*! TXT - TX Endpoint Type * 0b00..Control */ #define USBHS_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXT_SHIFT)) & USBHS_ENDPTCTRL0_TXT_MASK) #define USBHS_ENDPTCTRL0_TXE_MASK (0x800000U) #define USBHS_ENDPTCTRL0_TXE_SHIFT (23U) /*! TXE - TX Endpoint Enable * 0b0..Disabled * 0b1..Enabled */ #define USBHS_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXE_SHIFT)) & USBHS_ENDPTCTRL0_TXE_MASK) /*! @} */ /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ /*! @{ */ #define USBHS_ENDPTCTRL_RXS_MASK (0x1U) #define USBHS_ENDPTCTRL_RXS_SHIFT (0U) /*! RXS - RX Endpoint Stall * 0b0..Endpoint OK * 0b1..Endpoint stalled */ #define USBHS_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXS_SHIFT)) & USBHS_ENDPTCTRL_RXS_MASK) #define USBHS_ENDPTCTRL_RXD_MASK (0x2U) #define USBHS_ENDPTCTRL_RXD_SHIFT (1U) /*! RXD - RX Endpoint Data Sink * 0b0..Dual Port Memory Buffer/DMA Engine */ #define USBHS_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXD_SHIFT)) & USBHS_ENDPTCTRL_RXD_MASK) #define USBHS_ENDPTCTRL_RXT_MASK (0xCU) #define USBHS_ENDPTCTRL_RXT_SHIFT (2U) /*! RXT - RX Endpoint Type * 0b00..Control * 0b01..Isochronous * 0b10..Bulk * 0b11..Interrupt */ #define USBHS_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXT_SHIFT)) & USBHS_ENDPTCTRL_RXT_MASK) #define USBHS_ENDPTCTRL_RXI_MASK (0x20U) #define USBHS_ENDPTCTRL_RXI_SHIFT (5U) /*! RXI - RX Data Toggle Inhibit * 0b0..Disabled * 0b1..Enabled */ #define USBHS_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXI_SHIFT)) & USBHS_ENDPTCTRL_RXI_MASK) #define USBHS_ENDPTCTRL_RXR_MASK (0x40U) #define USBHS_ENDPTCTRL_RXR_SHIFT (6U) /*! RXR - RX Data Toggle Reset (WS) * 0b1..Reset PID sequence */ #define USBHS_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXR_SHIFT)) & USBHS_ENDPTCTRL_RXR_MASK) #define USBHS_ENDPTCTRL_RXE_MASK (0x80U) #define USBHS_ENDPTCTRL_RXE_SHIFT (7U) /*! RXE - RX Endpoint Enable * 0b0..Disabled * 0b1..Enabled */ #define USBHS_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXE_SHIFT)) & USBHS_ENDPTCTRL_RXE_MASK) #define USBHS_ENDPTCTRL_TXS_MASK (0x10000U) #define USBHS_ENDPTCTRL_TXS_SHIFT (16U) /*! TXS - TX Endpoint Stall * 0b0..Endpoint OK * 0b1..Endpoint stalled */ #define USBHS_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXS_SHIFT)) & USBHS_ENDPTCTRL_TXS_MASK) #define USBHS_ENDPTCTRL_TXD_MASK (0x20000U) #define USBHS_ENDPTCTRL_TXD_SHIFT (17U) /*! TXD - TX Endpoint Data Source * 0b0..Dual Port Memory Buffer/DMA Engine */ #define USBHS_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXD_SHIFT)) & USBHS_ENDPTCTRL_TXD_MASK) #define USBHS_ENDPTCTRL_TXT_MASK (0xC0000U) #define USBHS_ENDPTCTRL_TXT_SHIFT (18U) /*! TXT - TX Endpoint Type * 0b00..Control * 0b01..Isochronous * 0b10..Bulk * 0b11..Interrupt */ #define USBHS_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXT_SHIFT)) & USBHS_ENDPTCTRL_TXT_MASK) #define USBHS_ENDPTCTRL_TXI_MASK (0x200000U) #define USBHS_ENDPTCTRL_TXI_SHIFT (21U) /*! TXI - TX Data Toggle Inhibit * 0b0..PID sequencing enabled * 0b1..PID sequencing disabled */ #define USBHS_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXI_SHIFT)) & USBHS_ENDPTCTRL_TXI_MASK) #define USBHS_ENDPTCTRL_TXR_MASK (0x400000U) #define USBHS_ENDPTCTRL_TXR_SHIFT (22U) /*! TXR - TX Data Toggle Reset (WS) * 0b1..Reset PID sequence */ #define USBHS_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXR_SHIFT)) & USBHS_ENDPTCTRL_TXR_MASK) #define USBHS_ENDPTCTRL_TXE_MASK (0x800000U) #define USBHS_ENDPTCTRL_TXE_SHIFT (23U) /*! TXE - TX Endpoint Enable * 0b0..Disabled * 0b1..Enabled */ #define USBHS_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXE_SHIFT)) & USBHS_ENDPTCTRL_TXE_MASK) /*! @} */ /* The count of USBHS_ENDPTCTRL */ #define USBHS_ENDPTCTRL_COUNT (7U) /*! * @} */ /* end of group USBHS_Register_Masks */ /* USBHS - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral USBHS1__USBC base address */ #define USBHS1__USBC_BASE (0x5010B000u) /** Peripheral USBHS1__USBC base address */ #define USBHS1__USBC_BASE_NS (0x4010B000u) /** Peripheral USBHS1__USBC base pointer */ #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) /** Peripheral USBHS1__USBC base pointer */ #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) /** Array initializer of USBHS peripheral base addresses */ #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } /** Array initializer of USBHS peripheral base pointers */ #define USBHS_BASE_PTRS { USBHS1__USBC } /** Array initializer of USBHS peripheral base addresses */ #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } /** Array initializer of USBHS peripheral base pointers */ #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } #else /** Peripheral USBHS1__USBC base address */ #define USBHS1__USBC_BASE (0x4010B000u) /** Peripheral USBHS1__USBC base pointer */ #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) /** Array initializer of USBHS peripheral base addresses */ #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } /** Array initializer of USBHS peripheral base pointers */ #define USBHS_BASE_PTRS { USBHS1__USBC } #endif /** Interrupt vectors for the USBHS peripheral type */ #define USBHS_IRQS { USB1_HS_IRQn } /* Backward compatibility */ #define GPTIMER0CTL GPTIMER0CTRL #define GPTIMER1CTL GPTIMER1CTRL #define USB_SBUSCFG SBUSCFG #define EPLISTADDR ENDPTLISTADDR #define EPSETUPSR ENDPTSETUPSTAT #define EPPRIME ENDPTPRIME #define EPFLUSH ENDPTFLUSH #define EPSR ENDPTSTAT #define EPCOMPLETE ENDPTCOMPLETE #define EPCR ENDPTCTRL #define EPCR0 ENDPTCTRL0 #define USBHS_GPTIMER0CTL_GPTCNT_MASK USBHS_GPTIMER0CTRL_GPTCNT_MASK #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USBHS_GPTIMER0CTRL_GPTCNT_SHIFT #define USBHS_GPTIMER0CTL_GPTCNT(x) USBHS_GPTIMER0CTRL_GPTCNT(x) #define USBHS_GPTIMER0CTL_MODE_MASK USBHS_GPTIMER0CTRL_GPTMODE_MASK #define USBHS_GPTIMER0CTL_MODE_SHIFT USBHS_GPTIMER0CTRL_GPTMODE_SHIFT #define USBHS_GPTIMER0CTL_MODE(x) USBHS_GPTIMER0CTRL_GPTMODE(x) #define USBHS_GPTIMER0CTL_RST_MASK USBHS_GPTIMER0CTRL_GPTRST_MASK #define USBHS_GPTIMER0CTL_RST_SHIFT USBHS_GPTIMER0CTRL_GPTRST_SHIFT #define USBHS_GPTIMER0CTL_RST(x) USBHS_GPTIMER0CTRL_GPTRST(x) #define USBHS_GPTIMER0CTL_RUN_MASK USBHS_GPTIMER0CTRL_GPTRUN_MASK #define USBHS_GPTIMER0CTL_RUN_SHIFT USBHS_GPTIMER0CTRL_GPTRUN_SHIFT #define USBHS_GPTIMER0CTL_RUN(x) USBHS_GPTIMER0CTRL_GPTRUN(x) #define USBHS_GPTIMER1CTL_GPTCNT_MASK USBHS_GPTIMER1CTRL_GPTCNT_MASK #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USBHS_GPTIMER1CTRL_GPTCNT_SHIFT #define USBHS_GPTIMER1CTL_GPTCNT(x) USBHS_GPTIMER1CTRL_GPTCNT(x) #define USBHS_GPTIMER1CTL_MODE_MASK USBHS_GPTIMER1CTRL_GPTMODE_MASK #define USBHS_GPTIMER1CTL_MODE_SHIFT USBHS_GPTIMER1CTRL_GPTMODE_SHIFT #define USBHS_GPTIMER1CTL_MODE(x) USBHS_GPTIMER1CTRL_GPTMODE(x) #define USBHS_GPTIMER1CTL_RST_MASK USBHS_GPTIMER1CTRL_GPTRST_MASK #define USBHS_GPTIMER1CTL_RST_SHIFT USBHS_GPTIMER1CTRL_GPTRST_SHIFT #define USBHS_GPTIMER1CTL_RST(x) USBHS_GPTIMER1CTRL_GPTRST(x) #define USBHS_GPTIMER1CTL_RUN_MASK USBHS_GPTIMER1CTRL_GPTRUN_MASK #define USBHS_GPTIMER1CTL_RUN_SHIFT USBHS_GPTIMER1CTRL_GPTRUN_SHIFT #define USBHS_GPTIMER1CTL_RUN(x) USBHS_GPTIMER1CTRL_GPTRUN(x) #define USBHS_USB_SBUSCFG_BURSTMODE_MASK USBHS_SBUSCFG_AHBBRST_MASK #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USBHS_SBUSCFG_AHBBRST_SHIFT #define USBHS_USB_SBUSCFG_BURSTMODE(x) USBHS_SBUSCFG_AHBBRST(x) #define USBHS_USBCMD_FS_MASK USBHS_USBCMD_FS_1_MASK #define USBHS_USBCMD_FS_SHIFT USBHS_USBCMD_FS_1_SHIFT #define USBHS_USBCMD_FS(x) USBHS_USBCMD_FS_1(x) #define USBHS_EPLISTADDR_EPBASE_MASK USBHS_ENDPTLISTADDR_EPBASE_MASK #define USBHS_EPLISTADDR_EPBASE_SHIFT USBHS_ENDPTLISTADDR_EPBASE_SHIFT #define USBHS_EPLISTADDR_EPBASE(x) USBHS_ENDPTLISTADDR_EPBASE(x) #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT #define USBHS_EPSETUPSR_EPSETUPSTAT(x) USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) #define USBHS_EPPRIME_PERB_MASK USBHS_ENDPTPRIME_PERB_MASK #define USBHS_EPPRIME_PERB_SHIFT USBHS_ENDPTPRIME_PERB_SHIFT #define USBHS_EPPRIME_PERB(x) USBHS_ENDPTPRIME_PERB(x) #define USBHS_EPPRIME_PETB_MASK USBHS_ENDPTPRIME_PETB_MASK #define USBHS_EPPRIME_PETB_SHIFT USBHS_ENDPTPRIME_PETB_SHIFT #define USBHS_EPPRIME_PETB(x) USBHS_ENDPTPRIME_PETB(x) #define USBHS_EPFLUSH_FERB_MASK USBHS_ENDPTFLUSH_FERB_MASK #define USBHS_EPFLUSH_FERB_SHIFT USBHS_ENDPTFLUSH_FERB_SHIFT #define USBHS_EPFLUSH_FERB(x) USBHS_ENDPTFLUSH_FERB(x) #define USBHS_EPFLUSH_FETB_MASK USBHS_ENDPTFLUSH_FETB_MASK #define USBHS_EPFLUSH_FETB_SHIFT USBHS_ENDPTFLUSH_FETB_SHIFT #define USBHS_EPFLUSH_FETB(x) USBHS_ENDPTFLUSH_FETB(x) #define USBHS_EPSR_ERBR_MASK USBHS_ENDPTSTAT_ERBR_MASK #define USBHS_EPSR_ERBR_SHIFT USBHS_ENDPTSTAT_ERBR_SHIFT #define USBHS_EPSR_ERBR(x) USBHS_ENDPTSTAT_ERBR(x) #define USBHS_EPSR_ETBR_MASK USBHS_ENDPTSTAT_ETBR_MASK #define USBHS_EPSR_ETBR_SHIFT USBHS_ENDPTSTAT_ETBR_SHIFT #define USBHS_EPSR_ETBR(x) USBHS_ENDPTSTAT_ETBR(x) #define USBHS_EPCOMPLETE_ERCE_MASK USBHS_ENDPTCOMPLETE_ERCE_MASK #define USBHS_EPCOMPLETE_ERCE_SHIFT USBHS_ENDPTCOMPLETE_ERCE_SHIFT #define USBHS_EPCOMPLETE_ERCE(x) USBHS_ENDPTCOMPLETE_ERCE(x) #define USBHS_EPCOMPLETE_ETCE_MASK USBHS_ENDPTCOMPLETE_ETCE_MASK #define USBHS_EPCOMPLETE_ETCE_SHIFT USBHS_ENDPTCOMPLETE_ETCE_SHIFT #define USBHS_EPCOMPLETE_ETCE(x) USBHS_ENDPTCOMPLETE_ETCE(x) #define USBHS_EPCR0_RXS_MASK USBHS_ENDPTCTRL0_RXS_MASK #define USBHS_EPCR0_RXS_SHIFT USBHS_ENDPTCTRL0_RXS_SHIFT #define USBHS_EPCR0_RXS(x) USBHS_ENDPTCTRL0_RXS(x) #define USBHS_EPCR0_RXT_MASK USBHS_ENDPTCTRL0_RXT_MASK #define USBHS_EPCR0_RXT_SHIFT USBHS_ENDPTCTRL0_RXT_SHIFT #define USBHS_EPCR0_RXT(x) USBHS_ENDPTCTRL0_RXT(x) #define USBHS_EPCR0_RXE_MASK USBHS_ENDPTCTRL0_RXE_MASK #define USBHS_EPCR0_RXE_SHIFT USBHS_ENDPTCTRL0_RXE_SHIFT #define USBHS_EPCR0_RXE(x) USBHS_ENDPTCTRL0_RXE(x) #define USBHS_EPCR0_TXS_MASK USBHS_ENDPTCTRL0_TXS_MASK #define USBHS_EPCR0_TXS_SHIFT USBHS_ENDPTCTRL0_TXS_SHIFT #define USBHS_EPCR0_TXS(x) USBHS_ENDPTCTRL0_TXS(x) #define USBHS_EPCR0_TXT_MASK USBHS_ENDPTCTRL0_TXT_MASK #define USBHS_EPCR0_TXT_SHIFT USBHS_ENDPTCTRL0_TXT_SHIFT #define USBHS_EPCR0_TXT(x) USBHS_ENDPTCTRL0_TXT(x) #define USBHS_EPCR0_TXE_MASK USBHS_ENDPTCTRL0_TXE_MASK #define USBHS_EPCR0_TXE_SHIFT USBHS_ENDPTCTRL0_TXE_SHIFT #define USBHS_EPCR0_TXE(x) USBHS_ENDPTCTRL0_TXE(x) #define USBHS_EPCR_RXS_MASK USBHS_ENDPTCTRL_RXS_MASK #define USBHS_EPCR_RXS_SHIFT USBHS_ENDPTCTRL_RXS_SHIFT #define USBHS_EPCR_RXS(x) USBHS_ENDPTCTRL_RXS(x) #define USBHS_EPCR_RXD_MASK USBHS_ENDPTCTRL_RXD_MASK #define USBHS_EPCR_RXD_SHIFT USBHS_ENDPTCTRL_RXD_SHIFT #define USBHS_EPCR_RXD(x) USBHS_ENDPTCTRL_RXD(x) #define USBHS_EPCR_RXT_MASK USBHS_ENDPTCTRL_RXT_MASK #define USBHS_EPCR_RXT_SHIFT USBHS_ENDPTCTRL_RXT_SHIFT #define USBHS_EPCR_RXT(x) USBHS_ENDPTCTRL_RXT(x) #define USBHS_EPCR_RXI_MASK USBHS_ENDPTCTRL_RXI_MASK #define USBHS_EPCR_RXI_SHIFT USBHS_ENDPTCTRL_RXI_SHIFT #define USBHS_EPCR_RXI(x) USBHS_ENDPTCTRL_RXI(x) #define USBHS_EPCR_RXR_MASK USBHS_ENDPTCTRL_RXR_MASK #define USBHS_EPCR_RXR_SHIFT USBHS_ENDPTCTRL_RXR_SHIFT #define USBHS_EPCR_RXR(x) USBHS_ENDPTCTRL_RXR(x) #define USBHS_EPCR_RXE_MASK USBHS_ENDPTCTRL_RXE_MASK #define USBHS_EPCR_RXE_SHIFT USBHS_ENDPTCTRL_RXE_SHIFT #define USBHS_EPCR_RXE(x) USBHS_ENDPTCTRL_RXE(x) #define USBHS_EPCR_TXS_MASK USBHS_ENDPTCTRL_TXS_MASK #define USBHS_EPCR_TXS_SHIFT USBHS_ENDPTCTRL_TXS_SHIFT #define USBHS_EPCR_TXS(x) USBHS_ENDPTCTRL_TXS(x) #define USBHS_EPCR_TXD_MASK USBHS_ENDPTCTRL_TXD_MASK #define USBHS_EPCR_TXD_SHIFT USBHS_ENDPTCTRL_TXD_SHIFT #define USBHS_EPCR_TXD(x) USBHS_ENDPTCTRL_TXD(x) #define USBHS_EPCR_TXT_MASK USBHS_ENDPTCTRL_TXT_MASK #define USBHS_EPCR_TXT_SHIFT USBHS_ENDPTCTRL_TXT_SHIFT #define USBHS_EPCR_TXT(x) USBHS_ENDPTCTRL_TXT(x) #define USBHS_EPCR_TXI_MASK USBHS_ENDPTCTRL_TXI_MASK #define USBHS_EPCR_TXI_SHIFT USBHS_ENDPTCTRL_TXI_SHIFT #define USBHS_EPCR_TXI(x) USBHS_ENDPTCTRL_TXI(x) #define USBHS_EPCR_TXR_MASK USBHS_ENDPTCTRL_TXR_MASK #define USBHS_EPCR_TXR_SHIFT USBHS_ENDPTCTRL_TXR_SHIFT #define USBHS_EPCR_TXR(x) USBHS_ENDPTCTRL_TXR(x) #define USBHS_EPCR_TXE_MASK USBHS_ENDPTCTRL_TXE_MASK #define USBHS_EPCR_TXE_SHIFT USBHS_ENDPTCTRL_TXE_SHIFT #define USBHS_EPCR_TXE(x) USBHS_ENDPTCTRL_TXE(x) #define USBHS_EPCR_COUNT USBHS_ENDPTCTRL_COUNT #define USBHS_PORTSC1_WKDS_MASK USBHS_PORTSC1_WKDC_MASK #define USBHS_PORTSC1_WKDS_SHIFT USBHS_PORTSC1_WKDC_SHIFT #define USBHS_PORTSC1_WKDS(x) USBHS_PORTSC1_WKDC(x) #define USBHS_IRQHandler USB1_HS_IRQHandler /*! * @} */ /* end of group USBHS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBHSDCD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer * @{ */ /** USBHSDCD - Register Layout Typedef */ typedef struct { __IO uint32_t CONTROL; /**< Control, offset: 0x0 */ __IO uint32_t CLOCK; /**< Clock, offset: 0x4 */ __I uint32_t STATUS; /**< Status, offset: 0x8 */ __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override, offset: 0xC */ __IO uint32_t TIMER0; /**< TIMER0, offset: 0x10 */ __IO uint32_t TIMER1; /**< TIMER1, offset: 0x14 */ union { /* offset: 0x18 */ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11, offset: 0x18 */ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12, offset: 0x18 */ }; } USBHSDCD_Type; /* ---------------------------------------------------------------------------- -- USBHSDCD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks * @{ */ /*! @name CONTROL - Control */ /*! @{ */ #define USBHSDCD_CONTROL_IACK_MASK (0x1U) #define USBHSDCD_CONTROL_IACK_SHIFT (0U) /*! IACK - Interrupt Acknowledge * 0b0..Do not clear the interrupt. * 0b1..Clear the IF field (interrupt flag). */ #define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK) #define USBHSDCD_CONTROL_IF_MASK (0x100U) #define USBHSDCD_CONTROL_IF_SHIFT (8U) /*! IF - Interrupt Flag * 0b0..No interrupt is pending. * 0b1..An interrupt is pending. */ #define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK) #define USBHSDCD_CONTROL_IE_MASK (0x10000U) #define USBHSDCD_CONTROL_IE_SHIFT (16U) /*! IE - Interrupt Enable * 0b0..Disable interrupts to the system. * 0b1..Enable interrupts to the system. */ #define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK) #define USBHSDCD_CONTROL_BC12_MASK (0x20000U) #define USBHSDCD_CONTROL_BC12_SHIFT (17U) /*! BC12 - Battery Charging Revision 1.2 Compatibility * 0b0..Compatible with BC1.1 * 0b1..Compatible with BC1.2 (default) */ #define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK) #define USBHSDCD_CONTROL_START_MASK (0x1000000U) #define USBHSDCD_CONTROL_START_SHIFT (24U) /*! START - Start Change Detection Sequence * 0b0..Do not start the sequence. Writes of this value have no effect. * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. */ #define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK) #define USBHSDCD_CONTROL_SR_MASK (0x2000000U) #define USBHSDCD_CONTROL_SR_SHIFT (25U) /*! SR - Software Reset * 0b0..Do not perform a software reset. * 0b1..Perform a software reset. */ #define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK) /*! @} */ /*! @name CLOCK - Clock */ /*! @{ */ #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed * 0b0..kHz Speed (between 4 kHz and 1023 kHz) * 0b1..MHz Speed (between 1 MHz and 1023 MHz) */ #define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK) #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */ #define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK) /*! @} */ /*! @name STATUS - Status */ /*! @{ */ #define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U) #define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U) /*! SEQ_RES - Charger Detection Sequence Results * 0b00..No results to report. * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. * 0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached * to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The * charger type detection has completed.) * 0b11..Attached to a DCP. */ #define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK) #define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U) #define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U) /*! SEQ_STAT - Charger Detection Sequence Status * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. * 0b01..Data pin contact detection is complete. * 0b10..Charging port detection is complete. * 0b11..Charger type detection is complete. */ #define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK) #define USBHSDCD_STATUS_ERR_MASK (0x100000U) #define USBHSDCD_STATUS_ERR_SHIFT (20U) /*! ERR - Error Flag * 0b0..No sequence errors. * 0b1..Error in the detection sequence. */ #define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK) #define USBHSDCD_STATUS_TO_MASK (0x200000U) #define USBHSDCD_STATUS_TO_SHIFT (21U) /*! TO - Timeout Flag * 0b0..The detection sequence is not running for over 1 s. * 0b1..It is over 1 s since the data pin contact was detected and debounced. */ #define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK) #define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U) #define USBHSDCD_STATUS_ACTIVE_SHIFT (22U) /*! ACTIVE - Active Status Indicator * 0b0..The sequence is not running. * 0b1..The sequence is running. */ #define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK) /*! @} */ /*! @name SIGNAL_OVERRIDE - Signal Override */ /*! @{ */ #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x7U) #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) /*! PS - Phase Selection * 0b000..No overrides. Field must remain at this value during normal USB data communication to prevent * unexpected conditions on USB_DP and USB_DM pins. (Default) * 0b001..Reserved, not for customer use. * 0b010..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. * 0b011..Reserved, not for customer use. * 0b100..Enables VDM_SRC voltage source only. * 0b101..Reserved, not for customer use. * 0b110..Reserved, not for customer use. * 0b111..Reserved, not for customer use. */ #define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK) /*! @} */ /*! @name TIMER0 - TIMER0 */ /*! @{ */ #define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU) #define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U) /*! TUNITCON - Unit Connection Timer Elapse (in ms) */ #define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK) #define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U) /*! TSEQ_INIT - Sequence Initiation Time * 0b0000000000-0b1111111111..0 ms - 1023 ms */ #define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK) /*! @} */ /*! @name TIMER1 - TIMER1 */ /*! @{ */ #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) /*! TVDPSRC_ON - Time Period Comparator Enabled * 0b0000000001-0b1111111111..1 ms - 1023 ms */ #define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK) #define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U) /*! TDCD_DBNC - Time Period to Debounce D+ Signal * 0b0000000001-0b1111111111..1 ms - 1023 ms */ #define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK) /*! @} */ /*! @name TIMER2_BC11 - TIMER2_BC11 */ /*! @{ */ #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) /*! CHECK_DM - Time Before Check of D- Line * 0b0001-0b1111..1 ms - 15 ms */ #define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK) #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup * 0b0000000001-0b1111111111..1 ms - 1023 ms */ #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK) /*! @} */ /*! @name TIMER2_BC12 - TIMER2_BC12 */ /*! @{ */ #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) /*! TVDMSRC_ON - TVDMSRC_ON * 0b0000000000-0b0000101000..0 ms - 40 ms */ #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK) #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD * 0b0000000001-0b1111111111..1 ms - 1023 ms */ #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) /*! @} */ /*! * @} */ /* end of group USBHSDCD_Register_Masks */ /* USBHSDCD - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral USBHS1_PHY_DCD base address */ #define USBHS1_PHY_DCD_BASE (0x5010A800u) /** Peripheral USBHS1_PHY_DCD base address */ #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) /** Peripheral USBHS1_PHY_DCD base pointer */ #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) /** Peripheral USBHS1_PHY_DCD base pointer */ #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) /** Array initializer of USBHSDCD peripheral base addresses */ #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } /** Array initializer of USBHSDCD peripheral base pointers */ #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } /** Array initializer of USBHSDCD peripheral base addresses */ #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } /** Array initializer of USBHSDCD peripheral base pointers */ #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } #else /** Peripheral USBHS1_PHY_DCD base address */ #define USBHS1_PHY_DCD_BASE (0x4010A800u) /** Peripheral USBHS1_PHY_DCD base pointer */ #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) /** Array initializer of USBHSDCD peripheral base addresses */ #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } /** Array initializer of USBHSDCD peripheral base pointers */ #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } #endif /* Backward compatibility */ #define USBHSDCD_IRQS { USB1_HS_PHY_IRQn } #define USB1_HS_PHY_IRQS USBPHY_IRQS /*! * @} */ /* end of group USBHSDCD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBNC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer * @{ */ /** USBNC - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control, offset: 0x10 */ } USBNC_Type; /* ---------------------------------------------------------------------------- -- USBNC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Register_Masks USBNC Register Masks * @{ */ /*! @name CTRL1 - USB OTG Control 1 */ /*! @{ */ #define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) /*! OVER_CUR_DIS - Disable Overcurrent Detection * 0b1..Disables * 0b0..Enables */ #define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) #define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) #define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) /*! OVER_CUR_POL - Polarity of Overcurrent * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) */ #define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) #define USBNC_CTRL1_PWR_POL_MASK (0x200U) #define USBNC_CTRL1_PWR_POL_SHIFT (9U) /*! PWR_POL - Power Polarity * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. */ #define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) #define USBNC_CTRL1_WIE_MASK (0x400U) #define USBNC_CTRL1_WIE_SHIFT (10U) /*! WIE - Wake-up Interrupt Enable * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled */ #define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) #define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) #define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) /*! WKUP_SW_EN - Software Wake-up Enable * 0b1..Enables * 0b0..Disables */ #define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) #define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) #define USBNC_CTRL1_WKUP_SW_SHIFT (15U) /*! WKUP_SW - Software Wake-up * 0b1..Force wake-up * 0b0..Inactive */ #define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) #define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) #define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) /*! WKUP_ID_EN - Wake-up on ID Change Enable * 0b1..Enables * 0b0..Disables */ #define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) #define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) /*! WKUP_VBUS_EN - Wake-up on VBUS Change Enable * 0b1..Enables * 0b0..Disables */ #define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) #define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) /*! WKUP_DPDM_EN - Wake-up on DPDM Change Enable * 0b1..DPDM changes wake-up to be enabled, it is for device only * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0 */ #define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) #define USBNC_CTRL1_WIR_MASK (0x80000000U) #define USBNC_CTRL1_WIR_SHIFT (31U) /*! WIR - Wake-up Interrupt Request * 0b1..Request received * 0b0..No request received */ #define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) /*! @} */ /*! @name CTRL2 - USB OTG Control 2 */ /*! @{ */ #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) /*! VBUS_SOURCE_SEL - VBUS Source Select * 0b00..vbus_valid * 0b01..sess_valid * 0b10..sess_valid * 0b11..sess_valid */ #define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) #define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) #define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) /*! AUTURESUME_EN - Auto Resume Enable * 0b0..Default */ #define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) #define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) #define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) /*! LOWSPEED_EN - Low Speed Enable * 0b0..Default */ #define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) #define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) /*! UTMI_CLK_VLD - UTMI Clock Valid * 0b0..Default */ #define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) /*! @} */ /*! @name HSIC_CTRL - USB Host HSIC Control */ /*! @{ */ #define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) #define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) /*! HSIC_CLK_ON - HSIC Clock ON * 0b1..Active * 0b0..Inactive */ #define USBNC_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK) #define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U) #define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U) /*! HSIC_EN - Host HSIC Enable * 0b1..Enabled * 0b0..Disabled */ #define USBNC_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK) #define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) #define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U) /*! CLK_VLD - Clock Valid * 0b1..Valid * 0b0..Invalid */ #define USBNC_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK) /*! @} */ /*! * @} */ /* end of group USBNC_Register_Masks */ /* USBNC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral USBHS1__USBNC base address */ #define USBHS1__USBNC_BASE (0x5010B200u) /** Peripheral USBHS1__USBNC base address */ #define USBHS1__USBNC_BASE_NS (0x4010B200u) /** Peripheral USBHS1__USBNC base pointer */ #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) /** Peripheral USBHS1__USBNC base pointer */ #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) /** Array initializer of USBNC peripheral base addresses */ #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } /** Array initializer of USBNC peripheral base pointers */ #define USBNC_BASE_PTRS { USBHS1__USBNC } /** Array initializer of USBNC peripheral base addresses */ #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } /** Array initializer of USBNC peripheral base pointers */ #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } #else /** Peripheral USBHS1__USBNC base address */ #define USBHS1__USBNC_BASE (0x4010B200u) /** Peripheral USBHS1__USBNC base pointer */ #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) /** Array initializer of USBNC peripheral base addresses */ #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } /** Array initializer of USBNC peripheral base pointers */ #define USBNC_BASE_PTRS { USBHS1__USBNC } #endif /* Backward compatibility */ #define USB_OTGn_CTRL CTRL1 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK USBNC_CTRL1_OVER_CUR_DIS_MASK #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT USBNC_CTRL1_OVER_CUR_DIS_SHIFT #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) USBNC_CTRL1_OVER_CUR_DIS(x) #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK USBNC_CTRL1_OVER_CUR_POL_MASK #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT USBNC_CTRL1_OVER_CUR_POL_SHIFT #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) USBNC_CTRL1_OVER_CUR_POL(x) #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK USBNC_CTRL1_PWR_POL_MASK #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT USBNC_CTRL1_PWR_POL_SHIFT #define USBNC_USB_OTGn_CTRL_PWR_POL(x) USBNC_CTRL1_PWR_POL(x) #define USBNC_USB_OTGn_CTRL_WIE_MASK USBNC_CTRL1_WIE_MASK #define USBNC_USB_OTGn_CTRL_WIE_SHIFT USBNC_CTRL1_WIE_SHIFT #define USBNC_USB_OTGn_CTRL_WIE(x) USBNC_CTRL1_WIE(x) #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK USBNC_CTRL1_WKUP_SW_EN_MASK #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT USBNC_CTRL1_WKUP_SW_EN_SHIFT #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) USBNC_CTRL1_WKUP_SW_EN(x) #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK USBNC_CTRL1_WKUP_SW_MASK #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT USBNC_CTRL1_WKUP_SW_SHIFT #define USBNC_USB_OTGn_CTRL_WKUP_SW(x) USBNC_CTRL1_WKUP_SW(x) #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK USBNC_CTRL1_WKUP_ID_EN_MASK #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT USBNC_CTRL1_WKUP_ID_EN_SHIFT #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) USBNC_CTRL1_WKUP_ID_EN(x) #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK USBNC_CTRL1_WKUP_VBUS_EN_MASK #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT USBNC_CTRL1_WKUP_VBUS_EN_SHIFT #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) USBNC_CTRL1_WKUP_VBUS_EN(x) #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK USBNC_CTRL1_WKUP_DPDM_EN_MASK #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT USBNC_CTRL1_WKUP_DPDM_EN_SHIFT #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) USBNC_CTRL1_WKUP_DPDM_EN(x) #define USBNC_USB_OTGn_CTRL_WIR_MASK USBNC_CTRL1_WIR_MASK #define USBNC_USB_OTGn_CTRL_WIR_SHIFT USBNC_CTRL1_WIR_SHIFT #define USBNC_USB_OTGn_CTRL_WIR(x) USBNC_CTRL1_WIR(x) /*! * @} */ /* end of group USBNC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBPHY Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer * @{ */ /** USBPHY - Register Layout Typedef */ typedef struct { __IO uint32_t PWD; /**< Power Down, offset: 0x0 */ __IO uint32_t PWD_SET; /**< Power Down, offset: 0x4 */ __IO uint32_t PWD_CLR; /**< Power Down, offset: 0x8 */ __IO uint32_t PWD_TOG; /**< Power Down, offset: 0xC */ __IO uint32_t TX; /**< TX Control, offset: 0x10 */ __IO uint32_t TX_SET; /**< TX Control, offset: 0x14 */ __IO uint32_t TX_CLR; /**< TX Control, offset: 0x18 */ __IO uint32_t TX_TOG; /**< TX Control, offset: 0x1C */ __IO uint32_t RX; /**< RX Control, offset: 0x20 */ __IO uint32_t RX_SET; /**< RX Control, offset: 0x24 */ __IO uint32_t RX_CLR; /**< RX Control, offset: 0x28 */ __IO uint32_t RX_TOG; /**< RX Control, offset: 0x2C */ __IO uint32_t CTRL; /**< General Purpose Control, offset: 0x30 */ __IO uint32_t CTRL_SET; /**< General Purpose Control, offset: 0x34 */ __IO uint32_t CTRL_CLR; /**< General Purpose Control, offset: 0x38 */ __IO uint32_t CTRL_TOG; /**< General Purpose Control, offset: 0x3C */ __IO uint32_t STATUS; /**< Status, offset: 0x40 */ uint8_t RESERVED_0[12]; __IO uint32_t DEBUG0; /**< Debug 0, offset: 0x50 */ __IO uint32_t DEBUG0_SET; /**< Debug 0, offset: 0x54 */ __IO uint32_t DEBUG0_CLR; /**< Debug 0, offset: 0x58 */ __IO uint32_t DEBUG0_TOG; /**< Debug 0, offset: 0x5C */ uint8_t RESERVED_1[32]; __I uint32_t VERSION; /**< Version, offset: 0x80 */ uint8_t RESERVED_2[12]; __IO uint32_t IP; /**< IP Block, offset: 0x90 */ __IO uint32_t IP_SET; /**< IP Block, offset: 0x94 */ __IO uint32_t IP_CLR; /**< IP Block, offset: 0x98 */ __IO uint32_t IP_TOG; /**< IP Block, offset: 0x9C */ __IO uint32_t PLL_SIC; /**< PLL SIC, offset: 0xA0 */ __IO uint32_t PLL_SIC_SET; /**< PLL SIC, offset: 0xA4 */ __IO uint32_t PLL_SIC_CLR; /**< PLL SIC, offset: 0xA8 */ __IO uint32_t PLL_SIC_TOG; /**< PLL SIC, offset: 0xAC */ uint8_t RESERVED_3[16]; __IO uint32_t USB1_VBUS_DETECT; /**< VBUS Detect, offset: 0xC0 */ __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS Detect, offset: 0xC4 */ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS Detect, offset: 0xC8 */ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS Detect, offset: 0xCC */ __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status, offset: 0xD0 */ __I uint32_t USB1_VBUS_DET_STAT_SET; /**< VBUS Detect Status, offset: 0xD4 */ __I uint32_t USB1_VBUS_DET_STAT_CLR; /**< VBUS Detect Status, offset: 0xD8 */ __I uint32_t USB1_VBUS_DET_STAT_TOG; /**< VBUS Detect Status, offset: 0xDC */ __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect, offset: 0xE0 */ __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect, offset: 0xE4 */ __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect, offset: 0xE8 */ __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect, offset: 0xEC */ __I uint32_t USB1_CHRG_DET_STAT; /**< Charger Detect Status, offset: 0xF0 */ __I uint32_t USB1_CHRG_DET_STAT_SET; /**< Charger Detect Status, offset: 0xF4 */ __I uint32_t USB1_CHRG_DET_STAT_CLR; /**< Charger Detect Status, offset: 0xF8 */ __I uint32_t USB1_CHRG_DET_STAT_TOG; /**< Charger Detect Status, offset: 0xFC */ __IO uint32_t ANACTRL; /**< Analog Control, offset: 0x100 */ __IO uint32_t ANACTRL_SET; /**< Analog Control, offset: 0x104 */ __IO uint32_t ANACTRL_CLR; /**< Analog Control, offset: 0x108 */ __IO uint32_t ANACTRL_TOG; /**< Analog Control, offset: 0x10C */ uint8_t RESERVED_4[32]; __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim, offset: 0x130 */ __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim, offset: 0x134 */ __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim, offset: 0x138 */ __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim, offset: 0x13C */ __IO uint32_t PFDA; /**< PFD A, offset: 0x140 */ __IO uint32_t PFDA_SET; /**< PFD A, offset: 0x144 */ __IO uint32_t PFDA_CLR; /**< PFD A, offset: 0x148 */ __IO uint32_t PFDA_TOG; /**< PFD A, offset: 0x14C */ } USBPHY_Type; /* ---------------------------------------------------------------------------- -- USBPHY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBPHY_Register_Masks USBPHY Register Masks * @{ */ /*! @name PWD - Power Down */ /*! @{ */ #define USBPHY_PWD_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TXPWDFS_SHIFT (10U) /*! TXPWDFS - Power Down USB FS TX Drivers * 0b0..Provide bias to enable * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block * 0b0..Enable * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror * 0b0..Enable * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) #define USBPHY_PWD_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_RXPWDENV_SHIFT (17U) /*! RXPWDENV - Power Down USB HS RX Envelope Detector * 0b0..Enable * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 - Power Down USB FS Differential Receiver * 0b0..Enable * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF - Power Down USB HS Differential Receiver * 0b0..Enable * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) #define USBPHY_PWD_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_RXPWDRX_SHIFT (20U) /*! RXPWDRX - Power Down USBPHY Receiver Circuits * 0b0..Enable * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) /*! @} */ /*! @name PWD_SET - Power Down */ /*! @{ */ #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) /*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) /*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) /*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) /*! @} */ /*! @name PWD_CLR - Power Down */ /*! @{ */ #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) /*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) /*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) /*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) /*! @} */ /*! @name PWD_TOG - Power Down */ /*! @{ */ #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) /*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) /*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) /*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) /*! @} */ /*! @name TX - TX Control */ /*! @{ */ #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) /*! D_CAL - HS TX Output Current Trim * 0b0000..Maximum current, approximately 19% above nominal * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal */ #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) #define USBPHY_TX_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_TXCAL45DN_SHIFT (8U) /*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TXCAL45DP_SHIFT (16U) /*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) /*! @} */ /*! @name TX_SET - TX Control */ /*! @{ */ #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) /*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) #define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) /*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) /*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) /*! @} */ /*! @name TX_CLR - TX Control */ /*! @{ */ #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) /*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) #define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) /*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) /*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) /*! @} */ /*! @name TX_TOG - TX Control */ /*! @{ */ #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) /*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) #define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) /*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) /*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) /*! @} */ /*! @name RX - RX Control */ /*! @{ */ #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) /*! ENVADJ - Envelope Detector Trip Point * 0b000..0.1000 V * 0b001..0.1125 V * 0b010..0.1250 V * 0b011..0.0875 V * 0b1xx.. */ #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) #define USBPHY_RX_DISCONADJ_MASK (0x70U) #define USBPHY_RX_DISCONADJ_SHIFT (4U) /*! DISCONADJ - Disconnect Detector Trip Point * 0b000..0.56875 V * 0b001..0.55000 V * 0b010..0.58125 V * 0b011..0.60000 V * 0b1xx.. */ #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) /*! @} */ /*! @name RX_SET - RX Control */ /*! @{ */ #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) /*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) /*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) /*! @} */ /*! @name RX_CLR - RX Control */ /*! @{ */ #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) /*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) /*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) /*! @} */ /*! @name RX_TOG - RX Control */ /*! @{ */ #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) /*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) /*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) /*! @} */ /*! @name CTRL - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) /*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) /*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) /*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) /*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt * 0b0..Connected * 0b1..Disconnected */ #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) /*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) /*! DEVPLUGIN_POLARITY - Device Plug-In Polarity * 0b0..Plugged in * 0b1..Unplugged */ #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) /*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt * 0b0..No ID change interrupt * 0b1..ID change interrupt */ #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) /*! ENOTGIDDETECT - Enable Internal OTG ID Detector * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) /*! RESUMEIRQSTICKY - Resume Interrupt Sticky * 0b0..During the resume or reset state signaling period * 0b1..Until you write 0 to it */ #define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) /*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) /*! RESUME_IRQ - Resume Interrupt * 0b0..No resume interrupt * 0b1..Resume interrupt */ #define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) /*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) /*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) /*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) /*! ENUTMILEVEL2 - UTMI Level 2 Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) /*! ENUTMILEVEL3 - UTMI Level 3 Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) /*! ENIRQWAKEUP - Wake-Up Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) /*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) /*! AUTORESUME_EN - Autoresume Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) /*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) /*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) /*! OTG_ID_VALUE - OTG ID Value * 0b0..Host * 0b1..Device */ #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) /*! UTMI_SUSPENDM - UTMI Suspend * 0b0..Not suspended * 0b1..Suspended */ #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLKGATE_SHIFT (30U) /*! CLKGATE - UTMI Clock Gate * 0b0..Run clocks * 0b1..Gate clocks */ #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) /*! SFTRST - Software Reset * 0b0..Release from reset * 0b1..Soft-reset */ #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) /*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) /*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) /*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) /*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) /*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) /*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) /*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) /*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) /*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) /*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) /*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) /*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) /*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) /*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) /*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) /*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) /*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) /*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) /*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) /*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) /*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) /*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) /*! UTMI_SUSPENDM - UTMI Suspend */ #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) /*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) /*! SFTRST - Software Reset */ #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) /*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) /*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) /*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) /*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) /*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) /*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) /*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) /*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) /*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) /*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) /*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) /*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) /*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) /*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) /*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) /*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) /*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) /*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) /*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) /*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) /*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) /*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) /*! UTMI_SUSPENDM - UTMI Suspend */ #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) /*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) /*! SFTRST - Software Reset */ #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) /*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) /*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) /*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) /*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) /*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) /*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) /*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) /*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) /*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) /*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) /*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) /*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) /*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) /*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) /*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) /*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) /*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) /*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) /*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) /*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) /*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) /*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) /*! UTMI_SUSPENDM - UTMI Suspend */ #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) /*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) /*! SFTRST - Software Reset */ #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name STATUS - Status */ /*! @{ */ #define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) #define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) /*! OK_STATUS_3V - USB 3.3 V and 1.8 V Supply Status * 0b0..Not powered * 0b1..Powered */ #define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) /*! HOSTDISCONDETECT_STATUS - Host Disconnect Status * 0b0..Not detected * 0b1..Detected */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) /*! DEVPLUGIN_STATUS - Status Indicator for Nonstandard Resistive Plugged-In Detection * 0b0..No attachment detected * 0b1..Cable attachment detected */ #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) /*! OTGID_STATUS - OTG ID Status * 0b0..Host * 0b1..Device */ #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) /*! RESUME_STATUS - Resume Status */ #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) /*! @} */ /*! @name DEBUG0 - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) /*! OTGIDPIOLOCK - Hold OTG_ID */ #define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) /*! HSTPULLDOWN - Host Pulldown Overdrive Mode * 0b00..Disconnect * 0b01..Connect */ #define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) /*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode * 0b00..Disable * 0b01..Enable */ #define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) /*! @} */ /*! @name DEBUG0_SET - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) /*! OTGIDPIOLOCK - Hold OTG_ID */ #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) /*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) /*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) /*! @} */ /*! @name DEBUG0_CLR - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) /*! OTGIDPIOLOCK - Hold OTG_ID */ #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) /*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) /*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) /*! @} */ /*! @name DEBUG0_TOG - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) /*! OTGIDPIOLOCK - Hold OTG_ID */ #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) /*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) /*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) /*! @} */ /*! @name VERSION - Version */ /*! @{ */ #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) /*! STEP - Step */ #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) #define USBPHY_VERSION_MINOR_MASK (0xFF0000U) #define USBPHY_VERSION_MINOR_SHIFT (16U) /*! MINOR - Minor */ #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) /*! MAJOR - Major */ #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) /*! @} */ /*! @name IP - IP Block */ /*! @{ */ #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) /*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ /*! @name IP_SET - IP Block */ /*! @{ */ #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) /*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ /*! @name IP_CLR - IP Block */ /*! @{ */ #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) /*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ /*! @name IP_TOG - IP Block */ /*! @{ */ #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) /*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ /*! @name PLL_SIC - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) /*! MISC2_CONTROL0 - Miscellaneous Control * 0b0..Power up PLL * 0b1..Power down PLL */ #define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) /*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) /*! PLL_POWER - USB PLL Powerup Control * 0b0..Power down * 0b1..Allow powerup */ #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) /*! PLL_ENABLE - PLL Output Clock Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) /*! PLL_BYPASS - Bypass USB PLL * 0b0..480 MHz output clock * 0b1..Input reference clock */ #define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL - Reference Bias Power Control * 0b0..PLL_POWER internal state signal * 0b1..REFBIAS_PWD */ #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power Down Reference Bias * 0b0..Enable * 0b1..Disable or power down */ #define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) /*! PLL_REG_ENABLE - Enable PLL Regulator * 0b0..Disable * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL - PLL Divider Value Configuration * 0b000..Configure for a 32 MHz input clock (divide by 15) * 0b001..Configure for a 30 MHz input clock (divide by 16) * 0b010..Configure for a 24 MHz input clock (divide by 20) * 0b011..Reserved, not usable for USB operation (divide by 22) * 0b100..Configure for a 20 MHz input clock (divide by 24) * 0b101..Configure for a 19.2 MHz input clock (divide by 25) * 0b110..Configure for a 16 MHz input clock (divide by 30) * 0b111..Configure for a 12 MHz input clock (divide by 40) */ #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK - USB PLL Lock Status Indicator * 0b0..Not locked * 0b1..Locked */ #define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_SET - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) /*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) /*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) /*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) /*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) /*! PLL_BYPASS - Bypass USB PLL */ #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) /*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_CLR - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) /*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) /*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) /*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) /*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) /*! PLL_BYPASS - Bypass USB PLL */ #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) /*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_TOG - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) /*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) /*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) /*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) /*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) /*! PLL_BYPASS - Bypass USB PLL */ #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) /*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH - VBUS Comparator Threshold * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable * 0b0..Results of VBUS_VALID and session valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND * 0b1..Override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - VBUS_VALID Selection * 0b0..VBUS_VALID comparator result * 0b1..VBUS_VALID_3V comparator result */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection * 0b00..VBUS_VALID comparator result * 0b01..Session valid comparator result * 0b10..Session valid comparator result * 0b11.. */ #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) /*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override * 0b0..Use ID pin detector or external override * 0b1..Allow local override of ID pin detection status */ #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) /*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) /*! EXT_ID_OVERRIDE_EN - External ID Override Enable * 0b0..Internal detector or local override * 0b1..External ID signal value */ #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) /*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable * 0b0..Internal detector or local override * 0b1..External VBUS_VALID value */ #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT (18U) /*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection * 0b0..VBUS_VALID comparator * 0b1..Session valid detector */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) /*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable * 0bxx0..Disable or power down the VBUS_VALID comparator * 0bxx1..Enable the VBUS_VALID comparator * 0bx0x..Disable or power down the session valid detector * 0bx1x..Enable the session valid detector * 0b0xx..Disable or power down the VBUS_VALID_3V detector * 0b1xx..Enable the VBUS_VALID_3V detector */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - VBUS Discharge Resistor * 0b0..Disable * 0b1..Enable */ #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_SET - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) /*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) /*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) /*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) /*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT (18U) /*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) /*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_CLR - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) /*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) /*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) /*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) /*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT (18U) /*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) /*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_TOG - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) /*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) /*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) /*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) /*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT (18U) /*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) /*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) /*! @} */ /*! @name USB1_VBUS_DET_STAT - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) /*! SESSEND - Session End Indicator * 0b0..Above threshold * 0b1..Below threshold */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) /*! BVALID - B-Device Session Valid Status * 0b0..Below threshold * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) /*! AVALID - A-Device Session Valid Status * 0b0..Below threshold * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) /*! VBUS_VALID - VBUS Voltage Status * 0b0..Below threshold * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) /*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status * 0b0..Below threshold * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT (5U) /*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK) /*! @} */ /*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT (0U) /*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT (1U) /*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT (2U) /*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT (3U) /*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT (4U) /*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT (5U) /*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK) /*! @} */ /*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT (0U) /*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT (1U) /*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT (2U) /*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT (3U) /*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT (4U) /*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT (5U) /*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK) /*! @} */ /*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT (0U) /*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT (1U) /*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT (2U) /*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT (3U) /*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT (4U) /*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT (5U) /*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT (1U) /*! DETECT_SEC - Secondary Detection Function Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) /*! PULLUP_DP - DP Pullup Resistor Enable Override Control * 0b0..Disable * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT (4U) /*! VDM_SRC_ENABLE - VDM_SRC Function Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) /*! CHK_CONTACT - BC Data Contact Detect Function Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) /*! CHK_CHRG_B - BC Charger Detection Function Enable * 0b0..Enable * 0b1..Disable */ #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT (20U) /*! EN_B - Selection of BC v1.2 Function Enable * 0b0..Enable * 0b1..Disable */ #define USBPHY_USB1_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT (31U) /*! DCDSEL - DCD Selection * 0b0..Fields in USB1_CHRG_DETECT * 0b1..Fields and state machines in the USBHSDCD module */ #define USBPHY_USB1_CHRG_DETECT_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_SET - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT (1U) /*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) /*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT (4U) /*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) /*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) /*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT (20U) /*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U) /*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_CLR - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT (1U) /*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) /*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT (4U) /*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) /*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) /*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT (20U) /*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U) /*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_TOG - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT (1U) /*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) /*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT (4U) /*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) /*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) /*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT (20U) /*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U) /*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK) /*! @} */ /*! @name USB1_CHRG_DET_STAT - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) /*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output * 0b0..Not detected * 0b1..Detected */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) /*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output * 0b0..SDP detected * 0b1..Charging port detected */ #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) /*! DM_STATE - DM Voltage * 0b0..USB_DM pin voltage is <= 0.8 V * 0b1..USB_DM pin voltage is >= 2.0 V */ #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) /*! DP_STATE - DP Voltage * 0b0..USB_DP pin voltage is <= 0.8 V * 0b1..USB_DP pin voltage is >= 2.0 V */ #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) /*! SECDET_DCP - Battery Charging Secondary Detection Phase Output * 0b0..CDP detected * 0b1..DCP detected */ #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) /*! @} */ /*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT (0U) /*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT (1U) /*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT (2U) /*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT (3U) /*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT (4U) /*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK) /*! @} */ /*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT (0U) /*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT (1U) /*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT (2U) /*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT (3U) /*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT (4U) /*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK) /*! @} */ /*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT (0U) /*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT (1U) /*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT (2U) /*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT (3U) /*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT (4U) /*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK) /*! @} */ /*! @name ANACTRL - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) /*! LVI_EN - Internal Low Voltage Detector Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) #define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) /*! PFD_CLK_SEL - PFD Clock Selection * 0b00..USB1PFDCLK = USB PLL reference clock * 0b01..USB1PFDCLK = pfd_clk / 4 * 0b10..USB1PFDCLK frequency = pfd_clk / 2 * 0b11..USB1PFDCLK = pfd_clk */ #define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN - Device Pulldown Enable * 0b0..Disable * 0b1..Enable */ #define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_SET - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) /*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) /*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_CLR - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) /*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) /*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_TOG - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) /*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) /*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT (0U) /*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value * 0b0..TRIM_OVERRIDE_EN * 0b1..PLL_SIC */ #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT (2U) /*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim * 0b0..TRIM_OVERRIDE_EN * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT (3U) /*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim * 0b0..TRIM_OVERRIDE_EN * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT (4U) /*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim * 0b0..TRIM_OVERRIDE_EN * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT (15U) /*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT (20U) /*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY * 0b0000..Maximum current, approximately 19% above nominal * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT (24U) /*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT (28U) /*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_SET - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT (0U) /*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT (2U) /*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT (3U) /*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT (4U) /*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT (15U) /*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT (20U) /*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT (24U) /*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT (28U) /*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_CLR - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT (0U) /*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT (2U) /*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT (3U) /*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT (4U) /*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT (15U) /*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT (20U) /*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT (24U) /*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT (28U) /*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_TOG - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT (0U) /*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT (2U) /*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT (3U) /*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT (4U) /*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT (15U) /*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT (20U) /*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT (24U) /*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT (28U) /*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK) /*! @} */ /*! @name PFDA - PFD A */ /*! @{ */ #define USBPHY_PFDA_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_PFD0_CLKGATE_SHIFT (0U) /*! PFD0_CLKGATE - PFD0 Clock Gate * 0b0..Enable * 0b1..Disable */ #define USBPHY_PFDA_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_PFD0_FRAC_SHIFT (1U) /*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_PFD0_FRAC_MASK) #define USBPHY_PFDA_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_PFD0_STABLE_SHIFT (7U) /*! PFD0_STABLE - PFD0 Stable Signal * 0b0..Not stable * 0b1..Stable */ #define USBPHY_PFDA_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_PFD0_STABLE_MASK) /*! @} */ /*! @name PFDA_SET - PFD A */ /*! @{ */ #define USBPHY_PFDA_SET_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT (0U) /*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_SET_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_SET_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_SET_PFD0_FRAC_SHIFT (1U) /*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_SET_PFD0_FRAC_MASK) #define USBPHY_PFDA_SET_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_SET_PFD0_STABLE_SHIFT (7U) /*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_SET_PFD0_STABLE_MASK) /*! @} */ /*! @name PFDA_CLR - PFD A */ /*! @{ */ #define USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT (0U) /*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_CLR_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT (1U) /*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_CLR_PFD0_FRAC_MASK) #define USBPHY_PFDA_CLR_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT (7U) /*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_STABLE_MASK) /*! @} */ /*! @name PFDA_TOG - PFD A */ /*! @{ */ #define USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT (0U) /*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_TOG_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT (1U) /*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_TOG_PFD0_FRAC_MASK) #define USBPHY_PFDA_TOG_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT (7U) /*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_STABLE_MASK) /*! @} */ /*! * @} */ /* end of group USBPHY_Register_Masks */ /* USBPHY - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral USBPHY base address */ #define USBPHY_BASE (0x5010A000u) /** Peripheral USBPHY base address */ #define USBPHY_BASE_NS (0x4010A000u) /** Peripheral USBPHY base pointer */ #define USBPHY ((USBPHY_Type *)USBPHY_BASE) /** Peripheral USBPHY base pointer */ #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) /** Array initializer of USBPHY peripheral base addresses */ #define USBPHY_BASE_ADDRS { USBPHY_BASE } /** Array initializer of USBPHY peripheral base pointers */ #define USBPHY_BASE_PTRS { USBPHY } /** Array initializer of USBPHY peripheral base addresses */ #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } /** Array initializer of USBPHY peripheral base pointers */ #define USBPHY_BASE_PTRS_NS { USBPHY_NS } #else /** Peripheral USBPHY base address */ #define USBPHY_BASE (0x4010A000u) /** Peripheral USBPHY base pointer */ #define USBPHY ((USBPHY_Type *)USBPHY_BASE) /** Array initializer of USBPHY peripheral base addresses */ #define USBPHY_BASE_ADDRS { USBPHY_BASE } /** Array initializer of USBPHY peripheral base pointers */ #define USBPHY_BASE_PTRS { USBPHY } #endif /** Interrupt vectors for the USBPHY peripheral type */ #define USBPHY_IRQS { USB1_HS_PHY_IRQn } /* Backward compatibility */ #define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT #define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) #define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK #define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT #define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) /*! * @} */ /* end of group USBPHY_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USDHC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer * @{ */ /** USDHC - Register Layout Typedef */ typedef struct { __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ uint8_t RESERVED_0[4]; __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */ __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ uint8_t RESERVED_1[4]; __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ uint8_t RESERVED_2[84]; __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ __IO uint32_t MMC_BOOT; /**< eMMC Boot, offset: 0xC4 */ __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ } USDHC_Type; /* ---------------------------------------------------------------------------- -- USDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USDHC_Register_Masks USDHC Register Masks * @{ */ /*! @name DS_ADDR - DMA System Address */ /*! @{ */ #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) /*! DS_ADDR - System address */ #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) /*! @} */ /*! @name BLK_ATT - Block Attributes */ /*! @{ */ #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) /*! BLKSIZE - Transfer block size * 0b1000000000000..4096 bytes * 0b0100000000000..2048 bytes * 0b0001000000000..512 bytes * 0b0000111111111..511 bytes * 0b0000000000100..4 bytes * 0b0000000000011..3 bytes * 0b0000000000010..2 bytes * 0b0000000000001..1 byte * 0b0000000000000..No data transfer */ #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) /*! BLKCNT - Blocks count for current transfer * 0b1111111111111111..65535 blocks * 0b0000000000000010..2 blocks * 0b0000000000000001..1 block * 0b0000000000000000..Stop count */ #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) /*! @} */ /*! @name CMD_ARG - Command Argument */ /*! @{ */ #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) /*! CMDARG - Command argument */ #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) /*! @} */ /*! @name CMD_XFR_TYP - Command Transfer Type */ /*! @{ */ #define USDHC_CMD_XFR_TYP_DMAEN_MASK (0x1U) #define USDHC_CMD_XFR_TYP_DMAEN_SHIFT (0U) /*! DMAEN - DMAEN * 0b0..Disable * 0b1..Enable */ #define USDHC_CMD_XFR_TYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & USDHC_CMD_XFR_TYP_DMAEN_MASK) #define USDHC_CMD_XFR_TYP_BCEN_MASK (0x2U) #define USDHC_CMD_XFR_TYP_BCEN_SHIFT (1U) /*! BCEN - BCEN * 0b0..Disable * 0b1..Enable */ #define USDHC_CMD_XFR_TYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & USDHC_CMD_XFR_TYP_BCEN_MASK) #define USDHC_CMD_XFR_TYP_AC12EN_MASK (0x4U) #define USDHC_CMD_XFR_TYP_AC12EN_SHIFT (2U) /*! AC12EN - AC12EN * 0b0..Disable * 0b1..Enable */ #define USDHC_CMD_XFR_TYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC12EN_MASK) #define USDHC_CMD_XFR_TYP_DDR_EN_MASK (0x8U) #define USDHC_CMD_XFR_TYP_DDR_EN_SHIFT (3U) /*! DDR_EN - DDR_EN * 0b0..Disable * 0b1..Enable */ #define USDHC_CMD_XFR_TYP_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & USDHC_CMD_XFR_TYP_DDR_EN_MASK) #define USDHC_CMD_XFR_TYP_DTDSEL_MASK (0x10U) #define USDHC_CMD_XFR_TYP_DTDSEL_SHIFT (4U) /*! DTDSEL - DTDSEL * 0b0..Disable * 0b1..Enable */ #define USDHC_CMD_XFR_TYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DTDSEL_MASK) #define USDHC_CMD_XFR_TYP_MSBSEL_MASK (0x20U) #define USDHC_CMD_XFR_TYP_MSBSEL_SHIFT (5U) /*! MSBSEL - MSBSEL * 0b0..Disable * 0b1..Enable */ #define USDHC_CMD_XFR_TYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & USDHC_CMD_XFR_TYP_MSBSEL_MASK) #define USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK (0x40U) #define USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT (6U) /*! NIBBLE_POS - NIBBLE_POS * 0b0..Disable * 0b1..Enable */ #define USDHC_CMD_XFR_TYP_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK) #define USDHC_CMD_XFR_TYP_AC23EN_MASK (0x80U) #define USDHC_CMD_XFR_TYP_AC23EN_SHIFT (7U) /*! AC23EN - AC23EN * 0b0..Disable * 0b1..Enable */ #define USDHC_CMD_XFR_TYP_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC23EN_MASK) #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) /*! RSPTYP - Response type select * 0b00..No response * 0b01..Response length 136 * 0b10..Response length 48 * 0b11..Response length 48, check busy after response */ #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) /*! CCCEN - Command CRC check enable * 0b1..Enables command CRC check * 0b0..Disables command CRC check */ #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) /*! CICEN - Command index check enable * 0b1..Enables command index check * 0b0..Disable command index check */ #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) /*! DPSEL - Data present select * 0b1..Data present * 0b0..No data present */ #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) /*! CMDTYP - Command type * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR * 0b10..Resume CMD52 for writing function select in CCCR * 0b01..Suspend CMD52 for writing bus suspend in CCCR * 0b00..Normal other commands */ #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) /*! CMDINX - Command index */ #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) /*! @} */ /*! @name CMD_RSP0 - Command Response0 */ /*! @{ */ #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) /*! CMDRSP0 - Command response 0 */ #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) /*! @} */ /*! @name CMD_RSP1 - Command Response1 */ /*! @{ */ #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) /*! CMDRSP1 - Command response 1 */ #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) /*! @} */ /*! @name CMD_RSP2 - Command Response2 */ /*! @{ */ #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) /*! CMDRSP2 - Command response 2 */ #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) /*! @} */ /*! @name CMD_RSP3 - Command Response3 */ /*! @{ */ #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) /*! CMDRSP3 - Command response 3 */ #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) /*! @} */ /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ /*! @{ */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) /*! DATCONT - Data content */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) /*! @} */ /*! @name PRES_STATE - Present State */ /*! @{ */ #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) /*! CIHB - Command inhibit (CMD) * 0b1..Cannot issue command * 0b0..Can issue command using only CMD line */ #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) /*! CDIHB - Command Inhibit Data (DATA) * 0b1..Cannot issue command that uses the DATA line * 0b0..Can issue command that uses the DATA line */ #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) #define USDHC_PRES_STATE_DLA_MASK (0x4U) #define USDHC_PRES_STATE_DLA_SHIFT (2U) /*! DLA - Data line active * 0b1..DATA line active * 0b0..DATA line inactive */ #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) /*! SDSTB - SD clock stable * 0b1..Clock is stable. * 0b0..Clock is changing frequency and not stable. */ #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) #define USDHC_PRES_STATE_WTA_MASK (0x100U) #define USDHC_PRES_STATE_WTA_SHIFT (8U) /*! WTA - Write transfer active * 0b1..Transferring data * 0b0..No valid data */ #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) #define USDHC_PRES_STATE_RTA_MASK (0x200U) #define USDHC_PRES_STATE_RTA_SHIFT (9U) /*! RTA - Read transfer active * 0b1..Transferring data * 0b0..No valid data */ #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) #define USDHC_PRES_STATE_BWEN_MASK (0x400U) #define USDHC_PRES_STATE_BWEN_SHIFT (10U) /*! BWEN - Buffer write enable * 0b1..Write enable * 0b0..Write disable */ #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) #define USDHC_PRES_STATE_BREN_MASK (0x800U) #define USDHC_PRES_STATE_BREN_SHIFT (11U) /*! BREN - Buffer read enable * 0b1..Read enable * 0b0..Read disable */ #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode) * 0b1..Sampling clock needs re-tuning * 0b0..Fixed or well tuned sampling clock */ #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define USDHC_PRES_STATE_TSCD_SHIFT (15U) /*! TSCD - Tap select change done * 0b1..Delay cell select change is finished. * 0b0..Delay cell select change is not finished. */ #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) #define USDHC_PRES_STATE_CINST_MASK (0x10000U) #define USDHC_PRES_STATE_CINST_SHIFT (16U) /*! CINST - Card inserted * 0b1..Card inserted * 0b0..Power on reset or no card */ #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) #define USDHC_PRES_STATE_CLSL_SHIFT (23U) /*! CLSL - CMD line signal level */ #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) /*! DLSL - DATA[7:0] line signal level * 0b10000000..Data 7 line signal level * 0b01000000..Data 6 line signal level * 0b00100000..Data 5 line signal level * 0b00010000..Data 4 line signal level * 0b00001000..Data 3 line signal level * 0b00000100..Data 2 line signal level * 0b00000010..Data 1 line signal level * 0b00000001..Data 0 line signal level */ #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) /*! @} */ /*! @name PROT_CTRL - Protocol Control */ /*! @{ */ #define USDHC_PROT_CTRL_DTW_MASK (0x6U) #define USDHC_PROT_CTRL_DTW_SHIFT (1U) /*! DTW - Data transfer width * 0b10..8-bit mode * 0b01..4-bit mode * 0b00..1-bit mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) /*! D3CD - DATA3 as card detection pin * 0b1..DATA3 as card detection pin * 0b0..DATA3 does not monitor card insertion */ #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) /*! EMODE - Endian mode * 0b00..Big endian mode * 0b01..Half word big endian mode * 0b10..Little endian mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) /*! DMASEL - DMA select * 0b00..No DMA or simple DMA is selected. * 0b01..ADMA1 is selected. * 0b10..ADMA2 is selected. * 0b11..Reserved */ #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) /*! SABGREQ - Stop at block gap request * 0b1..Stop * 0b0..Transfer */ #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) /*! CREQ - Continue request * 0b1..Restart * 0b0..No effect */ #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) /*! RWCTL - Read wait control * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set */ #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define USDHC_PROT_CTRL_IABG_SHIFT (19U) /*! IABG - Interrupt at block gap * 0b1..Enables interrupt at block gap * 0b0..Disables interrupt at block gap */ #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) /*! RD_DONE_NO_8CLK - Read performed number 8 clock */ #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) /*! WECINT - Wakeup event enable on card interrupt * 0b1..Enables wakeup event enable on card interrupt * 0b0..Disables wakeup event enable on card interrupt */ #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) /*! WECINS - Wakeup event enable on SD card insertion * 0b1..Enable wakeup event enable on SD card insertion * 0b0..Disable wakeup event enable on SD card insertion */ #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) /*! WECRM - Wakeup event enable on SD card removal * 0b1..Enables wakeup event enable on SD card removal * 0b0..Disables wakeup event enable on SD card removal */ #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) /*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP * 0bxx1..Burst length is enabled for INCR. * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16. * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP. */ #define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) /*! NON_EXACT_BLK_RD - Non-exact block read * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. * 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. */ #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) /*! @} */ /*! @name SYS_CTRL - System Control */ /*! @{ */ #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define USDHC_SYS_CTRL_DVS_SHIFT (4U) /*! DVS - Divisor * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) /*! SDCLKFS - SDCLK frequency select */ #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data timeout counter value * 0b1110..SDCLK x 2 30, recommend to use for SDR104 mode * 0b1101..SDCLK x 2 29, recommend to use for supported speed modes except SDR104 mode * 0b0011..SDCLK x 2 19 * 0b0010..SDCLK x 2 18 * 0b0001..SDCLK x 2 33 * 0b0000..SDCLK x 2 32 */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) #define USDHC_SYS_CTRL_RST_FIFO_MASK (0x400000U) #define USDHC_SYS_CTRL_RST_FIFO_SHIFT (22U) /*! RST_FIFO - Reset the async FIFO */ #define USDHC_SYS_CTRL_RST_FIFO(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK) #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) /*! IPP_RST_N - Hardware reset */ #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) /*! RSTA - Software reset for all * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) /*! RSTC - Software reset for CMD line * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) /*! RSTD - Software reset for data line * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) #define USDHC_SYS_CTRL_INITA_SHIFT (27U) /*! INITA - Initialization active */ #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) /*! RSTT - Reset tuning */ #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status */ /*! @{ */ #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) /*! CC - Command complete * 0b1..Command complete * 0b0..Command not complete */ #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) #define USDHC_INT_STATUS_TC_MASK (0x2U) #define USDHC_INT_STATUS_TC_SHIFT (1U) /*! TC - Transfer complete * 0b1..Transfer complete * 0b0..Transfer does not complete */ #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) #define USDHC_INT_STATUS_BGE_MASK (0x4U) #define USDHC_INT_STATUS_BGE_SHIFT (2U) /*! BGE - Block gap event * 0b1..Transaction stopped at block gap * 0b0..No block gap event */ #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) #define USDHC_INT_STATUS_DINT_MASK (0x8U) #define USDHC_INT_STATUS_DINT_SHIFT (3U) /*! DINT - DMA interrupt * 0b1..DMA interrupt is generated. * 0b0..No DMA interrupt */ #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) #define USDHC_INT_STATUS_BWR_MASK (0x10U) #define USDHC_INT_STATUS_BWR_SHIFT (4U) /*! BWR - Buffer write ready * 0b1..Ready to write buffer * 0b0..Not ready to write buffer */ #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) #define USDHC_INT_STATUS_BRR_MASK (0x20U) #define USDHC_INT_STATUS_BRR_SHIFT (5U) /*! BRR - Buffer read ready * 0b1..Ready to read buffer * 0b0..Not ready to read buffer */ #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) #define USDHC_INT_STATUS_CINS_MASK (0x40U) #define USDHC_INT_STATUS_CINS_SHIFT (6U) /*! CINS - Card insertion * 0b1..Card inserted * 0b0..Card state unstable or removed */ #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) #define USDHC_INT_STATUS_CRM_MASK (0x80U) #define USDHC_INT_STATUS_CRM_SHIFT (7U) /*! CRM - Card removal * 0b1..Card removed * 0b0..Card state unstable or inserted */ #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) #define USDHC_INT_STATUS_CINT_MASK (0x100U) #define USDHC_INT_STATUS_CINT_SHIFT (8U) /*! CINT - Card interrupt * 0b1..Generate card interrupt * 0b0..No card interrupt */ #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode) * 0b1..Re-tuning should be performed. * 0b0..Re-tuning is not required. */ #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) #define USDHC_INT_STATUS_TP_MASK (0x4000U) #define USDHC_INT_STATUS_TP_SHIFT (14U) /*! TP - Tuning pass:(only for SD3.0 SDR104 mode) */ #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) #define USDHC_INT_STATUS_ERR_INT_STATUS_MASK (0x8000U) #define USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT (15U) /*! ERR_INT_STATUS - Error Interrupt Status */ #define USDHC_INT_STATUS_ERR_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & USDHC_INT_STATUS_ERR_INT_STATUS_MASK) #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define USDHC_INT_STATUS_CTOE_SHIFT (16U) /*! CTOE - Command timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) #define USDHC_INT_STATUS_CCE_MASK (0x20000U) #define USDHC_INT_STATUS_CCE_SHIFT (17U) /*! CCE - Command CRC error * 0b1..CRC error generated * 0b0..No error */ #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define USDHC_INT_STATUS_CEBE_SHIFT (18U) /*! CEBE - Command end bit error * 0b1..End bit error generated * 0b0..No error */ #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) #define USDHC_INT_STATUS_CIE_MASK (0x80000U) #define USDHC_INT_STATUS_CIE_SHIFT (19U) /*! CIE - Command index error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define USDHC_INT_STATUS_DTOE_SHIFT (20U) /*! DTOE - Data timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) #define USDHC_INT_STATUS_DCE_MASK (0x200000U) #define USDHC_INT_STATUS_DCE_SHIFT (21U) /*! DCE - Data CRC error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define USDHC_INT_STATUS_DEBE_SHIFT (22U) /*! DEBE - Data end bit error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define USDHC_INT_STATUS_AC12E_SHIFT (24U) /*! AC12E - Auto CMD12 error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define USDHC_INT_STATUS_TNE_SHIFT (26U) /*! TNE - Tuning error: (only for SD3.0 SDR104 mode) */ #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) /*! DMAE - DMA error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) /*! @} */ /*! @name INT_STATUS_EN - Interrupt Status Enable */ /*! @{ */ #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) /*! CCSEN - Command complete status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) /*! TCSEN - Transfer complete status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) /*! BGESEN - Block gap event status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) /*! DINTSEN - DMA interrupt status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) /*! BWRSEN - Buffer write ready status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) /*! BRRSEN - Buffer read ready status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) /*! CINSSEN - Card insertion status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) /*! CRMSEN - Card removal status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) /*! CINTSEN - Card interrupt status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) /*! RTESEN - Re-tuning event status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) /*! TPSEN - Tuning pass status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) /*! CTOESEN - Command timeout error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) /*! CCESEN - Command CRC error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) /*! CEBESEN - Command end bit error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) /*! CIESEN - Command index error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) /*! DTOESEN - Data timeout error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) /*! DCESEN - Data CRC error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) /*! DEBESEN - Data end bit error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) /*! AC12ESEN - Auto CMD12 error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) /*! TNESEN - Tuning error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) /*! DMAESEN - DMA error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) /*! @} */ /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ /*! @{ */ #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) /*! CCIEN - Command complete interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) /*! TCIEN - Transfer complete interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) /*! BGEIEN - Block gap event interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) /*! DINTIEN - DMA interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) /*! BWRIEN - Buffer write ready interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) /*! BRRIEN - Buffer read ready interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) /*! CINSIEN - Card insertion interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) /*! CRMIEN - Card removal interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) /*! CINTIEN - Card interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) /*! RTEIEN - Re-tuning event interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) /*! TPIEN - Tuning Pass interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) /*! CTOEIEN - Command timeout error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) /*! CCEIEN - Command CRC error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) /*! CEBEIEN - Command end bit error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) /*! CIEIEN - Command index error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) /*! DTOEIEN - Data timeout error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) /*! DCEIEN - Data CRC error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) /*! DEBEIEN - Data end bit error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) /*! AC12EIEN - Auto CMD12 error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) /*! TNEIEN - Tuning error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) /*! DMAEIEN - DMA error interrupt enable * 0b1..Enable * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) /*! @} */ /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ /*! @{ */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) /*! AC12NE - Auto CMD12 not executed * 0b1..Not executed * 0b0..Executed */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) /*! AC12TOE - Auto CMD12 / 23 timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x4U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (2U) /*! AC12CE - Auto CMD12 / 23 CRC error * 0b1..CRC error met in Auto CMD12/23 response * 0b0..No CRC error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x8U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U) /*! AC12EBE - Auto CMD12 / 23 end bit error * 0b1..End bit error generated * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) /*! AC12IE - Auto CMD12 / 23 index error * 0b1..Error, the CMD index in response is not CMD12/23 * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) /*! CNIBAC12E - Command not issued by Auto CMD12 error * 0b1..Not issued * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) /*! EXECUTE_TUNING - Execute tuning * 0b1..Start tuning procedure * 0b0..Tuning procedure is aborted */ #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Sample clock select * 0b1..Tuned clock is used to sample data * 0b0..Fixed clock is used to sample data */ #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) /*! @} */ /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ /*! @{ */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) /*! SDR50_SUPPORT - SDR50 support */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) /*! SDR104_SUPPORT - SDR104 support */ #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) /*! DDR50_SUPPORT - DDR50 support */ #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) /*! USE_TUNING_SDR50 - Use Tuning for SDR50 * 0b1..SDR50 supports tuning * 0b0..SDR50 does not support tuning */ #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) /*! MBL - Max block length * 0b000..512 bytes * 0b001..1024 bytes * 0b010..2048 bytes * 0b011..4096 bytes */ #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) /*! ADMAS - ADMA support * 0b1..Advanced DMA supported * 0b0..Advanced DMA not supported */ #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) /*! HSS - High speed support * 0b1..High speed supported * 0b0..High speed not supported */ #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) /*! DMAS - DMA support * 0b1..DMA supported * 0b0..DMA not supported */ #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) /*! SRS - Suspend / resume support * 0b1..Supported * 0b0..Not supported */ #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) /*! VS33 - Voltage support 3.3 V * 0b1..3.3 V supported * 0b0..3.3 V not supported */ #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) /*! VS30 - Voltage support 3.0 V * 0b1..3.0 V supported * 0b0..3.0 V not supported */ #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) /*! VS18 - Voltage support 1.8 V * 0b1..1.8 V supported * 0b0..1.8 V not supported */ #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) /*! @} */ /*! @name WTMK_LVL - Watermark Level */ /*! @{ */ #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) /*! RD_WML - Read watermark level */ #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) /*! RD_BRST_LEN - Read burst length due to system restriction, the actual burst length might not exceed 16 */ #define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) /*! WR_WML - Write watermark level */ #define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) /*! WR_BRST_LEN - Write burst length due to system restriction, the actual burst length might not exceed 16 */ #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) /*! @} */ /*! @name MIX_CTRL - Mixer Control */ /*! @{ */ #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) /*! DMAEN - DMA enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) /*! BCEN - Block count enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) /*! AC12EN - Auto CMD12 enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) /*! DDR_EN - Dual data rate mode selection */ #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) /*! DTDSEL - Data transfer direction select * 0b1..Read (Card to host) * 0b0..Write (Host to card) */ #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) /*! MSBSEL - Multi / Single block select * 0b1..Multiple blocks * 0b0..Single block */ #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) /*! NIBBLE_POS - Nibble position indication */ #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) /*! AC23EN - Auto CMD23 enable */ #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode) * 0b1..Execute tuning * 0b0..Not tuned or tuning completed */ #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Clock selection * 0b1..Tuned clock is used to sample data / cmd * 0b0..Fixed clock is used to sample data / cmd */ #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode) * 0b1..Enable auto tuning * 0b0..Disable auto tuning */ #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode) * 0b1..Feedback clock comes from the ipp_card_clk_out * 0b0..Feedback clock comes from the loopback CLK */ #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) /*! @} */ /*! @name FORCE_EVENT - Force Event */ /*! @{ */ #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) /*! FEVTAC12NE - Force event auto command 12 not executed */ #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) /*! FEVTAC12TOE - Force event auto command 12 time out error */ #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) /*! FEVTAC12CE - Force event auto command 12 CRC error */ #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */ #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) /*! FEVTAC12IE - Force event Auto Command 12 index error */ #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */ #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) /*! FEVTCTOE - Force event command time out error */ #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) /*! FEVTCCE - Force event command CRC error */ #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) /*! FEVTCEBE - Force event command end bit error */ #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) /*! FEVTCIE - Force event command index error */ #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) /*! FEVTDTOE - Force event data time out error */ #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) /*! FEVTDCE - Force event data CRC error */ #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) /*! FEVTDEBE - Force event data end bit error */ #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) /*! FEVTAC12E - Force event Auto Command 12 error */ #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) /*! FEVTTNE - Force tuning error */ #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) /*! FEVTDMAE - Force event DMA error */ #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) /*! FEVTCINT - Force event card interrupt */ #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) /*! @} */ /*! @name ADMA_ERR_STATUS - ADMA Error Status */ /*! @{ */ #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) /*! ADMAES - ADMA error state (when ADMA error is occurred) */ #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) /*! ADMALME - ADMA length mismatch error * 0b1..Error * 0b0..No error */ #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) /*! ADMADCE - ADMA descriptor error * 0b1..Error * 0b0..No error */ #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) /*! @} */ /*! @name ADMA_SYS_ADDR - ADMA System Address */ /*! @{ */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) /*! ADS_ADDR - ADMA system address */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) /*! @} */ /*! @name DLL_CTRL - DLL (Delay Line) Control */ /*! @{ */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) /*! DLL_CTRL_ENABLE - DLL and delay chain */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) /*! DLL_CTRL_RESET - DLL reset */ #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! DLL_CTRL_GATE_UPDATE - DLL gate update */ #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */ #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name DLL_STATUS - DLL Status */ /*! @{ */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) /*! DLL_STS_REF_LOCK - Reference DLL lock status */ #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) /*! DLL_STS_SLV_SEL - Slave delay line select status */ #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) /*! DLL_STS_REF_SEL - Reference delay line select taps */ #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ /*! @{ */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) /*! NXT_ERR - NXT error */ #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) /*! TAP_SEL_PRE - TAP_SEL_PRE */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) /*! PRE_ERR - PRE error */ #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) /*! @} */ /*! @name VEND_SPEC - Vendor Specific Register */ /*! @{ */ #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) /*! AC12_WR_CHKBUSY_EN - Check busy enable * 0b0..Do not check busy after auto CMD12 for write data packet * 0b1..Check busy after auto CMD12 for write data packet */ #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) /*! FRC_SDCLK_ON - Force CLK * 0b0..CLK active or inactive is fully controlled by the hardware. * 0b1..Force CLK active */ #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) /*! CRC_CHK_DIS - CRC Check Disable * 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet * 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet */ #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) /*! CMD_BYTE_EN - Register byte access for CMD_XFR_TYP * 0b0..Disable. MIX_CTRL[7:0] is read/write and CMD_XFR_TYP[7:0] is read-only. * 0b1..Enable. MIX_CTRL[7:0] is read-only and CMD_XFR_TYP[7:0] is read/write. */ #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) /*! @} */ /*! @name MMC_BOOT - eMMC Boot */ /*! @{ */ #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) /*! DTOCV_ACK - Boot ACK time out * 0b0000..SDCLK x 2^14 * 0b0001..SDCLK x 2^15 * 0b0010..SDCLK x 2^16 * 0b0011..SDCLK x 2^17 * 0b0100..SDCLK x 2^18 * 0b0101..SDCLK x 2^19 * 0b0110..SDCLK x 2^20 * 0b0111..SDCLK x 2^21 * 0b1110..SDCLK x 2^28 * 0b1111..SDCLK x 2^29 */ #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) /*! BOOT_ACK - BOOT ACK * 0b0..No ack * 0b1..Ack */ #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) /*! BOOT_MODE - Boot mode * 0b0..Normal boot * 0b1..Alternative boot */ #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) /*! BOOT_EN - Boot enable * 0b0..Fast boot disable * 0b1..Fast boot enable */ #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) /*! AUTO_SABG_EN - Auto stop at block gap */ #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) /*! DISABLE_TIME_OUT - Time out * 0b0..Enable time out * 0b1..Disable time out */ #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */ #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) /*! @} */ /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ /*! @{ */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) /*! CARD_INT_D3_TEST - Card interrupt detection test * 0b0..Check the card interrupt only when DATA3 is high. * 0b1..Check the card interrupt by ignoring the status of DATA3. */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) #define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK (0x30U) #define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT (4U) /*! TUNING_BIT_EN - Tuning bit enable * 0b00..Enable Tuning circuit for DATA[3:0] * 0b01..Enable Tuning circuit for DATA[7:0] * 0b10..Enable Tuning circuit for DATA[0] * 0b11..Invalid */ #define USDHC_VEND_SPEC2_TUNING_BIT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) /*! TUNING_CMD_EN - Tuning command enable * 0b0..Auto tuning circuit does not check the CMD line. * 0b1..Auto tuning circuit checks the CMD line. */ #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. * 0b0..Disable */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) #define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) #define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) /*! EN_32K_CLK - Select the clock source for host card detection. * 0b0..Use the peripheral clock (ipg_clk) for card detection. * 0b1..Use the low power clock (ipg_clk_lp) for card detection. */ #define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK) /*! @} */ /*! @name TUNING_CTRL - Tuning Control */ /*! @{ */ #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU) #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) /*! TUNING_START_TAP - Tuning start */ #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U) #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U) /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */ #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK) #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) /*! TUNING_COUNTER - Tuning counter */ #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) /*! TUNING_STEP - TUNING_STEP */ #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) /*! TUNING_WINDOW - Data window */ #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) /*! STD_TUNING_EN - Standard tuning circuit and procedure enable */ #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /*! @} */ /*! * @} */ /* end of group USDHC_Register_Masks */ /* USDHC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral USDHC0 base address */ #define USDHC0_BASE (0x50109000u) /** Peripheral USDHC0 base address */ #define USDHC0_BASE_NS (0x40109000u) /** Peripheral USDHC0 base pointer */ #define USDHC0 ((USDHC_Type *)USDHC0_BASE) /** Peripheral USDHC0 base pointer */ #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ #define USDHC_BASE_ADDRS { USDHC0_BASE } /** Array initializer of USDHC peripheral base pointers */ #define USDHC_BASE_PTRS { USDHC0 } /** Array initializer of USDHC peripheral base addresses */ #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ #define USDHC_BASE_PTRS_NS { USDHC0_NS } #else /** Peripheral USDHC0 base address */ #define USDHC0_BASE (0x40109000u) /** Peripheral USDHC0 base pointer */ #define USDHC0 ((USDHC_Type *)USDHC0_BASE) /** Array initializer of USDHC peripheral base addresses */ #define USDHC_BASE_ADDRS { USDHC0_BASE } /** Array initializer of USDHC peripheral base pointers */ #define USDHC_BASE_PTRS { USDHC0 } #endif /** Interrupt vectors for the USDHC peripheral type */ #define USDHC_IRQS { USDHC0_IRQn } /*! * @} */ /* end of group USDHC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- UTICK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer * @{ */ /** UTICK - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL; /**< Control, offset: 0x0 */ __IO uint32_t STAT; /**< Status, offset: 0x4 */ __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ __I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */ } UTICK_Type; /* ---------------------------------------------------------------------------- -- UTICK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup UTICK_Register_Masks UTICK Register Masks * @{ */ /*! @name CTRL - Control */ /*! @{ */ #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) #define UTICK_CTRL_DELAYVAL_SHIFT (0U) /*! DELAYVAL - Tick Interval * 0b0000000000000000000000000000000.. * *..Clock cycles as defined in the description */ #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) #define UTICK_CTRL_REPEAT_MASK (0x80000000U) #define UTICK_CTRL_REPEAT_SHIFT (31U) /*! REPEAT - Repeat Delay * 0b0..One-time delay * 0b1..Delay repeats continuously */ #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) /*! @} */ /*! @name STAT - Status */ /*! @{ */ #define UTICK_STAT_INTR_MASK (0x1U) #define UTICK_STAT_INTR_SHIFT (0U) /*! INTR - Interrupt Flag * 0b0..Not pending * 0b1..Pending */ #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) #define UTICK_STAT_ACTIVE_MASK (0x2U) #define UTICK_STAT_ACTIVE_SHIFT (1U) /*! ACTIVE - Timer Active Flag * 0b0..Inactive (stopped) * 0b1..Active */ #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) /*! @} */ /*! @name CFG - Capture Configuration */ /*! @{ */ #define UTICK_CFG_CAPEN0_MASK (0x1U) #define UTICK_CFG_CAPEN0_SHIFT (0U) /*! CAPEN0 - Enable Capture 0 * 0b0..Disable * 0b1..Enable */ #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) #define UTICK_CFG_CAPEN1_MASK (0x2U) #define UTICK_CFG_CAPEN1_SHIFT (1U) /*! CAPEN1 - Enable Capture 1 * 0b0..Disable * 0b1..Enable */ #define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) #define UTICK_CFG_CAPEN2_MASK (0x4U) #define UTICK_CFG_CAPEN2_SHIFT (2U) /*! CAPEN2 - Enable Capture 2 * 0b0..Disable * 0b1..Enable */ #define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) #define UTICK_CFG_CAPEN3_MASK (0x8U) #define UTICK_CFG_CAPEN3_SHIFT (3U) /*! CAPEN3 - Enable Capture 3 * 0b0..Disable * 0b1..Enable */ #define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) #define UTICK_CFG_CAPPOL0_MASK (0x100U) #define UTICK_CFG_CAPPOL0_SHIFT (8U) /*! CAPPOL0 - Capture Polarity 0 * 0b0..Positive * 0b1..Negative */ #define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) #define UTICK_CFG_CAPPOL1_MASK (0x200U) #define UTICK_CFG_CAPPOL1_SHIFT (9U) /*! CAPPOL1 - Capture-Polarity 1 * 0b0..Positive * 0b1..Negative */ #define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) #define UTICK_CFG_CAPPOL2_MASK (0x400U) #define UTICK_CFG_CAPPOL2_SHIFT (10U) /*! CAPPOL2 - Capture Polarity 2 * 0b0..Positive * 0b1..Negative */ #define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) #define UTICK_CFG_CAPPOL3_MASK (0x800U) #define UTICK_CFG_CAPPOL3_SHIFT (11U) /*! CAPPOL3 - Capture Polarity 3 * 0b0..Positive * 0b1..Negative */ #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) /*! @} */ /*! @name CAPCLR - Capture Clear */ /*! @{ */ #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) /*! CAPCLR0 - Clear Capture 0 * 0b0..Does nothing * 0b1..Clears the CAP0 register value */ #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) #define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) #define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) /*! CAPCLR1 - Clear Capture 1 * 0b0..Does nothing * 0b1..Clears the CAP1 register value */ #define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) #define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) #define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) /*! CAPCLR2 - Clear Capture 2 * 0b0..Does nothing * 0b1..Clears the CAP2 register value */ #define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) /*! CAPCLR3 - Clear Capture 3 * 0b0..Does nothing * 0b1..Clears the CAP3 register value */ #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) /*! @} */ /*! @name CAP - Capture */ /*! @{ */ #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) #define UTICK_CAP_CAP_VALUE_SHIFT (0U) /*! CAP_VALUE - Captured Value for the Related Capture Event */ #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) #define UTICK_CAP_VALID_MASK (0x80000000U) #define UTICK_CAP_VALID_SHIFT (31U) /*! VALID - Captured Value Valid Flag * 0b0..Valid value not captured * 0b1..Valid value captured */ #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) /*! @} */ /* The count of UTICK_CAP */ #define UTICK_CAP_COUNT (4U) /*! * @} */ /* end of group UTICK_Register_Masks */ /* UTICK - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral UTICK0 base address */ #define UTICK0_BASE (0x50012000u) /** Peripheral UTICK0 base address */ #define UTICK0_BASE_NS (0x40012000u) /** Peripheral UTICK0 base pointer */ #define UTICK0 ((UTICK_Type *)UTICK0_BASE) /** Peripheral UTICK0 base pointer */ #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) /** Array initializer of UTICK peripheral base addresses */ #define UTICK_BASE_ADDRS { UTICK0_BASE } /** Array initializer of UTICK peripheral base pointers */ #define UTICK_BASE_PTRS { UTICK0 } /** Array initializer of UTICK peripheral base addresses */ #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } /** Array initializer of UTICK peripheral base pointers */ #define UTICK_BASE_PTRS_NS { UTICK0_NS } #else /** Peripheral UTICK0 base address */ #define UTICK0_BASE (0x40012000u) /** Peripheral UTICK0 base pointer */ #define UTICK0 ((UTICK_Type *)UTICK0_BASE) /** Array initializer of UTICK peripheral base addresses */ #define UTICK_BASE_ADDRS { UTICK0_BASE } /** Array initializer of UTICK peripheral base pointers */ #define UTICK_BASE_PTRS { UTICK0 } #endif /** Interrupt vectors for the UTICK peripheral type */ #define UTICK_IRQS { UTICK0_IRQn } /*! * @} */ /* end of group UTICK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VBAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer * @{ */ /** VBAT - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t STATUSA; /**< Status A, offset: 0x10 */ __IO uint32_t STATUSB; /**< Status B, offset: 0x14 */ __IO uint32_t IRQENA; /**< Interrupt Enable A, offset: 0x18 */ __IO uint32_t IRQENB; /**< Interrupt Enable B, offset: 0x1C */ __IO uint32_t WAKENA; /**< Wake-up Enable A, offset: 0x20 */ __IO uint32_t WAKENB; /**< Wake-up Enable B, offset: 0x24 */ __IO uint32_t TAMPERA; /**< Tamper Enable A, offset: 0x28 */ __IO uint32_t TAMPERB; /**< Tamper Enable B, offset: 0x2C */ __IO uint32_t LOCKA; /**< Lock A, offset: 0x30 */ __IO uint32_t LOCKB; /**< Lock B, offset: 0x34 */ __IO uint32_t WAKECFG; /**< Wake-up Configuration, offset: 0x38 */ uint8_t RESERVED_1[196]; __IO uint32_t OSCCTLA; /**< Oscillator Control A, offset: 0x100 */ __IO uint32_t OSCCTLB; /**< Oscillator Control B, offset: 0x104 */ __IO uint32_t OSCCFGA; /**< Oscillator Configuration A, offset: 0x108 */ __IO uint32_t OSCCFGB; /**< Oscillator Configuration B, offset: 0x10C */ uint8_t RESERVED_2[8]; __IO uint32_t OSCLCKA; /**< Oscillator Lock A, offset: 0x118 */ __IO uint32_t OSCLCKB; /**< Oscillator Lock B, offset: 0x11C */ __IO uint32_t OSCCLKE; /**< Oscillator Clock Enable, offset: 0x120 */ uint8_t RESERVED_3[220]; __IO uint32_t FROCTLA; /**< FRO16K Control A, offset: 0x200 */ __IO uint32_t FROCTLB; /**< FRO16K Control B, offset: 0x204 */ uint8_t RESERVED_4[16]; __IO uint32_t FROLCKA; /**< FRO16K Lock A, offset: 0x218 */ __IO uint32_t FROLCKB; /**< FRO16K Lock B, offset: 0x21C */ __IO uint32_t FROCLKE; /**< FRO16K Clock Enable, offset: 0x220 */ uint8_t RESERVED_5[220]; __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ __IO uint32_t LDOCTLB; /**< LDO_RAM Control B, offset: 0x304 */ uint8_t RESERVED_6[16]; __IO uint32_t LDOLCKA; /**< LDO_RAM Lock A, offset: 0x318 */ __IO uint32_t LDOLCKB; /**< LDO_RAM Lock B, offset: 0x31C */ __IO uint32_t LDORAMC; /**< RAM Control, offset: 0x320 */ uint8_t RESERVED_7[12]; __IO uint32_t LDOTIMER0; /**< Bandgap Timer 0, offset: 0x330 */ uint8_t RESERVED_8[4]; __IO uint32_t LDOTIMER1; /**< Bandgap Timer 1, offset: 0x338 */ uint8_t RESERVED_9[196]; __IO uint32_t MONCTLA; /**< CLKMON Control A, offset: 0x400 */ __IO uint32_t MONCTLB; /**< CLKMON Control B, offset: 0x404 */ __IO uint32_t MONCFGA; /**< CLKMON Configuration A, offset: 0x408 */ __IO uint32_t MONCFGB; /**< CLKMON Configuration B, offset: 0x40C */ uint8_t RESERVED_10[8]; __IO uint32_t MONLCKA; /**< CLKMON Lock A, offset: 0x418 */ __IO uint32_t MONLCKB; /**< CLKMON Lock B, offset: 0x41C */ uint8_t RESERVED_11[224]; __IO uint32_t TAMCTLA; /**< TAMPER Control A, offset: 0x500 */ __IO uint32_t TAMCTLB; /**< TAMPER Control B, offset: 0x504 */ uint8_t RESERVED_12[16]; __IO uint32_t TAMLCKA; /**< TAMPER Lock A, offset: 0x518 */ __IO uint32_t TAMLCKB; /**< TAMPER Lock B, offset: 0x51C */ uint8_t RESERVED_13[224]; __IO uint32_t SWICTLA; /**< Switch Control A, offset: 0x600 */ __IO uint32_t SWICTLB; /**< Switch Control B, offset: 0x604 */ uint8_t RESERVED_14[16]; __IO uint32_t SWILCKA; /**< Switch Lock A, offset: 0x618 */ __IO uint32_t SWILCKB; /**< Switch Lock B, offset: 0x61C */ uint8_t RESERVED_15[224]; struct { /* offset: 0x700, array step: 0x8 */ __IO uint32_t WAKEUPA; /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */ __IO uint32_t WAKEUPB; /**< Wakeup 0 Register B, array offset: 0x704, array step: 0x8 */ } WAKEUP[2]; uint8_t RESERVED_16[232]; __IO uint32_t WAKLCKA; /**< Wakeup Lock A, offset: 0x7F8 */ __IO uint32_t WAKLCKB; /**< Wakeup Lock B, offset: 0x7FC */ } VBAT_Type; /* ---------------------------------------------------------------------------- -- VBAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VBAT_Register_Masks VBAT Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define VBAT_VERID_FEATURE_MASK (0xFFFFU) #define VBAT_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number */ #define VBAT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK) #define VBAT_VERID_MINOR_MASK (0xFF0000U) #define VBAT_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define VBAT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK) #define VBAT_VERID_MAJOR_MASK (0xFF000000U) #define VBAT_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define VBAT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK) /*! @} */ /*! @name STATUSA - Status A */ /*! @{ */ #define VBAT_STATUSA_POR_DET_MASK (0x1U) #define VBAT_STATUSA_POR_DET_SHIFT (0U) /*! POR_DET - POR Detect Flag * 0b0..Not reset * 0b1..Reset * 0b0..No effect * 0b1..Clear the flag */ #define VBAT_STATUSA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_POR_DET_SHIFT)) & VBAT_STATUSA_POR_DET_MASK) #define VBAT_STATUSA_WAKEUP_FLAG_MASK (0x2U) #define VBAT_STATUSA_WAKEUP_FLAG_SHIFT (1U) /*! WAKEUP_FLAG - Wakeup Pin Flag * 0b0..Not asserted * 0b1..Asserted * 0b0..No effect * 0b1..Clear the flag */ #define VBAT_STATUSA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_WAKEUP_FLAG_SHIFT)) & VBAT_STATUSA_WAKEUP_FLAG_MASK) #define VBAT_STATUSA_TIMER0_FLAG_MASK (0x4U) #define VBAT_STATUSA_TIMER0_FLAG_SHIFT (2U) /*! TIMER0_FLAG - Bandgap Timer 0 Flag * 0b0..Not reached * 0b1..Reached * 0b0..No effect * 0b1..Clear the flag */ #define VBAT_STATUSA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER0_FLAG_SHIFT)) & VBAT_STATUSA_TIMER0_FLAG_MASK) #define VBAT_STATUSA_TIMER1_FLAG_MASK (0x8U) #define VBAT_STATUSA_TIMER1_FLAG_SHIFT (3U) /*! TIMER1_FLAG - Bandgap Timer 1 Flag * 0b0..Not reached * 0b1..Reached * 0b0..No effect * 0b1..Clear the flag */ #define VBAT_STATUSA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER1_FLAG_SHIFT)) & VBAT_STATUSA_TIMER1_FLAG_MASK) #define VBAT_STATUSA_LDO_RDY_MASK (0x10U) #define VBAT_STATUSA_LDO_RDY_SHIFT (4U) /*! LDO_RDY - LDO Ready * 0b0..Disabled (not ready) * 0b1..Enabled (ready) */ #define VBAT_STATUSA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LDO_RDY_SHIFT)) & VBAT_STATUSA_LDO_RDY_MASK) #define VBAT_STATUSA_OSC_RDY_MASK (0x20U) #define VBAT_STATUSA_OSC_RDY_SHIFT (5U) /*! OSC_RDY - OSC32k Ready * 0b0..Disabled (clock not ready) * 0b1..Enabled (clock ready) */ #define VBAT_STATUSA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_OSC_RDY_SHIFT)) & VBAT_STATUSA_OSC_RDY_MASK) #define VBAT_STATUSA_CLOCK_DET_MASK (0x40U) #define VBAT_STATUSA_CLOCK_DET_SHIFT (6U) /*! CLOCK_DET - Clock Detect * 0b0..Clock error not detected * 0b1..Clock error detected */ #define VBAT_STATUSA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CLOCK_DET_SHIFT)) & VBAT_STATUSA_CLOCK_DET_MASK) #define VBAT_STATUSA_CONFIG_DET_MASK (0x80U) #define VBAT_STATUSA_CONFIG_DET_SHIFT (7U) /*! CONFIG_DET - Configuration Detect Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define VBAT_STATUSA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CONFIG_DET_SHIFT)) & VBAT_STATUSA_CONFIG_DET_MASK) #define VBAT_STATUSA_VOLT_DET_MASK (0x100U) #define VBAT_STATUSA_VOLT_DET_SHIFT (8U) /*! VOLT_DET - Voltage Detect * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define VBAT_STATUSA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_VOLT_DET_SHIFT)) & VBAT_STATUSA_VOLT_DET_MASK) #define VBAT_STATUSA_TEMP_DET_MASK (0x200U) #define VBAT_STATUSA_TEMP_DET_SHIFT (9U) /*! TEMP_DET - Temperature Detect * 0b0..Temperature error not detected * 0b1..Temperature error detected */ #define VBAT_STATUSA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TEMP_DET_SHIFT)) & VBAT_STATUSA_TEMP_DET_MASK) #define VBAT_STATUSA_LIGHT_DET_MASK (0x400U) #define VBAT_STATUSA_LIGHT_DET_SHIFT (10U) /*! LIGHT_DET - Light Detect * 0b0..Light error not detected * 0b1..Light error detected */ #define VBAT_STATUSA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LIGHT_DET_SHIFT)) & VBAT_STATUSA_LIGHT_DET_MASK) #define VBAT_STATUSA_SEC0_DET_MASK (0x1000U) #define VBAT_STATUSA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect * 0b0..Security input 0 not detected * 0b1..Security input 0 detected */ #define VBAT_STATUSA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_SEC0_DET_SHIFT)) & VBAT_STATUSA_SEC0_DET_MASK) #define VBAT_STATUSA_IRQ0_DET_MASK (0x10000U) #define VBAT_STATUSA_IRQ0_DET_SHIFT (16U) /*! IRQ0_DET - Interrupt 0 Detect * 0b0..Not asserted * 0b1..Asserted */ #define VBAT_STATUSA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ0_DET_SHIFT)) & VBAT_STATUSA_IRQ0_DET_MASK) #define VBAT_STATUSA_IRQ1_DET_MASK (0x20000U) #define VBAT_STATUSA_IRQ1_DET_SHIFT (17U) /*! IRQ1_DET - Interrupt 1 Detect * 0b0..Not asserted * 0b1..Asserted */ #define VBAT_STATUSA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ1_DET_SHIFT)) & VBAT_STATUSA_IRQ1_DET_MASK) #define VBAT_STATUSA_IRQ2_DET_MASK (0x40000U) #define VBAT_STATUSA_IRQ2_DET_SHIFT (18U) /*! IRQ2_DET - Interrupt 2 Detect * 0b0..Not asserted * 0b1..Asserted */ #define VBAT_STATUSA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ2_DET_SHIFT)) & VBAT_STATUSA_IRQ2_DET_MASK) #define VBAT_STATUSA_IRQ3_DET_MASK (0x80000U) #define VBAT_STATUSA_IRQ3_DET_SHIFT (19U) /*! IRQ3_DET - Interrupt 3 Detect * 0b0..Not asserted * 0b1..Asserted */ #define VBAT_STATUSA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ3_DET_SHIFT)) & VBAT_STATUSA_IRQ3_DET_MASK) /*! @} */ /*! @name STATUSB - Status B */ /*! @{ */ #define VBAT_STATUSB_INVERSE_MASK (0xFFFFFU) #define VBAT_STATUSB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse value */ #define VBAT_STATUSB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSB_INVERSE_SHIFT)) & VBAT_STATUSB_INVERSE_MASK) /*! @} */ /*! @name IRQENA - Interrupt Enable A */ /*! @{ */ #define VBAT_IRQENA_POR_DET_MASK (0x1U) #define VBAT_IRQENA_POR_DET_SHIFT (0U) /*! POR_DET - POR Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_POR_DET_SHIFT)) & VBAT_IRQENA_POR_DET_MASK) #define VBAT_IRQENA_WAKEUP_FLAG_MASK (0x2U) #define VBAT_IRQENA_WAKEUP_FLAG_SHIFT (1U) /*! WAKEUP_FLAG - Wakeup Pin Flag * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_WAKEUP_FLAG_SHIFT)) & VBAT_IRQENA_WAKEUP_FLAG_MASK) #define VBAT_IRQENA_TIMER0_FLAG_MASK (0x4U) #define VBAT_IRQENA_TIMER0_FLAG_SHIFT (2U) /*! TIMER0_FLAG - Bandgap Timer 0 * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER0_FLAG_SHIFT)) & VBAT_IRQENA_TIMER0_FLAG_MASK) #define VBAT_IRQENA_TIMER1_FLAG_MASK (0x8U) #define VBAT_IRQENA_TIMER1_FLAG_SHIFT (3U) /*! TIMER1_FLAG - Bandgap Timer 2 * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER1_FLAG_SHIFT)) & VBAT_IRQENA_TIMER1_FLAG_MASK) #define VBAT_IRQENA_LDO_RDY_MASK (0x10U) #define VBAT_IRQENA_LDO_RDY_SHIFT (4U) /*! LDO_RDY - LDO Ready * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LDO_RDY_SHIFT)) & VBAT_IRQENA_LDO_RDY_MASK) #define VBAT_IRQENA_OSC_RDY_MASK (0x20U) #define VBAT_IRQENA_OSC_RDY_SHIFT (5U) /*! OSC_RDY - OSC32k Ready * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_OSC_RDY_SHIFT)) & VBAT_IRQENA_OSC_RDY_MASK) #define VBAT_IRQENA_CLOCK_DET_MASK (0x40U) #define VBAT_IRQENA_CLOCK_DET_SHIFT (6U) /*! CLOCK_DET - Clock Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CLOCK_DET_SHIFT)) & VBAT_IRQENA_CLOCK_DET_MASK) #define VBAT_IRQENA_CONFIG_DET_MASK (0x80U) #define VBAT_IRQENA_CONFIG_DET_SHIFT (7U) /*! CONFIG_DET - Configuration Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CONFIG_DET_SHIFT)) & VBAT_IRQENA_CONFIG_DET_MASK) #define VBAT_IRQENA_VOLT_DET_MASK (0x100U) #define VBAT_IRQENA_VOLT_DET_SHIFT (8U) /*! VOLT_DET - Voltage Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_VOLT_DET_SHIFT)) & VBAT_IRQENA_VOLT_DET_MASK) #define VBAT_IRQENA_TEMP_DET_MASK (0x200U) #define VBAT_IRQENA_TEMP_DET_SHIFT (9U) /*! TEMP_DET - Temperature Detect * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define VBAT_IRQENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TEMP_DET_SHIFT)) & VBAT_IRQENA_TEMP_DET_MASK) #define VBAT_IRQENA_LIGHT_DET_MASK (0x400U) #define VBAT_IRQENA_LIGHT_DET_SHIFT (10U) /*! LIGHT_DET - Light Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LIGHT_DET_SHIFT)) & VBAT_IRQENA_LIGHT_DET_MASK) #define VBAT_IRQENA_SEC0_DET_MASK (0x1000U) #define VBAT_IRQENA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_SEC0_DET_SHIFT)) & VBAT_IRQENA_SEC0_DET_MASK) #define VBAT_IRQENA_IRQ0_DET_MASK (0x10000U) #define VBAT_IRQENA_IRQ0_DET_SHIFT (16U) /*! IRQ0_DET - Interrupt 0 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ0_DET_SHIFT)) & VBAT_IRQENA_IRQ0_DET_MASK) #define VBAT_IRQENA_IRQ1_DET_MASK (0x20000U) #define VBAT_IRQENA_IRQ1_DET_SHIFT (17U) /*! IRQ1_DET - Interrupt 1 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ1_DET_SHIFT)) & VBAT_IRQENA_IRQ1_DET_MASK) #define VBAT_IRQENA_IRQ2_DET_MASK (0x40000U) #define VBAT_IRQENA_IRQ2_DET_SHIFT (18U) /*! IRQ2_DET - Interrupt 2 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ2_DET_SHIFT)) & VBAT_IRQENA_IRQ2_DET_MASK) #define VBAT_IRQENA_IRQ3_DET_MASK (0x80000U) #define VBAT_IRQENA_IRQ3_DET_SHIFT (19U) /*! IRQ3_DET - Interrupt 3 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_IRQENA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ3_DET_SHIFT)) & VBAT_IRQENA_IRQ3_DET_MASK) /*! @} */ /*! @name IRQENB - Interrupt Enable B */ /*! @{ */ #define VBAT_IRQENB_INVERSE_MASK (0xFFFFFU) #define VBAT_IRQENB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse Value */ #define VBAT_IRQENB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENB_INVERSE_SHIFT)) & VBAT_IRQENB_INVERSE_MASK) /*! @} */ /*! @name WAKENA - Wake-up Enable A */ /*! @{ */ #define VBAT_WAKENA_POR_DET_MASK (0x1U) #define VBAT_WAKENA_POR_DET_SHIFT (0U) /*! POR_DET - POR Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_POR_DET_SHIFT)) & VBAT_WAKENA_POR_DET_MASK) #define VBAT_WAKENA_WAKEUP_FLAG_MASK (0x2U) #define VBAT_WAKENA_WAKEUP_FLAG_SHIFT (1U) /*! WAKEUP_FLAG - Wake-up Pin Flag * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_WAKEUP_FLAG_SHIFT)) & VBAT_WAKENA_WAKEUP_FLAG_MASK) #define VBAT_WAKENA_TIMER0_FLAG_MASK (0x4U) #define VBAT_WAKENA_TIMER0_FLAG_SHIFT (2U) /*! TIMER0_FLAG - Bandgap Timer 0 * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER0_FLAG_SHIFT)) & VBAT_WAKENA_TIMER0_FLAG_MASK) #define VBAT_WAKENA_TIMER1_FLAG_MASK (0x8U) #define VBAT_WAKENA_TIMER1_FLAG_SHIFT (3U) /*! TIMER1_FLAG - Bandgap Timer 2 * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER1_FLAG_SHIFT)) & VBAT_WAKENA_TIMER1_FLAG_MASK) #define VBAT_WAKENA_LDO_RDY_MASK (0x10U) #define VBAT_WAKENA_LDO_RDY_SHIFT (4U) /*! LDO_RDY - LDO Ready * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LDO_RDY_SHIFT)) & VBAT_WAKENA_LDO_RDY_MASK) #define VBAT_WAKENA_OSC_RDY_MASK (0x20U) #define VBAT_WAKENA_OSC_RDY_SHIFT (5U) /*! OSC_RDY - OSC32K Ready * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_OSC_RDY_SHIFT)) & VBAT_WAKENA_OSC_RDY_MASK) #define VBAT_WAKENA_CLOCK_DET_MASK (0x40U) #define VBAT_WAKENA_CLOCK_DET_SHIFT (6U) /*! CLOCK_DET - Clock Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CLOCK_DET_SHIFT)) & VBAT_WAKENA_CLOCK_DET_MASK) #define VBAT_WAKENA_CONFIG_DET_MASK (0x80U) #define VBAT_WAKENA_CONFIG_DET_SHIFT (7U) /*! CONFIG_DET - Configuration Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CONFIG_DET_SHIFT)) & VBAT_WAKENA_CONFIG_DET_MASK) #define VBAT_WAKENA_VOLT_DET_MASK (0x100U) #define VBAT_WAKENA_VOLT_DET_SHIFT (8U) /*! VOLT_DET - Voltage Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_VOLT_DET_SHIFT)) & VBAT_WAKENA_VOLT_DET_MASK) #define VBAT_WAKENA_TEMP_DET_MASK (0x200U) #define VBAT_WAKENA_TEMP_DET_SHIFT (9U) /*! TEMP_DET - Temperature Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TEMP_DET_SHIFT)) & VBAT_WAKENA_TEMP_DET_MASK) #define VBAT_WAKENA_LIGHT_DET_MASK (0x400U) #define VBAT_WAKENA_LIGHT_DET_SHIFT (10U) /*! LIGHT_DET - Light Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LIGHT_DET_SHIFT)) & VBAT_WAKENA_LIGHT_DET_MASK) #define VBAT_WAKENA_SEC0_DET_MASK (0x1000U) #define VBAT_WAKENA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect * 0b0..Disabled * 0b1..Enabled */ #define VBAT_WAKENA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_SEC0_DET_SHIFT)) & VBAT_WAKENA_SEC0_DET_MASK) #define VBAT_WAKENA_IRQ0_DET_MASK (0x10000U) #define VBAT_WAKENA_IRQ0_DET_SHIFT (16U) /*! IRQ0_DET - Interrupt 0 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ0_DET_SHIFT)) & VBAT_WAKENA_IRQ0_DET_MASK) #define VBAT_WAKENA_IRQ1_DET_MASK (0x20000U) #define VBAT_WAKENA_IRQ1_DET_SHIFT (17U) /*! IRQ1_DET - Interrupt 1 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ1_DET_SHIFT)) & VBAT_WAKENA_IRQ1_DET_MASK) #define VBAT_WAKENA_IRQ2_DET_MASK (0x40000U) #define VBAT_WAKENA_IRQ2_DET_SHIFT (18U) /*! IRQ2_DET - Interrupt 2 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ2_DET_SHIFT)) & VBAT_WAKENA_IRQ2_DET_MASK) #define VBAT_WAKENA_IRQ3_DET_MASK (0x80000U) #define VBAT_WAKENA_IRQ3_DET_SHIFT (19U) /*! IRQ3_DET - Interrupt 3 Detect * 0b0..Disable * 0b1..Enable */ #define VBAT_WAKENA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ3_DET_SHIFT)) & VBAT_WAKENA_IRQ3_DET_MASK) /*! @} */ /*! @name WAKENB - Wake-up Enable B */ /*! @{ */ #define VBAT_WAKENB_INVERSE_MASK (0xFFFFFU) #define VBAT_WAKENB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse Value */ #define VBAT_WAKENB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENB_INVERSE_SHIFT)) & VBAT_WAKENB_INVERSE_MASK) /*! @} */ /*! @name TAMPERA - Tamper Enable A */ /*! @{ */ #define VBAT_TAMPERA_POR_DET_MASK (0x1U) #define VBAT_TAMPERA_POR_DET_SHIFT (0U) /*! POR_DET - POR Detect * 0b0..Tamper disabled * 0b1..Tamper enabled */ #define VBAT_TAMPERA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_POR_DET_SHIFT)) & VBAT_TAMPERA_POR_DET_MASK) #define VBAT_TAMPERA_CLOCK_DET_MASK (0x40U) #define VBAT_TAMPERA_CLOCK_DET_SHIFT (6U) /*! CLOCK_DET - Clock Detect * 0b0..Tamper disabled * 0b1..Tamper enabled */ #define VBAT_TAMPERA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CLOCK_DET_SHIFT)) & VBAT_TAMPERA_CLOCK_DET_MASK) #define VBAT_TAMPERA_CONFIG_DET_MASK (0x80U) #define VBAT_TAMPERA_CONFIG_DET_SHIFT (7U) /*! CONFIG_DET - Configuration Detect * 0b0..Tamper disabled * 0b1..Tamper enabled */ #define VBAT_TAMPERA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CONFIG_DET_SHIFT)) & VBAT_TAMPERA_CONFIG_DET_MASK) #define VBAT_TAMPERA_VOLT_DET_MASK (0x100U) #define VBAT_TAMPERA_VOLT_DET_SHIFT (8U) /*! VOLT_DET - Voltage Detect * 0b0..Tamper disabled * 0b1..Tamper enabled */ #define VBAT_TAMPERA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_VOLT_DET_SHIFT)) & VBAT_TAMPERA_VOLT_DET_MASK) #define VBAT_TAMPERA_TEMP_DET_MASK (0x200U) #define VBAT_TAMPERA_TEMP_DET_SHIFT (9U) /*! TEMP_DET - Temperature Detect * 0b0..Tamper disabled * 0b1..Tamper enabled */ #define VBAT_TAMPERA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_TEMP_DET_SHIFT)) & VBAT_TAMPERA_TEMP_DET_MASK) #define VBAT_TAMPERA_LIGHT_DET_MASK (0x400U) #define VBAT_TAMPERA_LIGHT_DET_SHIFT (10U) /*! LIGHT_DET - Light Detect * 0b0..Tamper disabled * 0b1..Tamper enabled */ #define VBAT_TAMPERA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_LIGHT_DET_SHIFT)) & VBAT_TAMPERA_LIGHT_DET_MASK) #define VBAT_TAMPERA_SEC0_DET_MASK (0x1000U) #define VBAT_TAMPERA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect * 0b0..Tamper disabled * 0b1..Tamper enabled */ #define VBAT_TAMPERA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_SEC0_DET_SHIFT)) & VBAT_TAMPERA_SEC0_DET_MASK) /*! @} */ /*! @name TAMPERB - Tamper Enable B */ /*! @{ */ #define VBAT_TAMPERB_INVERSE_MASK (0xFFFFU) #define VBAT_TAMPERB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse value */ #define VBAT_TAMPERB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERB_INVERSE_SHIFT)) & VBAT_TAMPERB_INVERSE_MASK) /*! @} */ /*! @name LOCKA - Lock A */ /*! @{ */ #define VBAT_LOCKA_LOCK_MASK (0x1U) #define VBAT_LOCKA_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b0..Disables lock * 0b1..Enables lock. Cleared by VBAT POR. */ #define VBAT_LOCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKA_LOCK_SHIFT)) & VBAT_LOCKA_LOCK_MASK) /*! @} */ /*! @name LOCKB - Lock B */ /*! @{ */ #define VBAT_LOCKB_LOCK_MASK (0x1U) #define VBAT_LOCKB_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b1..Disables lock * 0b0..Enables lock */ #define VBAT_LOCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKB_LOCK_SHIFT)) & VBAT_LOCKB_LOCK_MASK) /*! @} */ /*! @name WAKECFG - Wake-up Configuration */ /*! @{ */ #define VBAT_WAKECFG_OUT_MASK (0x1U) #define VBAT_WAKECFG_OUT_SHIFT (0U) /*! OUT - Output * 0b0..Logic zero (asserted) * 0b1..Logic one */ #define VBAT_WAKECFG_OUT(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKECFG_OUT_SHIFT)) & VBAT_WAKECFG_OUT_MASK) /*! @} */ /*! @name OSCCTLA - Oscillator Control A */ /*! @{ */ #define VBAT_OSCCTLA_OSC_EN_MASK (0x1U) #define VBAT_OSCCTLA_OSC_EN_SHIFT (0U) /*! OSC_EN - Crystal Oscillator Enable * 0b0..Disable * 0b1..Enable */ #define VBAT_OSCCTLA_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_EN_SHIFT)) & VBAT_OSCCTLA_OSC_EN_MASK) #define VBAT_OSCCTLA_OSC_BYP_EN_MASK (0x2U) #define VBAT_OSCCTLA_OSC_BYP_EN_SHIFT (1U) /*! OSC_BYP_EN - Crystal Oscillator Bypass Enable * 0b0..Does not bypass * 0b1..Bypass */ #define VBAT_OSCCTLA_OSC_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_BYP_EN_SHIFT)) & VBAT_OSCCTLA_OSC_BYP_EN_MASK) #define VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK (0xCU) #define VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT (2U) /*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external * crystal ESR values See the device datasheet for the ranges supported by this device * 0b00..ESR Range 0 * 0b01..ESR Range 1 * 0b10..ESR Range 2 * 0b11..ESR Range 3 */ #define VBAT_OSCCTLA_COARSE_AMP_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) #define VBAT_OSCCTLA_CAP_SEL_EN_MASK (0x80U) #define VBAT_OSCCTLA_CAP_SEL_EN_SHIFT (7U) /*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable * 0b0..Disable * 0b1..Enable */ #define VBAT_OSCCTLA_CAP_SEL_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_CAP_SEL_EN_SHIFT)) & VBAT_OSCCTLA_CAP_SEL_EN_MASK) #define VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK (0xF00U) #define VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT (8U) /*! EXTAL_CAP_SEL - Crystal Load Capacitance Selection * 0b0000..0 pF * 0b0001..2 pF * 0b0010..4 pF * 0b0011..6 pF * 0b0100..8 pF * 0b0101..10 pF * 0b0110..12 pF * 0b0111..14 pF * 0b1000..16 pF * 0b1001..18 pF * 0b1010..20 pF * 0b1011..22 pF * 0b1100..24 pF * 0b1101..26 pF * 0b1110..28 pF * 0b1111..30 pF */ #define VBAT_OSCCTLA_EXTAL_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK) #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) #define VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT (12U) /*! XTAL_CAP_SEL - Crystal Load Capacitance Selection * 0b0000..0 pF * 0b0001..2 pF * 0b0010..4 pF * 0b0011..6 pF * 0b0100..8 pF * 0b0101..10 pF * 0b0110..12 pF * 0b0111..14 pF * 0b1000..16 pF * 0b1001..18 pF * 0b1010..20 pF * 0b1011..22 pF * 0b1100..24 pF * 0b1101..26 pF * 0b1110..28 pF * 0b1111..30 pF */ #define VBAT_OSCCTLA_XTAL_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK) #define VBAT_OSCCTLA_MODE_EN_MASK (0x30000U) #define VBAT_OSCCTLA_MODE_EN_SHIFT (16U) /*! MODE_EN - Mode Enable * 0b00..Normal mode * 0b01..Startup mode * 0b11..Low power mode */ #define VBAT_OSCCTLA_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_MODE_EN_SHIFT)) & VBAT_OSCCTLA_MODE_EN_MASK) #define VBAT_OSCCTLA_SUPPLY_DET_MASK (0xC0000U) #define VBAT_OSCCTLA_SUPPLY_DET_SHIFT (18U) /*! SUPPLY_DET - Supply Detector Trim * 0b00..VBAT supply is less than 3V * 0b01..VBAT supply is greater than 3V */ #define VBAT_OSCCTLA_SUPPLY_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_SUPPLY_DET_SHIFT)) & VBAT_OSCCTLA_SUPPLY_DET_MASK) /*! @} */ /*! @name OSCCTLB - Oscillator Control B */ /*! @{ */ #define VBAT_OSCCTLB_INVERSE_MASK (0xFFFFFU) #define VBAT_OSCCTLB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse Value */ #define VBAT_OSCCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLB_INVERSE_SHIFT)) & VBAT_OSCCTLB_INVERSE_MASK) /*! @} */ /*! @name OSCCFGA - Oscillator Configuration A */ /*! @{ */ #define VBAT_OSCCFGA_CMP_TRIM_MASK (0x3U) #define VBAT_OSCCFGA_CMP_TRIM_SHIFT (0U) /*! CMP_TRIM - Comparator Trim * 0b00..760 mV * 0b01..770 mV * 0b11..740 mV */ #define VBAT_OSCCFGA_CMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CMP_TRIM_SHIFT)) & VBAT_OSCCFGA_CMP_TRIM_MASK) #define VBAT_OSCCFGA_CAP2_TRIM_MASK (0x4U) #define VBAT_OSCCFGA_CAP2_TRIM_SHIFT (2U) /*! CAP2_TRIM - CAP2_TRIM */ #define VBAT_OSCCFGA_CAP2_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP2_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP2_TRIM_MASK) #define VBAT_OSCCFGA_DLY_TRIM_MASK (0x78U) #define VBAT_OSCCFGA_DLY_TRIM_SHIFT (3U) /*! DLY_TRIM - Delay Trim * 0b0000..P current 9(nA) and N Current 6(nA) * 0b0001..P current 13(nA) and N Current 6(nA) * 0b0011..P current 4(nA) and N Current 6(nA) * 0b0100..P current 9(nA) and N Current 4(nA) * 0b0101..P current 13(nA) and N Current 4(nA) * 0b0111..P current 4(nA) and N Current 4(nA) * 0b1000..P current 9(nA) and N Current 2(nA) * 0b1001..P current 13(nA) and N Current 2(nA) * 0b1011..P current 4(nA) and N Current 2(nA) */ #define VBAT_OSCCFGA_DLY_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_DLY_TRIM_SHIFT)) & VBAT_OSCCFGA_DLY_TRIM_MASK) #define VBAT_OSCCFGA_CAP_TRIM_MASK (0x180U) #define VBAT_OSCCFGA_CAP_TRIM_SHIFT (7U) /*! CAP_TRIM - Capacitor Trim * 0b00..Default (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 00 ) * 0b01..-1us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 01) * 0b10..-2us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 10) * 0b11..-2.5us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 11) */ #define VBAT_OSCCFGA_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP_TRIM_MASK) #define VBAT_OSCCFGA_INIT_TRIM_MASK (0xE00U) #define VBAT_OSCCFGA_INIT_TRIM_SHIFT (9U) /*! INIT_TRIM - Initialization Trim * 0b000..8 s * 0b001..4 s * 0b010..2 s * 0b011..1 s * 0b100..0.5 s * 0b101..0.25 s * 0b110..0.125 s * 0b111..0.5 ms */ #define VBAT_OSCCFGA_INIT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_INIT_TRIM_SHIFT)) & VBAT_OSCCFGA_INIT_TRIM_MASK) /*! @} */ /*! @name OSCCFGB - Oscillator Configuration B */ /*! @{ */ #define VBAT_OSCCFGB_INVERSE_MASK (0xFFFU) #define VBAT_OSCCFGB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse Value */ #define VBAT_OSCCFGB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGB_INVERSE_SHIFT)) & VBAT_OSCCFGB_INVERSE_MASK) /*! @} */ /*! @name OSCLCKA - Oscillator Lock A */ /*! @{ */ #define VBAT_OSCLCKA_LOCK_MASK (0x1U) #define VBAT_OSCLCKA_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b0..Do not block * 0b1..Block */ #define VBAT_OSCLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKA_LOCK_SHIFT)) & VBAT_OSCLCKA_LOCK_MASK) /*! @} */ /*! @name OSCLCKB - Oscillator Lock B */ /*! @{ */ #define VBAT_OSCLCKB_LOCK_MASK (0x1U) #define VBAT_OSCLCKB_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b1..Do not block * 0b0..Block */ #define VBAT_OSCLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKB_LOCK_SHIFT)) & VBAT_OSCLCKB_LOCK_MASK) /*! @} */ /*! @name OSCCLKE - Oscillator Clock Enable */ /*! @{ */ #define VBAT_OSCCLKE_CLKE_MASK (0xFU) #define VBAT_OSCCLKE_CLKE_SHIFT (0U) /*! CLKE - Clock Enable */ #define VBAT_OSCCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCLKE_CLKE_SHIFT)) & VBAT_OSCCLKE_CLKE_MASK) /*! @} */ /*! @name FROCTLA - FRO16K Control A */ /*! @{ */ #define VBAT_FROCTLA_FRO_EN_MASK (0x1U) #define VBAT_FROCTLA_FRO_EN_SHIFT (0U) /*! FRO_EN - FRO16K Enable * 0b0..Disable * 0b1..Enable */ #define VBAT_FROCTLA_FRO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK) /*! @} */ /*! @name FROCTLB - FRO16K Control B */ /*! @{ */ #define VBAT_FROCTLB_INVERSE_MASK (0x1U) #define VBAT_FROCTLB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse Value */ #define VBAT_FROCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLB_INVERSE_SHIFT)) & VBAT_FROCTLB_INVERSE_MASK) /*! @} */ /*! @name FROLCKA - FRO16K Lock A */ /*! @{ */ #define VBAT_FROLCKA_LOCK_MASK (0x1U) #define VBAT_FROLCKA_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b0..Do not block * 0b1..Block */ #define VBAT_FROLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK) /*! @} */ /*! @name FROLCKB - FRO16K Lock B */ /*! @{ */ #define VBAT_FROLCKB_LOCK_MASK (0x1U) #define VBAT_FROLCKB_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b1..Do not block * 0b0..Block */ #define VBAT_FROLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKB_LOCK_SHIFT)) & VBAT_FROLCKB_LOCK_MASK) /*! @} */ /*! @name FROCLKE - FRO16K Clock Enable */ /*! @{ */ #define VBAT_FROCLKE_CLKE_MASK (0xFU) #define VBAT_FROCLKE_CLKE_SHIFT (0U) /*! CLKE - Clock Enable */ #define VBAT_FROCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK) /*! @} */ /*! @name LDOCTLA - LDO_RAM Control A */ /*! @{ */ #define VBAT_LDOCTLA_BG_EN_MASK (0x1U) #define VBAT_LDOCTLA_BG_EN_SHIFT (0U) /*! BG_EN - Bandgap Enable * 0b0..Disable * 0b1..Enable */ #define VBAT_LDOCTLA_BG_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_BG_EN_SHIFT)) & VBAT_LDOCTLA_BG_EN_MASK) #define VBAT_LDOCTLA_LDO_EN_MASK (0x2U) #define VBAT_LDOCTLA_LDO_EN_SHIFT (1U) /*! LDO_EN - LDO Enable * 0b0..Disable * 0b1..Enable */ #define VBAT_LDOCTLA_LDO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_LDO_EN_SHIFT)) & VBAT_LDOCTLA_LDO_EN_MASK) #define VBAT_LDOCTLA_REFRESH_EN_MASK (0x4U) #define VBAT_LDOCTLA_REFRESH_EN_SHIFT (2U) /*! REFRESH_EN - Refresh Enable * 0b0..Refresh mode is disabled * 0b1..Refresh mode is enabled for low power operation */ #define VBAT_LDOCTLA_REFRESH_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_REFRESH_EN_SHIFT)) & VBAT_LDOCTLA_REFRESH_EN_MASK) /*! @} */ /*! @name LDOCTLB - LDO_RAM Control B */ /*! @{ */ #define VBAT_LDOCTLB_INVERSE_MASK (0x7U) #define VBAT_LDOCTLB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse Value */ #define VBAT_LDOCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLB_INVERSE_SHIFT)) & VBAT_LDOCTLB_INVERSE_MASK) /*! @} */ /*! @name LDOLCKA - LDO_RAM Lock A */ /*! @{ */ #define VBAT_LDOLCKA_LOCK_MASK (0x1U) #define VBAT_LDOLCKA_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b0..Do not block * 0b1..Block */ #define VBAT_LDOLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKA_LOCK_SHIFT)) & VBAT_LDOLCKA_LOCK_MASK) /*! @} */ /*! @name LDOLCKB - LDO_RAM Lock B */ /*! @{ */ #define VBAT_LDOLCKB_LOCK_MASK (0x1U) #define VBAT_LDOLCKB_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b1..Do not block * 0b0..Block */ #define VBAT_LDOLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKB_LOCK_SHIFT)) & VBAT_LDOLCKB_LOCK_MASK) /*! @} */ /*! @name LDORAMC - RAM Control */ /*! @{ */ #define VBAT_LDORAMC_ISO_MASK (0x1U) #define VBAT_LDORAMC_ISO_SHIFT (0U) /*! ISO - Isolate SRAM * 0b0..State follows the chip power modes * 0b1..Isolates SRAM and places it in Low-Power Retention mode */ #define VBAT_LDORAMC_ISO(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_ISO_SHIFT)) & VBAT_LDORAMC_ISO_MASK) #define VBAT_LDORAMC_SWI_MASK (0x2U) #define VBAT_LDORAMC_SWI_SHIFT (1U) /*! SWI - Switch SRAM * 0b0..Supply follows the chip power modes * 0b1..LDO_RAM powers the array */ #define VBAT_LDORAMC_SWI(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_SWI_SHIFT)) & VBAT_LDORAMC_SWI_MASK) #define VBAT_LDORAMC_RET0_MASK (0x100U) #define VBAT_LDORAMC_RET0_SHIFT (8U) /*! RET0 - Retention * 0b0..Corresponding SRAM array is retained in low-power modes * 0b1..Corresponding SRAM array is not retained in low-power modes */ #define VBAT_LDORAMC_RET0(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET0_SHIFT)) & VBAT_LDORAMC_RET0_MASK) #define VBAT_LDORAMC_RET1_MASK (0x200U) #define VBAT_LDORAMC_RET1_SHIFT (9U) /*! RET1 - Retention * 0b0..Corresponding SRAM array is retained in low-power modes * 0b1..Corresponding SRAM array is not retained in low-power modes */ #define VBAT_LDORAMC_RET1(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET1_SHIFT)) & VBAT_LDORAMC_RET1_MASK) #define VBAT_LDORAMC_RET2_MASK (0x400U) #define VBAT_LDORAMC_RET2_SHIFT (10U) /*! RET2 - Retention * 0b0..Corresponding SRAM array is retained in low-power modes * 0b1..Corresponding SRAM array is not retained in low-power modes */ #define VBAT_LDORAMC_RET2(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET2_SHIFT)) & VBAT_LDORAMC_RET2_MASK) #define VBAT_LDORAMC_RET3_MASK (0x800U) #define VBAT_LDORAMC_RET3_SHIFT (11U) /*! RET3 - Retention * 0b0..Corresponding SRAM array is retained in low-power modes * 0b1..Corresponding SRAM array is not retained in low-power modes */ #define VBAT_LDORAMC_RET3(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET3_SHIFT)) & VBAT_LDORAMC_RET3_MASK) /*! @} */ /*! @name LDOTIMER0 - Bandgap Timer 0 */ /*! @{ */ #define VBAT_LDOTIMER0_TIMCFG_MASK (0x7U) #define VBAT_LDOTIMER0_TIMCFG_SHIFT (0U) /*! TIMCFG - Timeout Configuration * 0b111..7.8125 ms * 0b110..15.625 ms * 0b101..31.25 ms * 0b100..62.5 ms * 0b011..125 ms * 0b010..250 ms * 0b001..500 ms * 0b000..1 s */ #define VBAT_LDOTIMER0_TIMCFG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMCFG_SHIFT)) & VBAT_LDOTIMER0_TIMCFG_MASK) #define VBAT_LDOTIMER0_TIMEN_MASK (0x80000000U) #define VBAT_LDOTIMER0_TIMEN_SHIFT (31U) /*! TIMEN - Bandgap Timeout Period Enable * 0b0..Disable * 0b1..Enable */ #define VBAT_LDOTIMER0_TIMEN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMEN_SHIFT)) & VBAT_LDOTIMER0_TIMEN_MASK) /*! @} */ /*! @name LDOTIMER1 - Bandgap Timer 1 */ /*! @{ */ #define VBAT_LDOTIMER1_TIMCFG_MASK (0xFFFFFFU) #define VBAT_LDOTIMER1_TIMCFG_SHIFT (0U) /*! TIMCFG - Timeout Configuration */ #define VBAT_LDOTIMER1_TIMCFG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMCFG_SHIFT)) & VBAT_LDOTIMER1_TIMCFG_MASK) #define VBAT_LDOTIMER1_TIMEN_MASK (0x80000000U) #define VBAT_LDOTIMER1_TIMEN_SHIFT (31U) /*! TIMEN - Bandgap Timeout Period Enable * 0b0..Disable * 0b1..Enable */ #define VBAT_LDOTIMER1_TIMEN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMEN_SHIFT)) & VBAT_LDOTIMER1_TIMEN_MASK) /*! @} */ /*! @name MONCTLA - CLKMON Control A */ /*! @{ */ #define VBAT_MONCTLA_MON_EN_MASK (0x1U) #define VBAT_MONCTLA_MON_EN_SHIFT (0U) /*! MON_EN - CLKMON Enable * 0b0..CLKMON is disabled * 0b1..CLKMON is enabled */ #define VBAT_MONCTLA_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLA_MON_EN_SHIFT)) & VBAT_MONCTLA_MON_EN_MASK) /*! @} */ /*! @name MONCTLB - CLKMON Control B */ /*! @{ */ #define VBAT_MONCTLB_INVERSE_MASK (0x1U) #define VBAT_MONCTLB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse value */ #define VBAT_MONCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLB_INVERSE_SHIFT)) & VBAT_MONCTLB_INVERSE_MASK) /*! @} */ /*! @name MONCFGA - CLKMON Configuration A */ /*! @{ */ #define VBAT_MONCFGA_FREQ_TRIM_MASK (0x3U) #define VBAT_MONCFGA_FREQ_TRIM_SHIFT (0U) /*! FREQ_TRIM - Frequency Trim * 0b00..Clock monitor asserts 2 cycle after expected edge * 0b01..Clock monitor asserts 4 cycles after expected edge * 0b10..Clock monitor asserts 6 cycles after expected edge * 0b11..Clock monitor asserts 8 cycles after expected edge */ #define VBAT_MONCFGA_FREQ_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_FREQ_TRIM_SHIFT)) & VBAT_MONCFGA_FREQ_TRIM_MASK) #define VBAT_MONCFGA_DIVIDE_TRIM_MASK (0x4U) #define VBAT_MONCFGA_DIVIDE_TRIM_SHIFT (2U) /*! DIVIDE_TRIM - Divide Trim * 0b0..Clock monitor operates at 1 kHz * 0b1..Clock monitor operates at 64 Hz */ #define VBAT_MONCFGA_DIVIDE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_DIVIDE_TRIM_SHIFT)) & VBAT_MONCFGA_DIVIDE_TRIM_MASK) #define VBAT_MONCFGA_RSVD_TRIM_MASK (0xF8U) #define VBAT_MONCFGA_RSVD_TRIM_SHIFT (3U) /*! RSVD_TRIM - Reserved Trim */ #define VBAT_MONCFGA_RSVD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_RSVD_TRIM_SHIFT)) & VBAT_MONCFGA_RSVD_TRIM_MASK) /*! @} */ /*! @name MONCFGB - CLKMON Configuration B */ /*! @{ */ #define VBAT_MONCFGB_INVERSE_MASK (0xFFU) #define VBAT_MONCFGB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse value */ #define VBAT_MONCFGB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGB_INVERSE_SHIFT)) & VBAT_MONCFGB_INVERSE_MASK) /*! @} */ /*! @name MONLCKA - CLKMON Lock A */ /*! @{ */ #define VBAT_MONLCKA_LOCK_MASK (0x1U) #define VBAT_MONLCKA_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b0..Lock is disabled * 0b1..Lock is enabled */ #define VBAT_MONLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKA_LOCK_SHIFT)) & VBAT_MONLCKA_LOCK_MASK) /*! @} */ /*! @name MONLCKB - CLKMON Lock B */ /*! @{ */ #define VBAT_MONLCKB_LOCK_MASK (0x1U) #define VBAT_MONLCKB_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b1..Lock is disabled * 0b0..Lock is enabled */ #define VBAT_MONLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKB_LOCK_SHIFT)) & VBAT_MONLCKB_LOCK_MASK) /*! @} */ /*! @name TAMCTLA - TAMPER Control A */ /*! @{ */ #define VBAT_TAMCTLA_VOLT_EN_MASK (0x1U) #define VBAT_TAMCTLA_VOLT_EN_SHIFT (0U) /*! VOLT_EN - Voltage Detect Enable * 0b0..Voltage detect is disabled * 0b1..Voltage detect is enabled */ #define VBAT_TAMCTLA_VOLT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_VOLT_EN_SHIFT)) & VBAT_TAMCTLA_VOLT_EN_MASK) #define VBAT_TAMCTLA_TEMP_EN_MASK (0x2U) #define VBAT_TAMCTLA_TEMP_EN_SHIFT (1U) /*! TEMP_EN - Temperature Detect Enable * 0b0..Temperature detect is disabled * 0b1..Temperature detect is enabled */ #define VBAT_TAMCTLA_TEMP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_TEMP_EN_SHIFT)) & VBAT_TAMCTLA_TEMP_EN_MASK) #define VBAT_TAMCTLA_LIGHT_EN_MASK (0x4U) #define VBAT_TAMCTLA_LIGHT_EN_SHIFT (2U) /*! LIGHT_EN - Light Detect Enable * 0b0..Light detect is disabled * 0b1..Light detect is enabled */ #define VBAT_TAMCTLA_LIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_LIGHT_EN_SHIFT)) & VBAT_TAMCTLA_LIGHT_EN_MASK) /*! @} */ /*! @name TAMCTLB - TAMPER Control B */ /*! @{ */ #define VBAT_TAMCTLB_INVERSE_MASK (0xFU) #define VBAT_TAMCTLB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse value */ #define VBAT_TAMCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLB_INVERSE_SHIFT)) & VBAT_TAMCTLB_INVERSE_MASK) /*! @} */ /*! @name TAMLCKA - TAMPER Lock A */ /*! @{ */ #define VBAT_TAMLCKA_LOCK_MASK (0x1U) #define VBAT_TAMLCKA_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b0..Lock is disabled * 0b1..Lock is enabled */ #define VBAT_TAMLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKA_LOCK_SHIFT)) & VBAT_TAMLCKA_LOCK_MASK) /*! @} */ /*! @name TAMLCKB - TAMPER Lock B */ /*! @{ */ #define VBAT_TAMLCKB_LOCK_MASK (0x1U) #define VBAT_TAMLCKB_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b1..Lock is disabled * 0b0..Lock is enabled */ #define VBAT_TAMLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKB_LOCK_SHIFT)) & VBAT_TAMLCKB_LOCK_MASK) /*! @} */ /*! @name SWICTLA - Switch Control A */ /*! @{ */ #define VBAT_SWICTLA_SWI_EN_MASK (0x1U) #define VBAT_SWICTLA_SWI_EN_SHIFT (0U) /*! SWI_EN - Switch Enable * 0b0..VDD_BAT * 0b1..VDD_SYS */ #define VBAT_SWICTLA_SWI_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_SWI_EN_SHIFT)) & VBAT_SWICTLA_SWI_EN_MASK) #define VBAT_SWICTLA_LP_EN_MASK (0x2U) #define VBAT_SWICTLA_LP_EN_SHIFT (1U) /*! LP_EN - Low Power Enable * 0b0..VDD_BAT always supplies VBAT modules in low-power modes * 0b1..VDD_SYS always supplies VBAT modules if SWI_EN is also 1 */ #define VBAT_SWICTLA_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_LP_EN_SHIFT)) & VBAT_SWICTLA_LP_EN_MASK) /*! @} */ /*! @name SWICTLB - Switch Control B */ /*! @{ */ #define VBAT_SWICTLB_INVERSE_MASK (0x3U) #define VBAT_SWICTLB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse Value */ #define VBAT_SWICTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLB_INVERSE_SHIFT)) & VBAT_SWICTLB_INVERSE_MASK) /*! @} */ /*! @name SWILCKA - Switch Lock A */ /*! @{ */ #define VBAT_SWILCKA_LOCK_MASK (0x1U) #define VBAT_SWILCKA_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b0..Do not block * 0b1..Block */ #define VBAT_SWILCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKA_LOCK_SHIFT)) & VBAT_SWILCKA_LOCK_MASK) /*! @} */ /*! @name SWILCKB - Switch Lock B */ /*! @{ */ #define VBAT_SWILCKB_LOCK_MASK (0x1U) #define VBAT_SWILCKB_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b1..Do not block * 0b0..Block */ #define VBAT_SWILCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKB_LOCK_SHIFT)) & VBAT_SWILCKB_LOCK_MASK) /*! @} */ /*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */ /*! @{ */ #define VBAT_WAKEUP_WAKEUPA_REG_MASK (0xFFFFFFFFU) #define VBAT_WAKEUP_WAKEUPA_REG_SHIFT (0U) /*! REG - Register */ #define VBAT_WAKEUP_WAKEUPA_REG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK) /*! @} */ /* The count of VBAT_WAKEUP_WAKEUPA */ #define VBAT_WAKEUP_WAKEUPA_COUNT (2U) /*! @name WAKEUP_WAKEUPB - Wakeup 0 Register B */ /*! @{ */ #define VBAT_WAKEUP_WAKEUPB_INVERSE_MASK (0xFFFFFFFFU) #define VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT (0U) /*! INVERSE - Inverse value */ #define VBAT_WAKEUP_WAKEUPB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT)) & VBAT_WAKEUP_WAKEUPB_INVERSE_MASK) /*! @} */ /* The count of VBAT_WAKEUP_WAKEUPB */ #define VBAT_WAKEUP_WAKEUPB_COUNT (2U) /*! @name WAKLCKA - Wakeup Lock A */ /*! @{ */ #define VBAT_WAKLCKA_LOCK_MASK (0x1U) #define VBAT_WAKLCKA_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b0..Lock is disabled * 0b1..Lock is enabled */ #define VBAT_WAKLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK) /*! @} */ /*! @name WAKLCKB - Wakeup Lock B */ /*! @{ */ #define VBAT_WAKLCKB_LOCK_MASK (0x1U) #define VBAT_WAKLCKB_LOCK_SHIFT (0U) /*! LOCK - Lock * 0b1..Lock is disabled * 0b0..Lock is enabled */ #define VBAT_WAKLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKB_LOCK_SHIFT)) & VBAT_WAKLCKB_LOCK_MASK) /*! @} */ /*! * @} */ /* end of group VBAT_Register_Masks */ /* VBAT - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral VBAT0 base address */ #define VBAT0_BASE (0x50059000u) /** Peripheral VBAT0 base address */ #define VBAT0_BASE_NS (0x40059000u) /** Peripheral VBAT0 base pointer */ #define VBAT0 ((VBAT_Type *)VBAT0_BASE) /** Peripheral VBAT0 base pointer */ #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) /** Array initializer of VBAT peripheral base addresses */ #define VBAT_BASE_ADDRS { VBAT0_BASE } /** Array initializer of VBAT peripheral base pointers */ #define VBAT_BASE_PTRS { VBAT0 } /** Array initializer of VBAT peripheral base addresses */ #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } /** Array initializer of VBAT peripheral base pointers */ #define VBAT_BASE_PTRS_NS { VBAT0_NS } #else /** Peripheral VBAT0 base address */ #define VBAT0_BASE (0x40059000u) /** Peripheral VBAT0 base pointer */ #define VBAT0 ((VBAT_Type *)VBAT0_BASE) /** Array initializer of VBAT peripheral base addresses */ #define VBAT_BASE_ADDRS { VBAT0_BASE } /** Array initializer of VBAT peripheral base pointers */ #define VBAT_BASE_PTRS { VBAT0 } #endif /*! * @} */ /* end of group VBAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VREF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer * @{ */ /** VREF - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t CSR; /**< Control and Status, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t UTRIM; /**< User Trim, offset: 0x10 */ } VREF_Type; /* ---------------------------------------------------------------------------- -- VREF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Register_Masks VREF Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define VREF_VERID_FEATURE_MASK (0xFFFFU) #define VREF_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number */ #define VREF_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK) #define VREF_VERID_MINOR_MASK (0xFF0000U) #define VREF_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define VREF_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK) #define VREF_VERID_MAJOR_MASK (0xFF000000U) #define VREF_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define VREF_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK) /*! @} */ /*! @name CSR - Control and Status */ /*! @{ */ #define VREF_CSR_HCBGEN_MASK (0x1U) #define VREF_CSR_HCBGEN_SHIFT (0U) /*! HCBGEN - HC Bandgap Enabled * 0b0..Disables * 0b1..Enables */ #define VREF_CSR_HCBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK) #define VREF_CSR_LPBGEN_MASK (0x2U) #define VREF_CSR_LPBGEN_SHIFT (1U) /*! LPBGEN - Low-Power Bandgap Enable * 0b0..Disables * 0b1..Enables */ #define VREF_CSR_LPBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK) #define VREF_CSR_LPBG_BUF_EN_MASK (0x4U) #define VREF_CSR_LPBG_BUF_EN_SHIFT (2U) /*! LPBG_BUF_EN - Low-Power Bandgap Buffer Enable * 0b0..Disables * 0b1..Enables */ #define VREF_CSR_LPBG_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK) #define VREF_CSR_CHOPEN_MASK (0x8U) #define VREF_CSR_CHOPEN_SHIFT (3U) /*! CHOPEN - Chop Oscillator Enable * 0b0..Disables * 0b1..Enables */ #define VREF_CSR_CHOPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK) #define VREF_CSR_ICOMPEN_MASK (0x10U) #define VREF_CSR_ICOMPEN_SHIFT (4U) /*! ICOMPEN - Current Compensation Enable * 0b0..Disables * 0b1..Enables */ #define VREF_CSR_ICOMPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK) #define VREF_CSR_REGEN_MASK (0x20U) #define VREF_CSR_REGEN_SHIFT (5U) /*! REGEN - Regulator Enable * 0b0..Disables * 0b1..Enables */ #define VREF_CSR_REGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK) #define VREF_CSR_HI_PWR_LV_MASK (0x800U) #define VREF_CSR_HI_PWR_LV_SHIFT (11U) /*! HI_PWR_LV - High-Power Level * 0b0..Low-power * 0b1..High-power */ #define VREF_CSR_HI_PWR_LV(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK) #define VREF_CSR_BUF21EN_MASK (0x10000U) #define VREF_CSR_BUF21EN_SHIFT (16U) /*! BUF21EN - Internal Buffer21 Enable * 0b0..Disables * 0b1..Enables */ #define VREF_CSR_BUF21EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK) #define VREF_CSR_VREFST_MASK (0x80000000U) #define VREF_CSR_VREFST_SHIFT (31U) /*! VREFST - Internal HC Voltage Reference Stable * 0b0..Disabled and unstable * 0b1..Stable */ #define VREF_CSR_VREFST(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK) /*! @} */ /*! @name UTRIM - User Trim */ /*! @{ */ #define VREF_UTRIM_TRIM2V1_MASK (0xFU) #define VREF_UTRIM_TRIM2V1_SHIFT (0U) /*! TRIM2V1 - VREF 2.1 V Trim */ #define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) #define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) #define VREF_UTRIM_VREFTRIM_SHIFT (8U) /*! VREFTRIM - VREF Trim */ #define VREF_UTRIM_VREFTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK) /*! @} */ /*! * @} */ /* end of group VREF_Register_Masks */ /* VREF - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral VREF0 base address */ #define VREF0_BASE (0x50111000u) /** Peripheral VREF0 base address */ #define VREF0_BASE_NS (0x40111000u) /** Peripheral VREF0 base pointer */ #define VREF0 ((VREF_Type *)VREF0_BASE) /** Peripheral VREF0 base pointer */ #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) /** Array initializer of VREF peripheral base addresses */ #define VREF_BASE_ADDRS { VREF0_BASE } /** Array initializer of VREF peripheral base pointers */ #define VREF_BASE_PTRS { VREF0 } /** Array initializer of VREF peripheral base addresses */ #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } /** Array initializer of VREF peripheral base pointers */ #define VREF_BASE_PTRS_NS { VREF0_NS } #else /** Peripheral VREF0 base address */ #define VREF0_BASE (0x40111000u) /** Peripheral VREF0 base pointer */ #define VREF0 ((VREF_Type *)VREF0_BASE) /** Array initializer of VREF peripheral base addresses */ #define VREF_BASE_ADDRS { VREF0_BASE } /** Array initializer of VREF peripheral base pointers */ #define VREF_BASE_PTRS { VREF0 } #endif /*! * @} */ /* end of group VREF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WUU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer * @{ */ /** WUU - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t PE1; /**< Pin Enable 1, offset: 0x8 */ __IO uint32_t PE2; /**< Pin Enable 2, offset: 0xC */ uint8_t RESERVED_0[8]; __IO uint32_t ME; /**< Module Interrupt Enable, offset: 0x18 */ __IO uint32_t DE; /**< Module DMA/Trigger Enable, offset: 0x1C */ __IO uint32_t PF; /**< Pin Flag, offset: 0x20 */ uint8_t RESERVED_1[12]; __IO uint32_t FILT; /**< Pin Filter, offset: 0x30 */ uint8_t RESERVED_2[4]; __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */ __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */ uint8_t RESERVED_3[8]; __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */ uint8_t RESERVED_4[4]; __IO uint32_t PMC; /**< Pin Mode Configuration, offset: 0x50 */ uint8_t RESERVED_5[4]; __IO uint32_t FMC; /**< Pin Filter Mode Configuration, offset: 0x58 */ } WUU_Type; /* ---------------------------------------------------------------------------- -- WUU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WUU_Register_Masks WUU Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define WUU_VERID_FEATURE_MASK (0xFFFFU) #define WUU_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for * external pin/filter detection during all power modes enabled. * *.. */ #define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) #define WUU_VERID_MINOR_MASK (0xFF0000U) #define WUU_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define WUU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK) #define WUU_VERID_MAJOR_MASK (0xFF000000U) #define WUU_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define WUU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define WUU_PARAM_FILTERS_MASK (0xFFU) #define WUU_PARAM_FILTERS_SHIFT (0U) /*! FILTERS - Filter Number */ #define WUU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK) #define WUU_PARAM_DMAS_MASK (0xFF00U) #define WUU_PARAM_DMAS_SHIFT (8U) /*! DMAS - DMA Number */ #define WUU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK) #define WUU_PARAM_MODULES_MASK (0xFF0000U) #define WUU_PARAM_MODULES_SHIFT (16U) /*! MODULES - Module Number */ #define WUU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK) #define WUU_PARAM_PINS_MASK (0xFF000000U) #define WUU_PARAM_PINS_SHIFT (24U) /*! PINS - Pin Number */ #define WUU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK) /*! @} */ /*! @name PE1 - Pin Enable 1 */ /*! @{ */ #define WUU_PE1_WUPE0_MASK (0x3U) #define WUU_PE1_WUPE0_SHIFT (0U) /*! WUPE0 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE0_SHIFT)) & WUU_PE1_WUPE0_MASK) #define WUU_PE1_WUPE1_MASK (0xCU) #define WUU_PE1_WUPE1_SHIFT (2U) /*! WUPE1 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE1_SHIFT)) & WUU_PE1_WUPE1_MASK) #define WUU_PE1_WUPE2_MASK (0x30U) #define WUU_PE1_WUPE2_SHIFT (4U) /*! WUPE2 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK) #define WUU_PE1_WUPE3_MASK (0xC0U) #define WUU_PE1_WUPE3_SHIFT (6U) /*! WUPE3 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK) #define WUU_PE1_WUPE4_MASK (0x300U) #define WUU_PE1_WUPE4_SHIFT (8U) /*! WUPE4 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK) #define WUU_PE1_WUPE5_MASK (0xC00U) #define WUU_PE1_WUPE5_SHIFT (10U) /*! WUPE5 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK) #define WUU_PE1_WUPE6_MASK (0x3000U) #define WUU_PE1_WUPE6_SHIFT (12U) /*! WUPE6 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK) #define WUU_PE1_WUPE7_MASK (0xC000U) #define WUU_PE1_WUPE7_SHIFT (14U) /*! WUPE7 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK) #define WUU_PE1_WUPE8_MASK (0x30000U) #define WUU_PE1_WUPE8_SHIFT (16U) /*! WUPE8 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK) #define WUU_PE1_WUPE9_MASK (0xC0000U) #define WUU_PE1_WUPE9_SHIFT (18U) /*! WUPE9 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK) #define WUU_PE1_WUPE10_MASK (0x300000U) #define WUU_PE1_WUPE10_SHIFT (20U) /*! WUPE10 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK) #define WUU_PE1_WUPE11_MASK (0xC00000U) #define WUU_PE1_WUPE11_SHIFT (22U) /*! WUPE11 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK) #define WUU_PE1_WUPE12_MASK (0x3000000U) #define WUU_PE1_WUPE12_SHIFT (24U) /*! WUPE12 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK) #define WUU_PE1_WUPE13_MASK (0xC000000U) #define WUU_PE1_WUPE13_SHIFT (26U) /*! WUPE13 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK) #define WUU_PE1_WUPE14_MASK (0x30000000U) #define WUU_PE1_WUPE14_SHIFT (28U) /*! WUPE14 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE14_SHIFT)) & WUU_PE1_WUPE14_MASK) #define WUU_PE1_WUPE15_MASK (0xC0000000U) #define WUU_PE1_WUPE15_SHIFT (30U) /*! WUPE15 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE15_SHIFT)) & WUU_PE1_WUPE15_MASK) /*! @} */ /*! @name PE2 - Pin Enable 2 */ /*! @{ */ #define WUU_PE2_WUPE16_MASK (0x3U) #define WUU_PE2_WUPE16_SHIFT (0U) /*! WUPE16 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK) #define WUU_PE2_WUPE17_MASK (0xCU) #define WUU_PE2_WUPE17_SHIFT (2U) /*! WUPE17 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK) #define WUU_PE2_WUPE18_MASK (0x30U) #define WUU_PE2_WUPE18_SHIFT (4U) /*! WUPE18 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK) #define WUU_PE2_WUPE19_MASK (0xC0U) #define WUU_PE2_WUPE19_SHIFT (6U) /*! WUPE19 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK) #define WUU_PE2_WUPE20_MASK (0x300U) #define WUU_PE2_WUPE20_SHIFT (8U) /*! WUPE20 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK) #define WUU_PE2_WUPE21_MASK (0xC00U) #define WUU_PE2_WUPE21_SHIFT (10U) /*! WUPE21 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK) #define WUU_PE2_WUPE22_MASK (0x3000U) #define WUU_PE2_WUPE22_SHIFT (12U) /*! WUPE22 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK) #define WUU_PE2_WUPE23_MASK (0xC000U) #define WUU_PE2_WUPE23_SHIFT (14U) /*! WUPE23 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK) #define WUU_PE2_WUPE24_MASK (0x30000U) #define WUU_PE2_WUPE24_SHIFT (16U) /*! WUPE24 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK) #define WUU_PE2_WUPE25_MASK (0xC0000U) #define WUU_PE2_WUPE25_SHIFT (18U) /*! WUPE25 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK) #define WUU_PE2_WUPE26_MASK (0x300000U) #define WUU_PE2_WUPE26_SHIFT (20U) /*! WUPE26 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK) #define WUU_PE2_WUPE27_MASK (0xC00000U) #define WUU_PE2_WUPE27_SHIFT (22U) /*! WUPE27 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK) #define WUU_PE2_WUPE28_MASK (0x3000000U) #define WUU_PE2_WUPE28_SHIFT (24U) /*! WUPE28 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE28_SHIFT)) & WUU_PE2_WUPE28_MASK) #define WUU_PE2_WUPE29_MASK (0xC000000U) #define WUU_PE2_WUPE29_SHIFT (26U) /*! WUPE29 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE29_SHIFT)) & WUU_PE2_WUPE29_MASK) #define WUU_PE2_WUPE30_MASK (0x30000000U) #define WUU_PE2_WUPE30_SHIFT (28U) /*! WUPE30 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE30_SHIFT)) & WUU_PE2_WUPE30_MASK) #define WUU_PE2_WUPE31_MASK (0xC0000000U) #define WUU_PE2_WUPE31_SHIFT (30U) /*! WUPE31 - Wake-up Pin Enable for WUU_Pn * 0b00..Disable * 0b01..Enable (detect on rising edge or high level) * 0b10..Enable (detect on falling edge or low level) * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK) /*! @} */ /*! @name ME - Module Interrupt Enable */ /*! @{ */ #define WUU_ME_WUME0_MASK (0x1U) #define WUU_ME_WUME0_SHIFT (0U) /*! WUME0 - Module Interrupt Wake-up Enable for Module 0 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) #define WUU_ME_WUME1_MASK (0x2U) #define WUU_ME_WUME1_SHIFT (1U) /*! WUME1 - Module Interrupt Wake-up Enable for Module 1 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK) #define WUU_ME_WUME2_MASK (0x4U) #define WUU_ME_WUME2_SHIFT (2U) /*! WUME2 - Module Interrupt Wake-up Enable for Module 2 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) #define WUU_ME_WUME3_MASK (0x8U) #define WUU_ME_WUME3_SHIFT (3U) /*! WUME3 - Module Interrupt Wake-up Enable for Module 3 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK) #define WUU_ME_WUME4_MASK (0x10U) #define WUU_ME_WUME4_SHIFT (4U) /*! WUME4 - Module Interrupt Wake-up Enable for Module 4 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK) #define WUU_ME_WUME5_MASK (0x20U) #define WUU_ME_WUME5_SHIFT (5U) /*! WUME5 - Module Interrupt Wake-up Enable for Module 5 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK) #define WUU_ME_WUME6_MASK (0x40U) #define WUU_ME_WUME6_SHIFT (6U) /*! WUME6 - Module Interrupt Wake-up Enable for Module 6 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) #define WUU_ME_WUME7_MASK (0x80U) #define WUU_ME_WUME7_SHIFT (7U) /*! WUME7 - Module Interrupt Wake-up Enable for Module 7 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK) #define WUU_ME_WUME8_MASK (0x100U) #define WUU_ME_WUME8_SHIFT (8U) /*! WUME8 - Module Interrupt Wake-up Enable for Module 8 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) #define WUU_ME_WUME9_MASK (0x200U) #define WUU_ME_WUME9_SHIFT (9U) /*! WUME9 - Module Interrupt Wake-up Enable for Module 9 * 0b0..Disable * 0b1..Enable */ #define WUU_ME_WUME9(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME9_SHIFT)) & WUU_ME_WUME9_MASK) /*! @} */ /*! @name DE - Module DMA/Trigger Enable */ /*! @{ */ #define WUU_DE_WUDE0_MASK (0x1U) #define WUU_DE_WUDE0_SHIFT (0U) /*! WUDE0 - DMA/Trigger Wake-up Enable for Module 0 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK) #define WUU_DE_WUDE1_MASK (0x2U) #define WUU_DE_WUDE1_SHIFT (1U) /*! WUDE1 - DMA/Trigger Wake-up Enable for Module 1 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK) #define WUU_DE_WUDE2_MASK (0x4U) #define WUU_DE_WUDE2_SHIFT (2U) /*! WUDE2 - DMA/Trigger Wake-up Enable for Module 2 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE2_SHIFT)) & WUU_DE_WUDE2_MASK) #define WUU_DE_WUDE3_MASK (0x8U) #define WUU_DE_WUDE3_SHIFT (3U) /*! WUDE3 - DMA/Trigger Wake-up Enable for Module 3 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE3_SHIFT)) & WUU_DE_WUDE3_MASK) #define WUU_DE_WUDE4_MASK (0x10U) #define WUU_DE_WUDE4_SHIFT (4U) /*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) #define WUU_DE_WUDE5_MASK (0x20U) #define WUU_DE_WUDE5_SHIFT (5U) /*! WUDE5 - DMA/Trigger Wake-up Enable for Module 5 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE5_SHIFT)) & WUU_DE_WUDE5_MASK) #define WUU_DE_WUDE6_MASK (0x40U) #define WUU_DE_WUDE6_SHIFT (6U) /*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) #define WUU_DE_WUDE7_MASK (0x80U) #define WUU_DE_WUDE7_SHIFT (7U) /*! WUDE7 - DMA/Trigger Wake-up Enable for Module 7 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE7_SHIFT)) & WUU_DE_WUDE7_MASK) #define WUU_DE_WUDE8_MASK (0x100U) #define WUU_DE_WUDE8_SHIFT (8U) /*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) #define WUU_DE_WUDE9_MASK (0x200U) #define WUU_DE_WUDE9_SHIFT (9U) /*! WUDE9 - DMA/Trigger Wake-up Enable for Module 9 * 0b0..Disable * 0b1..Enable */ #define WUU_DE_WUDE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE9_SHIFT)) & WUU_DE_WUDE9_MASK) /*! @} */ /*! @name PF - Pin Flag */ /*! @{ */ #define WUU_PF_WUF0_MASK (0x1U) #define WUU_PF_WUF0_SHIFT (0U) /*! WUF0 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF0_SHIFT)) & WUU_PF_WUF0_MASK) #define WUU_PF_WUF1_MASK (0x2U) #define WUU_PF_WUF1_SHIFT (1U) /*! WUF1 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF1_SHIFT)) & WUU_PF_WUF1_MASK) #define WUU_PF_WUF2_MASK (0x4U) #define WUU_PF_WUF2_SHIFT (2U) /*! WUF2 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK) #define WUU_PF_WUF3_MASK (0x8U) #define WUU_PF_WUF3_SHIFT (3U) /*! WUF3 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK) #define WUU_PF_WUF4_MASK (0x10U) #define WUU_PF_WUF4_SHIFT (4U) /*! WUF4 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK) #define WUU_PF_WUF5_MASK (0x20U) #define WUU_PF_WUF5_SHIFT (5U) /*! WUF5 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK) #define WUU_PF_WUF6_MASK (0x40U) #define WUU_PF_WUF6_SHIFT (6U) /*! WUF6 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK) #define WUU_PF_WUF7_MASK (0x80U) #define WUU_PF_WUF7_SHIFT (7U) /*! WUF7 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK) #define WUU_PF_WUF8_MASK (0x100U) #define WUU_PF_WUF8_SHIFT (8U) /*! WUF8 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK) #define WUU_PF_WUF9_MASK (0x200U) #define WUU_PF_WUF9_SHIFT (9U) /*! WUF9 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK) #define WUU_PF_WUF10_MASK (0x400U) #define WUU_PF_WUF10_SHIFT (10U) /*! WUF10 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK) #define WUU_PF_WUF11_MASK (0x800U) #define WUU_PF_WUF11_SHIFT (11U) /*! WUF11 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK) #define WUU_PF_WUF12_MASK (0x1000U) #define WUU_PF_WUF12_SHIFT (12U) /*! WUF12 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK) #define WUU_PF_WUF13_MASK (0x2000U) #define WUU_PF_WUF13_SHIFT (13U) /*! WUF13 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK) #define WUU_PF_WUF14_MASK (0x4000U) #define WUU_PF_WUF14_SHIFT (14U) /*! WUF14 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF14_SHIFT)) & WUU_PF_WUF14_MASK) #define WUU_PF_WUF15_MASK (0x8000U) #define WUU_PF_WUF15_SHIFT (15U) /*! WUF15 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF15_SHIFT)) & WUU_PF_WUF15_MASK) #define WUU_PF_WUF16_MASK (0x10000U) #define WUU_PF_WUF16_SHIFT (16U) /*! WUF16 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK) #define WUU_PF_WUF17_MASK (0x20000U) #define WUU_PF_WUF17_SHIFT (17U) /*! WUF17 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK) #define WUU_PF_WUF18_MASK (0x40000U) #define WUU_PF_WUF18_SHIFT (18U) /*! WUF18 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK) #define WUU_PF_WUF19_MASK (0x80000U) #define WUU_PF_WUF19_SHIFT (19U) /*! WUF19 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK) #define WUU_PF_WUF20_MASK (0x100000U) #define WUU_PF_WUF20_SHIFT (20U) /*! WUF20 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK) #define WUU_PF_WUF21_MASK (0x200000U) #define WUU_PF_WUF21_SHIFT (21U) /*! WUF21 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK) #define WUU_PF_WUF22_MASK (0x400000U) #define WUU_PF_WUF22_SHIFT (22U) /*! WUF22 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK) #define WUU_PF_WUF23_MASK (0x800000U) #define WUU_PF_WUF23_SHIFT (23U) /*! WUF23 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK) #define WUU_PF_WUF24_MASK (0x1000000U) #define WUU_PF_WUF24_SHIFT (24U) /*! WUF24 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK) #define WUU_PF_WUF25_MASK (0x2000000U) #define WUU_PF_WUF25_SHIFT (25U) /*! WUF25 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK) #define WUU_PF_WUF26_MASK (0x4000000U) #define WUU_PF_WUF26_SHIFT (26U) /*! WUF26 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK) #define WUU_PF_WUF27_MASK (0x8000000U) #define WUU_PF_WUF27_SHIFT (27U) /*! WUF27 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK) #define WUU_PF_WUF28_MASK (0x10000000U) #define WUU_PF_WUF28_SHIFT (28U) /*! WUF28 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF28_SHIFT)) & WUU_PF_WUF28_MASK) #define WUU_PF_WUF29_MASK (0x20000000U) #define WUU_PF_WUF29_SHIFT (29U) /*! WUF29 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF29_SHIFT)) & WUU_PF_WUF29_MASK) #define WUU_PF_WUF30_MASK (0x40000000U) #define WUU_PF_WUF30_SHIFT (30U) /*! WUF30 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF30_SHIFT)) & WUU_PF_WUF30_MASK) #define WUU_PF_WUF31_MASK (0x80000000U) #define WUU_PF_WUF31_SHIFT (31U) /*! WUF31 - Wake-up Flag for WUU_Pn * 0b0..No * 0b1..Yes */ #define WUU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK) /*! @} */ /*! @name FILT - Pin Filter */ /*! @{ */ #define WUU_FILT_FILTSEL1_MASK (0x1FU) #define WUU_FILT_FILTSEL1_SHIFT (0U) /*! FILTSEL1 - Filter 1 Pin Select */ #define WUU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK) #define WUU_FILT_FILTE1_MASK (0x60U) #define WUU_FILT_FILTE1_SHIFT (5U) /*! FILTE1 - Filter 1 Enable * 0b00..Disable * 0b01..Enable (Detect on rising edge or high level) * 0b10..Enable (Detect on falling edge or low level) * 0b11..Enable (Detect on any edge) */ #define WUU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK) #define WUU_FILT_FILTF1_MASK (0x80U) #define WUU_FILT_FILTF1_SHIFT (7U) /*! FILTF1 - Filter 1 Flag * 0b0..No * 0b1..Yes */ #define WUU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK) #define WUU_FILT_FILTSEL2_MASK (0x1F00U) #define WUU_FILT_FILTSEL2_SHIFT (8U) /*! FILTSEL2 - Filter 2 Pin Select */ #define WUU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK) #define WUU_FILT_FILTE2_MASK (0x6000U) #define WUU_FILT_FILTE2_SHIFT (13U) /*! FILTE2 - Filter 2 Enable * 0b00..Disable * 0b01..Enable (Detect on rising edge or high level) * 0b10..Enable (Detect on falling edge or low level) * 0b11..Enable (Detect on any edge) */ #define WUU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK) #define WUU_FILT_FILTF2_MASK (0x8000U) #define WUU_FILT_FILTF2_SHIFT (15U) /*! FILTF2 - Filter 2 Flag * 0b0..No * 0b1..Yes */ #define WUU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK) /*! @} */ /*! @name PDC1 - Pin DMA/Trigger Configuration 1 */ /*! @{ */ #define WUU_PDC1_WUPDC0_MASK (0x3U) #define WUU_PDC1_WUPDC0_SHIFT (0U) /*! WUPDC0 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC0_SHIFT)) & WUU_PDC1_WUPDC0_MASK) #define WUU_PDC1_WUPDC1_MASK (0xCU) #define WUU_PDC1_WUPDC1_SHIFT (2U) /*! WUPDC1 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC1_SHIFT)) & WUU_PDC1_WUPDC1_MASK) #define WUU_PDC1_WUPDC2_MASK (0x30U) #define WUU_PDC1_WUPDC2_SHIFT (4U) /*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK) #define WUU_PDC1_WUPDC3_MASK (0xC0U) #define WUU_PDC1_WUPDC3_SHIFT (6U) /*! WUPDC3 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK) #define WUU_PDC1_WUPDC4_MASK (0x300U) #define WUU_PDC1_WUPDC4_SHIFT (8U) /*! WUPDC4 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK) #define WUU_PDC1_WUPDC5_MASK (0xC00U) #define WUU_PDC1_WUPDC5_SHIFT (10U) /*! WUPDC5 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK) #define WUU_PDC1_WUPDC6_MASK (0x3000U) #define WUU_PDC1_WUPDC6_SHIFT (12U) /*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK) #define WUU_PDC1_WUPDC7_MASK (0xC000U) #define WUU_PDC1_WUPDC7_SHIFT (14U) /*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK) #define WUU_PDC1_WUPDC8_MASK (0x30000U) #define WUU_PDC1_WUPDC8_SHIFT (16U) /*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK) #define WUU_PDC1_WUPDC9_MASK (0xC0000U) #define WUU_PDC1_WUPDC9_SHIFT (18U) /*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK) #define WUU_PDC1_WUPDC10_MASK (0x300000U) #define WUU_PDC1_WUPDC10_SHIFT (20U) /*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK) #define WUU_PDC1_WUPDC11_MASK (0xC00000U) #define WUU_PDC1_WUPDC11_SHIFT (22U) /*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK) #define WUU_PDC1_WUPDC12_MASK (0x3000000U) #define WUU_PDC1_WUPDC12_SHIFT (24U) /*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK) #define WUU_PDC1_WUPDC13_MASK (0xC000000U) #define WUU_PDC1_WUPDC13_SHIFT (26U) /*! WUPDC13 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK) #define WUU_PDC1_WUPDC14_MASK (0x30000000U) #define WUU_PDC1_WUPDC14_SHIFT (28U) /*! WUPDC14 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC14_SHIFT)) & WUU_PDC1_WUPDC14_MASK) #define WUU_PDC1_WUPDC15_MASK (0xC0000000U) #define WUU_PDC1_WUPDC15_SHIFT (30U) /*! WUPDC15 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC1_WUPDC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC15_SHIFT)) & WUU_PDC1_WUPDC15_MASK) /*! @} */ /*! @name PDC2 - Pin DMA/Trigger Configuration 2 */ /*! @{ */ #define WUU_PDC2_WUPDC16_MASK (0x3U) #define WUU_PDC2_WUPDC16_SHIFT (0U) /*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK) #define WUU_PDC2_WUPDC17_MASK (0xCU) #define WUU_PDC2_WUPDC17_SHIFT (2U) /*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK) #define WUU_PDC2_WUPDC18_MASK (0x30U) #define WUU_PDC2_WUPDC18_SHIFT (4U) /*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK) #define WUU_PDC2_WUPDC19_MASK (0xC0U) #define WUU_PDC2_WUPDC19_SHIFT (6U) /*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK) #define WUU_PDC2_WUPDC20_MASK (0x300U) #define WUU_PDC2_WUPDC20_SHIFT (8U) /*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK) #define WUU_PDC2_WUPDC21_MASK (0xC00U) #define WUU_PDC2_WUPDC21_SHIFT (10U) /*! WUPDC21 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK) #define WUU_PDC2_WUPDC22_MASK (0x3000U) #define WUU_PDC2_WUPDC22_SHIFT (12U) /*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK) #define WUU_PDC2_WUPDC23_MASK (0xC000U) #define WUU_PDC2_WUPDC23_SHIFT (14U) /*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK) #define WUU_PDC2_WUPDC24_MASK (0x30000U) #define WUU_PDC2_WUPDC24_SHIFT (16U) /*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK) #define WUU_PDC2_WUPDC25_MASK (0xC0000U) #define WUU_PDC2_WUPDC25_SHIFT (18U) /*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK) #define WUU_PDC2_WUPDC26_MASK (0x300000U) #define WUU_PDC2_WUPDC26_SHIFT (20U) /*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK) #define WUU_PDC2_WUPDC27_MASK (0xC00000U) #define WUU_PDC2_WUPDC27_SHIFT (22U) /*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK) #define WUU_PDC2_WUPDC28_MASK (0x3000000U) #define WUU_PDC2_WUPDC28_SHIFT (24U) /*! WUPDC28 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC28_SHIFT)) & WUU_PDC2_WUPDC28_MASK) #define WUU_PDC2_WUPDC29_MASK (0xC000000U) #define WUU_PDC2_WUPDC29_SHIFT (26U) /*! WUPDC29 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC29_SHIFT)) & WUU_PDC2_WUPDC29_MASK) #define WUU_PDC2_WUPDC30_MASK (0x30000000U) #define WUU_PDC2_WUPDC30_SHIFT (28U) /*! WUPDC30 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC30_SHIFT)) & WUU_PDC2_WUPDC30_MASK) #define WUU_PDC2_WUPDC31_MASK (0xC0000000U) #define WUU_PDC2_WUPDC31_SHIFT (30U) /*! WUPDC31 - Wake-up Pin Configuration for WUU_Pn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK) /*! @} */ /*! @name FDC - Pin Filter DMA/Trigger Configuration */ /*! @{ */ #define WUU_FDC_FILTC1_MASK (0x3U) #define WUU_FDC_FILTC1_SHIFT (0U) /*! FILTC1 - Filter Configuration for FILTn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK) #define WUU_FDC_FILTC2_MASK (0xCU) #define WUU_FDC_FILTC2_SHIFT (2U) /*! FILTC2 - Filter Configuration for FILTn * 0b00..Interrupt * 0b01..DMA request * 0b10..Trigger event * 0b11..Reserved */ #define WUU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK) /*! @} */ /*! @name PMC - Pin Mode Configuration */ /*! @{ */ #define WUU_PMC_WUPMC0_MASK (0x1U) #define WUU_PMC_WUPMC0_SHIFT (0U) /*! WUPMC0 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC0_SHIFT)) & WUU_PMC_WUPMC0_MASK) #define WUU_PMC_WUPMC1_MASK (0x2U) #define WUU_PMC_WUPMC1_SHIFT (1U) /*! WUPMC1 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC1_SHIFT)) & WUU_PMC_WUPMC1_MASK) #define WUU_PMC_WUPMC2_MASK (0x4U) #define WUU_PMC_WUPMC2_SHIFT (2U) /*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK) #define WUU_PMC_WUPMC3_MASK (0x8U) #define WUU_PMC_WUPMC3_SHIFT (3U) /*! WUPMC3 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK) #define WUU_PMC_WUPMC4_MASK (0x10U) #define WUU_PMC_WUPMC4_SHIFT (4U) /*! WUPMC4 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK) #define WUU_PMC_WUPMC5_MASK (0x20U) #define WUU_PMC_WUPMC5_SHIFT (5U) /*! WUPMC5 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK) #define WUU_PMC_WUPMC6_MASK (0x40U) #define WUU_PMC_WUPMC6_SHIFT (6U) /*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK) #define WUU_PMC_WUPMC7_MASK (0x80U) #define WUU_PMC_WUPMC7_SHIFT (7U) /*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK) #define WUU_PMC_WUPMC8_MASK (0x100U) #define WUU_PMC_WUPMC8_SHIFT (8U) /*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK) #define WUU_PMC_WUPMC9_MASK (0x200U) #define WUU_PMC_WUPMC9_SHIFT (9U) /*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK) #define WUU_PMC_WUPMC10_MASK (0x400U) #define WUU_PMC_WUPMC10_SHIFT (10U) /*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK) #define WUU_PMC_WUPMC11_MASK (0x800U) #define WUU_PMC_WUPMC11_SHIFT (11U) /*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK) #define WUU_PMC_WUPMC12_MASK (0x1000U) #define WUU_PMC_WUPMC12_SHIFT (12U) /*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK) #define WUU_PMC_WUPMC13_MASK (0x2000U) #define WUU_PMC_WUPMC13_SHIFT (13U) /*! WUPMC13 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK) #define WUU_PMC_WUPMC14_MASK (0x4000U) #define WUU_PMC_WUPMC14_SHIFT (14U) /*! WUPMC14 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC14_SHIFT)) & WUU_PMC_WUPMC14_MASK) #define WUU_PMC_WUPMC15_MASK (0x8000U) #define WUU_PMC_WUPMC15_SHIFT (15U) /*! WUPMC15 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC15_SHIFT)) & WUU_PMC_WUPMC15_MASK) #define WUU_PMC_WUPMC16_MASK (0x10000U) #define WUU_PMC_WUPMC16_SHIFT (16U) /*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK) #define WUU_PMC_WUPMC17_MASK (0x20000U) #define WUU_PMC_WUPMC17_SHIFT (17U) /*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK) #define WUU_PMC_WUPMC18_MASK (0x40000U) #define WUU_PMC_WUPMC18_SHIFT (18U) /*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK) #define WUU_PMC_WUPMC19_MASK (0x80000U) #define WUU_PMC_WUPMC19_SHIFT (19U) /*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK) #define WUU_PMC_WUPMC20_MASK (0x100000U) #define WUU_PMC_WUPMC20_SHIFT (20U) /*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK) #define WUU_PMC_WUPMC21_MASK (0x200000U) #define WUU_PMC_WUPMC21_SHIFT (21U) /*! WUPMC21 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK) #define WUU_PMC_WUPMC22_MASK (0x400000U) #define WUU_PMC_WUPMC22_SHIFT (22U) /*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK) #define WUU_PMC_WUPMC23_MASK (0x800000U) #define WUU_PMC_WUPMC23_SHIFT (23U) /*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK) #define WUU_PMC_WUPMC24_MASK (0x1000000U) #define WUU_PMC_WUPMC24_SHIFT (24U) /*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK) #define WUU_PMC_WUPMC25_MASK (0x2000000U) #define WUU_PMC_WUPMC25_SHIFT (25U) /*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK) #define WUU_PMC_WUPMC26_MASK (0x4000000U) #define WUU_PMC_WUPMC26_SHIFT (26U) /*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK) #define WUU_PMC_WUPMC27_MASK (0x8000000U) #define WUU_PMC_WUPMC27_SHIFT (27U) /*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK) #define WUU_PMC_WUPMC28_MASK (0x10000000U) #define WUU_PMC_WUPMC28_SHIFT (28U) /*! WUPMC28 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC28_SHIFT)) & WUU_PMC_WUPMC28_MASK) #define WUU_PMC_WUPMC29_MASK (0x20000000U) #define WUU_PMC_WUPMC29_SHIFT (29U) /*! WUPMC29 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC29_SHIFT)) & WUU_PMC_WUPMC29_MASK) #define WUU_PMC_WUPMC30_MASK (0x40000000U) #define WUU_PMC_WUPMC30_SHIFT (30U) /*! WUPMC30 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC30_SHIFT)) & WUU_PMC_WUPMC30_MASK) #define WUU_PMC_WUPMC31_MASK (0x80000000U) #define WUU_PMC_WUPMC31_SHIFT (31U) /*! WUPMC31 - Wake-up Pin Mode Configuration for WUU_Pn * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or * Pin DMA/Trigger Configuration (PDCn). * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK) /*! @} */ /*! @name FMC - Pin Filter Mode Configuration */ /*! @{ */ #define WUU_FMC_FILTM1_MASK (0x1U) #define WUU_FMC_FILTM1_SHIFT (0U) /*! FILTM1 - Filter Mode for FILTn * 0b0..Active only during Power Down/Deep Power Down mode * 0b1..Active during all power modes */ #define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK) #define WUU_FMC_FILTM2_MASK (0x2U) #define WUU_FMC_FILTM2_SHIFT (1U) /*! FILTM2 - Filter Mode for FILTn * 0b0..Active only during Power Down/Deep Power Down mode * 0b1..Active during all power modes */ #define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK) /*! @} */ /*! * @} */ /* end of group WUU_Register_Masks */ /* WUU - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral WUU0 base address */ #define WUU0_BASE (0x50046000u) /** Peripheral WUU0 base address */ #define WUU0_BASE_NS (0x40046000u) /** Peripheral WUU0 base pointer */ #define WUU0 ((WUU_Type *)WUU0_BASE) /** Peripheral WUU0 base pointer */ #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) /** Array initializer of WUU peripheral base addresses */ #define WUU_BASE_ADDRS { WUU0_BASE } /** Array initializer of WUU peripheral base pointers */ #define WUU_BASE_PTRS { WUU0 } /** Array initializer of WUU peripheral base addresses */ #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } /** Array initializer of WUU peripheral base pointers */ #define WUU_BASE_PTRS_NS { WUU0_NS } #else /** Peripheral WUU0 base address */ #define WUU0_BASE (0x40046000u) /** Peripheral WUU0 base pointer */ #define WUU0 ((WUU_Type *)WUU0_BASE) /** Array initializer of WUU peripheral base addresses */ #define WUU_BASE_ADDRS { WUU0_BASE } /** Array initializer of WUU peripheral base pointers */ #define WUU_BASE_PTRS { WUU0 } #endif /*! * @} */ /* end of group WUU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WWDT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer * @{ */ /** WWDT - Register Layout Typedef */ typedef struct { __IO uint32_t MOD; /**< Mode, offset: 0x0 */ __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ __I uint32_t TV; /**< Timer Value, offset: 0xC */ uint8_t RESERVED_0[4]; __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ } WWDT_Type; /* ---------------------------------------------------------------------------- -- WWDT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WWDT_Register_Masks WWDT Register Masks * @{ */ /*! @name MOD - Mode */ /*! @{ */ #define WWDT_MOD_WDEN_MASK (0x1U) #define WWDT_MOD_WDEN_SHIFT (0U) /*! WDEN - Watchdog Enable * 0b0..Timer stopped * 0b1..Timer running */ #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) #define WWDT_MOD_WDRESET_MASK (0x2U) #define WWDT_MOD_WDRESET_SHIFT (1U) /*! WDRESET - Watchdog Reset Enable * 0b0..Interrupt * 0b1..Reset */ #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) #define WWDT_MOD_WDTOF_MASK (0x4U) #define WWDT_MOD_WDTOF_SHIFT (2U) /*! WDTOF - Watchdog Timeout Flag * 0b0..Watchdog event has not occurred. * 0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1). */ #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) #define WWDT_MOD_WDINT_MASK (0x8U) #define WWDT_MOD_WDINT_SHIFT (3U) /*! WDINT - Warning Interrupt Flag * 0b0..No flag * 0b1..Flag */ #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) #define WWDT_MOD_WDPROTECT_MASK (0x10U) #define WWDT_MOD_WDPROTECT_SHIFT (4U) /*! WDPROTECT - Watchdog Update Mode * 0b0..Flexible * 0b1..Threshold */ #define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) #define WWDT_MOD_LOCK_MASK (0x20U) #define WWDT_MOD_LOCK_SHIFT (5U) /*! LOCK - Lock * 0b0..No Lock * 0b1..Lock */ #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) #define WWDT_MOD_DEBUG_EN_MASK (0x40U) #define WWDT_MOD_DEBUG_EN_SHIFT (6U) /*! DEBUG_EN - Debug Enable * 0b0..Disabled * 0b1..Enabled */ #define WWDT_MOD_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_DEBUG_EN_SHIFT)) & WWDT_MOD_DEBUG_EN_MASK) /*! @} */ /*! @name TC - Timer Constant */ /*! @{ */ #define WWDT_TC_COUNT_MASK (0xFFFFFFU) #define WWDT_TC_COUNT_SHIFT (0U) /*! COUNT - Watchdog Timeout Value */ #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) /*! @} */ /*! @name FEED - Feed Sequence */ /*! @{ */ #define WWDT_FEED_FEED_MASK (0xFFU) #define WWDT_FEED_FEED_SHIFT (0U) /*! FEED - Feed Value */ #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) /*! @} */ /*! @name TV - Timer Value */ /*! @{ */ #define WWDT_TV_COUNT_MASK (0xFFFFFFU) #define WWDT_TV_COUNT_SHIFT (0U) /*! COUNT - Counter Timer Value */ #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) /*! @} */ /*! @name WARNINT - Warning Interrupt Compare Value */ /*! @{ */ #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) #define WWDT_WARNINT_WARNINT_SHIFT (0U) /*! WARNINT - Watchdog Warning Interrupt Compare Value */ #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) /*! @} */ /*! @name WINDOW - Window Compare Value */ /*! @{ */ #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) #define WWDT_WINDOW_WINDOW_SHIFT (0U) /*! WINDOW - Watchdog Window Value */ #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) /*! @} */ /*! * @} */ /* end of group WWDT_Register_Masks */ /* WWDT - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral WWDT0 base address */ #define WWDT0_BASE (0x50016000u) /** Peripheral WWDT0 base address */ #define WWDT0_BASE_NS (0x40016000u) /** Peripheral WWDT0 base pointer */ #define WWDT0 ((WWDT_Type *)WWDT0_BASE) /** Peripheral WWDT0 base pointer */ #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) /** Peripheral WWDT1 base address */ #define WWDT1_BASE (0x50017000u) /** Peripheral WWDT1 base address */ #define WWDT1_BASE_NS (0x40017000u) /** Peripheral WWDT1 base pointer */ #define WWDT1 ((WWDT_Type *)WWDT1_BASE) /** Peripheral WWDT1 base pointer */ #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) /** Array initializer of WWDT peripheral base addresses */ #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } /** Array initializer of WWDT peripheral base pointers */ #define WWDT_BASE_PTRS { WWDT0, WWDT1 } /** Array initializer of WWDT peripheral base addresses */ #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } /** Array initializer of WWDT peripheral base pointers */ #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } #else /** Peripheral WWDT0 base address */ #define WWDT0_BASE (0x40016000u) /** Peripheral WWDT0 base pointer */ #define WWDT0 ((WWDT_Type *)WWDT0_BASE) /** Peripheral WWDT1 base address */ #define WWDT1_BASE (0x40017000u) /** Peripheral WWDT1 base pointer */ #define WWDT1 ((WWDT_Type *)WWDT1_BASE) /** Array initializer of WWDT peripheral base addresses */ #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } /** Array initializer of WWDT peripheral base pointers */ #define WWDT_BASE_PTRS { WWDT0, WWDT1 } #endif /** Interrupt vectors for the WWDT peripheral type */ #define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } /*! * @} */ /* end of group WWDT_Peripheral_Access_Layer */ /* ** End of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #else #pragma pop #endif #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=default #else #error Not supported compiler type #endif /*! * @} */ /* end of group Peripheral_access_layer */ /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). ---------------------------------------------------------------------------- */ /*! * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). * @{ */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang system_header #endif #elif defined(__IAR_SYSTEMS_ICC__) #pragma system_include #endif /** * @brief Mask and left-shift a bit field value for use in a register bit range. * @param field Name of the register bit field. * @param value Value of the bit field. * @return Masked and shifted value. */ #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) /*! * @} */ /* end of group Bit_Field_Generic_Macros */ /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ /*! * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ /*! * @brief Get the chip value. * * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. */ static inline uint32_t Chip_GetVersion(void) { uint32_t deviceRevision; deviceRevision = SYSCON->DIEID & SYSCON_DIEID_MINOR_REVISION_MASK; if(0UL == deviceRevision) /* A0 device revision is 0 */ { return 0x0; } else if(1UL == deviceRevision) /* A1 device revision is 1 */ { return 0x1; } else { return 0xFF; } } /*! * @} */ /* end of group SDK_Compatibility_Symbols */ #endif /* MCXN946_CM33_CORE1_H_ */