/* * Copyright (c) 2022 ITE. * Copyright 2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _HDMITX_H_ #define _HDMITX_H_ typedef enum { PCLK_LOW = 0, PCLK_MEDIUM, PCLK_HIGH } VIDEOPCLKLEVEL; #define DDC_FIFO_MAXREQ (0x20U) #define MAX_AUDDES_COUNT (0x04U) #define SIZEOF_CSCMTX (21U) enum AUDIO_INTERFACES { AUDIO_IF_I2S = 1U, AUDIO_IF_SPDIF = 2U, AUDIO_IF_TDM = 3U, }; typedef union _tag_DCSUPPORT { struct { uint8_t DVI_Dual : 1; uint8_t Rsvd : 2; uint8_t DC_Y444 : 1; uint8_t DC_30Bit : 1; uint8_t DC_36Bit : 1; uint8_t DC_48Bit : 1; uint8_t SUPPORT_AI : 1; } info; uint8_t uc; } DCSUPPORT; typedef union _LATENCY_SUPPORT { struct { uint8_t Rsvd : 6; uint8_t I_Latency_Present : 1; uint8_t Latency_Present : 1; } info; uint8_t uc; } LATENCY_SUPPORT; typedef union { struct { uint8_t FL_FR : 1; uint8_t LFE : 1; uint8_t FC : 1; uint8_t RL_RR : 1; uint8_t RC : 1; uint8_t FLC_FRC : 1; uint8_t RLC_RRC : 1; uint8_t Reserve : 1; uint8_t Unuse[2]; } s; uint8_t uc[3]; } SPK_ALLOC; typedef union { struct { uint8_t channel : 3; uint8_t AudioFormatCode : 4; uint8_t Rsrv1 : 1; uint8_t b32KHz : 1; uint8_t b44_1KHz : 1; uint8_t b48KHz : 1; uint8_t b88_2KHz : 1; uint8_t b96KHz : 1; uint8_t b176_4KHz : 1; uint8_t b192KHz : 1; uint8_t Rsrv2 : 1; uint8_t ucCode; } s; uint8_t uc[3]; } AUDDESCRIPTOR; typedef struct _RX_CAP { uint8_t VideoMode; uint8_t NativeVDOMode; uint8_t VDOMode[8]; uint8_t AUDDesCount; AUDDESCRIPTOR AUDDes[MAX_AUDDES_COUNT]; uint8_t PA[2]; uint32_t IEEEOUI; DCSUPPORT dc; uint8_t MaxTMDSClock; LATENCY_SUPPORT lsupport; SPK_ALLOC SpeakerAllocBlk; uint8_t ValidCEA : 1; uint8_t ValidHDMI : 1; uint8_t Valid3D : 1; } RX_CAP; typedef struct { uint8_t offset; uint8_t invAndMask; uint8_t OrMask; } RegSetTable_t; #define NRTXRCLK (0x01U) /* true:set TRCLK by self */ #define FORCE_TXCLK_STABLE (0x01U) #define STABLE_LINEPIEXELCNT_SENSITIVITY (0x01U) #define RCLK_FREQ_SEL (0x01U) /* false: 10MHz(div1); true: 20 MHz(OSSDIV2) */ #define FORCE_TX_CLK_STABLE (0x01U) #define FORCE_TX_VID_STABLE (0x01U) #define V_SYNC_POL (0x00U) /* 0: active low; 1: active high */ #define H_SYNC_POL (0x00U) /* 0: active low; 1: active high */ #define HDMI_TX_PCLK_DIV2 (false) #define REG_TX_SW_RST 0x04 #define B_TX_ENTEST (1U << 7U) #define B_TX_REF_RST_HDMITX (1U << 5U) #define B_TX_AREF_RST (1U << 4U) #define B_HDMITX_VID_RST (1U << 3U) #define B_HDMITX_AUD_RST (1U << 2U) #define B_TX_HDMI_RST (1U << 1U) #define B_TX_HDCP_RST_HDMITX (1U << 0U) #define REG_TX_AFE_DRV_CTRL 0x61 #define B_TX_AFE_DRV_PWD (1U << 5U) #define B_TX_AFE_DRV_RST (1U << 4U) #define HDMI_TX_GENERAL_REG04 (0x04U) #define HDMI_TX_GENERAL_REG05 (0x05U) #define HDMI_TX_GENERAL_REG05_REGINTPOL_SHIFT (0x07U) #define HDMI_TX_GENERAL_REG05_REGINTPOL_MASK (HDMI_TX_GENERAL_REG05_REGINTPOL(0x01U)) #define HDMI_TX_GENERAL_REG05_REGINTPOL(N) ((N) << HDMI_TX_GENERAL_REG05_REGINTPOL_SHIFT) #define HDMI_TX_GENERAL_REG05_REGINTIOMODE_SHIFT (0x06U) #define HDMI_TX_GENERAL_REG05_REGINTIOMODE_MASK (HDMI_TX_GENERAL_REG05_REGINTIOMODE(0x01U)) #define HDMI_TX_GENERAL_REG05_REGINTIOMODE(N) ((N) << HDMI_TX_GENERAL_REG05_REGINTIOMODE_SHIFT) /* Interrupt Flags */ #define HDMI_TX_INT_FLAGS_REG06 (0x06U) #define HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus_SHIFT (0x00U) #define HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus_MASK (HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus(0x01U)) #define HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus(N) ((N) << HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus_SHIFT) #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang_SHIFT (0x02U) #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang_MASK (HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang(0x01U)) #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang(N) ((N) << HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang_SHIFT) #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr_SHIFT (0x04U) #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr_MASK (HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr(0x01U)) #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr(N) ((N) << HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr_SHIFT) #define HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus_SHIFT (0x07U) #define HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus_MASK (HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus(0x01U)) #define HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus(N) ((N) << HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus_SHIFT) #define HDMI_TX_INT_FLAGS_REG08 (0x08U) #define HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus_SHIFT (0x00U) #define HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus_MASK (HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus(0x01U)) #define HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus(N) ((N) << HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus_SHIFT) #define HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus_SHIFT (0x04U) #define HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus_MASK (HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus(0x01U)) #define HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus(N) ((N) << HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus_SHIFT) /* Interrupt Mask Registers */ #define HDMI_TX_INT_MASK_REG09 (0x09U) #define HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw_SHIFT (0x07U) #define HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw_MASK (HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw(0x01U)) #define HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw_SHIFT) #define HDMI_TX_INT_MASK_REG09_REG_DDCNoACK_SHIFT (0x05U) #define HDMI_TX_INT_MASK_REG09_REG_DDCNoACK_MASK (HDMI_TX_INT_MASK_REG09_REG_DDCNoACK(0x01U)) #define HDMI_TX_INT_MASK_REG09_REG_DDCNoACK(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_DDCNoACK_SHIFT) #define HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr_SHIFT (0x04U) #define HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr_MASK (HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr(0x01U)) #define HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr_SHIFT) #define HDMI_TX_INT_MASK_REG09_REG_DDCBusHang_SHIFT (0x02U) #define HDMI_TX_INT_MASK_REG09_REG_DDCBusHang_MASK (HDMI_TX_INT_MASK_REG09_REG_DDCBusHang(0x01U)) #define HDMI_TX_INT_MASK_REG09_REG_DDCBusHang(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_DDCBusHang_SHIFT) #define HDMI_TX_INT_MASK_REG09_REG_RxSEN_SHIFT (0x01U) #define HDMI_TX_INT_MASK_REG09_REG_RxSEN_MASK (HDMI_TX_INT_MASK_REG09_REG_RxSEN(0x01U)) #define HDMI_TX_INT_MASK_REG09_REG_RxSEN(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_RxSEN_SHIFT) #define HDMI_TX_INT_MASK_REG09_REG_HPD_SHIFT (0x00U) #define HDMI_TX_INT_MASK_REG09_REG_HPD_MASK (HDMI_TX_INT_MASK_REG09_REG_HPD(0x01U)) #define HDMI_TX_INT_MASK_REG09_REG_HPD(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_HPD_SHIFT) #define HDMI_TX_INT_MASK_REG0B (0x0BU) #define HDMI_TX_INT_MASK_REG0B_REG_VidStable_SHIFT (0x03U) #define HDMI_TX_INT_MASK_REG0B_REG_VidStable_MASK (HDMI_TX_INT_MASK_REG0B_REG_VidStable(0x01U)) #define HDMI_TX_INT_MASK_REG0B_REG_VidStable(N) ((N) << HDMI_TX_INT_MASK_REG0B_REG_VidStable_SHIFT) /* Interrupt Clear */ #define HDMI_TX_INT_CLEAR_REG0C (0x0CU) #define HDMI_TX_INT_CLEAR_REG0D (0x0DU) #define HDMI_TX_SYS_STATUS_REG0E (0x0EU) #define HDMI_TX_SYS_STATUS_REG0E_RHPDetect_SHIFT (0x06U) #define HDMI_TX_SYS_STATUS_REG0E_RHPDetect_MASK (HDMI_TX_SYS_STATUS_REG0E_RHPDetect(0x01U)) #define HDMI_TX_SYS_STATUS_REG0E_RHPDetect(N) ((N) << HDMI_TX_SYS_STATUS_REG0E_RHPDetect_SHIFT) #define HDMI_TX_SYS_STATUS_REG0E_TxVidStable_SHIFT (0x04U) #define HDMI_TX_SYS_STATUS_REG0E_TxVidStable_MASK (HDMI_TX_SYS_STATUS_REG0E_TxVidStable(0x01U)) #define HDMI_TX_SYS_STATUS_REG0E_TxVidStable(N) ((N) << HDMI_TX_SYS_STATUS_REG0E_TxVidStable_SHIFT) #define HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr_SHIFT (0x01U) #define HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr_MASK (HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr(0x01U)) #define HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr(N) ((N) << HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr_SHIFT) #define HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone_SHIFT (0x00U) #define HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone_MASK (HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone(0x01U)) #define HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone(N) ((N) << HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone_SHIFT) #define HDMI_TX_SYS_STATUS_REG0F (0x0FU) #define HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL_SHIFT (0x00U) #define HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL_MASK (HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL(0x03U)) #define HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL(N) ((N) << HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG10 (0x10U) #define HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel_SHIFT (0x00U) #define HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel(0x01U)) #define HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA_SHIFT (0x01U) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA(0x01U)) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL_SHIFT (0x02U) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL(0x01U)) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC_SHIFT (0x03U) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC(0x01U)) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse_SHIFT (0x04U) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse(0x0FU)) #define HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG11 (0x11U) #define HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER_SHIFT (0x00U) #define HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER_MASK (HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER(0xFFU)) #define HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER_SHIFT) /* RDDC_Header[7:0]: PC DDC request slave address */ #define HDMI_TX_DDC_HDCP_ADDR (0x74U) #define HDMI_TX_DDC_EDID_ADDR (0xA0U) #define HDMI_TX_SYS_DDC_CTRL_REG12 (0x12U) #define HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet_SHIFT (0x00U) #define HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet_MASK (HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet(0xFFU)) #define HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG13 (0x13U) #define HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte_SHIFT (0x00U) #define HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte_MASK (HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte(0xFFU)) #define HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG14 (0x14U) #define HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment_SHIFT (0x00U) #define HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment_MASK (HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment(0xFFU)) #define HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG15 (0x15U) #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_SHIFT (0x00U) #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_MASK (HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x0FU)) #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_EDID_read HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x03U) #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_DDC_FIFO_clear HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x09U) #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_GenerateSCL_clock_pulse HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x0AU) #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_Abort_DDC_CMD HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x0FU) #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG16 (0x16U) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done_SHIFT (0x07U) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done_MASK (HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done(0x01U)) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK_SHIFT (0x05U) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK_MASK (HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK(0x01U)) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus_SHIFT (0x04U) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus_MASK (HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus(0x01U)) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose_SHIFT (0x03U) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose_MASK (HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose(0x01U)) #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose(N) \ ((N) << HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose_SHIFT) #define HDMI_TX_SYS_DDC_CTRL_REG17 (0x17U) #define HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO_SHIFT (0x00U) #define HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO_MASK (HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO(0xFFU)) #define HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO_SHIFT) /* HDMI TX Clock Control */ #define HDMI_TX_CLOCK_CONTROL_REG58 (0x58U) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp_SHIFT (0x07U) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp_MASK (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp(0x01U)) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp(N) ((N) << HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp_SHIFT) #define HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK_SHIFT (0x04U) #define HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK_MASK (HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK(0x01U)) #define HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK(N) ((N) << HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK_SHIFT) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_SHIFT (0x00U) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_MASK (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x03U)) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(N) ((N) << HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_SHIFT) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_1x128Fs (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x00U)) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_2x128Fs (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x01U)) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_4x128Fs (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x02U)) #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_8x128Fs (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x03U)) #define HDMI_TX_CLOCK_CONTROL_REG5D (0x5DU) #define HDMI_TX_CLOCK_CONTROL_REG5F (0x5FU) #define HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock_SHIFT (0x05U) #define HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock_MASK (HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock(0x01U)) #define HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock(N) ((N) << HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock_SHIFT) /* Input Data Format Registers */ #define HDMI_TX_INPUT_DATA_FORMAT_REG70 (0x70U) #define HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2_SHIFT (0x05U) #define HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2(0x01U)) #define HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2(N) ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2_SHIFT) #define HDMI_TX_INPUT_DATA_FORMAT_REG72 (0x72U) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_SHIFT (0x00U) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(0x03U)) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(N) ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_SHIFT) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_BYPASS (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(0x00U)) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_RGB2YUV (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(0x02U)) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_YUV2RGB (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(0x03U)) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO_SHIFT (0x05U) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO(0x01U)) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO(N) ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO_SHIFT) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_SHIFT (0x06U) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER(0x01U)) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER(N) \ ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_SHIFT) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_SHIFT (0x07U) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER(0x01U)) #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER(N) ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_SHIFT) /* Color Space Conversion */ #define HDMI_TX_COLOR_SPACE_CONVERSION_REG73 (0x73U) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet_SHIFT (0x00U) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet_MASK (HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet(0xFFU)) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet(N) \ ((N) << HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet_SHIFT) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D (0x8DU) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK_SHIFT (0x00U) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK_MASK (HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK(0x01U)) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK(N) \ ((N) << HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK_SHIFT) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr_SHIFT (0x01U) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr_MASK \ (HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr(0x7FU)) #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr(N) \ ((N) << HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr_SHIFT) #define HDMI_TX_CEC_SLAVE_ADDR (0x4EU) /* Pattern Sync/DE Generation */ #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90 (0x90U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE(0x01U)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol_SHIFT (0x01U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol(0x01U)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol_SHIFT (0x02U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol(0x01U)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync_SHIFT (0x03U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync(0x01U)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal_SHIFT (0x04U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91 (0x91U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal(0xFFU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95 (0x95U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS(0xFFU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96 (0x96U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE(0xFFU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97 (0x97U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE_SHIFT (0x04U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98 (0x98U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal(0xFFU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99 (0x99U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal(0xFFU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0 (0xA0U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS(0xFFU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1 (0xA1U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE_SHIFT (0x04U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2 (0xA2U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd(0xFFU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3 (0xA3U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd_SHIFT (0x04U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4 (0xA4U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise(0xFFU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5 (0xA5U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced_SHIFT (0x04U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced(0x01U)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn_SHIFT (0x05U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn(0x01U)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6 (0xA6U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd_SHIFT (0x04U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd_SHIFT) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE_SHIFT (0x00U) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE_MASK \ (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE(0x0FU)) #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE(N) \ ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE_SHIFT) /* Pattern Generator */ #define HDMI_TX_PATTERN_GENERATOR_REGA9 (0xA9U) #define HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM_SHIFT (0x07U) #define HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM_MASK (HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM(0x01U)) #define HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM_SHIFT) #define HDMI_TX_PATTERN_GENERATOR_REGB1 (0xB1U) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE_SHIFT (0x06U) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE_MASK (HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE(0x01U)) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE_SHIFT) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS_SHIFT (0x04U) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS_MASK (HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS(0x01U)) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS_SHIFT) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES_SHIFT (0x00U) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES_MASK (HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES(0x01U)) #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES_SHIFT) #define HDMI_TX_PATTERN_GENERATOR_REGB2 (0xB2U) #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise_SHIFT (0x02U) #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise_MASK \ (HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise(0x01U)) #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise(N) \ ((N) << HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise_SHIFT) #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal_SHIFT (0x00U) #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal_MASK (HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal(0x01U)) #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal_SHIFT) #define HDMI_TX_PATTERN_GENERATOR_REGBF (0xBFU) #define HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap_SHIFT (0x00U) #define HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap_MASK (HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap(0x01U)) #define HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap_SHIFT) /* HDMI Control Registers */ #define HDMI_TX_HDMI_CONTROL_REGC0 (0xC0U) #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_SHIFT (0x00U) #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_MASK (HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_DVI_MODE (HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode(0x00U)) #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_HDMI_MODE (HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGC1 (0xC1U) #define HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute_SHIFT (0x00U) #define HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute_MASK (HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGC5 (0xC5U) #define HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt_SHIFT (0x00U) #define HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt_MASK (HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel_SHIFT (0x01U) #define HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel_MASK (HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGC6 (0xC6U) #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt_SHIFT (0x01U) #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt_MASK (HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn_SHIFT (0x00U) #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn_MASK (HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGCD (0xCDU) #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt_SHIFT (0x01U) #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt_MASK (HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt(N) ((N) << HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn_SHIFT (0x00U) #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn_MASK (HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn(N) ((N) << HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGCE (0xCEU) #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt_SHIFT (0x01U) #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt_MASK (HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt(N) ((N) << HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn_SHIFT (0x00U) #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn_MASK (HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn(N) ((N) << HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGD1 (0xD1U) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_SHIFT (0x00U) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_MASK (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd(0x0FU)) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd(N) ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable_SHIFT (0x03U) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable_MASK \ (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable(N) \ ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable_SHIFT (0x02U) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable_MASK \ (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable(N) \ ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity_SHIFT (0x01U) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity_MASK \ (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity(N) \ ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity_SHIFT) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStableCheck_SHIFT (0x00U) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStableCheck_MASK \ (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStableCheck(0x01U)) #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStableCheck(N) \ ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStable_SHIFT) /* Audio Channel Registers */ #define HDMI_TX_AUDIO_CHANNEL_REGE0 (0xE0U) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_SHIFT (0x06U) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_MASK (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x03U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_16bits (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x00U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_18bits (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_20bits (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x02U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_24bits (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x03U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC_SHIFT (0x05U) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC_MASK (HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_SHIFT (0x04U) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_I2S (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel(0x00U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_SPDIF (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_SHIFT (0x00U) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_MASK (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x0FU)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_Enable_Audio_Source_0 (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_Enable_Audio_Source_1 (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x02U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_Enable_Audio_Source_2 (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x04U)) #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_Enable_Audio_Source_3 (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x08U)) #define HDMI_TX_AUDIO_CHANNEL_REGE1 (0xE1U) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt_SHIFT (0x06U) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt_MASK (HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge_SHIFT (0x05U) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge_MASK (HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt_SHIFT (0x00U) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt_MASK (HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt(0x1FU)) #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE2 (0xE2U) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel_SHIFT (0x06U) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel(0x03U)) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel_SHIFT (0x04U) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel(0x03U)) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel_SHIFT (0x02U) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel(0x03U)) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel_SHIFT (0x00U) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel(0x03U)) #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE3 (0xE3U) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh_SHIFT (0x07U) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS_SHIFT (0x06U) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel_SHIFT (0x04U) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg_SHIFT (0x03U) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg_SHIFT (0x02U) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg_SHIFT (0x01U) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg_SHIFT (0x00U) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE4 (0xE4U) #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat_SHIFT (0x04U) #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat_MASK (HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat(0x0FU)) #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat_SHIFT (0x03U) #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat_MASK (HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE5 (0xE5U) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv_SHIFT (0x07U) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh_SHIFT (0x05U) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh(0x03U)) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit_SHIFT (0x04U) #define HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR_SHIFT (0x03U) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud_SHIFT (0x01U) #define HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud_SHIFT) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM_SHIFT (0x00U) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM(0x01U)) #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM_SHIFT) /* Registers in Bank 1 */ #define HDMI_TX_REGPktAudCTS0 (0x30U) // 7:0 #define HDMI_TX_REGPktAudCTS1 (0x31U) // 15:8 #define HDMI_TX_REGPktAudCTS2 (0x32U) // 19:16 #define HDMI_TX_REGPktAudN0 (0x33U) // 7:0 #define HDMI_TX_REGPktAudN1 (0x34U) // 15:8 #define HDMI_TX_REGPktAudN2 (0x35U) // 19:16 #define HDMI_TX_REGPktAudCTSCnt0 (0x35U) // 3:0 #define HDMI_TX_REGPktAudCTSCnt1 (0x36U) // 11:4 #define HDMI_TX_REGPktAudCTSCnt2 (0x37U) // 19:12 #define HDMI_TX_AVIINFO_DB1 (0x58U) #define HDMI_TX_AVIINFO_SUM (0x5DU) #define HDMI_TX_PKT_AUDINFO_CC (0x68U) // [2:0] #define HDMI_TX_PKT_AUDINFO_SF (0x69U) // [4:2] #define HDMI_TX_PKT_AUDINFO_CA (0x6BU) // [7:0] #define HDMI_TX_PKT_AUDINFO_DM_LSV (0x6CU) // [7][6:3] #define HDMI_TX_PKT_AUDINFO_SUM (0x6DU) // [7:0] #define HDMI_TX_AUDCHST_MODE (0x91U) #define HDMI_TX_AUDCHST_CAT (0x92U) #define HDMI_TX_AUDCHST_SRCNUM (0x93U) #define HDMI_TX_AUD0CHST_CHTNUM (0x94U) #define HDMI_TX_AUDCHST_CA_FS (0x98U) #define HDMI_TX_AUDCHST_OFS_WL (0x99U) #define HDMITX_MAX_DEV_COUNT 1 /////////////////////////////////////////////////////////////////////// // Output Mode Type /////////////////////////////////////////////////////////////////////// #define RES_ASPEC_4x3 0 #define RES_ASPEC_16x9 1 #define F_MODE_REPT_NO 0 #define F_MODE_REPT_TWICE 1 #define F_MODE_REPT_QUATRO 3 #define F_MODE_CSC_ITU601 0 #define F_MODE_CSC_ITU709 1 #define TIMER_LOOP_LEN 10 #define MS(x) (((x) + (TIMER_LOOP_LEN - 1)) / TIMER_LOOP_LEN); // for timer loop // #define SUPPORT_AUDI_AudSWL 16 // Jeilin case. #define SUPPORT_AUDI_AudSWL 24 // Jeilin case. #if (SUPPORT_AUDI_AudSWL == 16) #define CHTSTS_SWCODE 0x02U #elif (SUPPORT_AUDI_AudSWL == 18) #define CHTSTS_SWCODE 0x04U #elif (SUPPORT_AUDI_AudSWL == 20) #define CHTSTS_SWCODE 0x03U #else #define CHTSTS_SWCODE 0x0BU #endif void HDMITX_DevLoopProc(display_handle_t *handle); void HDMITX_VideoReset(display_handle_t *handle); void HDMITX_LoadRegSetting(display_handle_t *handle, RegSetTable_t *table, uint32_t table_sz); #endif // _HDMITX_H_