/* * Copyright 2021-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PM_DEVICE_H_ #define _FSL_PM_DEVICE_H_ #include "fsl_common.h" #include "fsl_pm_config.h" /* Power Mode Index */ #define PM_LP_STATE_PM0 (0U) #define PM_LP_STATE_PM1 (1U) #define PM_LP_STATE_PM2 (2U) #define PM_LP_STATE_PM3 (3U) #define PM_LP_STATE_PM4 (4U) #define PM_LP_STATE_NO_CONSTRAINT (0xFFU) /* Constraints used by application. */ #define PM_RESC_CAU_SOC_SLP_REF_CLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 0U) #define PM_RESC_SYSOSC_FRO_PLL_CLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 1U) #define PM_RESC_ENET_CLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 2U) #define PM_RESC_ENET_MEM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 4U) #define PM_RESC_ENET_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 4U) #define PM_RESC_SDIO_MEM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 5U) #define PM_RESC_SDIO_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 5U) #define PM_RESC_OTP_MEM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 6U) #define PM_RESC_OTP_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 6U) #define PM_RESC_ROM_MEM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 7U) #define PM_RESC_ROM_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 7U) #define PM_RESC_FLEXSPI_MEM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 8U) #define PM_RESC_FLEXSPI_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 8U) #define PM_RESC_POWERQUAD_MEM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 9U) #define PM_RESC_POWERQUAD_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 9U) #define PM_RESC_PKC_MEM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 10U) #define PM_RESC_PKC_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 10U) #define PM_RESC_CSS_MEM_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 11U) #define PM_RESC_CSS_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 11U) #define PM_RESC_SRAM_0K_384K_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 12U) #define PM_RESC_SRAM_0K_384K_STANDBY PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 12U) #define PM_RESC_SRAM_0K_384K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 13U) #define PM_RESC_SRAM_384K_448K_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 14U) #define PM_RESC_SRAM_384K_448K_STANDBY PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 14U) #define PM_RESC_SRAM_384K_448K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 15U) #define PM_RESC_SRAM_448K_512K_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 16U) #define PM_RESC_SRAM_448K_512K_STANDBY PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 16U) #define PM_RESC_SRAM_448K_512K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 17U) #define PM_RESC_SRAM_512K_640K_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 18U) #define PM_RESC_SRAM_512K_640K_STANDBY PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 18U) #define PM_RESC_SRAM_512K_640K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 19U) #define PM_RESC_SRAM_640K_896K_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 20U) #define PM_RESC_SRAM_640K_896K_STANDBY PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 20U) #define PM_RESC_SRAM_640K_896K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 21U) #define PM_RESC_SRAM_896K_1216K_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 22U) #define PM_RESC_SRAM_896K_1216K_STANDBY PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 22U) #define PM_RESC_SRAM_896K_1216K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 23U) #define PM_RESC_AON_MEM_0K_8K_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 24U) #define PM_RESC_AON_MEM_0K_8K_STANDBY PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 24U) #define PM_RESC_AON_MEM_0K_8K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 25U) #define PM_RESC_AON_MEM_8K_16K_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 26U) #define PM_RESC_AON_MEM_8K_16K_STANDBY PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 26U) #define PM_RESC_AON_MEM_8K_16K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 27U) #define PM_RESC_GAU_ANA_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 28U) #define PM_RESC_USB_ANA_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 29U) #define PM_RESC_BUCK18_NORMAL PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 30U) #define PM_RESC_BUCK18_SLEEP PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 30U) #define PM_RESC_BUCK11_NORMAL PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 31U) #define PM_RESC_BUCK11_SLEEP PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 31U) #if FSL_PM_SUPPORT_WAKEUP_SOURCE_MANAGER #define PM_WSID_WAKEUP_PIN0_LOW_LEVEL PM_ENCODE_WAKEUP_SOURCE_ID(PIN0_INT_IRQn, 0UL) #define PM_WSID_WAKEUP_PIN0_HIGH_LEVEL PM_ENCODE_WAKEUP_SOURCE_ID(PIN0_INT_IRQn, 1UL) #define PM_WSID_WAKEUP_PIN1_LOW_LEVEL PM_ENCODE_WAKEUP_SOURCE_ID(PIN1_INT_IRQn, 0UL) #define PM_WSID_WAKEUP_PIN1_HIGH_LEVEL PM_ENCODE_WAKEUP_SOURCE_ID(PIN1_INT_IRQn, 1UL) /* The other WSID is identical to the XX_IRQn macro in RW610.h */ #endif /* FSL_PM_SUPPORT_WAKEUP_SOURCE_MANAGER */ #endif /* _FSL_PM_DEVICE_H_ */