/*
 * NOTE: File generated by lpc_cfg_utils.py
 * from LPC55S36JBD100/signal_configuration.xml
 *
 * Copyright 2022 NXP
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef _ZEPHYR_DTS_BINDING_LPC55S36JBD100_
#define _ZEPHYR_DTS_BINDING_LPC55S36JBD100_

#define IOCON_MUX(offset, type, mux)		\
	(((offset & 0xFFF) << 20) |		\
	(((type) & 0x3) << 18) |		\
	(((mux) & 0xF) << 0))

#define IOCON_TYPE_D 0x0
#define IOCON_TYPE_I 0x1
#define IOCON_TYPE_A 0x2

#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */
#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */
#define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */
#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
#define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */
#define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */
#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */
#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */
#define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */
#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */
#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */
#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */
#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */
#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */
#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */
#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */
#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */
#define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */
#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */
#define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */
#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
#define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */
#define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */
#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */
#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */
#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */
#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */
#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */
#define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */
#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
#define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */
#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */
#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */
#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */
#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */
#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */
#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */
#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */
#define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */
#define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */
#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
#define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */
#define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */
#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */
#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */
#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */
#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */
#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */
#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */
#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */
#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
#define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */
#define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */
#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */
#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */
#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */
#define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */
#define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */
#define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */
#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
#define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */
#define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
#define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */
#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */
#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */
#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */
#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */
#define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */
#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */
#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */
#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */
#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */
#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */
#define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */
#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
#define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */
#define QSPI_CS0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 9) /* PIO0_7 */
#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */
#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */
#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */
#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */
#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */
#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */
#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */
#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */
#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */
#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */
#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */
#define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */
#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */
#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */
#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */
#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
#define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */
#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */
#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */
#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */
#define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */
#define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */
#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */
#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */
#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */
#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */
#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */
#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */
#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */
#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */
#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */
#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */
#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */
#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */
#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */
#define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define ADC0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define ADC1_CH3A_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define ADC1_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define ADC1_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define ADC1_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define ADC1_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define AOI1_OUT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 12) /* PIO0_12 */
#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG023_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG024_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG025_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG026_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG027_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG028_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG029_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG030_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG031_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG032_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG033_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG034_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG035_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG036_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG037_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG038_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG039_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG040_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG041_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG042_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG043_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG044_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG045_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG046_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG047_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG048_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG049_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG050_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG051_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */
#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 7) /* PIO0_12 */
#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define PIO0_12_PIO0_12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */
#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */
#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */
#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */
#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */
#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */
#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
#define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */
#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */
#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */
#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */
#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */
#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */
#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
#define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */
#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */
#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */
#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */
#define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */
#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */
#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */
#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */
#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */
#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */
#define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */
#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */
#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */
#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */
#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */
#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */
#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */
#define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */
#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */
#define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */
#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */
#define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
#define QSPI_SCLK_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 9) /* PIO0_17 */
#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */
#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */
#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */
#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */
#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */
#define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */
#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */
#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */
#define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */
#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
#define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */
#define QSPI_DIN1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 12) /* PIO0_18 */
#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */
#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */
#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */
#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */
#define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */
#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */
#define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */
#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */
#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */
#define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */
#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */
#define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */
#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
#define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */
#define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */
#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */
#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */
#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */
#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */
#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */
#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */
#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */
#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */
#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */
#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
#define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */
#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */
#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */
#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */
#define SPI_CS0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 12) /* PIO0_20 */
#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */
#define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */
#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */
#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */
#define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */
#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */
#define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */
#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */
#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
#define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */
#define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
#define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */
#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */
#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */
#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */
#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */
#define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define ADC0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define ADC1_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define ADC1_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define ADC1_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define ADC1_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define CT_INP15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG023_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG024_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG025_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG026_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG027_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG028_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG029_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG030_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG031_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG032_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG033_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG034_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG035_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG036_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG037_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG038_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG039_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG040_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG041_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG042_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG043_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG044_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG045_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG046_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG047_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG048_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG049_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG050_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG051_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define ENC0_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define ENC0_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define ENC1_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define ENC1_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define EXTTRIG_IN5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */
#define FC7_RTS_SCL_SSEL1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */
#define FLEXSPI0_SCLK_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 5) /* PIO0_22 */
#define FLEXSPI0_SS1_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 6) /* PIO0_22 */
#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PIO0_22_PIO0_22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
#define PWM0_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
#define PWM1_X0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 11) /* PIO0_22 */
#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */
#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */
#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */
#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */
#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */
#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */
#define ADC0_CH8B_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define ADC0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define ADC1_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define ADC1_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define ADC1_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define ADC1_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */
#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */
#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG024_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG025_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG026_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG027_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG028_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG029_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG030_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG031_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG032_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG033_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG034_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG035_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG036_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG037_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG038_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG039_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG040_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG041_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG042_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG043_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG044_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG045_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG046_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG047_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG048_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG049_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG050_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG051_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */
#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */
#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define PIO0_23_PIO0_23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */
#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */
#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */
#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */
#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */
#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */
#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
#define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */
#define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */
#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */
#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */
#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */
#define SPI_CS0_DIS_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 12) /* PIO0_24 */
#define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */
#define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define ADC0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define ADC1_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define ADC1_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define ADC1_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define ADC1_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define CT_INP9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG023_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG024_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG026_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG027_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG028_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG029_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG030_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG031_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG032_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG033_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG034_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG035_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG036_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG037_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG038_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG039_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG040_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG041_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG042_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG043_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG044_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG045_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG046_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG047_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG048_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG049_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG050_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG051_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define ENC0_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define ENC0_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define ENC1_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define ENC1_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define EXTTRIG_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */
#define FLEXSPI0_DQS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */
#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define HSCMP0_OUT_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 7) /* PIO0_25 */
#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PIO0_25_PIO0_25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
#define PWM0_A0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 11) /* PIO0_25 */
#define PWM0_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */
#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */
#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */
#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */
#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */
#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */
#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */
#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */
#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */
#define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */
#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */
#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */
#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */
#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */
#define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */
#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */
#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */
#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */
#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */
#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */
#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */
#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */
#define SPI_CS1_DIS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 12) /* PIO0_27 */
#define ADC0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define ADC0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define ADC1_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define ADC1_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define ADC1_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define ADC1_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define CT_INP11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG023_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG024_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG025_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG026_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG027_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG029_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG030_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG031_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG032_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG033_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG034_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG035_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG036_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG037_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG038_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG039_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG040_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG041_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG042_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG043_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG044_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG045_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG046_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG047_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG048_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG049_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG050_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG051_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */
#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define I3C0_PUR_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 8) /* PIO0_28 */
#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PIO0_28_PIO0_28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define PWM0_A2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 11) /* PIO0_28 */
#define QSPI_CS0_DIS_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 12) /* PIO0_28 */
#define RTC_TAMPER1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */
#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */
#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */
#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */
#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */
#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */
#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */
#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */
#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */
#define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */
#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
#define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */
#define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */
#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */
#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */
#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */
#define SPI_DIN_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 12) /* PIO0_29 */
#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */
#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */
#define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */
#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */
#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */
#define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */
#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
#define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */
#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */
#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */
#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */
#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */
#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */
#define ADC0_CH8A_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define ADC0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define ADC1_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define ADC1_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define ADC1_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define ADC1_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define AOI0_OUT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 12) /* PIO0_31 */
#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */
#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG023_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG024_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG025_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG026_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG027_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG028_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG029_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG030_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG032_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG033_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG034_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG035_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG036_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG037_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG038_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG039_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG040_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG041_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG042_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG043_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG044_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG045_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG046_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG047_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG048_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG049_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG050_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG051_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */
#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define PIO0_31_PIO0_31_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */
#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */
#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */
#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */
#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */
#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */
#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */
#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */
#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 12) /* PIO1_1 */
#define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */
#define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
#define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */
#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */
#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */
#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */
#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */
#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */
#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
#define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */
#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */
#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */
#define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */
#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */
#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
#define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */
#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */
#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */
#define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define ADC0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define ADC1_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define ADC1_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define ADC1_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define ADC1_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define AOI0_TRIGOUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 12) /* PIO1_4 */
#define AOI1_TRIGOUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 12) /* PIO1_4 */
#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */
#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG023_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG024_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG025_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG026_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG027_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG028_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG029_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG030_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG031_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG032_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG033_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG034_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG035_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG036_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG037_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG038_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG039_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG040_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG041_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG042_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG043_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG044_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG045_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG046_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG047_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG048_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG049_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG050_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG051_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define ENC0_PHASEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define ENC0_PHASEB_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define ENC1_PHASEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define ENC1_PHASEB_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define EXTTRIG_IN8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */
#define FC4_TXD_SCL_MISO_WS_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 7) /* PIO1_4 */
#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PIO1_4_PIO1_4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
#define PWM0_B2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 11) /* PIO1_4 */
#define PWM0_EXTA0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_EXTA1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_EXTA2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_EXTA3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_EXTA0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_EXTA1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_EXTA2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_EXTA3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */
#define SPI_DIN_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 10) /* PIO1_4 */
#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */
#define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define ADC0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define ADC1_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define ADC1_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define ADC1_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define ADC1_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define AOI0_TRIGOUT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 12) /* PIO1_5 */
#define AOI1_TRIGOUT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 12) /* PIO1_5 */
#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 3) /* PIO1_5 */
#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG023_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG024_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG025_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG026_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG027_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG028_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG029_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG030_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG031_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG032_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG033_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG034_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG035_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG036_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG037_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG038_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG039_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG040_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG041_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG042_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG043_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG044_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG045_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG046_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG047_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG048_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG049_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG050_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG051_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 1) /* PIO1_5 */
#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define HSCMP0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PIO1_5_PIO1_5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
#define PWM1_A3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 11) /* PIO1_5 */
#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
#define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define ADC0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define ADC1_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define ADC1_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define ADC1_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define ADC1_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define AOI0_TRIGOUT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 12) /* PIO1_6 */
#define AOI1_TRIGOUT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 12) /* PIO1_6 */
#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */
#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG023_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG024_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG025_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG026_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG027_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG028_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG029_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG030_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG031_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG032_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG033_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG034_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG035_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG036_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG037_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG038_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG039_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG040_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG041_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG042_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG043_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG044_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG045_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG046_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG047_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG048_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG049_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG050_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG051_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */
#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define HSCMP0_OUT_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 13) /* PIO1_6 */
#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PIO1_6_PIO1_6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
#define PWM0_A1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 11) /* PIO1_6 */
#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
#define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define ADC0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define ADC1_CH3B_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define ADC1_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define ADC1_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define ADC1_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define ADC1_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define AOI1_OUT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 12) /* PIO1_7 */
#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */
#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG023_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG024_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG025_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG026_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG027_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG028_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG029_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG030_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG031_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG032_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG033_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG034_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG035_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG036_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG037_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG038_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG039_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG040_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG041_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG042_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG043_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG044_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG045_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG046_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG047_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG048_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG049_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG050_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG051_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */
#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define PIO1_7_PIO1_7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
#define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define ADC0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define ADC1_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define ADC1_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define ADC1_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define ADC1_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define AOI0_TRIGOUT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 13) /* PIO1_8 */
#define AOI1_OUT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 12) /* PIO1_8 */
#define AOI1_TRIGOUT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 13) /* PIO1_8 */
#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG023_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG024_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG025_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG026_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG027_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG028_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG029_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG030_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG031_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG032_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG033_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG034_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG035_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG036_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG037_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG038_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG039_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG040_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG041_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG042_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG043_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG044_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG045_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG046_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG047_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG048_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG049_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG050_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG051_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */
#define FC1_SCK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 7) /* PIO1_8 */
#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */
#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PIO1_8_PIO1_8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
#define PWM0_A2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 11) /* PIO1_8 */
#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */
#define ADC0_CH0A_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define ADC0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define ADC0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define ADC1_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define ADC1_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define ADC1_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define ADC1_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define AOI1_OUT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 12) /* PIO1_9 */
#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define CT_INP4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG023_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG024_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG025_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG026_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG027_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG028_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG029_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG030_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG031_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG032_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG033_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG034_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG035_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG036_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG037_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG038_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG039_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG040_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG041_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG042_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG043_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG044_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG045_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG046_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG047_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG048_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG049_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG050_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG051_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */
#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */
#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define HSCMP0_IN4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define OPAMP0_OUT_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define PIO1_9_PIO1_9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */
#define ADC0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define ADC0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define ADC1_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define ADC1_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define ADC1_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define ADC1_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define AOI0_TRIGOUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 12) /* PIO1_10 */
#define AOI1_TRIGOUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 12) /* PIO1_10 */
#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 3) /* PIO1_10 */
#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG023_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG024_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG025_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG026_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG027_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG028_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG029_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG030_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG031_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG032_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG033_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG034_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG035_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG036_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG037_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG038_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG039_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG040_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG041_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG042_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG043_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG044_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG045_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG046_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG047_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG048_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG049_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG050_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG051_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 2) /* PIO1_10 */
#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define HSCMP1_IN3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define HSCMP2_OUT_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 13) /* PIO1_10 */
#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PIO1_10_PIO1_10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
#define PWM0_X1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 11) /* PIO1_10 */
#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 4) /* PIO1_10 */
#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */
#define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */
#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */
#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
#define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */
#define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
#define SPI_SCLK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 12) /* PIO1_11 */
#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */
#define ADC0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define ADC0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define ADC1_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define ADC1_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define ADC1_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define ADC1_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define AOI0_OUT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 12) /* PIO1_12 */
#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 3) /* PIO1_12 */
#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG023_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG024_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG025_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG026_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG027_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG028_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG029_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG030_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG031_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG032_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG033_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG034_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG035_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG036_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG037_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG038_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG039_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG040_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG041_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG042_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG043_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG044_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG045_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG046_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG047_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG048_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG049_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG050_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG051_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define ENC0_PHASEA_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define ENC0_PHASEB_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define ENC1_PHASEA_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define ENC1_PHASEB_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define EXTTRIG_IN9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 2) /* PIO1_12 */
#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define HSCMP0_IN1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 5) /* PIO1_12 */
#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PIO1_12_PIO1_12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
#define PWM0_A3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 11) /* PIO1_12 */
#define PWM0_EXTA0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_EXTA1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_EXTA2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_EXTA3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_EXTA0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_EXTA1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_EXTA2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_EXTA3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
#define QSPI_SCLK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 10) /* PIO1_12 */
#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 4) /* PIO1_12 */
#define ACMP0VREF_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define ADC0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define ADC1_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define ADC1_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define ADC1_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define ADC1_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define AOI0_OUT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 12) /* PIO1_13 */
#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define CT_INP6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG023_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG024_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG025_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG026_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG027_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG028_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG029_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG030_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG031_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG032_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG033_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG034_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG035_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG036_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG037_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG038_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG039_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG040_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG041_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG042_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG043_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG044_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG045_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG046_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG047_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG048_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG049_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG050_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG051_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 2) /* PIO1_13 */
#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PIO1_13_PIO1_13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
#define PWM1_X1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 11) /* PIO1_13 */
#define QSPI_DIN2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 10) /* PIO1_13 */
#define SCT0_OUT8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 8) /* PIO1_13 */
#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 5) /* PIO1_13 */
#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 4) /* PIO1_13 */
#define ADC0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define ADC0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define ADC1_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define ADC1_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define ADC1_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define ADC1_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */
#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG023_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG024_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG025_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG026_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG027_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG028_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG029_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG030_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG031_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG032_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG033_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG034_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG035_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG036_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG037_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG038_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG039_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG040_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG041_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG042_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG043_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG044_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG045_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG046_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG047_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG048_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG049_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG050_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG051_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define ENC0_PHASEA_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define ENC0_PHASEB_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define ENC1_PHASEA_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define ENC1_PHASEB_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define EXTTRIG_IN9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */
#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PIO1_14_PIO1_14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
#define PWM0_B3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 11) /* PIO1_14 */
#define PWM0_EXTA0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_EXTA1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_EXTA2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_EXTA3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_EXTA0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_EXTA1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_EXTA2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_EXTA3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
#define QSPI_DIN0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 12) /* PIO1_14 */
#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */
#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */
#define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define ADC0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define ADC1_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define ADC1_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define ADC1_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define ADC1_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define CT_INP7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG023_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG024_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG025_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG026_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG027_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG028_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG029_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG030_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG031_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG032_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG033_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG034_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG035_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG036_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG037_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG038_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG039_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG040_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG041_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG042_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG043_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG044_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG045_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG046_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG047_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG048_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG049_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG050_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG051_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define ENC0_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define ENC0_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define ENC1_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define ENC1_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define EXTTRIG_IN8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define FC1_SCK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 9) /* PIO1_15 */
#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */
#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */
#define FLEXSPI0_DATA5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 8) /* PIO1_15 */
#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PIO1_15_PIO1_15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
#define PWM0_B0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 11) /* PIO1_15 */
#define PWM0_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
#define QSPI_CS0_DIS_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 10) /* PIO1_15 */
#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */
#define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define ADC0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define ADC1_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define ADC1_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define ADC1_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define ADC1_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */
#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG023_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG024_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG025_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG026_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG027_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG028_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG029_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG030_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG031_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG032_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG033_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG034_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG035_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG036_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG037_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG038_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG039_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG040_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG041_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG042_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG043_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG044_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG045_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG046_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG047_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG048_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG049_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG050_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG051_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define ENC0_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define ENC0_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define ENC1_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define ENC1_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define EXTTRIG_IN7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define FC1_RXD_SDA_MOSI_DATA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 9) /* PIO1_16 */
#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */
#define FLEXSPI0_DATA4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 8) /* PIO1_16 */
#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PIO1_16_PIO1_16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
#define PWM0_B2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 11) /* PIO1_16 */
#define PWM0_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
#define QSPI_CS1_DIS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 10) /* PIO1_16 */
#define ADC0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define ADC0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define ADC1_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define ADC1_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define ADC1_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define ADC1_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define AOI1_OUT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 12) /* PIO1_17 */
#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG023_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG024_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG025_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG026_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG027_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG028_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG029_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG030_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG031_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG032_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG033_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG034_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG035_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG036_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG037_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG038_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG039_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG040_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG041_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG042_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG043_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG044_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG045_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG046_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG047_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG048_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG049_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG050_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG051_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */
#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PIO1_17_PIO1_17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
#define PWM0_B0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 11) /* PIO1_17 */
#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */
#define ADC0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define ADC0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define ADC1_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define ADC1_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define ADC1_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define ADC1_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG023_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG024_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG025_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG026_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG027_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG028_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG029_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG030_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG031_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG032_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG033_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG034_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG035_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG036_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG037_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG038_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG039_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG040_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG041_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG042_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG043_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG044_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG045_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG046_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG047_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG048_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG049_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG050_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG051_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define HSCMP2_OUT_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 13) /* PIO1_18 */
#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PIO1_18_PIO1_18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define PWM0_A2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 11) /* PIO1_18 */
#define QSPI_DIN3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 12) /* PIO1_18 */
#define RTC_ALARMOUT_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 8) /* PIO1_18 */
#define RTC_TAMPER3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */
#define ADC0_CH4B_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define ADC0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define ADC0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define ADC1_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define ADC1_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define ADC1_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define ADC1_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define AOI1_OUT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 13) /* PIO1_19 */
#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */
#define DAC1_OUT_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG023_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG024_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG025_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG026_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG027_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG028_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG029_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG030_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG031_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG032_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG033_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG034_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG035_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG036_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG037_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG038_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG039_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG040_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG041_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG042_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG043_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG044_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG045_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG046_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG047_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG048_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG049_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG050_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG051_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */
#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define HSCMP1_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define PIO1_19_PIO1_19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
#define QSPI_DIN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 10) /* PIO1_19 */
#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */
#define ADC0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define ADC0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define ADC1_CH8A_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define ADC1_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define ADC1_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define ADC1_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define ADC1_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define AOI0_OUT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 12) /* PIO1_20 */
#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define CT_INP14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG023_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG024_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG025_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG026_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG027_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG028_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG029_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG030_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG031_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG032_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG033_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG034_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG035_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG036_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG037_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG038_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG039_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG040_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG041_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG042_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG043_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG044_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG045_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG046_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG047_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG048_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG049_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG050_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG051_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 5) /* PIO1_20 */
#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 1) /* PIO1_20 */
#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PIO1_20_PIO1_20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
#define PWM0_A0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 11) /* PIO1_20 */
#define ADC0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define ADC0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define ADC1_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define ADC1_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define ADC1_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define ADC1_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define AOI0_TRIGOUT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 12) /* PIO1_21 */
#define AOI1_TRIGOUT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 12) /* PIO1_21 */
#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */
#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG023_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG024_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG025_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG026_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG027_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG028_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG029_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG030_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG031_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG032_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG033_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG034_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG035_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG036_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG037_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG038_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG039_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG040_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG041_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG042_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG043_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG044_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG045_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG046_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG047_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG048_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG049_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG050_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG051_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */
#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */
#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PIO1_21_PIO1_21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
#define PWM1_A0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 11) /* PIO1_21 */
#define ADC0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define ADC0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define ADC1_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define ADC1_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define ADC1_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define ADC1_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define AOI0_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */
#define AOI1_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */
#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 9) /* PIO1_22 */
#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 3) /* PIO1_22 */
#define DAC0_OUT_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG023_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG024_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG025_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG026_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG027_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG028_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG029_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG030_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG031_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG032_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG033_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG034_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG035_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG036_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG037_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG038_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG039_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG040_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG041_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG042_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG043_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG044_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG045_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG046_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG047_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG048_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG049_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG050_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG051_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 5) /* PIO1_22 */
#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define HSCMP1_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PIO1_22_PIO1_22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
#define PWM0_B1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 11) /* PIO1_22 */
#define QSPI_DIN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 10) /* PIO1_22 */
#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
#define ADC0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define ADC0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define ADC1_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define ADC1_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define ADC1_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define ADC1_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define AOI0_TRIGOUT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 12) /* PIO1_23 */
#define AOI1_TRIGOUT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 12) /* PIO1_23 */
#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG023_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG024_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG025_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG026_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG027_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG028_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG029_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG030_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG031_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG032_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG033_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG034_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG035_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG036_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG037_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG038_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG039_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG040_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG041_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG042_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG043_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG044_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG045_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG046_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG047_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG048_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG049_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG050_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG051_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 1) /* PIO1_23 */
#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 5) /* PIO1_23 */
#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define HSCMP2_IN1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PIO1_23_PIO1_23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
#define PWM1_A1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 11) /* PIO1_23 */
#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 2) /* PIO1_23 */
#define ADC0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define ADC0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define ADC1_CH8B_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define ADC1_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define ADC1_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define ADC1_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define ADC1_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define AOI0_OUT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 12) /* PIO1_24 */
#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG023_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG024_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG025_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG026_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG027_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG028_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG029_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG030_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG031_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG032_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG033_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG034_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG035_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG036_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG037_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG038_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG039_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG040_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG041_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG042_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG043_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG044_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG045_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG046_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG047_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG048_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG049_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG050_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG051_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 1) /* PIO1_24 */
#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 5) /* PIO1_24 */
#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define PIO1_24_PIO1_24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 2) /* PIO1_24 */
#define ADC0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define ADC0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define ADC1_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define ADC1_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define ADC1_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define ADC1_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define AOI0_OUT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 13) /* PIO1_25 */
#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG023_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG024_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG025_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG026_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG027_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG028_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG029_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG030_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG031_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG032_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG033_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG034_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG035_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG036_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG037_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG038_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG039_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG040_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG041_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG042_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG043_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG044_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG045_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG046_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG047_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG048_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG049_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG050_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG051_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */
#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PIO1_25_PIO1_25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
#define PWM1_A2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 11) /* PIO1_25 */
#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */
#define SPI_SCLK_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 12) /* PIO1_25 */
#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */
#define ADC0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define ADC0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define ADC1_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define ADC1_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define ADC1_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define ADC1_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define AOI1_OUT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 13) /* PIO1_26 */
#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define CT_INP3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG023_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG024_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG025_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG026_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG027_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG028_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG029_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG030_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG031_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG032_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG033_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG034_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG035_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG036_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG037_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG038_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG039_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG040_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG041_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG042_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG043_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG044_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG045_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG046_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG047_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG048_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG049_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG050_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG051_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */
#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */
#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PIO1_26_PIO1_26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
#define PWM0_A1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 11) /* PIO1_26 */
#define QSPI_CS1_DIS_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 12) /* PIO1_26 */
#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */
#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */
#define ADC0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define ADC0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define ADC1_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define ADC1_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define ADC1_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define ADC1_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */
#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */
#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */
#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG023_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG024_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG025_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG026_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG027_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG028_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG029_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG030_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG031_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG032_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG033_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG034_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG035_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG036_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG037_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG038_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG039_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG040_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG041_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG042_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG043_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG044_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG045_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG046_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG047_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG048_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG049_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG050_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG051_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */
#define FLEXSPI0_DATA6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 8) /* PIO1_27 */
#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PIO1_27_PIO1_27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
#define PWM1_B2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 11) /* PIO1_27 */
#define ADC0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define ADC0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define ADC1_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define ADC1_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define ADC1_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define ADC1_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define AOI0_TRIGOUT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 10) /* PIO1_28 */
#define AOI1_TRIGOUT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 10) /* PIO1_28 */
#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define CT_INP2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG023_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG024_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG025_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG026_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG027_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG028_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG029_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG030_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG031_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG032_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG033_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG034_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG035_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG036_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG037_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG038_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG039_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG040_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG041_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG042_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG043_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG044_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG045_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG046_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG047_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG048_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG049_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG050_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG051_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */
#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define HSCMP1_OUT_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 13) /* PIO1_28 */
#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PIO1_28_PIO1_28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
#define PWM1_X3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 11) /* PIO1_28 */
#define SPI_CS1_DIS_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 12) /* PIO1_28 */
#define ADC0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define ADC0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define ADC1_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define ADC1_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define ADC1_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define ADC1_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG023_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG024_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG025_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG026_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG027_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG028_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG029_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG030_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG031_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG032_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG033_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG034_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG035_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG036_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG037_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG038_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG039_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG040_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG041_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG042_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG043_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG044_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG045_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG046_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG047_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG048_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG049_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG050_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG051_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define ENC0_PHASEA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define ENC0_PHASEB_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define ENC1_PHASEA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define ENC1_PHASEB_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define EXTTRIG_IN9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */
#define FLEXSPI0_DATA7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 8) /* PIO1_29 */
#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PIO1_29_PIO1_29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
#define PWM0_EXTA0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_EXTA1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_EXTA2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_EXTA3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM0_X2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 11) /* PIO1_29 */
#define PWM1_EXTA0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_EXTA1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_EXTA2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_EXTA3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
#define ADC0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define ADC0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define ADC1_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define ADC1_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define ADC1_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define ADC1_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define AOI1_OUT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 12) /* PIO1_30 */
#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG023_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG024_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG025_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG026_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG027_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG028_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG029_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG030_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG031_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG032_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG033_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG034_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG035_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG036_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG037_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG038_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG039_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG040_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG041_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG042_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG043_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG044_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG045_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG046_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG047_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG048_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG049_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG050_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG051_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */
#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define HSCMP0_OUT_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 13) /* PIO1_30 */
#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PIO1_30_PIO1_30_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
#define PWM0_X3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 11) /* PIO1_30 */
#define QSPI_CS0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 10) /* PIO1_30 */
#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
#define ADC0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define ADC0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define ADC1_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define ADC1_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define ADC1_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define ADC1_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define AOI0_IN0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI0_IN9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define AOI1_IN9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */
#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG023_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG024_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG025_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG026_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG027_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG028_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG029_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG030_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG031_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG032_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG033_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG034_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG035_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG036_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG037_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG038_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG039_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG040_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG041_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG042_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG043_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG044_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG045_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG046_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG047_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG048_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG049_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG050_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG051_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define ENC0_PHASEA_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define ENC0_PHASEB_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define ENC1_PHASEA_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define ENC1_PHASEB_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define EXTTRIG_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */
#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PIO1_31_PIO1_31_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
#define PWM0_EXTA0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_EXTA1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_EXTA2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_EXTA3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_PWM_FAULT_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_PWM_FAULT_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_PWM_FAULT_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM0_PWM_FAULT_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_B2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 11) /* PIO1_31 */
#define PWM1_EXTA0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_EXTA1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_EXTA2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_EXTA3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_PWM_FAULT_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_PWM_FAULT_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_PWM_FAULT_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define PWM1_PWM_FAULT_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */
#define USB0_VBUS_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */
#define ADC0_CH9A_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 0) /* PIO2_0 */
#define AOI0_OUT0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 12) /* PIO2_0 */
#define CTIMER0_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER0_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER0_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER0_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER1_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER1_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER1_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER2_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER2_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER2_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER2_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER3_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER3_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER3_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER3_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER4_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER4_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER4_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CTIMER4_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define CT_INP4_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
#define FC0_RXD_SDA_MOSI_DATA_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 2) /* PIO2_0 */
#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 0) /* PIO2_0 */
#define I3C0_PUR_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 5) /* PIO2_0 */
#define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */
#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */
#define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */
#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */
#define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */
#define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */

#endif