/* * Copyright 2020-2023 NXP * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef EMAC_IP_WRAPPER_H #define EMAC_IP_WRAPPER_H /** * @file * * @internal * @addtogroup GMAC_DRIVER GMAC Driver * @{ */ #ifdef __cplusplus extern "C"{ #endif /*================================================================================================== * SOURCE FILE VERSION INFORMATION ==================================================================================================*/ #define EMAC_IP_WRAPPER_VENDOR_ID 43 #define EMAC_IP_WRAPPER_AR_RELEASE_MAJOR_VERSION 4 #define EMAC_IP_WRAPPER_AR_RELEASE_MINOR_VERSION 7 #define EMAC_IP_WRAPPER_AR_RELEASE_REVISION_VERSION 0 #define EMAC_IP_WRAPPER_SW_MAJOR_VERSION 3 #define EMAC_IP_WRAPPER_SW_MINOR_VERSION 0 #define EMAC_IP_WRAPPER_SW_PATCH_VERSION 0 /*================================================================================================== DEFINES AND MACROS ==================================================================================================*/ typedef EMAC_Type GMAC_Type; #define IP_GMAC_0_BASE IP_EMAC_BASE /** Peripheral IP_GMAC_0 base pointer */ #define IP_GMAC_0 IP_EMAC /** Array initializer of GMAC peripheral base addresses */ #define IP_GMAC_BASE_ADDRS IP_EMAC_BASE_ADDRS /** Array initializer of EMAC peripheral base pointers */ #define IP_GMAC_BASE_PTRS IP_EMAC_BASE_PTRS /* ---------------------------------------------------------------------------- -- EMAC Register Masks ---------------------------------------------------------------------------- */ /*! * @internal * @addtogroup GMAC_Register_Masks EMAC Register Masks * @{ */ /*! @name MAC_CONFIGURATION - */ /*! @{ */ #define GMAC_MAC_CONFIGURATION_RE_MASK EMAC_MAC_CONFIGURATION_RE_MASK #define GMAC_MAC_CONFIGURATION_RE_SHIFT EMAC_MAC_CONFIGURATION_RE_SHIFT #define GMAC_MAC_CONFIGURATION_RE_WIDTH EMAC_MAC_CONFIGURATION_RE_WIDTH #define GMAC_MAC_CONFIGURATION_RE(x) EMAC_MAC_CONFIGURATION_RE(x) #define GMAC_MAC_CONFIGURATION_TE_MASK EMAC_MAC_CONFIGURATION_TE_MASK #define GMAC_MAC_CONFIGURATION_TE_SHIFT EMAC_MAC_CONFIGURATION_TE_SHIFT #define GMAC_MAC_CONFIGURATION_TE_WIDTH EMAC_MAC_CONFIGURATION_TE_WIDTH #define GMAC_MAC_CONFIGURATION_TE(x) EMAC_MAC_CONFIGURATION_TE(x) #define GMAC_MAC_CONFIGURATION_PRELEN_MASK EMAC_MAC_CONFIGURATION_PRELEN_MASK #define GMAC_MAC_CONFIGURATION_PRELEN_SHIFT EMAC_MAC_CONFIGURATION_PRELEN_SHIFT #define GMAC_MAC_CONFIGURATION_PRELEN_WIDTH EMAC_MAC_CONFIGURATION_PRELEN_WIDTH #define GMAC_MAC_CONFIGURATION_PRELEN(x) EMAC_MAC_CONFIGURATION_PRELEN(x) #define GMAC_MAC_CONFIGURATION_DC_MASK EMAC_MAC_CONFIGURATION_DC_MASK #define GMAC_MAC_CONFIGURATION_DC_SHIFT EMAC_MAC_CONFIGURATION_DC_SHIFT #define GMAC_MAC_CONFIGURATION_DC_WIDTH EMAC_MAC_CONFIGURATION_DC_WIDTH #define GMAC_MAC_CONFIGURATION_DC(x) EMAC_MAC_CONFIGURATION_DC(x) #define GMAC_MAC_CONFIGURATION_BL_MASK EMAC_MAC_CONFIGURATION_BL_MASK #define GMAC_MAC_CONFIGURATION_BL_SHIFT EMAC_MAC_CONFIGURATION_BL_SHIFT #define GMAC_MAC_CONFIGURATION_BL_WIDTH EMAC_MAC_CONFIGURATION_BL_WIDTH #define GMAC_MAC_CONFIGURATION_BL(x) EMAC_MAC_CONFIGURATION_BL(x) #define GMAC_MAC_CONFIGURATION_DR_MASK EMAC_MAC_CONFIGURATION_DR_MASK #define GMAC_MAC_CONFIGURATION_DR_SHIFT EMAC_MAC_CONFIGURATION_DR_SHIFT #define GMAC_MAC_CONFIGURATION_DR_WIDTH EMAC_MAC_CONFIGURATION_DR_WIDTH #define GMAC_MAC_CONFIGURATION_DR(x) EMAC_MAC_CONFIGURATION_DR(x) #define GMAC_MAC_CONFIGURATION_DCRS_MASK EMAC_MAC_CONFIGURATION_DCRS_MASK #define GMAC_MAC_CONFIGURATION_DCRS_SHIFT EMAC_MAC_CONFIGURATION_DCRS_SHIFT #define GMAC_MAC_CONFIGURATION_DCRS_WIDTH EMAC_MAC_CONFIGURATION_DCRS_WIDTH #define GMAC_MAC_CONFIGURATION_DCRS(x) EMAC_MAC_CONFIGURATION_DCRS(x) #define GMAC_MAC_CONFIGURATION_DO_MASK EMAC_MAC_CONFIGURATION_DO_MASK #define GMAC_MAC_CONFIGURATION_DO_SHIFT EMAC_MAC_CONFIGURATION_DO_SHIFT #define GMAC_MAC_CONFIGURATION_DO_WIDTH EMAC_MAC_CONFIGURATION_DO_WIDTH #define GMAC_MAC_CONFIGURATION_DO(x) EMAC_MAC_CONFIGURATION_DO(x) #define GMAC_MAC_CONFIGURATION_ECRSFD_MASK EMAC_MAC_CONFIGURATION_ECRSFD_MASK #define GMAC_MAC_CONFIGURATION_ECRSFD_SHIFT EMAC_MAC_CONFIGURATION_ECRSFD_SHIFT #define GMAC_MAC_CONFIGURATION_ECRSFD_WIDTH EMAC_MAC_CONFIGURATION_ECRSFD_WIDTH #define GMAC_MAC_CONFIGURATION_ECRSFD(x) EMAC_MAC_CONFIGURATION_ECRSFD(x) #define GMAC_MAC_CONFIGURATION_LM_MASK EMAC_MAC_CONFIGURATION_LM_MASK #define GMAC_MAC_CONFIGURATION_LM_SHIFT EMAC_MAC_CONFIGURATION_LM_SHIFT #define GMAC_MAC_CONFIGURATION_LM_WIDTH EMAC_MAC_CONFIGURATION_LM_WIDTH #define GMAC_MAC_CONFIGURATION_LM(x) EMAC_MAC_CONFIGURATION_LM(x) #define GMAC_MAC_CONFIGURATION_DM_MASK EMAC_MAC_CONFIGURATION_DM_MASK #define GMAC_MAC_CONFIGURATION_DM_SHIFT EMAC_MAC_CONFIGURATION_DM_SHIFT #define GMAC_MAC_CONFIGURATION_DM_WIDTH EMAC_MAC_CONFIGURATION_DM_WIDTH #define GMAC_MAC_CONFIGURATION_DM(x) EMAC_MAC_CONFIGURATION_DM(x) #define GMAC_MAC_CONFIGURATION_FES_MASK EMAC_MAC_CONFIGURATION_FES_MASK #define GMAC_MAC_CONFIGURATION_FES_SHIFT EMAC_MAC_CONFIGURATION_FES_SHIFT #define GMAC_MAC_CONFIGURATION_FES_WIDTH EMAC_MAC_CONFIGURATION_FES_WIDTH #define GMAC_MAC_CONFIGURATION_FES(x) EMAC_MAC_CONFIGURATION_FES(x) #define GMAC_MAC_CONFIGURATION_PS_MASK EMAC_MAC_CONFIGURATION_PS_MASK #define GMAC_MAC_CONFIGURATION_PS_SHIFT EMAC_MAC_CONFIGURATION_PS_SHIFT #define GMAC_MAC_CONFIGURATION_PS_WIDTH EMAC_MAC_CONFIGURATION_PS_WIDTH #define GMAC_MAC_CONFIGURATION_PS(x) EMAC_MAC_CONFIGURATION_PS(x) #define GMAC_MAC_CONFIGURATION_JE_MASK EMAC_MAC_CONFIGURATION_JE_MASK #define GMAC_MAC_CONFIGURATION_JE_SHIFT EMAC_MAC_CONFIGURATION_JE_SHIFT #define GMAC_MAC_CONFIGURATION_JE_WIDTH EMAC_MAC_CONFIGURATION_JE_WIDTH #define GMAC_MAC_CONFIGURATION_JE(x) EMAC_MAC_CONFIGURATION_JE(x) #define GMAC_MAC_CONFIGURATION_JD_MASK EMAC_MAC_CONFIGURATION_JD_MASK #define GMAC_MAC_CONFIGURATION_JD_SHIFT EMAC_MAC_CONFIGURATION_JD_SHIFT #define GMAC_MAC_CONFIGURATION_JD_WIDTH EMAC_MAC_CONFIGURATION_JD_WIDTH #define GMAC_MAC_CONFIGURATION_JD(x) EMAC_MAC_CONFIGURATION_JD(x) #define GMAC_MAC_CONFIGURATION_WD_MASK EMAC_MAC_CONFIGURATION_WD_MASK #define GMAC_MAC_CONFIGURATION_WD_SHIFT EMAC_MAC_CONFIGURATION_WD_SHIFT #define GMAC_MAC_CONFIGURATION_WD_WIDTH EMAC_MAC_CONFIGURATION_WD_WIDTH #define GMAC_MAC_CONFIGURATION_WD(x) EMAC_MAC_CONFIGURATION_WD(x) #define GMAC_MAC_CONFIGURATION_ACS_MASK EMAC_MAC_CONFIGURATION_ACS_MASK #define GMAC_MAC_CONFIGURATION_ACS_SHIFT EMAC_MAC_CONFIGURATION_ACS_SHIFT #define GMAC_MAC_CONFIGURATION_ACS_WIDTH EMAC_MAC_CONFIGURATION_ACS_WIDTH #define GMAC_MAC_CONFIGURATION_ACS(x) EMAC_MAC_CONFIGURATION_ACS(x) #define GMAC_MAC_CONFIGURATION_CST_MASK EMAC_MAC_CONFIGURATION_CST_MASK #define GMAC_MAC_CONFIGURATION_CST_SHIFT EMAC_MAC_CONFIGURATION_CST_SHIFT #define GMAC_MAC_CONFIGURATION_CST_WIDTH EMAC_MAC_CONFIGURATION_CST_WIDTH #define GMAC_MAC_CONFIGURATION_CST(x) EMAC_MAC_CONFIGURATION_CST(x) #define GMAC_MAC_CONFIGURATION_S2KP_MASK EMAC_MAC_CONFIGURATION_S2KP_MASK #define GMAC_MAC_CONFIGURATION_S2KP_SHIFT EMAC_MAC_CONFIGURATION_S2KP_SHIFT #define GMAC_MAC_CONFIGURATION_S2KP_WIDTH EMAC_MAC_CONFIGURATION_S2KP_WIDTH #define GMAC_MAC_CONFIGURATION_S2KP(x) EMAC_MAC_CONFIGURATION_S2KP(x) #define GMAC_MAC_CONFIGURATION_GPSLCE_MASK EMAC_MAC_CONFIGURATION_GPSLCE_MASK #define GMAC_MAC_CONFIGURATION_GPSLCE_SHIFT EMAC_MAC_CONFIGURATION_GPSLCE_SHIFT #define GMAC_MAC_CONFIGURATION_GPSLCE_WIDTH EMAC_MAC_CONFIGURATION_GPSLCE_WIDTH #define GMAC_MAC_CONFIGURATION_GPSLCE(x) EMAC_MAC_CONFIGURATION_GPSLCE(x) #define GMAC_MAC_CONFIGURATION_IPG_MASK EMAC_MAC_CONFIGURATION_IPG_MASK #define GMAC_MAC_CONFIGURATION_IPG_SHIFT EMAC_MAC_CONFIGURATION_IPG_SHIFT #define GMAC_MAC_CONFIGURATION_IPG_WIDTH EMAC_MAC_CONFIGURATION_IPG_WIDTH #define GMAC_MAC_CONFIGURATION_IPG(x) EMAC_MAC_CONFIGURATION_IPG(x) #define GMAC_MAC_CONFIGURATION_IPC_MASK EMAC_MAC_CONFIGURATION_IPC_MASK #define GMAC_MAC_CONFIGURATION_IPC_SHIFT EMAC_MAC_CONFIGURATION_IPC_SHIFT #define GMAC_MAC_CONFIGURATION_IPC_WIDTH EMAC_MAC_CONFIGURATION_IPC_WIDTH #define GMAC_MAC_CONFIGURATION_IPC(x) EMAC_MAC_CONFIGURATION_IPC(x) #define GMAC_MAC_CONFIGURATION_SARC_MASK EMAC_MAC_CONFIGURATION_SARC_MASK #define GMAC_MAC_CONFIGURATION_SARC_SHIFT EMAC_MAC_CONFIGURATION_SARC_SHIFT #define GMAC_MAC_CONFIGURATION_SARC_WIDTH EMAC_MAC_CONFIGURATION_SARC_WIDTH #define GMAC_MAC_CONFIGURATION_SARC(x) EMAC_MAC_CONFIGURATION_SARC(x) /*! @} */ /*! @name MAC_EXT_CONFIGURATION - */ /*! @{ */ #define GMAC_MAC_EXT_CONFIGURATION_GPSL_MASK EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK #define GMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT #define GMAC_MAC_EXT_CONFIGURATION_GPSL_WIDTH EMAC_MAC_EXT_CONFIGURATION_GPSL_WIDTH #define GMAC_MAC_EXT_CONFIGURATION_GPSL(x) EMAC_MAC_EXT_CONFIGURATION_GPSL(x) #define GMAC_MAC_EXT_CONFIGURATION_DCRCC_MASK EMAC_MAC_EXT_CONFIGURATION_DCRCC_MASK #define GMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT EMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT #define GMAC_MAC_EXT_CONFIGURATION_DCRCC_WIDTH EMAC_MAC_EXT_CONFIGURATION_DCRCC_WIDTH #define GMAC_MAC_EXT_CONFIGURATION_DCRCC(x) EMAC_MAC_EXT_CONFIGURATION_DCRCC(x) #define GMAC_MAC_EXT_CONFIGURATION_SPEN_MASK EMAC_MAC_EXT_CONFIGURATION_SPEN_MASK #define GMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT EMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT #define GMAC_MAC_EXT_CONFIGURATION_SPEN_WIDTH EMAC_MAC_EXT_CONFIGURATION_SPEN_WIDTH #define GMAC_MAC_EXT_CONFIGURATION_SPEN(x) EMAC_MAC_EXT_CONFIGURATION_SPEN(x) #define GMAC_MAC_EXT_CONFIGURATION_USP_MASK EMAC_MAC_EXT_CONFIGURATION_USP_MASK #define GMAC_MAC_EXT_CONFIGURATION_USP_SHIFT EMAC_MAC_EXT_CONFIGURATION_USP_SHIFT #define GMAC_MAC_EXT_CONFIGURATION_USP_WIDTH EMAC_MAC_EXT_CONFIGURATION_USP_WIDTH #define GMAC_MAC_EXT_CONFIGURATION_USP(x) EMAC_MAC_EXT_CONFIGURATION_USP(x) #define GMAC_MAC_EXT_CONFIGURATION_PDC_MASK EMAC_MAC_EXT_CONFIGURATION_PDC_MASK #define GMAC_MAC_EXT_CONFIGURATION_PDC_SHIFT EMAC_MAC_EXT_CONFIGURATION_PDC_SHIFT #define GMAC_MAC_EXT_CONFIGURATION_PDC_WIDTH EMAC_MAC_EXT_CONFIGURATION_PDC_WIDTH #define GMAC_MAC_EXT_CONFIGURATION_PDC(x) EMAC_MAC_EXT_CONFIGURATION_PDC(x) #define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_MASK EMAC_MAC_EXT_CONFIGURATION_EIPGEN_MASK #define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT EMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT #define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_WIDTH EMAC_MAC_EXT_CONFIGURATION_EIPGEN_WIDTH #define GMAC_MAC_EXT_CONFIGURATION_EIPGEN(x) EMAC_MAC_EXT_CONFIGURATION_EIPGEN(x) #define GMAC_MAC_EXT_CONFIGURATION_EIPG_MASK EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK #define GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT #define GMAC_MAC_EXT_CONFIGURATION_EIPG_WIDTH EMAC_MAC_EXT_CONFIGURATION_EIPG_WIDTH #define GMAC_MAC_EXT_CONFIGURATION_EIPG(x) EMAC_MAC_EXT_CONFIGURATION_EIPG(x) /*! @} */ /*! @name MAC_PACKET_FILTER - */ /*! @{ */ #define GMAC_MAC_PACKET_FILTER_PR_MASK EMAC_MAC_PACKET_FILTER_PR_MASK #define GMAC_MAC_PACKET_FILTER_PR_SHIFT EMAC_MAC_PACKET_FILTER_PR_SHIFT #define GMAC_MAC_PACKET_FILTER_PR_WIDTH EMAC_MAC_PACKET_FILTER_PR_WIDTH #define GMAC_MAC_PACKET_FILTER_PR(x) EMAC_MAC_PACKET_FILTER_PR(x) #define GMAC_MAC_PACKET_FILTER_HUC_MASK EMAC_MAC_PACKET_FILTER_HUC_MASK #define GMAC_MAC_PACKET_FILTER_HUC_SHIFT EMAC_MAC_PACKET_FILTER_HUC_SHIFT #define GMAC_MAC_PACKET_FILTER_HUC_WIDTH EMAC_MAC_PACKET_FILTER_HUC_WIDTH #define GMAC_MAC_PACKET_FILTER_HUC(x) EMAC_MAC_PACKET_FILTER_HUC(x) #define GMAC_MAC_PACKET_FILTER_HMC_MASK EMAC_MAC_PACKET_FILTER_HMC_MASK #define GMAC_MAC_PACKET_FILTER_HMC_SHIFT EMAC_MAC_PACKET_FILTER_HMC_SHIFT #define GMAC_MAC_PACKET_FILTER_HMC_WIDTH EMAC_MAC_PACKET_FILTER_HMC_WIDTH #define GMAC_MAC_PACKET_FILTER_HMC(x) EMAC_MAC_PACKET_FILTER_HMC(x) #define GMAC_MAC_PACKET_FILTER_DAIF_MASK EMAC_MAC_PACKET_FILTER_DAIF_MASK #define GMAC_MAC_PACKET_FILTER_DAIF_SHIFT EMAC_MAC_PACKET_FILTER_DAIF_SHIFT #define GMAC_MAC_PACKET_FILTER_DAIF_WIDTH EMAC_MAC_PACKET_FILTER_DAIF_WIDTH #define GMAC_MAC_PACKET_FILTER_DAIF(x) EMAC_MAC_PACKET_FILTER_DAIF(x) #define GMAC_MAC_PACKET_FILTER_PM_MASK EMAC_MAC_PACKET_FILTER_PM_MASK #define GMAC_MAC_PACKET_FILTER_PM_SHIFT EMAC_MAC_PACKET_FILTER_PM_SHIFT #define GMAC_MAC_PACKET_FILTER_PM_WIDTH EMAC_MAC_PACKET_FILTER_PM_WIDTH #define GMAC_MAC_PACKET_FILTER_PM(x) EMAC_MAC_PACKET_FILTER_PM(x) #define GMAC_MAC_PACKET_FILTER_DBF_MASK EMAC_MAC_PACKET_FILTER_DBF_MASK #define GMAC_MAC_PACKET_FILTER_DBF_SHIFT EMAC_MAC_PACKET_FILTER_DBF_SHIFT #define GMAC_MAC_PACKET_FILTER_DBF_WIDTH EMAC_MAC_PACKET_FILTER_DBF_WIDTH #define GMAC_MAC_PACKET_FILTER_DBF(x) EMAC_MAC_PACKET_FILTER_DBF(x) #define GMAC_MAC_PACKET_FILTER_PCF_MASK EMAC_MAC_PACKET_FILTER_PCF_MASK #define GMAC_MAC_PACKET_FILTER_PCF_SHIFT EMAC_MAC_PACKET_FILTER_PCF_SHIFT #define GMAC_MAC_PACKET_FILTER_PCF_WIDTH EMAC_MAC_PACKET_FILTER_PCF_WIDTH #define GMAC_MAC_PACKET_FILTER_PCF(x) EMAC_MAC_PACKET_FILTER_PCF(x) #define GMAC_MAC_PACKET_FILTER_SAIF_MASK EMAC_MAC_PACKET_FILTER_SAIF_MASK #define GMAC_MAC_PACKET_FILTER_SAIF_SHIFT EMAC_MAC_PACKET_FILTER_SAIF_SHIFT #define GMAC_MAC_PACKET_FILTER_SAIF_WIDTH EMAC_MAC_PACKET_FILTER_SAIF_WIDTH #define GMAC_MAC_PACKET_FILTER_SAIF(x) EMAC_MAC_PACKET_FILTER_SAIF(x) #define GMAC_MAC_PACKET_FILTER_SAF_MASK EMAC_MAC_PACKET_FILTER_SAF_MASK #define GMAC_MAC_PACKET_FILTER_SAF_SHIFT EMAC_MAC_PACKET_FILTER_SAF_SHIFT #define GMAC_MAC_PACKET_FILTER_SAF_WIDTH EMAC_MAC_PACKET_FILTER_SAF_WIDTH #define GMAC_MAC_PACKET_FILTER_SAF(x) EMAC_MAC_PACKET_FILTER_SAF(x) #define GMAC_MAC_PACKET_FILTER_HPF_MASK EMAC_MAC_PACKET_FILTER_HPF_MASK #define GMAC_MAC_PACKET_FILTER_HPF_SHIFT EMAC_MAC_PACKET_FILTER_HPF_SHIFT #define GMAC_MAC_PACKET_FILTER_HPF_WIDTH EMAC_MAC_PACKET_FILTER_HPF_WIDTH #define GMAC_MAC_PACKET_FILTER_HPF(x) EMAC_MAC_PACKET_FILTER_HPF(x) #define GMAC_MAC_PACKET_FILTER_VTFE_MASK EMAC_MAC_PACKET_FILTER_VTFE_MASK #define GMAC_MAC_PACKET_FILTER_VTFE_SHIFT EMAC_MAC_PACKET_FILTER_VTFE_SHIFT #define GMAC_MAC_PACKET_FILTER_VTFE_WIDTH EMAC_MAC_PACKET_FILTER_VTFE_WIDTH #define GMAC_MAC_PACKET_FILTER_VTFE(x) EMAC_MAC_PACKET_FILTER_VTFE(x) #define GMAC_MAC_PACKET_FILTER_IPFE_MASK EMAC_MAC_PACKET_FILTER_IPFE_MASK #define GMAC_MAC_PACKET_FILTER_IPFE_SHIFT EMAC_MAC_PACKET_FILTER_IPFE_SHIFT #define GMAC_MAC_PACKET_FILTER_IPFE_WIDTH EMAC_MAC_PACKET_FILTER_IPFE_WIDTH #define GMAC_MAC_PACKET_FILTER_IPFE(x) EMAC_MAC_PACKET_FILTER_IPFE(x) #define GMAC_MAC_PACKET_FILTER_DNTU_MASK EMAC_MAC_PACKET_FILTER_DNTU_MASK #define GMAC_MAC_PACKET_FILTER_DNTU_SHIFT EMAC_MAC_PACKET_FILTER_DNTU_SHIFT #define GMAC_MAC_PACKET_FILTER_DNTU_WIDTH EMAC_MAC_PACKET_FILTER_DNTU_WIDTH #define GMAC_MAC_PACKET_FILTER_DNTU(x) EMAC_MAC_PACKET_FILTER_DNTU(x) #define GMAC_MAC_PACKET_FILTER_RA_MASK EMAC_MAC_PACKET_FILTER_RA_MASK #define GMAC_MAC_PACKET_FILTER_RA_SHIFT EMAC_MAC_PACKET_FILTER_RA_SHIFT #define GMAC_MAC_PACKET_FILTER_RA_WIDTH EMAC_MAC_PACKET_FILTER_RA_WIDTH #define GMAC_MAC_PACKET_FILTER_RA(x) EMAC_MAC_PACKET_FILTER_RA(x) /*! @} */ /*! @name MAC_WATCHDOG_TIMEOUT - */ /*! @{ */ #define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK #define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT #define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_WIDTH EMAC_MAC_WATCHDOG_TIMEOUT_WTO_WIDTH #define GMAC_MAC_WATCHDOG_TIMEOUT_WTO(x) EMAC_MAC_WATCHDOG_TIMEOUT_WTO(x) #define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_MASK EMAC_MAC_WATCHDOG_TIMEOUT_PWE_MASK #define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT EMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT #define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_WIDTH EMAC_MAC_WATCHDOG_TIMEOUT_PWE_WIDTH #define GMAC_MAC_WATCHDOG_TIMEOUT_PWE(x) EMAC_MAC_WATCHDOG_TIMEOUT_PWE(x) /*! @} */ /*! @name MAC_HASH_TABLE_REG0 - */ /*! @{ */ #define GMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK #define GMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT #define GMAC_MAC_HASH_TABLE_REG0_HT31T0_WIDTH EMAC_MAC_HASH_TABLE_REG0_HT31T0_WIDTH #define GMAC_MAC_HASH_TABLE_REG0_HT31T0(x) EMAC_MAC_HASH_TABLE_REG0_HT31T0(x) /*! @} */ /*! @name MAC_HASH_TABLE_REG1 - */ /*! @{ */ #define GMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK #define GMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT #define GMAC_MAC_HASH_TABLE_REG1_HT63T32_WIDTH EMAC_MAC_HASH_TABLE_REG1_HT63T32_WIDTH #define GMAC_MAC_HASH_TABLE_REG1_HT63T32(x) EMAC_MAC_HASH_TABLE_REG1_HT63T32(x) /*! @} */ /*! @name MAC_VLAN_TAG_CTRL - */ /*! @{ */ #define GMAC_MAC_VLAN_TAG_CTRL_OB_MASK EMAC_MAC_VLAN_TAG_CTRL_OB_MASK #define GMAC_MAC_VLAN_TAG_CTRL_OB_SHIFT EMAC_MAC_VLAN_TAG_CTRL_OB_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_OB_WIDTH EMAC_MAC_VLAN_TAG_CTRL_OB_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_OB(x) EMAC_MAC_VLAN_TAG_CTRL_OB(x) #define GMAC_MAC_VLAN_TAG_CTRL_CT_MASK EMAC_MAC_VLAN_TAG_CTRL_CT_MASK #define GMAC_MAC_VLAN_TAG_CTRL_CT_SHIFT EMAC_MAC_VLAN_TAG_CTRL_CT_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_CT_WIDTH EMAC_MAC_VLAN_TAG_CTRL_CT_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_CT(x) EMAC_MAC_VLAN_TAG_CTRL_CT(x) #define GMAC_MAC_VLAN_TAG_CTRL_OFS_MASK EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK #define GMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_OFS_WIDTH EMAC_MAC_VLAN_TAG_CTRL_OFS_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_OFS(x) EMAC_MAC_VLAN_TAG_CTRL_OFS(x) #define GMAC_MAC_VLAN_TAG_CTRL_ETV_MASK EMAC_MAC_VLAN_TAG_CTRL_ETV_MASK #define GMAC_MAC_VLAN_TAG_CTRL_ETV_SHIFT EMAC_MAC_VLAN_TAG_CTRL_ETV_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_ETV_WIDTH EMAC_MAC_VLAN_TAG_CTRL_ETV_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_ETV(x) EMAC_MAC_VLAN_TAG_CTRL_ETV(x) #define GMAC_MAC_VLAN_TAG_CTRL_VTIM_MASK EMAC_MAC_VLAN_TAG_CTRL_VTIM_MASK #define GMAC_MAC_VLAN_TAG_CTRL_VTIM_SHIFT EMAC_MAC_VLAN_TAG_CTRL_VTIM_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_VTIM_WIDTH EMAC_MAC_VLAN_TAG_CTRL_VTIM_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_VTIM(x) EMAC_MAC_VLAN_TAG_CTRL_VTIM(x) #define GMAC_MAC_VLAN_TAG_CTRL_ESVL_MASK EMAC_MAC_VLAN_TAG_CTRL_ESVL_MASK #define GMAC_MAC_VLAN_TAG_CTRL_ESVL_SHIFT EMAC_MAC_VLAN_TAG_CTRL_ESVL_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_ESVL_WIDTH EMAC_MAC_VLAN_TAG_CTRL_ESVL_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_ESVL(x) EMAC_MAC_VLAN_TAG_CTRL_ESVL(x) #define GMAC_MAC_VLAN_TAG_CTRL_ERSVLM_MASK EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_MASK #define GMAC_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_ERSVLM_WIDTH EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_ERSVLM(x) EMAC_MAC_VLAN_TAG_CTRL_ERSVLM(x) #define GMAC_MAC_VLAN_TAG_CTRL_DOVLTC_MASK EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_MASK #define GMAC_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_DOVLTC_WIDTH EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_DOVLTC(x) EMAC_MAC_VLAN_TAG_CTRL_DOVLTC(x) #define GMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK #define GMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_EVLS_WIDTH EMAC_MAC_VLAN_TAG_CTRL_EVLS_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_EVLS(x) EMAC_MAC_VLAN_TAG_CTRL_EVLS(x) #define GMAC_MAC_VLAN_TAG_CTRL_EVLRXS_MASK EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_MASK #define GMAC_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_EVLRXS_WIDTH EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_EVLRXS(x) EMAC_MAC_VLAN_TAG_CTRL_EVLRXS(x) #define GMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK EMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK #define GMAC_MAC_VLAN_TAG_CTRL_VTHM_SHIFT EMAC_MAC_VLAN_TAG_CTRL_VTHM_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_VTHM_WIDTH EMAC_MAC_VLAN_TAG_CTRL_VTHM_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_VTHM(x) EMAC_MAC_VLAN_TAG_CTRL_VTHM(x) #define GMAC_MAC_VLAN_TAG_CTRL_EDVLP_MASK EMAC_MAC_VLAN_TAG_CTRL_EDVLP_MASK #define GMAC_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT EMAC_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_EDVLP_WIDTH EMAC_MAC_VLAN_TAG_CTRL_EDVLP_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_EDVLP(x) EMAC_MAC_VLAN_TAG_CTRL_EDVLP(x) #define GMAC_MAC_VLAN_TAG_CTRL_ERIVLT_MASK EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_MASK #define GMAC_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_ERIVLT_WIDTH EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_ERIVLT(x) EMAC_MAC_VLAN_TAG_CTRL_ERIVLT(x) #define GMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK #define GMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_EIVLS_WIDTH EMAC_MAC_VLAN_TAG_CTRL_EIVLS_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_EIVLS(x) EMAC_MAC_VLAN_TAG_CTRL_EIVLS(x) #define GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK #define GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT #define GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_WIDTH EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_WIDTH #define GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS(x) EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS(x) /*! @} */ /*! @name MAC_VLAN_TAG_DATA - */ /*! @{ */ #define GMAC_MAC_VLAN_TAG_DATA_VID_MASK EMAC_MAC_VLAN_TAG_DATA_VID_MASK #define GMAC_MAC_VLAN_TAG_DATA_VID_SHIFT EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT #define GMAC_MAC_VLAN_TAG_DATA_VID_WIDTH EMAC_MAC_VLAN_TAG_DATA_VID_WIDTH #define GMAC_MAC_VLAN_TAG_DATA_VID(x) EMAC_MAC_VLAN_TAG_DATA_VID(x) #define GMAC_MAC_VLAN_TAG_DATA_VEN_MASK EMAC_MAC_VLAN_TAG_DATA_VEN_MASK #define GMAC_MAC_VLAN_TAG_DATA_VEN_SHIFT EMAC_MAC_VLAN_TAG_DATA_VEN_SHIFT #define GMAC_MAC_VLAN_TAG_DATA_VEN_WIDTH EMAC_MAC_VLAN_TAG_DATA_VEN_WIDTH #define GMAC_MAC_VLAN_TAG_DATA_VEN(x) EMAC_MAC_VLAN_TAG_DATA_VEN(x) #define GMAC_MAC_VLAN_TAG_DATA_ETV_MASK EMAC_MAC_VLAN_TAG_DATA_ETV_MASK #define GMAC_MAC_VLAN_TAG_DATA_ETV_SHIFT EMAC_MAC_VLAN_TAG_DATA_ETV_SHIFT #define GMAC_MAC_VLAN_TAG_DATA_ETV_WIDTH EMAC_MAC_VLAN_TAG_DATA_ETV_WIDTH #define GMAC_MAC_VLAN_TAG_DATA_ETV(x) EMAC_MAC_VLAN_TAG_DATA_ETV(x) #define GMAC_MAC_VLAN_TAG_DATA_DOVLTC_MASK EMAC_MAC_VLAN_TAG_DATA_DOVLTC_MASK #define GMAC_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT EMAC_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT #define GMAC_MAC_VLAN_TAG_DATA_DOVLTC_WIDTH EMAC_MAC_VLAN_TAG_DATA_DOVLTC_WIDTH #define GMAC_MAC_VLAN_TAG_DATA_DOVLTC(x) EMAC_MAC_VLAN_TAG_DATA_DOVLTC(x) #define GMAC_MAC_VLAN_TAG_DATA_ERSVLM_MASK EMAC_MAC_VLAN_TAG_DATA_ERSVLM_MASK #define GMAC_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT EMAC_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT #define GMAC_MAC_VLAN_TAG_DATA_ERSVLM_WIDTH EMAC_MAC_VLAN_TAG_DATA_ERSVLM_WIDTH #define GMAC_MAC_VLAN_TAG_DATA_ERSVLM(x) EMAC_MAC_VLAN_TAG_DATA_ERSVLM(x) #define GMAC_MAC_VLAN_TAG_DATA_ERIVLT_MASK EMAC_MAC_VLAN_TAG_DATA_ERIVLT_MASK #define GMAC_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT EMAC_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT #define GMAC_MAC_VLAN_TAG_DATA_ERIVLT_WIDTH EMAC_MAC_VLAN_TAG_DATA_ERIVLT_WIDTH #define GMAC_MAC_VLAN_TAG_DATA_ERIVLT(x) EMAC_MAC_VLAN_TAG_DATA_ERIVLT(x) #define GMAC_MAC_VLAN_TAG_DATA_DMACHEN_MASK EMAC_MAC_VLAN_TAG_DATA_DMACHEN_MASK #define GMAC_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT EMAC_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT #define GMAC_MAC_VLAN_TAG_DATA_DMACHEN_WIDTH EMAC_MAC_VLAN_TAG_DATA_DMACHEN_WIDTH #define GMAC_MAC_VLAN_TAG_DATA_DMACHEN(x) EMAC_MAC_VLAN_TAG_DATA_DMACHEN(x) #define GMAC_MAC_VLAN_TAG_DATA_DMACHN_MASK EMAC_MAC_VLAN_TAG_DATA_DMACHN_MASK #define GMAC_MAC_VLAN_TAG_DATA_DMACHN_SHIFT EMAC_MAC_VLAN_TAG_DATA_DMACHN_SHIFT #define GMAC_MAC_VLAN_TAG_DATA_DMACHN_WIDTH EMAC_MAC_VLAN_TAG_DATA_DMACHN_WIDTH #define GMAC_MAC_VLAN_TAG_DATA_DMACHN(x) EMAC_MAC_VLAN_TAG_DATA_DMACHN(x) /*! @} */ /*! @name MAC_VLAN_HASH_TABLE - */ /*! @{ */ #define GMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK #define GMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT #define GMAC_MAC_VLAN_HASH_TABLE_VLHT_WIDTH EMAC_MAC_VLAN_HASH_TABLE_VLHT_WIDTH #define GMAC_MAC_VLAN_HASH_TABLE_VLHT(x) EMAC_MAC_VLAN_HASH_TABLE_VLHT(x) /*! @} */ /*! @name MAC_VLAN_INCL - */ /*! @{ */ #define GMAC_MAC_VLAN_INCL_VLT_MASK EMAC_MAC_VLAN_INCL_VLT_MASK #define GMAC_MAC_VLAN_INCL_VLT_SHIFT EMAC_MAC_VLAN_INCL_VLT_SHIFT #define GMAC_MAC_VLAN_INCL_VLT_WIDTH EMAC_MAC_VLAN_INCL_VLT_WIDTH #define GMAC_MAC_VLAN_INCL_VLT(x) EMAC_MAC_VLAN_INCL_VLT(x) #define GMAC_MAC_VLAN_INCL_VLC_MASK EMAC_MAC_VLAN_INCL_VLC_MASK #define GMAC_MAC_VLAN_INCL_VLC_SHIFT EMAC_MAC_VLAN_INCL_VLC_SHIFT #define GMAC_MAC_VLAN_INCL_VLC_WIDTH EMAC_MAC_VLAN_INCL_VLC_WIDTH #define GMAC_MAC_VLAN_INCL_VLC(x) EMAC_MAC_VLAN_INCL_VLC(x) #define GMAC_MAC_VLAN_INCL_VLP_MASK EMAC_MAC_VLAN_INCL_VLP_MASK #define GMAC_MAC_VLAN_INCL_VLP_SHIFT EMAC_MAC_VLAN_INCL_VLP_SHIFT #define GMAC_MAC_VLAN_INCL_VLP_WIDTH EMAC_MAC_VLAN_INCL_VLP_WIDTH #define GMAC_MAC_VLAN_INCL_VLP(x) EMAC_MAC_VLAN_INCL_VLP(x) #define GMAC_MAC_VLAN_INCL_CSVL_MASK EMAC_MAC_VLAN_INCL_CSVL_MASK #define GMAC_MAC_VLAN_INCL_CSVL_SHIFT EMAC_MAC_VLAN_INCL_CSVL_SHIFT #define GMAC_MAC_VLAN_INCL_CSVL_WIDTH EMAC_MAC_VLAN_INCL_CSVL_WIDTH #define GMAC_MAC_VLAN_INCL_CSVL(x) EMAC_MAC_VLAN_INCL_CSVL(x) #define GMAC_MAC_VLAN_INCL_VLTI_MASK EMAC_MAC_VLAN_INCL_VLTI_MASK #define GMAC_MAC_VLAN_INCL_VLTI_SHIFT EMAC_MAC_VLAN_INCL_VLTI_SHIFT #define GMAC_MAC_VLAN_INCL_VLTI_WIDTH EMAC_MAC_VLAN_INCL_VLTI_WIDTH #define GMAC_MAC_VLAN_INCL_VLTI(x) EMAC_MAC_VLAN_INCL_VLTI(x) #define GMAC_MAC_VLAN_INCL_CBTI_MASK EMAC_MAC_VLAN_INCL_CBTI_MASK #define GMAC_MAC_VLAN_INCL_CBTI_SHIFT EMAC_MAC_VLAN_INCL_CBTI_SHIFT #define GMAC_MAC_VLAN_INCL_CBTI_WIDTH EMAC_MAC_VLAN_INCL_CBTI_WIDTH #define GMAC_MAC_VLAN_INCL_CBTI(x) EMAC_MAC_VLAN_INCL_CBTI(x) #define GMAC_MAC_VLAN_INCL_ADDR_MASK EMAC_MAC_VLAN_INCL_ADDR_MASK #define GMAC_MAC_VLAN_INCL_ADDR_SHIFT EMAC_MAC_VLAN_INCL_ADDR_SHIFT #define GMAC_MAC_VLAN_INCL_ADDR_WIDTH EMAC_MAC_VLAN_INCL_ADDR_WIDTH #define GMAC_MAC_VLAN_INCL_ADDR(x) EMAC_MAC_VLAN_INCL_ADDR(x) #define GMAC_MAC_VLAN_INCL_RDWR_MASK EMAC_MAC_VLAN_INCL_RDWR_MASK #define GMAC_MAC_VLAN_INCL_RDWR_SHIFT EMAC_MAC_VLAN_INCL_RDWR_SHIFT #define GMAC_MAC_VLAN_INCL_RDWR_WIDTH EMAC_MAC_VLAN_INCL_RDWR_WIDTH #define GMAC_MAC_VLAN_INCL_RDWR(x) EMAC_MAC_VLAN_INCL_RDWR(x) #define GMAC_MAC_VLAN_INCL_BUSY_MASK EMAC_MAC_VLAN_INCL_BUSY_MASK #define GMAC_MAC_VLAN_INCL_BUSY_SHIFT EMAC_MAC_VLAN_INCL_BUSY_SHIFT #define GMAC_MAC_VLAN_INCL_BUSY_WIDTH EMAC_MAC_VLAN_INCL_BUSY_WIDTH #define GMAC_MAC_VLAN_INCL_BUSY(x) EMAC_MAC_VLAN_INCL_BUSY(x) /*! @} */ /*! @name MAC_INNER_VLAN_INCL - */ /*! @{ */ #define GMAC_MAC_INNER_VLAN_INCL_VLT_MASK EMAC_MAC_INNER_VLAN_INCL_VLT_MASK #define GMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT #define GMAC_MAC_INNER_VLAN_INCL_VLT_WIDTH EMAC_MAC_INNER_VLAN_INCL_VLT_WIDTH #define GMAC_MAC_INNER_VLAN_INCL_VLT(x) EMAC_MAC_INNER_VLAN_INCL_VLT(x) #define GMAC_MAC_INNER_VLAN_INCL_VLC_MASK EMAC_MAC_INNER_VLAN_INCL_VLC_MASK #define GMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT #define GMAC_MAC_INNER_VLAN_INCL_VLC_WIDTH EMAC_MAC_INNER_VLAN_INCL_VLC_WIDTH #define GMAC_MAC_INNER_VLAN_INCL_VLC(x) EMAC_MAC_INNER_VLAN_INCL_VLC(x) #define GMAC_MAC_INNER_VLAN_INCL_VLP_MASK EMAC_MAC_INNER_VLAN_INCL_VLP_MASK #define GMAC_MAC_INNER_VLAN_INCL_VLP_SHIFT EMAC_MAC_INNER_VLAN_INCL_VLP_SHIFT #define GMAC_MAC_INNER_VLAN_INCL_VLP_WIDTH EMAC_MAC_INNER_VLAN_INCL_VLP_WIDTH #define GMAC_MAC_INNER_VLAN_INCL_VLP(x) EMAC_MAC_INNER_VLAN_INCL_VLP(x) #define GMAC_MAC_INNER_VLAN_INCL_CSVL_MASK EMAC_MAC_INNER_VLAN_INCL_CSVL_MASK #define GMAC_MAC_INNER_VLAN_INCL_CSVL_SHIFT EMAC_MAC_INNER_VLAN_INCL_CSVL_SHIFT #define GMAC_MAC_INNER_VLAN_INCL_CSVL_WIDTH EMAC_MAC_INNER_VLAN_INCL_CSVL_WIDTH #define GMAC_MAC_INNER_VLAN_INCL_CSVL(x) EMAC_MAC_INNER_VLAN_INCL_CSVL(x) #define GMAC_MAC_INNER_VLAN_INCL_VLTI_MASK EMAC_MAC_INNER_VLAN_INCL_VLTI_MASK #define GMAC_MAC_INNER_VLAN_INCL_VLTI_SHIFT EMAC_MAC_INNER_VLAN_INCL_VLTI_SHIFT #define GMAC_MAC_INNER_VLAN_INCL_VLTI_WIDTH EMAC_MAC_INNER_VLAN_INCL_VLTI_WIDTH #define GMAC_MAC_INNER_VLAN_INCL_VLTI(x) EMAC_MAC_INNER_VLAN_INCL_VLTI(x) /*! @} */ /*! @name MAC_Q0_TX_FLOW_CTRL - */ /*! @{ */ #define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK #define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT #define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_WIDTH EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_WIDTH #define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA(x) EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA(x) #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_WIDTH EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_WIDTH #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE(x) EMAC_MAC_Q0_TX_FLOW_CTRL_TFE(x) #define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK #define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT #define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_WIDTH EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_WIDTH #define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT(x) EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(x) #define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK #define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT #define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_WIDTH EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_WIDTH #define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ(x) EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ(x) #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_WIDTH EMAC_MAC_Q0_TX_FLOW_CTRL_PT_WIDTH #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT(x) EMAC_MAC_Q0_TX_FLOW_CTRL_PT(x) /*! @} */ /*! @name MAC_RX_FLOW_CTRL - */ /*! @{ */ #define GMAC_MAC_RX_FLOW_CTRL_RFE_MASK EMAC_MAC_RX_FLOW_CTRL_RFE_MASK #define GMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT EMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT #define GMAC_MAC_RX_FLOW_CTRL_RFE_WIDTH EMAC_MAC_RX_FLOW_CTRL_RFE_WIDTH #define GMAC_MAC_RX_FLOW_CTRL_RFE(x) EMAC_MAC_RX_FLOW_CTRL_RFE(x) #define GMAC_MAC_RX_FLOW_CTRL_UP_MASK EMAC_MAC_RX_FLOW_CTRL_UP_MASK #define GMAC_MAC_RX_FLOW_CTRL_UP_SHIFT EMAC_MAC_RX_FLOW_CTRL_UP_SHIFT #define GMAC_MAC_RX_FLOW_CTRL_UP_WIDTH EMAC_MAC_RX_FLOW_CTRL_UP_WIDTH #define GMAC_MAC_RX_FLOW_CTRL_UP(x) EMAC_MAC_RX_FLOW_CTRL_UP(x) /*! @} */ /*! @name MAC_RXQ_CTRL4 - */ /*! @{ */ #define GMAC_MAC_RXQ_CTRL4_UFFQE_MASK EMAC_MAC_RXQ_CTRL4_UFFQE_MASK #define GMAC_MAC_RXQ_CTRL4_UFFQE_SHIFT EMAC_MAC_RXQ_CTRL4_UFFQE_SHIFT #define GMAC_MAC_RXQ_CTRL4_UFFQE_WIDTH EMAC_MAC_RXQ_CTRL4_UFFQE_WIDTH #define GMAC_MAC_RXQ_CTRL4_UFFQE(x) EMAC_MAC_RXQ_CTRL4_UFFQE(x) #define GMAC_MAC_RXQ_CTRL4_UFFQ_MASK EMAC_MAC_RXQ_CTRL4_UFFQ_MASK #define GMAC_MAC_RXQ_CTRL4_UFFQ_SHIFT EMAC_MAC_RXQ_CTRL4_UFFQ_SHIFT #define GMAC_MAC_RXQ_CTRL4_UFFQ_WIDTH EMAC_MAC_RXQ_CTRL4_UFFQ_WIDTH #define GMAC_MAC_RXQ_CTRL4_UFFQ(x) EMAC_MAC_RXQ_CTRL4_UFFQ(x) #define GMAC_MAC_RXQ_CTRL4_MFFQE_MASK EMAC_MAC_RXQ_CTRL4_MFFQE_MASK #define GMAC_MAC_RXQ_CTRL4_MFFQE_SHIFT EMAC_MAC_RXQ_CTRL4_MFFQE_SHIFT #define GMAC_MAC_RXQ_CTRL4_MFFQE_WIDTH EMAC_MAC_RXQ_CTRL4_MFFQE_WIDTH #define GMAC_MAC_RXQ_CTRL4_MFFQE(x) EMAC_MAC_RXQ_CTRL4_MFFQE(x) #define GMAC_MAC_RXQ_CTRL4_MFFQ_MASK EMAC_MAC_RXQ_CTRL4_MFFQ_MASK #define GMAC_MAC_RXQ_CTRL4_MFFQ_SHIFT EMAC_MAC_RXQ_CTRL4_MFFQ_SHIFT #define GMAC_MAC_RXQ_CTRL4_MFFQ_WIDTH EMAC_MAC_RXQ_CTRL4_MFFQ_WIDTH #define GMAC_MAC_RXQ_CTRL4_MFFQ(x) EMAC_MAC_RXQ_CTRL4_MFFQ(x) #define GMAC_MAC_RXQ_CTRL4_VFFQE_MASK EMAC_MAC_RXQ_CTRL4_VFFQE_MASK #define GMAC_MAC_RXQ_CTRL4_VFFQE_SHIFT EMAC_MAC_RXQ_CTRL4_VFFQE_SHIFT #define GMAC_MAC_RXQ_CTRL4_VFFQE_WIDTH EMAC_MAC_RXQ_CTRL4_VFFQE_WIDTH #define GMAC_MAC_RXQ_CTRL4_VFFQE(x) EMAC_MAC_RXQ_CTRL4_VFFQE(x) #define GMAC_MAC_RXQ_CTRL4_VFFQ_MASK EMAC_MAC_RXQ_CTRL4_VFFQ_MASK #define GMAC_MAC_RXQ_CTRL4_VFFQ_SHIFT EMAC_MAC_RXQ_CTRL4_VFFQ_SHIFT #define GMAC_MAC_RXQ_CTRL4_VFFQ_WIDTH EMAC_MAC_RXQ_CTRL4_VFFQ_WIDTH #define GMAC_MAC_RXQ_CTRL4_VFFQ(x) EMAC_MAC_RXQ_CTRL4_VFFQ(x) /*! @} */ /*! @name MAC_RXQ_CTRL0 - */ /*! @{ */ #define GMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK #define GMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT #define GMAC_MAC_RXQ_CTRL0_RXQ0EN_WIDTH EMAC_MAC_RXQ_CTRL0_RXQ0EN_WIDTH #define GMAC_MAC_RXQ_CTRL0_RXQ0EN(x) EMAC_MAC_RXQ_CTRL0_RXQ0EN(x) #define GMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK #define GMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT #define GMAC_MAC_RXQ_CTRL0_RXQ1EN_WIDTH EMAC_MAC_RXQ_CTRL0_RXQ1EN_WIDTH #define GMAC_MAC_RXQ_CTRL0_RXQ1EN(x) EMAC_MAC_RXQ_CTRL0_RXQ1EN(x) /*! @} */ /*! @name MAC_RXQ_CTRL1 - */ /*! @{ */ #define GMAC_MAC_RXQ_CTRL1_AVCPQ_MASK EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK #define GMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT #define GMAC_MAC_RXQ_CTRL1_AVCPQ_WIDTH EMAC_MAC_RXQ_CTRL1_AVCPQ_WIDTH #define GMAC_MAC_RXQ_CTRL1_AVCPQ(x) EMAC_MAC_RXQ_CTRL1_AVCPQ(x) #define GMAC_MAC_RXQ_CTRL1_PTPQ_MASK EMAC_MAC_RXQ_CTRL1_PTPQ_MASK #define GMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT #define GMAC_MAC_RXQ_CTRL1_PTPQ_WIDTH EMAC_MAC_RXQ_CTRL1_PTPQ_WIDTH #define GMAC_MAC_RXQ_CTRL1_PTPQ(x) EMAC_MAC_RXQ_CTRL1_PTPQ(x) #define GMAC_MAC_RXQ_CTRL1_UPQ_MASK EMAC_MAC_RXQ_CTRL1_UPQ_MASK #define GMAC_MAC_RXQ_CTRL1_UPQ_SHIFT EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT #define GMAC_MAC_RXQ_CTRL1_UPQ_WIDTH EMAC_MAC_RXQ_CTRL1_UPQ_WIDTH #define GMAC_MAC_RXQ_CTRL1_UPQ(x) EMAC_MAC_RXQ_CTRL1_UPQ(x) #define GMAC_MAC_RXQ_CTRL1_MCBCQ_MASK EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK #define GMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT #define GMAC_MAC_RXQ_CTRL1_MCBCQ_WIDTH EMAC_MAC_RXQ_CTRL1_MCBCQ_WIDTH #define GMAC_MAC_RXQ_CTRL1_MCBCQ(x) EMAC_MAC_RXQ_CTRL1_MCBCQ(x) #define GMAC_MAC_RXQ_CTRL1_MCBCQEN_MASK EMAC_MAC_RXQ_CTRL1_MCBCQEN_MASK #define GMAC_MAC_RXQ_CTRL1_MCBCQEN_SHIFT EMAC_MAC_RXQ_CTRL1_MCBCQEN_SHIFT #define GMAC_MAC_RXQ_CTRL1_MCBCQEN_WIDTH EMAC_MAC_RXQ_CTRL1_MCBCQEN_WIDTH #define GMAC_MAC_RXQ_CTRL1_MCBCQEN(x) EMAC_MAC_RXQ_CTRL1_MCBCQEN(x) #define GMAC_MAC_RXQ_CTRL1_TACPQE_MASK EMAC_MAC_RXQ_CTRL1_TACPQE_MASK #define GMAC_MAC_RXQ_CTRL1_TACPQE_SHIFT EMAC_MAC_RXQ_CTRL1_TACPQE_SHIFT #define GMAC_MAC_RXQ_CTRL1_TACPQE_WIDTH EMAC_MAC_RXQ_CTRL1_TACPQE_WIDTH #define GMAC_MAC_RXQ_CTRL1_TACPQE(x) EMAC_MAC_RXQ_CTRL1_TACPQE(x) #define GMAC_MAC_RXQ_CTRL1_TPQC_MASK EMAC_MAC_RXQ_CTRL1_TPQC_MASK #define GMAC_MAC_RXQ_CTRL1_TPQC_SHIFT EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT #define GMAC_MAC_RXQ_CTRL1_TPQC_WIDTH EMAC_MAC_RXQ_CTRL1_TPQC_WIDTH #define GMAC_MAC_RXQ_CTRL1_TPQC(x) EMAC_MAC_RXQ_CTRL1_TPQC(x) #define GMAC_MAC_RXQ_CTRL1_FPRQ_MASK EMAC_MAC_RXQ_CTRL1_FPRQ_MASK #define GMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT #define GMAC_MAC_RXQ_CTRL1_FPRQ_WIDTH EMAC_MAC_RXQ_CTRL1_FPRQ_WIDTH #define GMAC_MAC_RXQ_CTRL1_FPRQ(x) EMAC_MAC_RXQ_CTRL1_FPRQ(x) /*! @} */ /*! @name MAC_RXQ_CTRL2 - */ /*! @{ */ #define GMAC_MAC_RXQ_CTRL2_PSRQ0_MASK EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK #define GMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT #define GMAC_MAC_RXQ_CTRL2_PSRQ0_WIDTH EMAC_MAC_RXQ_CTRL2_PSRQ0_WIDTH #define GMAC_MAC_RXQ_CTRL2_PSRQ0(x) EMAC_MAC_RXQ_CTRL2_PSRQ0(x) #define GMAC_MAC_RXQ_CTRL2_PSRQ1_MASK EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK #define GMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT #define GMAC_MAC_RXQ_CTRL2_PSRQ1_WIDTH EMAC_MAC_RXQ_CTRL2_PSRQ1_WIDTH #define GMAC_MAC_RXQ_CTRL2_PSRQ1(x) EMAC_MAC_RXQ_CTRL2_PSRQ1(x) /*! @} */ /*! @name MAC_INTERRUPT_STATUS - */ /*! @{ */ #define GMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK EMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_PHYIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_PHYIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_PHYIS(x) EMAC_MAC_INTERRUPT_STATUS_PHYIS(x) #define GMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK EMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_MMCIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_MMCIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_MMCIS(x) EMAC_MAC_INTERRUPT_STATUS_MMCIS(x) #define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS(x) EMAC_MAC_INTERRUPT_STATUS_MMCRXIS(x) #define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS(x) EMAC_MAC_INTERRUPT_STATUS_MMCTXIS(x) #define GMAC_MAC_INTERRUPT_STATUS_TSIS_MASK EMAC_MAC_INTERRUPT_STATUS_TSIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_TSIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_TSIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_TSIS(x) EMAC_MAC_INTERRUPT_STATUS_TSIS(x) #define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS(x) EMAC_MAC_INTERRUPT_STATUS_TXSTSIS(x) #define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS(x) EMAC_MAC_INTERRUPT_STATUS_RXSTSIS(x) #define GMAC_MAC_INTERRUPT_STATUS_FPEIS_MASK EMAC_MAC_INTERRUPT_STATUS_FPEIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_FPEIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_FPEIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_FPEIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_FPEIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_FPEIS(x) EMAC_MAC_INTERRUPT_STATUS_FPEIS(x) #define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK EMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_MDIOIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_MDIOIS(x) EMAC_MAC_INTERRUPT_STATUS_MDIOIS(x) #define GMAC_MAC_INTERRUPT_STATUS_MFTIS_MASK EMAC_MAC_INTERRUPT_STATUS_MFTIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_MFTIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_MFTIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_MFTIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_MFTIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_MFTIS(x) EMAC_MAC_INTERRUPT_STATUS_MFTIS(x) #define GMAC_MAC_INTERRUPT_STATUS_MFRIS_MASK EMAC_MAC_INTERRUPT_STATUS_MFRIS_MASK #define GMAC_MAC_INTERRUPT_STATUS_MFRIS_SHIFT EMAC_MAC_INTERRUPT_STATUS_MFRIS_SHIFT #define GMAC_MAC_INTERRUPT_STATUS_MFRIS_WIDTH EMAC_MAC_INTERRUPT_STATUS_MFRIS_WIDTH #define GMAC_MAC_INTERRUPT_STATUS_MFRIS(x) EMAC_MAC_INTERRUPT_STATUS_MFRIS(x) /*! @} */ /*! @name MAC_INTERRUPT_ENABLE - */ /*! @{ */ #define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_MASK EMAC_MAC_INTERRUPT_ENABLE_PHYIE_MASK #define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT EMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT #define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_WIDTH EMAC_MAC_INTERRUPT_ENABLE_PHYIE_WIDTH #define GMAC_MAC_INTERRUPT_ENABLE_PHYIE(x) EMAC_MAC_INTERRUPT_ENABLE_PHYIE(x) #define GMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK EMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK #define GMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT EMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT #define GMAC_MAC_INTERRUPT_ENABLE_TSIE_WIDTH EMAC_MAC_INTERRUPT_ENABLE_TSIE_WIDTH #define GMAC_MAC_INTERRUPT_ENABLE_TSIE(x) EMAC_MAC_INTERRUPT_ENABLE_TSIE(x) #define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK #define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT #define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_WIDTH EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_WIDTH #define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE(x) EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE(x) #define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK #define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT #define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_WIDTH EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_WIDTH #define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE(x) EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE(x) #define GMAC_MAC_INTERRUPT_ENABLE_FPEIE_MASK EMAC_MAC_INTERRUPT_ENABLE_FPEIE_MASK #define GMAC_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT EMAC_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT #define GMAC_MAC_INTERRUPT_ENABLE_FPEIE_WIDTH EMAC_MAC_INTERRUPT_ENABLE_FPEIE_WIDTH #define GMAC_MAC_INTERRUPT_ENABLE_FPEIE(x) EMAC_MAC_INTERRUPT_ENABLE_FPEIE(x) #define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_MASK EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_MASK #define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT #define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_WIDTH EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_WIDTH #define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE(x) EMAC_MAC_INTERRUPT_ENABLE_MDIOIE(x) /*! @} */ /*! @name MAC_RX_TX_STATUS - */ /*! @{ */ #define GMAC_MAC_RX_TX_STATUS_TJT_MASK EMAC_MAC_RX_TX_STATUS_TJT_MASK #define GMAC_MAC_RX_TX_STATUS_TJT_SHIFT EMAC_MAC_RX_TX_STATUS_TJT_SHIFT #define GMAC_MAC_RX_TX_STATUS_TJT_WIDTH EMAC_MAC_RX_TX_STATUS_TJT_WIDTH #define GMAC_MAC_RX_TX_STATUS_TJT(x) EMAC_MAC_RX_TX_STATUS_TJT(x) #define GMAC_MAC_RX_TX_STATUS_NCARR_MASK EMAC_MAC_RX_TX_STATUS_NCARR_MASK #define GMAC_MAC_RX_TX_STATUS_NCARR_SHIFT EMAC_MAC_RX_TX_STATUS_NCARR_SHIFT #define GMAC_MAC_RX_TX_STATUS_NCARR_WIDTH EMAC_MAC_RX_TX_STATUS_NCARR_WIDTH #define GMAC_MAC_RX_TX_STATUS_NCARR(x) EMAC_MAC_RX_TX_STATUS_NCARR(x) #define GMAC_MAC_RX_TX_STATUS_LCARR_MASK EMAC_MAC_RX_TX_STATUS_LCARR_MASK #define GMAC_MAC_RX_TX_STATUS_LCARR_SHIFT EMAC_MAC_RX_TX_STATUS_LCARR_SHIFT #define GMAC_MAC_RX_TX_STATUS_LCARR_WIDTH EMAC_MAC_RX_TX_STATUS_LCARR_WIDTH #define GMAC_MAC_RX_TX_STATUS_LCARR(x) EMAC_MAC_RX_TX_STATUS_LCARR(x) #define GMAC_MAC_RX_TX_STATUS_EXDEF_MASK EMAC_MAC_RX_TX_STATUS_EXDEF_MASK #define GMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT EMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT #define GMAC_MAC_RX_TX_STATUS_EXDEF_WIDTH EMAC_MAC_RX_TX_STATUS_EXDEF_WIDTH #define GMAC_MAC_RX_TX_STATUS_EXDEF(x) EMAC_MAC_RX_TX_STATUS_EXDEF(x) #define GMAC_MAC_RX_TX_STATUS_LCOL_MASK EMAC_MAC_RX_TX_STATUS_LCOL_MASK #define GMAC_MAC_RX_TX_STATUS_LCOL_SHIFT EMAC_MAC_RX_TX_STATUS_LCOL_SHIFT #define GMAC_MAC_RX_TX_STATUS_LCOL_WIDTH EMAC_MAC_RX_TX_STATUS_LCOL_WIDTH #define GMAC_MAC_RX_TX_STATUS_LCOL(x) EMAC_MAC_RX_TX_STATUS_LCOL(x) #define GMAC_MAC_RX_TX_STATUS_EXCOL_MASK EMAC_MAC_RX_TX_STATUS_EXCOL_MASK #define GMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT EMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT #define GMAC_MAC_RX_TX_STATUS_EXCOL_WIDTH EMAC_MAC_RX_TX_STATUS_EXCOL_WIDTH #define GMAC_MAC_RX_TX_STATUS_EXCOL(x) EMAC_MAC_RX_TX_STATUS_EXCOL(x) #define GMAC_MAC_RX_TX_STATUS_RWT_MASK EMAC_MAC_RX_TX_STATUS_RWT_MASK #define GMAC_MAC_RX_TX_STATUS_RWT_SHIFT EMAC_MAC_RX_TX_STATUS_RWT_SHIFT #define GMAC_MAC_RX_TX_STATUS_RWT_WIDTH EMAC_MAC_RX_TX_STATUS_RWT_WIDTH #define GMAC_MAC_RX_TX_STATUS_RWT(x) EMAC_MAC_RX_TX_STATUS_RWT(x) /*! @} */ /*! @name MAC_VERSION - */ /*! @{ */ #define GMAC_MAC_VERSION_IPVER_MASK EMAC_MAC_VERSION_IPVER_MASK #define GMAC_MAC_VERSION_IPVER_SHIFT EMAC_MAC_VERSION_IPVER_SHIFT #define GMAC_MAC_VERSION_IPVER_WIDTH EMAC_MAC_VERSION_IPVER_WIDTH #define GMAC_MAC_VERSION_IPVER(x) EMAC_MAC_VERSION_IPVER(x) #define GMAC_MAC_VERSION_CFGVER_MASK EMAC_MAC_VERSION_CFGVER_MASK #define GMAC_MAC_VERSION_CFGVER_SHIFT EMAC_MAC_VERSION_CFGVER_SHIFT #define GMAC_MAC_VERSION_CFGVER_WIDTH EMAC_MAC_VERSION_CFGVER_WIDTH #define GMAC_MAC_VERSION_CFGVER(x) EMAC_MAC_VERSION_CFGVER(x) /*! @} */ /*! @name MAC_DEBUG - */ /*! @{ */ #define GMAC_MAC_DEBUG_RPESTS_MASK EMAC_MAC_DEBUG_RPESTS_MASK #define GMAC_MAC_DEBUG_RPESTS_SHIFT EMAC_MAC_DEBUG_RPESTS_SHIFT #define GMAC_MAC_DEBUG_RPESTS_WIDTH EMAC_MAC_DEBUG_RPESTS_WIDTH #define GMAC_MAC_DEBUG_RPESTS(x) EMAC_MAC_DEBUG_RPESTS(x) #define GMAC_MAC_DEBUG_RFCFCSTS_MASK EMAC_MAC_DEBUG_RFCFCSTS_MASK #define GMAC_MAC_DEBUG_RFCFCSTS_SHIFT EMAC_MAC_DEBUG_RFCFCSTS_SHIFT #define GMAC_MAC_DEBUG_RFCFCSTS_WIDTH EMAC_MAC_DEBUG_RFCFCSTS_WIDTH #define GMAC_MAC_DEBUG_RFCFCSTS(x) EMAC_MAC_DEBUG_RFCFCSTS(x) #define GMAC_MAC_DEBUG_TPESTS_MASK EMAC_MAC_DEBUG_TPESTS_MASK #define GMAC_MAC_DEBUG_TPESTS_SHIFT EMAC_MAC_DEBUG_TPESTS_SHIFT #define GMAC_MAC_DEBUG_TPESTS_WIDTH EMAC_MAC_DEBUG_TPESTS_WIDTH #define GMAC_MAC_DEBUG_TPESTS(x) EMAC_MAC_DEBUG_TPESTS(x) #define GMAC_MAC_DEBUG_TFCSTS_MASK EMAC_MAC_DEBUG_TFCSTS_MASK #define GMAC_MAC_DEBUG_TFCSTS_SHIFT EMAC_MAC_DEBUG_TFCSTS_SHIFT #define GMAC_MAC_DEBUG_TFCSTS_WIDTH EMAC_MAC_DEBUG_TFCSTS_WIDTH #define GMAC_MAC_DEBUG_TFCSTS(x) EMAC_MAC_DEBUG_TFCSTS(x) /*! @} */ /*! @name MAC_HW_FEATURE0 - */ /*! @{ */ #define GMAC_MAC_HW_FEATURE0_MIISEL_MASK EMAC_MAC_HW_FEATURE0_MIISEL_MASK #define GMAC_MAC_HW_FEATURE0_MIISEL_SHIFT EMAC_MAC_HW_FEATURE0_MIISEL_SHIFT #define GMAC_MAC_HW_FEATURE0_MIISEL_WIDTH EMAC_MAC_HW_FEATURE0_MIISEL_WIDTH #define GMAC_MAC_HW_FEATURE0_MIISEL(x) EMAC_MAC_HW_FEATURE0_MIISEL(x) #define GMAC_MAC_HW_FEATURE0_GMIISEL_MASK EMAC_MAC_HW_FEATURE0_GMIISEL_MASK #define GMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT EMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT #define GMAC_MAC_HW_FEATURE0_GMIISEL_WIDTH EMAC_MAC_HW_FEATURE0_GMIISEL_WIDTH #define GMAC_MAC_HW_FEATURE0_GMIISEL(x) EMAC_MAC_HW_FEATURE0_GMIISEL(x) #define GMAC_MAC_HW_FEATURE0_HDSEL_MASK EMAC_MAC_HW_FEATURE0_HDSEL_MASK #define GMAC_MAC_HW_FEATURE0_HDSEL_SHIFT EMAC_MAC_HW_FEATURE0_HDSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_HDSEL_WIDTH EMAC_MAC_HW_FEATURE0_HDSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_HDSEL(x) EMAC_MAC_HW_FEATURE0_HDSEL(x) #define GMAC_MAC_HW_FEATURE0_PCSSEL_MASK EMAC_MAC_HW_FEATURE0_PCSSEL_MASK #define GMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT EMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_PCSSEL_WIDTH EMAC_MAC_HW_FEATURE0_PCSSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_PCSSEL(x) EMAC_MAC_HW_FEATURE0_PCSSEL(x) #define GMAC_MAC_HW_FEATURE0_VLHASH_MASK EMAC_MAC_HW_FEATURE0_VLHASH_MASK #define GMAC_MAC_HW_FEATURE0_VLHASH_SHIFT EMAC_MAC_HW_FEATURE0_VLHASH_SHIFT #define GMAC_MAC_HW_FEATURE0_VLHASH_WIDTH EMAC_MAC_HW_FEATURE0_VLHASH_WIDTH #define GMAC_MAC_HW_FEATURE0_VLHASH(x) EMAC_MAC_HW_FEATURE0_VLHASH(x) #define GMAC_MAC_HW_FEATURE0_SMASEL_MASK EMAC_MAC_HW_FEATURE0_SMASEL_MASK #define GMAC_MAC_HW_FEATURE0_SMASEL_SHIFT EMAC_MAC_HW_FEATURE0_SMASEL_SHIFT #define GMAC_MAC_HW_FEATURE0_SMASEL_WIDTH EMAC_MAC_HW_FEATURE0_SMASEL_WIDTH #define GMAC_MAC_HW_FEATURE0_SMASEL(x) EMAC_MAC_HW_FEATURE0_SMASEL(x) #define GMAC_MAC_HW_FEATURE0_RWKSEL_MASK EMAC_MAC_HW_FEATURE0_RWKSEL_MASK #define GMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT EMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_RWKSEL_WIDTH EMAC_MAC_HW_FEATURE0_RWKSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_RWKSEL(x) EMAC_MAC_HW_FEATURE0_RWKSEL(x) #define GMAC_MAC_HW_FEATURE0_MGKSEL_MASK EMAC_MAC_HW_FEATURE0_MGKSEL_MASK #define GMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT EMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_MGKSEL_WIDTH EMAC_MAC_HW_FEATURE0_MGKSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_MGKSEL(x) EMAC_MAC_HW_FEATURE0_MGKSEL(x) #define GMAC_MAC_HW_FEATURE0_MMCSEL_MASK EMAC_MAC_HW_FEATURE0_MMCSEL_MASK #define GMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT EMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_MMCSEL_WIDTH EMAC_MAC_HW_FEATURE0_MMCSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_MMCSEL(x) EMAC_MAC_HW_FEATURE0_MMCSEL(x) #define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK EMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK #define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT EMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_WIDTH EMAC_MAC_HW_FEATURE0_ARPOFFSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_ARPOFFSEL(x) EMAC_MAC_HW_FEATURE0_ARPOFFSEL(x) #define GMAC_MAC_HW_FEATURE0_TSSEL_MASK EMAC_MAC_HW_FEATURE0_TSSEL_MASK #define GMAC_MAC_HW_FEATURE0_TSSEL_SHIFT EMAC_MAC_HW_FEATURE0_TSSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_TSSEL_WIDTH EMAC_MAC_HW_FEATURE0_TSSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_TSSEL(x) EMAC_MAC_HW_FEATURE0_TSSEL(x) #define GMAC_MAC_HW_FEATURE0_EEESEL_MASK EMAC_MAC_HW_FEATURE0_EEESEL_MASK #define GMAC_MAC_HW_FEATURE0_EEESEL_SHIFT EMAC_MAC_HW_FEATURE0_EEESEL_SHIFT #define GMAC_MAC_HW_FEATURE0_EEESEL_WIDTH EMAC_MAC_HW_FEATURE0_EEESEL_WIDTH #define GMAC_MAC_HW_FEATURE0_EEESEL(x) EMAC_MAC_HW_FEATURE0_EEESEL(x) #define GMAC_MAC_HW_FEATURE0_TXCOESEL_MASK EMAC_MAC_HW_FEATURE0_TXCOESEL_MASK #define GMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT EMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT #define GMAC_MAC_HW_FEATURE0_TXCOESEL_WIDTH EMAC_MAC_HW_FEATURE0_TXCOESEL_WIDTH #define GMAC_MAC_HW_FEATURE0_TXCOESEL(x) EMAC_MAC_HW_FEATURE0_TXCOESEL(x) #define GMAC_MAC_HW_FEATURE0_RXCOESEL_MASK EMAC_MAC_HW_FEATURE0_RXCOESEL_MASK #define GMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT EMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT #define GMAC_MAC_HW_FEATURE0_RXCOESEL_WIDTH EMAC_MAC_HW_FEATURE0_RXCOESEL_WIDTH #define GMAC_MAC_HW_FEATURE0_RXCOESEL(x) EMAC_MAC_HW_FEATURE0_RXCOESEL(x) #define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK #define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_WIDTH EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL(x) EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(x) #define GMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK EMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK #define GMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT EMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT #define GMAC_MAC_HW_FEATURE0_MACADR32SEL_WIDTH EMAC_MAC_HW_FEATURE0_MACADR32SEL_WIDTH #define GMAC_MAC_HW_FEATURE0_MACADR32SEL(x) EMAC_MAC_HW_FEATURE0_MACADR32SEL(x) #define GMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK EMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK #define GMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT EMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT #define GMAC_MAC_HW_FEATURE0_MACADR64SEL_WIDTH EMAC_MAC_HW_FEATURE0_MACADR64SEL_WIDTH #define GMAC_MAC_HW_FEATURE0_MACADR64SEL(x) EMAC_MAC_HW_FEATURE0_MACADR64SEL(x) #define GMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK #define GMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_TSSTSSEL_WIDTH EMAC_MAC_HW_FEATURE0_TSSTSSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_TSSTSSEL(x) EMAC_MAC_HW_FEATURE0_TSSTSSEL(x) #define GMAC_MAC_HW_FEATURE0_SAVLANINS_MASK EMAC_MAC_HW_FEATURE0_SAVLANINS_MASK #define GMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT EMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT #define GMAC_MAC_HW_FEATURE0_SAVLANINS_WIDTH EMAC_MAC_HW_FEATURE0_SAVLANINS_WIDTH #define GMAC_MAC_HW_FEATURE0_SAVLANINS(x) EMAC_MAC_HW_FEATURE0_SAVLANINS(x) #define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK #define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT #define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_WIDTH EMAC_MAC_HW_FEATURE0_ACTPHYSEL_WIDTH #define GMAC_MAC_HW_FEATURE0_ACTPHYSEL(x) EMAC_MAC_HW_FEATURE0_ACTPHYSEL(x) /*! @} */ /*! @name MAC_HW_FEATURE1 - */ /*! @{ */ #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_WIDTH EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_WIDTH #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) #define GMAC_MAC_HW_FEATURE1_SPRAM_MASK EMAC_MAC_HW_FEATURE1_SPRAM_MASK #define GMAC_MAC_HW_FEATURE1_SPRAM_SHIFT EMAC_MAC_HW_FEATURE1_SPRAM_SHIFT #define GMAC_MAC_HW_FEATURE1_SPRAM_WIDTH EMAC_MAC_HW_FEATURE1_SPRAM_WIDTH #define GMAC_MAC_HW_FEATURE1_SPRAM(x) EMAC_MAC_HW_FEATURE1_SPRAM(x) #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_WIDTH EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_WIDTH #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) #define GMAC_MAC_HW_FEATURE1_OSTEN_MASK EMAC_MAC_HW_FEATURE1_OSTEN_MASK #define GMAC_MAC_HW_FEATURE1_OSTEN_SHIFT EMAC_MAC_HW_FEATURE1_OSTEN_SHIFT #define GMAC_MAC_HW_FEATURE1_OSTEN_WIDTH EMAC_MAC_HW_FEATURE1_OSTEN_WIDTH #define GMAC_MAC_HW_FEATURE1_OSTEN(x) EMAC_MAC_HW_FEATURE1_OSTEN(x) #define GMAC_MAC_HW_FEATURE1_PTOEN_MASK EMAC_MAC_HW_FEATURE1_PTOEN_MASK #define GMAC_MAC_HW_FEATURE1_PTOEN_SHIFT EMAC_MAC_HW_FEATURE1_PTOEN_SHIFT #define GMAC_MAC_HW_FEATURE1_PTOEN_WIDTH EMAC_MAC_HW_FEATURE1_PTOEN_WIDTH #define GMAC_MAC_HW_FEATURE1_PTOEN(x) EMAC_MAC_HW_FEATURE1_PTOEN(x) #define GMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK EMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK #define GMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT EMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT #define GMAC_MAC_HW_FEATURE1_ADVTHWORD_WIDTH EMAC_MAC_HW_FEATURE1_ADVTHWORD_WIDTH #define GMAC_MAC_HW_FEATURE1_ADVTHWORD(x) EMAC_MAC_HW_FEATURE1_ADVTHWORD(x) #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK EMAC_MAC_HW_FEATURE1_ADDR64_MASK #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT #define GMAC_MAC_HW_FEATURE1_ADDR64_WIDTH EMAC_MAC_HW_FEATURE1_ADDR64_WIDTH #define GMAC_MAC_HW_FEATURE1_ADDR64(x) EMAC_MAC_HW_FEATURE1_ADDR64(x) #define GMAC_MAC_HW_FEATURE1_DCBEN_MASK EMAC_MAC_HW_FEATURE1_DCBEN_MASK #define GMAC_MAC_HW_FEATURE1_DCBEN_SHIFT EMAC_MAC_HW_FEATURE1_DCBEN_SHIFT #define GMAC_MAC_HW_FEATURE1_DCBEN_WIDTH EMAC_MAC_HW_FEATURE1_DCBEN_WIDTH #define GMAC_MAC_HW_FEATURE1_DCBEN(x) EMAC_MAC_HW_FEATURE1_DCBEN(x) #define GMAC_MAC_HW_FEATURE1_SPHEN_MASK EMAC_MAC_HW_FEATURE1_SPHEN_MASK #define GMAC_MAC_HW_FEATURE1_SPHEN_SHIFT EMAC_MAC_HW_FEATURE1_SPHEN_SHIFT #define GMAC_MAC_HW_FEATURE1_SPHEN_WIDTH EMAC_MAC_HW_FEATURE1_SPHEN_WIDTH #define GMAC_MAC_HW_FEATURE1_SPHEN(x) EMAC_MAC_HW_FEATURE1_SPHEN(x) #define GMAC_MAC_HW_FEATURE1_TSOEN_MASK EMAC_MAC_HW_FEATURE1_TSOEN_MASK #define GMAC_MAC_HW_FEATURE1_TSOEN_SHIFT EMAC_MAC_HW_FEATURE1_TSOEN_SHIFT #define GMAC_MAC_HW_FEATURE1_TSOEN_WIDTH EMAC_MAC_HW_FEATURE1_TSOEN_WIDTH #define GMAC_MAC_HW_FEATURE1_TSOEN(x) EMAC_MAC_HW_FEATURE1_TSOEN(x) #define GMAC_MAC_HW_FEATURE1_DBGMEMA_MASK EMAC_MAC_HW_FEATURE1_DBGMEMA_MASK #define GMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT EMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT #define GMAC_MAC_HW_FEATURE1_DBGMEMA_WIDTH EMAC_MAC_HW_FEATURE1_DBGMEMA_WIDTH #define GMAC_MAC_HW_FEATURE1_DBGMEMA(x) EMAC_MAC_HW_FEATURE1_DBGMEMA(x) #define GMAC_MAC_HW_FEATURE1_AVSEL_MASK EMAC_MAC_HW_FEATURE1_AVSEL_MASK #define GMAC_MAC_HW_FEATURE1_AVSEL_SHIFT EMAC_MAC_HW_FEATURE1_AVSEL_SHIFT #define GMAC_MAC_HW_FEATURE1_AVSEL_WIDTH EMAC_MAC_HW_FEATURE1_AVSEL_WIDTH #define GMAC_MAC_HW_FEATURE1_AVSEL(x) EMAC_MAC_HW_FEATURE1_AVSEL(x) #define GMAC_MAC_HW_FEATURE1_RAVSEL_MASK EMAC_MAC_HW_FEATURE1_RAVSEL_MASK #define GMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT EMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT #define GMAC_MAC_HW_FEATURE1_RAVSEL_WIDTH EMAC_MAC_HW_FEATURE1_RAVSEL_WIDTH #define GMAC_MAC_HW_FEATURE1_RAVSEL(x) EMAC_MAC_HW_FEATURE1_RAVSEL(x) #define GMAC_MAC_HW_FEATURE1_POUOST_MASK EMAC_MAC_HW_FEATURE1_POUOST_MASK #define GMAC_MAC_HW_FEATURE1_POUOST_SHIFT EMAC_MAC_HW_FEATURE1_POUOST_SHIFT #define GMAC_MAC_HW_FEATURE1_POUOST_WIDTH EMAC_MAC_HW_FEATURE1_POUOST_WIDTH #define GMAC_MAC_HW_FEATURE1_POUOST(x) EMAC_MAC_HW_FEATURE1_POUOST(x) #define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK #define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT #define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_WIDTH EMAC_MAC_HW_FEATURE1_HASHTBLSZ_WIDTH #define GMAC_MAC_HW_FEATURE1_HASHTBLSZ(x) EMAC_MAC_HW_FEATURE1_HASHTBLSZ(x) #define GMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK #define GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT #define GMAC_MAC_HW_FEATURE1_L3L4FNUM_WIDTH EMAC_MAC_HW_FEATURE1_L3L4FNUM_WIDTH #define GMAC_MAC_HW_FEATURE1_L3L4FNUM(x) EMAC_MAC_HW_FEATURE1_L3L4FNUM(x) /*! @} */ /*! @name MAC_HW_FEATURE2 - */ /*! @{ */ #define GMAC_MAC_HW_FEATURE2_RXQCNT_MASK EMAC_MAC_HW_FEATURE2_RXQCNT_MASK #define GMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT #define GMAC_MAC_HW_FEATURE2_RXQCNT_WIDTH EMAC_MAC_HW_FEATURE2_RXQCNT_WIDTH #define GMAC_MAC_HW_FEATURE2_RXQCNT(x) EMAC_MAC_HW_FEATURE2_RXQCNT(x) #define GMAC_MAC_HW_FEATURE2_TXQCNT_MASK EMAC_MAC_HW_FEATURE2_TXQCNT_MASK #define GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT #define GMAC_MAC_HW_FEATURE2_TXQCNT_WIDTH EMAC_MAC_HW_FEATURE2_TXQCNT_WIDTH #define GMAC_MAC_HW_FEATURE2_TXQCNT(x) EMAC_MAC_HW_FEATURE2_TXQCNT(x) #define GMAC_MAC_HW_FEATURE2_RXCHCNT_MASK EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK #define GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT #define GMAC_MAC_HW_FEATURE2_RXCHCNT_WIDTH EMAC_MAC_HW_FEATURE2_RXCHCNT_WIDTH #define GMAC_MAC_HW_FEATURE2_RXCHCNT(x) EMAC_MAC_HW_FEATURE2_RXCHCNT(x) #define GMAC_MAC_HW_FEATURE2_TXCHCNT_MASK EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK #define GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT #define GMAC_MAC_HW_FEATURE2_TXCHCNT_WIDTH EMAC_MAC_HW_FEATURE2_TXCHCNT_WIDTH #define GMAC_MAC_HW_FEATURE2_TXCHCNT(x) EMAC_MAC_HW_FEATURE2_TXCHCNT(x) #define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK #define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT #define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_WIDTH EMAC_MAC_HW_FEATURE2_PPSOUTNUM_WIDTH #define GMAC_MAC_HW_FEATURE2_PPSOUTNUM(x) EMAC_MAC_HW_FEATURE2_PPSOUTNUM(x) #define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK #define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT #define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_WIDTH EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_WIDTH #define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM(x) EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(x) /*! @} */ /*! @name MAC_HW_FEATURE3 - */ /*! @{ */ #define GMAC_MAC_HW_FEATURE3_NRVF_MASK EMAC_MAC_HW_FEATURE3_NRVF_MASK #define GMAC_MAC_HW_FEATURE3_NRVF_SHIFT EMAC_MAC_HW_FEATURE3_NRVF_SHIFT #define GMAC_MAC_HW_FEATURE3_NRVF_WIDTH EMAC_MAC_HW_FEATURE3_NRVF_WIDTH #define GMAC_MAC_HW_FEATURE3_NRVF(x) EMAC_MAC_HW_FEATURE3_NRVF(x) #define GMAC_MAC_HW_FEATURE3_CBTISEL_MASK EMAC_MAC_HW_FEATURE3_CBTISEL_MASK #define GMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT EMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT #define GMAC_MAC_HW_FEATURE3_CBTISEL_WIDTH EMAC_MAC_HW_FEATURE3_CBTISEL_WIDTH #define GMAC_MAC_HW_FEATURE3_CBTISEL(x) EMAC_MAC_HW_FEATURE3_CBTISEL(x) #define GMAC_MAC_HW_FEATURE3_DVLAN_MASK EMAC_MAC_HW_FEATURE3_DVLAN_MASK #define GMAC_MAC_HW_FEATURE3_DVLAN_SHIFT EMAC_MAC_HW_FEATURE3_DVLAN_SHIFT #define GMAC_MAC_HW_FEATURE3_DVLAN_WIDTH EMAC_MAC_HW_FEATURE3_DVLAN_WIDTH #define GMAC_MAC_HW_FEATURE3_DVLAN(x) EMAC_MAC_HW_FEATURE3_DVLAN(x) #define GMAC_MAC_HW_FEATURE3_PDUPSEL_MASK EMAC_MAC_HW_FEATURE3_PDUPSEL_MASK #define GMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT EMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT #define GMAC_MAC_HW_FEATURE3_PDUPSEL_WIDTH EMAC_MAC_HW_FEATURE3_PDUPSEL_WIDTH #define GMAC_MAC_HW_FEATURE3_PDUPSEL(x) EMAC_MAC_HW_FEATURE3_PDUPSEL(x) #define GMAC_MAC_HW_FEATURE3_FRPSEL_MASK EMAC_MAC_HW_FEATURE3_FRPSEL_MASK #define GMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT EMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT #define GMAC_MAC_HW_FEATURE3_FRPSEL_WIDTH EMAC_MAC_HW_FEATURE3_FRPSEL_WIDTH #define GMAC_MAC_HW_FEATURE3_FRPSEL(x) EMAC_MAC_HW_FEATURE3_FRPSEL(x) #define GMAC_MAC_HW_FEATURE3_FRPBS_MASK EMAC_MAC_HW_FEATURE3_FRPBS_MASK #define GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT #define GMAC_MAC_HW_FEATURE3_FRPBS_WIDTH EMAC_MAC_HW_FEATURE3_FRPBS_WIDTH #define GMAC_MAC_HW_FEATURE3_FRPBS(x) EMAC_MAC_HW_FEATURE3_FRPBS(x) #define GMAC_MAC_HW_FEATURE3_FRPES_MASK EMAC_MAC_HW_FEATURE3_FRPES_MASK #define GMAC_MAC_HW_FEATURE3_FRPES_SHIFT EMAC_MAC_HW_FEATURE3_FRPES_SHIFT #define GMAC_MAC_HW_FEATURE3_FRPES_WIDTH EMAC_MAC_HW_FEATURE3_FRPES_WIDTH #define GMAC_MAC_HW_FEATURE3_FRPES(x) EMAC_MAC_HW_FEATURE3_FRPES(x) #define GMAC_MAC_HW_FEATURE3_ESTSEL_MASK EMAC_MAC_HW_FEATURE3_ESTSEL_MASK #define GMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT EMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT #define GMAC_MAC_HW_FEATURE3_ESTSEL_WIDTH EMAC_MAC_HW_FEATURE3_ESTSEL_WIDTH #define GMAC_MAC_HW_FEATURE3_ESTSEL(x) EMAC_MAC_HW_FEATURE3_ESTSEL(x) #define GMAC_MAC_HW_FEATURE3_ESTDEP_MASK EMAC_MAC_HW_FEATURE3_ESTDEP_MASK #define GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT #define GMAC_MAC_HW_FEATURE3_ESTDEP_WIDTH EMAC_MAC_HW_FEATURE3_ESTDEP_WIDTH #define GMAC_MAC_HW_FEATURE3_ESTDEP(x) EMAC_MAC_HW_FEATURE3_ESTDEP(x) #define GMAC_MAC_HW_FEATURE3_ESTWID_MASK EMAC_MAC_HW_FEATURE3_ESTWID_MASK #define GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT #define GMAC_MAC_HW_FEATURE3_ESTWID_WIDTH EMAC_MAC_HW_FEATURE3_ESTWID_WIDTH #define GMAC_MAC_HW_FEATURE3_ESTWID(x) EMAC_MAC_HW_FEATURE3_ESTWID(x) #define GMAC_MAC_HW_FEATURE3_FPESEL_MASK EMAC_MAC_HW_FEATURE3_FPESEL_MASK #define GMAC_MAC_HW_FEATURE3_FPESEL_SHIFT EMAC_MAC_HW_FEATURE3_FPESEL_SHIFT #define GMAC_MAC_HW_FEATURE3_FPESEL_WIDTH EMAC_MAC_HW_FEATURE3_FPESEL_WIDTH #define GMAC_MAC_HW_FEATURE3_FPESEL(x) EMAC_MAC_HW_FEATURE3_FPESEL(x) #define GMAC_MAC_HW_FEATURE3_TBSSEL_MASK EMAC_MAC_HW_FEATURE3_TBSSEL_MASK #define GMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT EMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT #define GMAC_MAC_HW_FEATURE3_TBSSEL_WIDTH EMAC_MAC_HW_FEATURE3_TBSSEL_WIDTH #define GMAC_MAC_HW_FEATURE3_TBSSEL(x) EMAC_MAC_HW_FEATURE3_TBSSEL(x) #define GMAC_MAC_HW_FEATURE3_ASP_MASK EMAC_MAC_HW_FEATURE3_ASP_MASK #define GMAC_MAC_HW_FEATURE3_ASP_SHIFT EMAC_MAC_HW_FEATURE3_ASP_SHIFT #define GMAC_MAC_HW_FEATURE3_ASP_WIDTH EMAC_MAC_HW_FEATURE3_ASP_WIDTH #define GMAC_MAC_HW_FEATURE3_ASP(x) EMAC_MAC_HW_FEATURE3_ASP(x) /*! @} */ /*! @name MAC_DPP_FSM_INTERRUPT_STATUS - */ /*! @{ */ #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES(x) #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_MASK #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_SHIFT #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_WIDTH #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES(x) /*! @} */ /*! @name MAC_FSM_CONTROL - */ /*! @{ */ #define GMAC_MAC_FSM_CONTROL_TMOUTEN_MASK EMAC_MAC_FSM_CONTROL_TMOUTEN_MASK #define GMAC_MAC_FSM_CONTROL_TMOUTEN_SHIFT EMAC_MAC_FSM_CONTROL_TMOUTEN_SHIFT #define GMAC_MAC_FSM_CONTROL_TMOUTEN_WIDTH EMAC_MAC_FSM_CONTROL_TMOUTEN_WIDTH #define GMAC_MAC_FSM_CONTROL_TMOUTEN(x) EMAC_MAC_FSM_CONTROL_TMOUTEN(x) #define GMAC_MAC_FSM_CONTROL_PRTYEN_MASK EMAC_MAC_FSM_CONTROL_PRTYEN_MASK #define GMAC_MAC_FSM_CONTROL_PRTYEN_SHIFT EMAC_MAC_FSM_CONTROL_PRTYEN_SHIFT #define GMAC_MAC_FSM_CONTROL_PRTYEN_WIDTH EMAC_MAC_FSM_CONTROL_PRTYEN_WIDTH #define GMAC_MAC_FSM_CONTROL_PRTYEN(x) EMAC_MAC_FSM_CONTROL_PRTYEN(x) #define GMAC_MAC_FSM_CONTROL_TTEIN_MASK EMAC_MAC_FSM_CONTROL_TTEIN_MASK #define GMAC_MAC_FSM_CONTROL_TTEIN_SHIFT EMAC_MAC_FSM_CONTROL_TTEIN_SHIFT #define GMAC_MAC_FSM_CONTROL_TTEIN_WIDTH EMAC_MAC_FSM_CONTROL_TTEIN_WIDTH #define GMAC_MAC_FSM_CONTROL_TTEIN(x) EMAC_MAC_FSM_CONTROL_TTEIN(x) #define GMAC_MAC_FSM_CONTROL_RTEIN_MASK EMAC_MAC_FSM_CONTROL_RTEIN_MASK #define GMAC_MAC_FSM_CONTROL_RTEIN_SHIFT EMAC_MAC_FSM_CONTROL_RTEIN_SHIFT #define GMAC_MAC_FSM_CONTROL_RTEIN_WIDTH EMAC_MAC_FSM_CONTROL_RTEIN_WIDTH #define GMAC_MAC_FSM_CONTROL_RTEIN(x) EMAC_MAC_FSM_CONTROL_RTEIN(x) #define GMAC_MAC_FSM_CONTROL_ATEIN_MASK EMAC_MAC_FSM_CONTROL_ATEIN_MASK #define GMAC_MAC_FSM_CONTROL_ATEIN_SHIFT EMAC_MAC_FSM_CONTROL_ATEIN_SHIFT #define GMAC_MAC_FSM_CONTROL_ATEIN_WIDTH EMAC_MAC_FSM_CONTROL_ATEIN_WIDTH #define GMAC_MAC_FSM_CONTROL_ATEIN(x) EMAC_MAC_FSM_CONTROL_ATEIN(x) #define GMAC_MAC_FSM_CONTROL_PTEIN_MASK EMAC_MAC_FSM_CONTROL_PTEIN_MASK #define GMAC_MAC_FSM_CONTROL_PTEIN_SHIFT EMAC_MAC_FSM_CONTROL_PTEIN_SHIFT #define GMAC_MAC_FSM_CONTROL_PTEIN_WIDTH EMAC_MAC_FSM_CONTROL_PTEIN_WIDTH #define GMAC_MAC_FSM_CONTROL_PTEIN(x) EMAC_MAC_FSM_CONTROL_PTEIN(x) #define GMAC_MAC_FSM_CONTROL_TPEIN_MASK EMAC_MAC_FSM_CONTROL_TPEIN_MASK #define GMAC_MAC_FSM_CONTROL_TPEIN_SHIFT EMAC_MAC_FSM_CONTROL_TPEIN_SHIFT #define GMAC_MAC_FSM_CONTROL_TPEIN_WIDTH EMAC_MAC_FSM_CONTROL_TPEIN_WIDTH #define GMAC_MAC_FSM_CONTROL_TPEIN(x) EMAC_MAC_FSM_CONTROL_TPEIN(x) #define GMAC_MAC_FSM_CONTROL_RPEIN_MASK EMAC_MAC_FSM_CONTROL_RPEIN_MASK #define GMAC_MAC_FSM_CONTROL_RPEIN_SHIFT EMAC_MAC_FSM_CONTROL_RPEIN_SHIFT #define GMAC_MAC_FSM_CONTROL_RPEIN_WIDTH EMAC_MAC_FSM_CONTROL_RPEIN_WIDTH #define GMAC_MAC_FSM_CONTROL_RPEIN(x) EMAC_MAC_FSM_CONTROL_RPEIN(x) #define GMAC_MAC_FSM_CONTROL_APEIN_MASK EMAC_MAC_FSM_CONTROL_APEIN_MASK #define GMAC_MAC_FSM_CONTROL_APEIN_SHIFT EMAC_MAC_FSM_CONTROL_APEIN_SHIFT #define GMAC_MAC_FSM_CONTROL_APEIN_WIDTH EMAC_MAC_FSM_CONTROL_APEIN_WIDTH #define GMAC_MAC_FSM_CONTROL_APEIN(x) EMAC_MAC_FSM_CONTROL_APEIN(x) #define GMAC_MAC_FSM_CONTROL_PPEIN_MASK EMAC_MAC_FSM_CONTROL_PPEIN_MASK #define GMAC_MAC_FSM_CONTROL_PPEIN_SHIFT EMAC_MAC_FSM_CONTROL_PPEIN_SHIFT #define GMAC_MAC_FSM_CONTROL_PPEIN_WIDTH EMAC_MAC_FSM_CONTROL_PPEIN_WIDTH #define GMAC_MAC_FSM_CONTROL_PPEIN(x) EMAC_MAC_FSM_CONTROL_PPEIN(x) #define GMAC_MAC_FSM_CONTROL_TLGRNML_MASK EMAC_MAC_FSM_CONTROL_TLGRNML_MASK #define GMAC_MAC_FSM_CONTROL_TLGRNML_SHIFT EMAC_MAC_FSM_CONTROL_TLGRNML_SHIFT #define GMAC_MAC_FSM_CONTROL_TLGRNML_WIDTH EMAC_MAC_FSM_CONTROL_TLGRNML_WIDTH #define GMAC_MAC_FSM_CONTROL_TLGRNML(x) EMAC_MAC_FSM_CONTROL_TLGRNML(x) #define GMAC_MAC_FSM_CONTROL_RLGRNML_MASK EMAC_MAC_FSM_CONTROL_RLGRNML_MASK #define GMAC_MAC_FSM_CONTROL_RLGRNML_SHIFT EMAC_MAC_FSM_CONTROL_RLGRNML_SHIFT #define GMAC_MAC_FSM_CONTROL_RLGRNML_WIDTH EMAC_MAC_FSM_CONTROL_RLGRNML_WIDTH #define GMAC_MAC_FSM_CONTROL_RLGRNML(x) EMAC_MAC_FSM_CONTROL_RLGRNML(x) #define GMAC_MAC_FSM_CONTROL_ALGRNML_MASK EMAC_MAC_FSM_CONTROL_ALGRNML_MASK #define GMAC_MAC_FSM_CONTROL_ALGRNML_SHIFT EMAC_MAC_FSM_CONTROL_ALGRNML_SHIFT #define GMAC_MAC_FSM_CONTROL_ALGRNML_WIDTH EMAC_MAC_FSM_CONTROL_ALGRNML_WIDTH #define GMAC_MAC_FSM_CONTROL_ALGRNML(x) EMAC_MAC_FSM_CONTROL_ALGRNML(x) #define GMAC_MAC_FSM_CONTROL_PLGRNML_MASK EMAC_MAC_FSM_CONTROL_PLGRNML_MASK #define GMAC_MAC_FSM_CONTROL_PLGRNML_SHIFT EMAC_MAC_FSM_CONTROL_PLGRNML_SHIFT #define GMAC_MAC_FSM_CONTROL_PLGRNML_WIDTH EMAC_MAC_FSM_CONTROL_PLGRNML_WIDTH #define GMAC_MAC_FSM_CONTROL_PLGRNML(x) EMAC_MAC_FSM_CONTROL_PLGRNML(x) /*! @} */ /*! @name MAC_FSM_ACT_TIMER - */ /*! @{ */ #define GMAC_MAC_FSM_ACT_TIMER_TMR_MASK EMAC_MAC_FSM_ACT_TIMER_TMR_MASK #define GMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT #define GMAC_MAC_FSM_ACT_TIMER_TMR_WIDTH EMAC_MAC_FSM_ACT_TIMER_TMR_WIDTH #define GMAC_MAC_FSM_ACT_TIMER_TMR(x) EMAC_MAC_FSM_ACT_TIMER_TMR(x) #define GMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK #define GMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT #define GMAC_MAC_FSM_ACT_TIMER_NTMRMD_WIDTH EMAC_MAC_FSM_ACT_TIMER_NTMRMD_WIDTH #define GMAC_MAC_FSM_ACT_TIMER_NTMRMD(x) EMAC_MAC_FSM_ACT_TIMER_NTMRMD(x) #define GMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK #define GMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT #define GMAC_MAC_FSM_ACT_TIMER_LTMRMD_WIDTH EMAC_MAC_FSM_ACT_TIMER_LTMRMD_WIDTH #define GMAC_MAC_FSM_ACT_TIMER_LTMRMD(x) EMAC_MAC_FSM_ACT_TIMER_LTMRMD(x) /*! @} */ /*! @name SCS_REG1 - */ /*! @{ */ #define GMAC_SCS_REG1_MAC_SCS1_MASK EMAC_SCS_REG1_MAC_SCS1_MASK #define GMAC_SCS_REG1_MAC_SCS1_SHIFT EMAC_SCS_REG1_MAC_SCS1_SHIFT #define GMAC_SCS_REG1_MAC_SCS1_WIDTH EMAC_SCS_REG1_MAC_SCS1_WIDTH #define GMAC_SCS_REG1_MAC_SCS1(x) EMAC_SCS_REG1_MAC_SCS1(x) /*! @} */ /*! @name MAC_MDIO_ADDRESS - */ /*! @{ */ #define GMAC_MAC_MDIO_ADDRESS_GB_MASK EMAC_MAC_MDIO_ADDRESS_GB_MASK #define GMAC_MAC_MDIO_ADDRESS_GB_SHIFT EMAC_MAC_MDIO_ADDRESS_GB_SHIFT #define GMAC_MAC_MDIO_ADDRESS_GB_WIDTH EMAC_MAC_MDIO_ADDRESS_GB_WIDTH #define GMAC_MAC_MDIO_ADDRESS_GB(x) EMAC_MAC_MDIO_ADDRESS_GB(x) #define GMAC_MAC_MDIO_ADDRESS_C45E_MASK EMAC_MAC_MDIO_ADDRESS_C45E_MASK #define GMAC_MAC_MDIO_ADDRESS_C45E_SHIFT EMAC_MAC_MDIO_ADDRESS_C45E_SHIFT #define GMAC_MAC_MDIO_ADDRESS_C45E_WIDTH EMAC_MAC_MDIO_ADDRESS_C45E_WIDTH #define GMAC_MAC_MDIO_ADDRESS_C45E(x) EMAC_MAC_MDIO_ADDRESS_C45E(x) #define GMAC_MAC_MDIO_ADDRESS_GOC_0_MASK EMAC_MAC_MDIO_ADDRESS_GOC_0_MASK #define GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT EMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT #define GMAC_MAC_MDIO_ADDRESS_GOC_0_WIDTH EMAC_MAC_MDIO_ADDRESS_GOC_0_WIDTH #define GMAC_MAC_MDIO_ADDRESS_GOC_0(x) EMAC_MAC_MDIO_ADDRESS_GOC_0(x) #define GMAC_MAC_MDIO_ADDRESS_GOC_1_MASK EMAC_MAC_MDIO_ADDRESS_GOC_1_MASK #define GMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT EMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT #define GMAC_MAC_MDIO_ADDRESS_GOC_1_WIDTH EMAC_MAC_MDIO_ADDRESS_GOC_1_WIDTH #define GMAC_MAC_MDIO_ADDRESS_GOC_1(x) EMAC_MAC_MDIO_ADDRESS_GOC_1(x) #define GMAC_MAC_MDIO_ADDRESS_SKAP_MASK EMAC_MAC_MDIO_ADDRESS_SKAP_MASK #define GMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT EMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT #define GMAC_MAC_MDIO_ADDRESS_SKAP_WIDTH EMAC_MAC_MDIO_ADDRESS_SKAP_WIDTH #define GMAC_MAC_MDIO_ADDRESS_SKAP(x) EMAC_MAC_MDIO_ADDRESS_SKAP(x) #define GMAC_MAC_MDIO_ADDRESS_CR_MASK EMAC_MAC_MDIO_ADDRESS_CR_MASK #define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT EMAC_MAC_MDIO_ADDRESS_CR_SHIFT #define GMAC_MAC_MDIO_ADDRESS_CR_WIDTH EMAC_MAC_MDIO_ADDRESS_CR_WIDTH #define GMAC_MAC_MDIO_ADDRESS_CR(x) EMAC_MAC_MDIO_ADDRESS_CR(x) #define GMAC_MAC_MDIO_ADDRESS_NTC_MASK EMAC_MAC_MDIO_ADDRESS_NTC_MASK #define GMAC_MAC_MDIO_ADDRESS_NTC_SHIFT EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT #define GMAC_MAC_MDIO_ADDRESS_NTC_WIDTH EMAC_MAC_MDIO_ADDRESS_NTC_WIDTH #define GMAC_MAC_MDIO_ADDRESS_NTC(x) EMAC_MAC_MDIO_ADDRESS_NTC(x) #define GMAC_MAC_MDIO_ADDRESS_RDA_MASK EMAC_MAC_MDIO_ADDRESS_RDA_MASK #define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT #define GMAC_MAC_MDIO_ADDRESS_RDA_WIDTH EMAC_MAC_MDIO_ADDRESS_RDA_WIDTH #define GMAC_MAC_MDIO_ADDRESS_RDA(x) EMAC_MAC_MDIO_ADDRESS_RDA(x) #define GMAC_MAC_MDIO_ADDRESS_PA_MASK EMAC_MAC_MDIO_ADDRESS_PA_MASK #define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT EMAC_MAC_MDIO_ADDRESS_PA_SHIFT #define GMAC_MAC_MDIO_ADDRESS_PA_WIDTH EMAC_MAC_MDIO_ADDRESS_PA_WIDTH #define GMAC_MAC_MDIO_ADDRESS_PA(x) EMAC_MAC_MDIO_ADDRESS_PA(x) #define GMAC_MAC_MDIO_ADDRESS_BTB_MASK EMAC_MAC_MDIO_ADDRESS_BTB_MASK #define GMAC_MAC_MDIO_ADDRESS_BTB_SHIFT EMAC_MAC_MDIO_ADDRESS_BTB_SHIFT #define GMAC_MAC_MDIO_ADDRESS_BTB_WIDTH EMAC_MAC_MDIO_ADDRESS_BTB_WIDTH #define GMAC_MAC_MDIO_ADDRESS_BTB(x) EMAC_MAC_MDIO_ADDRESS_BTB(x) #define GMAC_MAC_MDIO_ADDRESS_PSE_MASK EMAC_MAC_MDIO_ADDRESS_PSE_MASK #define GMAC_MAC_MDIO_ADDRESS_PSE_SHIFT EMAC_MAC_MDIO_ADDRESS_PSE_SHIFT #define GMAC_MAC_MDIO_ADDRESS_PSE_WIDTH EMAC_MAC_MDIO_ADDRESS_PSE_WIDTH #define GMAC_MAC_MDIO_ADDRESS_PSE(x) EMAC_MAC_MDIO_ADDRESS_PSE(x) /*! @} */ /*! @name MAC_MDIO_DATA - */ /*! @{ */ #define GMAC_MAC_MDIO_DATA_GD_MASK EMAC_MAC_MDIO_DATA_GD_MASK #define GMAC_MAC_MDIO_DATA_GD_SHIFT EMAC_MAC_MDIO_DATA_GD_SHIFT #define GMAC_MAC_MDIO_DATA_GD_WIDTH EMAC_MAC_MDIO_DATA_GD_WIDTH #define GMAC_MAC_MDIO_DATA_GD(x) EMAC_MAC_MDIO_DATA_GD(x) #define GMAC_MAC_MDIO_DATA_RA_MASK EMAC_MAC_MDIO_DATA_RA_MASK #define GMAC_MAC_MDIO_DATA_RA_SHIFT EMAC_MAC_MDIO_DATA_RA_SHIFT #define GMAC_MAC_MDIO_DATA_RA_WIDTH EMAC_MAC_MDIO_DATA_RA_WIDTH #define GMAC_MAC_MDIO_DATA_RA(x) EMAC_MAC_MDIO_DATA_RA(x) /*! @} */ /*! @name MAC_CSR_SW_CTRL - */ /*! @{ */ #define GMAC_MAC_CSR_SW_CTRL_RCWE_MASK EMAC_MAC_CSR_SW_CTRL_RCWE_MASK #define GMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT EMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT #define GMAC_MAC_CSR_SW_CTRL_RCWE_WIDTH EMAC_MAC_CSR_SW_CTRL_RCWE_WIDTH #define GMAC_MAC_CSR_SW_CTRL_RCWE(x) EMAC_MAC_CSR_SW_CTRL_RCWE(x) #define GMAC_MAC_CSR_SW_CTRL_SEEN_MASK EMAC_MAC_CSR_SW_CTRL_SEEN_MASK #define GMAC_MAC_CSR_SW_CTRL_SEEN_SHIFT EMAC_MAC_CSR_SW_CTRL_SEEN_SHIFT #define GMAC_MAC_CSR_SW_CTRL_SEEN_WIDTH EMAC_MAC_CSR_SW_CTRL_SEEN_WIDTH #define GMAC_MAC_CSR_SW_CTRL_SEEN(x) EMAC_MAC_CSR_SW_CTRL_SEEN(x) /*! @} */ /*! @name MAC_FPE_CTRL_STS - */ /*! @{ */ #define GMAC_MAC_FPE_CTRL_STS_EFPE_MASK EMAC_MAC_FPE_CTRL_STS_EFPE_MASK #define GMAC_MAC_FPE_CTRL_STS_EFPE_SHIFT EMAC_MAC_FPE_CTRL_STS_EFPE_SHIFT #define GMAC_MAC_FPE_CTRL_STS_EFPE_WIDTH EMAC_MAC_FPE_CTRL_STS_EFPE_WIDTH #define GMAC_MAC_FPE_CTRL_STS_EFPE(x) EMAC_MAC_FPE_CTRL_STS_EFPE(x) #define GMAC_MAC_FPE_CTRL_STS_SVER_MASK EMAC_MAC_FPE_CTRL_STS_SVER_MASK #define GMAC_MAC_FPE_CTRL_STS_SVER_SHIFT EMAC_MAC_FPE_CTRL_STS_SVER_SHIFT #define GMAC_MAC_FPE_CTRL_STS_SVER_WIDTH EMAC_MAC_FPE_CTRL_STS_SVER_WIDTH #define GMAC_MAC_FPE_CTRL_STS_SVER(x) EMAC_MAC_FPE_CTRL_STS_SVER(x) #define GMAC_MAC_FPE_CTRL_STS_SRSP_MASK EMAC_MAC_FPE_CTRL_STS_SRSP_MASK #define GMAC_MAC_FPE_CTRL_STS_SRSP_SHIFT EMAC_MAC_FPE_CTRL_STS_SRSP_SHIFT #define GMAC_MAC_FPE_CTRL_STS_SRSP_WIDTH EMAC_MAC_FPE_CTRL_STS_SRSP_WIDTH #define GMAC_MAC_FPE_CTRL_STS_SRSP(x) EMAC_MAC_FPE_CTRL_STS_SRSP(x) #define GMAC_MAC_FPE_CTRL_STS_S1_SET_0_MASK EMAC_MAC_FPE_CTRL_STS_S1_SET_0_MASK #define GMAC_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT EMAC_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT #define GMAC_MAC_FPE_CTRL_STS_S1_SET_0_WIDTH EMAC_MAC_FPE_CTRL_STS_S1_SET_0_WIDTH #define GMAC_MAC_FPE_CTRL_STS_S1_SET_0(x) EMAC_MAC_FPE_CTRL_STS_S1_SET_0(x) #define GMAC_MAC_FPE_CTRL_STS_RVER_MASK EMAC_MAC_FPE_CTRL_STS_RVER_MASK #define GMAC_MAC_FPE_CTRL_STS_RVER_SHIFT EMAC_MAC_FPE_CTRL_STS_RVER_SHIFT #define GMAC_MAC_FPE_CTRL_STS_RVER_WIDTH EMAC_MAC_FPE_CTRL_STS_RVER_WIDTH #define GMAC_MAC_FPE_CTRL_STS_RVER(x) EMAC_MAC_FPE_CTRL_STS_RVER(x) #define GMAC_MAC_FPE_CTRL_STS_RRSP_MASK EMAC_MAC_FPE_CTRL_STS_RRSP_MASK #define GMAC_MAC_FPE_CTRL_STS_RRSP_SHIFT EMAC_MAC_FPE_CTRL_STS_RRSP_SHIFT #define GMAC_MAC_FPE_CTRL_STS_RRSP_WIDTH EMAC_MAC_FPE_CTRL_STS_RRSP_WIDTH #define GMAC_MAC_FPE_CTRL_STS_RRSP(x) EMAC_MAC_FPE_CTRL_STS_RRSP(x) #define GMAC_MAC_FPE_CTRL_STS_TVER_MASK EMAC_MAC_FPE_CTRL_STS_TVER_MASK #define GMAC_MAC_FPE_CTRL_STS_TVER_SHIFT EMAC_MAC_FPE_CTRL_STS_TVER_SHIFT #define GMAC_MAC_FPE_CTRL_STS_TVER_WIDTH EMAC_MAC_FPE_CTRL_STS_TVER_WIDTH #define GMAC_MAC_FPE_CTRL_STS_TVER(x) EMAC_MAC_FPE_CTRL_STS_TVER(x) #define GMAC_MAC_FPE_CTRL_STS_TRSP_MASK EMAC_MAC_FPE_CTRL_STS_TRSP_MASK #define GMAC_MAC_FPE_CTRL_STS_TRSP_SHIFT EMAC_MAC_FPE_CTRL_STS_TRSP_SHIFT #define GMAC_MAC_FPE_CTRL_STS_TRSP_WIDTH EMAC_MAC_FPE_CTRL_STS_TRSP_WIDTH #define GMAC_MAC_FPE_CTRL_STS_TRSP(x) EMAC_MAC_FPE_CTRL_STS_TRSP(x) /*! @} */ /*! @name MAC_PRESN_TIME_NS - */ /*! @{ */ #define GMAC_MAC_PRESN_TIME_NS_MPTN_MASK EMAC_MAC_PRESN_TIME_NS_MPTN_MASK #define GMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT #define GMAC_MAC_PRESN_TIME_NS_MPTN_WIDTH EMAC_MAC_PRESN_TIME_NS_MPTN_WIDTH #define GMAC_MAC_PRESN_TIME_NS_MPTN(x) EMAC_MAC_PRESN_TIME_NS_MPTN(x) /*! @} */ /*! @name MAC_PRESN_TIME_UPDT - */ /*! @{ */ #define GMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK #define GMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT #define GMAC_MAC_PRESN_TIME_UPDT_MPTU_WIDTH EMAC_MAC_PRESN_TIME_UPDT_MPTU_WIDTH #define GMAC_MAC_PRESN_TIME_UPDT_MPTU(x) EMAC_MAC_PRESN_TIME_UPDT_MPTU(x) /*! @} */ /*! @name MAC_ADDRESS0_HIGH - */ /*! @{ */ #define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK #define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT #define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_WIDTH EMAC_MAC_ADDRESS0_HIGH_ADDRHI_WIDTH #define GMAC_MAC_ADDRESS0_HIGH_ADDRHI(x) EMAC_MAC_ADDRESS0_HIGH_ADDRHI(x) #define GMAC_MAC_ADDRESS0_HIGH_DCS_MASK EMAC_MAC_ADDRESS0_HIGH_DCS_MASK #define GMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT #define GMAC_MAC_ADDRESS0_HIGH_DCS_WIDTH EMAC_MAC_ADDRESS0_HIGH_DCS_WIDTH #define GMAC_MAC_ADDRESS0_HIGH_DCS(x) EMAC_MAC_ADDRESS0_HIGH_DCS(x) #define GMAC_MAC_ADDRESS0_HIGH_AE_MASK EMAC_MAC_ADDRESS0_HIGH_AE_MASK #define GMAC_MAC_ADDRESS0_HIGH_AE_SHIFT EMAC_MAC_ADDRESS0_HIGH_AE_SHIFT #define GMAC_MAC_ADDRESS0_HIGH_AE_WIDTH EMAC_MAC_ADDRESS0_HIGH_AE_WIDTH #define GMAC_MAC_ADDRESS0_HIGH_AE(x) EMAC_MAC_ADDRESS0_HIGH_AE(x) /*! @} */ /*! @name MAC_ADDRESS0_LOW - */ /*! @{ */ #define GMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK #define GMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT #define GMAC_MAC_ADDRESS0_LOW_ADDRLO_WIDTH EMAC_MAC_ADDRESS0_LOW_ADDRLO_WIDTH #define GMAC_MAC_ADDRESS0_LOW_ADDRLO(x) EMAC_MAC_ADDRESS0_LOW_ADDRLO(x) /*! @} */ /*! @name MAC_ADDRESS1_HIGH - */ /*! @{ */ #define GMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK #define GMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT #define GMAC_MAC_ADDRESS1_HIGH_ADDRHI_WIDTH EMAC_MAC_ADDRESS1_HIGH_ADDRHI_WIDTH #define GMAC_MAC_ADDRESS1_HIGH_ADDRHI(x) EMAC_MAC_ADDRESS1_HIGH_ADDRHI(x) #define GMAC_MAC_ADDRESS1_HIGH_DCS_MASK EMAC_MAC_ADDRESS1_HIGH_DCS_MASK #define GMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT #define GMAC_MAC_ADDRESS1_HIGH_DCS_WIDTH EMAC_MAC_ADDRESS1_HIGH_DCS_WIDTH #define GMAC_MAC_ADDRESS1_HIGH_DCS(x) EMAC_MAC_ADDRESS1_HIGH_DCS(x) #define GMAC_MAC_ADDRESS1_HIGH_MBC_MASK EMAC_MAC_ADDRESS1_HIGH_MBC_MASK #define GMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT #define GMAC_MAC_ADDRESS1_HIGH_MBC_WIDTH EMAC_MAC_ADDRESS1_HIGH_MBC_WIDTH #define GMAC_MAC_ADDRESS1_HIGH_MBC(x) EMAC_MAC_ADDRESS1_HIGH_MBC(x) #define GMAC_MAC_ADDRESS1_HIGH_SA_MASK EMAC_MAC_ADDRESS1_HIGH_SA_MASK #define GMAC_MAC_ADDRESS1_HIGH_SA_SHIFT EMAC_MAC_ADDRESS1_HIGH_SA_SHIFT #define GMAC_MAC_ADDRESS1_HIGH_SA_WIDTH EMAC_MAC_ADDRESS1_HIGH_SA_WIDTH #define GMAC_MAC_ADDRESS1_HIGH_SA(x) EMAC_MAC_ADDRESS1_HIGH_SA(x) #define GMAC_MAC_ADDRESS1_HIGH_AE_MASK EMAC_MAC_ADDRESS1_HIGH_AE_MASK #define GMAC_MAC_ADDRESS1_HIGH_AE_SHIFT EMAC_MAC_ADDRESS1_HIGH_AE_SHIFT #define GMAC_MAC_ADDRESS1_HIGH_AE_WIDTH EMAC_MAC_ADDRESS1_HIGH_AE_WIDTH #define GMAC_MAC_ADDRESS1_HIGH_AE(x) EMAC_MAC_ADDRESS1_HIGH_AE(x) /*! @} */ /*! @name MAC_ADDRESS1_LOW - */ /*! @{ */ #define GMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK #define GMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT #define GMAC_MAC_ADDRESS1_LOW_ADDRLO_WIDTH EMAC_MAC_ADDRESS1_LOW_ADDRLO_WIDTH #define GMAC_MAC_ADDRESS1_LOW_ADDRLO(x) EMAC_MAC_ADDRESS1_LOW_ADDRLO(x) /*! @} */ /*! @name MAC_ADDRESS2_HIGH - */ /*! @{ */ #define GMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK #define GMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT #define GMAC_MAC_ADDRESS2_HIGH_ADDRHI_WIDTH EMAC_MAC_ADDRESS2_HIGH_ADDRHI_WIDTH #define GMAC_MAC_ADDRESS2_HIGH_ADDRHI(x) EMAC_MAC_ADDRESS2_HIGH_ADDRHI(x) #define GMAC_MAC_ADDRESS2_HIGH_DCS_MASK EMAC_MAC_ADDRESS2_HIGH_DCS_MASK #define GMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT #define GMAC_MAC_ADDRESS2_HIGH_DCS_WIDTH EMAC_MAC_ADDRESS2_HIGH_DCS_WIDTH #define GMAC_MAC_ADDRESS2_HIGH_DCS(x) EMAC_MAC_ADDRESS2_HIGH_DCS(x) #define GMAC_MAC_ADDRESS2_HIGH_MBC_MASK EMAC_MAC_ADDRESS2_HIGH_MBC_MASK #define GMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT #define GMAC_MAC_ADDRESS2_HIGH_MBC_WIDTH EMAC_MAC_ADDRESS2_HIGH_MBC_WIDTH #define GMAC_MAC_ADDRESS2_HIGH_MBC(x) EMAC_MAC_ADDRESS2_HIGH_MBC(x) #define GMAC_MAC_ADDRESS2_HIGH_SA_MASK EMAC_MAC_ADDRESS2_HIGH_SA_MASK #define GMAC_MAC_ADDRESS2_HIGH_SA_SHIFT EMAC_MAC_ADDRESS2_HIGH_SA_SHIFT #define GMAC_MAC_ADDRESS2_HIGH_SA_WIDTH EMAC_MAC_ADDRESS2_HIGH_SA_WIDTH #define GMAC_MAC_ADDRESS2_HIGH_SA(x) EMAC_MAC_ADDRESS2_HIGH_SA(x) #define GMAC_MAC_ADDRESS2_HIGH_AE_MASK EMAC_MAC_ADDRESS2_HIGH_AE_MASK #define GMAC_MAC_ADDRESS2_HIGH_AE_SHIFT EMAC_MAC_ADDRESS2_HIGH_AE_SHIFT #define GMAC_MAC_ADDRESS2_HIGH_AE_WIDTH EMAC_MAC_ADDRESS2_HIGH_AE_WIDTH #define GMAC_MAC_ADDRESS2_HIGH_AE(x) EMAC_MAC_ADDRESS2_HIGH_AE(x) /*! @} */ /*! @name MAC_ADDRESS2_LOW - */ /*! @{ */ #define GMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK #define GMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT #define GMAC_MAC_ADDRESS2_LOW_ADDRLO_WIDTH EMAC_MAC_ADDRESS2_LOW_ADDRLO_WIDTH #define GMAC_MAC_ADDRESS2_LOW_ADDRLO(x) EMAC_MAC_ADDRESS2_LOW_ADDRLO(x) /*! @} */ /*! @name MMC_CONTROL - */ /*! @{ */ #define GMAC_MMC_CONTROL_CNTRST_MASK EMAC_MMC_CONTROL_CNTRST_MASK #define GMAC_MMC_CONTROL_CNTRST_SHIFT EMAC_MMC_CONTROL_CNTRST_SHIFT #define GMAC_MMC_CONTROL_CNTRST_WIDTH EMAC_MMC_CONTROL_CNTRST_WIDTH #define GMAC_MMC_CONTROL_CNTRST(x) EMAC_MMC_CONTROL_CNTRST(x) #define GMAC_MMC_CONTROL_CNTSTOPRO_MASK EMAC_MMC_CONTROL_CNTSTOPRO_MASK #define GMAC_MMC_CONTROL_CNTSTOPRO_SHIFT EMAC_MMC_CONTROL_CNTSTOPRO_SHIFT #define GMAC_MMC_CONTROL_CNTSTOPRO_WIDTH EMAC_MMC_CONTROL_CNTSTOPRO_WIDTH #define GMAC_MMC_CONTROL_CNTSTOPRO(x) EMAC_MMC_CONTROL_CNTSTOPRO(x) #define GMAC_MMC_CONTROL_RSTONRD_MASK EMAC_MMC_CONTROL_RSTONRD_MASK #define GMAC_MMC_CONTROL_RSTONRD_SHIFT EMAC_MMC_CONTROL_RSTONRD_SHIFT #define GMAC_MMC_CONTROL_RSTONRD_WIDTH EMAC_MMC_CONTROL_RSTONRD_WIDTH #define GMAC_MMC_CONTROL_RSTONRD(x) EMAC_MMC_CONTROL_RSTONRD(x) #define GMAC_MMC_CONTROL_CNTFREEZ_MASK EMAC_MMC_CONTROL_CNTFREEZ_MASK #define GMAC_MMC_CONTROL_CNTFREEZ_SHIFT EMAC_MMC_CONTROL_CNTFREEZ_SHIFT #define GMAC_MMC_CONTROL_CNTFREEZ_WIDTH EMAC_MMC_CONTROL_CNTFREEZ_WIDTH #define GMAC_MMC_CONTROL_CNTFREEZ(x) EMAC_MMC_CONTROL_CNTFREEZ(x) #define GMAC_MMC_CONTROL_CNTPRST_MASK EMAC_MMC_CONTROL_CNTPRST_MASK #define GMAC_MMC_CONTROL_CNTPRST_SHIFT EMAC_MMC_CONTROL_CNTPRST_SHIFT #define GMAC_MMC_CONTROL_CNTPRST_WIDTH EMAC_MMC_CONTROL_CNTPRST_WIDTH #define GMAC_MMC_CONTROL_CNTPRST(x) EMAC_MMC_CONTROL_CNTPRST(x) #define GMAC_MMC_CONTROL_CNTPRSTLVL_MASK EMAC_MMC_CONTROL_CNTPRSTLVL_MASK #define GMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT EMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT #define GMAC_MMC_CONTROL_CNTPRSTLVL_WIDTH EMAC_MMC_CONTROL_CNTPRSTLVL_WIDTH #define GMAC_MMC_CONTROL_CNTPRSTLVL(x) EMAC_MMC_CONTROL_CNTPRSTLVL(x) #define GMAC_MMC_CONTROL_UCDBC_MASK EMAC_MMC_CONTROL_UCDBC_MASK #define GMAC_MMC_CONTROL_UCDBC_SHIFT EMAC_MMC_CONTROL_UCDBC_SHIFT #define GMAC_MMC_CONTROL_UCDBC_WIDTH EMAC_MMC_CONTROL_UCDBC_WIDTH #define GMAC_MMC_CONTROL_UCDBC(x) EMAC_MMC_CONTROL_UCDBC(x) /*! @} */ /*! @name MMC_RX_INTERRUPT - */ /*! @{ */ #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) EMAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) EMAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK EMAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXGOCTIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS(x) EMAC_MMC_RX_INTERRUPT_RXGOCTIS(x) #define GMAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK EMAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXBCGPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXBCGPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXBCGPIS(x) EMAC_MMC_RX_INTERRUPT_RXBCGPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK EMAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXMCGPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS(x) EMAC_MMC_RX_INTERRUPT_RXMCGPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) EMAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXALGNERPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) EMAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXRUNTPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) EMAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK EMAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXJABERPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXJABERPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXJABERPIS(x) EMAC_MMC_RX_INTERRUPT_RXJABERPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) #define GMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) #define GMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) #define GMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) #define GMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) #define GMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) #define GMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK EMAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXUCGPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXUCGPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXUCGPIS(x) EMAC_MMC_RX_INTERRUPT_RXUCGPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK EMAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXLENERPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS(x) EMAC_MMC_RX_INTERRUPT_RXLENERPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXORANGEPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) EMAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXPAUSPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) EMAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK EMAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXFOVPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS(x) EMAC_MMC_RX_INTERRUPT_RXFOVPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXWDOGPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) EMAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) #define GMAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK #define GMAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT #define GMAC_MMC_RX_INTERRUPT_RXCTRLPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_WIDTH #define GMAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) EMAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) /*! @} */ /*! @name MMC_TX_INTERRUPT - */ /*! @{ */ #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) EMAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) EMAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) #define GMAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK EMAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXBCGPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXBCGPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXBCGPIS(x) EMAC_MMC_TX_INTERRUPT_TXBCGPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK EMAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXMCGPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXMCGPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXMCGPIS(x) EMAC_MMC_TX_INTERRUPT_TXMCGPIS(x) #define GMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXUCGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) EMAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXMCGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) EMAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXBCGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) EMAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK EMAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXDEFPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXDEFPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXDEFPIS(x) EMAC_MMC_TX_INTERRUPT_TXDEFPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK EMAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXCARERPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS(x) EMAC_MMC_TX_INTERRUPT_TXCARERPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK EMAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXGOCTIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS(x) EMAC_MMC_TX_INTERRUPT_TXGOCTIS(x) #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK EMAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXGPKTIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS(x) EMAC_MMC_TX_INTERRUPT_TXGPKTIS(x) #define GMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXPAUSPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) EMAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXVLANGPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) EMAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) #define GMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK #define GMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT #define GMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_WIDTH #define GMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) /*! @} */ /*! @name MMC_RX_INTERRUPT_MASK - */ /*! @{ */ #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) #define GMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK #define GMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT #define GMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_WIDTH #define GMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) /*! @} */ /*! @name MMC_TX_INTERRUPT_MASK - */ /*! @{ */ #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) #define GMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK #define GMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT #define GMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_WIDTH #define GMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) /*! @} */ /*! @name TX_OCTET_COUNT_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK #define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT #define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_WIDTH EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_WIDTH #define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) /*! @} */ /*! @name TX_PACKET_COUNT_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK #define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT #define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_WIDTH EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_WIDTH #define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) /*! @} */ /*! @name TX_BROADCAST_PACKETS_GOOD - */ /*! @{ */ #define GMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK #define GMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT #define GMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_WIDTH EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_WIDTH #define GMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) /*! @} */ /*! @name TX_MULTICAST_PACKETS_GOOD - */ /*! @{ */ #define GMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK #define GMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT #define GMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_WIDTH EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_WIDTH #define GMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) /*! @} */ /*! @name TX_64OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK #define GMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT #define GMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_WIDTH EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_WIDTH #define GMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) /*! @} */ /*! @name TX_65TO127OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK #define GMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT #define GMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_WIDTH EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_WIDTH #define GMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) /*! @} */ /*! @name TX_128TO255OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK #define GMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT #define GMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_WIDTH EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_WIDTH #define GMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) /*! @} */ /*! @name TX_256TO511OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK #define GMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT #define GMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_WIDTH EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_WIDTH #define GMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) /*! @} */ /*! @name TX_512TO1023OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK #define GMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT #define GMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_WIDTH EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_WIDTH #define GMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) /*! @} */ /*! @name TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK #define GMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT #define GMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_WIDTH EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_WIDTH #define GMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) /*! @} */ /*! @name TX_UNICAST_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK #define GMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT #define GMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_WIDTH EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_WIDTH #define GMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) /*! @} */ /*! @name TX_MULTICAST_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK #define GMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT #define GMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_WIDTH EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_WIDTH #define GMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) /*! @} */ /*! @name TX_BROADCAST_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK #define GMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT #define GMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_WIDTH EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_WIDTH #define GMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) /*! @} */ /*! @name TX_UNDERFLOW_ERROR_PACKETS - */ /*! @{ */ #define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK #define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT #define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_WIDTH EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_WIDTH #define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) /*! @} */ /*! @name TX_SINGLE_COLLISION_GOOD_PACKETS - */ /*! @{ */ #define GMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK #define GMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT #define GMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_WIDTH EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_WIDTH #define GMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) /*! @} */ /*! @name TX_MULTIPLE_COLLISION_GOOD_PACKETS - */ /*! @{ */ #define GMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK #define GMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT #define GMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_WIDTH EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_WIDTH #define GMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) /*! @} */ /*! @name TX_DEFERRED_PACKETS - */ /*! @{ */ #define GMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK #define GMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT #define GMAC_TX_DEFERRED_PACKETS_TXDEFRD_WIDTH EMAC_TX_DEFERRED_PACKETS_TXDEFRD_WIDTH #define GMAC_TX_DEFERRED_PACKETS_TXDEFRD(x) EMAC_TX_DEFERRED_PACKETS_TXDEFRD(x) /*! @} */ /*! @name TX_LATE_COLLISION_PACKETS - */ /*! @{ */ #define GMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK #define GMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT #define GMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_WIDTH EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_WIDTH #define GMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) /*! @} */ /*! @name TX_EXCESSIVE_COLLISION_PACKETS - */ /*! @{ */ #define GMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK #define GMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT #define GMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_WIDTH EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_WIDTH #define GMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) /*! @} */ /*! @name TX_CARRIER_ERROR_PACKETS - */ /*! @{ */ #define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK #define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT #define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_WIDTH EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_WIDTH #define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) /*! @} */ /*! @name TX_OCTET_COUNT_GOOD - */ /*! @{ */ #define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK #define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT #define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_WIDTH EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_WIDTH #define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) /*! @} */ /*! @name TX_PACKET_COUNT_GOOD - */ /*! @{ */ #define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK #define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT #define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_WIDTH EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_WIDTH #define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) /*! @} */ /*! @name TX_EXCESSIVE_DEFERRAL_ERROR - */ /*! @{ */ #define GMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK #define GMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT #define GMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_WIDTH EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_WIDTH #define GMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) /*! @} */ /*! @name TX_PAUSE_PACKETS - */ /*! @{ */ #define GMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK #define GMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT #define GMAC_TX_PAUSE_PACKETS_TXPAUSE_WIDTH EMAC_TX_PAUSE_PACKETS_TXPAUSE_WIDTH #define GMAC_TX_PAUSE_PACKETS_TXPAUSE(x) EMAC_TX_PAUSE_PACKETS_TXPAUSE(x) /*! @} */ /*! @name TX_VLAN_PACKETS_GOOD - */ /*! @{ */ #define GMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK #define GMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT #define GMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_WIDTH EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_WIDTH #define GMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) /*! @} */ /*! @name TX_OSIZE_PACKETS_GOOD - */ /*! @{ */ #define GMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK #define GMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT #define GMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_WIDTH EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_WIDTH #define GMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) /*! @} */ /*! @name RX_PACKETS_COUNT_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK #define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT #define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_WIDTH EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_WIDTH #define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) /*! @} */ /*! @name RX_OCTET_COUNT_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK #define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT #define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_WIDTH EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_WIDTH #define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) /*! @} */ /*! @name RX_OCTET_COUNT_GOOD - */ /*! @{ */ #define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK #define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT #define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_WIDTH EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_WIDTH #define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) /*! @} */ /*! @name RX_BROADCAST_PACKETS_GOOD - */ /*! @{ */ #define GMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK #define GMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT #define GMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_WIDTH EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_WIDTH #define GMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) /*! @} */ /*! @name RX_MULTICAST_PACKETS_GOOD - */ /*! @{ */ #define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK #define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT #define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_WIDTH EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_WIDTH #define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) /*! @} */ /*! @name RX_CRC_ERROR_PACKETS - */ /*! @{ */ #define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK #define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT #define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_WIDTH EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_WIDTH #define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) /*! @} */ /*! @name RX_ALIGNMENT_ERROR_PACKETS - */ /*! @{ */ #define GMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK #define GMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT #define GMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_WIDTH EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_WIDTH #define GMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) /*! @} */ /*! @name RX_RUNT_ERROR_PACKETS - */ /*! @{ */ #define GMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK #define GMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT #define GMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_WIDTH EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_WIDTH #define GMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) /*! @} */ /*! @name RX_JABBER_ERROR_PACKETS - */ /*! @{ */ #define GMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK #define GMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT #define GMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_WIDTH EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_WIDTH #define GMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) /*! @} */ /*! @name RX_UNDERSIZE_PACKETS_GOOD - */ /*! @{ */ #define GMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK #define GMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT #define GMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_WIDTH EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_WIDTH #define GMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) /*! @} */ /*! @name RX_OVERSIZE_PACKETS_GOOD - */ /*! @{ */ #define GMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK #define GMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT #define GMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_WIDTH EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_WIDTH #define GMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) /*! @} */ /*! @name RX_64OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK #define GMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT #define GMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_WIDTH EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_WIDTH #define GMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) /*! @} */ /*! @name RX_65TO127OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK #define GMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT #define GMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_WIDTH EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_WIDTH #define GMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) /*! @} */ /*! @name RX_128TO255OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK #define GMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT #define GMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_WIDTH EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_WIDTH #define GMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) /*! @} */ /*! @name RX_256TO511OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK #define GMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT #define GMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_WIDTH EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_WIDTH #define GMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) /*! @} */ /*! @name RX_512TO1023OCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK #define GMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT #define GMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_WIDTH EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_WIDTH #define GMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) /*! @} */ /*! @name RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK #define GMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT #define GMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_WIDTH EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_WIDTH #define GMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) /*! @} */ /*! @name RX_UNICAST_PACKETS_GOOD - */ /*! @{ */ #define GMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK #define GMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT #define GMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_WIDTH EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_WIDTH #define GMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) /*! @} */ /*! @name RX_LENGTH_ERROR_PACKETS - */ /*! @{ */ #define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK #define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT #define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_WIDTH EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_WIDTH #define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) /*! @} */ /*! @name RX_OUT_OF_RANGE_TYPE_PACKETS - */ /*! @{ */ #define GMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK #define GMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT #define GMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_WIDTH EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_WIDTH #define GMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) /*! @} */ /*! @name RX_PAUSE_PACKETS - */ /*! @{ */ #define GMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK #define GMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT #define GMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_WIDTH EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_WIDTH #define GMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) /*! @} */ /*! @name RX_FIFO_OVERFLOW_PACKETS - */ /*! @{ */ #define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK #define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT #define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_WIDTH EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_WIDTH #define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) /*! @} */ /*! @name RX_VLAN_PACKETS_GOOD_BAD - */ /*! @{ */ #define GMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK #define GMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT #define GMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_WIDTH EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_WIDTH #define GMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) /*! @} */ /*! @name RX_WATCHDOG_ERROR_PACKETS - */ /*! @{ */ #define GMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK #define GMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT #define GMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_WIDTH EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_WIDTH #define GMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) /*! @} */ /*! @name RX_RECEIVE_ERROR_PACKETS - */ /*! @{ */ #define GMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK #define GMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT #define GMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_WIDTH EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_WIDTH #define GMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) /*! @} */ /*! @name RX_CONTROL_PACKETS_GOOD - */ /*! @{ */ #define GMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK #define GMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT #define GMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_WIDTH EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_WIDTH #define GMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) /*! @} */ /*! @name MMC_FPE_TX_INTERRUPT - */ /*! @{ */ #define GMAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK EMAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK #define GMAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT EMAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT #define GMAC_MMC_FPE_TX_INTERRUPT_FCIS_WIDTH EMAC_MMC_FPE_TX_INTERRUPT_FCIS_WIDTH #define GMAC_MMC_FPE_TX_INTERRUPT_FCIS(x) EMAC_MMC_FPE_TX_INTERRUPT_FCIS(x) #define GMAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK #define GMAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT #define GMAC_MMC_FPE_TX_INTERRUPT_HRCIS_WIDTH EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_WIDTH #define GMAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) EMAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) /*! @} */ /*! @name MMC_FPE_TX_INTERRUPT_MASK - */ /*! @{ */ #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_WIDTH EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_WIDTH #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_WIDTH EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_WIDTH #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) /*! @} */ /*! @name MMC_TX_FPE_FRAGMENT_CNTR - */ /*! @{ */ #define GMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK #define GMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT #define GMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_WIDTH EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_WIDTH #define GMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) /*! @} */ /*! @name MMC_TX_HOLD_REQ_CNTR - */ /*! @{ */ #define GMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK #define GMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT #define GMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_WIDTH EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_WIDTH #define GMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) /*! @} */ /*! @name MMC_FPE_RX_INTERRUPT - */ /*! @{ */ #define GMAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK #define GMAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT #define GMAC_MMC_FPE_RX_INTERRUPT_PAECIS_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_WIDTH #define GMAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) EMAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) #define GMAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK #define GMAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT #define GMAC_MMC_FPE_RX_INTERRUPT_PSECIS_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_WIDTH #define GMAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) EMAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) #define GMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK #define GMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT #define GMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_WIDTH #define GMAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) #define GMAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK EMAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK #define GMAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT #define GMAC_MMC_FPE_RX_INTERRUPT_FCIS_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_FCIS_WIDTH #define GMAC_MMC_FPE_RX_INTERRUPT_FCIS(x) EMAC_MMC_FPE_RX_INTERRUPT_FCIS(x) /*! @} */ /*! @name MMC_FPE_RX_INTERRUPT_MASK - */ /*! @{ */ #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_WIDTH #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_WIDTH #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_WIDTH #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_WIDTH #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) /*! @} */ /*! @name MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - */ /*! @{ */ #define GMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK #define GMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT #define GMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_WIDTH EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_WIDTH #define GMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) /*! @} */ /*! @name MMC_RX_PACKET_SMD_ERR_CNTR - */ /*! @{ */ #define GMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK #define GMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT #define GMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_WIDTH EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_WIDTH #define GMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) /*! @} */ /*! @name MMC_RX_PACKET_ASSEMBLY_OK_CNTR - */ /*! @{ */ #define GMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK #define GMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT #define GMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_WIDTH EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_WIDTH #define GMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) /*! @} */ /*! @name MMC_RX_FPE_FRAGMENT_CNTR - */ /*! @{ */ #define GMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK #define GMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT #define GMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_WIDTH EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_WIDTH #define GMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) /*! @} */ /*! @name MAC_L3_L4_CONTROL0 - */ /*! @{ */ #define GMAC_MAC_L3_L4_CONTROL0_L3PEN0_MASK EMAC_MAC_L3_L4_CONTROL0_L3PEN0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L3PEN0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L3PEN0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L3PEN0(x) EMAC_MAC_L3_L4_CONTROL0_L3PEN0(x) #define GMAC_MAC_L3_L4_CONTROL0_L3SAM0_MASK EMAC_MAC_L3_L4_CONTROL0_L3SAM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L3SAM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L3SAM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L3SAM0(x) EMAC_MAC_L3_L4_CONTROL0_L3SAM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L3SAIM0_MASK EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L3SAIM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L3SAIM0(x) EMAC_MAC_L3_L4_CONTROL0_L3SAIM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L3DAM0_MASK EMAC_MAC_L3_L4_CONTROL0_L3DAM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L3DAM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L3DAM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L3DAM0(x) EMAC_MAC_L3_L4_CONTROL0_L3DAM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L3DAIM0_MASK EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L3DAIM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L3DAIM0(x) EMAC_MAC_L3_L4_CONTROL0_L3DAIM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L3HSBM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L3HSBM0(x) EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L3HDBM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L3HDBM0(x) EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L4PEN0_MASK EMAC_MAC_L3_L4_CONTROL0_L4PEN0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L4PEN0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L4PEN0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L4PEN0(x) EMAC_MAC_L3_L4_CONTROL0_L4PEN0(x) #define GMAC_MAC_L3_L4_CONTROL0_L4SPM0_MASK EMAC_MAC_L3_L4_CONTROL0_L4SPM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L4SPM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L4SPM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L4SPM0(x) EMAC_MAC_L3_L4_CONTROL0_L4SPM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L4SPIM0_MASK EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L4SPIM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L4SPIM0(x) EMAC_MAC_L3_L4_CONTROL0_L4SPIM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L4DPM0_MASK EMAC_MAC_L3_L4_CONTROL0_L4DPM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L4DPM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L4DPM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L4DPM0(x) EMAC_MAC_L3_L4_CONTROL0_L4DPM0(x) #define GMAC_MAC_L3_L4_CONTROL0_L4DPIM0_MASK EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_MASK #define GMAC_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_L4DPIM0_WIDTH EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_L4DPIM0(x) EMAC_MAC_L3_L4_CONTROL0_L4DPIM0(x) #define GMAC_MAC_L3_L4_CONTROL0_DMCHN0_MASK EMAC_MAC_L3_L4_CONTROL0_DMCHN0_MASK #define GMAC_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT EMAC_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_DMCHN0_WIDTH EMAC_MAC_L3_L4_CONTROL0_DMCHN0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_DMCHN0(x) EMAC_MAC_L3_L4_CONTROL0_DMCHN0(x) #define GMAC_MAC_L3_L4_CONTROL0_DMCHEN0_MASK EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_MASK #define GMAC_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT #define GMAC_MAC_L3_L4_CONTROL0_DMCHEN0_WIDTH EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_WIDTH #define GMAC_MAC_L3_L4_CONTROL0_DMCHEN0(x) EMAC_MAC_L3_L4_CONTROL0_DMCHEN0(x) /*! @} */ /*! @name MAC_LAYER4_ADDRESS0 - */ /*! @{ */ #define GMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK #define GMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT #define GMAC_MAC_LAYER4_ADDRESS0_L4SP0_WIDTH EMAC_MAC_LAYER4_ADDRESS0_L4SP0_WIDTH #define GMAC_MAC_LAYER4_ADDRESS0_L4SP0(x) EMAC_MAC_LAYER4_ADDRESS0_L4SP0(x) #define GMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK #define GMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT #define GMAC_MAC_LAYER4_ADDRESS0_L4DP0_WIDTH EMAC_MAC_LAYER4_ADDRESS0_L4DP0_WIDTH #define GMAC_MAC_LAYER4_ADDRESS0_L4DP0(x) EMAC_MAC_LAYER4_ADDRESS0_L4DP0(x) /*! @} */ /*! @name MAC_LAYER3_ADDR0_REG0 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK #define GMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT #define GMAC_MAC_LAYER3_ADDR0_REG0_L3A00_WIDTH EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_WIDTH #define GMAC_MAC_LAYER3_ADDR0_REG0_L3A00(x) EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(x) /*! @} */ /*! @name MAC_LAYER3_ADDR1_REG0 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK #define GMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT #define GMAC_MAC_LAYER3_ADDR1_REG0_L3A10_WIDTH EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_WIDTH #define GMAC_MAC_LAYER3_ADDR1_REG0_L3A10(x) EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(x) /*! @} */ /*! @name MAC_LAYER3_ADDR2_REG0 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK #define GMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT #define GMAC_MAC_LAYER3_ADDR2_REG0_L3A20_WIDTH EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_WIDTH #define GMAC_MAC_LAYER3_ADDR2_REG0_L3A20(x) EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(x) /*! @} */ /*! @name MAC_LAYER3_ADDR3_REG0 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK #define GMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT #define GMAC_MAC_LAYER3_ADDR3_REG0_L3A30_WIDTH EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_WIDTH #define GMAC_MAC_LAYER3_ADDR3_REG0_L3A30(x) EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(x) /*! @} */ /*! @name MAC_L3_L4_CONTROL1 - */ /*! @{ */ #define GMAC_MAC_L3_L4_CONTROL1_L3PEN1_MASK EMAC_MAC_L3_L4_CONTROL1_L3PEN1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L3PEN1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L3PEN1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L3PEN1(x) EMAC_MAC_L3_L4_CONTROL1_L3PEN1(x) #define GMAC_MAC_L3_L4_CONTROL1_L3SAM1_MASK EMAC_MAC_L3_L4_CONTROL1_L3SAM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L3SAM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L3SAM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L3SAM1(x) EMAC_MAC_L3_L4_CONTROL1_L3SAM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L3SAIM1_MASK EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L3SAIM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L3SAIM1(x) EMAC_MAC_L3_L4_CONTROL1_L3SAIM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L3DAM1_MASK EMAC_MAC_L3_L4_CONTROL1_L3DAM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L3DAM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L3DAM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L3DAM1(x) EMAC_MAC_L3_L4_CONTROL1_L3DAM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L3DAIM1_MASK EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L3DAIM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L3DAIM1(x) EMAC_MAC_L3_L4_CONTROL1_L3DAIM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L3HSBM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L3HSBM1(x) EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L3HDBM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L3HDBM1(x) EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L4PEN1_MASK EMAC_MAC_L3_L4_CONTROL1_L4PEN1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L4PEN1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L4PEN1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L4PEN1(x) EMAC_MAC_L3_L4_CONTROL1_L4PEN1(x) #define GMAC_MAC_L3_L4_CONTROL1_L4SPM1_MASK EMAC_MAC_L3_L4_CONTROL1_L4SPM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L4SPM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L4SPM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L4SPM1(x) EMAC_MAC_L3_L4_CONTROL1_L4SPM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L4SPIM1_MASK EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L4SPIM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L4SPIM1(x) EMAC_MAC_L3_L4_CONTROL1_L4SPIM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L4DPM1_MASK EMAC_MAC_L3_L4_CONTROL1_L4DPM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L4DPM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L4DPM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L4DPM1(x) EMAC_MAC_L3_L4_CONTROL1_L4DPM1(x) #define GMAC_MAC_L3_L4_CONTROL1_L4DPIM1_MASK EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_MASK #define GMAC_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_L4DPIM1_WIDTH EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_L4DPIM1(x) EMAC_MAC_L3_L4_CONTROL1_L4DPIM1(x) #define GMAC_MAC_L3_L4_CONTROL1_DMCHN1_MASK EMAC_MAC_L3_L4_CONTROL1_DMCHN1_MASK #define GMAC_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT EMAC_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_DMCHN1_WIDTH EMAC_MAC_L3_L4_CONTROL1_DMCHN1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_DMCHN1(x) EMAC_MAC_L3_L4_CONTROL1_DMCHN1(x) #define GMAC_MAC_L3_L4_CONTROL1_DMCHEN1_MASK EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_MASK #define GMAC_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT #define GMAC_MAC_L3_L4_CONTROL1_DMCHEN1_WIDTH EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_WIDTH #define GMAC_MAC_L3_L4_CONTROL1_DMCHEN1(x) EMAC_MAC_L3_L4_CONTROL1_DMCHEN1(x) /*! @} */ /*! @name MAC_LAYER4_ADDRESS1 - */ /*! @{ */ #define GMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK #define GMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT #define GMAC_MAC_LAYER4_ADDRESS1_L4SP1_WIDTH EMAC_MAC_LAYER4_ADDRESS1_L4SP1_WIDTH #define GMAC_MAC_LAYER4_ADDRESS1_L4SP1(x) EMAC_MAC_LAYER4_ADDRESS1_L4SP1(x) #define GMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK #define GMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT #define GMAC_MAC_LAYER4_ADDRESS1_L4DP1_WIDTH EMAC_MAC_LAYER4_ADDRESS1_L4DP1_WIDTH #define GMAC_MAC_LAYER4_ADDRESS1_L4DP1(x) EMAC_MAC_LAYER4_ADDRESS1_L4DP1(x) /*! @} */ /*! @name MAC_LAYER3_ADDR0_REG1 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK #define GMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT #define GMAC_MAC_LAYER3_ADDR0_REG1_L3A01_WIDTH EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_WIDTH #define GMAC_MAC_LAYER3_ADDR0_REG1_L3A01(x) EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(x) /*! @} */ /*! @name MAC_LAYER3_ADDR1_REG1 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK #define GMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT #define GMAC_MAC_LAYER3_ADDR1_REG1_L3A11_WIDTH EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_WIDTH #define GMAC_MAC_LAYER3_ADDR1_REG1_L3A11(x) EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(x) /*! @} */ /*! @name MAC_LAYER3_ADDR2_REG1 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK #define GMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT #define GMAC_MAC_LAYER3_ADDR2_REG1_L3A21_WIDTH EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_WIDTH #define GMAC_MAC_LAYER3_ADDR2_REG1_L3A21(x) EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(x) /*! @} */ /*! @name MAC_LAYER3_ADDR3_REG1 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK #define GMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT #define GMAC_MAC_LAYER3_ADDR3_REG1_L3A31_WIDTH EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_WIDTH #define GMAC_MAC_LAYER3_ADDR3_REG1_L3A31(x) EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(x) /*! @} */ /*! @name MAC_L3_L4_CONTROL2 - */ /*! @{ */ #define GMAC_MAC_L3_L4_CONTROL2_L3PEN2_MASK EMAC_MAC_L3_L4_CONTROL2_L3PEN2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L3PEN2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L3PEN2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L3PEN2(x) EMAC_MAC_L3_L4_CONTROL2_L3PEN2(x) #define GMAC_MAC_L3_L4_CONTROL2_L3SAM2_MASK EMAC_MAC_L3_L4_CONTROL2_L3SAM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L3SAM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L3SAM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L3SAM2(x) EMAC_MAC_L3_L4_CONTROL2_L3SAM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L3SAIM2_MASK EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L3SAIM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L3SAIM2(x) EMAC_MAC_L3_L4_CONTROL2_L3SAIM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L3DAM2_MASK EMAC_MAC_L3_L4_CONTROL2_L3DAM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L3DAM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L3DAM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L3DAM2(x) EMAC_MAC_L3_L4_CONTROL2_L3DAM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L3DAIM2_MASK EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L3DAIM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L3DAIM2(x) EMAC_MAC_L3_L4_CONTROL2_L3DAIM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L3HSBM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L3HSBM2(x) EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L3HDBM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L3HDBM2(x) EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L4PEN2_MASK EMAC_MAC_L3_L4_CONTROL2_L4PEN2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L4PEN2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L4PEN2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L4PEN2(x) EMAC_MAC_L3_L4_CONTROL2_L4PEN2(x) #define GMAC_MAC_L3_L4_CONTROL2_L4SPM2_MASK EMAC_MAC_L3_L4_CONTROL2_L4SPM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L4SPM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L4SPM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L4SPM2(x) EMAC_MAC_L3_L4_CONTROL2_L4SPM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L4SPIM2_MASK EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L4SPIM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L4SPIM2(x) EMAC_MAC_L3_L4_CONTROL2_L4SPIM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L4DPM2_MASK EMAC_MAC_L3_L4_CONTROL2_L4DPM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L4DPM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L4DPM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L4DPM2(x) EMAC_MAC_L3_L4_CONTROL2_L4DPM2(x) #define GMAC_MAC_L3_L4_CONTROL2_L4DPIM2_MASK EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_MASK #define GMAC_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_L4DPIM2_WIDTH EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_L4DPIM2(x) EMAC_MAC_L3_L4_CONTROL2_L4DPIM2(x) #define GMAC_MAC_L3_L4_CONTROL2_DMCHN2_MASK EMAC_MAC_L3_L4_CONTROL2_DMCHN2_MASK #define GMAC_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT EMAC_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_DMCHN2_WIDTH EMAC_MAC_L3_L4_CONTROL2_DMCHN2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_DMCHN2(x) EMAC_MAC_L3_L4_CONTROL2_DMCHN2(x) #define GMAC_MAC_L3_L4_CONTROL2_DMCHEN2_MASK EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_MASK #define GMAC_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT #define GMAC_MAC_L3_L4_CONTROL2_DMCHEN2_WIDTH EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_WIDTH #define GMAC_MAC_L3_L4_CONTROL2_DMCHEN2(x) EMAC_MAC_L3_L4_CONTROL2_DMCHEN2(x) /*! @} */ /*! @name MAC_LAYER4_ADDRESS2 - */ /*! @{ */ #define GMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK #define GMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT #define GMAC_MAC_LAYER4_ADDRESS2_L4SP2_WIDTH EMAC_MAC_LAYER4_ADDRESS2_L4SP2_WIDTH #define GMAC_MAC_LAYER4_ADDRESS2_L4SP2(x) EMAC_MAC_LAYER4_ADDRESS2_L4SP2(x) #define GMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK #define GMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT #define GMAC_MAC_LAYER4_ADDRESS2_L4DP2_WIDTH EMAC_MAC_LAYER4_ADDRESS2_L4DP2_WIDTH #define GMAC_MAC_LAYER4_ADDRESS2_L4DP2(x) EMAC_MAC_LAYER4_ADDRESS2_L4DP2(x) /*! @} */ /*! @name MAC_LAYER3_ADDR0_REG2 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK #define GMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT #define GMAC_MAC_LAYER3_ADDR0_REG2_L3A02_WIDTH EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_WIDTH #define GMAC_MAC_LAYER3_ADDR0_REG2_L3A02(x) EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(x) /*! @} */ /*! @name MAC_LAYER3_ADDR1_REG2 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK #define GMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT #define GMAC_MAC_LAYER3_ADDR1_REG2_L3A12_WIDTH EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_WIDTH #define GMAC_MAC_LAYER3_ADDR1_REG2_L3A12(x) EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(x) /*! @} */ /*! @name MAC_LAYER3_ADDR2_REG2 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK #define GMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT #define GMAC_MAC_LAYER3_ADDR2_REG2_L3A22_WIDTH EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_WIDTH #define GMAC_MAC_LAYER3_ADDR2_REG2_L3A22(x) EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(x) /*! @} */ /*! @name MAC_LAYER3_ADDR3_REG2 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK #define GMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT #define GMAC_MAC_LAYER3_ADDR3_REG2_L3A32_WIDTH EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_WIDTH #define GMAC_MAC_LAYER3_ADDR3_REG2_L3A32(x) EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(x) /*! @} */ /*! @name MAC_L3_L4_CONTROL3 - */ /*! @{ */ #define GMAC_MAC_L3_L4_CONTROL3_L3PEN3_MASK EMAC_MAC_L3_L4_CONTROL3_L3PEN3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L3PEN3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L3PEN3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L3PEN3(x) EMAC_MAC_L3_L4_CONTROL3_L3PEN3(x) #define GMAC_MAC_L3_L4_CONTROL3_L3SAM3_MASK EMAC_MAC_L3_L4_CONTROL3_L3SAM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L3SAM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L3SAM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L3SAM3(x) EMAC_MAC_L3_L4_CONTROL3_L3SAM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L3SAIM3_MASK EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L3SAIM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L3SAIM3(x) EMAC_MAC_L3_L4_CONTROL3_L3SAIM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L3DAM3_MASK EMAC_MAC_L3_L4_CONTROL3_L3DAM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L3DAM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L3DAM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L3DAM3(x) EMAC_MAC_L3_L4_CONTROL3_L3DAM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L3DAIM3_MASK EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L3DAIM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L3DAIM3(x) EMAC_MAC_L3_L4_CONTROL3_L3DAIM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L3HSBM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L3HSBM3(x) EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L3HDBM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L3HDBM3(x) EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L4PEN3_MASK EMAC_MAC_L3_L4_CONTROL3_L4PEN3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L4PEN3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L4PEN3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L4PEN3(x) EMAC_MAC_L3_L4_CONTROL3_L4PEN3(x) #define GMAC_MAC_L3_L4_CONTROL3_L4SPM3_MASK EMAC_MAC_L3_L4_CONTROL3_L4SPM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L4SPM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L4SPM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L4SPM3(x) EMAC_MAC_L3_L4_CONTROL3_L4SPM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L4SPIM3_MASK EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L4SPIM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L4SPIM3(x) EMAC_MAC_L3_L4_CONTROL3_L4SPIM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L4DPM3_MASK EMAC_MAC_L3_L4_CONTROL3_L4DPM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L4DPM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L4DPM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L4DPM3(x) EMAC_MAC_L3_L4_CONTROL3_L4DPM3(x) #define GMAC_MAC_L3_L4_CONTROL3_L4DPIM3_MASK EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_MASK #define GMAC_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_L4DPIM3_WIDTH EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_L4DPIM3(x) EMAC_MAC_L3_L4_CONTROL3_L4DPIM3(x) #define GMAC_MAC_L3_L4_CONTROL3_DMCHN3_MASK EMAC_MAC_L3_L4_CONTROL3_DMCHN3_MASK #define GMAC_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT EMAC_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_DMCHN3_WIDTH EMAC_MAC_L3_L4_CONTROL3_DMCHN3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_DMCHN3(x) EMAC_MAC_L3_L4_CONTROL3_DMCHN3(x) #define GMAC_MAC_L3_L4_CONTROL3_DMCHEN3_MASK EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_MASK #define GMAC_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT #define GMAC_MAC_L3_L4_CONTROL3_DMCHEN3_WIDTH EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_WIDTH #define GMAC_MAC_L3_L4_CONTROL3_DMCHEN3(x) EMAC_MAC_L3_L4_CONTROL3_DMCHEN3(x) /*! @} */ /*! @name MAC_LAYER4_ADDRESS3 - */ /*! @{ */ #define GMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK #define GMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT #define GMAC_MAC_LAYER4_ADDRESS3_L4SP3_WIDTH EMAC_MAC_LAYER4_ADDRESS3_L4SP3_WIDTH #define GMAC_MAC_LAYER4_ADDRESS3_L4SP3(x) EMAC_MAC_LAYER4_ADDRESS3_L4SP3(x) #define GMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK #define GMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT #define GMAC_MAC_LAYER4_ADDRESS3_L4DP3_WIDTH EMAC_MAC_LAYER4_ADDRESS3_L4DP3_WIDTH #define GMAC_MAC_LAYER4_ADDRESS3_L4DP3(x) EMAC_MAC_LAYER4_ADDRESS3_L4DP3(x) /*! @} */ /*! @name MAC_LAYER3_ADDR0_REG3 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK #define GMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT #define GMAC_MAC_LAYER3_ADDR0_REG3_L3A03_WIDTH EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_WIDTH #define GMAC_MAC_LAYER3_ADDR0_REG3_L3A03(x) EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(x) /*! @} */ /*! @name MAC_LAYER3_ADDR1_REG3 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK #define GMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT #define GMAC_MAC_LAYER3_ADDR1_REG3_L3A13_WIDTH EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_WIDTH #define GMAC_MAC_LAYER3_ADDR1_REG3_L3A13(x) EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(x) /*! @} */ /*! @name MAC_LAYER3_ADDR2_REG3 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK #define GMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT #define GMAC_MAC_LAYER3_ADDR2_REG3_L3A23_WIDTH EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_WIDTH #define GMAC_MAC_LAYER3_ADDR2_REG3_L3A23(x) EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(x) /*! @} */ /*! @name MAC_LAYER3_ADDR3_REG3 - */ /*! @{ */ #define GMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK #define GMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT #define GMAC_MAC_LAYER3_ADDR3_REG3_L3A33_WIDTH EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_WIDTH #define GMAC_MAC_LAYER3_ADDR3_REG3_L3A33(x) EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(x) /*! @} */ /*! @name MAC_TIMESTAMP_CONTROL - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSENA_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSENA(x) EMAC_MAC_TIMESTAMP_CONTROL_TSENA(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT(x) EMAC_MAC_TIMESTAMP_CONTROL_TSINIT(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT(x) EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG(x) EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG(x) #define GMAC_MAC_TIMESTAMP_CONTROL_PTGE_MASK EMAC_MAC_TIMESTAMP_CONTROL_PTGE_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_PTGE_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_PTGE_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_PTGE(x) EMAC_MAC_TIMESTAMP_CONTROL_PTGE(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL(x) EMAC_MAC_TIMESTAMP_CONTROL_TSENALL(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA(x) EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) #define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) #define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_MASK EMAC_MAC_TIMESTAMP_CONTROL_ESTI_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_ESTI_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_ESTI(x) EMAC_MAC_TIMESTAMP_CONTROL_ESTI(x) #define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) #define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK #define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT #define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_WIDTH #define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) /*! @} */ /*! @name MAC_SUB_SECOND_INCREMENT - */ /*! @{ */ #define GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK #define GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT #define GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_WIDTH EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_WIDTH #define GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(x) EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(x) #define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK #define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT #define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_WIDTH EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_WIDTH #define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC(x) EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(x) /*! @} */ /*! @name MAC_SYSTEM_TIME_SECONDS - */ /*! @{ */ #define GMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK #define GMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT #define GMAC_MAC_SYSTEM_TIME_SECONDS_TSS_WIDTH EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_WIDTH #define GMAC_MAC_SYSTEM_TIME_SECONDS_TSS(x) EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(x) /*! @} */ /*! @name MAC_SYSTEM_TIME_NANOSECONDS - */ /*! @{ */ #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_WIDTH EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_WIDTH #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) /*! @} */ /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - */ /*! @{ */ #define GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK #define GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT #define GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_WIDTH EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_WIDTH #define GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) /*! @} */ /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - */ /*! @{ */ #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_WIDTH EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_WIDTH #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_WIDTH EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_WIDTH #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) /*! @} */ /*! @name MAC_TIMESTAMP_ADDEND - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK #define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT #define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_WIDTH EMAC_MAC_TIMESTAMP_ADDEND_TSAR_WIDTH #define GMAC_MAC_TIMESTAMP_ADDEND_TSAR(x) EMAC_MAC_TIMESTAMP_ADDEND_TSAR(x) /*! @} */ /*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - */ /*! @{ */ #define GMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK #define GMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT #define GMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_WIDTH EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_WIDTH #define GMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) /*! @} */ /*! @name MAC_TIMESTAMP_STATUS - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_MASK EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF(x) EMAC_MAC_TIMESTAMP_STATUS_TSSOVF(x) #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0(x) EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0(x) #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT1(x) EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1(x) #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT2(x) EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2(x) #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT3(x) EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3(x) #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) #define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK #define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT #define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_WIDTH #define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS(x) EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS(x) /*! @} */ /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - */ /*! @{ */ #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_WIDTH EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_WIDTH #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_WIDTH EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_WIDTH #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) /*! @} */ /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - */ /*! @{ */ #define GMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK #define GMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT #define GMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_WIDTH EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_WIDTH #define GMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) /*! @} */ /*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK #define GMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT #define GMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_WIDTH #define GMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) /*! @} */ /*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK #define GMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT #define GMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_WIDTH #define GMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) /*! @} */ /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_WIDTH #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) /*! @} */ /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_WIDTH #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) /*! @} */ /*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_WIDTH #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) /*! @} */ /*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_WIDTH #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) /*! @} */ /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_WIDTH #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_WIDTH #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) /*! @} */ /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - */ /*! @{ */ #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_WIDTH #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_WIDTH #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) /*! @} */ /*! @name MAC_PPS_CONTROL - */ /*! @{ */ #define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK #define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT #define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_WIDTH EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_WIDTH #define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) #define GMAC_MAC_PPS_CONTROL_PPSEN0_MASK EMAC_MAC_PPS_CONTROL_PPSEN0_MASK #define GMAC_MAC_PPS_CONTROL_PPSEN0_SHIFT EMAC_MAC_PPS_CONTROL_PPSEN0_SHIFT #define GMAC_MAC_PPS_CONTROL_PPSEN0_WIDTH EMAC_MAC_PPS_CONTROL_PPSEN0_WIDTH #define GMAC_MAC_PPS_CONTROL_PPSEN0(x) EMAC_MAC_PPS_CONTROL_PPSEN0(x) #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL0_WIDTH EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_WIDTH #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL0(x) EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(x) #define GMAC_MAC_PPS_CONTROL_MCGREN0_MASK EMAC_MAC_PPS_CONTROL_MCGREN0_MASK #define GMAC_MAC_PPS_CONTROL_MCGREN0_SHIFT EMAC_MAC_PPS_CONTROL_MCGREN0_SHIFT #define GMAC_MAC_PPS_CONTROL_MCGREN0_WIDTH EMAC_MAC_PPS_CONTROL_MCGREN0_WIDTH #define GMAC_MAC_PPS_CONTROL_MCGREN0(x) EMAC_MAC_PPS_CONTROL_MCGREN0(x) #define GMAC_MAC_PPS_CONTROL_PPSCMD1_MASK EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK #define GMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT #define GMAC_MAC_PPS_CONTROL_PPSCMD1_WIDTH EMAC_MAC_PPS_CONTROL_PPSCMD1_WIDTH #define GMAC_MAC_PPS_CONTROL_PPSCMD1(x) EMAC_MAC_PPS_CONTROL_PPSCMD1(x) #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL1_WIDTH EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_WIDTH #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL1(x) EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(x) #define GMAC_MAC_PPS_CONTROL_MCGREN1_MASK EMAC_MAC_PPS_CONTROL_MCGREN1_MASK #define GMAC_MAC_PPS_CONTROL_MCGREN1_SHIFT EMAC_MAC_PPS_CONTROL_MCGREN1_SHIFT #define GMAC_MAC_PPS_CONTROL_MCGREN1_WIDTH EMAC_MAC_PPS_CONTROL_MCGREN1_WIDTH #define GMAC_MAC_PPS_CONTROL_MCGREN1(x) EMAC_MAC_PPS_CONTROL_MCGREN1(x) #define GMAC_MAC_PPS_CONTROL_PPSCMD2_MASK EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK #define GMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT #define GMAC_MAC_PPS_CONTROL_PPSCMD2_WIDTH EMAC_MAC_PPS_CONTROL_PPSCMD2_WIDTH #define GMAC_MAC_PPS_CONTROL_PPSCMD2(x) EMAC_MAC_PPS_CONTROL_PPSCMD2(x) #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL2_WIDTH EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_WIDTH #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL2(x) EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(x) #define GMAC_MAC_PPS_CONTROL_MCGREN2_MASK EMAC_MAC_PPS_CONTROL_MCGREN2_MASK #define GMAC_MAC_PPS_CONTROL_MCGREN2_SHIFT EMAC_MAC_PPS_CONTROL_MCGREN2_SHIFT #define GMAC_MAC_PPS_CONTROL_MCGREN2_WIDTH EMAC_MAC_PPS_CONTROL_MCGREN2_WIDTH #define GMAC_MAC_PPS_CONTROL_MCGREN2(x) EMAC_MAC_PPS_CONTROL_MCGREN2(x) #define GMAC_MAC_PPS_CONTROL_PPSCMD3_MASK EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK #define GMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT #define GMAC_MAC_PPS_CONTROL_PPSCMD3_WIDTH EMAC_MAC_PPS_CONTROL_PPSCMD3_WIDTH #define GMAC_MAC_PPS_CONTROL_PPSCMD3(x) EMAC_MAC_PPS_CONTROL_PPSCMD3(x) #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL3_WIDTH EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_WIDTH #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL3(x) EMAC_MAC_PPS_CONTROL_TRGTMODSEL3(x) #define GMAC_MAC_PPS_CONTROL_MCGREN3_MASK EMAC_MAC_PPS_CONTROL_MCGREN3_MASK #define GMAC_MAC_PPS_CONTROL_MCGREN3_SHIFT EMAC_MAC_PPS_CONTROL_MCGREN3_SHIFT #define GMAC_MAC_PPS_CONTROL_MCGREN3_WIDTH EMAC_MAC_PPS_CONTROL_MCGREN3_WIDTH #define GMAC_MAC_PPS_CONTROL_MCGREN3(x) EMAC_MAC_PPS_CONTROL_MCGREN3(x) /*! @} */ /*! @name MAC_PPS0_TARGET_TIME_SECONDS - */ /*! @{ */ #define GMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK #define GMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT #define GMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_WIDTH EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_WIDTH #define GMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) /*! @} */ /*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - */ /*! @{ */ #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_WIDTH EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_WIDTH #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_WIDTH EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_WIDTH #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) /*! @} */ /*! @name MAC_PPS0_INTERVAL - */ /*! @{ */ #define GMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK #define GMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT #define GMAC_MAC_PPS0_INTERVAL_PPSINT0_WIDTH EMAC_MAC_PPS0_INTERVAL_PPSINT0_WIDTH #define GMAC_MAC_PPS0_INTERVAL_PPSINT0(x) EMAC_MAC_PPS0_INTERVAL_PPSINT0(x) /*! @} */ /*! @name MAC_PPS0_WIDTH - */ /*! @{ */ #define GMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK #define GMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT #define GMAC_MAC_PPS0_WIDTH_PPSWIDTH0_WIDTH EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_WIDTH #define GMAC_MAC_PPS0_WIDTH_PPSWIDTH0(x) EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(x) /*! @} */ /*! @name MAC_PPS1_TARGET_TIME_SECONDS - */ /*! @{ */ #define GMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK #define GMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT #define GMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_WIDTH EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_WIDTH #define GMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) /*! @} */ /*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - */ /*! @{ */ #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_WIDTH EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_WIDTH #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_WIDTH EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_WIDTH #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) /*! @} */ /*! @name MAC_PPS1_INTERVAL - */ /*! @{ */ #define GMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK #define GMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT #define GMAC_MAC_PPS1_INTERVAL_PPSINT1_WIDTH EMAC_MAC_PPS1_INTERVAL_PPSINT1_WIDTH #define GMAC_MAC_PPS1_INTERVAL_PPSINT1(x) EMAC_MAC_PPS1_INTERVAL_PPSINT1(x) /*! @} */ /*! @name MAC_PPS1_WIDTH - */ /*! @{ */ #define GMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK #define GMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT #define GMAC_MAC_PPS1_WIDTH_PPSWIDTH1_WIDTH EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_WIDTH #define GMAC_MAC_PPS1_WIDTH_PPSWIDTH1(x) EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(x) /*! @} */ /*! @name MAC_PPS2_TARGET_TIME_SECONDS - */ /*! @{ */ #define GMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK #define GMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT #define GMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_WIDTH EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_WIDTH #define GMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) /*! @} */ /*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - */ /*! @{ */ #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_WIDTH EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_WIDTH #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_WIDTH EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_WIDTH #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) /*! @} */ /*! @name MAC_PPS2_INTERVAL - */ /*! @{ */ #define GMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK #define GMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT #define GMAC_MAC_PPS2_INTERVAL_PPSINT2_WIDTH EMAC_MAC_PPS2_INTERVAL_PPSINT2_WIDTH #define GMAC_MAC_PPS2_INTERVAL_PPSINT2(x) EMAC_MAC_PPS2_INTERVAL_PPSINT2(x) /*! @} */ /*! @name MAC_PPS2_WIDTH - */ /*! @{ */ #define GMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK #define GMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT #define GMAC_MAC_PPS2_WIDTH_PPSWIDTH2_WIDTH EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_WIDTH #define GMAC_MAC_PPS2_WIDTH_PPSWIDTH2(x) EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(x) /*! @} */ /*! @name MAC_PPS3_TARGET_TIME_SECONDS - */ /*! @{ */ #define GMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK #define GMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT #define GMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_WIDTH EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_WIDTH #define GMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) /*! @} */ /*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - */ /*! @{ */ #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_WIDTH EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_WIDTH #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_WIDTH EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_WIDTH #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) /*! @} */ /*! @name MAC_PPS3_INTERVAL - */ /*! @{ */ #define GMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK #define GMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT #define GMAC_MAC_PPS3_INTERVAL_PPSINT3_WIDTH EMAC_MAC_PPS3_INTERVAL_PPSINT3_WIDTH #define GMAC_MAC_PPS3_INTERVAL_PPSINT3(x) EMAC_MAC_PPS3_INTERVAL_PPSINT3(x) /*! @} */ /*! @name MAC_PPS3_WIDTH - */ /*! @{ */ #define GMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK #define GMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT #define GMAC_MAC_PPS3_WIDTH_PPSWIDTH3_WIDTH EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_WIDTH #define GMAC_MAC_PPS3_WIDTH_PPSWIDTH3(x) EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(x) /*! @} */ /*! @name MTL_OPERATION_MODE - */ /*! @{ */ #define GMAC_MTL_OPERATION_MODE_DTXSTS_MASK EMAC_MTL_OPERATION_MODE_DTXSTS_MASK #define GMAC_MTL_OPERATION_MODE_DTXSTS_SHIFT EMAC_MTL_OPERATION_MODE_DTXSTS_SHIFT #define GMAC_MTL_OPERATION_MODE_DTXSTS_WIDTH EMAC_MTL_OPERATION_MODE_DTXSTS_WIDTH #define GMAC_MTL_OPERATION_MODE_DTXSTS(x) EMAC_MTL_OPERATION_MODE_DTXSTS(x) #define GMAC_MTL_OPERATION_MODE_RAA_MASK EMAC_MTL_OPERATION_MODE_RAA_MASK #define GMAC_MTL_OPERATION_MODE_RAA_SHIFT EMAC_MTL_OPERATION_MODE_RAA_SHIFT #define GMAC_MTL_OPERATION_MODE_RAA_WIDTH EMAC_MTL_OPERATION_MODE_RAA_WIDTH #define GMAC_MTL_OPERATION_MODE_RAA(x) EMAC_MTL_OPERATION_MODE_RAA(x) #define GMAC_MTL_OPERATION_MODE_SCHALG_MASK EMAC_MTL_OPERATION_MODE_SCHALG_MASK #define GMAC_MTL_OPERATION_MODE_SCHALG_SHIFT EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT #define GMAC_MTL_OPERATION_MODE_SCHALG_WIDTH EMAC_MTL_OPERATION_MODE_SCHALG_WIDTH #define GMAC_MTL_OPERATION_MODE_SCHALG(x) EMAC_MTL_OPERATION_MODE_SCHALG(x) #define GMAC_MTL_OPERATION_MODE_CNTPRST_MASK EMAC_MTL_OPERATION_MODE_CNTPRST_MASK #define GMAC_MTL_OPERATION_MODE_CNTPRST_SHIFT EMAC_MTL_OPERATION_MODE_CNTPRST_SHIFT #define GMAC_MTL_OPERATION_MODE_CNTPRST_WIDTH EMAC_MTL_OPERATION_MODE_CNTPRST_WIDTH #define GMAC_MTL_OPERATION_MODE_CNTPRST(x) EMAC_MTL_OPERATION_MODE_CNTPRST(x) #define GMAC_MTL_OPERATION_MODE_CNTCLR_MASK EMAC_MTL_OPERATION_MODE_CNTCLR_MASK #define GMAC_MTL_OPERATION_MODE_CNTCLR_SHIFT EMAC_MTL_OPERATION_MODE_CNTCLR_SHIFT #define GMAC_MTL_OPERATION_MODE_CNTCLR_WIDTH EMAC_MTL_OPERATION_MODE_CNTCLR_WIDTH #define GMAC_MTL_OPERATION_MODE_CNTCLR(x) EMAC_MTL_OPERATION_MODE_CNTCLR(x) #define GMAC_MTL_OPERATION_MODE_FRPE_MASK EMAC_MTL_OPERATION_MODE_FRPE_MASK #define GMAC_MTL_OPERATION_MODE_FRPE_SHIFT EMAC_MTL_OPERATION_MODE_FRPE_SHIFT #define GMAC_MTL_OPERATION_MODE_FRPE_WIDTH EMAC_MTL_OPERATION_MODE_FRPE_WIDTH #define GMAC_MTL_OPERATION_MODE_FRPE(x) EMAC_MTL_OPERATION_MODE_FRPE(x) /*! @} */ /*! @name MTL_DBG_CTL - */ /*! @{ */ #define GMAC_MTL_DBG_CTL_FDBGEN_MASK EMAC_MTL_DBG_CTL_FDBGEN_MASK #define GMAC_MTL_DBG_CTL_FDBGEN_SHIFT EMAC_MTL_DBG_CTL_FDBGEN_SHIFT #define GMAC_MTL_DBG_CTL_FDBGEN_WIDTH EMAC_MTL_DBG_CTL_FDBGEN_WIDTH #define GMAC_MTL_DBG_CTL_FDBGEN(x) EMAC_MTL_DBG_CTL_FDBGEN(x) #define GMAC_MTL_DBG_CTL_DBGMOD_MASK EMAC_MTL_DBG_CTL_DBGMOD_MASK #define GMAC_MTL_DBG_CTL_DBGMOD_SHIFT EMAC_MTL_DBG_CTL_DBGMOD_SHIFT #define GMAC_MTL_DBG_CTL_DBGMOD_WIDTH EMAC_MTL_DBG_CTL_DBGMOD_WIDTH #define GMAC_MTL_DBG_CTL_DBGMOD(x) EMAC_MTL_DBG_CTL_DBGMOD(x) #define GMAC_MTL_DBG_CTL_BYTEEN_MASK EMAC_MTL_DBG_CTL_BYTEEN_MASK #define GMAC_MTL_DBG_CTL_BYTEEN_SHIFT EMAC_MTL_DBG_CTL_BYTEEN_SHIFT #define GMAC_MTL_DBG_CTL_BYTEEN_WIDTH EMAC_MTL_DBG_CTL_BYTEEN_WIDTH #define GMAC_MTL_DBG_CTL_BYTEEN(x) EMAC_MTL_DBG_CTL_BYTEEN(x) #define GMAC_MTL_DBG_CTL_PKTSTATE_MASK EMAC_MTL_DBG_CTL_PKTSTATE_MASK #define GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT #define GMAC_MTL_DBG_CTL_PKTSTATE_WIDTH EMAC_MTL_DBG_CTL_PKTSTATE_WIDTH #define GMAC_MTL_DBG_CTL_PKTSTATE(x) EMAC_MTL_DBG_CTL_PKTSTATE(x) #define GMAC_MTL_DBG_CTL_RSTALL_MASK EMAC_MTL_DBG_CTL_RSTALL_MASK #define GMAC_MTL_DBG_CTL_RSTALL_SHIFT EMAC_MTL_DBG_CTL_RSTALL_SHIFT #define GMAC_MTL_DBG_CTL_RSTALL_WIDTH EMAC_MTL_DBG_CTL_RSTALL_WIDTH #define GMAC_MTL_DBG_CTL_RSTALL(x) EMAC_MTL_DBG_CTL_RSTALL(x) #define GMAC_MTL_DBG_CTL_RSTSEL_MASK EMAC_MTL_DBG_CTL_RSTSEL_MASK #define GMAC_MTL_DBG_CTL_RSTSEL_SHIFT EMAC_MTL_DBG_CTL_RSTSEL_SHIFT #define GMAC_MTL_DBG_CTL_RSTSEL_WIDTH EMAC_MTL_DBG_CTL_RSTSEL_WIDTH #define GMAC_MTL_DBG_CTL_RSTSEL(x) EMAC_MTL_DBG_CTL_RSTSEL(x) #define GMAC_MTL_DBG_CTL_FIFORDEN_MASK EMAC_MTL_DBG_CTL_FIFORDEN_MASK #define GMAC_MTL_DBG_CTL_FIFORDEN_SHIFT EMAC_MTL_DBG_CTL_FIFORDEN_SHIFT #define GMAC_MTL_DBG_CTL_FIFORDEN_WIDTH EMAC_MTL_DBG_CTL_FIFORDEN_WIDTH #define GMAC_MTL_DBG_CTL_FIFORDEN(x) EMAC_MTL_DBG_CTL_FIFORDEN(x) #define GMAC_MTL_DBG_CTL_FIFOWREN_MASK EMAC_MTL_DBG_CTL_FIFOWREN_MASK #define GMAC_MTL_DBG_CTL_FIFOWREN_SHIFT EMAC_MTL_DBG_CTL_FIFOWREN_SHIFT #define GMAC_MTL_DBG_CTL_FIFOWREN_WIDTH EMAC_MTL_DBG_CTL_FIFOWREN_WIDTH #define GMAC_MTL_DBG_CTL_FIFOWREN(x) EMAC_MTL_DBG_CTL_FIFOWREN(x) #define GMAC_MTL_DBG_CTL_FIFOSEL_MASK EMAC_MTL_DBG_CTL_FIFOSEL_MASK #define GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT #define GMAC_MTL_DBG_CTL_FIFOSEL_WIDTH EMAC_MTL_DBG_CTL_FIFOSEL_WIDTH #define GMAC_MTL_DBG_CTL_FIFOSEL(x) EMAC_MTL_DBG_CTL_FIFOSEL(x) #define GMAC_MTL_DBG_CTL_PKTIE_MASK EMAC_MTL_DBG_CTL_PKTIE_MASK #define GMAC_MTL_DBG_CTL_PKTIE_SHIFT EMAC_MTL_DBG_CTL_PKTIE_SHIFT #define GMAC_MTL_DBG_CTL_PKTIE_WIDTH EMAC_MTL_DBG_CTL_PKTIE_WIDTH #define GMAC_MTL_DBG_CTL_PKTIE(x) EMAC_MTL_DBG_CTL_PKTIE(x) #define GMAC_MTL_DBG_CTL_STSIE_MASK EMAC_MTL_DBG_CTL_STSIE_MASK #define GMAC_MTL_DBG_CTL_STSIE_SHIFT EMAC_MTL_DBG_CTL_STSIE_SHIFT #define GMAC_MTL_DBG_CTL_STSIE_WIDTH EMAC_MTL_DBG_CTL_STSIE_WIDTH #define GMAC_MTL_DBG_CTL_STSIE(x) EMAC_MTL_DBG_CTL_STSIE(x) #define GMAC_MTL_DBG_CTL_EIEE_MASK EMAC_MTL_DBG_CTL_EIEE_MASK #define GMAC_MTL_DBG_CTL_EIEE_SHIFT EMAC_MTL_DBG_CTL_EIEE_SHIFT #define GMAC_MTL_DBG_CTL_EIEE_WIDTH EMAC_MTL_DBG_CTL_EIEE_WIDTH #define GMAC_MTL_DBG_CTL_EIEE(x) EMAC_MTL_DBG_CTL_EIEE(x) #define GMAC_MTL_DBG_CTL_EIEC_MASK EMAC_MTL_DBG_CTL_EIEC_MASK #define GMAC_MTL_DBG_CTL_EIEC_SHIFT EMAC_MTL_DBG_CTL_EIEC_SHIFT #define GMAC_MTL_DBG_CTL_EIEC_WIDTH EMAC_MTL_DBG_CTL_EIEC_WIDTH #define GMAC_MTL_DBG_CTL_EIEC(x) EMAC_MTL_DBG_CTL_EIEC(x) /*! @} */ /*! @name MTL_DBG_STS - */ /*! @{ */ #define GMAC_MTL_DBG_STS_FIFOBUSY_MASK EMAC_MTL_DBG_STS_FIFOBUSY_MASK #define GMAC_MTL_DBG_STS_FIFOBUSY_SHIFT EMAC_MTL_DBG_STS_FIFOBUSY_SHIFT #define GMAC_MTL_DBG_STS_FIFOBUSY_WIDTH EMAC_MTL_DBG_STS_FIFOBUSY_WIDTH #define GMAC_MTL_DBG_STS_FIFOBUSY(x) EMAC_MTL_DBG_STS_FIFOBUSY(x) #define GMAC_MTL_DBG_STS_PKTSTATE_MASK EMAC_MTL_DBG_STS_PKTSTATE_MASK #define GMAC_MTL_DBG_STS_PKTSTATE_SHIFT EMAC_MTL_DBG_STS_PKTSTATE_SHIFT #define GMAC_MTL_DBG_STS_PKTSTATE_WIDTH EMAC_MTL_DBG_STS_PKTSTATE_WIDTH #define GMAC_MTL_DBG_STS_PKTSTATE(x) EMAC_MTL_DBG_STS_PKTSTATE(x) #define GMAC_MTL_DBG_STS_BYTEEN_MASK EMAC_MTL_DBG_STS_BYTEEN_MASK #define GMAC_MTL_DBG_STS_BYTEEN_SHIFT EMAC_MTL_DBG_STS_BYTEEN_SHIFT #define GMAC_MTL_DBG_STS_BYTEEN_WIDTH EMAC_MTL_DBG_STS_BYTEEN_WIDTH #define GMAC_MTL_DBG_STS_BYTEEN(x) EMAC_MTL_DBG_STS_BYTEEN(x) #define GMAC_MTL_DBG_STS_PKTI_MASK EMAC_MTL_DBG_STS_PKTI_MASK #define GMAC_MTL_DBG_STS_PKTI_SHIFT EMAC_MTL_DBG_STS_PKTI_SHIFT #define GMAC_MTL_DBG_STS_PKTI_WIDTH EMAC_MTL_DBG_STS_PKTI_WIDTH #define GMAC_MTL_DBG_STS_PKTI(x) EMAC_MTL_DBG_STS_PKTI(x) #define GMAC_MTL_DBG_STS_STSI_MASK EMAC_MTL_DBG_STS_STSI_MASK #define GMAC_MTL_DBG_STS_STSI_SHIFT EMAC_MTL_DBG_STS_STSI_SHIFT #define GMAC_MTL_DBG_STS_STSI_WIDTH EMAC_MTL_DBG_STS_STSI_WIDTH #define GMAC_MTL_DBG_STS_STSI(x) EMAC_MTL_DBG_STS_STSI(x) #define GMAC_MTL_DBG_STS_LOCR_MASK EMAC_MTL_DBG_STS_LOCR_MASK #define GMAC_MTL_DBG_STS_LOCR_SHIFT EMAC_MTL_DBG_STS_LOCR_SHIFT #define GMAC_MTL_DBG_STS_LOCR_WIDTH EMAC_MTL_DBG_STS_LOCR_WIDTH #define GMAC_MTL_DBG_STS_LOCR(x) EMAC_MTL_DBG_STS_LOCR(x) /*! @} */ /*! @name MTL_FIFO_DEBUG_DATA - */ /*! @{ */ #define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK #define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT #define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_WIDTH EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_WIDTH #define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) /*! @} */ /*! @name MTL_INTERRUPT_STATUS - */ /*! @{ */ #define GMAC_MTL_INTERRUPT_STATUS_Q0IS_MASK EMAC_MTL_INTERRUPT_STATUS_Q0IS_MASK #define GMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT EMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT #define GMAC_MTL_INTERRUPT_STATUS_Q0IS_WIDTH EMAC_MTL_INTERRUPT_STATUS_Q0IS_WIDTH #define GMAC_MTL_INTERRUPT_STATUS_Q0IS(x) EMAC_MTL_INTERRUPT_STATUS_Q0IS(x) #define GMAC_MTL_INTERRUPT_STATUS_Q1IS_MASK EMAC_MTL_INTERRUPT_STATUS_Q1IS_MASK #define GMAC_MTL_INTERRUPT_STATUS_Q1IS_SHIFT EMAC_MTL_INTERRUPT_STATUS_Q1IS_SHIFT #define GMAC_MTL_INTERRUPT_STATUS_Q1IS_WIDTH EMAC_MTL_INTERRUPT_STATUS_Q1IS_WIDTH #define GMAC_MTL_INTERRUPT_STATUS_Q1IS(x) EMAC_MTL_INTERRUPT_STATUS_Q1IS(x) #define GMAC_MTL_INTERRUPT_STATUS_DBGIS_MASK EMAC_MTL_INTERRUPT_STATUS_DBGIS_MASK #define GMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT EMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT #define GMAC_MTL_INTERRUPT_STATUS_DBGIS_WIDTH EMAC_MTL_INTERRUPT_STATUS_DBGIS_WIDTH #define GMAC_MTL_INTERRUPT_STATUS_DBGIS(x) EMAC_MTL_INTERRUPT_STATUS_DBGIS(x) #define GMAC_MTL_INTERRUPT_STATUS_ESTIS_MASK EMAC_MTL_INTERRUPT_STATUS_ESTIS_MASK #define GMAC_MTL_INTERRUPT_STATUS_ESTIS_SHIFT EMAC_MTL_INTERRUPT_STATUS_ESTIS_SHIFT #define GMAC_MTL_INTERRUPT_STATUS_ESTIS_WIDTH EMAC_MTL_INTERRUPT_STATUS_ESTIS_WIDTH #define GMAC_MTL_INTERRUPT_STATUS_ESTIS(x) EMAC_MTL_INTERRUPT_STATUS_ESTIS(x) #define GMAC_MTL_INTERRUPT_STATUS_MTLPIS_MASK EMAC_MTL_INTERRUPT_STATUS_MTLPIS_MASK #define GMAC_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT EMAC_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT #define GMAC_MTL_INTERRUPT_STATUS_MTLPIS_WIDTH EMAC_MTL_INTERRUPT_STATUS_MTLPIS_WIDTH #define GMAC_MTL_INTERRUPT_STATUS_MTLPIS(x) EMAC_MTL_INTERRUPT_STATUS_MTLPIS(x) /*! @} */ /*! @name MTL_RXQ_DMA_MAP0 - */ /*! @{ */ #define GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK #define GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT #define GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_WIDTH EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_WIDTH #define GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) #define GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK #define GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT #define GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_WIDTH EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_WIDTH #define GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) #define GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK #define GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT #define GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_WIDTH EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_WIDTH #define GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) #define GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK #define GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT #define GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_WIDTH EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_WIDTH #define GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) /*! @} */ /*! @name MTL_TBS_CTRL - */ /*! @{ */ #define GMAC_MTL_TBS_CTRL_ESTM_MASK EMAC_MTL_TBS_CTRL_ESTM_MASK #define GMAC_MTL_TBS_CTRL_ESTM_SHIFT EMAC_MTL_TBS_CTRL_ESTM_SHIFT #define GMAC_MTL_TBS_CTRL_ESTM_WIDTH EMAC_MTL_TBS_CTRL_ESTM_WIDTH #define GMAC_MTL_TBS_CTRL_ESTM(x) EMAC_MTL_TBS_CTRL_ESTM(x) #define GMAC_MTL_TBS_CTRL_LEOV_MASK EMAC_MTL_TBS_CTRL_LEOV_MASK #define GMAC_MTL_TBS_CTRL_LEOV_SHIFT EMAC_MTL_TBS_CTRL_LEOV_SHIFT #define GMAC_MTL_TBS_CTRL_LEOV_WIDTH EMAC_MTL_TBS_CTRL_LEOV_WIDTH #define GMAC_MTL_TBS_CTRL_LEOV(x) EMAC_MTL_TBS_CTRL_LEOV(x) #define GMAC_MTL_TBS_CTRL_LEGOS_MASK EMAC_MTL_TBS_CTRL_LEGOS_MASK #define GMAC_MTL_TBS_CTRL_LEGOS_SHIFT EMAC_MTL_TBS_CTRL_LEGOS_SHIFT #define GMAC_MTL_TBS_CTRL_LEGOS_WIDTH EMAC_MTL_TBS_CTRL_LEGOS_WIDTH #define GMAC_MTL_TBS_CTRL_LEGOS(x) EMAC_MTL_TBS_CTRL_LEGOS(x) #define GMAC_MTL_TBS_CTRL_LEOS_MASK EMAC_MTL_TBS_CTRL_LEOS_MASK #define GMAC_MTL_TBS_CTRL_LEOS_SHIFT EMAC_MTL_TBS_CTRL_LEOS_SHIFT #define GMAC_MTL_TBS_CTRL_LEOS_WIDTH EMAC_MTL_TBS_CTRL_LEOS_WIDTH #define GMAC_MTL_TBS_CTRL_LEOS(x) EMAC_MTL_TBS_CTRL_LEOS(x) /*! @} */ /*! @name MTL_EST_CONTROL - */ /*! @{ */ #define GMAC_MTL_EST_CONTROL_EEST_MASK EMAC_MTL_EST_CONTROL_EEST_MASK #define GMAC_MTL_EST_CONTROL_EEST_SHIFT EMAC_MTL_EST_CONTROL_EEST_SHIFT #define GMAC_MTL_EST_CONTROL_EEST_WIDTH EMAC_MTL_EST_CONTROL_EEST_WIDTH #define GMAC_MTL_EST_CONTROL_EEST(x) EMAC_MTL_EST_CONTROL_EEST(x) #define GMAC_MTL_EST_CONTROL_SSWL_MASK EMAC_MTL_EST_CONTROL_SSWL_MASK #define GMAC_MTL_EST_CONTROL_SSWL_SHIFT EMAC_MTL_EST_CONTROL_SSWL_SHIFT #define GMAC_MTL_EST_CONTROL_SSWL_WIDTH EMAC_MTL_EST_CONTROL_SSWL_WIDTH #define GMAC_MTL_EST_CONTROL_SSWL(x) EMAC_MTL_EST_CONTROL_SSWL(x) #define GMAC_MTL_EST_CONTROL_DDBF_MASK EMAC_MTL_EST_CONTROL_DDBF_MASK #define GMAC_MTL_EST_CONTROL_DDBF_SHIFT EMAC_MTL_EST_CONTROL_DDBF_SHIFT #define GMAC_MTL_EST_CONTROL_DDBF_WIDTH EMAC_MTL_EST_CONTROL_DDBF_WIDTH #define GMAC_MTL_EST_CONTROL_DDBF(x) EMAC_MTL_EST_CONTROL_DDBF(x) #define GMAC_MTL_EST_CONTROL_DFBS_MASK EMAC_MTL_EST_CONTROL_DFBS_MASK #define GMAC_MTL_EST_CONTROL_DFBS_SHIFT EMAC_MTL_EST_CONTROL_DFBS_SHIFT #define GMAC_MTL_EST_CONTROL_DFBS_WIDTH EMAC_MTL_EST_CONTROL_DFBS_WIDTH #define GMAC_MTL_EST_CONTROL_DFBS(x) EMAC_MTL_EST_CONTROL_DFBS(x) #define GMAC_MTL_EST_CONTROL_LCSE_MASK EMAC_MTL_EST_CONTROL_LCSE_MASK #define GMAC_MTL_EST_CONTROL_LCSE_SHIFT EMAC_MTL_EST_CONTROL_LCSE_SHIFT #define GMAC_MTL_EST_CONTROL_LCSE_WIDTH EMAC_MTL_EST_CONTROL_LCSE_WIDTH #define GMAC_MTL_EST_CONTROL_LCSE(x) EMAC_MTL_EST_CONTROL_LCSE(x) #define GMAC_MTL_EST_CONTROL_TILS_MASK EMAC_MTL_EST_CONTROL_TILS_MASK #define GMAC_MTL_EST_CONTROL_TILS_SHIFT EMAC_MTL_EST_CONTROL_TILS_SHIFT #define GMAC_MTL_EST_CONTROL_TILS_WIDTH EMAC_MTL_EST_CONTROL_TILS_WIDTH #define GMAC_MTL_EST_CONTROL_TILS(x) EMAC_MTL_EST_CONTROL_TILS(x) #define GMAC_MTL_EST_CONTROL_CTOV_MASK EMAC_MTL_EST_CONTROL_CTOV_MASK #define GMAC_MTL_EST_CONTROL_CTOV_SHIFT EMAC_MTL_EST_CONTROL_CTOV_SHIFT #define GMAC_MTL_EST_CONTROL_CTOV_WIDTH EMAC_MTL_EST_CONTROL_CTOV_WIDTH #define GMAC_MTL_EST_CONTROL_CTOV(x) EMAC_MTL_EST_CONTROL_CTOV(x) #define GMAC_MTL_EST_CONTROL_PTOV_MASK EMAC_MTL_EST_CONTROL_PTOV_MASK #define GMAC_MTL_EST_CONTROL_PTOV_SHIFT EMAC_MTL_EST_CONTROL_PTOV_SHIFT #define GMAC_MTL_EST_CONTROL_PTOV_WIDTH EMAC_MTL_EST_CONTROL_PTOV_WIDTH #define GMAC_MTL_EST_CONTROL_PTOV(x) EMAC_MTL_EST_CONTROL_PTOV(x) /*! @} */ /*! @name MTL_EST_STATUS - */ /*! @{ */ #define GMAC_MTL_EST_STATUS_SWLC_MASK EMAC_MTL_EST_STATUS_SWLC_MASK #define GMAC_MTL_EST_STATUS_SWLC_SHIFT EMAC_MTL_EST_STATUS_SWLC_SHIFT #define GMAC_MTL_EST_STATUS_SWLC_WIDTH EMAC_MTL_EST_STATUS_SWLC_WIDTH #define GMAC_MTL_EST_STATUS_SWLC(x) EMAC_MTL_EST_STATUS_SWLC(x) #define GMAC_MTL_EST_STATUS_BTRE_MASK EMAC_MTL_EST_STATUS_BTRE_MASK #define GMAC_MTL_EST_STATUS_BTRE_SHIFT EMAC_MTL_EST_STATUS_BTRE_SHIFT #define GMAC_MTL_EST_STATUS_BTRE_WIDTH EMAC_MTL_EST_STATUS_BTRE_WIDTH #define GMAC_MTL_EST_STATUS_BTRE(x) EMAC_MTL_EST_STATUS_BTRE(x) #define GMAC_MTL_EST_STATUS_HLBF_MASK EMAC_MTL_EST_STATUS_HLBF_MASK #define GMAC_MTL_EST_STATUS_HLBF_SHIFT EMAC_MTL_EST_STATUS_HLBF_SHIFT #define GMAC_MTL_EST_STATUS_HLBF_WIDTH EMAC_MTL_EST_STATUS_HLBF_WIDTH #define GMAC_MTL_EST_STATUS_HLBF(x) EMAC_MTL_EST_STATUS_HLBF(x) #define GMAC_MTL_EST_STATUS_HLBS_MASK EMAC_MTL_EST_STATUS_HLBS_MASK #define GMAC_MTL_EST_STATUS_HLBS_SHIFT EMAC_MTL_EST_STATUS_HLBS_SHIFT #define GMAC_MTL_EST_STATUS_HLBS_WIDTH EMAC_MTL_EST_STATUS_HLBS_WIDTH #define GMAC_MTL_EST_STATUS_HLBS(x) EMAC_MTL_EST_STATUS_HLBS(x) #define GMAC_MTL_EST_STATUS_CGCE_MASK EMAC_MTL_EST_STATUS_CGCE_MASK #define GMAC_MTL_EST_STATUS_CGCE_SHIFT EMAC_MTL_EST_STATUS_CGCE_SHIFT #define GMAC_MTL_EST_STATUS_CGCE_WIDTH EMAC_MTL_EST_STATUS_CGCE_WIDTH #define GMAC_MTL_EST_STATUS_CGCE(x) EMAC_MTL_EST_STATUS_CGCE(x) #define GMAC_MTL_EST_STATUS_SWOL_MASK EMAC_MTL_EST_STATUS_SWOL_MASK #define GMAC_MTL_EST_STATUS_SWOL_SHIFT EMAC_MTL_EST_STATUS_SWOL_SHIFT #define GMAC_MTL_EST_STATUS_SWOL_WIDTH EMAC_MTL_EST_STATUS_SWOL_WIDTH #define GMAC_MTL_EST_STATUS_SWOL(x) EMAC_MTL_EST_STATUS_SWOL(x) #define GMAC_MTL_EST_STATUS_BTRL_MASK EMAC_MTL_EST_STATUS_BTRL_MASK #define GMAC_MTL_EST_STATUS_BTRL_SHIFT EMAC_MTL_EST_STATUS_BTRL_SHIFT #define GMAC_MTL_EST_STATUS_BTRL_WIDTH EMAC_MTL_EST_STATUS_BTRL_WIDTH #define GMAC_MTL_EST_STATUS_BTRL(x) EMAC_MTL_EST_STATUS_BTRL(x) #define GMAC_MTL_EST_STATUS_CGSN_MASK EMAC_MTL_EST_STATUS_CGSN_MASK #define GMAC_MTL_EST_STATUS_CGSN_SHIFT EMAC_MTL_EST_STATUS_CGSN_SHIFT #define GMAC_MTL_EST_STATUS_CGSN_WIDTH EMAC_MTL_EST_STATUS_CGSN_WIDTH #define GMAC_MTL_EST_STATUS_CGSN(x) EMAC_MTL_EST_STATUS_CGSN(x) /*! @} */ /*! @name MTL_EST_SCH_ERROR - */ /*! @{ */ #define GMAC_MTL_EST_SCH_ERROR_SEQN_MASK EMAC_MTL_EST_SCH_ERROR_SEQN_MASK #define GMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT #define GMAC_MTL_EST_SCH_ERROR_SEQN_WIDTH EMAC_MTL_EST_SCH_ERROR_SEQN_WIDTH #define GMAC_MTL_EST_SCH_ERROR_SEQN(x) EMAC_MTL_EST_SCH_ERROR_SEQN(x) /*! @} */ /*! @name MTL_EST_FRM_SIZE_ERROR - */ /*! @{ */ #define GMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK #define GMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT #define GMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_WIDTH EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_WIDTH #define GMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(x) EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(x) /*! @} */ /*! @name MTL_EST_FRM_SIZE_CAPTURE - */ /*! @{ */ #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_WIDTH EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_WIDTH #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_WIDTH EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_WIDTH #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) /*! @} */ /*! @name MTL_EST_INTR_ENABLE - */ /*! @{ */ #define GMAC_MTL_EST_INTR_ENABLE_IECC_MASK EMAC_MTL_EST_INTR_ENABLE_IECC_MASK #define GMAC_MTL_EST_INTR_ENABLE_IECC_SHIFT EMAC_MTL_EST_INTR_ENABLE_IECC_SHIFT #define GMAC_MTL_EST_INTR_ENABLE_IECC_WIDTH EMAC_MTL_EST_INTR_ENABLE_IECC_WIDTH #define GMAC_MTL_EST_INTR_ENABLE_IECC(x) EMAC_MTL_EST_INTR_ENABLE_IECC(x) #define GMAC_MTL_EST_INTR_ENABLE_IEBE_MASK EMAC_MTL_EST_INTR_ENABLE_IEBE_MASK #define GMAC_MTL_EST_INTR_ENABLE_IEBE_SHIFT EMAC_MTL_EST_INTR_ENABLE_IEBE_SHIFT #define GMAC_MTL_EST_INTR_ENABLE_IEBE_WIDTH EMAC_MTL_EST_INTR_ENABLE_IEBE_WIDTH #define GMAC_MTL_EST_INTR_ENABLE_IEBE(x) EMAC_MTL_EST_INTR_ENABLE_IEBE(x) #define GMAC_MTL_EST_INTR_ENABLE_IEHF_MASK EMAC_MTL_EST_INTR_ENABLE_IEHF_MASK #define GMAC_MTL_EST_INTR_ENABLE_IEHF_SHIFT EMAC_MTL_EST_INTR_ENABLE_IEHF_SHIFT #define GMAC_MTL_EST_INTR_ENABLE_IEHF_WIDTH EMAC_MTL_EST_INTR_ENABLE_IEHF_WIDTH #define GMAC_MTL_EST_INTR_ENABLE_IEHF(x) EMAC_MTL_EST_INTR_ENABLE_IEHF(x) #define GMAC_MTL_EST_INTR_ENABLE_IEHS_MASK EMAC_MTL_EST_INTR_ENABLE_IEHS_MASK #define GMAC_MTL_EST_INTR_ENABLE_IEHS_SHIFT EMAC_MTL_EST_INTR_ENABLE_IEHS_SHIFT #define GMAC_MTL_EST_INTR_ENABLE_IEHS_WIDTH EMAC_MTL_EST_INTR_ENABLE_IEHS_WIDTH #define GMAC_MTL_EST_INTR_ENABLE_IEHS(x) EMAC_MTL_EST_INTR_ENABLE_IEHS(x) #define GMAC_MTL_EST_INTR_ENABLE_CGCE_MASK EMAC_MTL_EST_INTR_ENABLE_CGCE_MASK #define GMAC_MTL_EST_INTR_ENABLE_CGCE_SHIFT EMAC_MTL_EST_INTR_ENABLE_CGCE_SHIFT #define GMAC_MTL_EST_INTR_ENABLE_CGCE_WIDTH EMAC_MTL_EST_INTR_ENABLE_CGCE_WIDTH #define GMAC_MTL_EST_INTR_ENABLE_CGCE(x) EMAC_MTL_EST_INTR_ENABLE_CGCE(x) /*! @} */ /*! @name MTL_EST_GCL_CONTROL - */ /*! @{ */ #define GMAC_MTL_EST_GCL_CONTROL_SRWO_MASK EMAC_MTL_EST_GCL_CONTROL_SRWO_MASK #define GMAC_MTL_EST_GCL_CONTROL_SRWO_SHIFT EMAC_MTL_EST_GCL_CONTROL_SRWO_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_SRWO_WIDTH EMAC_MTL_EST_GCL_CONTROL_SRWO_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_SRWO(x) EMAC_MTL_EST_GCL_CONTROL_SRWO(x) #define GMAC_MTL_EST_GCL_CONTROL_R1W0_MASK EMAC_MTL_EST_GCL_CONTROL_R1W0_MASK #define GMAC_MTL_EST_GCL_CONTROL_R1W0_SHIFT EMAC_MTL_EST_GCL_CONTROL_R1W0_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_R1W0_WIDTH EMAC_MTL_EST_GCL_CONTROL_R1W0_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_R1W0(x) EMAC_MTL_EST_GCL_CONTROL_R1W0(x) #define GMAC_MTL_EST_GCL_CONTROL_GCRR_MASK EMAC_MTL_EST_GCL_CONTROL_GCRR_MASK #define GMAC_MTL_EST_GCL_CONTROL_GCRR_SHIFT EMAC_MTL_EST_GCL_CONTROL_GCRR_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_GCRR_WIDTH EMAC_MTL_EST_GCL_CONTROL_GCRR_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_GCRR(x) EMAC_MTL_EST_GCL_CONTROL_GCRR(x) #define GMAC_MTL_EST_GCL_CONTROL_DBGM_MASK EMAC_MTL_EST_GCL_CONTROL_DBGM_MASK #define GMAC_MTL_EST_GCL_CONTROL_DBGM_SHIFT EMAC_MTL_EST_GCL_CONTROL_DBGM_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_DBGM_WIDTH EMAC_MTL_EST_GCL_CONTROL_DBGM_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_DBGM(x) EMAC_MTL_EST_GCL_CONTROL_DBGM(x) #define GMAC_MTL_EST_GCL_CONTROL_DBGB_MASK EMAC_MTL_EST_GCL_CONTROL_DBGB_MASK #define GMAC_MTL_EST_GCL_CONTROL_DBGB_SHIFT EMAC_MTL_EST_GCL_CONTROL_DBGB_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_DBGB_WIDTH EMAC_MTL_EST_GCL_CONTROL_DBGB_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_DBGB(x) EMAC_MTL_EST_GCL_CONTROL_DBGB(x) #define GMAC_MTL_EST_GCL_CONTROL_ADDR_MASK EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK #define GMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_ADDR_WIDTH EMAC_MTL_EST_GCL_CONTROL_ADDR_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_ADDR(x) EMAC_MTL_EST_GCL_CONTROL_ADDR(x) #define GMAC_MTL_EST_GCL_CONTROL_ERR0_MASK EMAC_MTL_EST_GCL_CONTROL_ERR0_MASK #define GMAC_MTL_EST_GCL_CONTROL_ERR0_SHIFT EMAC_MTL_EST_GCL_CONTROL_ERR0_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_ERR0_WIDTH EMAC_MTL_EST_GCL_CONTROL_ERR0_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_ERR0(x) EMAC_MTL_EST_GCL_CONTROL_ERR0(x) #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEE_MASK EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_MASK #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEE_WIDTH EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEE(x) EMAC_MTL_EST_GCL_CONTROL_ESTEIEE(x) #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEC_WIDTH EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_WIDTH #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEC(x) EMAC_MTL_EST_GCL_CONTROL_ESTEIEC(x) /*! @} */ /*! @name MTL_EST_GCL_DATA - */ /*! @{ */ #define GMAC_MTL_EST_GCL_DATA_GCD_MASK EMAC_MTL_EST_GCL_DATA_GCD_MASK #define GMAC_MTL_EST_GCL_DATA_GCD_SHIFT EMAC_MTL_EST_GCL_DATA_GCD_SHIFT #define GMAC_MTL_EST_GCL_DATA_GCD_WIDTH EMAC_MTL_EST_GCL_DATA_GCD_WIDTH #define GMAC_MTL_EST_GCL_DATA_GCD(x) EMAC_MTL_EST_GCL_DATA_GCD(x) /*! @} */ /*! @name MTL_FPE_CTRL_STS - */ /*! @{ */ #define GMAC_MTL_FPE_CTRL_STS_AFSZ_MASK EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK #define GMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT #define GMAC_MTL_FPE_CTRL_STS_AFSZ_WIDTH EMAC_MTL_FPE_CTRL_STS_AFSZ_WIDTH #define GMAC_MTL_FPE_CTRL_STS_AFSZ(x) EMAC_MTL_FPE_CTRL_STS_AFSZ(x) #define GMAC_MTL_FPE_CTRL_STS_PEC_MASK EMAC_MTL_FPE_CTRL_STS_PEC_MASK #define GMAC_MTL_FPE_CTRL_STS_PEC_SHIFT EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT #define GMAC_MTL_FPE_CTRL_STS_PEC_WIDTH EMAC_MTL_FPE_CTRL_STS_PEC_WIDTH #define GMAC_MTL_FPE_CTRL_STS_PEC(x) EMAC_MTL_FPE_CTRL_STS_PEC(x) #define GMAC_MTL_FPE_CTRL_STS_HRS_MASK EMAC_MTL_FPE_CTRL_STS_HRS_MASK #define GMAC_MTL_FPE_CTRL_STS_HRS_SHIFT EMAC_MTL_FPE_CTRL_STS_HRS_SHIFT #define GMAC_MTL_FPE_CTRL_STS_HRS_WIDTH EMAC_MTL_FPE_CTRL_STS_HRS_WIDTH #define GMAC_MTL_FPE_CTRL_STS_HRS(x) EMAC_MTL_FPE_CTRL_STS_HRS(x) /*! @} */ /*! @name MTL_FPE_ADVANCE - */ /*! @{ */ #define GMAC_MTL_FPE_ADVANCE_HADV_MASK EMAC_MTL_FPE_ADVANCE_HADV_MASK #define GMAC_MTL_FPE_ADVANCE_HADV_SHIFT EMAC_MTL_FPE_ADVANCE_HADV_SHIFT #define GMAC_MTL_FPE_ADVANCE_HADV_WIDTH EMAC_MTL_FPE_ADVANCE_HADV_WIDTH #define GMAC_MTL_FPE_ADVANCE_HADV(x) EMAC_MTL_FPE_ADVANCE_HADV(x) #define GMAC_MTL_FPE_ADVANCE_RADV_MASK EMAC_MTL_FPE_ADVANCE_RADV_MASK #define GMAC_MTL_FPE_ADVANCE_RADV_SHIFT EMAC_MTL_FPE_ADVANCE_RADV_SHIFT #define GMAC_MTL_FPE_ADVANCE_RADV_WIDTH EMAC_MTL_FPE_ADVANCE_RADV_WIDTH #define GMAC_MTL_FPE_ADVANCE_RADV(x) EMAC_MTL_FPE_ADVANCE_RADV(x) /*! @} */ /*! @name MTL_RXP_CONTROL_STATUS - */ /*! @{ */ #define GMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK #define GMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT #define GMAC_MTL_RXP_CONTROL_STATUS_NVE_WIDTH EMAC_MTL_RXP_CONTROL_STATUS_NVE_WIDTH #define GMAC_MTL_RXP_CONTROL_STATUS_NVE(x) EMAC_MTL_RXP_CONTROL_STATUS_NVE(x) #define GMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_MASK EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_MASK #define GMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_SHIFT EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_SHIFT #define GMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_WIDTH EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_WIDTH #define GMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1(x) EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1(x) #define GMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK #define GMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT #define GMAC_MTL_RXP_CONTROL_STATUS_NPE_WIDTH EMAC_MTL_RXP_CONTROL_STATUS_NPE_WIDTH #define GMAC_MTL_RXP_CONTROL_STATUS_NPE(x) EMAC_MTL_RXP_CONTROL_STATUS_NPE(x) #define GMAC_MTL_RXP_CONTROL_STATUS_RXPI_MASK EMAC_MTL_RXP_CONTROL_STATUS_RXPI_MASK #define GMAC_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT EMAC_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT #define GMAC_MTL_RXP_CONTROL_STATUS_RXPI_WIDTH EMAC_MTL_RXP_CONTROL_STATUS_RXPI_WIDTH #define GMAC_MTL_RXP_CONTROL_STATUS_RXPI(x) EMAC_MTL_RXP_CONTROL_STATUS_RXPI(x) /*! @} */ /*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - */ /*! @{ */ #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_WIDTH #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_WIDTH #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_WIDTH #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_WIDTH #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_WIDTH #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_WIDTH #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_WIDTH #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_WIDTH #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) /*! @} */ /*! @name MTL_RXP_DROP_CNT - */ /*! @{ */ #define GMAC_MTL_RXP_DROP_CNT_RXPDC_MASK EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK #define GMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT #define GMAC_MTL_RXP_DROP_CNT_RXPDC_WIDTH EMAC_MTL_RXP_DROP_CNT_RXPDC_WIDTH #define GMAC_MTL_RXP_DROP_CNT_RXPDC(x) EMAC_MTL_RXP_DROP_CNT_RXPDC(x) #define GMAC_MTL_RXP_DROP_CNT_RXPDCOVF_MASK EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_MASK #define GMAC_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT #define GMAC_MTL_RXP_DROP_CNT_RXPDCOVF_WIDTH EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_WIDTH #define GMAC_MTL_RXP_DROP_CNT_RXPDCOVF(x) EMAC_MTL_RXP_DROP_CNT_RXPDCOVF(x) /*! @} */ /*! @name MTL_RXP_ERROR_CNT - */ /*! @{ */ #define GMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK #define GMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT #define GMAC_MTL_RXP_ERROR_CNT_RXPEC_WIDTH EMAC_MTL_RXP_ERROR_CNT_RXPEC_WIDTH #define GMAC_MTL_RXP_ERROR_CNT_RXPEC(x) EMAC_MTL_RXP_ERROR_CNT_RXPEC(x) #define GMAC_MTL_RXP_ERROR_CNT_RXPECOVF_MASK EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_MASK #define GMAC_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT #define GMAC_MTL_RXP_ERROR_CNT_RXPECOVF_WIDTH EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_WIDTH #define GMAC_MTL_RXP_ERROR_CNT_RXPECOVF(x) EMAC_MTL_RXP_ERROR_CNT_RXPECOVF(x) /*! @} */ /*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - */ /*! @{ */ #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_WIDTH #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_WIDTH #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_MASK #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_SHIFT #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_WIDTH #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE(x) #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_WIDTH #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(x) #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_WIDTH #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) /*! @} */ /*! @name MTL_RXP_INDIRECT_ACC_DATA - */ /*! @{ */ #define GMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK #define GMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT #define GMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_WIDTH #define GMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) /*! @} */ /*! @name MTL_ECC_CONTROL - */ /*! @{ */ #define GMAC_MTL_ECC_CONTROL_MTXEE_MASK EMAC_MTL_ECC_CONTROL_MTXEE_MASK #define GMAC_MTL_ECC_CONTROL_MTXEE_SHIFT EMAC_MTL_ECC_CONTROL_MTXEE_SHIFT #define GMAC_MTL_ECC_CONTROL_MTXEE_WIDTH EMAC_MTL_ECC_CONTROL_MTXEE_WIDTH #define GMAC_MTL_ECC_CONTROL_MTXEE(x) EMAC_MTL_ECC_CONTROL_MTXEE(x) #define GMAC_MTL_ECC_CONTROL_MRXEE_MASK EMAC_MTL_ECC_CONTROL_MRXEE_MASK #define GMAC_MTL_ECC_CONTROL_MRXEE_SHIFT EMAC_MTL_ECC_CONTROL_MRXEE_SHIFT #define GMAC_MTL_ECC_CONTROL_MRXEE_WIDTH EMAC_MTL_ECC_CONTROL_MRXEE_WIDTH #define GMAC_MTL_ECC_CONTROL_MRXEE(x) EMAC_MTL_ECC_CONTROL_MRXEE(x) #define GMAC_MTL_ECC_CONTROL_MESTEE_MASK EMAC_MTL_ECC_CONTROL_MESTEE_MASK #define GMAC_MTL_ECC_CONTROL_MESTEE_SHIFT EMAC_MTL_ECC_CONTROL_MESTEE_SHIFT #define GMAC_MTL_ECC_CONTROL_MESTEE_WIDTH EMAC_MTL_ECC_CONTROL_MESTEE_WIDTH #define GMAC_MTL_ECC_CONTROL_MESTEE(x) EMAC_MTL_ECC_CONTROL_MESTEE(x) #define GMAC_MTL_ECC_CONTROL_MRXPEE_MASK EMAC_MTL_ECC_CONTROL_MRXPEE_MASK #define GMAC_MTL_ECC_CONTROL_MRXPEE_SHIFT EMAC_MTL_ECC_CONTROL_MRXPEE_SHIFT #define GMAC_MTL_ECC_CONTROL_MRXPEE_WIDTH EMAC_MTL_ECC_CONTROL_MRXPEE_WIDTH #define GMAC_MTL_ECC_CONTROL_MRXPEE(x) EMAC_MTL_ECC_CONTROL_MRXPEE(x) #define GMAC_MTL_ECC_CONTROL_MEEAO_MASK EMAC_MTL_ECC_CONTROL_MEEAO_MASK #define GMAC_MTL_ECC_CONTROL_MEEAO_SHIFT EMAC_MTL_ECC_CONTROL_MEEAO_SHIFT #define GMAC_MTL_ECC_CONTROL_MEEAO_WIDTH EMAC_MTL_ECC_CONTROL_MEEAO_WIDTH #define GMAC_MTL_ECC_CONTROL_MEEAO(x) EMAC_MTL_ECC_CONTROL_MEEAO(x) /*! @} */ /*! @name MTL_SAFETY_INTERRUPT_STATUS - */ /*! @{ */ #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_MASK EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_MASK #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_SHIFT EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_SHIFT #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_WIDTH EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_WIDTH #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS(x) EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS(x) #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_MASK EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_MASK #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_SHIFT EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_SHIFT #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_WIDTH EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_WIDTH #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS(x) EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS(x) /*! @} */ /*! @name MTL_ECC_INTERRUPT_ENABLE - */ /*! @{ */ #define GMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_MASK EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_MASK #define GMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_SHIFT EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_SHIFT #define GMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_WIDTH EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_WIDTH #define GMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE(x) EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE(x) #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_MASK EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_MASK #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_SHIFT EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_SHIFT #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_WIDTH EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_WIDTH #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE(x) EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE(x) #define GMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_MASK EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_MASK #define GMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_SHIFT EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_SHIFT #define GMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_WIDTH EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_WIDTH #define GMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE(x) EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE(x) #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_MASK EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_MASK #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_SHIFT EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_SHIFT #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_WIDTH EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_WIDTH #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE(x) EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE(x) /*! @} */ /*! @name MTL_ECC_INTERRUPT_STATUS - */ /*! @{ */ #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXCES(x) EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS(x) EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES(x) EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXCES(x) EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS(x) EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES(x) EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_ECES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_ECES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_ECES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_ECES(x) EMAC_MTL_ECC_INTERRUPT_STATUS_ECES(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS(x) EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_EUES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_EUES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_EUES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_EUES(x) EMAC_MTL_ECC_INTERRUPT_STATUS_EUES(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPCES(x) EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS(x) EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS(x) #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_MASK #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_SHIFT #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_WIDTH #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPUES(x) EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES(x) /*! @} */ /*! @name MTL_ECC_ERR_STS_RCTL - */ /*! @{ */ #define GMAC_MTL_ECC_ERR_STS_RCTL_EESRE_MASK EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_MASK #define GMAC_MTL_ECC_ERR_STS_RCTL_EESRE_SHIFT EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_SHIFT #define GMAC_MTL_ECC_ERR_STS_RCTL_EESRE_WIDTH EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_WIDTH #define GMAC_MTL_ECC_ERR_STS_RCTL_EESRE(x) EMAC_MTL_ECC_ERR_STS_RCTL_EESRE(x) #define GMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK #define GMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT #define GMAC_MTL_ECC_ERR_STS_RCTL_EMS_WIDTH EMAC_MTL_ECC_ERR_STS_RCTL_EMS_WIDTH #define GMAC_MTL_ECC_ERR_STS_RCTL_EMS(x) EMAC_MTL_ECC_ERR_STS_RCTL_EMS(x) #define GMAC_MTL_ECC_ERR_STS_RCTL_CCES_MASK EMAC_MTL_ECC_ERR_STS_RCTL_CCES_MASK #define GMAC_MTL_ECC_ERR_STS_RCTL_CCES_SHIFT EMAC_MTL_ECC_ERR_STS_RCTL_CCES_SHIFT #define GMAC_MTL_ECC_ERR_STS_RCTL_CCES_WIDTH EMAC_MTL_ECC_ERR_STS_RCTL_CCES_WIDTH #define GMAC_MTL_ECC_ERR_STS_RCTL_CCES(x) EMAC_MTL_ECC_ERR_STS_RCTL_CCES(x) #define GMAC_MTL_ECC_ERR_STS_RCTL_CUES_MASK EMAC_MTL_ECC_ERR_STS_RCTL_CUES_MASK #define GMAC_MTL_ECC_ERR_STS_RCTL_CUES_SHIFT EMAC_MTL_ECC_ERR_STS_RCTL_CUES_SHIFT #define GMAC_MTL_ECC_ERR_STS_RCTL_CUES_WIDTH EMAC_MTL_ECC_ERR_STS_RCTL_CUES_WIDTH #define GMAC_MTL_ECC_ERR_STS_RCTL_CUES(x) EMAC_MTL_ECC_ERR_STS_RCTL_CUES(x) /*! @} */ /*! @name MTL_ECC_ERR_ADDR_STATUS - */ /*! @{ */ #define GMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK #define GMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT #define GMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_WIDTH EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_WIDTH #define GMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(x) EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(x) #define GMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK #define GMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT #define GMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_WIDTH EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_WIDTH #define GMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(x) EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(x) /*! @} */ /*! @name MTL_ECC_ERR_CNTR_STATUS - */ /*! @{ */ #define GMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK #define GMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT #define GMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_WIDTH EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_WIDTH #define GMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(x) EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(x) #define GMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK #define GMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT #define GMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_WIDTH EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_WIDTH #define GMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(x) EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(x) /*! @} */ /*! @name MTL_DPP_CONTROL - */ /*! @{ */ #define GMAC_MTL_DPP_CONTROL_EDPP_MASK EMAC_MTL_DPP_CONTROL_EDPP_MASK #define GMAC_MTL_DPP_CONTROL_EDPP_SHIFT EMAC_MTL_DPP_CONTROL_EDPP_SHIFT #define GMAC_MTL_DPP_CONTROL_EDPP_WIDTH EMAC_MTL_DPP_CONTROL_EDPP_WIDTH #define GMAC_MTL_DPP_CONTROL_EDPP(x) EMAC_MTL_DPP_CONTROL_EDPP(x) #define GMAC_MTL_DPP_CONTROL_OPE_MASK EMAC_MTL_DPP_CONTROL_OPE_MASK #define GMAC_MTL_DPP_CONTROL_OPE_SHIFT EMAC_MTL_DPP_CONTROL_OPE_SHIFT #define GMAC_MTL_DPP_CONTROL_OPE_WIDTH EMAC_MTL_DPP_CONTROL_OPE_WIDTH #define GMAC_MTL_DPP_CONTROL_OPE(x) EMAC_MTL_DPP_CONTROL_OPE(x) #define GMAC_MTL_DPP_CONTROL_IPEID_MASK EMAC_MTL_DPP_CONTROL_IPEID_MASK #define GMAC_MTL_DPP_CONTROL_IPEID_SHIFT EMAC_MTL_DPP_CONTROL_IPEID_SHIFT #define GMAC_MTL_DPP_CONTROL_IPEID_WIDTH EMAC_MTL_DPP_CONTROL_IPEID_WIDTH #define GMAC_MTL_DPP_CONTROL_IPEID(x) EMAC_MTL_DPP_CONTROL_IPEID(x) #define GMAC_MTL_DPP_CONTROL_IPEMC_MASK EMAC_MTL_DPP_CONTROL_IPEMC_MASK #define GMAC_MTL_DPP_CONTROL_IPEMC_SHIFT EMAC_MTL_DPP_CONTROL_IPEMC_SHIFT #define GMAC_MTL_DPP_CONTROL_IPEMC_WIDTH EMAC_MTL_DPP_CONTROL_IPEMC_WIDTH #define GMAC_MTL_DPP_CONTROL_IPEMC(x) EMAC_MTL_DPP_CONTROL_IPEMC(x) #define GMAC_MTL_DPP_CONTROL_IPEMTS_MASK EMAC_MTL_DPP_CONTROL_IPEMTS_MASK #define GMAC_MTL_DPP_CONTROL_IPEMTS_SHIFT EMAC_MTL_DPP_CONTROL_IPEMTS_SHIFT #define GMAC_MTL_DPP_CONTROL_IPEMTS_WIDTH EMAC_MTL_DPP_CONTROL_IPEMTS_WIDTH #define GMAC_MTL_DPP_CONTROL_IPEMTS(x) EMAC_MTL_DPP_CONTROL_IPEMTS(x) #define GMAC_MTL_DPP_CONTROL_IPEMRF_MASK EMAC_MTL_DPP_CONTROL_IPEMRF_MASK #define GMAC_MTL_DPP_CONTROL_IPEMRF_SHIFT EMAC_MTL_DPP_CONTROL_IPEMRF_SHIFT #define GMAC_MTL_DPP_CONTROL_IPEMRF_WIDTH EMAC_MTL_DPP_CONTROL_IPEMRF_WIDTH #define GMAC_MTL_DPP_CONTROL_IPEMRF(x) EMAC_MTL_DPP_CONTROL_IPEMRF(x) #define GMAC_MTL_DPP_CONTROL_IPEDDC_MASK EMAC_MTL_DPP_CONTROL_IPEDDC_MASK #define GMAC_MTL_DPP_CONTROL_IPEDDC_SHIFT EMAC_MTL_DPP_CONTROL_IPEDDC_SHIFT #define GMAC_MTL_DPP_CONTROL_IPEDDC_WIDTH EMAC_MTL_DPP_CONTROL_IPEDDC_WIDTH #define GMAC_MTL_DPP_CONTROL_IPEDDC(x) EMAC_MTL_DPP_CONTROL_IPEDDC(x) #define GMAC_MTL_DPP_CONTROL_IPETD_MASK EMAC_MTL_DPP_CONTROL_IPETD_MASK #define GMAC_MTL_DPP_CONTROL_IPETD_SHIFT EMAC_MTL_DPP_CONTROL_IPETD_SHIFT #define GMAC_MTL_DPP_CONTROL_IPETD_WIDTH EMAC_MTL_DPP_CONTROL_IPETD_WIDTH #define GMAC_MTL_DPP_CONTROL_IPETD(x) EMAC_MTL_DPP_CONTROL_IPETD(x) #define GMAC_MTL_DPP_CONTROL_IPERD_MASK EMAC_MTL_DPP_CONTROL_IPERD_MASK #define GMAC_MTL_DPP_CONTROL_IPERD_SHIFT EMAC_MTL_DPP_CONTROL_IPERD_SHIFT #define GMAC_MTL_DPP_CONTROL_IPERD_WIDTH EMAC_MTL_DPP_CONTROL_IPERD_WIDTH #define GMAC_MTL_DPP_CONTROL_IPERD(x) EMAC_MTL_DPP_CONTROL_IPERD(x) /*! @} */ /*! @name MTL_TXQ0_OPERATION_MODE - */ /*! @{ */ #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_WIDTH EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_WIDTH #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ(x) EMAC_MTL_TXQ0_OPERATION_MODE_FTQ(x) #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK EMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT EMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_WIDTH EMAC_MTL_TXQ0_OPERATION_MODE_TSF_WIDTH #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF(x) EMAC_MTL_TXQ0_OPERATION_MODE_TSF(x) #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_WIDTH EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_WIDTH #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(x) EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(x) #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_WIDTH EMAC_MTL_TXQ0_OPERATION_MODE_TTC_WIDTH #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC(x) EMAC_MTL_TXQ0_OPERATION_MODE_TTC(x) #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS_WIDTH EMAC_MTL_TXQ0_OPERATION_MODE_TQS_WIDTH #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS(x) EMAC_MTL_TXQ0_OPERATION_MODE_TQS(x) /*! @} */ /*! @name MTL_TXQ0_UNDERFLOW - */ /*! @{ */ #define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK #define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT #define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_WIDTH EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_WIDTH #define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(x) EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(x) #define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK #define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT #define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_WIDTH EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_WIDTH #define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF(x) EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF(x) /*! @} */ /*! @name MTL_TXQ0_DEBUG - */ /*! @{ */ #define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK #define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT #define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_WIDTH EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_WIDTH #define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED(x) EMAC_MTL_TXQ0_DEBUG_TXQPAUSED(x) #define GMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK #define GMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT #define GMAC_MTL_TXQ0_DEBUG_TRCSTS_WIDTH EMAC_MTL_TXQ0_DEBUG_TRCSTS_WIDTH #define GMAC_MTL_TXQ0_DEBUG_TRCSTS(x) EMAC_MTL_TXQ0_DEBUG_TRCSTS(x) #define GMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK EMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK #define GMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT EMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT #define GMAC_MTL_TXQ0_DEBUG_TWCSTS_WIDTH EMAC_MTL_TXQ0_DEBUG_TWCSTS_WIDTH #define GMAC_MTL_TXQ0_DEBUG_TWCSTS(x) EMAC_MTL_TXQ0_DEBUG_TWCSTS(x) #define GMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK EMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK #define GMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT EMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT #define GMAC_MTL_TXQ0_DEBUG_TXQSTS_WIDTH EMAC_MTL_TXQ0_DEBUG_TXQSTS_WIDTH #define GMAC_MTL_TXQ0_DEBUG_TXQSTS(x) EMAC_MTL_TXQ0_DEBUG_TXQSTS(x) #define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK #define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT #define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_WIDTH EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_WIDTH #define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS(x) EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS(x) #define GMAC_MTL_TXQ0_DEBUG_PTXQ_MASK EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK #define GMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT #define GMAC_MTL_TXQ0_DEBUG_PTXQ_WIDTH EMAC_MTL_TXQ0_DEBUG_PTXQ_WIDTH #define GMAC_MTL_TXQ0_DEBUG_PTXQ(x) EMAC_MTL_TXQ0_DEBUG_PTXQ(x) #define GMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK #define GMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT #define GMAC_MTL_TXQ0_DEBUG_STXSTSF_WIDTH EMAC_MTL_TXQ0_DEBUG_STXSTSF_WIDTH #define GMAC_MTL_TXQ0_DEBUG_STXSTSF(x) EMAC_MTL_TXQ0_DEBUG_STXSTSF(x) /*! @} */ /*! @name MTL_TXQ0_ETS_STATUS - */ /*! @{ */ #define GMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK #define GMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT #define GMAC_MTL_TXQ0_ETS_STATUS_ABS_WIDTH EMAC_MTL_TXQ0_ETS_STATUS_ABS_WIDTH #define GMAC_MTL_TXQ0_ETS_STATUS_ABS(x) EMAC_MTL_TXQ0_ETS_STATUS_ABS(x) /*! @} */ /*! @name MTL_TXQ0_QUANTUM_WEIGHT - */ /*! @{ */ #define GMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK #define GMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT #define GMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_WIDTH EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_WIDTH #define GMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(x) EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(x) /*! @} */ /*! @name MTL_Q0_INTERRUPT_CONTROL_STATUS - */ /*! @{ */ #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS(x) #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MASK #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE(x) #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE(x) #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MASK #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE(x) /*! @} */ /*! @name MTL_RXQ0_OPERATION_MODE - */ /*! @{ */ #define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_RTC_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_RTC(x) EMAC_MTL_RXQ0_OPERATION_MODE_RTC(x) #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK EMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_FUP_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP(x) EMAC_MTL_RXQ0_OPERATION_MODE_FUP(x) #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK EMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_FEP_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP(x) EMAC_MTL_RXQ0_OPERATION_MODE_FEP(x) #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK EMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_RSF_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF(x) EMAC_MTL_RXQ0_OPERATION_MODE_RSF(x) #define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF(x) EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF(x) #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC(x) EMAC_MTL_RXQ0_OPERATION_MODE_EHFC(x) #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_RFA_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA(x) EMAC_MTL_RXQ0_OPERATION_MODE_RFA(x) #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_RFD_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD(x) EMAC_MTL_RXQ0_OPERATION_MODE_RFD(x) #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_RQS_WIDTH #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS(x) EMAC_MTL_RXQ0_OPERATION_MODE_RQS(x) /*! @} */ /*! @name MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT - */ /*! @{ */ #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) /*! @} */ /*! @name MTL_RXQ0_DEBUG - */ /*! @{ */ #define GMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK EMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK #define GMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT EMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT #define GMAC_MTL_RXQ0_DEBUG_RWCSTS_WIDTH EMAC_MTL_RXQ0_DEBUG_RWCSTS_WIDTH #define GMAC_MTL_RXQ0_DEBUG_RWCSTS(x) EMAC_MTL_RXQ0_DEBUG_RWCSTS(x) #define GMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK #define GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT #define GMAC_MTL_RXQ0_DEBUG_RRCSTS_WIDTH EMAC_MTL_RXQ0_DEBUG_RRCSTS_WIDTH #define GMAC_MTL_RXQ0_DEBUG_RRCSTS(x) EMAC_MTL_RXQ0_DEBUG_RRCSTS(x) #define GMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK #define GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT #define GMAC_MTL_RXQ0_DEBUG_RXQSTS_WIDTH EMAC_MTL_RXQ0_DEBUG_RXQSTS_WIDTH #define GMAC_MTL_RXQ0_DEBUG_RXQSTS(x) EMAC_MTL_RXQ0_DEBUG_RXQSTS(x) #define GMAC_MTL_RXQ0_DEBUG_PRXQ_MASK EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK #define GMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT #define GMAC_MTL_RXQ0_DEBUG_PRXQ_WIDTH EMAC_MTL_RXQ0_DEBUG_PRXQ_WIDTH #define GMAC_MTL_RXQ0_DEBUG_PRXQ(x) EMAC_MTL_RXQ0_DEBUG_PRXQ(x) /*! @} */ /*! @name MTL_RXQ0_CONTROL - */ /*! @{ */ #define GMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK #define GMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT #define GMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_WIDTH EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_WIDTH #define GMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(x) EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(x) #define GMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MASK EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MASK #define GMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_SHIFT EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_SHIFT #define GMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_WIDTH EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_WIDTH #define GMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT(x) EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT(x) /*! @} */ /*! @name MTL_TXQ1_OPERATION_MODE - */ /*! @{ */ #define GMAC_MTL_TXQ1_OPERATION_MODE_FTQ_MASK EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_MASK #define GMAC_MTL_TXQ1_OPERATION_MODE_FTQ_SHIFT EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_SHIFT #define GMAC_MTL_TXQ1_OPERATION_MODE_FTQ_WIDTH EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_WIDTH #define GMAC_MTL_TXQ1_OPERATION_MODE_FTQ(x) EMAC_MTL_TXQ1_OPERATION_MODE_FTQ(x) #define GMAC_MTL_TXQ1_OPERATION_MODE_TSF_MASK EMAC_MTL_TXQ1_OPERATION_MODE_TSF_MASK #define GMAC_MTL_TXQ1_OPERATION_MODE_TSF_SHIFT EMAC_MTL_TXQ1_OPERATION_MODE_TSF_SHIFT #define GMAC_MTL_TXQ1_OPERATION_MODE_TSF_WIDTH EMAC_MTL_TXQ1_OPERATION_MODE_TSF_WIDTH #define GMAC_MTL_TXQ1_OPERATION_MODE_TSF(x) EMAC_MTL_TXQ1_OPERATION_MODE_TSF(x) #define GMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK #define GMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT #define GMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_WIDTH EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_WIDTH #define GMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(x) EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(x) #define GMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK #define GMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT #define GMAC_MTL_TXQ1_OPERATION_MODE_TTC_WIDTH EMAC_MTL_TXQ1_OPERATION_MODE_TTC_WIDTH #define GMAC_MTL_TXQ1_OPERATION_MODE_TTC(x) EMAC_MTL_TXQ1_OPERATION_MODE_TTC(x) #define GMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK #define GMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT #define GMAC_MTL_TXQ1_OPERATION_MODE_TQS_WIDTH EMAC_MTL_TXQ1_OPERATION_MODE_TQS_WIDTH #define GMAC_MTL_TXQ1_OPERATION_MODE_TQS(x) EMAC_MTL_TXQ1_OPERATION_MODE_TQS(x) /*! @} */ /*! @name MTL_TXQ1_UNDERFLOW - */ /*! @{ */ #define GMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK #define GMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT #define GMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_WIDTH EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_WIDTH #define GMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(x) EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(x) #define GMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_MASK EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_MASK #define GMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_SHIFT EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_SHIFT #define GMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_WIDTH EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_WIDTH #define GMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF(x) EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF(x) /*! @} */ /*! @name MTL_TXQ1_DEBUG - */ /*! @{ */ #define GMAC_MTL_TXQ1_DEBUG_TXQPAUSED_MASK EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_MASK #define GMAC_MTL_TXQ1_DEBUG_TXQPAUSED_SHIFT EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_SHIFT #define GMAC_MTL_TXQ1_DEBUG_TXQPAUSED_WIDTH EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_WIDTH #define GMAC_MTL_TXQ1_DEBUG_TXQPAUSED(x) EMAC_MTL_TXQ1_DEBUG_TXQPAUSED(x) #define GMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK #define GMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT #define GMAC_MTL_TXQ1_DEBUG_TRCSTS_WIDTH EMAC_MTL_TXQ1_DEBUG_TRCSTS_WIDTH #define GMAC_MTL_TXQ1_DEBUG_TRCSTS(x) EMAC_MTL_TXQ1_DEBUG_TRCSTS(x) #define GMAC_MTL_TXQ1_DEBUG_TWCSTS_MASK EMAC_MTL_TXQ1_DEBUG_TWCSTS_MASK #define GMAC_MTL_TXQ1_DEBUG_TWCSTS_SHIFT EMAC_MTL_TXQ1_DEBUG_TWCSTS_SHIFT #define GMAC_MTL_TXQ1_DEBUG_TWCSTS_WIDTH EMAC_MTL_TXQ1_DEBUG_TWCSTS_WIDTH #define GMAC_MTL_TXQ1_DEBUG_TWCSTS(x) EMAC_MTL_TXQ1_DEBUG_TWCSTS(x) #define GMAC_MTL_TXQ1_DEBUG_TXQSTS_MASK EMAC_MTL_TXQ1_DEBUG_TXQSTS_MASK #define GMAC_MTL_TXQ1_DEBUG_TXQSTS_SHIFT EMAC_MTL_TXQ1_DEBUG_TXQSTS_SHIFT #define GMAC_MTL_TXQ1_DEBUG_TXQSTS_WIDTH EMAC_MTL_TXQ1_DEBUG_TXQSTS_WIDTH #define GMAC_MTL_TXQ1_DEBUG_TXQSTS(x) EMAC_MTL_TXQ1_DEBUG_TXQSTS(x) #define GMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_MASK EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_MASK #define GMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_SHIFT EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_SHIFT #define GMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_WIDTH EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_WIDTH #define GMAC_MTL_TXQ1_DEBUG_TXSTSFSTS(x) EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS(x) #define GMAC_MTL_TXQ1_DEBUG_PTXQ_MASK EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK #define GMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT #define GMAC_MTL_TXQ1_DEBUG_PTXQ_WIDTH EMAC_MTL_TXQ1_DEBUG_PTXQ_WIDTH #define GMAC_MTL_TXQ1_DEBUG_PTXQ(x) EMAC_MTL_TXQ1_DEBUG_PTXQ(x) #define GMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK #define GMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT #define GMAC_MTL_TXQ1_DEBUG_STXSTSF_WIDTH EMAC_MTL_TXQ1_DEBUG_STXSTSF_WIDTH #define GMAC_MTL_TXQ1_DEBUG_STXSTSF(x) EMAC_MTL_TXQ1_DEBUG_STXSTSF(x) /*! @} */ /*! @name MTL_TXQ1_ETS_CONTROL - */ /*! @{ */ #define GMAC_MTL_TXQ1_ETS_CONTROL_AVALG_MASK EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_MASK #define GMAC_MTL_TXQ1_ETS_CONTROL_AVALG_SHIFT EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_SHIFT #define GMAC_MTL_TXQ1_ETS_CONTROL_AVALG_WIDTH EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_WIDTH #define GMAC_MTL_TXQ1_ETS_CONTROL_AVALG(x) EMAC_MTL_TXQ1_ETS_CONTROL_AVALG(x) #define GMAC_MTL_TXQ1_ETS_CONTROL_CC_MASK EMAC_MTL_TXQ1_ETS_CONTROL_CC_MASK #define GMAC_MTL_TXQ1_ETS_CONTROL_CC_SHIFT EMAC_MTL_TXQ1_ETS_CONTROL_CC_SHIFT #define GMAC_MTL_TXQ1_ETS_CONTROL_CC_WIDTH EMAC_MTL_TXQ1_ETS_CONTROL_CC_WIDTH #define GMAC_MTL_TXQ1_ETS_CONTROL_CC(x) EMAC_MTL_TXQ1_ETS_CONTROL_CC(x) #define GMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK #define GMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT #define GMAC_MTL_TXQ1_ETS_CONTROL_SLC_WIDTH EMAC_MTL_TXQ1_ETS_CONTROL_SLC_WIDTH #define GMAC_MTL_TXQ1_ETS_CONTROL_SLC(x) EMAC_MTL_TXQ1_ETS_CONTROL_SLC(x) /*! @} */ /*! @name MTL_TXQ1_ETS_STATUS - */ /*! @{ */ #define GMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK #define GMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT #define GMAC_MTL_TXQ1_ETS_STATUS_ABS_WIDTH EMAC_MTL_TXQ1_ETS_STATUS_ABS_WIDTH #define GMAC_MTL_TXQ1_ETS_STATUS_ABS(x) EMAC_MTL_TXQ1_ETS_STATUS_ABS(x) /*! @} */ /*! @name MTL_TXQ1_QUANTUM_WEIGHT - */ /*! @{ */ #define GMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK #define GMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT #define GMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_WIDTH EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_WIDTH #define GMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(x) EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(x) /*! @} */ /*! @name MTL_TXQ1_SENDSLOPECREDIT - */ /*! @{ */ #define GMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK #define GMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT #define GMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_WIDTH EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_WIDTH #define GMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(x) EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(x) /*! @} */ /*! @name MTL_TXQ1_HICREDIT - */ /*! @{ */ #define GMAC_MTL_TXQ1_HICREDIT_HC_MASK EMAC_MTL_TXQ1_HICREDIT_HC_MASK #define GMAC_MTL_TXQ1_HICREDIT_HC_SHIFT EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT #define GMAC_MTL_TXQ1_HICREDIT_HC_WIDTH EMAC_MTL_TXQ1_HICREDIT_HC_WIDTH #define GMAC_MTL_TXQ1_HICREDIT_HC(x) EMAC_MTL_TXQ1_HICREDIT_HC(x) /*! @} */ /*! @name MTL_TXQ1_LOCREDIT - */ /*! @{ */ #define GMAC_MTL_TXQ1_LOCREDIT_LC_MASK EMAC_MTL_TXQ1_LOCREDIT_LC_MASK #define GMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT #define GMAC_MTL_TXQ1_LOCREDIT_LC_WIDTH EMAC_MTL_TXQ1_LOCREDIT_LC_WIDTH #define GMAC_MTL_TXQ1_LOCREDIT_LC(x) EMAC_MTL_TXQ1_LOCREDIT_LC(x) /*! @} */ /*! @name MTL_Q1_INTERRUPT_CONTROL_STATUS - */ /*! @{ */ #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS(x) #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_MASK #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE(x) #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE(x) #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_MASK #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE(x) /*! @} */ /*! @name MTL_RXQ1_OPERATION_MODE - */ /*! @{ */ #define GMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_RTC_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_RTC_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_RTC(x) EMAC_MTL_RXQ1_OPERATION_MODE_RTC(x) #define GMAC_MTL_RXQ1_OPERATION_MODE_FUP_MASK EMAC_MTL_RXQ1_OPERATION_MODE_FUP_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_FUP_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_FUP_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_FUP_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_FUP_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_FUP(x) EMAC_MTL_RXQ1_OPERATION_MODE_FUP(x) #define GMAC_MTL_RXQ1_OPERATION_MODE_FEP_MASK EMAC_MTL_RXQ1_OPERATION_MODE_FEP_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_FEP_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_FEP_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_FEP_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_FEP_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_FEP(x) EMAC_MTL_RXQ1_OPERATION_MODE_FEP(x) #define GMAC_MTL_RXQ1_OPERATION_MODE_RSF_MASK EMAC_MTL_RXQ1_OPERATION_MODE_RSF_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_RSF_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_RSF_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_RSF_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_RSF_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_RSF(x) EMAC_MTL_RXQ1_OPERATION_MODE_RSF(x) #define GMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_MASK EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF(x) EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF(x) #define GMAC_MTL_RXQ1_OPERATION_MODE_EHFC_MASK EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_EHFC_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_EHFC_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_EHFC(x) EMAC_MTL_RXQ1_OPERATION_MODE_EHFC(x) #define GMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_RFA_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_RFA_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_RFA(x) EMAC_MTL_RXQ1_OPERATION_MODE_RFA(x) #define GMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_RFD_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_RFD_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_RFD(x) EMAC_MTL_RXQ1_OPERATION_MODE_RFD(x) #define GMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK #define GMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT #define GMAC_MTL_RXQ1_OPERATION_MODE_RQS_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_RQS_WIDTH #define GMAC_MTL_RXQ1_OPERATION_MODE_RQS(x) EMAC_MTL_RXQ1_OPERATION_MODE_RQS(x) /*! @} */ /*! @name MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT - */ /*! @{ */ #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) /*! @} */ /*! @name MTL_RXQ1_DEBUG - */ /*! @{ */ #define GMAC_MTL_RXQ1_DEBUG_RWCSTS_MASK EMAC_MTL_RXQ1_DEBUG_RWCSTS_MASK #define GMAC_MTL_RXQ1_DEBUG_RWCSTS_SHIFT EMAC_MTL_RXQ1_DEBUG_RWCSTS_SHIFT #define GMAC_MTL_RXQ1_DEBUG_RWCSTS_WIDTH EMAC_MTL_RXQ1_DEBUG_RWCSTS_WIDTH #define GMAC_MTL_RXQ1_DEBUG_RWCSTS(x) EMAC_MTL_RXQ1_DEBUG_RWCSTS(x) #define GMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK #define GMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT #define GMAC_MTL_RXQ1_DEBUG_RRCSTS_WIDTH EMAC_MTL_RXQ1_DEBUG_RRCSTS_WIDTH #define GMAC_MTL_RXQ1_DEBUG_RRCSTS(x) EMAC_MTL_RXQ1_DEBUG_RRCSTS(x) #define GMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK #define GMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT #define GMAC_MTL_RXQ1_DEBUG_RXQSTS_WIDTH EMAC_MTL_RXQ1_DEBUG_RXQSTS_WIDTH #define GMAC_MTL_RXQ1_DEBUG_RXQSTS(x) EMAC_MTL_RXQ1_DEBUG_RXQSTS(x) #define GMAC_MTL_RXQ1_DEBUG_PRXQ_MASK EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK #define GMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT #define GMAC_MTL_RXQ1_DEBUG_PRXQ_WIDTH EMAC_MTL_RXQ1_DEBUG_PRXQ_WIDTH #define GMAC_MTL_RXQ1_DEBUG_PRXQ(x) EMAC_MTL_RXQ1_DEBUG_PRXQ(x) /*! @} */ /*! @name MTL_RXQ1_CONTROL - */ /*! @{ */ #define GMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK #define GMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT #define GMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_WIDTH EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_WIDTH #define GMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(x) EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(x) #define GMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_MASK EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_MASK #define GMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_SHIFT EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_SHIFT #define GMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_WIDTH EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_WIDTH #define GMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT(x) EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT(x) /*! @} */ /*! @name DMA_MODE - */ /*! @{ */ #define GMAC_DMA_MODE_SWR_MASK EMAC_DMA_MODE_SWR_MASK #define GMAC_DMA_MODE_SWR_SHIFT EMAC_DMA_MODE_SWR_SHIFT #define GMAC_DMA_MODE_SWR_WIDTH EMAC_DMA_MODE_SWR_WIDTH #define GMAC_DMA_MODE_SWR(x) EMAC_DMA_MODE_SWR(x) #define GMAC_DMA_MODE_DA_MASK EMAC_DMA_MODE_DA_MASK #define GMAC_DMA_MODE_DA_SHIFT EMAC_DMA_MODE_DA_SHIFT #define GMAC_DMA_MODE_DA_WIDTH EMAC_DMA_MODE_DA_WIDTH #define GMAC_DMA_MODE_DA(x) EMAC_DMA_MODE_DA(x) #define GMAC_DMA_MODE_TAA_MASK EMAC_DMA_MODE_TAA_MASK #define GMAC_DMA_MODE_TAA_SHIFT EMAC_DMA_MODE_TAA_SHIFT #define GMAC_DMA_MODE_TAA_WIDTH EMAC_DMA_MODE_TAA_WIDTH #define GMAC_DMA_MODE_TAA(x) EMAC_DMA_MODE_TAA(x) #define GMAC_DMA_MODE_ARBC_MASK EMAC_DMA_MODE_ARBC_MASK #define GMAC_DMA_MODE_ARBC_SHIFT EMAC_DMA_MODE_ARBC_SHIFT #define GMAC_DMA_MODE_ARBC_WIDTH EMAC_DMA_MODE_ARBC_WIDTH #define GMAC_DMA_MODE_ARBC(x) EMAC_DMA_MODE_ARBC(x) #define GMAC_DMA_MODE_TXPR_MASK EMAC_DMA_MODE_TXPR_MASK #define GMAC_DMA_MODE_TXPR_SHIFT EMAC_DMA_MODE_TXPR_SHIFT #define GMAC_DMA_MODE_TXPR_WIDTH EMAC_DMA_MODE_TXPR_WIDTH #define GMAC_DMA_MODE_TXPR(x) EMAC_DMA_MODE_TXPR(x) #define GMAC_DMA_MODE_PR_MASK EMAC_DMA_MODE_PR_MASK #define GMAC_DMA_MODE_PR_SHIFT EMAC_DMA_MODE_PR_SHIFT #define GMAC_DMA_MODE_PR_WIDTH EMAC_DMA_MODE_PR_WIDTH #define GMAC_DMA_MODE_PR(x) EMAC_DMA_MODE_PR(x) #define GMAC_DMA_MODE_INTM_MASK EMAC_DMA_MODE_INTM_MASK #define GMAC_DMA_MODE_INTM_SHIFT EMAC_DMA_MODE_INTM_SHIFT #define GMAC_DMA_MODE_INTM_WIDTH EMAC_DMA_MODE_INTM_WIDTH #define GMAC_DMA_MODE_INTM(x) EMAC_DMA_MODE_INTM(x) /*! @} */ /*! @name DMA_SYSBUS_MODE - */ /*! @{ */ #define GMAC_DMA_SYSBUS_MODE_FB_MASK EMAC_DMA_SYSBUS_MODE_FB_MASK #define GMAC_DMA_SYSBUS_MODE_FB_SHIFT EMAC_DMA_SYSBUS_MODE_FB_SHIFT #define GMAC_DMA_SYSBUS_MODE_FB_WIDTH EMAC_DMA_SYSBUS_MODE_FB_WIDTH #define GMAC_DMA_SYSBUS_MODE_FB(x) EMAC_DMA_SYSBUS_MODE_FB(x) #define GMAC_DMA_SYSBUS_MODE_AAL_MASK EMAC_DMA_SYSBUS_MODE_AAL_MASK #define GMAC_DMA_SYSBUS_MODE_AAL_SHIFT EMAC_DMA_SYSBUS_MODE_AAL_SHIFT #define GMAC_DMA_SYSBUS_MODE_AAL_WIDTH EMAC_DMA_SYSBUS_MODE_AAL_WIDTH #define GMAC_DMA_SYSBUS_MODE_AAL(x) EMAC_DMA_SYSBUS_MODE_AAL(x) #define GMAC_DMA_SYSBUS_MODE_MB_MASK EMAC_DMA_SYSBUS_MODE_MB_MASK #define GMAC_DMA_SYSBUS_MODE_MB_SHIFT EMAC_DMA_SYSBUS_MODE_MB_SHIFT #define GMAC_DMA_SYSBUS_MODE_MB_WIDTH EMAC_DMA_SYSBUS_MODE_MB_WIDTH #define GMAC_DMA_SYSBUS_MODE_MB(x) EMAC_DMA_SYSBUS_MODE_MB(x) #define GMAC_DMA_SYSBUS_MODE_RB_MASK EMAC_DMA_SYSBUS_MODE_RB_MASK #define GMAC_DMA_SYSBUS_MODE_RB_SHIFT EMAC_DMA_SYSBUS_MODE_RB_SHIFT #define GMAC_DMA_SYSBUS_MODE_RB_WIDTH EMAC_DMA_SYSBUS_MODE_RB_WIDTH #define GMAC_DMA_SYSBUS_MODE_RB(x) EMAC_DMA_SYSBUS_MODE_RB(x) /*! @} */ /*! @name DMA_INTERRUPT_STATUS - */ /*! @{ */ #define GMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK #define GMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT EMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT #define GMAC_DMA_INTERRUPT_STATUS_DC0IS_WIDTH EMAC_DMA_INTERRUPT_STATUS_DC0IS_WIDTH #define GMAC_DMA_INTERRUPT_STATUS_DC0IS(x) EMAC_DMA_INTERRUPT_STATUS_DC0IS(x) #define GMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK #define GMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT EMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT #define GMAC_DMA_INTERRUPT_STATUS_DC1IS_WIDTH EMAC_DMA_INTERRUPT_STATUS_DC1IS_WIDTH #define GMAC_DMA_INTERRUPT_STATUS_DC1IS(x) EMAC_DMA_INTERRUPT_STATUS_DC1IS(x) #define GMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK EMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK #define GMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT EMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT #define GMAC_DMA_INTERRUPT_STATUS_MTLIS_WIDTH EMAC_DMA_INTERRUPT_STATUS_MTLIS_WIDTH #define GMAC_DMA_INTERRUPT_STATUS_MTLIS(x) EMAC_DMA_INTERRUPT_STATUS_MTLIS(x) #define GMAC_DMA_INTERRUPT_STATUS_MACIS_MASK EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK #define GMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT EMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT #define GMAC_DMA_INTERRUPT_STATUS_MACIS_WIDTH EMAC_DMA_INTERRUPT_STATUS_MACIS_WIDTH #define GMAC_DMA_INTERRUPT_STATUS_MACIS(x) EMAC_DMA_INTERRUPT_STATUS_MACIS(x) /*! @} */ /*! @name DMA_DEBUG_STATUS0 - */ /*! @{ */ #define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK EMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK #define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT EMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT #define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_WIDTH EMAC_DMA_DEBUG_STATUS0_AXWHSTS_WIDTH #define GMAC_DMA_DEBUG_STATUS0_AXWHSTS(x) EMAC_DMA_DEBUG_STATUS0_AXWHSTS(x) #define GMAC_DMA_DEBUG_STATUS0_RPS0_MASK EMAC_DMA_DEBUG_STATUS0_RPS0_MASK #define GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT #define GMAC_DMA_DEBUG_STATUS0_RPS0_WIDTH EMAC_DMA_DEBUG_STATUS0_RPS0_WIDTH #define GMAC_DMA_DEBUG_STATUS0_RPS0(x) EMAC_DMA_DEBUG_STATUS0_RPS0(x) #define GMAC_DMA_DEBUG_STATUS0_TPS0_MASK EMAC_DMA_DEBUG_STATUS0_TPS0_MASK #define GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT #define GMAC_DMA_DEBUG_STATUS0_TPS0_WIDTH EMAC_DMA_DEBUG_STATUS0_TPS0_WIDTH #define GMAC_DMA_DEBUG_STATUS0_TPS0(x) EMAC_DMA_DEBUG_STATUS0_TPS0(x) #define GMAC_DMA_DEBUG_STATUS0_RPS1_MASK EMAC_DMA_DEBUG_STATUS0_RPS1_MASK #define GMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT #define GMAC_DMA_DEBUG_STATUS0_RPS1_WIDTH EMAC_DMA_DEBUG_STATUS0_RPS1_WIDTH #define GMAC_DMA_DEBUG_STATUS0_RPS1(x) EMAC_DMA_DEBUG_STATUS0_RPS1(x) #define GMAC_DMA_DEBUG_STATUS0_TPS1_MASK EMAC_DMA_DEBUG_STATUS0_TPS1_MASK #define GMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT #define GMAC_DMA_DEBUG_STATUS0_TPS1_WIDTH EMAC_DMA_DEBUG_STATUS0_TPS1_WIDTH #define GMAC_DMA_DEBUG_STATUS0_TPS1(x) EMAC_DMA_DEBUG_STATUS0_TPS1(x) /*! @} */ /*! @name DMA_TBS_CTRL - */ /*! @{ */ #define GMAC_DMA_TBS_CTRL_FTOV_MASK EMAC_DMA_TBS_CTRL_FTOV_MASK #define GMAC_DMA_TBS_CTRL_FTOV_SHIFT EMAC_DMA_TBS_CTRL_FTOV_SHIFT #define GMAC_DMA_TBS_CTRL_FTOV_WIDTH EMAC_DMA_TBS_CTRL_FTOV_WIDTH #define GMAC_DMA_TBS_CTRL_FTOV(x) EMAC_DMA_TBS_CTRL_FTOV(x) #define GMAC_DMA_TBS_CTRL_FGOS_MASK EMAC_DMA_TBS_CTRL_FGOS_MASK #define GMAC_DMA_TBS_CTRL_FGOS_SHIFT EMAC_DMA_TBS_CTRL_FGOS_SHIFT #define GMAC_DMA_TBS_CTRL_FGOS_WIDTH EMAC_DMA_TBS_CTRL_FGOS_WIDTH #define GMAC_DMA_TBS_CTRL_FGOS(x) EMAC_DMA_TBS_CTRL_FGOS(x) #define GMAC_DMA_TBS_CTRL_FTOS_MASK EMAC_DMA_TBS_CTRL_FTOS_MASK #define GMAC_DMA_TBS_CTRL_FTOS_SHIFT EMAC_DMA_TBS_CTRL_FTOS_SHIFT #define GMAC_DMA_TBS_CTRL_FTOS_WIDTH EMAC_DMA_TBS_CTRL_FTOS_WIDTH #define GMAC_DMA_TBS_CTRL_FTOS(x) EMAC_DMA_TBS_CTRL_FTOS(x) /*! @} */ /*! @name DMA_SAFETY_INTERRUPT_STATUS - */ /*! @{ */ #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_WIDTH #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS(x) #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_WIDTH #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS(x) #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_WIDTH #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS(x) #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_WIDTH #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS(x) #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_WIDTH #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS(x) /*! @} */ /*! @name DMA_CH0_CONTROL - */ /*! @{ */ #define GMAC_DMA_CH0_CONTROL_PBLx8_MASK EMAC_DMA_CH0_CONTROL_PBLx8_MASK #define GMAC_DMA_CH0_CONTROL_PBLx8_SHIFT EMAC_DMA_CH0_CONTROL_PBLx8_SHIFT #define GMAC_DMA_CH0_CONTROL_PBLx8_WIDTH EMAC_DMA_CH0_CONTROL_PBLx8_WIDTH #define GMAC_DMA_CH0_CONTROL_PBLx8(x) EMAC_DMA_CH0_CONTROL_PBLx8(x) #define GMAC_DMA_CH0_CONTROL_DSL_MASK EMAC_DMA_CH0_CONTROL_DSL_MASK #define GMAC_DMA_CH0_CONTROL_DSL_SHIFT EMAC_DMA_CH0_CONTROL_DSL_SHIFT #define GMAC_DMA_CH0_CONTROL_DSL_WIDTH EMAC_DMA_CH0_CONTROL_DSL_WIDTH #define GMAC_DMA_CH0_CONTROL_DSL(x) EMAC_DMA_CH0_CONTROL_DSL(x) /*! @} */ /*! @name DMA_CH0_TX_CONTROL - */ /*! @{ */ #define GMAC_DMA_CH0_TX_CONTROL_ST_MASK EMAC_DMA_CH0_TX_CONTROL_ST_MASK #define GMAC_DMA_CH0_TX_CONTROL_ST_SHIFT EMAC_DMA_CH0_TX_CONTROL_ST_SHIFT #define GMAC_DMA_CH0_TX_CONTROL_ST_WIDTH EMAC_DMA_CH0_TX_CONTROL_ST_WIDTH #define GMAC_DMA_CH0_TX_CONTROL_ST(x) EMAC_DMA_CH0_TX_CONTROL_ST(x) #define GMAC_DMA_CH0_TX_CONTROL_TCW_MASK EMAC_DMA_CH0_TX_CONTROL_TCW_MASK #define GMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT #define GMAC_DMA_CH0_TX_CONTROL_TCW_WIDTH EMAC_DMA_CH0_TX_CONTROL_TCW_WIDTH #define GMAC_DMA_CH0_TX_CONTROL_TCW(x) EMAC_DMA_CH0_TX_CONTROL_TCW(x) #define GMAC_DMA_CH0_TX_CONTROL_OSF_MASK EMAC_DMA_CH0_TX_CONTROL_OSF_MASK #define GMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT EMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT #define GMAC_DMA_CH0_TX_CONTROL_OSF_WIDTH EMAC_DMA_CH0_TX_CONTROL_OSF_WIDTH #define GMAC_DMA_CH0_TX_CONTROL_OSF(x) EMAC_DMA_CH0_TX_CONTROL_OSF(x) #define GMAC_DMA_CH0_TX_CONTROL_TxPBL_MASK EMAC_DMA_CH0_TX_CONTROL_TxPBL_MASK #define GMAC_DMA_CH0_TX_CONTROL_TxPBL_SHIFT EMAC_DMA_CH0_TX_CONTROL_TxPBL_SHIFT #define GMAC_DMA_CH0_TX_CONTROL_TxPBL_WIDTH EMAC_DMA_CH0_TX_CONTROL_TxPBL_WIDTH #define GMAC_DMA_CH0_TX_CONTROL_TxPBL(x) EMAC_DMA_CH0_TX_CONTROL_TxPBL(x) #define GMAC_DMA_CH0_TX_CONTROL_ETIC_MASK EMAC_DMA_CH0_TX_CONTROL_ETIC_MASK #define GMAC_DMA_CH0_TX_CONTROL_ETIC_SHIFT EMAC_DMA_CH0_TX_CONTROL_ETIC_SHIFT #define GMAC_DMA_CH0_TX_CONTROL_ETIC_WIDTH EMAC_DMA_CH0_TX_CONTROL_ETIC_WIDTH #define GMAC_DMA_CH0_TX_CONTROL_ETIC(x) EMAC_DMA_CH0_TX_CONTROL_ETIC(x) #define GMAC_DMA_CH0_TX_CONTROL_EDSE_MASK EMAC_DMA_CH0_TX_CONTROL_EDSE_MASK #define GMAC_DMA_CH0_TX_CONTROL_EDSE_SHIFT EMAC_DMA_CH0_TX_CONTROL_EDSE_SHIFT #define GMAC_DMA_CH0_TX_CONTROL_EDSE_WIDTH EMAC_DMA_CH0_TX_CONTROL_EDSE_WIDTH #define GMAC_DMA_CH0_TX_CONTROL_EDSE(x) EMAC_DMA_CH0_TX_CONTROL_EDSE(x) /*! @} */ /*! @name DMA_CH0_RX_CONTROL - */ /*! @{ */ #define GMAC_DMA_CH0_RX_CONTROL_SR_MASK EMAC_DMA_CH0_RX_CONTROL_SR_MASK #define GMAC_DMA_CH0_RX_CONTROL_SR_SHIFT EMAC_DMA_CH0_RX_CONTROL_SR_SHIFT #define GMAC_DMA_CH0_RX_CONTROL_SR_WIDTH EMAC_DMA_CH0_RX_CONTROL_SR_WIDTH #define GMAC_DMA_CH0_RX_CONTROL_SR(x) EMAC_DMA_CH0_RX_CONTROL_SR(x) #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_MASK EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_MASK #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_SHIFT EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_SHIFT #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_WIDTH EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_WIDTH #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0(x) EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0(x) #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_MASK EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_MASK #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_SHIFT EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_SHIFT #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_WIDTH EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_WIDTH #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y(x) EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y(x) #define GMAC_DMA_CH0_RX_CONTROL_RxPBL_MASK EMAC_DMA_CH0_RX_CONTROL_RxPBL_MASK #define GMAC_DMA_CH0_RX_CONTROL_RxPBL_SHIFT EMAC_DMA_CH0_RX_CONTROL_RxPBL_SHIFT #define GMAC_DMA_CH0_RX_CONTROL_RxPBL_WIDTH EMAC_DMA_CH0_RX_CONTROL_RxPBL_WIDTH #define GMAC_DMA_CH0_RX_CONTROL_RxPBL(x) EMAC_DMA_CH0_RX_CONTROL_RxPBL(x) #define GMAC_DMA_CH0_RX_CONTROL_ERIC_MASK EMAC_DMA_CH0_RX_CONTROL_ERIC_MASK #define GMAC_DMA_CH0_RX_CONTROL_ERIC_SHIFT EMAC_DMA_CH0_RX_CONTROL_ERIC_SHIFT #define GMAC_DMA_CH0_RX_CONTROL_ERIC_WIDTH EMAC_DMA_CH0_RX_CONTROL_ERIC_WIDTH #define GMAC_DMA_CH0_RX_CONTROL_ERIC(x) EMAC_DMA_CH0_RX_CONTROL_ERIC(x) #define GMAC_DMA_CH0_RX_CONTROL_RPF_MASK EMAC_DMA_CH0_RX_CONTROL_RPF_MASK #define GMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT EMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT #define GMAC_DMA_CH0_RX_CONTROL_RPF_WIDTH EMAC_DMA_CH0_RX_CONTROL_RPF_WIDTH #define GMAC_DMA_CH0_RX_CONTROL_RPF(x) EMAC_DMA_CH0_RX_CONTROL_RPF(x) /*! @} */ /*! @name DMA_CH0_TXDESC_LIST_ADDRESS - */ /*! @{ */ #define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK #define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT #define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_WIDTH EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_WIDTH #define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(x) EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(x) /*! @} */ /*! @name DMA_CH0_RXDESC_LIST_ADDRESS - */ /*! @{ */ #define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK #define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT #define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_WIDTH EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_WIDTH #define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(x) EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(x) /*! @} */ /*! @name DMA_CH0_TXDESC_TAIL_POINTER - */ /*! @{ */ #define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK #define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT #define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_WIDTH EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_WIDTH #define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(x) EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(x) /*! @} */ /*! @name DMA_CH0_RXDESC_TAIL_POINTER - */ /*! @{ */ #define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK #define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT #define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_WIDTH EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_WIDTH #define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(x) EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(x) /*! @} */ /*! @name DMA_CH0_TXDESC_RING_LENGTH - */ /*! @{ */ #define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK #define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT #define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_WIDTH EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_WIDTH #define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(x) EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(x) /*! @} */ /*! @name DMA_CH0_RXDESC_RING_LENGTH - */ /*! @{ */ #define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK #define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT #define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_WIDTH EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_WIDTH #define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(x) EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(x) /*! @} */ /*! @name DMA_CH0_INTERRUPT_ENABLE - */ /*! @{ */ #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE(x) #define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK #define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT #define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_WIDTH #define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE(x) EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE(x) /*! @} */ /*! @name DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER - */ /*! @{ */ #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) /*! @} */ /*! @name DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS - */ /*! @{ */ #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) /*! @} */ /*! @name DMA_CH0_CURRENT_APP_TXDESC - */ /*! @{ */ #define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK #define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT #define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH #define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(x) EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(x) /*! @} */ /*! @name DMA_CH0_CURRENT_APP_RXDESC - */ /*! @{ */ #define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK #define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT #define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH #define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(x) EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(x) /*! @} */ /*! @name DMA_CH0_CURRENT_APP_TXBUFFER - */ /*! @{ */ #define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK #define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT #define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH #define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) /*! @} */ /*! @name DMA_CH0_CURRENT_APP_RXBUFFER - */ /*! @{ */ #define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK #define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT #define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH #define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) /*! @} */ /*! @name DMA_CH0_STATUS - */ /*! @{ */ #define GMAC_DMA_CH0_STATUS_TI_MASK EMAC_DMA_CH0_STATUS_TI_MASK #define GMAC_DMA_CH0_STATUS_TI_SHIFT EMAC_DMA_CH0_STATUS_TI_SHIFT #define GMAC_DMA_CH0_STATUS_TI_WIDTH EMAC_DMA_CH0_STATUS_TI_WIDTH #define GMAC_DMA_CH0_STATUS_TI(x) EMAC_DMA_CH0_STATUS_TI(x) #define GMAC_DMA_CH0_STATUS_TPS_MASK EMAC_DMA_CH0_STATUS_TPS_MASK #define GMAC_DMA_CH0_STATUS_TPS_SHIFT EMAC_DMA_CH0_STATUS_TPS_SHIFT #define GMAC_DMA_CH0_STATUS_TPS_WIDTH EMAC_DMA_CH0_STATUS_TPS_WIDTH #define GMAC_DMA_CH0_STATUS_TPS(x) EMAC_DMA_CH0_STATUS_TPS(x) #define GMAC_DMA_CH0_STATUS_TBU_MASK EMAC_DMA_CH0_STATUS_TBU_MASK #define GMAC_DMA_CH0_STATUS_TBU_SHIFT EMAC_DMA_CH0_STATUS_TBU_SHIFT #define GMAC_DMA_CH0_STATUS_TBU_WIDTH EMAC_DMA_CH0_STATUS_TBU_WIDTH #define GMAC_DMA_CH0_STATUS_TBU(x) EMAC_DMA_CH0_STATUS_TBU(x) #define GMAC_DMA_CH0_STATUS_RI_MASK EMAC_DMA_CH0_STATUS_RI_MASK #define GMAC_DMA_CH0_STATUS_RI_SHIFT EMAC_DMA_CH0_STATUS_RI_SHIFT #define GMAC_DMA_CH0_STATUS_RI_WIDTH EMAC_DMA_CH0_STATUS_RI_WIDTH #define GMAC_DMA_CH0_STATUS_RI(x) EMAC_DMA_CH0_STATUS_RI(x) #define GMAC_DMA_CH0_STATUS_RBU_MASK EMAC_DMA_CH0_STATUS_RBU_MASK #define GMAC_DMA_CH0_STATUS_RBU_SHIFT EMAC_DMA_CH0_STATUS_RBU_SHIFT #define GMAC_DMA_CH0_STATUS_RBU_WIDTH EMAC_DMA_CH0_STATUS_RBU_WIDTH #define GMAC_DMA_CH0_STATUS_RBU(x) EMAC_DMA_CH0_STATUS_RBU(x) #define GMAC_DMA_CH0_STATUS_RPS_MASK EMAC_DMA_CH0_STATUS_RPS_MASK #define GMAC_DMA_CH0_STATUS_RPS_SHIFT EMAC_DMA_CH0_STATUS_RPS_SHIFT #define GMAC_DMA_CH0_STATUS_RPS_WIDTH EMAC_DMA_CH0_STATUS_RPS_WIDTH #define GMAC_DMA_CH0_STATUS_RPS(x) EMAC_DMA_CH0_STATUS_RPS(x) #define GMAC_DMA_CH0_STATUS_RWT_MASK EMAC_DMA_CH0_STATUS_RWT_MASK #define GMAC_DMA_CH0_STATUS_RWT_SHIFT EMAC_DMA_CH0_STATUS_RWT_SHIFT #define GMAC_DMA_CH0_STATUS_RWT_WIDTH EMAC_DMA_CH0_STATUS_RWT_WIDTH #define GMAC_DMA_CH0_STATUS_RWT(x) EMAC_DMA_CH0_STATUS_RWT(x) #define GMAC_DMA_CH0_STATUS_ETI_MASK EMAC_DMA_CH0_STATUS_ETI_MASK #define GMAC_DMA_CH0_STATUS_ETI_SHIFT EMAC_DMA_CH0_STATUS_ETI_SHIFT #define GMAC_DMA_CH0_STATUS_ETI_WIDTH EMAC_DMA_CH0_STATUS_ETI_WIDTH #define GMAC_DMA_CH0_STATUS_ETI(x) EMAC_DMA_CH0_STATUS_ETI(x) #define GMAC_DMA_CH0_STATUS_ERI_MASK EMAC_DMA_CH0_STATUS_ERI_MASK #define GMAC_DMA_CH0_STATUS_ERI_SHIFT EMAC_DMA_CH0_STATUS_ERI_SHIFT #define GMAC_DMA_CH0_STATUS_ERI_WIDTH EMAC_DMA_CH0_STATUS_ERI_WIDTH #define GMAC_DMA_CH0_STATUS_ERI(x) EMAC_DMA_CH0_STATUS_ERI(x) #define GMAC_DMA_CH0_STATUS_FBE_MASK EMAC_DMA_CH0_STATUS_FBE_MASK #define GMAC_DMA_CH0_STATUS_FBE_SHIFT EMAC_DMA_CH0_STATUS_FBE_SHIFT #define GMAC_DMA_CH0_STATUS_FBE_WIDTH EMAC_DMA_CH0_STATUS_FBE_WIDTH #define GMAC_DMA_CH0_STATUS_FBE(x) EMAC_DMA_CH0_STATUS_FBE(x) #define GMAC_DMA_CH0_STATUS_CDE_MASK EMAC_DMA_CH0_STATUS_CDE_MASK #define GMAC_DMA_CH0_STATUS_CDE_SHIFT EMAC_DMA_CH0_STATUS_CDE_SHIFT #define GMAC_DMA_CH0_STATUS_CDE_WIDTH EMAC_DMA_CH0_STATUS_CDE_WIDTH #define GMAC_DMA_CH0_STATUS_CDE(x) EMAC_DMA_CH0_STATUS_CDE(x) #define GMAC_DMA_CH0_STATUS_AIS_MASK EMAC_DMA_CH0_STATUS_AIS_MASK #define GMAC_DMA_CH0_STATUS_AIS_SHIFT EMAC_DMA_CH0_STATUS_AIS_SHIFT #define GMAC_DMA_CH0_STATUS_AIS_WIDTH EMAC_DMA_CH0_STATUS_AIS_WIDTH #define GMAC_DMA_CH0_STATUS_AIS(x) EMAC_DMA_CH0_STATUS_AIS(x) #define GMAC_DMA_CH0_STATUS_NIS_MASK EMAC_DMA_CH0_STATUS_NIS_MASK #define GMAC_DMA_CH0_STATUS_NIS_SHIFT EMAC_DMA_CH0_STATUS_NIS_SHIFT #define GMAC_DMA_CH0_STATUS_NIS_WIDTH EMAC_DMA_CH0_STATUS_NIS_WIDTH #define GMAC_DMA_CH0_STATUS_NIS(x) EMAC_DMA_CH0_STATUS_NIS(x) #define GMAC_DMA_CH0_STATUS_TEB_MASK EMAC_DMA_CH0_STATUS_TEB_MASK #define GMAC_DMA_CH0_STATUS_TEB_SHIFT EMAC_DMA_CH0_STATUS_TEB_SHIFT #define GMAC_DMA_CH0_STATUS_TEB_WIDTH EMAC_DMA_CH0_STATUS_TEB_WIDTH #define GMAC_DMA_CH0_STATUS_TEB(x) EMAC_DMA_CH0_STATUS_TEB(x) #define GMAC_DMA_CH0_STATUS_REB_MASK EMAC_DMA_CH0_STATUS_REB_MASK #define GMAC_DMA_CH0_STATUS_REB_SHIFT EMAC_DMA_CH0_STATUS_REB_SHIFT #define GMAC_DMA_CH0_STATUS_REB_WIDTH EMAC_DMA_CH0_STATUS_REB_WIDTH #define GMAC_DMA_CH0_STATUS_REB(x) EMAC_DMA_CH0_STATUS_REB(x) /*! @} */ /*! @name DMA_CH0_MISS_FRAME_CNT - */ /*! @{ */ #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_WIDTH EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_WIDTH #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC(x) EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(x) #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_MASK EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_MASK #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_SHIFT EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_SHIFT #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_WIDTH EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_WIDTH #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFCO(x) EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO(x) /*! @} */ /*! @name DMA_CH0_RXP_ACCEPT_CNT - */ /*! @{ */ #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_WIDTH EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_WIDTH #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(x) EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(x) #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_MASK EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_MASK #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_SHIFT EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_SHIFT #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_WIDTH EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_WIDTH #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF(x) EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF(x) /*! @} */ /*! @name DMA_CH0_RX_ERI_CNT - */ /*! @{ */ #define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK #define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT #define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_WIDTH EMAC_DMA_CH0_RX_ERI_CNT_ECNT_WIDTH #define GMAC_DMA_CH0_RX_ERI_CNT_ECNT(x) EMAC_DMA_CH0_RX_ERI_CNT_ECNT(x) /*! @} */ /*! @name DMA_CH1_CONTROL - */ /*! @{ */ #define GMAC_DMA_CH1_CONTROL_PBLx8_MASK EMAC_DMA_CH1_CONTROL_PBLx8_MASK #define GMAC_DMA_CH1_CONTROL_PBLx8_SHIFT EMAC_DMA_CH1_CONTROL_PBLx8_SHIFT #define GMAC_DMA_CH1_CONTROL_PBLx8_WIDTH EMAC_DMA_CH1_CONTROL_PBLx8_WIDTH #define GMAC_DMA_CH1_CONTROL_PBLx8(x) EMAC_DMA_CH1_CONTROL_PBLx8(x) #define GMAC_DMA_CH1_CONTROL_DSL_MASK EMAC_DMA_CH1_CONTROL_DSL_MASK #define GMAC_DMA_CH1_CONTROL_DSL_SHIFT EMAC_DMA_CH1_CONTROL_DSL_SHIFT #define GMAC_DMA_CH1_CONTROL_DSL_WIDTH EMAC_DMA_CH1_CONTROL_DSL_WIDTH #define GMAC_DMA_CH1_CONTROL_DSL(x) EMAC_DMA_CH1_CONTROL_DSL(x) /*! @} */ /*! @name DMA_CH1_TX_CONTROL - */ /*! @{ */ #define GMAC_DMA_CH1_TX_CONTROL_ST_MASK EMAC_DMA_CH1_TX_CONTROL_ST_MASK #define GMAC_DMA_CH1_TX_CONTROL_ST_SHIFT EMAC_DMA_CH1_TX_CONTROL_ST_SHIFT #define GMAC_DMA_CH1_TX_CONTROL_ST_WIDTH EMAC_DMA_CH1_TX_CONTROL_ST_WIDTH #define GMAC_DMA_CH1_TX_CONTROL_ST(x) EMAC_DMA_CH1_TX_CONTROL_ST(x) #define GMAC_DMA_CH1_TX_CONTROL_TCW_MASK EMAC_DMA_CH1_TX_CONTROL_TCW_MASK #define GMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT #define GMAC_DMA_CH1_TX_CONTROL_TCW_WIDTH EMAC_DMA_CH1_TX_CONTROL_TCW_WIDTH #define GMAC_DMA_CH1_TX_CONTROL_TCW(x) EMAC_DMA_CH1_TX_CONTROL_TCW(x) #define GMAC_DMA_CH1_TX_CONTROL_OSF_MASK EMAC_DMA_CH1_TX_CONTROL_OSF_MASK #define GMAC_DMA_CH1_TX_CONTROL_OSF_SHIFT EMAC_DMA_CH1_TX_CONTROL_OSF_SHIFT #define GMAC_DMA_CH1_TX_CONTROL_OSF_WIDTH EMAC_DMA_CH1_TX_CONTROL_OSF_WIDTH #define GMAC_DMA_CH1_TX_CONTROL_OSF(x) EMAC_DMA_CH1_TX_CONTROL_OSF(x) #define GMAC_DMA_CH1_TX_CONTROL_TxPBL_MASK EMAC_DMA_CH1_TX_CONTROL_TxPBL_MASK #define GMAC_DMA_CH1_TX_CONTROL_TxPBL_SHIFT EMAC_DMA_CH1_TX_CONTROL_TxPBL_SHIFT #define GMAC_DMA_CH1_TX_CONTROL_TxPBL_WIDTH EMAC_DMA_CH1_TX_CONTROL_TxPBL_WIDTH #define GMAC_DMA_CH1_TX_CONTROL_TxPBL(x) EMAC_DMA_CH1_TX_CONTROL_TxPBL(x) #define GMAC_DMA_CH1_TX_CONTROL_ETIC_MASK EMAC_DMA_CH1_TX_CONTROL_ETIC_MASK #define GMAC_DMA_CH1_TX_CONTROL_ETIC_SHIFT EMAC_DMA_CH1_TX_CONTROL_ETIC_SHIFT #define GMAC_DMA_CH1_TX_CONTROL_ETIC_WIDTH EMAC_DMA_CH1_TX_CONTROL_ETIC_WIDTH #define GMAC_DMA_CH1_TX_CONTROL_ETIC(x) EMAC_DMA_CH1_TX_CONTROL_ETIC(x) #define GMAC_DMA_CH1_TX_CONTROL_EDSE_MASK EMAC_DMA_CH1_TX_CONTROL_EDSE_MASK #define GMAC_DMA_CH1_TX_CONTROL_EDSE_SHIFT EMAC_DMA_CH1_TX_CONTROL_EDSE_SHIFT #define GMAC_DMA_CH1_TX_CONTROL_EDSE_WIDTH EMAC_DMA_CH1_TX_CONTROL_EDSE_WIDTH #define GMAC_DMA_CH1_TX_CONTROL_EDSE(x) EMAC_DMA_CH1_TX_CONTROL_EDSE(x) /*! @} */ /*! @name DMA_CH1_RX_CONTROL - */ /*! @{ */ #define GMAC_DMA_CH1_RX_CONTROL_SR_MASK EMAC_DMA_CH1_RX_CONTROL_SR_MASK #define GMAC_DMA_CH1_RX_CONTROL_SR_SHIFT EMAC_DMA_CH1_RX_CONTROL_SR_SHIFT #define GMAC_DMA_CH1_RX_CONTROL_SR_WIDTH EMAC_DMA_CH1_RX_CONTROL_SR_WIDTH #define GMAC_DMA_CH1_RX_CONTROL_SR(x) EMAC_DMA_CH1_RX_CONTROL_SR(x) #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_MASK EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_MASK #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_SHIFT EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_SHIFT #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_WIDTH EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_WIDTH #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0(x) EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0(x) #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_MASK EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_MASK #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_SHIFT EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_SHIFT #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_WIDTH EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_WIDTH #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y(x) EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y(x) #define GMAC_DMA_CH1_RX_CONTROL_RxPBL_MASK EMAC_DMA_CH1_RX_CONTROL_RxPBL_MASK #define GMAC_DMA_CH1_RX_CONTROL_RxPBL_SHIFT EMAC_DMA_CH1_RX_CONTROL_RxPBL_SHIFT #define GMAC_DMA_CH1_RX_CONTROL_RxPBL_WIDTH EMAC_DMA_CH1_RX_CONTROL_RxPBL_WIDTH #define GMAC_DMA_CH1_RX_CONTROL_RxPBL(x) EMAC_DMA_CH1_RX_CONTROL_RxPBL(x) #define GMAC_DMA_CH1_RX_CONTROL_ERIC_MASK EMAC_DMA_CH1_RX_CONTROL_ERIC_MASK #define GMAC_DMA_CH1_RX_CONTROL_ERIC_SHIFT EMAC_DMA_CH1_RX_CONTROL_ERIC_SHIFT #define GMAC_DMA_CH1_RX_CONTROL_ERIC_WIDTH EMAC_DMA_CH1_RX_CONTROL_ERIC_WIDTH #define GMAC_DMA_CH1_RX_CONTROL_ERIC(x) EMAC_DMA_CH1_RX_CONTROL_ERIC(x) #define GMAC_DMA_CH1_RX_CONTROL_RPF_MASK EMAC_DMA_CH1_RX_CONTROL_RPF_MASK #define GMAC_DMA_CH1_RX_CONTROL_RPF_SHIFT EMAC_DMA_CH1_RX_CONTROL_RPF_SHIFT #define GMAC_DMA_CH1_RX_CONTROL_RPF_WIDTH EMAC_DMA_CH1_RX_CONTROL_RPF_WIDTH #define GMAC_DMA_CH1_RX_CONTROL_RPF(x) EMAC_DMA_CH1_RX_CONTROL_RPF(x) /*! @} */ /*! @name DMA_CH1_TXDESC_LIST_ADDRESS - */ /*! @{ */ #define GMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK #define GMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT #define GMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_WIDTH EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_WIDTH #define GMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(x) EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(x) /*! @} */ /*! @name DMA_CH1_RXDESC_LIST_ADDRESS - */ /*! @{ */ #define GMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK #define GMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT #define GMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_WIDTH EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_WIDTH #define GMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(x) EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(x) /*! @} */ /*! @name DMA_CH1_TXDESC_TAIL_POINTER - */ /*! @{ */ #define GMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK #define GMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT #define GMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_WIDTH EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_WIDTH #define GMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(x) EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(x) /*! @} */ /*! @name DMA_CH1_RXDESC_TAIL_POINTER - */ /*! @{ */ #define GMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK #define GMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT #define GMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_WIDTH EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_WIDTH #define GMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(x) EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(x) /*! @} */ /*! @name DMA_CH1_TXDESC_RING_LENGTH - */ /*! @{ */ #define GMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK #define GMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT #define GMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_WIDTH EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_WIDTH #define GMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(x) EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(x) /*! @} */ /*! @name DMA_CH1_RXDESC_RING_LENGTH - */ /*! @{ */ #define GMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK #define GMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT #define GMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_WIDTH EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_WIDTH #define GMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(x) EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(x) /*! @} */ /*! @name DMA_CH1_INTERRUPT_ENABLE - */ /*! @{ */ #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TIE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RIE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RSE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_AIE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE(x) #define GMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_MASK EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_MASK #define GMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_SHIFT #define GMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_WIDTH #define GMAC_DMA_CH1_INTERRUPT_ENABLE_NIE(x) EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE(x) /*! @} */ /*! @name DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER - */ /*! @{ */ #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) /*! @} */ /*! @name DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS - */ /*! @{ */ #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) /*! @} */ /*! @name DMA_CH1_CURRENT_APP_TXDESC - */ /*! @{ */ #define GMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK #define GMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT #define GMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH #define GMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(x) EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(x) /*! @} */ /*! @name DMA_CH1_CURRENT_APP_RXDESC - */ /*! @{ */ #define GMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK #define GMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT #define GMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH #define GMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(x) EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(x) /*! @} */ /*! @name DMA_CH1_CURRENT_APP_TXBUFFER - */ /*! @{ */ #define GMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK #define GMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT #define GMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH #define GMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) /*! @} */ /*! @name DMA_CH1_CURRENT_APP_RXBUFFER - */ /*! @{ */ #define GMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK #define GMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT #define GMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH #define GMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) /*! @} */ /*! @name DMA_CH1_STATUS - */ /*! @{ */ #define GMAC_DMA_CH1_STATUS_TI_MASK EMAC_DMA_CH1_STATUS_TI_MASK #define GMAC_DMA_CH1_STATUS_TI_SHIFT EMAC_DMA_CH1_STATUS_TI_SHIFT #define GMAC_DMA_CH1_STATUS_TI_WIDTH EMAC_DMA_CH1_STATUS_TI_WIDTH #define GMAC_DMA_CH1_STATUS_TI(x) EMAC_DMA_CH1_STATUS_TI(x) #define GMAC_DMA_CH1_STATUS_TPS_MASK EMAC_DMA_CH1_STATUS_TPS_MASK #define GMAC_DMA_CH1_STATUS_TPS_SHIFT EMAC_DMA_CH1_STATUS_TPS_SHIFT #define GMAC_DMA_CH1_STATUS_TPS_WIDTH EMAC_DMA_CH1_STATUS_TPS_WIDTH #define GMAC_DMA_CH1_STATUS_TPS(x) EMAC_DMA_CH1_STATUS_TPS(x) #define GMAC_DMA_CH1_STATUS_TBU_MASK EMAC_DMA_CH1_STATUS_TBU_MASK #define GMAC_DMA_CH1_STATUS_TBU_SHIFT EMAC_DMA_CH1_STATUS_TBU_SHIFT #define GMAC_DMA_CH1_STATUS_TBU_WIDTH EMAC_DMA_CH1_STATUS_TBU_WIDTH #define GMAC_DMA_CH1_STATUS_TBU(x) EMAC_DMA_CH1_STATUS_TBU(x) #define GMAC_DMA_CH1_STATUS_RI_MASK EMAC_DMA_CH1_STATUS_RI_MASK #define GMAC_DMA_CH1_STATUS_RI_SHIFT EMAC_DMA_CH1_STATUS_RI_SHIFT #define GMAC_DMA_CH1_STATUS_RI_WIDTH EMAC_DMA_CH1_STATUS_RI_WIDTH #define GMAC_DMA_CH1_STATUS_RI(x) EMAC_DMA_CH1_STATUS_RI(x) #define GMAC_DMA_CH1_STATUS_RBU_MASK EMAC_DMA_CH1_STATUS_RBU_MASK #define GMAC_DMA_CH1_STATUS_RBU_SHIFT EMAC_DMA_CH1_STATUS_RBU_SHIFT #define GMAC_DMA_CH1_STATUS_RBU_WIDTH EMAC_DMA_CH1_STATUS_RBU_WIDTH #define GMAC_DMA_CH1_STATUS_RBU(x) EMAC_DMA_CH1_STATUS_RBU(x) #define GMAC_DMA_CH1_STATUS_RPS_MASK EMAC_DMA_CH1_STATUS_RPS_MASK #define GMAC_DMA_CH1_STATUS_RPS_SHIFT EMAC_DMA_CH1_STATUS_RPS_SHIFT #define GMAC_DMA_CH1_STATUS_RPS_WIDTH EMAC_DMA_CH1_STATUS_RPS_WIDTH #define GMAC_DMA_CH1_STATUS_RPS(x) EMAC_DMA_CH1_STATUS_RPS(x) #define GMAC_DMA_CH1_STATUS_RWT_MASK EMAC_DMA_CH1_STATUS_RWT_MASK #define GMAC_DMA_CH1_STATUS_RWT_SHIFT EMAC_DMA_CH1_STATUS_RWT_SHIFT #define GMAC_DMA_CH1_STATUS_RWT_WIDTH EMAC_DMA_CH1_STATUS_RWT_WIDTH #define GMAC_DMA_CH1_STATUS_RWT(x) EMAC_DMA_CH1_STATUS_RWT(x) #define GMAC_DMA_CH1_STATUS_ETI_MASK EMAC_DMA_CH1_STATUS_ETI_MASK #define GMAC_DMA_CH1_STATUS_ETI_SHIFT EMAC_DMA_CH1_STATUS_ETI_SHIFT #define GMAC_DMA_CH1_STATUS_ETI_WIDTH EMAC_DMA_CH1_STATUS_ETI_WIDTH #define GMAC_DMA_CH1_STATUS_ETI(x) EMAC_DMA_CH1_STATUS_ETI(x) #define GMAC_DMA_CH1_STATUS_ERI_MASK EMAC_DMA_CH1_STATUS_ERI_MASK #define GMAC_DMA_CH1_STATUS_ERI_SHIFT EMAC_DMA_CH1_STATUS_ERI_SHIFT #define GMAC_DMA_CH1_STATUS_ERI_WIDTH EMAC_DMA_CH1_STATUS_ERI_WIDTH #define GMAC_DMA_CH1_STATUS_ERI(x) EMAC_DMA_CH1_STATUS_ERI(x) #define GMAC_DMA_CH1_STATUS_FBE_MASK EMAC_DMA_CH1_STATUS_FBE_MASK #define GMAC_DMA_CH1_STATUS_FBE_SHIFT EMAC_DMA_CH1_STATUS_FBE_SHIFT #define GMAC_DMA_CH1_STATUS_FBE_WIDTH EMAC_DMA_CH1_STATUS_FBE_WIDTH #define GMAC_DMA_CH1_STATUS_FBE(x) EMAC_DMA_CH1_STATUS_FBE(x) #define GMAC_DMA_CH1_STATUS_CDE_MASK EMAC_DMA_CH1_STATUS_CDE_MASK #define GMAC_DMA_CH1_STATUS_CDE_SHIFT EMAC_DMA_CH1_STATUS_CDE_SHIFT #define GMAC_DMA_CH1_STATUS_CDE_WIDTH EMAC_DMA_CH1_STATUS_CDE_WIDTH #define GMAC_DMA_CH1_STATUS_CDE(x) EMAC_DMA_CH1_STATUS_CDE(x) #define GMAC_DMA_CH1_STATUS_AIS_MASK EMAC_DMA_CH1_STATUS_AIS_MASK #define GMAC_DMA_CH1_STATUS_AIS_SHIFT EMAC_DMA_CH1_STATUS_AIS_SHIFT #define GMAC_DMA_CH1_STATUS_AIS_WIDTH EMAC_DMA_CH1_STATUS_AIS_WIDTH #define GMAC_DMA_CH1_STATUS_AIS(x) EMAC_DMA_CH1_STATUS_AIS(x) #define GMAC_DMA_CH1_STATUS_NIS_MASK EMAC_DMA_CH1_STATUS_NIS_MASK #define GMAC_DMA_CH1_STATUS_NIS_SHIFT EMAC_DMA_CH1_STATUS_NIS_SHIFT #define GMAC_DMA_CH1_STATUS_NIS_WIDTH EMAC_DMA_CH1_STATUS_NIS_WIDTH #define GMAC_DMA_CH1_STATUS_NIS(x) EMAC_DMA_CH1_STATUS_NIS(x) #define GMAC_DMA_CH1_STATUS_TEB_MASK EMAC_DMA_CH1_STATUS_TEB_MASK #define GMAC_DMA_CH1_STATUS_TEB_SHIFT EMAC_DMA_CH1_STATUS_TEB_SHIFT #define GMAC_DMA_CH1_STATUS_TEB_WIDTH EMAC_DMA_CH1_STATUS_TEB_WIDTH #define GMAC_DMA_CH1_STATUS_TEB(x) EMAC_DMA_CH1_STATUS_TEB(x) #define GMAC_DMA_CH1_STATUS_REB_MASK EMAC_DMA_CH1_STATUS_REB_MASK #define GMAC_DMA_CH1_STATUS_REB_SHIFT EMAC_DMA_CH1_STATUS_REB_SHIFT #define GMAC_DMA_CH1_STATUS_REB_WIDTH EMAC_DMA_CH1_STATUS_REB_WIDTH #define GMAC_DMA_CH1_STATUS_REB(x) EMAC_DMA_CH1_STATUS_REB(x) /*! @} */ /*! @name DMA_CH1_MISS_FRAME_CNT - */ /*! @{ */ #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFC_WIDTH EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_WIDTH #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFC(x) EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(x) #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_MASK EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_MASK #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_SHIFT EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_SHIFT #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_WIDTH EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_WIDTH #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFCO(x) EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO(x) /*! @} */ /*! @name DMA_CH1_RXP_ACCEPT_CNT - */ /*! @{ */ #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_WIDTH EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_WIDTH #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(x) EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(x) #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_MASK EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_MASK #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_SHIFT EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_SHIFT #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_WIDTH EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_WIDTH #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF(x) EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF(x) /*! @} */ /*! @name DMA_CH1_RX_ERI_CNT - */ /*! @{ */ #define GMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK #define GMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT #define GMAC_DMA_CH1_RX_ERI_CNT_ECNT_WIDTH EMAC_DMA_CH1_RX_ERI_CNT_ECNT_WIDTH #define GMAC_DMA_CH1_RX_ERI_CNT_ECNT(x) EMAC_DMA_CH1_RX_ERI_CNT_ECNT(x) /*! @} */ /*! * @} */ /* end of group GMAC_Register_Masks */ #ifdef __cplusplus } #endif /** @} */ #endif /* EMAC_IP_WRAPPER_H */