/* * NOTE: File generated by lpc_cfg_utils.py * from LPC51U68JBD64/signal_configuration.xml * * */ #ifndef _ZEPHYR_DTS_BINDING_LPC51U68JBD64_ #define _ZEPHYR_DTS_BINDING_LPC51U68JBD64_ #define IOCON_MUX(offset, type, mux) \ (((offset & 0xFFF) << 20) | \ (((type) & 0x3) << 18) | \ (((mux) & 0xF) << 0)) #define IOCON_TYPE_D 0x0 #define IOCON_TYPE_I 0x1 #define IOCON_TYPE_A 0x2 #define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define CTIMER0_CAPTURE0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ #define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define FC0_RXD_SDA_MOSI_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ #define FC3_CTS_SDA_SSEL0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ #define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ #define SCT0_OUT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ #define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ #define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define FC0_TXD_SCL_MISO_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ #define FC3_RTS_SCL_SSEL1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ #define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ #define SCT0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ #define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define FC0_CTS_SDA_SSEL0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ #define FC2_SSEL3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ #define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ #define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define CTIMER1_MATCH3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ #define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define FC0_RTS_SCL_SSEL1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ #define FC2_SSEL2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ #define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ #define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ #define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define FC0_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ #define FC3_SSEL2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ #define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ #define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define CTIMER0_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ #define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define FC6_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ #define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ #define SCT0_OUT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ #define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define CTIMER0_MATCH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ #define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define FC6_TXD_SCL_MISO_WS_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ #define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ #define UTICK0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ #define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define CTIMER0_CAPTURE2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ #define CTIMER0_MATCH2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ #define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define FC6_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ #define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ #define SCT0_OUT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ #define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define CTIMER0_MATCH3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ #define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define FC2_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ #define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ #define SCT0_OUT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ #define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define CTIMER3_CAPTURE0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ #define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define FC2_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ #define FC3_CTS_SDA_SSEL0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ #define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ #define SCT0_OUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ #define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define CTIMER3_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ #define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define FC2_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ #define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ #define SCT0_OUT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ #define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define FC3_SCK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ #define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ #define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ #define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define FC3_RXD_SDA_MOSI_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ #define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 2) /* PIO0_12 */ #define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ #define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define FC3_TXD_SCL_MISO_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ #define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ #define SCT0_OUT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ #define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define FC1_SCK_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 5) /* PIO0_14 */ #define FC3_CTS_SDA_SSEL0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ #define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ #define SCT0_OUT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ #define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define FC3_RTS_SCL_SSEL1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ #define FC4_SCK_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 5) /* PIO0_15 */ #define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ #define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define CTIMER3_MATCH1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ #define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define FC3_SSEL2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ #define FC6_CTS_SDA_SSEL0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ #define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ #define SWCLK_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 5) /* PIO0_16 */ #define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define CTIMER3_MATCH2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ #define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define FC3_SSEL3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ #define FC6_RTS_SCL_SSEL1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ #define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ #define SWDIO_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 5) /* PIO0_17 */ #define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define CTIMER0_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ #define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define FC5_TXD_SCL_MISO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ #define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ #define SCT0_OUT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ #define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define CTIMER0_MATCH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ #define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define FC5_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ #define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ #define SCT0_OUT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ #define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ #define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define FC0_SCK_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ #define FC5_RXD_SDA_MOSI_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ #define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ #define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define CLKOUT_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ #define CTIMER3_MATCH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ #define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define FC0_TXD_SCL_MISO_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ #define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ #define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define CLKIN_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ #define CTIMER3_MATCH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ #define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define FC0_RXD_SDA_MOSI_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ #define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ #define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define CTIMER0_CAPTURE0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ #define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define FC1_RTS_SCL_SSEL1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ #define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ #define UTICK0_CAPTURE1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ #define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ #define CTIMER0_MATCH0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 5) /* PIO0_24 */ #define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define FC1_CTS_SDA_SSEL0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ #define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ #define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ #define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 5) /* PIO0_25 */ #define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define FC4_RTS_SCL_SSEL1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ #define FC6_CTS_SDA_SSEL0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ #define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ #define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ #define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define FC4_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ #define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ #define ADC0_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define CTIMER0_CAPTURE1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ #define CTIMER0_MATCH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ #define CTIMER0_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ #define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define FC1_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ #define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ #define SCT0_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ #define ADC0_CH1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define CTIMER0_CAPTURE2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ #define CTIMER0_MATCH2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ #define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define FC1_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ #define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ #define SCT0_OUT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ #define ADC0_CH2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define CTIMER0_CAPTURE3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ #define CTIMER0_MATCH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 6) /* PIO0_31 */ #define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define FC2_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ #define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ #define ADC0_CH3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ #define CTIMER3_MATCH1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ #define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define FC2_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ #define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ #define ADC0_CH4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define FC4_TXD_SCL_MISO_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ #define FC5_SSEL2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ #define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ #define SCT0_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ #define ADC0_CH5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define FC4_RXD_SDA_MOSI_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ #define FC5_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ #define FC7_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 2) /* PIO1_2 */ #define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define MCLK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ #define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ #define SCT0_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ #define ADC0_CH6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define CTIMER0_CAPTURE1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ #define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define FC3_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ #define FC7_SSEL2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 2) /* PIO1_3 */ #define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ #define SCT0_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ #define USB0_UP_LED_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ #define ADC0_CH7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define CTIMER0_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ #define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define FC3_TXD_SCL_MISO_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ #define FC7_RTS_SCL_SSEL1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ #define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ #define SCT0_OUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ #define ADC0_CH8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define CTIMER1_CAPTURE0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ #define CTIMER1_MATCH3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 5) /* PIO1_5 */ #define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define FC7_CTS_SDA_SSEL0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ #define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ #define USB0_FRAME_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 7) /* PIO1_5 */ #define ADC0_CH9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define CTIMER1_CAPTURE2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ #define CTIMER1_MATCH2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 5) /* PIO1_6 */ #define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define FC7_SCK_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ #define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ #define USB0_VBUS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 7) /* PIO1_6 */ #define ADC0_CH10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define CTIMER1_CAPTURE2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 5) /* PIO1_7 */ #define CTIMER1_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ #define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define FC7_RXD_SDA_MOSI_DATA_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ #define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ #define ADC0_CH11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define CTIMER1_CAPTURE3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ #define CTIMER1_MATCH3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 3) /* PIO1_8 */ #define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define FC7_TXD_SCL_MISO_WS_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ #define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ #define ADC0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ #define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define FC3_RXD_SDA_MOSI_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ #define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ #define USB0_UP_LED_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ #define ADC0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define FC1_SCK_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ #define FC6_TXD_SCL_MISO_WS_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ #define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ #define SCT0_OUT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ #define USB0_FRAME_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 7) /* PIO1_10 */ #define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ #define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define FC4_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ #define FC6_RTS_SCL_SSEL1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ #define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ #define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ #define ADC0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define CTIMER1_MATCH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ #define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define FC5_RXD_SDA_MOSI_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ #define FC7_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ #define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ #define UTICK0_CAPTURE2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ #define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define CTIMER1_MATCH1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ #define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define FC5_TXD_SCL_MISO_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ #define FC7_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ #define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ #define ADC0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define FC2_RXD_SDA_MOSI_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ #define FC7_TXD_SCL_MISO_WS_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ #define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ #define SCT0_OUT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ #define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ #define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define FC7_CTS_SDA_SSEL0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ #define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ #define SCT0_OUT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ #define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define CTIMER0_CAPTURE0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ #define CTIMER0_MATCH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ #define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define FC7_RTS_SCL_SSEL1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ #define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ #define ADC0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define MCLK_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ #define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ #define UTICK0_CAPTURE3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ #endif