/*
 * NOTE: Autogenerated file by kinetis_signal2dts.py
 *       for MKE18F256VLL16/signal_configuration.xml
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Pin nodes are of the form:
 *
 *	<SIGNAL[0..n]>: <signal[0]> {
 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
 *	};
 */

&porta {
	ADC0_SE0_PTA0: ACMP0_IN0_PTA0: adc0_se0_pta0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTA0: GPIOA_PTA0: gpioa_pta0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	FTM2_CH1_PTA0: ftm2_ch1_pta0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	LPI2C0_SCLS_PTA0: lpi2c0_scls_pta0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	FXIO_D2_PTA0: fxio_d2_pta0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	FTM2_QD_PHA_PTA0: ftm2_qd_pha_pta0 {
		nxp,kinetis-port-pins = < 0 5 >;
	};
	LPUART0_CTS_PTA0: lpuart0_cts_pta0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	TRGMUX_OUT3_PTA0: trgmux_out3_pta0 {
		nxp,kinetis-port-pins = < 0 7 >;
	};
	ADC0_SE1_PTA1: ACMP0_IN1_PTA1: adc0_se1_pta1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTA1: GPIOA_PTA1: gpioa_pta1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	FTM1_CH1_PTA1: ftm1_ch1_pta1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	LPI2C0_SDAS_PTA1: lpi2c0_sdas_pta1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	FXIO_D3_PTA1: fxio_d3_pta1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	FTM1_QD_PHA_PTA1: ftm1_qd_pha_pta1 {
		nxp,kinetis-port-pins = < 1 5 >;
	};
	LPUART0_RTS_PTA1: lpuart0_rts_pta1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	TRGMUX_OUT0_PTA1: trgmux_out0_pta1 {
		nxp,kinetis-port-pins = < 1 7 >;
	};
	ADC1_SE0_PTA2: adc1_se0_pta2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTA2: GPIOA_PTA2: gpioa_pta2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	FTM3_CH0_PTA2: ftm3_ch0_pta2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	LPI2C0_SDA_PTA2: lpi2c0_sda_pta2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	EWM_OUT_b_PTA2: ewm_out_b_pta2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	LPUART0_RX_PTA2: lpuart0_rx_pta2 {
		nxp,kinetis-port-pins = < 2 6 >;
	};
	ADC1_SE1_PTA3: adc1_se1_pta3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTA3: GPIOA_PTA3: gpioa_pta3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	FTM3_CH1_PTA3: ftm3_ch1_pta3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	LPI2C0_SCL_PTA3: lpi2c0_scl_pta3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	EWM_IN_PTA3: ewm_in_pta3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	LPUART0_TX_PTA3: lpuart0_tx_pta3 {
		nxp,kinetis-port-pins = < 3 6 >;
	};
	PTA4: GPIOA_PTA4: gpioa_pta4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	ACMP0_OUT_PTA4: acmp0_out_pta4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	EWM_OUT_b_PTA4: ewm_out_b_pta4 {
		nxp,kinetis-port-pins = < 4 5 >;
	};
	JTAG_TMS_PTA4: SWD_DIO_PTA4: jtag_tms_pta4 {
		nxp,kinetis-port-pins = < 4 7 >;
	};
	PTA5: GPIOA_PTA5: gpioa_pta5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	TCLK1_PTA5: tclk1_pta5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	JTAG_TRST_b_PTA5: jtag_trst_b_pta5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	RESET_b_PTA5: reset_b_pta5 {
		nxp,kinetis-port-pins = < 5 7 >;
	};
	ADC0_SE2_PTA6: ACMP1_IN0_PTA6: adc0_se2_pta6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTA6: GPIOA_PTA6: gpioa_pta6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	FTM0_FLT1_PTA6: ftm0_flt1_pta6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	LPSPI1_PCS1_PTA6: lpspi1_pcs1_pta6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	LPUART1_CTS_PTA6: lpuart1_cts_pta6 {
		nxp,kinetis-port-pins = < 6 6 >;
	};
	ADC0_SE3_PTA7: ACMP1_IN1_PTA7: adc0_se3_pta7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTA7: GPIOA_PTA7: gpioa_pta7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	FTM0_FLT2_PTA7: ftm0_flt2_pta7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	RTC_CLKIN_PTA7: rtc_clkin_pta7 {
		nxp,kinetis-port-pins = < 7 4 >;
	};
	LPUART1_RTS_PTA7: lpuart1_rts_pta7 {
		nxp,kinetis-port-pins = < 7 6 >;
	};
	PTA8: GPIOA_PTA8: gpioa_pta8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	FXIO_D6_PTA8: fxio_d6_pta8 {
		nxp,kinetis-port-pins = < 8 4 >;
	};
	FTM3_FLT3_PTA8: ftm3_flt3_pta8 {
		nxp,kinetis-port-pins = < 8 5 >;
	};
	PTA9: GPIOA_PTA9: gpioa_pta9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	FXIO_D7_PTA9: fxio_d7_pta9 {
		nxp,kinetis-port-pins = < 9 4 >;
	};
	FTM3_FLT2_PTA9: ftm3_flt2_pta9 {
		nxp,kinetis-port-pins = < 9 5 >;
	};
	FTM1_FLT3_PTA9: ftm1_flt3_pta9 {
		nxp,kinetis-port-pins = < 9 6 >;
	};
	PTA10: GPIOA_PTA10: gpioa_pta10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	FTM1_CH4_PTA10: ftm1_ch4_pta10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	LPUART0_TX_PTA10: lpuart0_tx_pta10 {
		nxp,kinetis-port-pins = < 10 3 >;
	};
	FXIO_D0_PTA10: fxio_d0_pta10 {
		nxp,kinetis-port-pins = < 10 4 >;
	};
	JTAG_TDO_PTA10: noetm_Trace_SWO_PTA10: jtag_tdo_pta10 {
		nxp,kinetis-port-pins = < 10 7 >;
	};
	PTA11: GPIOA_PTA11: gpioa_pta11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	FTM1_CH5_PTA11: ftm1_ch5_pta11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	LPUART0_RX_PTA11: lpuart0_rx_pta11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	FXIO_D1_PTA11: fxio_d1_pta11 {
		nxp,kinetis-port-pins = < 11 4 >;
	};
	ADC2_SE5_PTA12: adc2_se5_pta12 {
		nxp,kinetis-port-pins = < 12 0 >;
	};
	PTA12: GPIOA_PTA12: gpioa_pta12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	FTM1_CH6_PTA12: ftm1_ch6_pta12 {
		nxp,kinetis-port-pins = < 12 2 >;
	};
	CAN1_RX_PTA12: can1_rx_pta12 {
		nxp,kinetis-port-pins = < 12 3 >;
	};
	LPI2C1_SDAS_PTA12: lpi2c1_sdas_pta12 {
		nxp,kinetis-port-pins = < 12 4 >;
	};
	ADC2_SE4_PTA13: adc2_se4_pta13 {
		nxp,kinetis-port-pins = < 13 0 >;
	};
	PTA13: GPIOA_PTA13: gpioa_pta13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	FTM1_CH7_PTA13: ftm1_ch7_pta13 {
		nxp,kinetis-port-pins = < 13 2 >;
	};
	CAN1_TX_PTA13: can1_tx_pta13 {
		nxp,kinetis-port-pins = < 13 3 >;
	};
	LPI2C1_SCLS_PTA13: lpi2c1_scls_pta13 {
		nxp,kinetis-port-pins = < 13 4 >;
	};
	PTA14: GPIOA_PTA14: gpioa_pta14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	FTM0_FLT0_PTA14: ftm0_flt0_pta14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	FTM3_FLT1_PTA14: ftm3_flt1_pta14 {
		nxp,kinetis-port-pins = < 14 3 >;
	};
	EWM_IN_PTA14: ewm_in_pta14 {
		nxp,kinetis-port-pins = < 14 4 >;
	};
	FTM1_FLT0_PTA14: ftm1_flt0_pta14 {
		nxp,kinetis-port-pins = < 14 6 >;
	};
	BUSOUT_PTA14: busout_pta14 {
		nxp,kinetis-port-pins = < 14 7 >;
	};
	ADC1_SE12_PTA15: adc1_se12_pta15 {
		nxp,kinetis-port-pins = < 15 0 >;
	};
	PTA15: GPIOA_PTA15: gpioa_pta15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	FTM1_CH2_PTA15: ftm1_ch2_pta15 {
		nxp,kinetis-port-pins = < 15 2 >;
	};
	LPSPI0_PCS3_PTA15: lpspi0_pcs3_pta15 {
		nxp,kinetis-port-pins = < 15 3 >;
	};
	ADC1_SE13_PTA16: adc1_se13_pta16 {
		nxp,kinetis-port-pins = < 16 0 >;
	};
	PTA16: GPIOA_PTA16: gpioa_pta16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	FTM1_CH3_PTA16: ftm1_ch3_pta16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	LPSPI1_PCS2_PTA16: lpspi1_pcs2_pta16 {
		nxp,kinetis-port-pins = < 16 3 >;
	};
	PTA17: GPIOA_PTA17: gpioa_pta17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	FTM0_CH6_PTA17: ftm0_ch6_pta17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	FTM3_FLT0_PTA17: ftm3_flt0_pta17 {
		nxp,kinetis-port-pins = < 17 3 >;
	};
	EWM_OUT_b_PTA17: ewm_out_b_pta17 {
		nxp,kinetis-port-pins = < 17 4 >;
	};
};

&portb {
	ADC0_SE4_PTB0: ADC1_SE14_PTB0: adc0_se4_ptb0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTB0: GPIOB_PTB0: gpiob_ptb0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	LPUART0_RX_PTB0: lpuart0_rx_ptb0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	LPSPI0_PCS0_PTB0: lpspi0_pcs0_ptb0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	LPTMR0_ALT3_PTB0: lptmr0_alt3_ptb0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	PWT_IN3_PTB0: pwt_in3_ptb0 {
		nxp,kinetis-port-pins = < 0 5 >;
	};
	ADC0_SE5_PTB1: ADC1_SE15_PTB1: adc0_se5_ptb1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTB1: GPIOB_PTB1: gpiob_ptb1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	LPUART0_TX_PTB1: lpuart0_tx_ptb1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	LPSPI0_SOUT_PTB1: lpspi0_sout_ptb1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	TCLK0_PTB1: tclk0_ptb1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	ADC0_SE6_PTB2: adc0_se6_ptb2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTB2: GPIOB_PTB2: gpiob_ptb2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	FTM1_CH0_PTB2: ftm1_ch0_ptb2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	LPSPI0_SCK_PTB2: lpspi0_sck_ptb2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	FTM1_QD_PHB_PTB2: ftm1_qd_phb_ptb2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	TRGMUX_IN3_PTB2: trgmux_in3_ptb2 {
		nxp,kinetis-port-pins = < 2 6 >;
	};
	ADC0_SE7_PTB3: adc0_se7_ptb3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTB3: GPIOB_PTB3: gpiob_ptb3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	FTM1_CH1_PTB3: ftm1_ch1_ptb3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	LPSPI0_SIN_PTB3: lpspi0_sin_ptb3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	FTM1_QD_PHA_PTB3: ftm1_qd_pha_ptb3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	TRGMUX_IN2_PTB3: trgmux_in2_ptb3 {
		nxp,kinetis-port-pins = < 3 6 >;
	};
	ACMP1_IN2_PTB4: acmp1_in2_ptb4 {
		nxp,kinetis-port-pins = < 4 0 >;
	};
	PTB4: GPIOB_PTB4: gpiob_ptb4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	FTM0_CH4_PTB4: ftm0_ch4_ptb4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	LPSPI0_SOUT_PTB4: lpspi0_sout_ptb4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	TRGMUX_IN1_PTB4: trgmux_in1_ptb4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	PTB5: GPIOB_PTB5: gpiob_ptb5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	FTM0_CH5_PTB5: ftm0_ch5_ptb5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	LPSPI0_PCS1_PTB5: lpspi0_pcs1_ptb5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	TRGMUX_IN0_PTB5: trgmux_in0_ptb5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	ACMP1_OUT_PTB5: acmp1_out_ptb5 {
		nxp,kinetis-port-pins = < 5 7 >;
	};
	XTAL_PTB6: xtal_ptb6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTB6: GPIOB_PTB6: gpiob_ptb6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	LPI2C0_SDA_PTB6: lpi2c0_sda_ptb6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	EXTAL_PTB7: extal_ptb7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTB7: GPIOB_PTB7: gpiob_ptb7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	LPI2C0_SCL_PTB7: lpi2c0_scl_ptb7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	ADC2_SE11_PTB8: adc2_se11_ptb8 {
		nxp,kinetis-port-pins = < 8 0 >;
	};
	PTB8: GPIOB_PTB8: gpiob_ptb8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	FTM3_CH0_PTB8: ftm3_ch0_ptb8 {
		nxp,kinetis-port-pins = < 8 2 >;
	};
	ADC2_SE10_PTB9: adc2_se10_ptb9 {
		nxp,kinetis-port-pins = < 9 0 >;
	};
	PTB9: GPIOB_PTB9: gpiob_ptb9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	FTM3_CH1_PTB9: ftm3_ch1_ptb9 {
		nxp,kinetis-port-pins = < 9 2 >;
	};
	LPI2C0_SCLS_PTB9: lpi2c0_scls_ptb9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	ADC2_SE9_PTB10: adc2_se9_ptb10 {
		nxp,kinetis-port-pins = < 10 0 >;
	};
	PTB10: GPIOB_PTB10: gpiob_ptb10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	FTM3_CH2_PTB10: ftm3_ch2_ptb10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	LPI2C0_SDAS_PTB10: lpi2c0_sdas_ptb10 {
		nxp,kinetis-port-pins = < 10 3 >;
	};
	ADC2_SE8_PTB11: adc2_se8_ptb11 {
		nxp,kinetis-port-pins = < 11 0 >;
	};
	PTB11: GPIOB_PTB11: gpiob_ptb11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	FTM3_CH3_PTB11: ftm3_ch3_ptb11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	LPI2C0_HREQ_PTB11: lpi2c0_hreq_ptb11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	ADC1_SE7_PTB12: adc1_se7_ptb12 {
		nxp,kinetis-port-pins = < 12 0 >;
	};
	PTB12: GPIOB_PTB12: gpiob_ptb12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	FTM0_CH0_PTB12: ftm0_ch0_ptb12 {
		nxp,kinetis-port-pins = < 12 2 >;
	};
	FTM3_FLT2_PTB12: ftm3_flt2_ptb12 {
		nxp,kinetis-port-pins = < 12 3 >;
	};
	ADC1_SE8_PTB13: ADC2_SE8_PTB13: adc1_se8_ptb13 {
		nxp,kinetis-port-pins = < 13 0 >;
	};
	PTB13: GPIOB_PTB13: gpiob_ptb13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	FTM0_CH1_PTB13: ftm0_ch1_ptb13 {
		nxp,kinetis-port-pins = < 13 2 >;
	};
	FTM3_FLT1_PTB13: ftm3_flt1_ptb13 {
		nxp,kinetis-port-pins = < 13 3 >;
	};
	ADC1_SE9_PTB14: ADC2_SE9_PTB14: adc1_se9_ptb14 {
		nxp,kinetis-port-pins = < 14 0 >;
	};
	PTB14: GPIOB_PTB14: gpiob_ptb14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	FTM0_CH2_PTB14: ftm0_ch2_ptb14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	LPSPI1_SCK_PTB14: lpspi1_sck_ptb14 {
		nxp,kinetis-port-pins = < 14 3 >;
	};
	ADC1_SE14_PTB15: adc1_se14_ptb15 {
		nxp,kinetis-port-pins = < 15 0 >;
	};
	PTB15: GPIOB_PTB15: gpiob_ptb15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	FTM0_CH3_PTB15: ftm0_ch3_ptb15 {
		nxp,kinetis-port-pins = < 15 2 >;
	};
	LPSPI1_SIN_PTB15: lpspi1_sin_ptb15 {
		nxp,kinetis-port-pins = < 15 3 >;
	};
	ADC1_SE15_PTB16: adc1_se15_ptb16 {
		nxp,kinetis-port-pins = < 16 0 >;
	};
	PTB16: GPIOB_PTB16: gpiob_ptb16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	FTM0_CH4_PTB16: ftm0_ch4_ptb16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	LPSPI1_SOUT_PTB16: lpspi1_sout_ptb16 {
		nxp,kinetis-port-pins = < 16 3 >;
	};
	ADC2_SE3_PTB17: adc2_se3_ptb17 {
		nxp,kinetis-port-pins = < 17 0 >;
	};
	PTB17: GPIOB_PTB17: gpiob_ptb17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	FTM0_CH5_PTB17: ftm0_ch5_ptb17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	LPSPI1_PCS3_PTB17: lpspi1_pcs3_ptb17 {
		nxp,kinetis-port-pins = < 17 3 >;
	};
};

&portc {
	ADC0_SE8_PTC0: ACMP1_IN4_PTC0: adc0_se8_ptc0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTC0: GPIOC_PTC0: gpioc_ptc0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	FTM0_CH0_PTC0: ftm0_ch0_ptc0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	FTM1_CH6_PTC0: ftm1_ch6_ptc0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	ADC0_SE9_PTC1: ACMP1_IN3_PTC1: adc0_se9_ptc1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTC1: GPIOC_PTC1: gpioc_ptc1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	FTM0_CH1_PTC1: ftm0_ch1_ptc1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	FTM1_CH7_PTC1: ftm1_ch7_ptc1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	ADC0_SE10_PTC2: ACMP0_IN5_PTC2: XTAL32_PTC2: adc0_se10_ptc2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTC2: GPIOC_PTC2: gpioc_ptc2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	FTM0_CH2_PTC2: ftm0_ch2_ptc2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	CAN0_RX_PTC2: can0_rx_ptc2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	ADC0_SE11_PTC3: ACMP0_IN4_PTC3: EXTAL32_PTC3: adc0_se11_ptc3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTC3: GPIOC_PTC3: gpioc_ptc3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	FTM0_CH3_PTC3: ftm0_ch3_ptc3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	CAN0_TX_PTC3: can0_tx_ptc3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	ACMP0_IN2_PTC4: acmp0_in2_ptc4 {
		nxp,kinetis-port-pins = < 4 0 >;
	};
	PTC4: GPIOC_PTC4: gpioc_ptc4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	FTM1_CH0_PTC4: ftm1_ch0_ptc4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	RTC_CLKOUT_PTC4: rtc_clkout_ptc4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	EWM_IN_PTC4: ewm_in_ptc4 {
		nxp,kinetis-port-pins = < 4 5 >;
	};
	FTM1_QD_PHB_PTC4: ftm1_qd_phb_ptc4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	JTAG_TCLK_PTC4: SWD_CLK_PTC4: jtag_tclk_ptc4 {
		nxp,kinetis-port-pins = < 4 7 >;
	};
	PTC5: GPIOC_PTC5: gpioc_ptc5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	FTM2_CH0_PTC5: ftm2_ch0_ptc5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	RTC_CLKOUT_PTC5: rtc_clkout_ptc5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	LPI2C1_HREQ_PTC5: lpi2c1_hreq_ptc5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	FTM2_QD_PHB_PTC5: ftm2_qd_phb_ptc5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	JTAG_TDI_PTC5: jtag_tdi_ptc5 {
		nxp,kinetis-port-pins = < 5 7 >;
	};
	ADC1_SE4_PTC6: adc1_se4_ptc6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTC6: GPIOC_PTC6: gpioc_ptc6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	LPUART1_RX_PTC6: lpuart1_rx_ptc6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	CAN1_RX_PTC6: can1_rx_ptc6 {
		nxp,kinetis-port-pins = < 6 3 >;
	};
	FTM3_CH2_PTC6: ftm3_ch2_ptc6 {
		nxp,kinetis-port-pins = < 6 4 >;
	};
	ADC1_SE5_PTC7: adc1_se5_ptc7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTC7: GPIOC_PTC7: gpioc_ptc7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	LPUART1_TX_PTC7: lpuart1_tx_ptc7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	CAN1_TX_PTC7: can1_tx_ptc7 {
		nxp,kinetis-port-pins = < 7 3 >;
	};
	FTM3_CH3_PTC7: ftm3_ch3_ptc7 {
		nxp,kinetis-port-pins = < 7 4 >;
	};
	ADC2_SE14_PTC8: adc2_se14_ptc8 {
		nxp,kinetis-port-pins = < 8 0 >;
	};
	PTC8: GPIOC_PTC8: gpioc_ptc8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	LPUART1_RX_PTC8: lpuart1_rx_ptc8 {
		nxp,kinetis-port-pins = < 8 2 >;
	};
	FTM1_FLT0_PTC8: ftm1_flt0_ptc8 {
		nxp,kinetis-port-pins = < 8 3 >;
	};
	LPUART0_CTS_PTC8: lpuart0_cts_ptc8 {
		nxp,kinetis-port-pins = < 8 6 >;
	};
	ADC2_SE15_PTC9: adc2_se15_ptc9 {
		nxp,kinetis-port-pins = < 9 0 >;
	};
	PTC9: GPIOC_PTC9: gpioc_ptc9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	LPUART1_TX_PTC9: lpuart1_tx_ptc9 {
		nxp,kinetis-port-pins = < 9 2 >;
	};
	FTM1_FLT1_PTC9: ftm1_flt1_ptc9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	LPUART0_RTS_PTC9: lpuart0_rts_ptc9 {
		nxp,kinetis-port-pins = < 9 6 >;
	};
	PTC10: GPIOC_PTC10: gpioc_ptc10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	FTM3_CH4_PTC10: ftm3_ch4_ptc10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	PTC11: GPIOC_PTC11: gpioc_ptc11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	FTM3_CH5_PTC11: ftm3_ch5_ptc11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	PTC12: GPIOC_PTC12: gpioc_ptc12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	FTM3_CH6_PTC12: ftm3_ch6_ptc12 {
		nxp,kinetis-port-pins = < 12 2 >;
	};
	FTM2_CH6_PTC12: ftm2_ch6_ptc12 {
		nxp,kinetis-port-pins = < 12 3 >;
	};
	PTC13: GPIOC_PTC13: gpioc_ptc13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	FTM3_CH7_PTC13: ftm3_ch7_ptc13 {
		nxp,kinetis-port-pins = < 13 2 >;
	};
	FTM2_CH7_PTC13: ftm2_ch7_ptc13 {
		nxp,kinetis-port-pins = < 13 3 >;
	};
	ADC0_SE12_PTC14: ACMP2_IN5_PTC14: adc0_se12_ptc14 {
		nxp,kinetis-port-pins = < 14 0 >;
	};
	PTC14: GPIOC_PTC14: gpioc_ptc14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	FTM1_CH2_PTC14: ftm1_ch2_ptc14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	ADC0_SE13_PTC15: ACMP2_IN4_PTC15: adc0_se13_ptc15 {
		nxp,kinetis-port-pins = < 15 0 >;
	};
	PTC15: GPIOC_PTC15: gpioc_ptc15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	FTM1_CH3_PTC15: ftm1_ch3_ptc15 {
		nxp,kinetis-port-pins = < 15 2 >;
	};
	ADC0_SE14_PTC16: adc0_se14_ptc16 {
		nxp,kinetis-port-pins = < 16 0 >;
	};
	PTC16: GPIOC_PTC16: gpioc_ptc16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	FTM1_FLT2_PTC16: ftm1_flt2_ptc16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	LPI2C1_SDAS_PTC16: lpi2c1_sdas_ptc16 {
		nxp,kinetis-port-pins = < 16 4 >;
	};
	ADC0_SE15_PTC17: adc0_se15_ptc17 {
		nxp,kinetis-port-pins = < 17 0 >;
	};
	PTC17: GPIOC_PTC17: gpioc_ptc17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	FTM1_FLT3_PTC17: ftm1_flt3_ptc17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	LPI2C1_SCLS_PTC17: lpi2c1_scls_ptc17 {
		nxp,kinetis-port-pins = < 17 4 >;
	};
};

&portd {
	ADC2_SE0_PTD0: adc2_se0_ptd0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTD0: GPIOD_PTD0: gpiod_ptd0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	FTM0_CH2_PTD0: ftm0_ch2_ptd0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	LPSPI1_SCK_PTD0: lpspi1_sck_ptd0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	FTM2_CH0_PTD0: ftm2_ch0_ptd0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	FXIO_D0_PTD0: fxio_d0_ptd0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	TRGMUX_OUT1_PTD0: trgmux_out1_ptd0 {
		nxp,kinetis-port-pins = < 0 7 >;
	};
	ADC2_SE1_PTD1: adc2_se1_ptd1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTD1: GPIOD_PTD1: gpiod_ptd1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	FTM0_CH3_PTD1: ftm0_ch3_ptd1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	LPSPI1_SIN_PTD1: lpspi1_sin_ptd1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	FTM2_CH1_PTD1: ftm2_ch1_ptd1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	FXIO_D1_PTD1: fxio_d1_ptd1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	TRGMUX_OUT2_PTD1: trgmux_out2_ptd1 {
		nxp,kinetis-port-pins = < 1 7 >;
	};
	ADC1_SE2_PTD2: adc1_se2_ptd2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTD2: GPIOD_PTD2: gpiod_ptd2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	FTM3_CH4_PTD2: ftm3_ch4_ptd2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	LPSPI1_SOUT_PTD2: lpspi1_sout_ptd2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	FXIO_D4_PTD2: fxio_d4_ptd2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	TRGMUX_IN5_PTD2: trgmux_in5_ptd2 {
		nxp,kinetis-port-pins = < 2 6 >;
	};
	ADC1_SE3_PTD3: adc1_se3_ptd3 {
		nxp,kinetis-port-pins = < 3 0 >;
	};
	PTD3: GPIOD_PTD3: gpiod_ptd3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	FTM3_CH5_PTD3: ftm3_ch5_ptd3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	LPSPI1_PCS0_PTD3: lpspi1_pcs0_ptd3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	FXIO_D5_PTD3: fxio_d5_ptd3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	TRGMUX_IN4_PTD3: trgmux_in4_ptd3 {
		nxp,kinetis-port-pins = < 3 6 >;
	};
	NMI_b_PTD3: nmi_b_ptd3 {
		nxp,kinetis-port-pins = < 3 7 >;
	};
	ADC1_SE6_PTD4: ACMP1_IN6_PTD4: adc1_se6_ptd4 {
		nxp,kinetis-port-pins = < 4 0 >;
	};
	PTD4: GPIOD_PTD4: gpiod_ptd4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	FTM0_FLT3_PTD4: ftm0_flt3_ptd4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	FTM3_FLT3_PTD4: ftm3_flt3_ptd4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	PTD5: GPIOD_PTD5: gpiod_ptd5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	FTM2_CH3_PTD5: ftm2_ch3_ptd5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	LPTMR0_ALT2_PTD5: lptmr0_alt2_ptd5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	FTM2_FLT1_PTD5: ftm2_flt1_ptd5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	PWT_IN2_PTD5: pwt_in2_ptd5 {
		nxp,kinetis-port-pins = < 5 5 >;
	};
	TRGMUX_IN7_PTD5: trgmux_in7_ptd5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	PTD6: GPIOD_PTD6: gpiod_ptd6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	LPUART2_RX_PTD6: lpuart2_rx_ptd6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	FTM2_FLT2_PTD6: ftm2_flt2_ptd6 {
		nxp,kinetis-port-pins = < 6 4 >;
	};
	PTD7: GPIOD_PTD7: gpiod_ptd7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	LPUART2_TX_PTD7: lpuart2_tx_ptd7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	FTM2_FLT3_PTD7: ftm2_flt3_ptd7 {
		nxp,kinetis-port-pins = < 7 4 >;
	};
	PTD8: GPIOD_PTD8: gpiod_ptd8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	LPI2C1_SDA_PTD8: lpi2c1_sda_ptd8 {
		nxp,kinetis-port-pins = < 8 2 >;
	};
	FTM2_FLT2_PTD8: ftm2_flt2_ptd8 {
		nxp,kinetis-port-pins = < 8 4 >;
	};
	FTM1_CH4_PTD8: ftm1_ch4_ptd8 {
		nxp,kinetis-port-pins = < 8 6 >;
	};
	ACMP1_IN5_PTD9: acmp1_in5_ptd9 {
		nxp,kinetis-port-pins = < 9 0 >;
	};
	PTD9: GPIOD_PTD9: gpiod_ptd9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	LPI2C1_SCL_PTD9: lpi2c1_scl_ptd9 {
		nxp,kinetis-port-pins = < 9 2 >;
	};
	FTM2_FLT3_PTD9: ftm2_flt3_ptd9 {
		nxp,kinetis-port-pins = < 9 4 >;
	};
	FTM1_CH5_PTD9: ftm1_ch5_ptd9 {
		nxp,kinetis-port-pins = < 9 6 >;
	};
	PTD10: GPIOD_PTD10: gpiod_ptd10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	FTM2_CH0_PTD10: ftm2_ch0_ptd10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	FTM2_QD_PHB_PTD10: ftm2_qd_phb_ptd10 {
		nxp,kinetis-port-pins = < 10 3 >;
	};
	PTD11: GPIOD_PTD11: gpiod_ptd11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	FTM2_CH1_PTD11: ftm2_ch1_ptd11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	FTM2_QD_PHA_PTD11: ftm2_qd_pha_ptd11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	LPUART2_CTS_PTD11: lpuart2_cts_ptd11 {
		nxp,kinetis-port-pins = < 11 6 >;
	};
	PTD12: GPIOD_PTD12: gpiod_ptd12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	FTM2_CH2_PTD12: ftm2_ch2_ptd12 {
		nxp,kinetis-port-pins = < 12 2 >;
	};
	LPI2C1_HREQ_PTD12: lpi2c1_hreq_ptd12 {
		nxp,kinetis-port-pins = < 12 3 >;
	};
	LPUART2_RTS_PTD12: lpuart2_rts_ptd12 {
		nxp,kinetis-port-pins = < 12 6 >;
	};
	PTD13: GPIOD_PTD13: gpiod_ptd13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	FTM2_CH4_PTD13: ftm2_ch4_ptd13 {
		nxp,kinetis-port-pins = < 13 2 >;
	};
	RTC_CLKOUT_PTD13: rtc_clkout_ptd13 {
		nxp,kinetis-port-pins = < 13 7 >;
	};
	PTD14: GPIOD_PTD14: gpiod_ptd14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	FTM2_CH5_PTD14: ftm2_ch5_ptd14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	CLKOUT_PTD14: clkout_ptd14 {
		nxp,kinetis-port-pins = < 14 7 >;
	};
	ACMP2_IN1_PTD15: acmp2_in1_ptd15 {
		nxp,kinetis-port-pins = < 15 0 >;
	};
	PTD15: GPIOD_PTD15: gpiod_ptd15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	FTM0_CH0_PTD15: ftm0_ch0_ptd15 {
		nxp,kinetis-port-pins = < 15 2 >;
	};
	ACMP2_IN0_PTD16: acmp2_in0_ptd16 {
		nxp,kinetis-port-pins = < 16 0 >;
	};
	PTD16: GPIOD_PTD16: gpiod_ptd16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	FTM0_CH1_PTD16: ftm0_ch1_ptd16 {
		nxp,kinetis-port-pins = < 16 2 >;
	};
	PTD17: GPIOD_PTD17: gpiod_ptd17 {
		nxp,kinetis-port-pins = < 17 1 >;
	};
	FTM0_FLT2_PTD17: ftm0_flt2_ptd17 {
		nxp,kinetis-port-pins = < 17 2 >;
	};
	LPUART2_RX_PTD17: lpuart2_rx_ptd17 {
		nxp,kinetis-port-pins = < 17 3 >;
	};
};

&porte {
	ADC2_SE7_PTE0: adc2_se7_pte0 {
		nxp,kinetis-port-pins = < 0 0 >;
	};
	PTE0: GPIOE_PTE0: gpioe_pte0 {
		nxp,kinetis-port-pins = < 0 1 >;
	};
	LPSPI0_SCK_PTE0: lpspi0_sck_pte0 {
		nxp,kinetis-port-pins = < 0 2 >;
	};
	TCLK1_PTE0: tclk1_pte0 {
		nxp,kinetis-port-pins = < 0 3 >;
	};
	LPI2C1_SDA_PTE0: lpi2c1_sda_pte0 {
		nxp,kinetis-port-pins = < 0 4 >;
	};
	FTM1_FLT2_PTE0: ftm1_flt2_pte0 {
		nxp,kinetis-port-pins = < 0 6 >;
	};
	ADC2_SE6_PTE1: adc2_se6_pte1 {
		nxp,kinetis-port-pins = < 1 0 >;
	};
	PTE1: GPIOE_PTE1: gpioe_pte1 {
		nxp,kinetis-port-pins = < 1 1 >;
	};
	LPSPI0_SIN_PTE1: lpspi0_sin_pte1 {
		nxp,kinetis-port-pins = < 1 2 >;
	};
	LPI2C0_HREQ_PTE1: lpi2c0_hreq_pte1 {
		nxp,kinetis-port-pins = < 1 3 >;
	};
	LPI2C1_SCL_PTE1: lpi2c1_scl_pte1 {
		nxp,kinetis-port-pins = < 1 4 >;
	};
	FTM1_FLT1_PTE1: ftm1_flt1_pte1 {
		nxp,kinetis-port-pins = < 1 6 >;
	};
	ADC1_SE10_PTE2: adc1_se10_pte2 {
		nxp,kinetis-port-pins = < 2 0 >;
	};
	PTE2: GPIOE_PTE2: gpioe_pte2 {
		nxp,kinetis-port-pins = < 2 1 >;
	};
	LPSPI0_SOUT_PTE2: lpspi0_sout_pte2 {
		nxp,kinetis-port-pins = < 2 2 >;
	};
	LPTMR0_ALT3_PTE2: lptmr0_alt3_pte2 {
		nxp,kinetis-port-pins = < 2 3 >;
	};
	FTM3_CH6_PTE2: ftm3_ch6_pte2 {
		nxp,kinetis-port-pins = < 2 4 >;
	};
	PWT_IN3_PTE2: pwt_in3_pte2 {
		nxp,kinetis-port-pins = < 2 5 >;
	};
	LPUART1_CTS_PTE2: lpuart1_cts_pte2 {
		nxp,kinetis-port-pins = < 2 6 >;
	};
	PTE3: GPIOE_PTE3: gpioe_pte3 {
		nxp,kinetis-port-pins = < 3 1 >;
	};
	FTM0_FLT0_PTE3: ftm0_flt0_pte3 {
		nxp,kinetis-port-pins = < 3 2 >;
	};
	LPUART2_RTS_PTE3: lpuart2_rts_pte3 {
		nxp,kinetis-port-pins = < 3 3 >;
	};
	FTM2_FLT0_PTE3: ftm2_flt0_pte3 {
		nxp,kinetis-port-pins = < 3 4 >;
	};
	TRGMUX_IN6_PTE3: trgmux_in6_pte3 {
		nxp,kinetis-port-pins = < 3 6 >;
	};
	ACMP2_OUT_PTE3: acmp2_out_pte3 {
		nxp,kinetis-port-pins = < 3 7 >;
	};
	PTE4: GPIOE_PTE4: gpioe_pte4 {
		nxp,kinetis-port-pins = < 4 1 >;
	};
	BUSOUT_PTE4: busout_pte4 {
		nxp,kinetis-port-pins = < 4 2 >;
	};
	FTM2_QD_PHB_PTE4: ftm2_qd_phb_pte4 {
		nxp,kinetis-port-pins = < 4 3 >;
	};
	FTM2_CH2_PTE4: ftm2_ch2_pte4 {
		nxp,kinetis-port-pins = < 4 4 >;
	};
	CAN0_RX_PTE4: can0_rx_pte4 {
		nxp,kinetis-port-pins = < 4 5 >;
	};
	FXIO_D6_PTE4: fxio_d6_pte4 {
		nxp,kinetis-port-pins = < 4 6 >;
	};
	EWM_OUT_b_PTE4: ewm_out_b_pte4 {
		nxp,kinetis-port-pins = < 4 7 >;
	};
	PTE5: GPIOE_PTE5: gpioe_pte5 {
		nxp,kinetis-port-pins = < 5 1 >;
	};
	TCLK2_PTE5: tclk2_pte5 {
		nxp,kinetis-port-pins = < 5 2 >;
	};
	FTM2_QD_PHA_PTE5: ftm2_qd_pha_pte5 {
		nxp,kinetis-port-pins = < 5 3 >;
	};
	FTM2_CH3_PTE5: ftm2_ch3_pte5 {
		nxp,kinetis-port-pins = < 5 4 >;
	};
	CAN0_TX_PTE5: can0_tx_pte5 {
		nxp,kinetis-port-pins = < 5 5 >;
	};
	FXIO_D7_PTE5: fxio_d7_pte5 {
		nxp,kinetis-port-pins = < 5 6 >;
	};
	EWM_IN_PTE5: ewm_in_pte5 {
		nxp,kinetis-port-pins = < 5 7 >;
	};
	ADC1_SE11_PTE6: ACMP0_IN6_PTE6: adc1_se11_pte6 {
		nxp,kinetis-port-pins = < 6 0 >;
	};
	PTE6: GPIOE_PTE6: gpioe_pte6 {
		nxp,kinetis-port-pins = < 6 1 >;
	};
	LPSPI0_PCS2_PTE6: lpspi0_pcs2_pte6 {
		nxp,kinetis-port-pins = < 6 2 >;
	};
	FTM3_CH7_PTE6: ftm3_ch7_pte6 {
		nxp,kinetis-port-pins = < 6 4 >;
	};
	LPUART1_RTS_PTE6: lpuart1_rts_pte6 {
		nxp,kinetis-port-pins = < 6 6 >;
	};
	ADC2_SE2_PTE7: ACMP2_IN6_PTE7: adc2_se2_pte7 {
		nxp,kinetis-port-pins = < 7 0 >;
	};
	PTE7: GPIOE_PTE7: gpioe_pte7 {
		nxp,kinetis-port-pins = < 7 1 >;
	};
	FTM0_CH7_PTE7: ftm0_ch7_pte7 {
		nxp,kinetis-port-pins = < 7 2 >;
	};
	FTM3_FLT0_PTE7: ftm3_flt0_pte7 {
		nxp,kinetis-port-pins = < 7 3 >;
	};
	ACMP0_IN3_PTE8: acmp0_in3_pte8 {
		nxp,kinetis-port-pins = < 8 0 >;
	};
	PTE8: GPIOE_PTE8: gpioe_pte8 {
		nxp,kinetis-port-pins = < 8 1 >;
	};
	FTM0_CH6_PTE8: ftm0_ch6_pte8 {
		nxp,kinetis-port-pins = < 8 2 >;
	};
	ACMP2_IN2_PTE9: DAC0_OUT_PTE9: acmp2_in2_pte9 {
		nxp,kinetis-port-pins = < 9 0 >;
	};
	PTE9: GPIOE_PTE9: gpioe_pte9 {
		nxp,kinetis-port-pins = < 9 1 >;
	};
	FTM0_CH7_PTE9: ftm0_ch7_pte9 {
		nxp,kinetis-port-pins = < 9 2 >;
	};
	LPUART2_CTS_PTE9: lpuart2_cts_pte9 {
		nxp,kinetis-port-pins = < 9 3 >;
	};
	ADC2_SE12_PTE10: adc2_se12_pte10 {
		nxp,kinetis-port-pins = < 10 0 >;
	};
	PTE10: GPIOE_PTE10: gpioe_pte10 {
		nxp,kinetis-port-pins = < 10 1 >;
	};
	CLKOUT_PTE10: clkout_pte10 {
		nxp,kinetis-port-pins = < 10 2 >;
	};
	FTM2_CH4_PTE10: ftm2_ch4_pte10 {
		nxp,kinetis-port-pins = < 10 4 >;
	};
	FXIO_D4_PTE10: fxio_d4_pte10 {
		nxp,kinetis-port-pins = < 10 6 >;
	};
	TRGMUX_OUT4_PTE10: trgmux_out4_pte10 {
		nxp,kinetis-port-pins = < 10 7 >;
	};
	ADC2_SE13_PTE11: adc2_se13_pte11 {
		nxp,kinetis-port-pins = < 11 0 >;
	};
	PTE11: GPIOE_PTE11: gpioe_pte11 {
		nxp,kinetis-port-pins = < 11 1 >;
	};
	PWT_IN1_PTE11: pwt_in1_pte11 {
		nxp,kinetis-port-pins = < 11 2 >;
	};
	LPTMR0_ALT1_PTE11: lptmr0_alt1_pte11 {
		nxp,kinetis-port-pins = < 11 3 >;
	};
	FTM2_CH5_PTE11: ftm2_ch5_pte11 {
		nxp,kinetis-port-pins = < 11 4 >;
	};
	FXIO_D5_PTE11: fxio_d5_pte11 {
		nxp,kinetis-port-pins = < 11 6 >;
	};
	TRGMUX_OUT5_PTE11: trgmux_out5_pte11 {
		nxp,kinetis-port-pins = < 11 7 >;
	};
	PTE12: GPIOE_PTE12: gpioe_pte12 {
		nxp,kinetis-port-pins = < 12 1 >;
	};
	FTM0_FLT3_PTE12: ftm0_flt3_pte12 {
		nxp,kinetis-port-pins = < 12 2 >;
	};
	LPUART2_TX_PTE12: lpuart2_tx_pte12 {
		nxp,kinetis-port-pins = < 12 3 >;
	};
	PTE13: GPIOE_PTE13: gpioe_pte13 {
		nxp,kinetis-port-pins = < 13 1 >;
	};
	FTM2_FLT0_PTE13: ftm2_flt0_pte13 {
		nxp,kinetis-port-pins = < 13 4 >;
	};
	ACMP2_IN3_PTE14: acmp2_in3_pte14 {
		nxp,kinetis-port-pins = < 14 0 >;
	};
	PTE14: GPIOE_PTE14: gpioe_pte14 {
		nxp,kinetis-port-pins = < 14 1 >;
	};
	FTM0_FLT1_PTE14: ftm0_flt1_pte14 {
		nxp,kinetis-port-pins = < 14 2 >;
	};
	FTM2_FLT1_PTE14: ftm2_flt1_pte14 {
		nxp,kinetis-port-pins = < 14 4 >;
	};
	PTE15: GPIOE_PTE15: gpioe_pte15 {
		nxp,kinetis-port-pins = < 15 1 >;
	};
	FTM2_CH6_PTE15: ftm2_ch6_pte15 {
		nxp,kinetis-port-pins = < 15 4 >;
	};
	FXIO_D2_PTE15: fxio_d2_pte15 {
		nxp,kinetis-port-pins = < 15 6 >;
	};
	TRGMUX_OUT6_PTE15: trgmux_out6_pte15 {
		nxp,kinetis-port-pins = < 15 7 >;
	};
	PTE16: GPIOE_PTE16: gpioe_pte16 {
		nxp,kinetis-port-pins = < 16 1 >;
	};
	FTM2_CH7_PTE16: ftm2_ch7_pte16 {
		nxp,kinetis-port-pins = < 16 4 >;
	};
	FXIO_D3_PTE16: fxio_d3_pte16 {
		nxp,kinetis-port-pins = < 16 6 >;
	};
	TRGMUX_OUT7_PTE16: trgmux_out7_pte16 {
		nxp,kinetis-port-pins = < 16 7 >;
	};
};