/*

Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this
   list of conditions and the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright
   notice, this list of conditions and the following disclaimer in the
   documentation and/or other materials provided with the distribution.

3. Neither the name of Nordic Semiconductor ASA nor the names of its
   contributors may be used to endorse or promote products derived from this
   software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

*/

#ifndef _NRF9160_PERIPHERALS_H
#define _NRF9160_PERIPHERALS_H

/* UICR */
#define UICR_KEYSLOT_COUNT 128

/* Clock Peripheral */
#define CLOCK_PRESENT
#define CLOCK_COUNT 1

/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1

/* Non-Volatile Memory Controller */
#define NVMC_PRESENT
#define NVMC_COUNT 1

#define NVMC_FEATURE_CACHE_PRESENT

/* Memory Protection Unit */
#define MPU_REGION_NUM 16

/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1

#define P0_PIN_NUM 32

#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL

/* Distributed  Peripheral to Peripheral Interconnect */
#define DPPIC_PRESENT
#define DPPIC_COUNT 1

#define DPPIC_CH_NUM 16
#define DPPIC_GROUP_NUM 6

/* Event Generator Unit */
#define EGU_PRESENT
#define EGU_COUNT 6

#define EGU0_CH_NUM 16
#define EGU1_CH_NUM 16
#define EGU2_CH_NUM 16
#define EGU3_CH_NUM 16
#define EGU4_CH_NUM 16
#define EGU5_CH_NUM 16

/* Timer/Counter */
#define TIMER_PRESENT
#define TIMER_COUNT 3

#define TIMER0_MAX_SIZE 32
#define TIMER1_MAX_SIZE 32
#define TIMER2_MAX_SIZE 32


#define TIMER0_CC_NUM 6
#define TIMER1_CC_NUM 6
#define TIMER2_CC_NUM 6

/* Real Time Counter */
#define RTC_PRESENT
#define RTC_COUNT 2

#define RTC0_CC_NUM 4
#define RTC1_CC_NUM 4

/* Watchdog Timer */
#define WDT_PRESENT
#define WDT_COUNT 1

/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 4

#define SPIM0_MAX_DATARATE  8
#define SPIM1_MAX_DATARATE  8
#define SPIM2_MAX_DATARATE  8
#define SPIM3_MAX_DATARATE  8

#define SPIM0_EASYDMA_MAXCNT_SIZE 13
#define SPIM1_EASYDMA_MAXCNT_SIZE 13
#define SPIM2_EASYDMA_MAXCNT_SIZE 13
#define SPIM3_EASYDMA_MAXCNT_SIZE 13

/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 4

#define SPIS0_EASYDMA_MAXCNT_SIZE 13
#define SPIS1_EASYDMA_MAXCNT_SIZE 13
#define SPIS2_EASYDMA_MAXCNT_SIZE 13
#define SPIS3_EASYDMA_MAXCNT_SIZE 13

/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 4

#define TWIM0_EASYDMA_MAXCNT_SIZE 13
#define TWIM1_EASYDMA_MAXCNT_SIZE 13
#define TWIM2_EASYDMA_MAXCNT_SIZE 13
#define TWIM3_EASYDMA_MAXCNT_SIZE 13

/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 4

#define TWIS0_EASYDMA_MAXCNT_SIZE 13
#define TWIS1_EASYDMA_MAXCNT_SIZE 13
#define TWIS2_EASYDMA_MAXCNT_SIZE 13
#define TWIS3_EASYDMA_MAXCNT_SIZE 13

/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 4

#define UARTE0_EASYDMA_MAXCNT_SIZE 13
#define UARTE1_EASYDMA_MAXCNT_SIZE 13
#define UARTE2_EASYDMA_MAXCNT_SIZE 13
#define UARTE3_EASYDMA_MAXCNT_SIZE 13

/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
#define SAADC_COUNT 1

#define SAADC_CH_NUM 8
#define SAADC_EASYDMA_MAXCNT_SIZE 15

/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 2

#define GPIOTE_CH_NUM 8

#define GPIOTE_FEATURE_SET_PRESENT
#define GPIOTE_FEATURE_CLR_PRESENT

/* Pulse Width Modulator */
#define PWM_PRESENT
#define PWM_COUNT 4

#define PWM_CH_NUM 4

#define PWM_EASYDMA_MAXCNT_SIZE 15

/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1

#define PDM_EASYDMA_MAXCNT_SIZE 15

/* Inter-IC Sound Interface */
#define I2S_PRESENT
#define I2S_COUNT 1

#define I2S_EASYDMA_MAXCNT_SIZE 14

/* Inter Processor Communication */
#define IPC_PRESENT
#define IPC_COUNT 1

#define IPC_CH_NUM 8
#define IPC_CONF_NUM 8
#define IPC_GPMEM_NUM 4

/* FPU */
#define FPU_PRESENT
#define FPU_COUNT 1

/* SPU */
#define SPU_PRESENT
#define SPU_COUNT 1

#define SPU_RAMREGION_SIZE 0x2000ul

/*CRYPTOCELL register interface*/
#define CRYPTOCELL_PRESENT 1
#define CRYPTOCELL_COUNT 1
#define CRYPTOCELL_VERSION 310

/*CRYPTOCELL AES engine*/
#define CC_AES_PRESENT 1
#define CC_AES_COUNT 1

/*CRYPTOCELL AHB interface*/
#define CC_AHB_PRESENT 1
#define CC_AHB_COUNT 1

/*CRYPTOCELL CHACHA engine*/
#define CC_CHACHA_PRESENT 1
#define CC_CHACHA_COUNT 1

/*CRYPTOCELL CTL interface*/
#define CC_CTL_PRESENT 1
#define CC_CTL_COUNT 1

/*CRYPTOCELL Data IN interface*/
#define CC_DIN_PRESENT 1
#define CC_DIN_COUNT 1

/*CRYPTOCELL Data OUT interface*/
#define CC_DOUT_PRESENT 1
#define CC_DOUT_COUNT 1

/*CRYPTOCELL HASH engine*/
#define CC_HASH_PRESENT 1
#define CC_HASH_COUNT 1

/*CRYPTOCELL HOST register interface*/
#define CC_HOST_RGF_PRESENT 1
#define CC_HOST_RGF_COUNT 1

/*CRYPTOCELL MISC interface*/
#define CC_MISC_PRESENT 1
#define CC_MISC_COUNT 1

/*CRYPTOCELL PKA engine*/
#define CC_PKA_PRESENT 1
#define CC_PKA_COUNT 1

/*CRYPTOCELL RNG engine*/
#define CC_RNG_PRESENT 1
#define CC_RNG_COUNT 1

/*CRYPTOCELL RNG SRAM interface*/
#define CC_RNG_SRAM_PRESENT 1
#define CC_RNG_SRAM_COUNT 1

/* KMU */
#define KMU_PRESENT
#define KMU_COUNT 1

#define KMU_KEYSLOT_PRESENT

/* MAGPIO */
#define MAGPIO_PRESENT
#define MAGPIO_COUNT 1
#define MAGPIO_PIN_NUM 3

/* REGULATORS */
#define REGULATORS_PRESENT
#define REGULATORS_COUNT 1

/*Embedded Trace Macrocell*/
#define ETM_PRESENT 1
#define ETM_COUNT 1

/*Embedded Trace Buffer*/
#define ETB_PRESENT 1
#define ETB_COUNT 1

/*Trace Port Interface Unit*/
#define TPIU_PRESENT 1
#define TPIU_COUNT 1

/*ATB Replicator module*/
#define ATBREPLICATOR_PRESENT 1
#define ATBREPLICATOR_COUNT 1

/*ATB funnel module*/
#define ATBFUNNEL_PRESENT 1
#define ATBFUNNEL_COUNT 2

#endif  // _NRF9160_PERIPHERALS_H