Nordic Semiconductor Nordic nrf52840 nrf52 1 nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. 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IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 32 32 0x00000000 0xFFFFFFFF NRF_ CM4 r0p1 little 1 1 3 0 112 0 system_nrf52840 112 FICR Factory information configuration registers 0x10000000 0 0x1000 registers FICR 0x20 CODEPAGESIZE Code memory page size 0x010 read-only 0xFFFFFFFF 0x20 CODEPAGESIZE Code memory page size 0 31 CODESIZE Code memory size 0x014 read-only 0xFFFFFFFF 0x20 CODESIZE Code memory size in number of pages 0 31 0x2 0x4 DEVICEID[%s] Description collection: Device identifier 0x060 read-only 0xFFFFFFFF 0x20 DEVICEID 64 bit unique device identifier 0 31 0x4 0x4 ER[%s] Description collection: Encryption root, word n 0x080 read-only 0xFFFFFFFF 0x20 ER Encryption root, word n 0 31 0x4 0x4 IR[%s] Description collection: Identity Root, word n 0x090 read-only 0xFFFFFFFF 0x20 IR Identity Root, word n 0 31 DEVICEADDRTYPE Device address type 0x0A0 read-only 0xFFFFFFFF 0x20 DEVICEADDRTYPE Device address type 0 0 Public Public address 0x0 Random Random address 0x1 0x2 0x4 DEVICEADDR[%s] Description collection: Device address n 0x0A4 read-only 0xFFFFFFFF 0x20 DEVICEADDR 48 bit device address 0 31 INFO Device info FICR_INFO read-only 0x100 PART Part code 0x000 read-only 0x00052840 0x20 PART Part code 0 31 N52840 nRF52840 0x00052840 Unspecified Unspecified 0xFFFFFFFF VARIANT Build code, last two letters of Package Variant and first two characters of Build Code, encoded in ASCII. 0x004 read-only 0xFFFFFFFF 0x20 VARIANT For valid values see SoC revisions and variants. 0 31 PACKAGE Package option 0x008 read-only 0xFFFFFFFF 0x20 PACKAGE Package option 0 31 QI QIxx - 7x7 73-pin aQFN 0x00002004 QF QFxx - 6x6 48-pin QFN 0x00002000 CK CKxx - 3.544 x 3.607 WLCSP 0x00002005 Unspecified Unspecified 0xFFFFFFFF RAM RAM variant 0x00C read-only 0xFFFFFFFF 0x20 RAM RAM variant 0 31 K16 16 kB RAM 0x00000010 K32 32 kB RAM 0x00000020 K64 64 kB RAM 0x00000040 K128 128 kB RAM 0x00000080 K256 256 kB RAM 0x00000100 Unspecified Unspecified 0xFFFFFFFF FLASH Flash variant 0x010 read-only 0xFFFFFFFF 0x20 FLASH Flash variant 0 31 K128 128 kB FLASH 0x00000080 K256 256 kB FLASH 0x00000100 K512 512 kB FLASH 0x00000200 K1024 1 MB FLASH 0x00000400 K2048 2 MB FLASH 0x00000800 Unspecified Unspecified 0xFFFFFFFF 0x3 0x4 PRODTEST[%s] Description collection: Production test signature n 0x350 read-only 0xFFFFFFFF 0x20 PRODTEST Production test signature n 0 31 Done Production tests done 0xBB42319F NotDone Production tests not done 0xFFFFFFFF TEMP Registers storing factory TEMP module linearization coefficients FICR_TEMP read-only 0x404 A0 Slope definition A0 0x000 read-only 0xFFFFFFFF 0x20 A A (slope definition) register. 0 11 A1 Slope definition A1 0x004 read-only 0xFFFFFFFF 0x20 A A (slope definition) register. 0 11 A2 Slope definition A2 0x008 read-only 0xFFFFFFFF 0x20 A A (slope definition) register. 0 11 A3 Slope definition A3 0x00C read-only 0xFFFFFFFF 0x20 A A (slope definition) register. 0 11 A4 Slope definition A4 0x010 read-only 0xFFFFFFFF 0x20 A A (slope definition) register. 0 11 A5 Slope definition A5 0x014 read-only 0xFFFFFFFF 0x20 A A (slope definition) register. 0 11 B0 Y-intercept B0 0x018 read-only 0xFFFFFFFF 0x20 B B (y-intercept) 0 13 B1 Y-intercept B1 0x01C read-only 0xFFFFFFFF 0x20 B B (y-intercept) 0 13 B2 Y-intercept B2 0x020 read-only 0xFFFFFFFF 0x20 B B (y-intercept) 0 13 B3 Y-intercept B3 0x024 read-only 0xFFFFFFFF 0x20 B B (y-intercept) 0 13 B4 Y-intercept B4 0x028 read-only 0xFFFFFFFF 0x20 B B (y-intercept) 0 13 B5 Y-intercept B5 0x02C read-only 0xFFFFFFFF 0x20 B B (y-intercept) 0 13 T0 Segment end T0 0x030 read-only 0xFFFFFFFF 0x20 T T (segment end) register 0 7 T1 Segment end T1 0x034 read-only 0xFFFFFFFF 0x20 T T (segment end) register 0 7 T2 Segment end T2 0x038 read-only 0xFFFFFFFF 0x20 T T (segment end) register 0 7 T3 Segment end T3 0x03C read-only 0xFFFFFFFF 0x20 T T (segment end) register 0 7 T4 Segment end T4 0x040 read-only 0xFFFFFFFF 0x20 T T (segment end) register 0 7 NFC Unspecified FICR_NFC read-write 0x450 TAGHEADER0 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 0x000 read-only 0xFFFFFF5F 0x20 MFGID Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F 0 7 UD1 Unique identifier byte 1 8 15 UD2 Unique identifier byte 2 16 23 UD3 Unique identifier byte 3 24 31 TAGHEADER1 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 0x004 read-only 0xFFFFFFFF 0x20 UD4 Unique identifier byte 4 0 7 UD5 Unique identifier byte 5 8 15 UD6 Unique identifier byte 6 16 23 UD7 Unique identifier byte 7 24 31 TAGHEADER2 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 0x008 read-only 0xFFFFFFFF 0x20 UD8 Unique identifier byte 8 0 7 UD9 Unique identifier byte 9 8 15 UD10 Unique identifier byte 10 16 23 UD11 Unique identifier byte 11 24 31 TAGHEADER3 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 0x00C read-only 0xFFFFFFFF 0x20 UD12 Unique identifier byte 12 0 7 UD13 Unique identifier byte 13 8 15 UD14 Unique identifier byte 14 16 23 UD15 Unique identifier byte 15 24 31 TRNG90B NIST800-90B RNG calibration data FICR_TRNG90B read-write 0xC00 BYTES Amount of bytes for the required entropy bits 0x000 read-only 0xFFFFFFFF 0x20 BYTES Amount of bytes for the required entropy bits 0 31 RCCUTOFF Repetition counter cutoff 0x004 read-only 0xFFFFFFFF 0x20 RCCUTOFF Repetition counter cutoff 0 31 APCUTOFF Adaptive proportion cutoff 0x008 read-only 0xFFFFFFFF 0x20 APCUTOFF Adaptive proportion cutoff 0 31 STARTUP Amount of bytes for the startup tests 0x00C read-only 0xFFFFFFFF 0x20 STARTUP Amount of bytes for the startup tests 0 31 ROSC1 Sample count for ring oscillator 1 0x010 read-only 0xFFFFFFFF 0x20 ROSC1 Sample count for ring oscillator 1 0 31 ROSC2 Sample count for ring oscillator 2 0x014 read-only 0xFFFFFFFF 0x20 ROSC2 Sample count for ring oscillator 2 0 31 ROSC3 Sample count for ring oscillator 3 0x018 read-only 0xFFFFFFFF 0x20 ROSC3 Sample count for ring oscillator 3 0 31 ROSC4 Sample count for ring oscillator 4 0x01C read-only 0xFFFFFFFF 0x20 ROSC4 Sample count for ring oscillator 4 0 31 UICR User information configuration registers 0x10001000 0 0x1000 registers UICR 0x20 0xD 0x4 NRFFW[%s] Description collection: Reserved for Nordic firmware design 0x014 read-write 0xFFFFFFFF 0x20 NRFFW Reserved for Nordic firmware design 0 31 0xC 0x4 NRFHW[%s] Description collection: Reserved for Nordic hardware design 0x050 read-write 0xFFFFFFFF 0x20 NRFHW Reserved for Nordic hardware design 0 31 0x20 0x4 CUSTOMER[%s] Description collection: Reserved for customer 0x080 read-write 0xFFFFFFFF 0x20 CUSTOMER Reserved for customer 0 31 0x2 0x4 PSELRESET[%s] Description collection: Mapping of the nRESET function (see POWER chapter for details) 0x200 read-write 0xFFFFFFFF 0x20 PIN GPIO pin number onto which nRESET is exposed 0 4 PORT Port number onto which nRESET is exposed 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 APPROTECT Access port protection 0x208 read-write 0xFFFFFFFF 0x20 PALL Enable or disable access port protection. 0 7 Disabled Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF HwDisabled Hardware disable of access port protection for devices where access port protection is controlled by hardware and software 0x5A Enabled Enable 0x00 NFCPINS Setting of pins dedicated to NFC functionality: NFC antenna or GPIO 0x20C read-write 0xFFFFFFFF 0x20 PROTECT Setting of pins dedicated to NFC functionality 0 0 Disabled Operation as GPIO pins. Same protection as normal GPIO pins. 0x0 NFC Operation as NFC antenna pins. Configures the protection for NFC operation. 0x1 DEBUGCTRL Processor debug control 0x210 read-write 0xFFFFFFFF 0x20 CPUNIDEN Configure CPU non-intrusive debug features 0 7 Enabled Enable CPU ITM and ETM functionality (default behavior) 0xFF Disabled Disable CPU ITM and ETM functionality 0x00 CPUFPBEN Configure CPU flash patch and breakpoint (FPB) unit behavior 8 15 Enabled Enable CPU FPB unit (default behavior) 0xFF Disabled Disable CPU FPB unit. Writes into the FPB registers will be ignored. 0x00 REGOUT0 Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. 0x304 read-write 0xFFFFFFFF 0x20 VOUT Output voltage from REG0 regulator stage. 0 2 1V8 1.8 V 0x0 2V1 2.1 V 0x1 2V4 2.4 V 0x2 2V7 2.7 V 0x3 3V0 3.0 V 0x4 3V3 3.3 V 0x5 DEFAULT Default voltage: 1.8 V 0x7 APPROTECT Access Port Protection 0x40000000 0 0x1000 registers APPROTECT 0x20 FORCEPROTECT Software force enable APPROTECT mechanism until next reset. 0x550 read-writeonce 0xFFFFFFFF 0x20 FORCEPROTECT Write 0x0 to force enable APPROTECT mechanism 0 7 write Force Software force enable APPROTECT mechanism 0x00 DISABLE Software disable APPROTECT mechanism 0x558 read-write 0x00000000 0x20 DISABLE Software disable APPROTECT mechanism 0 7 SwDisable Software disable APPROTECT mechanism 0x5A CLOCK Clock control 0x40000000 APPROTECT 0 0x1000 registers CLOCK_POWER 0 CLOCK 0x20 TASKS_HFCLKSTART Start HFXO crystal oscillator 0x000 write-only 0x00000000 0x20 TASKS_HFCLKSTART Start HFXO crystal oscillator 0 0 Trigger Trigger task 0x1 TASKS_HFCLKSTOP Stop HFXO crystal oscillator 0x004 write-only 0x00000000 0x20 TASKS_HFCLKSTOP Stop HFXO crystal oscillator 0 0 Trigger Trigger task 0x1 TASKS_LFCLKSTART Start LFCLK 0x008 write-only 0x00000000 0x20 TASKS_LFCLKSTART Start LFCLK 0 0 Trigger Trigger task 0x1 TASKS_LFCLKSTOP Stop LFCLK 0x00C write-only 0x00000000 0x20 TASKS_LFCLKSTOP Stop LFCLK 0 0 Trigger Trigger task 0x1 TASKS_CAL Start calibration of LFRC 0x010 write-only 0x00000000 0x20 TASKS_CAL Start calibration of LFRC 0 0 Trigger Trigger task 0x1 TASKS_CTSTART Start calibration timer 0x014 write-only 0x00000000 0x20 TASKS_CTSTART Start calibration timer 0 0 Trigger Trigger task 0x1 TASKS_CTSTOP Stop calibration timer 0x018 write-only 0x00000000 0x20 TASKS_CTSTOP Stop calibration timer 0 0 Trigger Trigger task 0x1 EVENTS_HFCLKSTARTED HFXO crystal oscillator started 0x100 read-write 0x00000000 0x20 EVENTS_HFCLKSTARTED HFXO crystal oscillator started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_LFCLKSTARTED LFCLK started 0x104 read-write 0x00000000 0x20 EVENTS_LFCLKSTARTED LFCLK started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DONE Calibration of LFRC completed 0x10C read-write 0x00000000 0x20 EVENTS_DONE Calibration of LFRC completed 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CTTO Calibration timer timeout 0x110 read-write 0x00000000 0x20 EVENTS_CTTO Calibration timer timeout 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CTSTARTED Calibration timer has been started and is ready to process new tasks 0x128 read-write 0x00000000 0x20 EVENTS_CTSTARTED Calibration timer has been started and is ready to process new tasks 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CTSTOPPED Calibration timer has been stopped and is ready to process new tasks 0x12C read-write 0x00000000 0x20 EVENTS_CTSTOPPED Calibration timer has been stopped and is ready to process new tasks 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 HFCLKSTARTED Write '1' to enable interrupt for event HFCLKSTARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 LFCLKSTARTED Write '1' to enable interrupt for event LFCLKSTARTED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DONE Write '1' to enable interrupt for event DONE 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CTTO Write '1' to enable interrupt for event CTTO 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CTSTARTED Write '1' to enable interrupt for event CTSTARTED 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CTSTOPPED Write '1' to enable interrupt for event CTSTOPPED 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 HFCLKSTARTED Write '1' to disable interrupt for event HFCLKSTARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 LFCLKSTARTED Write '1' to disable interrupt for event LFCLKSTARTED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DONE Write '1' to disable interrupt for event DONE 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CTTO Write '1' to disable interrupt for event CTTO 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CTSTARTED Write '1' to disable interrupt for event CTSTARTED 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CTSTOPPED Write '1' to disable interrupt for event CTSTOPPED 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 HFCLKRUN Status indicating that HFCLKSTART task has been triggered 0x408 read-only 0x00000000 0x20 STATUS HFCLKSTART task triggered or not 0 0 NotTriggered Task not triggered 0x0 Triggered Task triggered 0x1 HFCLKSTAT HFCLK status 0x40C read-only 0x00000000 0x20 SRC Source of HFCLK 0 0 RC 64 MHz internal oscillator (HFINT) 0x0 Xtal 64 MHz crystal oscillator (HFXO) 0x1 STATE HFCLK state 16 16 NotRunning HFCLK not running 0x0 Running HFCLK running 0x1 LFCLKRUN Status indicating that LFCLKSTART task has been triggered 0x414 read-only 0x00000000 0x20 STATUS LFCLKSTART task triggered or not 0 0 NotTriggered Task not triggered 0x0 Triggered Task triggered 0x1 LFCLKSTAT LFCLK status 0x418 read-only 0x00000000 0x20 SRC Source of LFCLK 0 1 RC 32.768 kHz RC oscillator (LFRC) 0x0 Xtal 32.768 kHz crystal oscillator (LFXO) 0x1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) 0x2 STATE LFCLK state 16 16 NotRunning LFCLK not running 0x0 Running LFCLK running 0x1 LFCLKSRCCOPY Copy of LFCLKSRC register, set when LFCLKSTART task was triggered 0x41C read-only 0x00000000 0x20 SRC Clock source 0 1 RC 32.768 kHz RC oscillator (LFRC) 0x0 Xtal 32.768 kHz crystal oscillator (LFXO) 0x1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) 0x2 LFCLKSRC Clock source for the LFCLK 0x518 read-write 0x00000000 0x20 SRC Clock source 0 1 RC 32.768 kHz RC oscillator (LFRC) 0x0 Xtal 32.768 kHz crystal oscillator (LFXO) 0x1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) 0x2 BYPASS Enable or disable bypass of LFCLK crystal oscillator with external clock source 16 16 Disabled Disable (use with Xtal or low-swing external source) 0x0 Enabled Enable (use with rail-to-rail external source) 0x1 EXTERNAL Enable or disable external source for LFCLK 17 17 Disabled Disable external source (use with Xtal) 0x0 Enabled Enable use of external source instead of Xtal (SRC needs to be set to Xtal) 0x1 HFXODEBOUNCE HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. 0x528 read-write 0x00000010 0x20 HFXODEBOUNCE HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. 0 7 Db256us 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. 0x10 Db1024us 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. 0x40 CTIV Calibration timer interval 0x538 read-write 0x00000000 0x20 CTIV Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. 0 6 TRACECONFIG Clocking options for the trace port debug interface 0x55C read-write 0x00000000 0x20 TRACEPORTSPEED Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. 0 1 32MHz 32 MHz trace port clock (TRACECLK = 16 MHz) 0x0 16MHz 16 MHz trace port clock (TRACECLK = 8 MHz) 0x1 8MHz 8 MHz trace port clock (TRACECLK = 4 MHz) 0x2 4MHz 4 MHz trace port clock (TRACECLK = 2 MHz) 0x3 TRACEMUX Pin multiplexing of trace signals. See pin assignment chapter for more details. 16 17 GPIO No trace signals routed to pins. All pins can be used as regular GPIOs. 0x0 Serial SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. 0x1 Parallel All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. 0x2 LFRCMODE LFRC mode configuration 0x5B4 read-write 0x00000000 0x20 MODE Set LFRC mode 0 0 Normal Normal mode 0x0 ULP Ultra-low power mode (ULP) 0x1 STATUS Active LFRC mode. This field is read only. 16 16 Normal Normal mode 0x0 ULP Ultra-low power mode (ULP) 0x1 POWER Power control 0x40000000 APPROTECT 0 0x1000 registers CLOCK_POWER 0 POWER 0x20 TASKS_CONSTLAT Enable Constant Latency mode 0x78 write-only 0x00000000 0x20 TASKS_CONSTLAT Enable Constant Latency mode 0 0 Trigger Trigger task 0x1 TASKS_LOWPWR Enable Low-power mode (variable latency) 0x7C write-only 0x00000000 0x20 TASKS_LOWPWR Enable Low-power mode (variable latency) 0 0 Trigger Trigger task 0x1 EVENTS_POFWARN Power failure warning 0x108 read-write 0x00000000 0x20 EVENTS_POFWARN Power failure warning 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SLEEPENTER CPU entered WFI/WFE sleep 0x114 read-write 0x00000000 0x20 EVENTS_SLEEPENTER CPU entered WFI/WFE sleep 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SLEEPEXIT CPU exited WFI/WFE sleep 0x118 read-write 0x00000000 0x20 EVENTS_SLEEPEXIT CPU exited WFI/WFE sleep 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_USBDETECTED Voltage supply detected on VBUS 0x11C read-write 0x00000000 0x20 EVENTS_USBDETECTED Voltage supply detected on VBUS 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_USBREMOVED Voltage supply removed from VBUS 0x120 read-write 0x00000000 0x20 EVENTS_USBREMOVED Voltage supply removed from VBUS 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_USBPWRRDY USB 3.3 V supply ready 0x124 read-write 0x00000000 0x20 EVENTS_USBPWRRDY USB 3.3 V supply ready 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 POFWARN Write '1' to enable interrupt for event POFWARN 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SLEEPENTER Write '1' to enable interrupt for event SLEEPENTER 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SLEEPEXIT Write '1' to enable interrupt for event SLEEPEXIT 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 USBDETECTED Write '1' to enable interrupt for event USBDETECTED 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 USBREMOVED Write '1' to enable interrupt for event USBREMOVED 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 USBPWRRDY Write '1' to enable interrupt for event USBPWRRDY 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 POFWARN Write '1' to disable interrupt for event POFWARN 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SLEEPENTER Write '1' to disable interrupt for event SLEEPENTER 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SLEEPEXIT Write '1' to disable interrupt for event SLEEPEXIT 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 USBDETECTED Write '1' to disable interrupt for event USBDETECTED 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 USBREMOVED Write '1' to disable interrupt for event USBREMOVED 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 USBPWRRDY Write '1' to disable interrupt for event USBPWRRDY 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RESETREAS Reset reason 0x400 read-write 0x00000000 0x20 RESETPIN Reset from pin-reset detected 0 0 NotDetected Not detected 0x0 Detected Detected 0x1 DOG Reset from watchdog detected 1 1 NotDetected Not detected 0x0 Detected Detected 0x1 SREQ Reset from soft reset detected 2 2 NotDetected Not detected 0x0 Detected Detected 0x1 LOCKUP Reset from CPU lock-up detected 3 3 NotDetected Not detected 0x0 Detected Detected 0x1 OFF Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO 16 16 NotDetected Not detected 0x0 Detected Detected 0x1 LPCOMP Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP 17 17 NotDetected Not detected 0x0 Detected Detected 0x1 DIF Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode 18 18 NotDetected Not detected 0x0 Detected Detected 0x1 NFC Reset due to wake up from System OFF mode by NFC field detect 19 19 NotDetected Not detected 0x0 Detected Detected 0x1 VBUS Reset due to wake up from System OFF mode by VBUS rising into valid range 20 20 NotDetected Not detected 0x0 Detected Detected 0x1 RAMSTATUS Deprecated register - RAM status register 0x428 read-only 0x00000000 0x20 RAMBLOCK0 RAM block 0 is on or off/powering up 0 0 Off Off 0x0 On On 0x1 RAMBLOCK1 RAM block 1 is on or off/powering up 1 1 Off Off 0x0 On On 0x1 RAMBLOCK2 RAM block 2 is on or off/powering up 2 2 Off Off 0x0 On On 0x1 RAMBLOCK3 RAM block 3 is on or off/powering up 3 3 Off Off 0x0 On On 0x1 USBREGSTATUS USB supply status 0x438 read-only 0x00000000 0x20 VBUSDETECT VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) 0 0 NoVbus VBUS voltage below valid threshold 0x0 VbusPresent VBUS voltage above valid threshold 0x1 OUTPUTRDY USB supply output settling time elapsed 1 1 NotReady USBREG output settling time not elapsed 0x0 Ready USBREG output settling time elapsed (same information as USBPWRRDY event) 0x1 SYSTEMOFF System OFF register 0x500 write-only 0x00000000 0x20 SYSTEMOFF Enable System OFF mode 0 0 Enter Enable System OFF mode 0x1 POFCON Power-fail comparator configuration 0x510 read-write 0x00000000 0x20 POF Enable or disable power failure warning 0 0 Disabled Disable 0x0 Enabled Enable 0x1 THRESHOLD Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. 1 4 V17 Set threshold to 1.7 V 0x4 V18 Set threshold to 1.8 V 0x5 V19 Set threshold to 1.9 V 0x6 V20 Set threshold to 2.0 V 0x7 V21 Set threshold to 2.1 V 0x8 V22 Set threshold to 2.2 V 0x9 V23 Set threshold to 2.3 V 0xA V24 Set threshold to 2.4 V 0xB V25 Set threshold to 2.5 V 0xC V26 Set threshold to 2.6 V 0xD V27 Set threshold to 2.7 V 0xE V28 Set threshold to 2.8 V 0xF THRESHOLDVDDH Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). 8 11 V27 Set threshold to 2.7 V 0x0 V28 Set threshold to 2.8 V 0x1 V29 Set threshold to 2.9 V 0x2 V30 Set threshold to 3.0 V 0x3 V31 Set threshold to 3.1 V 0x4 V32 Set threshold to 3.2 V 0x5 V33 Set threshold to 3.3 V 0x6 V34 Set threshold to 3.4 V 0x7 V35 Set threshold to 3.5 V 0x8 V36 Set threshold to 3.6 V 0x9 V37 Set threshold to 3.7 V 0xA V38 Set threshold to 3.8 V 0xB V39 Set threshold to 3.9 V 0xC V40 Set threshold to 4.0 V 0xD V41 Set threshold to 4.1 V 0xE V42 Set threshold to 4.2 V 0xF GPREGRET General purpose retention register 0x51C read-write 0x00000000 0x20 GPREGRET General purpose retention register 0 7 GPREGRET2 General purpose retention register 0x520 read-write 0x00000000 0x20 GPREGRET General purpose retention register 0 7 DCDCEN Enable DC/DC converter for REG1 stage 0x578 read-write 0x00000000 0x20 DCDCEN Enable DC/DC converter for REG1 stage. 0 0 Disabled Disable 0x0 Enabled Enable 0x1 DCDCEN0 Enable DC/DC converter for REG0 stage 0x580 read-write 0x00000000 0x20 DCDCEN Enable DC/DC converter for REG0 stage. 0 0 Disabled Disable 0x0 Enabled Enable 0x1 MAINREGSTATUS Main supply status 0x640 read-only 0x00000000 0x20 MAINREGSTATUS Main supply status 0 0 Normal Normal voltage mode. Voltage supplied on VDD. 0x0 High High voltage mode. Voltage supplied on VDDH. 0x1 9 0x010 RAM[%s] Unspecified POWER_RAM read-write 0x900 POWER Description cluster: RAMn power control register 0x000 read-write 0x0000FFFF 0x20 S0POWER Keep RAM section S0 on or off in System ON mode. 0 0 Off Off 0x0 On On 0x1 S1POWER Keep RAM section S1 on or off in System ON mode. 1 1 Off Off 0x0 On On 0x1 S2POWER Keep RAM section S2 on or off in System ON mode. 2 2 Off Off 0x0 On On 0x1 S3POWER Keep RAM section S3 on or off in System ON mode. 3 3 Off Off 0x0 On On 0x1 S4POWER Keep RAM section S4 on or off in System ON mode. 4 4 Off Off 0x0 On On 0x1 S5POWER Keep RAM section S5 on or off in System ON mode. 5 5 Off Off 0x0 On On 0x1 S6POWER Keep RAM section S6 on or off in System ON mode. 6 6 Off Off 0x0 On On 0x1 S7POWER Keep RAM section S7 on or off in System ON mode. 7 7 Off Off 0x0 On On 0x1 S8POWER Keep RAM section S8 on or off in System ON mode. 8 8 Off Off 0x0 On On 0x1 S9POWER Keep RAM section S9 on or off in System ON mode. 9 9 Off Off 0x0 On On 0x1 S10POWER Keep RAM section S10 on or off in System ON mode. 10 10 Off Off 0x0 On On 0x1 S11POWER Keep RAM section S11 on or off in System ON mode. 11 11 Off Off 0x0 On On 0x1 S12POWER Keep RAM section S12 on or off in System ON mode. 12 12 Off Off 0x0 On On 0x1 S13POWER Keep RAM section S13 on or off in System ON mode. 13 13 Off Off 0x0 On On 0x1 S14POWER Keep RAM section S14 on or off in System ON mode. 14 14 Off Off 0x0 On On 0x1 S15POWER Keep RAM section S15 on or off in System ON mode. 15 15 Off Off 0x0 On On 0x1 S0RETENTION Keep retention on RAM section S0 when RAM section is off 16 16 Off Off 0x0 On On 0x1 S1RETENTION Keep retention on RAM section S1 when RAM section is off 17 17 Off Off 0x0 On On 0x1 S2RETENTION Keep retention on RAM section S2 when RAM section is off 18 18 Off Off 0x0 On On 0x1 S3RETENTION Keep retention on RAM section S3 when RAM section is off 19 19 Off Off 0x0 On On 0x1 S4RETENTION Keep retention on RAM section S4 when RAM section is off 20 20 Off Off 0x0 On On 0x1 S5RETENTION Keep retention on RAM section S5 when RAM section is off 21 21 Off Off 0x0 On On 0x1 S6RETENTION Keep retention on RAM section S6 when RAM section is off 22 22 Off Off 0x0 On On 0x1 S7RETENTION Keep retention on RAM section S7 when RAM section is off 23 23 Off Off 0x0 On On 0x1 S8RETENTION Keep retention on RAM section S8 when RAM section is off 24 24 Off Off 0x0 On On 0x1 S9RETENTION Keep retention on RAM section S9 when RAM section is off 25 25 Off Off 0x0 On On 0x1 S10RETENTION Keep retention on RAM section S10 when RAM section is off 26 26 Off Off 0x0 On On 0x1 S11RETENTION Keep retention on RAM section S11 when RAM section is off 27 27 Off Off 0x0 On On 0x1 S12RETENTION Keep retention on RAM section S12 when RAM section is off 28 28 Off Off 0x0 On On 0x1 S13RETENTION Keep retention on RAM section S13 when RAM section is off 29 29 Off Off 0x0 On On 0x1 S14RETENTION Keep retention on RAM section S14 when RAM section is off 30 30 Off Off 0x0 On On 0x1 S15RETENTION Keep retention on RAM section S15 when RAM section is off 31 31 Off Off 0x0 On On 0x1 POWERSET Description cluster: RAMn power control set register 0x004 write-only 0x0000FFFF 0x20 S0POWER Keep RAM section S0 of RAMn on or off in System ON mode 0 0 On On 0x1 S1POWER Keep RAM section S1 of RAMn on or off in System ON mode 1 1 On On 0x1 S2POWER Keep RAM section S2 of RAMn on or off in System ON mode 2 2 On On 0x1 S3POWER Keep RAM section S3 of RAMn on or off in System ON mode 3 3 On On 0x1 S4POWER Keep RAM section S4 of RAMn on or off in System ON mode 4 4 On On 0x1 S5POWER Keep RAM section S5 of RAMn on or off in System ON mode 5 5 On On 0x1 S6POWER Keep RAM section S6 of RAMn on or off in System ON mode 6 6 On On 0x1 S7POWER Keep RAM section S7 of RAMn on or off in System ON mode 7 7 On On 0x1 S8POWER Keep RAM section S8 of RAMn on or off in System ON mode 8 8 On On 0x1 S9POWER Keep RAM section S9 of RAMn on or off in System ON mode 9 9 On On 0x1 S10POWER Keep RAM section S10 of RAMn on or off in System ON mode 10 10 On On 0x1 S11POWER Keep RAM section S11 of RAMn on or off in System ON mode 11 11 On On 0x1 S12POWER Keep RAM section S12 of RAMn on or off in System ON mode 12 12 On On 0x1 S13POWER Keep RAM section S13 of RAMn on or off in System ON mode 13 13 On On 0x1 S14POWER Keep RAM section S14 of RAMn on or off in System ON mode 14 14 On On 0x1 S15POWER Keep RAM section S15 of RAMn on or off in System ON mode 15 15 On On 0x1 S0RETENTION Keep retention on RAM section S0 when RAM section is switched off 16 16 On On 0x1 S1RETENTION Keep retention on RAM section S1 when RAM section is switched off 17 17 On On 0x1 S2RETENTION Keep retention on RAM section S2 when RAM section is switched off 18 18 On On 0x1 S3RETENTION Keep retention on RAM section S3 when RAM section is switched off 19 19 On On 0x1 S4RETENTION Keep retention on RAM section S4 when RAM section is switched off 20 20 On On 0x1 S5RETENTION Keep retention on RAM section S5 when RAM section is switched off 21 21 On On 0x1 S6RETENTION Keep retention on RAM section S6 when RAM section is switched off 22 22 On On 0x1 S7RETENTION Keep retention on RAM section S7 when RAM section is switched off 23 23 On On 0x1 S8RETENTION Keep retention on RAM section S8 when RAM section is switched off 24 24 On On 0x1 S9RETENTION Keep retention on RAM section S9 when RAM section is switched off 25 25 On On 0x1 S10RETENTION Keep retention on RAM section S10 when RAM section is switched off 26 26 On On 0x1 S11RETENTION Keep retention on RAM section S11 when RAM section is switched off 27 27 On On 0x1 S12RETENTION Keep retention on RAM section S12 when RAM section is switched off 28 28 On On 0x1 S13RETENTION Keep retention on RAM section S13 when RAM section is switched off 29 29 On On 0x1 S14RETENTION Keep retention on RAM section S14 when RAM section is switched off 30 30 On On 0x1 S15RETENTION Keep retention on RAM section S15 when RAM section is switched off 31 31 On On 0x1 POWERCLR Description cluster: RAMn power control clear register 0x008 write-only 0x0000FFFF 0x20 S0POWER Keep RAM section S0 of RAMn on or off in System ON mode 0 0 Off Off 0x1 S1POWER Keep RAM section S1 of RAMn on or off in System ON mode 1 1 Off Off 0x1 S2POWER Keep RAM section S2 of RAMn on or off in System ON mode 2 2 Off Off 0x1 S3POWER Keep RAM section S3 of RAMn on or off in System ON mode 3 3 Off Off 0x1 S4POWER Keep RAM section S4 of RAMn on or off in System ON mode 4 4 Off Off 0x1 S5POWER Keep RAM section S5 of RAMn on or off in System ON mode 5 5 Off Off 0x1 S6POWER Keep RAM section S6 of RAMn on or off in System ON mode 6 6 Off Off 0x1 S7POWER Keep RAM section S7 of RAMn on or off in System ON mode 7 7 Off Off 0x1 S8POWER Keep RAM section S8 of RAMn on or off in System ON mode 8 8 Off Off 0x1 S9POWER Keep RAM section S9 of RAMn on or off in System ON mode 9 9 Off Off 0x1 S10POWER Keep RAM section S10 of RAMn on or off in System ON mode 10 10 Off Off 0x1 S11POWER Keep RAM section S11 of RAMn on or off in System ON mode 11 11 Off Off 0x1 S12POWER Keep RAM section S12 of RAMn on or off in System ON mode 12 12 Off Off 0x1 S13POWER Keep RAM section S13 of RAMn on or off in System ON mode 13 13 Off Off 0x1 S14POWER Keep RAM section S14 of RAMn on or off in System ON mode 14 14 Off Off 0x1 S15POWER Keep RAM section S15 of RAMn on or off in System ON mode 15 15 Off Off 0x1 S0RETENTION Keep retention on RAM section S0 when RAM section is switched off 16 16 Off Off 0x1 S1RETENTION Keep retention on RAM section S1 when RAM section is switched off 17 17 Off Off 0x1 S2RETENTION Keep retention on RAM section S2 when RAM section is switched off 18 18 Off Off 0x1 S3RETENTION Keep retention on RAM section S3 when RAM section is switched off 19 19 Off Off 0x1 S4RETENTION Keep retention on RAM section S4 when RAM section is switched off 20 20 Off Off 0x1 S5RETENTION Keep retention on RAM section S5 when RAM section is switched off 21 21 Off Off 0x1 S6RETENTION Keep retention on RAM section S6 when RAM section is switched off 22 22 Off Off 0x1 S7RETENTION Keep retention on RAM section S7 when RAM section is switched off 23 23 Off Off 0x1 S8RETENTION Keep retention on RAM section S8 when RAM section is switched off 24 24 Off Off 0x1 S9RETENTION Keep retention on RAM section S9 when RAM section is switched off 25 25 Off Off 0x1 S10RETENTION Keep retention on RAM section S10 when RAM section is switched off 26 26 Off Off 0x1 S11RETENTION Keep retention on RAM section S11 when RAM section is switched off 27 27 Off Off 0x1 S12RETENTION Keep retention on RAM section S12 when RAM section is switched off 28 28 Off Off 0x1 S13RETENTION Keep retention on RAM section S13 when RAM section is switched off 29 29 Off Off 0x1 S14RETENTION Keep retention on RAM section S14 when RAM section is switched off 30 30 Off Off 0x1 S15RETENTION Keep retention on RAM section S15 when RAM section is switched off 31 31 Off Off 0x1 P0 GPIO Port 0 0x50000000 GPIO 0 0x1000 registers GPIO 0x20 OUT Write GPIO port 0x504 read-write 0x00000000 0x20 PIN0 Pin 0 0 0 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN1 Pin 1 1 1 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN2 Pin 2 2 2 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN3 Pin 3 3 3 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN4 Pin 4 4 4 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN5 Pin 5 5 5 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN6 Pin 6 6 6 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN7 Pin 7 7 7 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN8 Pin 8 8 8 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN9 Pin 9 9 9 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN10 Pin 10 10 10 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN11 Pin 11 11 11 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN12 Pin 12 12 12 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN13 Pin 13 13 13 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN14 Pin 14 14 14 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN15 Pin 15 15 15 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN16 Pin 16 16 16 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN17 Pin 17 17 17 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN18 Pin 18 18 18 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN19 Pin 19 19 19 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN20 Pin 20 20 20 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN21 Pin 21 21 21 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN22 Pin 22 22 22 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN23 Pin 23 23 23 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN24 Pin 24 24 24 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN25 Pin 25 25 25 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN26 Pin 26 26 26 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN27 Pin 27 27 27 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN28 Pin 28 28 28 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN29 Pin 29 29 29 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN30 Pin 30 30 30 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN31 Pin 31 31 31 Low Pin driver is low 0x0 High Pin driver is high 0x1 OUTSET Set individual bits in GPIO port 0x508 read-write 0x00000000 oneToSet 0x20 PIN0 Pin 0 0 0 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: a '1' sets the pin high; a '0' has no effect 0x1 OUTCLR Clear individual bits in GPIO port 0x50C read-write 0x00000000 oneToClear 0x20 PIN0 Pin 0 0 0 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: a '1' sets the pin low; a '0' has no effect 0x1 IN Read GPIO port 0x510 read-only 0x00000000 0x20 PIN0 Pin 0 0 0 Low Pin input is low 0x0 High Pin input is high 0x1 PIN1 Pin 1 1 1 Low Pin input is low 0x0 High Pin input is high 0x1 PIN2 Pin 2 2 2 Low Pin input is low 0x0 High Pin input is high 0x1 PIN3 Pin 3 3 3 Low Pin input is low 0x0 High Pin input is high 0x1 PIN4 Pin 4 4 4 Low Pin input is low 0x0 High Pin input is high 0x1 PIN5 Pin 5 5 5 Low Pin input is low 0x0 High Pin input is high 0x1 PIN6 Pin 6 6 6 Low Pin input is low 0x0 High Pin input is high 0x1 PIN7 Pin 7 7 7 Low Pin input is low 0x0 High Pin input is high 0x1 PIN8 Pin 8 8 8 Low Pin input is low 0x0 High Pin input is high 0x1 PIN9 Pin 9 9 9 Low Pin input is low 0x0 High Pin input is high 0x1 PIN10 Pin 10 10 10 Low Pin input is low 0x0 High Pin input is high 0x1 PIN11 Pin 11 11 11 Low Pin input is low 0x0 High Pin input is high 0x1 PIN12 Pin 12 12 12 Low Pin input is low 0x0 High Pin input is high 0x1 PIN13 Pin 13 13 13 Low Pin input is low 0x0 High Pin input is high 0x1 PIN14 Pin 14 14 14 Low Pin input is low 0x0 High Pin input is high 0x1 PIN15 Pin 15 15 15 Low Pin input is low 0x0 High Pin input is high 0x1 PIN16 Pin 16 16 16 Low Pin input is low 0x0 High Pin input is high 0x1 PIN17 Pin 17 17 17 Low Pin input is low 0x0 High Pin input is high 0x1 PIN18 Pin 18 18 18 Low Pin input is low 0x0 High Pin input is high 0x1 PIN19 Pin 19 19 19 Low Pin input is low 0x0 High Pin input is high 0x1 PIN20 Pin 20 20 20 Low Pin input is low 0x0 High Pin input is high 0x1 PIN21 Pin 21 21 21 Low Pin input is low 0x0 High Pin input is high 0x1 PIN22 Pin 22 22 22 Low Pin input is low 0x0 High Pin input is high 0x1 PIN23 Pin 23 23 23 Low Pin input is low 0x0 High Pin input is high 0x1 PIN24 Pin 24 24 24 Low Pin input is low 0x0 High Pin input is high 0x1 PIN25 Pin 25 25 25 Low Pin input is low 0x0 High Pin input is high 0x1 PIN26 Pin 26 26 26 Low Pin input is low 0x0 High Pin input is high 0x1 PIN27 Pin 27 27 27 Low Pin input is low 0x0 High Pin input is high 0x1 PIN28 Pin 28 28 28 Low Pin input is low 0x0 High Pin input is high 0x1 PIN29 Pin 29 29 29 Low Pin input is low 0x0 High Pin input is high 0x1 PIN30 Pin 30 30 30 Low Pin input is low 0x0 High Pin input is high 0x1 PIN31 Pin 31 31 31 Low Pin input is low 0x0 High Pin input is high 0x1 DIR Direction of GPIO pins 0x514 read-write 0x00000000 0x20 PIN0 Pin 0 0 0 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN1 Pin 1 1 1 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN2 Pin 2 2 2 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN3 Pin 3 3 3 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN4 Pin 4 4 4 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN5 Pin 5 5 5 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN6 Pin 6 6 6 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN7 Pin 7 7 7 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN8 Pin 8 8 8 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN9 Pin 9 9 9 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN10 Pin 10 10 10 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN11 Pin 11 11 11 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN12 Pin 12 12 12 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN13 Pin 13 13 13 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN14 Pin 14 14 14 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN15 Pin 15 15 15 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN16 Pin 16 16 16 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN17 Pin 17 17 17 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN18 Pin 18 18 18 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN19 Pin 19 19 19 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN20 Pin 20 20 20 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN21 Pin 21 21 21 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN22 Pin 22 22 22 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN23 Pin 23 23 23 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN24 Pin 24 24 24 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN25 Pin 25 25 25 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN26 Pin 26 26 26 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN27 Pin 27 27 27 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN28 Pin 28 28 28 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN29 Pin 29 29 29 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN30 Pin 30 30 30 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN31 Pin 31 31 31 Input Pin set as input 0x0 Output Pin set as output 0x1 DIRSET DIR set register 0x518 read-write 0x00000000 oneToSet 0x20 PIN0 Set as output pin 0 0 0 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN1 Set as output pin 1 1 1 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN2 Set as output pin 2 2 2 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN3 Set as output pin 3 3 3 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN4 Set as output pin 4 4 4 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN5 Set as output pin 5 5 5 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN6 Set as output pin 6 6 6 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN7 Set as output pin 7 7 7 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN8 Set as output pin 8 8 8 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN9 Set as output pin 9 9 9 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN10 Set as output pin 10 10 10 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN11 Set as output pin 11 11 11 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN12 Set as output pin 12 12 12 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN13 Set as output pin 13 13 13 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN14 Set as output pin 14 14 14 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN15 Set as output pin 15 15 15 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN16 Set as output pin 16 16 16 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN17 Set as output pin 17 17 17 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN18 Set as output pin 18 18 18 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN19 Set as output pin 19 19 19 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN20 Set as output pin 20 20 20 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN21 Set as output pin 21 21 21 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN22 Set as output pin 22 22 22 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN23 Set as output pin 23 23 23 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN24 Set as output pin 24 24 24 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN25 Set as output pin 25 25 25 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN26 Set as output pin 26 26 26 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN27 Set as output pin 27 27 27 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN28 Set as output pin 28 28 28 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN29 Set as output pin 29 29 29 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN30 Set as output pin 30 30 30 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 PIN31 Set as output pin 31 31 31 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: a '1' sets pin to output; a '0' has no effect 0x1 DIRCLR DIR clear register 0x51C read-write 0x00000000 oneToClear 0x20 PIN0 Set as input pin 0 0 0 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN1 Set as input pin 1 1 1 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN2 Set as input pin 2 2 2 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN3 Set as input pin 3 3 3 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN4 Set as input pin 4 4 4 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN5 Set as input pin 5 5 5 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN6 Set as input pin 6 6 6 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN7 Set as input pin 7 7 7 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN8 Set as input pin 8 8 8 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN9 Set as input pin 9 9 9 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN10 Set as input pin 10 10 10 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN11 Set as input pin 11 11 11 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN12 Set as input pin 12 12 12 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN13 Set as input pin 13 13 13 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN14 Set as input pin 14 14 14 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN15 Set as input pin 15 15 15 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN16 Set as input pin 16 16 16 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN17 Set as input pin 17 17 17 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN18 Set as input pin 18 18 18 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN19 Set as input pin 19 19 19 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN20 Set as input pin 20 20 20 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN21 Set as input pin 21 21 21 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN22 Set as input pin 22 22 22 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN23 Set as input pin 23 23 23 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN24 Set as input pin 24 24 24 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN25 Set as input pin 25 25 25 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN26 Set as input pin 26 26 26 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN27 Set as input pin 27 27 27 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN28 Set as input pin 28 28 28 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN29 Set as input pin 29 29 29 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN30 Set as input pin 30 30 30 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 PIN31 Set as input pin 31 31 31 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: a '1' sets pin to input; a '0' has no effect 0x1 LATCH Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers 0x520 read-write 0x00000000 0x20 PIN0 Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. 0 0 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN1 Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. 1 1 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN2 Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. 2 2 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN3 Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. 3 3 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN4 Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. 4 4 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN5 Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. 5 5 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN6 Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. 6 6 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN7 Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. 7 7 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN8 Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. 8 8 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN9 Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. 9 9 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN10 Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. 10 10 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN11 Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. 11 11 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN12 Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. 12 12 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN13 Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. 13 13 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN14 Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. 14 14 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN15 Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. 15 15 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN16 Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. 16 16 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN17 Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. 17 17 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN18 Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. 18 18 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN19 Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. 19 19 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN20 Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. 20 20 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN21 Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. 21 21 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN22 Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. 22 22 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN23 Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. 23 23 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN24 Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. 24 24 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN25 Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. 25 25 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN26 Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. 26 26 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN27 Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. 27 27 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN28 Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. 28 28 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN29 Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. 29 29 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN30 Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. 30 30 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN31 Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. 31 31 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 DETECTMODE Select between default DETECT signal behavior and LDETECT mode 0x524 read-write 0x00000000 0x20 DETECTMODE Select between default DETECT signal behavior and LDETECT mode 0 0 Default DETECT directly connected to PIN DETECT signals 0x0 LDETECT Use the latched LDETECT behavior 0x1 0x20 0x4 PIN_CNF[%s] Description collection: Configuration of GPIO pins 0x700 read-write 0x00000002 0x20 DIR Pin direction. Same physical register as DIR register 0 0 Input Configure pin as an input pin 0x0 Output Configure pin as an output pin 0x1 INPUT Connect or disconnect input buffer 1 1 Connect Connect input buffer 0x0 Disconnect Disconnect input buffer 0x1 PULL Pull configuration 2 3 Disabled No pull 0x0 Pulldown Pull down on pin 0x1 Pullup Pull up on pin 0x3 DRIVE Drive configuration 8 10 S0S1 Standard '0', standard '1' 0x0 H0S1 High drive '0', standard '1' 0x1 S0H1 Standard '0', high drive '1' 0x2 H0H1 High drive '0', high 'drive '1'' 0x3 D0S1 Disconnect '0' standard '1' (normally used for wired-or connections) 0x4 D0H1 Disconnect '0', high drive '1' (normally used for wired-or connections) 0x5 S0D1 Standard '0'. disconnect '1' (normally used for wired-and connections) 0x6 H0D1 High drive '0', disconnect '1' (normally used for wired-and connections) 0x7 SENSE Pin sensing mechanism 16 17 Disabled Disabled 0x0 High Sense for high level 0x2 Low Sense for low level 0x3 P1 GPIO Port 1 0x50000300 P0 RADIO 2.4 GHz radio 0x40001000 0 0x1000 registers RADIO 1 RADIO 0x20 TASKS_TXEN Enable RADIO in TX mode 0x000 write-only 0x00000000 0x20 TASKS_TXEN Enable RADIO in TX mode 0 0 Trigger Trigger task 0x1 TASKS_RXEN Enable RADIO in RX mode 0x004 write-only 0x00000000 0x20 TASKS_RXEN Enable RADIO in RX mode 0 0 Trigger Trigger task 0x1 TASKS_START Start RADIO 0x008 write-only 0x00000000 0x20 TASKS_START Start RADIO 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop RADIO 0x00C write-only 0x00000000 0x20 TASKS_STOP Stop RADIO 0 0 Trigger Trigger task 0x1 TASKS_DISABLE Disable RADIO 0x010 write-only 0x00000000 0x20 TASKS_DISABLE Disable RADIO 0 0 Trigger Trigger task 0x1 TASKS_RSSISTART Start the RSSI and take one single sample of the receive signal strength 0x014 write-only 0x00000000 0x20 TASKS_RSSISTART Start the RSSI and take one single sample of the receive signal strength 0 0 Trigger Trigger task 0x1 TASKS_RSSISTOP Stop the RSSI measurement 0x018 write-only 0x00000000 0x20 TASKS_RSSISTOP Stop the RSSI measurement 0 0 Trigger Trigger task 0x1 TASKS_BCSTART Start the bit counter 0x01C write-only 0x00000000 0x20 TASKS_BCSTART Start the bit counter 0 0 Trigger Trigger task 0x1 TASKS_BCSTOP Stop the bit counter 0x020 write-only 0x00000000 0x20 TASKS_BCSTOP Stop the bit counter 0 0 Trigger Trigger task 0x1 TASKS_EDSTART Start the energy detect measurement used in IEEE 802.15.4 mode 0x024 write-only 0x00000000 0x20 TASKS_EDSTART Start the energy detect measurement used in IEEE 802.15.4 mode 0 0 Trigger Trigger task 0x1 TASKS_EDSTOP Stop the energy detect measurement 0x028 write-only 0x00000000 0x20 TASKS_EDSTOP Stop the energy detect measurement 0 0 Trigger Trigger task 0x1 TASKS_CCASTART Start the clear channel assessment used in IEEE 802.15.4 mode 0x02C write-only 0x00000000 0x20 TASKS_CCASTART Start the clear channel assessment used in IEEE 802.15.4 mode 0 0 Trigger Trigger task 0x1 TASKS_CCASTOP Stop the clear channel assessment 0x030 write-only 0x00000000 0x20 TASKS_CCASTOP Stop the clear channel assessment 0 0 Trigger Trigger task 0x1 EVENTS_READY RADIO has ramped up and is ready to be started 0x100 read-write 0x00000000 0x20 EVENTS_READY RADIO has ramped up and is ready to be started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ADDRESS Address sent or received 0x104 read-write 0x00000000 0x20 EVENTS_ADDRESS Address sent or received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_PAYLOAD Packet payload sent or received 0x108 read-write 0x00000000 0x20 EVENTS_PAYLOAD Packet payload sent or received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_END Packet sent or received 0x10C read-write 0x00000000 0x20 EVENTS_END Packet sent or received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DISABLED RADIO has been disabled 0x110 read-write 0x00000000 0x20 EVENTS_DISABLED RADIO has been disabled 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DEVMATCH A device address match occurred on the last received packet 0x114 read-write 0x00000000 0x20 EVENTS_DEVMATCH A device address match occurred on the last received packet 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DEVMISS No device address match occurred on the last received packet 0x118 read-write 0x00000000 0x20 EVENTS_DEVMISS No device address match occurred on the last received packet 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RSSIEND Sampling of receive signal strength complete 0x11C read-write 0x00000000 0x20 EVENTS_RSSIEND Sampling of receive signal strength complete 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_BCMATCH Bit counter reached bit count value 0x128 read-write 0x00000000 0x20 EVENTS_BCMATCH Bit counter reached bit count value 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CRCOK Packet received with CRC ok 0x130 read-write 0x00000000 0x20 EVENTS_CRCOK Packet received with CRC ok 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CRCERROR Packet received with CRC error 0x134 read-write 0x00000000 0x20 EVENTS_CRCERROR Packet received with CRC error 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_FRAMESTART IEEE 802.15.4 length field received 0x138 read-write 0x00000000 0x20 EVENTS_FRAMESTART IEEE 802.15.4 length field received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_EDEND Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0x13C read-write 0x00000000 0x20 EVENTS_EDEND Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_EDSTOPPED The sampling of energy detection has stopped 0x140 read-write 0x00000000 0x20 EVENTS_EDSTOPPED The sampling of energy detection has stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CCAIDLE Wireless medium in idle - clear to send 0x144 read-write 0x00000000 0x20 EVENTS_CCAIDLE Wireless medium in idle - clear to send 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CCABUSY Wireless medium busy - do not send 0x148 read-write 0x00000000 0x20 EVENTS_CCABUSY Wireless medium busy - do not send 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CCASTOPPED The CCA has stopped 0x14C read-write 0x00000000 0x20 EVENTS_CCASTOPPED The CCA has stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RATEBOOST Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. 0x150 read-write 0x00000000 0x20 EVENTS_RATEBOOST Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXREADY RADIO has ramped up and is ready to be started TX path 0x154 read-write 0x00000000 0x20 EVENTS_TXREADY RADIO has ramped up and is ready to be started TX path 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXREADY RADIO has ramped up and is ready to be started RX path 0x158 read-write 0x00000000 0x20 EVENTS_RXREADY RADIO has ramped up and is ready to be started RX path 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_MHRMATCH MAC header match found 0x15C read-write 0x00000000 0x20 EVENTS_MHRMATCH MAC header match found 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SYNC Preamble indicator. 0x168 read-write 0x00000000 0x20 EVENTS_SYNC Preamble indicator. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_PHYEND Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. 0x16C read-write 0x00000000 0x20 EVENTS_PHYEND Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 READY_START Shortcut between event READY and task START 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 END_DISABLE Shortcut between event END and task DISABLE 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DISABLED_TXEN Shortcut between event DISABLED and task TXEN 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DISABLED_RXEN Shortcut between event DISABLED and task RXEN 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 ADDRESS_RSSISTART Shortcut between event ADDRESS and task RSSISTART 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 END_START Shortcut between event END and task START 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 ADDRESS_BCSTART Shortcut between event ADDRESS and task BCSTART 6 6 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DISABLED_RSSISTOP Shortcut between event DISABLED and task RSSISTOP 8 8 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RXREADY_CCASTART Shortcut between event RXREADY and task CCASTART 11 11 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 CCAIDLE_TXEN Shortcut between event CCAIDLE and task TXEN 12 12 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 CCABUSY_DISABLE Shortcut between event CCABUSY and task DISABLE 13 13 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 FRAMESTART_BCSTART Shortcut between event FRAMESTART and task BCSTART 14 14 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 READY_EDSTART Shortcut between event READY and task EDSTART 15 15 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 EDEND_DISABLE Shortcut between event EDEND and task DISABLE 16 16 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 CCAIDLE_STOP Shortcut between event CCAIDLE and task STOP 17 17 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 TXREADY_START Shortcut between event TXREADY and task START 18 18 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RXREADY_START Shortcut between event RXREADY and task START 19 19 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 PHYEND_DISABLE Shortcut between event PHYEND and task DISABLE 20 20 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 PHYEND_START Shortcut between event PHYEND and task START 21 21 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ADDRESS Write '1' to enable interrupt for event ADDRESS 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PAYLOAD Write '1' to enable interrupt for event PAYLOAD 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 END Write '1' to enable interrupt for event END 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DISABLED Write '1' to enable interrupt for event DISABLED 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DEVMATCH Write '1' to enable interrupt for event DEVMATCH 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DEVMISS Write '1' to enable interrupt for event DEVMISS 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RSSIEND Write '1' to enable interrupt for event RSSIEND 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 BCMATCH Write '1' to enable interrupt for event BCMATCH 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CRCOK Write '1' to enable interrupt for event CRCOK 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CRCERROR Write '1' to enable interrupt for event CRCERROR 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 FRAMESTART Write '1' to enable interrupt for event FRAMESTART 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 EDEND Write '1' to enable interrupt for event EDEND 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 EDSTOPPED Write '1' to enable interrupt for event EDSTOPPED 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CCAIDLE Write '1' to enable interrupt for event CCAIDLE 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CCABUSY Write '1' to enable interrupt for event CCABUSY 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CCASTOPPED Write '1' to enable interrupt for event CCASTOPPED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RATEBOOST Write '1' to enable interrupt for event RATEBOOST 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXREADY Write '1' to enable interrupt for event TXREADY 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXREADY Write '1' to enable interrupt for event RXREADY 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 MHRMATCH Write '1' to enable interrupt for event MHRMATCH 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SYNC Write '1' to enable interrupt for event SYNC 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PHYEND Write '1' to enable interrupt for event PHYEND 27 27 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ADDRESS Write '1' to disable interrupt for event ADDRESS 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PAYLOAD Write '1' to disable interrupt for event PAYLOAD 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 END Write '1' to disable interrupt for event END 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DISABLED Write '1' to disable interrupt for event DISABLED 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DEVMATCH Write '1' to disable interrupt for event DEVMATCH 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DEVMISS Write '1' to disable interrupt for event DEVMISS 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RSSIEND Write '1' to disable interrupt for event RSSIEND 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 BCMATCH Write '1' to disable interrupt for event BCMATCH 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CRCOK Write '1' to disable interrupt for event CRCOK 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CRCERROR Write '1' to disable interrupt for event CRCERROR 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 FRAMESTART Write '1' to disable interrupt for event FRAMESTART 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 EDEND Write '1' to disable interrupt for event EDEND 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 EDSTOPPED Write '1' to disable interrupt for event EDSTOPPED 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CCAIDLE Write '1' to disable interrupt for event CCAIDLE 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CCABUSY Write '1' to disable interrupt for event CCABUSY 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CCASTOPPED Write '1' to disable interrupt for event CCASTOPPED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RATEBOOST Write '1' to disable interrupt for event RATEBOOST 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXREADY Write '1' to disable interrupt for event TXREADY 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXREADY Write '1' to disable interrupt for event RXREADY 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 MHRMATCH Write '1' to disable interrupt for event MHRMATCH 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SYNC Write '1' to disable interrupt for event SYNC 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PHYEND Write '1' to disable interrupt for event PHYEND 27 27 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CRCSTATUS CRC status 0x400 read-only 0x00000000 0x20 CRCSTATUS CRC status of packet received 0 0 CRCError Packet received with CRC error 0x0 CRCOk Packet received with CRC ok 0x1 RXMATCH Received address 0x408 read-only 0x00000000 0x20 RXMATCH Received address 0 2 RXCRC CRC field of previously received packet 0x40C read-only 0x00000000 0x20 RXCRC CRC field of previously received packet 0 23 DAI Device address match index 0x410 read-only 0x00000000 0x20 DAI Device address match index 0 2 PDUSTAT Payload status 0x414 read-only 0x00000000 0x20 PDUSTAT Status on payload length vs. PCNF1.MAXLEN 0 0 LessThan Payload less than PCNF1.MAXLEN 0x0 GreaterThan Payload greater than PCNF1.MAXLEN 0x1 CISTAT Status on what rate packet is received with in Long Range 1 2 LR125kbit Frame is received at 125kbps 0x0 LR500kbit Frame is received at 500kbps 0x1 PACKETPTR Packet pointer 0x504 read-write 0x00000000 0x20 PACKETPTR Packet pointer 0 31 FREQUENCY Frequency 0x508 read-write 0x00000002 0x20 FREQUENCY Radio channel frequency 0 6 MAP Channel map selection. 8 8 Default Channel map between 2400 MHZ .. 2500 MHz 0x0 Low Channel map between 2360 MHZ .. 2460 MHz 0x1 TXPOWER Output power 0x50C read-write 0x00000000 0x20 TXPOWER RADIO output power 0 7 Pos8dBm +8 dBm 0x08 Pos7dBm +7 dBm 0x07 Pos6dBm +6 dBm 0x06 Pos5dBm +5 dBm 0x05 Pos4dBm +4 dBm 0x04 Pos3dBm +3 dBm 0x03 Pos2dBm +2 dBm 0x02 0dBm 0 dBm 0x00 Neg4dBm -4 dBm 0xFC Neg8dBm -8 dBm 0xF8 Neg12dBm -12 dBm 0xF4 Neg16dBm -16 dBm 0xF0 Neg20dBm -20 dBm 0xEC Neg30dBm Deprecated enumerator - -40 dBm 0xE2 Neg40dBm -40 dBm 0xD8 MODE Data rate and modulation 0x510 read-write 0x00000000 0x20 MODE Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. 0 3 Nrf_1Mbit 1 Mbit/s Nordic proprietary radio mode 0x0 Nrf_2Mbit 2 Mbit/s Nordic proprietary radio mode 0x1 Ble_1Mbit 1 Mbit/s BLE 0x3 Ble_2Mbit 2 Mbit/s BLE 0x4 Ble_LR125Kbit Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX 0x5 Ble_LR500Kbit Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX 0x6 Ieee802154_250Kbit IEEE 802.15.4-2006 250 kbit/s 0xF PCNF0 Packet configuration register 0 0x514 read-write 0x00000000 0x20 LFLEN Length on air of LENGTH field in number of bits. 0 3 S0LEN Length on air of S0 field in number of bytes. 8 8 S1LEN Length on air of S1 field in number of bits. 16 19 S1INCL Include or exclude S1 field in RAM 20 20 Automatic Include S1 field in RAM only if S1LEN > 0 0x0 Include Always include S1 field in RAM independent of S1LEN 0x1 CILEN Length of code indicator - long range 22 23 PLEN Length of preamble on air. Decision point: TASKS_START task 24 25 8bit 8-bit preamble 0x0 16bit 16-bit preamble 0x1 32bitZero 32-bit zero preamble - used for IEEE 802.15.4 0x2 LongRange Preamble - used for BLE long range 0x3 CRCINC Indicates if LENGTH field contains CRC or not 26 26 Exclude LENGTH does not contain CRC 0x0 Include LENGTH includes CRC 0x1 TERMLEN Length of TERM field in Long Range operation 29 30 PCNF1 Packet configuration register 1 0x518 read-write 0x00000000 0x20 MAXLEN Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. 0 7 STATLEN Static length in number of bytes 8 15 BALEN Base address length in number of bytes 16 18 ENDIAN On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. 24 24 Little Least significant bit on air first 0x0 Big Most significant bit on air first 0x1 WHITEEN Enable or disable packet whitening 25 25 Disabled Disable 0x0 Enabled Enable 0x1 BASE0 Base address 0 0x51C read-write 0x00000000 0x20 BASE0 Base address 0 0 31 BASE1 Base address 1 0x520 read-write 0x00000000 0x20 BASE1 Base address 1 0 31 PREFIX0 Prefixes bytes for logical addresses 0-3 0x524 read-write 0x00000000 0x20 AP0 Address prefix 0. 0 7 AP1 Address prefix 1. 8 15 AP2 Address prefix 2. 16 23 AP3 Address prefix 3. 24 31 PREFIX1 Prefixes bytes for logical addresses 4-7 0x528 read-write 0x00000000 0x20 AP4 Address prefix 4. 0 7 AP5 Address prefix 5. 8 15 AP6 Address prefix 6. 16 23 AP7 Address prefix 7. 24 31 TXADDRESS Transmit address select 0x52C read-write 0x00000000 0x20 TXADDRESS Transmit address select 0 2 RXADDRESSES Receive address select 0x530 read-write 0x00000000 0x20 ADDR0 Enable or disable reception on logical address 0. 0 0 Disabled Disable 0x0 Enabled Enable 0x1 ADDR1 Enable or disable reception on logical address 1. 1 1 Disabled Disable 0x0 Enabled Enable 0x1 ADDR2 Enable or disable reception on logical address 2. 2 2 Disabled Disable 0x0 Enabled Enable 0x1 ADDR3 Enable or disable reception on logical address 3. 3 3 Disabled Disable 0x0 Enabled Enable 0x1 ADDR4 Enable or disable reception on logical address 4. 4 4 Disabled Disable 0x0 Enabled Enable 0x1 ADDR5 Enable or disable reception on logical address 5. 5 5 Disabled Disable 0x0 Enabled Enable 0x1 ADDR6 Enable or disable reception on logical address 6. 6 6 Disabled Disable 0x0 Enabled Enable 0x1 ADDR7 Enable or disable reception on logical address 7. 7 7 Disabled Disable 0x0 Enabled Enable 0x1 CRCCNF CRC configuration 0x534 read-write 0x00000000 0x20 LEN CRC length in number of bytes. 0 1 Disabled CRC length is zero and CRC calculation is disabled 0x0 One CRC length is one byte and CRC calculation is enabled 0x1 Two CRC length is two bytes and CRC calculation is enabled 0x2 Three CRC length is three bytes and CRC calculation is enabled 0x3 SKIPADDR Include or exclude packet address field out of CRC calculation. 8 9 Include CRC calculation includes address field 0x0 Skip CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. 0x1 Ieee802154 CRC calculation as per 802.15.4 standard. Starting at first byte after length field. 0x2 CRCPOLY CRC polynomial 0x538 read-write 0x00000000 0x20 CRCPOLY CRC polynomial 0 23 CRCINIT CRC initial value 0x53C read-write 0x00000000 0x20 CRCINIT CRC initial value 0 23 TIFS Interframe spacing in us 0x544 read-write 0x00000000 0x20 TIFS Interframe spacing in us 0 9 RSSISAMPLE RSSI sample 0x548 read-only 0x00000000 0x20 RSSISAMPLE RSSI sample 0 6 STATE Current radio state 0x550 read-only 0x00000000 0x20 STATE Current radio state 0 3 Disabled RADIO is in the Disabled state 0x0 RxRu RADIO is in the RXRU state 0x1 RxIdle RADIO is in the RXIDLE state 0x2 Rx RADIO is in the RX state 0x3 RxDisable RADIO is in the RXDISABLED state 0x4 TxRu RADIO is in the TXRU state 0x9 TxIdle RADIO is in the TXIDLE state 0xA Tx RADIO is in the TX state 0xB TxDisable RADIO is in the TXDISABLED state 0xC DATAWHITEIV Data whitening initial value 0x554 read-write 0x00000040 0x20 DATAWHITEIV Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. 0 6 BCC Bit counter compare 0x560 read-write 0x00000000 0x20 BCC Bit counter compare 0 31 0x8 0x4 DAB[%s] Description collection: Device address base segment n 0x600 read-write 0x00000000 0x20 DAB Device address base segment n 0 31 0x8 0x4 DAP[%s] Description collection: Device address prefix n 0x620 read-write 0x00000000 0x20 DAP Device address prefix n 0 15 DACNF Device address match configuration 0x640 read-write 0x00000000 0x20 ENA0 Enable or disable device address matching using device address 0 0 0 Disabled Disabled 0x0 Enabled Enabled 0x1 ENA1 Enable or disable device address matching using device address 1 1 1 Disabled Disabled 0x0 Enabled Enabled 0x1 ENA2 Enable or disable device address matching using device address 2 2 2 Disabled Disabled 0x0 Enabled Enabled 0x1 ENA3 Enable or disable device address matching using device address 3 3 3 Disabled Disabled 0x0 Enabled Enabled 0x1 ENA4 Enable or disable device address matching using device address 4 4 4 Disabled Disabled 0x0 Enabled Enabled 0x1 ENA5 Enable or disable device address matching using device address 5 5 5 Disabled Disabled 0x0 Enabled Enabled 0x1 ENA6 Enable or disable device address matching using device address 6 6 6 Disabled Disabled 0x0 Enabled Enabled 0x1 ENA7 Enable or disable device address matching using device address 7 7 7 Disabled Disabled 0x0 Enabled Enabled 0x1 TXADD0 TxAdd for device address 0 8 8 TXADD1 TxAdd for device address 1 9 9 TXADD2 TxAdd for device address 2 10 10 TXADD3 TxAdd for device address 3 11 11 TXADD4 TxAdd for device address 4 12 12 TXADD5 TxAdd for device address 5 13 13 TXADD6 TxAdd for device address 6 14 14 TXADD7 TxAdd for device address 7 15 15 MHRMATCHCONF Search pattern configuration 0x644 read-write 0x00000000 0x20 MHRMATCHCONF Search pattern configuration 0 31 MHRMATCHMAS Pattern mask 0x648 read-write 0x00000000 0x20 MHRMATCHMAS Pattern mask 0 31 MODECNF0 Radio mode configuration register 0 0x650 read-write 0x00000200 0x20 RU Radio ramp-up time 0 0 Default Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 0x0 Fast Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information 0x1 DTX Default TX value 8 9 B1 Transmit '1' 0x0 B0 Transmit '0' 0x1 Center Transmit center frequency 0x2 SFD IEEE 802.15.4 start of frame delimiter 0x660 read-write 0x000000A7 0x20 SFD IEEE 802.15.4 start of frame delimiter 0 7 EDCNT IEEE 802.15.4 energy detect loop count 0x664 read-write 0x00000000 0x20 EDCNT IEEE 802.15.4 energy detect loop count 0 20 EDSAMPLE IEEE 802.15.4 energy detect level 0x668 read-write 0x00000000 0x20 EDLVL IEEE 802.15.4 energy detect level 0 7 CCACTRL IEEE 802.15.4 clear channel assessment control 0x66C read-write 0x052D0000 0x20 CCAMODE CCA mode of operation 0 2 EdMode Energy above threshold 0x0 CarrierMode Carrier seen 0x1 CarrierAndEdMode Energy above threshold AND carrier seen 0x2 CarrierOrEdMode Energy above threshold OR carrier seen 0x3 EdModeTest1 Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. 0x4 CCAEDTHRES CCA energy busy threshold. Used in all the CCA modes except CarrierMode. 8 15 CCACORRTHRES CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. 16 23 CCACORRCNT Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. 24 31 POWER Peripheral power control 0xFFC read-write 0x00000001 0x20 POWER Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. 0 0 Disabled Peripheral is powered off 0x0 Enabled Peripheral is powered on 0x1 UART0 Universal Asynchronous Receiver/Transmitter 0x40002000 UART 0 0x1000 registers UART0_UARTE0 2 UART 0x20 TASKS_STARTRX Start UART receiver 0x000 write-only 0x00000000 0x20 TASKS_STARTRX Start UART receiver 0 0 Trigger Trigger task 0x1 TASKS_STOPRX Stop UART receiver 0x004 write-only 0x00000000 0x20 TASKS_STOPRX Stop UART receiver 0 0 Trigger Trigger task 0x1 TASKS_STARTTX Start UART transmitter 0x008 write-only 0x00000000 0x20 TASKS_STARTTX Start UART transmitter 0 0 Trigger Trigger task 0x1 TASKS_STOPTX Stop UART transmitter 0x00C write-only 0x00000000 0x20 TASKS_STOPTX Stop UART transmitter 0 0 Trigger Trigger task 0x1 TASKS_SUSPEND Suspend UART 0x01C write-only 0x00000000 0x20 TASKS_SUSPEND Suspend UART 0 0 Trigger Trigger task 0x1 EVENTS_CTS CTS is activated (set low). Clear To Send. 0x100 read-write 0x00000000 0x20 EVENTS_CTS CTS is activated (set low). Clear To Send. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0x104 read-write 0x00000000 0x20 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXDRDY Data received in RXD 0x108 read-write 0x00000000 0x20 EVENTS_RXDRDY Data received in RXD 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXDRDY Data sent from TXD 0x11C read-write 0x00000000 0x20 EVENTS_TXDRDY Data sent from TXD 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR Error detected 0x124 read-write 0x00000000 0x20 EVENTS_ERROR Error detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXTO Receiver timeout 0x144 read-write 0x00000000 0x20 EVENTS_RXTO Receiver timeout 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 CTS_STARTRX Shortcut between event CTS and task STARTRX 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 NCTS_STOPRX Shortcut between event NCTS and task STOPRX 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 CTS Write '1' to enable interrupt for event CTS 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 NCTS Write '1' to enable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXDRDY Write '1' to enable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXDRDY Write '1' to enable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXTO Write '1' to enable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 CTS Write '1' to disable interrupt for event CTS 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 NCTS Write '1' to disable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXDRDY Write '1' to disable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXDRDY Write '1' to disable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXTO Write '1' to disable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSRC Error source 0x480 read-write 0x00000000 oneToClear 0x20 OVERRUN Overrun error 0 0 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 PARITY Parity error 1 1 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 FRAMING Framing error occurred 2 2 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 BREAK Break condition 3 3 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 ENABLE Enable UART 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable UART 0 3 Disabled Disable UART 0x0 Enabled Enable UART 0x4 PSEL Unspecified UART_PSEL read-write 0x508 RTS Pin select for RTS 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 TXD Pin select for TXD 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 CTS Pin select for CTS 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD Pin select for RXD 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD RXD register. Register is cleared on read and the double buffered byte will be moved to RXD if it exists. 0x518 read-only 0x00000000 modifyExternal 0x20 RXD RX data received in previous transfers, double buffered 0 7 TXD TXD register 0x51C write-only 0x00000000 0x20 TXD TX data to be transferred 0 7 BAUDRATE Baud rate. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 BAUDRATE Baud rate 0 31 Baud1200 1200 baud (actual rate: 1205) 0x0004F000 Baud2400 2400 baud (actual rate: 2396) 0x0009D000 Baud4800 4800 baud (actual rate: 4808) 0x0013B000 Baud9600 9600 baud (actual rate: 9598) 0x00275000 Baud14400 14400 baud (actual rate: 14414) 0x003B0000 Baud19200 19200 baud (actual rate: 19208) 0x004EA000 Baud28800 28800 baud (actual rate: 28829) 0x0075F000 Baud31250 31250 baud 0x00800000 Baud38400 38400 baud (actual rate: 38462) 0x009D5000 Baud56000 56000 baud (actual rate: 55944) 0x00E50000 Baud57600 57600 baud (actual rate: 57762) 0x00EBF000 Baud76800 76800 baud (actual rate: 76923) 0x013A9000 Baud115200 115200 baud (actual rate: 115942) 0x01D7E000 Baud230400 230400 baud (actual rate: 231884) 0x03AFB000 Baud250000 250000 baud 0x04000000 Baud460800 460800 baud (actual rate: 470588) 0x075F7000 Baud921600 921600 baud (actual rate: 941176) 0x0EBED000 Baud1M 1Mega baud 0x10000000 CONFIG Configuration of parity and hardware flow control 0x56C read-write 0x00000000 0x20 HWFC Hardware flow control 0 0 Disabled Disabled 0x0 Enabled Enabled 0x1 PARITY Parity 1 3 Excluded Exclude parity bit 0x0 Included Include parity bit 0x7 STOP Stop bits 4 4 One One stop bit 0x0 Two Two stop bits 0x1 UARTE0 UART with EasyDMA 0 0x40002000 UART0 UARTE 0 0x1000 registers UART0_UARTE0 2 UARTE 0x20 TASKS_STARTRX Start UART receiver 0x000 write-only 0x00000000 0x20 TASKS_STARTRX Start UART receiver 0 0 Trigger Trigger task 0x1 TASKS_STOPRX Stop UART receiver 0x004 write-only 0x00000000 0x20 TASKS_STOPRX Stop UART receiver 0 0 Trigger Trigger task 0x1 TASKS_STARTTX Start UART transmitter 0x008 write-only 0x00000000 0x20 TASKS_STARTTX Start UART transmitter 0 0 Trigger Trigger task 0x1 TASKS_STOPTX Stop UART transmitter 0x00C write-only 0x00000000 0x20 TASKS_STOPTX Stop UART transmitter 0 0 Trigger Trigger task 0x1 TASKS_FLUSHRX Flush RX FIFO into RX buffer 0x02C write-only 0x00000000 0x20 TASKS_FLUSHRX Flush RX FIFO into RX buffer 0 0 Trigger Trigger task 0x1 EVENTS_CTS CTS is activated (set low). Clear To Send. 0x100 read-write 0x00000000 0x20 EVENTS_CTS CTS is activated (set low). Clear To Send. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0x104 read-write 0x00000000 0x20 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0x108 read-write 0x00000000 0x20 EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDRX Receive buffer is filled up 0x110 read-write 0x00000000 0x20 EVENTS_ENDRX Receive buffer is filled up 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXDRDY Data sent from TXD 0x11C read-write 0x00000000 0x20 EVENTS_TXDRDY Data sent from TXD 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDTX Last TX byte transmitted 0x120 read-write 0x00000000 0x20 EVENTS_ENDTX Last TX byte transmitted 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR Error detected 0x124 read-write 0x00000000 0x20 EVENTS_ERROR Error detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXTO Receiver timeout 0x144 read-write 0x00000000 0x20 EVENTS_RXTO Receiver timeout 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXSTARTED UART receiver has started 0x14C read-write 0x00000000 0x20 EVENTS_RXSTARTED UART receiver has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXSTARTED UART transmitter has started 0x150 read-write 0x00000000 0x20 EVENTS_TXSTARTED UART transmitter has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXSTOPPED Transmitter stopped 0x158 read-write 0x00000000 0x20 EVENTS_TXSTOPPED Transmitter stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 ENDRX_STARTRX Shortcut between event ENDRX and task STARTRX 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 ENDRX_STOPRX Shortcut between event ENDRX and task STOPRX 6 6 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 CTS Enable or disable interrupt for event CTS 0 0 Disabled Disable 0x0 Enabled Enable 0x1 NCTS Enable or disable interrupt for event NCTS 1 1 Disabled Disable 0x0 Enabled Enable 0x1 RXDRDY Enable or disable interrupt for event RXDRDY 2 2 Disabled Disable 0x0 Enabled Enable 0x1 ENDRX Enable or disable interrupt for event ENDRX 4 4 Disabled Disable 0x0 Enabled Enable 0x1 TXDRDY Enable or disable interrupt for event TXDRDY 7 7 Disabled Disable 0x0 Enabled Enable 0x1 ENDTX Enable or disable interrupt for event ENDTX 8 8 Disabled Disable 0x0 Enabled Enable 0x1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0x0 Enabled Enable 0x1 RXTO Enable or disable interrupt for event RXTO 17 17 Disabled Disable 0x0 Enabled Enable 0x1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0x0 Enabled Enable 0x1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0x0 Enabled Enable 0x1 TXSTOPPED Enable or disable interrupt for event TXSTOPPED 22 22 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 CTS Write '1' to enable interrupt for event CTS 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 NCTS Write '1' to enable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXDRDY Write '1' to enable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXDRDY Write '1' to enable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDTX Write '1' to enable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXTO Write '1' to enable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXSTOPPED Write '1' to enable interrupt for event TXSTOPPED 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 CTS Write '1' to disable interrupt for event CTS 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 NCTS Write '1' to disable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXDRDY Write '1' to disable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXDRDY Write '1' to disable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDTX Write '1' to disable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXTO Write '1' to disable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXSTOPPED Write '1' to disable interrupt for event TXSTOPPED 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSRC Error source This register is read/write one to clear. 0x480 read-write 0x00000000 oneToClear 0x20 OVERRUN Overrun error 0 0 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 PARITY Parity error 1 1 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 FRAMING Framing error occurred 2 2 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 BREAK Break condition 3 3 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 ENABLE Enable UART 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable UARTE 0 3 Disabled Disable UARTE 0x0 Enabled Enable UARTE 0x8 PSEL Unspecified UARTE_PSEL read-write 0x508 RTS Pin select for RTS signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 TXD Pin select for TXD signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 CTS Pin select for CTS signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD Pin select for RXD signal 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 BAUDRATE Baud rate. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 BAUDRATE Baud rate 0 31 Baud1200 1200 baud (actual rate: 1205) 0x0004F000 Baud2400 2400 baud (actual rate: 2396) 0x0009D000 Baud4800 4800 baud (actual rate: 4808) 0x0013B000 Baud9600 9600 baud (actual rate: 9598) 0x00275000 Baud14400 14400 baud (actual rate: 14401) 0x003AF000 Baud19200 19200 baud (actual rate: 19208) 0x004EA000 Baud28800 28800 baud (actual rate: 28777) 0x0075C000 Baud31250 31250 baud 0x00800000 Baud38400 38400 baud (actual rate: 38369) 0x009D0000 Baud56000 56000 baud (actual rate: 55944) 0x00E50000 Baud57600 57600 baud (actual rate: 57554) 0x00EB0000 Baud76800 76800 baud (actual rate: 76923) 0x013A9000 Baud115200 115200 baud (actual rate: 115108) 0x01D60000 Baud230400 230400 baud (actual rate: 231884) 0x03B00000 Baud250000 250000 baud 0x04000000 Baud460800 460800 baud (actual rate: 457143) 0x07400000 Baud921600 921600 baud (actual rate: 941176) 0x0F000000 Baud1M 1 megabaud 0x10000000 RXD RXD EasyDMA channel UARTE_RXD read-write 0x534 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in receive buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 15 TXD TXD EasyDMA channel UARTE_TXD read-write 0x544 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in transmit buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 15 CONFIG Configuration of parity and hardware flow control 0x56C read-write 0x00000000 0x20 HWFC Hardware flow control 0 0 Disabled Disabled 0x0 Enabled Enabled 0x1 PARITY Parity 1 3 Excluded Exclude parity bit 0x0 Included Include even parity bit 0x7 STOP Stop bits 4 4 One One stop bit 0x0 Two Two stop bits 0x1 SPI0 Serial Peripheral Interface 0 0x40003000 SPI 0 0x1000 registers SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 3 SPI 0x20 EVENTS_READY TXD byte sent and RXD byte received 0x108 read-write 0x00000000 0x20 EVENTS_READY TXD byte sent and RXD byte received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE Enable SPI 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable SPI 0 3 Disabled Disable SPI 0x0 Enabled Enable SPI 0x1 PSEL Unspecified SPI_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MOSI Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MISO Pin select for MISO signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD RXD register. Register is cleared on read and the buffer pointer will be modified if read. 0x518 read-only 0x00000000 modifyExternal 0x20 RXD RX data received. Double buffered 0 7 TXD TXD register 0x51C read-write 0x00000000 0x20 TXD TX data to send. Double buffered. 0 7 FREQUENCY SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 FREQUENCY SPI master data rate 0 31 K125 125 kbps 0x02000000 K250 250 kbps 0x04000000 K500 500 kbps 0x08000000 M1 1 Mbps 0x10000000 M2 2 Mbps 0x20000000 M4 4 Mbps 0x40000000 M8 8 Mbps 0x80000000 CONFIG Configuration register 0x554 read-write 0x00000000 0x20 ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0x0 LsbFirst Least significant bit shifted out first 0x1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0x0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 0x1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0x0 ActiveLow Active low 0x1 SPIM0 Serial Peripheral Interface Master with EasyDMA 0 0x40003000 SPI0 SPIM 0 0x1000 registers SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 3 SPIM 0x20 TASKS_START Start SPI transaction 0x010 write-only 0x00000000 0x20 TASKS_START Start SPI transaction 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop SPI transaction 0x014 write-only 0x00000000 0x20 TASKS_STOP Stop SPI transaction 0 0 Trigger Trigger task 0x1 TASKS_SUSPEND Suspend SPI transaction 0x01C write-only 0x00000000 0x20 TASKS_SUSPEND Suspend SPI transaction 0 0 Trigger Trigger task 0x1 TASKS_RESUME Resume SPI transaction 0x020 write-only 0x00000000 0x20 TASKS_RESUME Resume SPI transaction 0 0 Trigger Trigger task 0x1 EVENTS_STOPPED SPI transaction has stopped 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED SPI transaction has stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write 0x00000000 0x20 EVENTS_ENDRX End of RXD buffer reached 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_END End of RXD buffer and TXD buffer reached 0x118 read-write 0x00000000 0x20 EVENTS_END End of RXD buffer and TXD buffer reached 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDTX End of TXD buffer reached 0x120 read-write 0x00000000 0x20 EVENTS_ENDTX End of TXD buffer reached 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STARTED Transaction started 0x14C read-write 0x00000000 0x20 EVENTS_STARTED Transaction started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 END_START Shortcut between event END and task START 17 17 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 END Write '1' to enable interrupt for event END 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDTX Write '1' to enable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STARTED Write '1' to enable interrupt for event STARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 END Write '1' to disable interrupt for event END 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDTX Write '1' to disable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STARTED Write '1' to disable interrupt for event STARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STALLSTAT Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. 0x400 read-write 0x00000000 0x20 TX Stall status for EasyDMA RAM reads 0 0 NOSTALL No stall 0x0 STALL A stall has occurred 0x1 RX Stall status for EasyDMA RAM writes 1 1 NOSTALL No stall 0x0 STALL A stall has occurred 0x1 ENABLE Enable SPIM 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable SPIM 0 3 Disabled Disable SPIM 0x0 Enabled Enable SPIM 0x7 PSEL Unspecified SPIM_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MOSI Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MISO Pin select for MISO signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 CSN Pin select for CSN 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 FREQUENCY SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 FREQUENCY SPI master data rate 0 31 K125 125 kbps 0x02000000 K250 250 kbps 0x04000000 K500 500 kbps 0x08000000 M1 1 Mbps 0x10000000 M2 2 Mbps 0x20000000 M4 4 Mbps 0x40000000 M8 8 Mbps 0x80000000 M16 16 Mbps 0x0A000000 M32 32 Mbps 0x14000000 RXD RXD EasyDMA channel SPIM_RXD read-write 0x534 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in receive buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 15 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 TXD TXD EasyDMA channel SPIM_TXD read-write 0x544 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Number of bytes in transmit buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in transmit buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 15 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 CONFIG Configuration register 0x554 read-write 0x00000000 0x20 ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0x0 LsbFirst Least significant bit shifted out first 0x1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0x0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 0x1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0x0 ActiveLow Active low 0x1 IFTIMING Unspecified SPIM_IFTIMING read-write 0x560 RXDELAY Sample delay for input serial data on MISO 0x000 read-write 0x00000002 0x20 RXDELAY Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. 0 2 CSNDUR Minimum duration between edge of CSN and edge of SCK at the start and the end of a transaction, and minimum duration CSN will stay high between transactions if END-START shortcut is used 0x004 read-write 0x00000002 0x20 CSNDUR Minimum duration between edge of CSN and edge of SCK at the start and end of a transaction. If END-START shortcut is used, minimum duration CSN will stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). 0 7 CSNPOL Polarity of CSN output 0x568 read-write 0x00000000 0x20 CSNPOL Polarity of CSN output 0 0 LOW Active low (idle state high) 0x0 HIGH Active high (idle state low) 0x1 PSELDCX Pin select for DCX signal 0x56C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 DCXCNT DCX configuration 0x570 read-write 0x00000000 0x20 DCXCNT This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. 0 3 ORC Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT 0x5C0 read-write 0x00000000 0x20 ORC Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. 0 7 SPIS0 SPI Slave 0 0x40003000 SPI0 SPIS 0 0x1000 registers SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 3 SPIS 0x20 TASKS_ACQUIRE Acquire SPI semaphore 0x024 write-only 0x00000000 0x20 TASKS_ACQUIRE Acquire SPI semaphore 0 0 Trigger Trigger task 0x1 TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0x028 write-only 0x00000000 0x20 TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0 0 Trigger Trigger task 0x1 EVENTS_END Granted transaction completed 0x104 read-write 0x00000000 0x20 EVENTS_END Granted transaction completed 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write 0x00000000 0x20 EVENTS_ENDRX End of RXD buffer reached 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ACQUIRED Semaphore acquired 0x128 read-write 0x00000000 0x20 EVENTS_ACQUIRED Semaphore acquired 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 END_ACQUIRE Shortcut between event END and task ACQUIRE 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 END Write '1' to enable interrupt for event END 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACQUIRED Write '1' to enable interrupt for event ACQUIRED 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 END Write '1' to disable interrupt for event END 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACQUIRED Write '1' to disable interrupt for event ACQUIRED 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEMSTAT Semaphore status register 0x400 read-only 0x00000001 0x20 SEMSTAT Semaphore status 0 1 Free Semaphore is free 0x0 CPU Semaphore is assigned to CPU 0x1 SPIS Semaphore is assigned to SPI slave 0x2 CPUPending Semaphore is assigned to SPI but a handover to the CPU is pending 0x3 STATUS Status from last transaction 0x440 read-write 0x00000000 0x20 OVERREAD TX buffer over-read detected, and prevented 0 0 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 write Clear Write: clear error on writing '1' 0x1 OVERFLOW RX buffer overflow detected, and prevented 1 1 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 write Clear Write: clear error on writing '1' 0x1 ENABLE Enable SPI slave 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable SPI slave 0 3 Disabled Disable SPI slave 0x0 Enabled Enable SPI slave 0x2 PSEL Unspecified SPIS_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MISO Pin select for MISO signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MOSI Pin select for MOSI signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 CSN Pin select for CSN signal 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD Unspecified SPIS_RXD read-write 0x534 PTR RXD data pointer 0x000 read-write 0x00000000 0x20 PTR RXD data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in receive buffer 0 15 AMOUNT Number of bytes received in last granted transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes received in the last granted transaction 0 15 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 TXD Unspecified SPIS_TXD read-write 0x544 PTR TXD data pointer 0x000 read-write 0x00000000 0x20 PTR TXD data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in transmit buffer 0 15 AMOUNT Number of bytes transmitted in last granted transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transmitted in last granted transaction 0 15 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 CONFIG Configuration register 0x554 read-write 0x00000000 0x20 ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0x0 LsbFirst Least significant bit shifted out first 0x1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0x0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 0x1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0x0 ActiveLow Active low 0x1 DEF Default character. Character clocked out in case of an ignored transaction. 0x55C read-write 0x00000000 0x20 DEF Default character. Character clocked out in case of an ignored transaction. 0 7 ORC Over-read character 0x5C0 read-write 0x00000000 0x20 ORC Over-read character. Character clocked out after an over-read of the transmit buffer. 0 7 TWI0 I2C compatible Two-Wire Interface 0 0x40003000 SPI0 TWI 0 0x1000 registers SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 3 TWI 0x20 TASKS_STARTRX Start TWI receive sequence 0x000 write-only 0x00000000 0x20 TASKS_STARTRX Start TWI receive sequence 0 0 Trigger Trigger task 0x1 TASKS_STARTTX Start TWI transmit sequence 0x008 write-only 0x00000000 0x20 TASKS_STARTTX Start TWI transmit sequence 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop TWI transaction 0x014 write-only 0x00000000 0x20 TASKS_STOP Stop TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only 0x00000000 0x20 TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_RESUME Resume TWI transaction 0x020 write-only 0x00000000 0x20 TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 0x1 EVENTS_STOPPED TWI stopped 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXDREADY TWI RXD byte received 0x108 read-write 0x00000000 0x20 EVENTS_RXDREADY TWI RXD byte received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXDSENT TWI TXD byte sent 0x11C read-write 0x00000000 0x20 EVENTS_TXDSENT TWI TXD byte sent 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR TWI error 0x124 read-write 0x00000000 0x20 EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_BB TWI byte boundary, generated before each byte that is sent or received 0x138 read-write 0x00000000 0x20 EVENTS_BB TWI byte boundary, generated before each byte that is sent or received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SUSPENDED TWI entered the suspended state 0x148 read-write 0x00000000 0x20 EVENTS_SUSPENDED TWI entered the suspended state 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 BB_SUSPEND Shortcut between event BB and task SUSPEND 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 BB_STOP Shortcut between event BB and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXDREADY Write '1' to enable interrupt for event RXDREADY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXDSENT Write '1' to enable interrupt for event TXDSENT 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 BB Write '1' to enable interrupt for event BB 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SUSPENDED Write '1' to enable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXDREADY Write '1' to disable interrupt for event RXDREADY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXDSENT Write '1' to disable interrupt for event TXDSENT 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 BB Write '1' to disable interrupt for event BB 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SUSPENDED Write '1' to disable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSRC Error source 0x4C4 read-write 0x00000000 oneToClear 0x20 OVERRUN Overrun error 0 0 read NotPresent Read: no overrun occured 0x0 Present Read: overrun occured 0x1 ANACK NACK received after sending the address (write '1' to clear) 1 1 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 DNACK NACK received after sending a data byte (write '1' to clear) 2 2 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 ENABLE Enable TWI 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable TWI 0 3 Disabled Disable TWI 0x0 Enabled Enable TWI 0x5 PSEL Unspecified TWI_PSEL read-write 0x508 SCL Pin select for SCL 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDA Pin select for SDA 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD RXD register. Register is cleared on read and the buffer pointer will be modified if read. 0x518 read-only 0x00000000 modifyExternal 0x20 RXD RXD register 0 7 TXD TXD register 0x51C read-write 0x00000000 0x20 TXD TXD register 0 7 FREQUENCY TWI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 FREQUENCY TWI master clock frequency 0 31 K100 100 kbps 0x01980000 K250 250 kbps 0x04000000 K400 400 kbps (actual rate 410.256 kbps) 0x06680000 ADDRESS Address used in the TWI transfer 0x588 read-write 0x00000000 0x20 ADDRESS Address used in the TWI transfer 0 6 TWIM0 I2C compatible Two-Wire Master Interface with EasyDMA 0 0x40003000 SPI0 TWIM 0 0x1000 registers SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 3 TWIM 0x20 TASKS_STARTRX Start TWI receive sequence 0x000 write-only 0x00000000 0x20 TASKS_STARTRX Start TWI receive sequence 0 0 Trigger Trigger task 0x1 TASKS_STARTTX Start TWI transmit sequence 0x008 write-only 0x00000000 0x20 TASKS_STARTTX Start TWI transmit sequence 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0x014 write-only 0x00000000 0x20 TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0 0 Trigger Trigger task 0x1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only 0x00000000 0x20 TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_RESUME Resume TWI transaction 0x020 write-only 0x00000000 0x20 TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 0x1 EVENTS_STOPPED TWI stopped 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR TWI error 0x124 read-write 0x00000000 0x20 EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SUSPENDED SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write 0x00000000 0x20 EVENTS_SUSPENDED SUSPEND task has been issued, TWI traffic is now suspended. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXSTARTED Receive sequence started 0x14C read-write 0x00000000 0x20 EVENTS_RXSTARTED Receive sequence started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write 0x00000000 0x20 EVENTS_TXSTARTED Transmit sequence started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_LASTRX Byte boundary, starting to receive the last byte 0x15C read-write 0x00000000 0x20 EVENTS_LASTRX Byte boundary, starting to receive the last byte 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0x160 read-write 0x00000000 0x20 EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 LASTTX_STARTRX Shortcut between event LASTTX and task STARTRX 7 7 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTTX_SUSPEND Shortcut between event LASTTX and task SUSPEND 8 8 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTTX_STOP Shortcut between event LASTTX and task STOP 9 9 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTRX_STARTTX Shortcut between event LASTRX and task STARTTX 10 10 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTRX_SUSPEND Shortcut between event LASTRX and task SUSPEND 11 11 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTRX_STOP Shortcut between event LASTRX and task STOP 12 12 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0x0 Enabled Enable 0x1 SUSPENDED Enable or disable interrupt for event SUSPENDED 18 18 Disabled Disable 0x0 Enabled Enable 0x1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0x0 Enabled Enable 0x1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0x0 Enabled Enable 0x1 LASTRX Enable or disable interrupt for event LASTRX 23 23 Disabled Disable 0x0 Enabled Enable 0x1 LASTTX Enable or disable interrupt for event LASTTX 24 24 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SUSPENDED Write '1' to enable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 LASTRX Write '1' to enable interrupt for event LASTRX 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 LASTTX Write '1' to enable interrupt for event LASTTX 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SUSPENDED Write '1' to disable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 LASTRX Write '1' to disable interrupt for event LASTRX 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 LASTTX Write '1' to disable interrupt for event LASTTX 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSRC Error source 0x4C4 read-write 0x00000000 oneToClear 0x20 OVERRUN Overrun error 0 0 NotReceived Error did not occur 0x0 Received Error occurred 0x1 ANACK NACK received after sending the address (write '1' to clear) 1 1 NotReceived Error did not occur 0x0 Received Error occurred 0x1 DNACK NACK received after sending a data byte (write '1' to clear) 2 2 NotReceived Error did not occur 0x0 Received Error occurred 0x1 ENABLE Enable TWIM 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable TWIM 0 3 Disabled Disable TWIM 0x0 Enabled Enable TWIM 0x6 PSEL Unspecified TWIM_PSEL read-write 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 FREQUENCY TWI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 FREQUENCY TWI master clock frequency 0 31 K100 100 kbps 0x01980000 K250 250 kbps 0x04000000 K400 400 kbps 0x06400000 RXD RXD EasyDMA channel TWIM_RXD read-write 0x534 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in receive buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 15 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 2 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 TXD TXD EasyDMA channel TWIM_TXD read-write 0x544 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in transmit buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 15 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 2 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 ADDRESS Address used in the TWI transfer 0x588 read-write 0x00000000 0x20 ADDRESS Address used in the TWI transfer 0 6 TWIS0 I2C compatible Two-Wire Slave Interface with EasyDMA 0 0x40003000 SPI0 TWIS 0 0x1000 registers SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 3 TWIS 0x20 TASKS_STOP Stop TWI transaction 0x014 write-only 0x00000000 0x20 TASKS_STOP Stop TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only 0x00000000 0x20 TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_RESUME Resume TWI transaction 0x020 write-only 0x00000000 0x20 TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0x030 write-only 0x00000000 0x20 TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0 0 Trigger Trigger task 0x1 TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0x034 write-only 0x00000000 0x20 TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0 0 Trigger Trigger task 0x1 EVENTS_STOPPED TWI stopped 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR TWI error 0x124 read-write 0x00000000 0x20 EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXSTARTED Receive sequence started 0x14C read-write 0x00000000 0x20 EVENTS_RXSTARTED Receive sequence started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write 0x00000000 0x20 EVENTS_TXSTARTED Transmit sequence started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_WRITE Write command received 0x164 read-write 0x00000000 0x20 EVENTS_WRITE Write command received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_READ Read command received 0x168 read-write 0x00000000 0x20 EVENTS_READ Read command received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 WRITE_SUSPEND Shortcut between event WRITE and task SUSPEND 13 13 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 READ_SUSPEND Shortcut between event READ and task SUSPEND 14 14 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0x0 Enabled Enable 0x1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0x0 Enabled Enable 0x1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0x0 Enabled Enable 0x1 WRITE Enable or disable interrupt for event WRITE 25 25 Disabled Disable 0x0 Enabled Enable 0x1 READ Enable or disable interrupt for event READ 26 26 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 WRITE Write '1' to enable interrupt for event WRITE 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 READ Write '1' to enable interrupt for event READ 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 WRITE Write '1' to disable interrupt for event WRITE 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 READ Write '1' to disable interrupt for event READ 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSRC Error source 0x4D0 read-write 0x00000000 oneToClear 0x20 OVERFLOW RX buffer overflow detected, and prevented 0 0 NotDetected Error did not occur 0x0 Detected Error occurred 0x1 DNACK NACK sent after receiving a data byte 2 2 NotReceived Error did not occur 0x0 Received Error occurred 0x1 OVERREAD TX buffer over-read detected, and prevented 3 3 NotDetected Error did not occur 0x0 Detected Error occurred 0x1 MATCH Status register indicating which address had a match 0x4D4 read-only 0x00000000 0x20 MATCH Indication of which address in ADDRESS that matched the incoming address 0 0 ENABLE Enable TWIS 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable TWIS 0 3 Disabled Disable TWIS 0x0 Enabled Enable TWIS 0x9 PSEL Unspecified TWIS_PSEL read-write 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD RXD EasyDMA channel TWIS_RXD read-write 0x534 PTR RXD Data pointer 0x000 read-write 0x00000000 0x20 PTR RXD Data pointer 0 31 MAXCNT Maximum number of bytes in RXD buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in RXD buffer 0 15 AMOUNT Number of bytes transferred in the last RXD transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last RXD transaction 0 15 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 TXD TXD EasyDMA channel TWIS_TXD read-write 0x544 PTR TXD Data pointer 0x000 read-write 0x00000000 0x20 PTR TXD Data pointer 0 31 MAXCNT Maximum number of bytes in TXD buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in TXD buffer 0 15 AMOUNT Number of bytes transferred in the last TXD transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last TXD transaction 0 15 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 0x2 0x4 ADDRESS[%s] Description collection: TWI slave address n 0x588 read-write 0x00000000 0x20 ADDRESS TWI slave address 0 6 CONFIG Configuration register for the address match mechanism 0x594 read-write 0x00000001 0x20 ADDRESS0 Enable or disable address matching on ADDRESS[0] 0 0 Disabled Disabled 0x0 Enabled Enabled 0x1 ADDRESS1 Enable or disable address matching on ADDRESS[1] 1 1 Disabled Disabled 0x0 Enabled Enabled 0x1 ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0x5C0 read-write 0x00000000 0x20 ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0 7 SPI1 Serial Peripheral Interface 1 0x40004000 SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 4 SPIM1 Serial Peripheral Interface Master with EasyDMA 1 0x40004000 SPI1 SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 4 SPIS1 SPI Slave 1 0x40004000 SPI1 SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 4 TWI1 I2C compatible Two-Wire Interface 1 0x40004000 SPI1 SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 4 TWIM1 I2C compatible Two-Wire Master Interface with EasyDMA 1 0x40004000 SPI1 SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 4 TWIS1 I2C compatible Two-Wire Slave Interface with EasyDMA 1 0x40004000 SPI1 SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 4 NFCT NFC-A compatible radio 0x40005000 0 0x1000 registers NFCT 5 NFCT 0x20 TASKS_ACTIVATE Activate NFCT peripheral for incoming and outgoing frames, change state to activated 0x000 write-only 0x00000000 0x20 TASKS_ACTIVATE Activate NFCT peripheral for incoming and outgoing frames, change state to activated 0 0 Trigger Trigger task 0x1 TASKS_DISABLE Disable NFCT peripheral 0x004 write-only 0x00000000 0x20 TASKS_DISABLE Disable NFCT peripheral 0 0 Trigger Trigger task 0x1 TASKS_SENSE Enable NFC sense field mode, change state to sense mode 0x008 write-only 0x00000000 0x20 TASKS_SENSE Enable NFC sense field mode, change state to sense mode 0 0 Trigger Trigger task 0x1 TASKS_STARTTX Start transmission of an outgoing frame, change state to transmit 0x00C write-only 0x00000000 0x20 TASKS_STARTTX Start transmission of an outgoing frame, change state to transmit 0 0 Trigger Trigger task 0x1 TASKS_ENABLERXDATA Initializes the EasyDMA for receive. 0x01C write-only 0x00000000 0x20 TASKS_ENABLERXDATA Initializes the EasyDMA for receive. 0 0 Trigger Trigger task 0x1 TASKS_GOIDLE Force state machine to IDLE state 0x024 write-only 0x00000000 0x20 TASKS_GOIDLE Force state machine to IDLE state 0 0 Trigger Trigger task 0x1 TASKS_GOSLEEP Force state machine to SLEEP_A state 0x028 write-only 0x00000000 0x20 TASKS_GOSLEEP Force state machine to SLEEP_A state 0 0 Trigger Trigger task 0x1 EVENTS_READY The NFCT peripheral is ready to receive and send frames 0x100 read-write 0x00000000 0x20 EVENTS_READY The NFCT peripheral is ready to receive and send frames 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_FIELDDETECTED Remote NFC field detected 0x104 read-write 0x00000000 0x20 EVENTS_FIELDDETECTED Remote NFC field detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_FIELDLOST Remote NFC field lost 0x108 read-write 0x00000000 0x20 EVENTS_FIELDLOST Remote NFC field lost 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXFRAMESTART Marks the start of the first symbol of a transmitted frame 0x10C read-write 0x00000000 0x20 EVENTS_TXFRAMESTART Marks the start of the first symbol of a transmitted frame 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXFRAMEEND Marks the end of the last transmitted on-air symbol of a frame 0x110 read-write 0x00000000 0x20 EVENTS_TXFRAMEEND Marks the end of the last transmitted on-air symbol of a frame 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXFRAMESTART Marks the end of the first symbol of a received frame 0x114 read-write 0x00000000 0x20 EVENTS_RXFRAMESTART Marks the end of the first symbol of a received frame 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXFRAMEEND Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer 0x118 read-write 0x00000000 0x20 EVENTS_RXFRAMEEND Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR NFC error reported. The ERRORSTATUS register contains details on the source of the error. 0x11C read-write 0x00000000 0x20 EVENTS_ERROR NFC error reported. The ERRORSTATUS register contains details on the source of the error. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXERROR NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. 0x128 read-write 0x00000000 0x20 EVENTS_RXERROR NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDRX RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. 0x12C read-write 0x00000000 0x20 EVENTS_ENDRX RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDTX Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer 0x130 read-write 0x00000000 0x20 EVENTS_ENDTX Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_AUTOCOLRESSTARTED Auto collision resolution process has started 0x138 read-write 0x00000000 0x20 EVENTS_AUTOCOLRESSTARTED Auto collision resolution process has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_COLLISION NFC auto collision resolution error reported. 0x148 read-write 0x00000000 0x20 EVENTS_COLLISION NFC auto collision resolution error reported. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SELECTED NFC auto collision resolution successfully completed 0x14C read-write 0x00000000 0x20 EVENTS_SELECTED NFC auto collision resolution successfully completed 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STARTED EasyDMA is ready to receive or send frames. 0x150 read-write 0x00000000 0x20 EVENTS_STARTED EasyDMA is ready to receive or send frames. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 FIELDDETECTED_ACTIVATE Shortcut between event FIELDDETECTED and task ACTIVATE 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 FIELDLOST_SENSE Shortcut between event FIELDLOST and task SENSE 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 TXFRAMEEND_ENABLERXDATA Shortcut between event TXFRAMEEND and task ENABLERXDATA 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 READY Enable or disable interrupt for event READY 0 0 Disabled Disable 0x0 Enabled Enable 0x1 FIELDDETECTED Enable or disable interrupt for event FIELDDETECTED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 FIELDLOST Enable or disable interrupt for event FIELDLOST 2 2 Disabled Disable 0x0 Enabled Enable 0x1 TXFRAMESTART Enable or disable interrupt for event TXFRAMESTART 3 3 Disabled Disable 0x0 Enabled Enable 0x1 TXFRAMEEND Enable or disable interrupt for event TXFRAMEEND 4 4 Disabled Disable 0x0 Enabled Enable 0x1 RXFRAMESTART Enable or disable interrupt for event RXFRAMESTART 5 5 Disabled Disable 0x0 Enabled Enable 0x1 RXFRAMEEND Enable or disable interrupt for event RXFRAMEEND 6 6 Disabled Disable 0x0 Enabled Enable 0x1 ERROR Enable or disable interrupt for event ERROR 7 7 Disabled Disable 0x0 Enabled Enable 0x1 RXERROR Enable or disable interrupt for event RXERROR 10 10 Disabled Disable 0x0 Enabled Enable 0x1 ENDRX Enable or disable interrupt for event ENDRX 11 11 Disabled Disable 0x0 Enabled Enable 0x1 ENDTX Enable or disable interrupt for event ENDTX 12 12 Disabled Disable 0x0 Enabled Enable 0x1 AUTOCOLRESSTARTED Enable or disable interrupt for event AUTOCOLRESSTARTED 14 14 Disabled Disable 0x0 Enabled Enable 0x1 COLLISION Enable or disable interrupt for event COLLISION 18 18 Disabled Disable 0x0 Enabled Enable 0x1 SELECTED Enable or disable interrupt for event SELECTED 19 19 Disabled Disable 0x0 Enabled Enable 0x1 STARTED Enable or disable interrupt for event STARTED 20 20 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 FIELDDETECTED Write '1' to enable interrupt for event FIELDDETECTED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 FIELDLOST Write '1' to enable interrupt for event FIELDLOST 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXFRAMESTART Write '1' to enable interrupt for event TXFRAMESTART 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXFRAMEEND Write '1' to enable interrupt for event TXFRAMEEND 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXFRAMESTART Write '1' to enable interrupt for event RXFRAMESTART 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXFRAMEEND Write '1' to enable interrupt for event RXFRAMEEND 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXERROR Write '1' to enable interrupt for event RXERROR 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDRX Write '1' to enable interrupt for event ENDRX 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDTX Write '1' to enable interrupt for event ENDTX 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 AUTOCOLRESSTARTED Write '1' to enable interrupt for event AUTOCOLRESSTARTED 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COLLISION Write '1' to enable interrupt for event COLLISION 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SELECTED Write '1' to enable interrupt for event SELECTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STARTED Write '1' to enable interrupt for event STARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 FIELDDETECTED Write '1' to disable interrupt for event FIELDDETECTED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 FIELDLOST Write '1' to disable interrupt for event FIELDLOST 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXFRAMESTART Write '1' to disable interrupt for event TXFRAMESTART 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXFRAMEEND Write '1' to disable interrupt for event TXFRAMEEND 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXFRAMESTART Write '1' to disable interrupt for event RXFRAMESTART 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXFRAMEEND Write '1' to disable interrupt for event RXFRAMEEND 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXERROR Write '1' to disable interrupt for event RXERROR 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDRX Write '1' to disable interrupt for event ENDRX 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDTX Write '1' to disable interrupt for event ENDTX 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 AUTOCOLRESSTARTED Write '1' to disable interrupt for event AUTOCOLRESSTARTED 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COLLISION Write '1' to disable interrupt for event COLLISION 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SELECTED Write '1' to disable interrupt for event SELECTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STARTED Write '1' to disable interrupt for event STARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSTATUS NFC Error Status register 0x404 read-write 0x00000000 oneToClear 0x20 FRAMEDELAYTIMEOUT No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX 0 0 FRAMESTATUS Unspecified NFCT_FRAMESTATUS read-write 0x40C RX Result of last incoming frame 0x000 read-write 0x00000000 oneToClear 0x20 CRCERROR No valid end of frame (EoF) detected 0 0 CRCCorrect Valid CRC detected 0x0 CRCError CRC received does not match local check 0x1 PARITYSTATUS Parity status of received frame 2 2 ParityOK Frame received with parity OK 0x0 ParityError Frame received with parity error 0x1 OVERRUN Overrun detected 3 3 NoOverrun No overrun detected 0x0 Overrun Overrun error 0x1 NFCTAGSTATE NfcTag state register 0x410 read-only 0x00000000 0x20 NFCTAGSTATE NfcTag state 0 2 Disabled Disabled or sense 0x0 RampUp RampUp 0x2 Idle Idle 0x3 Receive Receive 0x4 FrameDelay FrameDelay 0x5 Transmit Transmit 0x6 SLEEPSTATE Sleep state during automatic collision resolution 0x420 read-only 0x00000000 0x20 SLEEPSTATE Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. 0 0 Idle State is IDLE. 0x0 SleepA State is SLEEP_A. 0x1 FIELDPRESENT Indicates the presence or not of a valid field 0x43C read-only 0x00000000 0x20 FIELDPRESENT Indicates if a valid field is present. Available only in the activated state. 0 0 NoField No valid field detected 0x0 FieldPresent Valid field detected 0x1 LOCKDETECT Indicates if the low level has locked to the field 1 1 NotLocked Not locked to field 0x0 Locked Locked to field 0x1 FRAMEDELAYMIN Minimum frame delay 0x504 read-write 0x00000480 0x20 FRAMEDELAYMIN Minimum frame delay in number of 13.56 MHz clocks 0 15 FRAMEDELAYMAX Maximum frame delay 0x508 read-write 0x00001000 0x20 FRAMEDELAYMAX Maximum frame delay in number of 13.56 MHz clocks 0 19 FRAMEDELAYMODE Configuration register for the Frame Delay Timer 0x50C read-write 0x00000001 0x20 FRAMEDELAYMODE Configuration register for the Frame Delay Timer 0 1 FreeRun Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. 0x0 Window Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX 0x1 ExactVal Frame is transmitted exactly at FRAMEDELAYMAX 0x2 WindowGrid Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX 0x3 PACKETPTR Packet pointer for TXD and RXD data storage in Data RAM 0x510 read-write 0x00000000 0x20 PTR Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. 0 31 MAXLEN Size of the RAM buffer allocated to TXD and RXD data storage each 0x514 read-write 0x00000000 0x20 MAXLEN Size of the RAM buffer allocated to TXD and RXD data storage each 0 8 TXD Unspecified NFCT_TXD read-write 0x518 FRAMECONFIG Configuration of outgoing frames 0x000 read-write 0x00000017 0x20 PARITY Indicates if parity is added to the frame 0 0 NoParity Parity is not added to TX frames 0x0 Parity Parity is added to TX frames 0x1 DISCARDMODE Discarding unused bits at start or end of a frame 1 1 DiscardEnd Unused bits are discarded at end of frame (EoF) 0x0 DiscardStart Unused bits are discarded at start of frame (SoF) 0x1 SOF Adding SoF or not in TX frames 2 2 NoSoF SoF symbol not added 0x0 SoF SoF symbol added 0x1 CRCMODETX CRC mode for outgoing frames 4 4 NoCRCTX CRC is not added to the frame 0x0 CRC16TX 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame 0x1 AMOUNT Size of outgoing frame 0x004 read-write 0x00000000 0x20 TXDATABITS Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). 0 2 TXDATABYTES Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing 3 11 RXD Unspecified NFCT_RXD read-write 0x520 FRAMECONFIG Configuration of incoming frames 0x000 read-write 0x00000015 0x20 PARITY Indicates if parity expected in RX frame 0 0 NoParity Parity is not expected in RX frames 0x0 Parity Parity is expected in RX frames 0x1 SOF SoF expected or not in RX frames 2 2 NoSoF SoF symbol is not expected in RX frames 0x0 SoF SoF symbol is expected in RX frames 0x1 CRCMODERX CRC mode for incoming frames 4 4 NoCRCRX CRC is not expected in RX frames 0x0 CRC16RX Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated 0x1 AMOUNT Size of last incoming frame 0x004 read-only 0x00000000 0x20 RXDATABITS Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). 0 2 RXDATABYTES Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) 3 11 NFCID1_LAST Last NFCID1 part (4, 7 or 10 bytes ID) 0x590 read-write 0x00006363 0x20 NFCID1_Z NFCID1 byte Z (very last byte sent) 0 7 NFCID1_Y NFCID1 byte Y 8 15 NFCID1_X NFCID1 byte X 16 23 NFCID1_W NFCID1 byte W 24 31 NFCID1_2ND_LAST Second last NFCID1 part (7 or 10 bytes ID) 0x594 read-write 0x00000000 0x20 NFCID1_V NFCID1 byte V 0 7 NFCID1_U NFCID1 byte U 8 15 NFCID1_T NFCID1 byte T 16 23 NFCID1_3RD_LAST Third last NFCID1 part (10 bytes ID) 0x598 read-write 0x00000000 0x20 NFCID1_S NFCID1 byte S 0 7 NFCID1_R NFCID1 byte R 8 15 NFCID1_Q NFCID1 byte Q 16 23 AUTOCOLRESCONFIG Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. 0x59C read-write 0x00000002 0x20 MODE Enables/disables auto collision resolution 0 0 Enabled Auto collision resolution enabled 0x0 Disabled Auto collision resolution disabled 0x1 SENSRES NFC-A SENS_RES auto-response settings 0x5A0 read-write 0x00000001 0x20 BITFRAMESDD Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 0 4 SDD00000 SDD pattern 00000 0x00 SDD00001 SDD pattern 00001 0x01 SDD00010 SDD pattern 00010 0x02 SDD00100 SDD pattern 00100 0x04 SDD01000 SDD pattern 01000 0x08 SDD10000 SDD pattern 10000 0x10 RFU5 Reserved for future use. Shall be 0. 5 5 NFCIDSIZE NFCID1 size. This value is used by the auto collision resolution engine. 6 7 NFCID1Single NFCID1 size: single (4 bytes) 0x0 NFCID1Double NFCID1 size: double (7 bytes) 0x1 NFCID1Triple NFCID1 size: triple (10 bytes) 0x2 PLATFCONFIG Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 8 11 RFU74 Reserved for future use. Shall be 0. 12 15 SELRES NFC-A SEL_RES auto-response settings 0x5A4 read-write 0x00000000 0x20 RFU10 Reserved for future use. Shall be 0. 0 1 CASCADE Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) 2 2 RFU43 Reserved for future use. Shall be 0. 3 4 PROTOCOL Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 5 6 RFU7 Reserved for future use. Shall be 0. 7 7 GPIOTE GPIO Tasks and Events 0x40006000 0 0x1000 registers GPIOTE 6 GPIOTE 0x20 0x8 0x4 TASKS_OUT[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0x000 write-only 0x00000000 0x20 TASKS_OUT Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0 0 Trigger Trigger task 0x1 0x8 0x4 TASKS_SET[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0x030 write-only 0x00000000 0x20 TASKS_SET Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0 0 Trigger Trigger task 0x1 0x8 0x4 TASKS_CLR[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0x060 write-only 0x00000000 0x20 TASKS_CLR Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0 0 Trigger Trigger task 0x1 0x8 0x4 EVENTS_IN[%s] Description collection: Event generated from pin specified in CONFIG[n].PSEL 0x100 read-write 0x00000000 0x20 EVENTS_IN Event generated from pin specified in CONFIG[n].PSEL 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_PORT Event generated from multiple input GPIO pins with SENSE mechanism enabled 0x17C read-write 0x00000000 0x20 EVENTS_PORT Event generated from multiple input GPIO pins with SENSE mechanism enabled 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 IN0 Write '1' to enable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN1 Write '1' to enable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN2 Write '1' to enable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN3 Write '1' to enable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN4 Write '1' to enable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN5 Write '1' to enable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN6 Write '1' to enable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN7 Write '1' to enable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT Write '1' to enable interrupt for event PORT 31 31 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 IN0 Write '1' to disable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN1 Write '1' to disable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN2 Write '1' to disable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN3 Write '1' to disable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN4 Write '1' to disable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN5 Write '1' to disable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN6 Write '1' to disable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN7 Write '1' to disable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT Write '1' to disable interrupt for event PORT 31 31 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 0x8 0x4 CONFIG[%s] Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event 0x510 read-write 0x00000000 0x20 MODE Mode 0 1 Disabled Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. 0x0 Event Event mode 0x1 Task Task mode 0x3 PSEL GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event 8 12 PORT Port number 13 13 POLARITY When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. 16 17 None Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. 0x0 LoToHi Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. 0x1 HiToLo Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. 0x2 Toggle Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. 0x3 OUTINIT When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. 20 20 Low Task mode: Initial value of pin before task triggering is low 0x0 High Task mode: Initial value of pin before task triggering is high 0x1 SAADC Successive approximation register (SAR) analog-to-digital converter 0x40007000 0 0x1000 registers SAADC 7 SAADC 0x20 TASKS_START Starts the SAADC and prepares the result buffer in RAM 0x000 write-only 0x00000000 0x20 TASKS_START Starts the SAADC and prepares the result buffer in RAM 0 0 Trigger Trigger task 0x1 TASKS_SAMPLE Takes one SAADC sample 0x004 write-only 0x00000000 0x20 TASKS_SAMPLE Takes one SAADC sample 0 0 Trigger Trigger task 0x1 TASKS_STOP Stops the SAADC and terminates all on-going conversions 0x008 write-only 0x00000000 0x20 TASKS_STOP Stops the SAADC and terminates all on-going conversions 0 0 Trigger Trigger task 0x1 TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0x00C write-only 0x00000000 0x20 TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0 0 Trigger Trigger task 0x1 EVENTS_STARTED The SAADC has started 0x100 read-write 0x00000000 0x20 EVENTS_STARTED The SAADC has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_END The SAADC has filled up the result buffer 0x104 read-write 0x00000000 0x20 EVENTS_END The SAADC has filled up the result buffer 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DONE A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 0x108 read-write 0x00000000 0x20 EVENTS_DONE A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RESULTDONE Result ready for transfer to RAM 0x10C read-write 0x00000000 0x20 EVENTS_RESULTDONE Result ready for transfer to RAM 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CALIBRATEDONE Calibration is complete 0x110 read-write 0x00000000 0x20 EVENTS_CALIBRATEDONE Calibration is complete 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED The SAADC has stopped 0x114 read-write 0x00000000 0x20 EVENTS_STOPPED The SAADC has stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 8 0x008 EVENTS_CH[%s] Peripheral events. SAADC_EVENTS_CH read-write 0x118 LIMITH Description cluster: Last result is equal or above CH[n].LIMIT.HIGH 0x000 read-write 0x00000000 0x20 LIMITH Last result is equal or above CH[n].LIMIT.HIGH 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 LIMITL Description cluster: Last result is equal or below CH[n].LIMIT.LOW 0x004 read-write 0x00000000 0x20 LIMITL Last result is equal or below CH[n].LIMIT.LOW 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STARTED Enable or disable interrupt for event STARTED 0 0 Disabled Disable 0x0 Enabled Enable 0x1 END Enable or disable interrupt for event END 1 1 Disabled Disable 0x0 Enabled Enable 0x1 DONE Enable or disable interrupt for event DONE 2 2 Disabled Disable 0x0 Enabled Enable 0x1 RESULTDONE Enable or disable interrupt for event RESULTDONE 3 3 Disabled Disable 0x0 Enabled Enable 0x1 CALIBRATEDONE Enable or disable interrupt for event CALIBRATEDONE 4 4 Disabled Disable 0x0 Enabled Enable 0x1 STOPPED Enable or disable interrupt for event STOPPED 5 5 Disabled Disable 0x0 Enabled Enable 0x1 CH0LIMITH Enable or disable interrupt for event CH0LIMITH 6 6 Disabled Disable 0x0 Enabled Enable 0x1 CH0LIMITL Enable or disable interrupt for event CH0LIMITL 7 7 Disabled Disable 0x0 Enabled Enable 0x1 CH1LIMITH Enable or disable interrupt for event CH1LIMITH 8 8 Disabled Disable 0x0 Enabled Enable 0x1 CH1LIMITL Enable or disable interrupt for event CH1LIMITL 9 9 Disabled Disable 0x0 Enabled Enable 0x1 CH2LIMITH Enable or disable interrupt for event CH2LIMITH 10 10 Disabled Disable 0x0 Enabled Enable 0x1 CH2LIMITL Enable or disable interrupt for event CH2LIMITL 11 11 Disabled Disable 0x0 Enabled Enable 0x1 CH3LIMITH Enable or disable interrupt for event CH3LIMITH 12 12 Disabled Disable 0x0 Enabled Enable 0x1 CH3LIMITL Enable or disable interrupt for event CH3LIMITL 13 13 Disabled Disable 0x0 Enabled Enable 0x1 CH4LIMITH Enable or disable interrupt for event CH4LIMITH 14 14 Disabled Disable 0x0 Enabled Enable 0x1 CH4LIMITL Enable or disable interrupt for event CH4LIMITL 15 15 Disabled Disable 0x0 Enabled Enable 0x1 CH5LIMITH Enable or disable interrupt for event CH5LIMITH 16 16 Disabled Disable 0x0 Enabled Enable 0x1 CH5LIMITL Enable or disable interrupt for event CH5LIMITL 17 17 Disabled Disable 0x0 Enabled Enable 0x1 CH6LIMITH Enable or disable interrupt for event CH6LIMITH 18 18 Disabled Disable 0x0 Enabled Enable 0x1 CH6LIMITL Enable or disable interrupt for event CH6LIMITL 19 19 Disabled Disable 0x0 Enabled Enable 0x1 CH7LIMITH Enable or disable interrupt for event CH7LIMITH 20 20 Disabled Disable 0x0 Enabled Enable 0x1 CH7LIMITL Enable or disable interrupt for event CH7LIMITL 21 21 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STARTED Write '1' to enable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 END Write '1' to enable interrupt for event END 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DONE Write '1' to enable interrupt for event DONE 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RESULTDONE Write '1' to enable interrupt for event RESULTDONE 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CALIBRATEDONE Write '1' to enable interrupt for event CALIBRATEDONE 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH0LIMITH Write '1' to enable interrupt for event CH0LIMITH 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH0LIMITL Write '1' to enable interrupt for event CH0LIMITL 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH1LIMITH Write '1' to enable interrupt for event CH1LIMITH 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH1LIMITL Write '1' to enable interrupt for event CH1LIMITL 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH2LIMITH Write '1' to enable interrupt for event CH2LIMITH 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH2LIMITL Write '1' to enable interrupt for event CH2LIMITL 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH3LIMITH Write '1' to enable interrupt for event CH3LIMITH 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH3LIMITL Write '1' to enable interrupt for event CH3LIMITL 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH4LIMITH Write '1' to enable interrupt for event CH4LIMITH 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH4LIMITL Write '1' to enable interrupt for event CH4LIMITL 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH5LIMITH Write '1' to enable interrupt for event CH5LIMITH 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH5LIMITL Write '1' to enable interrupt for event CH5LIMITL 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH6LIMITH Write '1' to enable interrupt for event CH6LIMITH 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH6LIMITL Write '1' to enable interrupt for event CH6LIMITL 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH7LIMITH Write '1' to enable interrupt for event CH7LIMITH 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH7LIMITL Write '1' to enable interrupt for event CH7LIMITL 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STARTED Write '1' to disable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 END Write '1' to disable interrupt for event END 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DONE Write '1' to disable interrupt for event DONE 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RESULTDONE Write '1' to disable interrupt for event RESULTDONE 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CALIBRATEDONE Write '1' to disable interrupt for event CALIBRATEDONE 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH0LIMITH Write '1' to disable interrupt for event CH0LIMITH 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH0LIMITL Write '1' to disable interrupt for event CH0LIMITL 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH1LIMITH Write '1' to disable interrupt for event CH1LIMITH 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH1LIMITL Write '1' to disable interrupt for event CH1LIMITL 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH2LIMITH Write '1' to disable interrupt for event CH2LIMITH 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH2LIMITL Write '1' to disable interrupt for event CH2LIMITL 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH3LIMITH Write '1' to disable interrupt for event CH3LIMITH 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH3LIMITL Write '1' to disable interrupt for event CH3LIMITL 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH4LIMITH Write '1' to disable interrupt for event CH4LIMITH 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH4LIMITL Write '1' to disable interrupt for event CH4LIMITL 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH5LIMITH Write '1' to disable interrupt for event CH5LIMITH 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH5LIMITL Write '1' to disable interrupt for event CH5LIMITL 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH6LIMITH Write '1' to disable interrupt for event CH6LIMITH 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH6LIMITL Write '1' to disable interrupt for event CH6LIMITL 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH7LIMITH Write '1' to disable interrupt for event CH7LIMITH 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH7LIMITL Write '1' to disable interrupt for event CH7LIMITL 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STATUS Status 0x400 read-only 0x00000000 0x20 STATUS Status 0 0 Ready SAADC is ready. No on-going conversions. 0x0 Busy SAADC is busy. Conversion in progress. 0x1 ENABLE Enable or disable SAADC 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable SAADC 0 0 Disabled Disable SAADC 0x0 Enabled Enable SAADC 0x1 8 0x010 CH[%s] Unspecified SAADC_CH read-write 0x510 PSELP Description cluster: Input positive pin selection for CH[n] 0x000 read-write 0x00000000 0x20 PSELP Analog positive input channel 0 4 NC Not connected 0x00 AnalogInput0 AIN0 0x01 AnalogInput1 AIN1 0x02 AnalogInput2 AIN2 0x03 AnalogInput3 AIN3 0x04 AnalogInput4 AIN4 0x05 AnalogInput5 AIN5 0x06 AnalogInput6 AIN6 0x07 AnalogInput7 AIN7 0x08 VDD VDD 0x09 VDDHDIV5 VDDH/5 0x0D PSELN Description cluster: Input negative pin selection for CH[n] 0x004 read-write 0x00000000 0x20 PSELN Analog negative input, enables differential channel 0 4 NC Not connected 0x00 AnalogInput0 AIN0 0x01 AnalogInput1 AIN1 0x02 AnalogInput2 AIN2 0x03 AnalogInput3 AIN3 0x04 AnalogInput4 AIN4 0x05 AnalogInput5 AIN5 0x06 AnalogInput6 AIN6 0x07 AnalogInput7 AIN7 0x08 VDD VDD 0x09 VDDHDIV5 VDDH/5 0x0D CONFIG Description cluster: Input configuration for CH[n] 0x008 read-write 0x00020000 0x20 RESP Positive channel resistor control 0 1 Bypass Bypass resistor ladder 0x0 Pulldown Pull-down to GND 0x1 Pullup Pull-up to VDD 0x2 VDD1_2 Set input at VDD/2 0x3 RESN Negative channel resistor control 4 5 Bypass Bypass resistor ladder 0x0 Pulldown Pull-down to GND 0x1 Pullup Pull-up to VDD 0x2 VDD1_2 Set input at VDD/2 0x3 GAIN Gain control 8 10 Gain1_6 1/6 0x0 Gain1_5 1/5 0x1 Gain1_4 1/4 0x2 Gain1_3 1/3 0x3 Gain1_2 1/2 0x4 Gain1 1 0x5 Gain2 2 0x6 Gain4 4 0x7 REFSEL Reference control 12 12 Internal Internal reference (0.6 V) 0x0 VDD1_4 VDD/4 as reference 0x1 TACQ Acquisition time, the time the SAADC uses to sample the input voltage 16 18 3us 3 us 0x0 5us 5 us 0x1 10us 10 us 0x2 15us 15 us 0x3 20us 20 us 0x4 40us 40 us 0x5 MODE Enable differential mode 20 20 SE Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND 0x0 Diff Differential 0x1 BURST Enable burst mode 24 24 Disabled Burst mode is disabled (normal operation) 0x0 Enabled Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. 0x1 LIMIT Description cluster: High/low limits for event monitoring of a channel 0x00C read-write 0x7FFF8000 0x20 LOW Low level limit 0 15 HIGH High level limit 16 31 RESOLUTION Resolution configuration 0x5F0 read-write 0x00000001 0x20 VAL Set the resolution 0 2 8bit 8 bits 0x0 10bit 10 bits 0x1 12bit 12 bits 0x2 14bit 14 bits 0x3 OVERSAMPLE Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 0x5F4 read-write 0x00000000 0x20 OVERSAMPLE Oversample control 0 3 Bypass Bypass oversampling 0x0 Over2x Oversample 2x 0x1 Over4x Oversample 4x 0x2 Over8x Oversample 8x 0x3 Over16x Oversample 16x 0x4 Over32x Oversample 32x 0x5 Over64x Oversample 64x 0x6 Over128x Oversample 128x 0x7 Over256x Oversample 256x 0x8 SAMPLERATE Controls normal or continuous sample rate 0x5F8 read-write 0x00000000 0x20 CC Capture and compare value. Sample rate is 16 MHz/CC 0 10 MODE Select mode for sample rate control 12 12 Task Rate is controlled from SAMPLE task 0x0 Timers Rate is controlled from local timer (use CC to control the rate) 0x1 RESULT RESULT EasyDMA channel SAADC_RESULT read-write 0x62C PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of 16-bit samples to be written to output RAM buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of 16-bit samples to be written to output RAM buffer 0 14 AMOUNT Number of 16-bit samples written to output RAM buffer since the previous START task 0x008 read-only 0x00000000 0x20 AMOUNT Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. 0 14 TIMER0 Timer/Counter 0 0x40008000 TIMER 0 0x1000 registers TIMER0 8 TIMER 0x20 TASKS_START Start Timer 0x000 write-only 0x00000000 0x20 TASKS_START Start Timer 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop Timer 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop Timer 0 0 Trigger Trigger task 0x1 TASKS_COUNT Increment Timer (Counter mode only) 0x008 write-only 0x00000000 0x20 TASKS_COUNT Increment Timer (Counter mode only) 0 0 Trigger Trigger task 0x1 TASKS_CLEAR Clear time 0x00C write-only 0x00000000 0x20 TASKS_CLEAR Clear time 0 0 Trigger Trigger task 0x1 TASKS_SHUTDOWN Deprecated register - Shut down timer 0x010 write-only 0x00000000 0x20 TASKS_SHUTDOWN Deprecated field - Shut down timer 0 0 Trigger Trigger task 0x1 0x6 0x4 TASKS_CAPTURE[%s] Description collection: Capture Timer value to CC[n] register 0x040 write-only 0x00000000 0x20 TASKS_CAPTURE Capture Timer value to CC[n] register 0 0 Trigger Trigger task 0x1 0x6 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x140 read-write 0x00000000 0x20 EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 COMPARE0_CLEAR Shortcut between event COMPARE[0] and task CLEAR 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE1_CLEAR Shortcut between event COMPARE[1] and task CLEAR 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE2_CLEAR Shortcut between event COMPARE[2] and task CLEAR 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE3_CLEAR Shortcut between event COMPARE[3] and task CLEAR 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE4_CLEAR Shortcut between event COMPARE[4] and task CLEAR 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE5_CLEAR Shortcut between event COMPARE[5] and task CLEAR 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE0_STOP Shortcut between event COMPARE[0] and task STOP 8 8 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE1_STOP Shortcut between event COMPARE[1] and task STOP 9 9 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE2_STOP Shortcut between event COMPARE[2] and task STOP 10 10 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE3_STOP Shortcut between event COMPARE[3] and task STOP 11 11 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE4_STOP Shortcut between event COMPARE[4] and task STOP 12 12 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE5_STOP Shortcut between event COMPARE[5] and task STOP 13 13 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE4 Write '1' to enable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE5 Write '1' to enable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE4 Write '1' to disable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE5 Write '1' to disable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 MODE Timer mode selection 0x504 read-write 0x00000000 0x20 MODE Timer mode 0 1 Timer Select Timer mode 0x0 Counter Deprecated enumerator - Select Counter mode 0x1 LowPowerCounter Select Low Power Counter mode 0x2 BITMODE Configure the number of bits used by the TIMER 0x508 read-write 0x00000000 0x20 BITMODE Timer bit width 0 1 16Bit 16 bit timer bit width 0x0 08Bit 8 bit timer bit width 0x1 24Bit 24 bit timer bit width 0x2 32Bit 32 bit timer bit width 0x3 PRESCALER Timer prescaler register 0x510 read-write 0x00000004 0x20 PRESCALER Prescaler value 0 3 0x6 0x4 CC[%s] Description collection: Capture/Compare register n 0x540 read-write 0x00000000 0x20 CC Capture/Compare value 0 31 TIMER1 Timer/Counter 1 0x40009000 TIMER1 9 TIMER2 Timer/Counter 2 0x4000A000 TIMER2 10 RTC0 Real time counter 0 0x4000B000 RTC 0 0x1000 registers RTC0 11 RTC 0x20 TASKS_START Start RTC COUNTER 0x000 write-only 0x00000000 0x20 TASKS_START Start RTC COUNTER 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop RTC COUNTER 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop RTC COUNTER 0 0 Trigger Trigger task 0x1 TASKS_CLEAR Clear RTC COUNTER 0x008 write-only 0x00000000 0x20 TASKS_CLEAR Clear RTC COUNTER 0 0 Trigger Trigger task 0x1 TASKS_TRIGOVRFLW Set COUNTER to 0xFFFFF0 0x00C write-only 0x00000000 0x20 TASKS_TRIGOVRFLW Set COUNTER to 0xFFFFF0 0 0 Trigger Trigger task 0x1 EVENTS_TICK Event on COUNTER increment 0x100 read-write 0x00000000 0x20 EVENTS_TICK Event on COUNTER increment 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_OVRFLW Event on COUNTER overflow 0x104 read-write 0x00000000 0x20 EVENTS_OVRFLW Event on COUNTER overflow 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x4 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x140 read-write 0x00000000 0x20 EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 TICK Write '1' to enable interrupt for event TICK 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 OVRFLW Write '1' to enable interrupt for event OVRFLW 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 TICK Write '1' to disable interrupt for event TICK 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 OVRFLW Write '1' to disable interrupt for event OVRFLW 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 EVTEN Enable or disable event routing 0x340 read-write 0x00000000 0x20 TICK Enable or disable event routing for event TICK 0 0 Disabled Disable 0x0 Enabled Enable 0x1 OVRFLW Enable or disable event routing for event OVRFLW 1 1 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE0 Enable or disable event routing for event COMPARE[0] 16 16 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE1 Enable or disable event routing for event COMPARE[1] 17 17 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE2 Enable or disable event routing for event COMPARE[2] 18 18 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE3 Enable or disable event routing for event COMPARE[3] 19 19 Disabled Disable 0x0 Enabled Enable 0x1 EVTENSET Enable event routing 0x344 read-write 0x00000000 0x20 TICK Write '1' to enable event routing for event TICK 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 OVRFLW Write '1' to enable event routing for event OVRFLW 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE0 Write '1' to enable event routing for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE1 Write '1' to enable event routing for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE2 Write '1' to enable event routing for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE3 Write '1' to enable event routing for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 EVTENCLR Disable event routing 0x348 read-write 0x00000000 0x20 TICK Write '1' to disable event routing for event TICK 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 OVRFLW Write '1' to disable event routing for event OVRFLW 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE0 Write '1' to disable event routing for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE1 Write '1' to disable event routing for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE2 Write '1' to disable event routing for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE3 Write '1' to disable event routing for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COUNTER Current COUNTER value 0x504 read-only 0x00000000 0x20 COUNTER Counter value 0 23 PRESCALER 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. 0x508 read-write 0x00000000 0x20 PRESCALER Prescaler value 0 11 0x4 0x4 CC[%s] Description collection: Compare register n 0x540 read-write 0x00000000 0x20 COMPARE Compare value 0 23 TEMP Temperature Sensor 0x4000C000 0 0x1000 registers TEMP 12 TEMP 0x20 TASKS_START Start temperature measurement 0x000 write-only 0x00000000 0x20 TASKS_START Start temperature measurement 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop temperature measurement 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop temperature measurement 0 0 Trigger Trigger task 0x1 EVENTS_DATARDY Temperature measurement complete, data ready 0x100 read-write 0x00000000 0x20 EVENTS_DATARDY Temperature measurement complete, data ready 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 DATARDY Write '1' to enable interrupt for event DATARDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 DATARDY Write '1' to disable interrupt for event DATARDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TEMP Temperature in degC (0.25deg steps) 0x508 read-only 0x00000000 int32_t 0x20 TEMP Temperature in degC (0.25deg steps) 0 31 A0 Slope of first piecewise linear function 0x520 read-write 0x00000326 0x20 A0 Slope of first piecewise linear function 0 11 A1 Slope of second piecewise linear function 0x524 read-write 0x00000348 0x20 A1 Slope of second piecewise linear function 0 11 A2 Slope of third piecewise linear function 0x528 read-write 0x000003AA 0x20 A2 Slope of third piecewise linear function 0 11 A3 Slope of fourth piecewise linear function 0x52C read-write 0x0000040E 0x20 A3 Slope of fourth piecewise linear function 0 11 A4 Slope of fifth piecewise linear function 0x530 read-write 0x000004BD 0x20 A4 Slope of fifth piecewise linear function 0 11 A5 Slope of sixth piecewise linear function 0x534 read-write 0x000005A3 0x20 A5 Slope of sixth piecewise linear function 0 11 B0 y-intercept of first piecewise linear function 0x540 read-write 0x00003FEF 0x20 B0 y-intercept of first piecewise linear function 0 13 B1 y-intercept of second piecewise linear function 0x544 read-write 0x00003FBE 0x20 B1 y-intercept of second piecewise linear function 0 13 B2 y-intercept of third piecewise linear function 0x548 read-write 0x00003FBE 0x20 B2 y-intercept of third piecewise linear function 0 13 B3 y-intercept of fourth piecewise linear function 0x54C read-write 0x00000012 0x20 B3 y-intercept of fourth piecewise linear function 0 13 B4 y-intercept of fifth piecewise linear function 0x550 read-write 0x00000124 0x20 B4 y-intercept of fifth piecewise linear function 0 13 B5 y-intercept of sixth piecewise linear function 0x554 read-write 0x0000027C 0x20 B5 y-intercept of sixth piecewise linear function 0 13 T0 End point of first piecewise linear function 0x560 read-write 0x000000E2 0x20 T0 End point of first piecewise linear function 0 7 T1 End point of second piecewise linear function 0x564 read-write 0x00000000 0x20 T1 End point of second piecewise linear function 0 7 T2 End point of third piecewise linear function 0x568 read-write 0x00000019 0x20 T2 End point of third piecewise linear function 0 7 T3 End point of fourth piecewise linear function 0x56C read-write 0x0000003C 0x20 T3 End point of fourth piecewise linear function 0 7 T4 End point of fifth piecewise linear function 0x570 read-write 0x00000050 0x20 T4 End point of fifth piecewise linear function 0 7 RNG Random Number Generator 0x4000D000 0 0x1000 registers RNG 13 RNG 0x20 TASKS_START Task starting the random number generator 0x000 write-only 0x00000000 0x20 TASKS_START Task starting the random number generator 0 0 Trigger Trigger task 0x1 TASKS_STOP Task stopping the random number generator 0x004 write-only 0x00000000 0x20 TASKS_STOP Task stopping the random number generator 0 0 Trigger Trigger task 0x1 EVENTS_VALRDY Event being generated for every new random number written to the VALUE register 0x100 read-write 0x00000000 0x20 EVENTS_VALRDY Event being generated for every new random number written to the VALUE register 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 VALRDY_STOP Shortcut between event VALRDY and task STOP 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 VALRDY Write '1' to enable interrupt for event VALRDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 VALRDY Write '1' to disable interrupt for event VALRDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CONFIG Configuration register 0x504 read-write 0x00000000 0x20 DERCEN Bias correction 0 0 Disabled Disabled 0x0 Enabled Enabled 0x1 VALUE Output random number 0x508 read-only 0x00000000 0x20 VALUE Generated random number 0 7 ECB AES ECB Mode Encryption 0x4000E000 0 0x1000 registers ECB 14 ECB 0x20 TASKS_STARTECB Start ECB block encrypt 0x000 write-only 0x00000000 0x20 TASKS_STARTECB Start ECB block encrypt 0 0 Trigger Trigger task 0x1 TASKS_STOPECB Abort a possible executing ECB operation 0x004 write-only 0x00000000 0x20 TASKS_STOPECB Abort a possible executing ECB operation 0 0 Trigger Trigger task 0x1 EVENTS_ENDECB ECB block encrypt complete 0x100 read-write 0x00000000 0x20 EVENTS_ENDECB ECB block encrypt complete 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERRORECB ECB block encrypt aborted because of a STOPECB task or due to an error 0x104 read-write 0x00000000 0x20 EVENTS_ERRORECB ECB block encrypt aborted because of a STOPECB task or due to an error 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 ENDECB Write '1' to enable interrupt for event ENDECB 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERRORECB Write '1' to enable interrupt for event ERRORECB 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 ENDECB Write '1' to disable interrupt for event ENDECB 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORECB Write '1' to disable interrupt for event ERRORECB 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ECBDATAPTR ECB block encrypt memory pointers 0x504 read-write 0x00000000 0x20 ECBDATAPTR Pointer to the ECB data structure (see Table 1 ECB data structure overview) 0 31 AAR Accelerated Address Resolver 0x4000F000 0 0x1000 registers AAR_CCM 15 AAR 0x20 TASKS_START Start resolving addresses based on IRKs specified in the IRK data structure 0x000 write-only 0x00000000 0x20 TASKS_START Start resolving addresses based on IRKs specified in the IRK data structure 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop resolving addresses 0x008 write-only 0x00000000 0x20 TASKS_STOP Stop resolving addresses 0 0 Trigger Trigger task 0x1 EVENTS_END Address resolution procedure complete 0x100 read-write 0x00000000 0x20 EVENTS_END Address resolution procedure complete 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RESOLVED Address resolved 0x104 read-write 0x00000000 0x20 EVENTS_RESOLVED Address resolved 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_NOTRESOLVED Address not resolved 0x108 read-write 0x00000000 0x20 EVENTS_NOTRESOLVED Address not resolved 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 END Write '1' to enable interrupt for event END 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RESOLVED Write '1' to enable interrupt for event RESOLVED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 NOTRESOLVED Write '1' to enable interrupt for event NOTRESOLVED 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 END Write '1' to disable interrupt for event END 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RESOLVED Write '1' to disable interrupt for event RESOLVED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 NOTRESOLVED Write '1' to disable interrupt for event NOTRESOLVED 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STATUS Resolution status 0x400 read-only 0x00000000 0x20 STATUS The IRK that was used last time an address was resolved 0 3 ENABLE Enable AAR 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable AAR 0 1 Disabled Disable 0x0 Enabled Enable 0x3 NIRK Number of IRKs 0x504 read-write 0x00000001 0x20 NIRK Number of Identity Root Keys available in the IRK data structure 0 4 IRKPTR Pointer to IRK data structure 0x508 read-write 0x00000000 0x20 IRKPTR Pointer to the IRK data structure 0 31 ADDRPTR Pointer to the resolvable address 0x510 read-write 0x00000000 0x20 ADDRPTR Pointer to the resolvable address (6-bytes) 0 31 SCRATCHPTR Pointer to data area used for temporary storage 0x514 read-write 0x00000000 0x20 SCRATCHPTR Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. 0 31 CCM AES CCM mode encryption 0x4000F000 AAR 0 0x1000 registers AAR_CCM 15 CCM 0x20 TASKS_KSGEN Start generation of keystream. This operation will stop by itself when completed. 0x000 write-only 0x00000000 0x20 TASKS_KSGEN Start generation of keystream. This operation will stop by itself when completed. 0 0 Trigger Trigger task 0x1 TASKS_CRYPT Start encryption/decryption. This operation will stop by itself when completed. 0x004 write-only 0x00000000 0x20 TASKS_CRYPT Start encryption/decryption. This operation will stop by itself when completed. 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop encryption/decryption 0x008 write-only 0x00000000 0x20 TASKS_STOP Stop encryption/decryption 0 0 Trigger Trigger task 0x1 TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption 0x00C write-only 0x00000000 0x20 TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption 0 0 Trigger Trigger task 0x1 EVENTS_ENDKSGEN Keystream generation complete 0x100 read-write 0x00000000 0x20 EVENTS_ENDKSGEN Keystream generation complete 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDCRYPT Encrypt/decrypt complete 0x104 read-write 0x00000000 0x20 EVENTS_ENDCRYPT Encrypt/decrypt complete 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR Deprecated register - CCM error event 0x108 read-write 0x00000000 0x20 EVENTS_ERROR Deprecated field - CCM error event 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 ENDKSGEN_CRYPT Shortcut between event ENDKSGEN and task CRYPT 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 ENDKSGEN Write '1' to enable interrupt for event ENDKSGEN 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDCRYPT Write '1' to enable interrupt for event ENDCRYPT 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Deprecated intsetfield - Write '1' to enable interrupt for event ERROR 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 ENDKSGEN Write '1' to disable interrupt for event ENDKSGEN 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDCRYPT Write '1' to disable interrupt for event ENDCRYPT 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Deprecated intclrfield - Write '1' to disable interrupt for event ERROR 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 MICSTATUS MIC check result 0x400 read-only 0x00000000 0x20 MICSTATUS The result of the MIC check performed during the previous decryption operation 0 0 CheckFailed MIC check failed 0x0 CheckPassed MIC check passed 0x1 ENABLE Enable 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable CCM 0 1 Disabled Disable 0x0 Enabled Enable 0x2 MODE Operation mode 0x504 read-write 0x00000001 0x20 MODE The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. 0 0 Encryption AES CCM packet encryption mode 0x0 Decryption AES CCM packet decryption mode 0x1 DATARATE Radio data rate that the CCM shall run synchronous with 16 17 1Mbit 1 Mbps 0x0 2Mbit 2 Mbps 0x1 125Kbps 125 kbps 0x2 500Kbps 500 kbps 0x3 LENGTH Packet length configuration 24 24 Default Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. 0x0 Extended Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 0x1 CNFPTR Pointer to data structure holding the AES key and the NONCE vector 0x508 read-write 0x00000000 0x20 CNFPTR Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) 0 31 INPTR Input pointer 0x50C read-write 0x00000000 0x20 INPTR Input pointer 0 31 OUTPTR Output pointer 0x510 read-write 0x00000000 0x20 OUTPTR Output pointer 0 31 SCRATCHPTR Pointer to data area used for temporary storage 0x514 read-write 0x00000000 0x20 SCRATCHPTR Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. 0 31 MAXPACKETSIZE Length of keystream generated when MODE.LENGTH = Extended 0x518 read-write 0x000000FB 0x20 MAXPACKETSIZE Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 RATEOVERRIDE Data rate override setting. 0x51C read-write 0x00000000 0x20 RATEOVERRIDE Data rate override setting 0 1 1Mbit 1 Mbps 0x0 2Mbit 2 Mbps 0x1 125Kbps 125 kbps 0x2 500Kbps 500 kbps 0x3 WDT Watchdog Timer 0x40010000 0 0x1000 registers WDT 16 WDT 0x20 TASKS_START Start the watchdog 0x000 write-only 0x00000000 0x20 TASKS_START Start the watchdog 0 0 Trigger Trigger task 0x1 EVENTS_TIMEOUT Watchdog timeout 0x100 read-write 0x00000000 0x20 EVENTS_TIMEOUT Watchdog timeout 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 TIMEOUT Write '1' to enable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 TIMEOUT Write '1' to disable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RUNSTATUS Run status 0x400 read-only 0x00000000 0x20 RUNSTATUS Indicates whether or not the watchdog is running 0 0 NotRunning Watchdog not running 0x0 Running Watchdog is running 0x1 REQSTATUS Request status 0x404 read-only 0x00000001 0x20 RR0 Request status for RR[0] register 0 0 DisabledOrRequested RR[0] register is not enabled, or is already requesting reload 0x0 EnabledAndUnrequested RR[0] register is enabled, and is not yet requesting reload 0x1 RR1 Request status for RR[1] register 1 1 DisabledOrRequested RR[1] register is not enabled, or is already requesting reload 0x0 EnabledAndUnrequested RR[1] register is enabled, and is not yet requesting reload 0x1 RR2 Request status for RR[2] register 2 2 DisabledOrRequested RR[2] register is not enabled, or is already requesting reload 0x0 EnabledAndUnrequested RR[2] register is enabled, and is not yet requesting reload 0x1 RR3 Request status for RR[3] register 3 3 DisabledOrRequested RR[3] register is not enabled, or is already requesting reload 0x0 EnabledAndUnrequested RR[3] register is enabled, and is not yet requesting reload 0x1 RR4 Request status for RR[4] register 4 4 DisabledOrRequested RR[4] register is not enabled, or is already requesting reload 0x0 EnabledAndUnrequested RR[4] register is enabled, and is not yet requesting reload 0x1 RR5 Request status for RR[5] register 5 5 DisabledOrRequested RR[5] register is not enabled, or is already requesting reload 0x0 EnabledAndUnrequested RR[5] register is enabled, and is not yet requesting reload 0x1 RR6 Request status for RR[6] register 6 6 DisabledOrRequested RR[6] register is not enabled, or is already requesting reload 0x0 EnabledAndUnrequested RR[6] register is enabled, and is not yet requesting reload 0x1 RR7 Request status for RR[7] register 7 7 DisabledOrRequested RR[7] register is not enabled, or is already requesting reload 0x0 EnabledAndUnrequested RR[7] register is enabled, and is not yet requesting reload 0x1 CRV Counter reload value 0x504 read-write 0xFFFFFFFF 0x20 CRV Counter reload value in number of cycles of the 32.768 kHz clock 0 31 RREN Enable register for reload request registers 0x508 read-write 0x00000001 0x20 RR0 Enable or disable RR[0] register 0 0 Disabled Disable RR[0] register 0x0 Enabled Enable RR[0] register 0x1 RR1 Enable or disable RR[1] register 1 1 Disabled Disable RR[1] register 0x0 Enabled Enable RR[1] register 0x1 RR2 Enable or disable RR[2] register 2 2 Disabled Disable RR[2] register 0x0 Enabled Enable RR[2] register 0x1 RR3 Enable or disable RR[3] register 3 3 Disabled Disable RR[3] register 0x0 Enabled Enable RR[3] register 0x1 RR4 Enable or disable RR[4] register 4 4 Disabled Disable RR[4] register 0x0 Enabled Enable RR[4] register 0x1 RR5 Enable or disable RR[5] register 5 5 Disabled Disable RR[5] register 0x0 Enabled Enable RR[5] register 0x1 RR6 Enable or disable RR[6] register 6 6 Disabled Disable RR[6] register 0x0 Enabled Enable RR[6] register 0x1 RR7 Enable or disable RR[7] register 7 7 Disabled Disable RR[7] register 0x0 Enabled Enable RR[7] register 0x1 CONFIG Configuration register 0x50C read-write 0x00000001 0x20 SLEEP Configure the watchdog to either be paused, or kept running, while the CPU is sleeping 0 0 Pause Pause watchdog while the CPU is sleeping 0x0 Run Keep the watchdog running while the CPU is sleeping 0x1 HALT Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger 3 3 Pause Pause watchdog while the CPU is halted by the debugger 0x0 Run Keep the watchdog running while the CPU is halted by the debugger 0x1 0x8 0x4 RR[%s] Description collection: Reload request n 0x600 write-only 0x00000000 0x20 RR Reload request register 0 31 Reload Value to request a reload of the watchdog timer 0x6E524635 RTC1 Real time counter 1 0x40011000 RTC1 17 QDEC Quadrature Decoder 0x40012000 0 0x1000 registers QDEC 18 QDEC 0x20 TASKS_START Task starting the quadrature decoder 0x000 write-only 0x00000000 0x20 TASKS_START Task starting the quadrature decoder 0 0 Trigger Trigger task 0x1 TASKS_STOP Task stopping the quadrature decoder 0x004 write-only 0x00000000 0x20 TASKS_STOP Task stopping the quadrature decoder 0 0 Trigger Trigger task 0x1 TASKS_READCLRACC Read and clear ACC and ACCDBL 0x008 write-only 0x00000000 0x20 TASKS_READCLRACC Read and clear ACC and ACCDBL 0 0 Trigger Trigger task 0x1 TASKS_RDCLRACC Read and clear ACC 0x00C write-only 0x00000000 0x20 TASKS_RDCLRACC Read and clear ACC 0 0 Trigger Trigger task 0x1 TASKS_RDCLRDBL Read and clear ACCDBL 0x010 write-only 0x00000000 0x20 TASKS_RDCLRDBL Read and clear ACCDBL 0 0 Trigger Trigger task 0x1 EVENTS_SAMPLERDY Event being generated for every new sample value written to the SAMPLE register 0x100 read-write 0x00000000 0x20 EVENTS_SAMPLERDY Event being generated for every new sample value written to the SAMPLE register 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_REPORTRDY Non-null report ready 0x104 read-write 0x00000000 0x20 EVENTS_REPORTRDY Non-null report ready 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ACCOF ACC or ACCDBL register overflow 0x108 read-write 0x00000000 0x20 EVENTS_ACCOF ACC or ACCDBL register overflow 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DBLRDY Double displacement(s) detected 0x10C read-write 0x00000000 0x20 EVENTS_DBLRDY Double displacement(s) detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED QDEC has been stopped 0x110 read-write 0x00000000 0x20 EVENTS_STOPPED QDEC has been stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 REPORTRDY_READCLRACC Shortcut between event REPORTRDY and task READCLRACC 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 SAMPLERDY_STOP Shortcut between event SAMPLERDY and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 REPORTRDY_RDCLRACC Shortcut between event REPORTRDY and task RDCLRACC 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 REPORTRDY_STOP Shortcut between event REPORTRDY and task STOP 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DBLRDY_RDCLRDBL Shortcut between event DBLRDY and task RDCLRDBL 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DBLRDY_STOP Shortcut between event DBLRDY and task STOP 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 SAMPLERDY_READCLRACC Shortcut between event SAMPLERDY and task READCLRACC 6 6 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 SAMPLERDY Write '1' to enable interrupt for event SAMPLERDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REPORTRDY Write '1' to enable interrupt for event REPORTRDY 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACCOF Write '1' to enable interrupt for event ACCOF 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DBLRDY Write '1' to enable interrupt for event DBLRDY 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 SAMPLERDY Write '1' to disable interrupt for event SAMPLERDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REPORTRDY Write '1' to disable interrupt for event REPORTRDY 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACCOF Write '1' to disable interrupt for event ACCOF 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DBLRDY Write '1' to disable interrupt for event DBLRDY 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE Enable the quadrature decoder 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable the quadrature decoder 0 0 Disabled Disable 0x0 Enabled Enable 0x1 LEDPOL LED output pin polarity 0x504 read-write 0x00000000 0x20 LEDPOL LED output pin polarity 0 0 ActiveLow Led active on output pin low 0x0 ActiveHigh Led active on output pin high 0x1 SAMPLEPER Sample period 0x508 read-write 0x00000000 0x20 SAMPLEPER Sample period. The SAMPLE register will be updated for every new sample 0 3 128us 128 us 0x0 256us 256 us 0x1 512us 512 us 0x2 1024us 1024 us 0x3 2048us 2048 us 0x4 4096us 4096 us 0x5 8192us 8192 us 0x6 16384us 16384 us 0x7 32ms 32768 us 0x8 65ms 65536 us 0x9 131ms 131072 us 0xA SAMPLE Motion sample value 0x50C read-only 0x00000000 int32_t 0x20 SAMPLE Last motion sample 0 31 REPORTPER Number of samples to be taken before REPORTRDY and DBLRDY events can be generated 0x510 read-write 0x00000000 0x20 REPORTPER Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. 0 3 10Smpl 10 samples/report 0x0 40Smpl 40 samples/report 0x1 80Smpl 80 samples/report 0x2 120Smpl 120 samples/report 0x3 160Smpl 160 samples/report 0x4 200Smpl 200 samples/report 0x5 240Smpl 240 samples/report 0x6 280Smpl 280 samples/report 0x7 1Smpl 1 sample/report 0x8 ACC Register accumulating the valid transitions 0x514 read-only 0x00000000 int32_t 0x20 ACC Register accumulating all valid samples (not double transition) read from the SAMPLE register. 0 31 ACCREAD Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task 0x518 read-only 0x00000000 int32_t 0x20 ACCREAD Snapshot of the ACC register. 0 31 PSEL Unspecified QDEC_PSEL read-write 0x51C LED Pin select for LED signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 A Pin select for A signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 B Pin select for B signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 DBFEN Enable input debounce filters 0x528 read-write 0x00000000 0x20 DBFEN Enable input debounce filters 0 0 Disabled Debounce input filters disabled 0x0 Enabled Debounce input filters enabled 0x1 LEDPRE Time period the LED is switched ON prior to sampling 0x540 read-write 0x00000010 0x20 LEDPRE Period in us the LED is switched on prior to sampling 0 8 ACCDBL Register accumulating the number of detected double transitions 0x544 read-only 0x00000000 0x20 ACCDBL Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). 0 3 ACCDBLREAD Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task 0x548 read-only 0x00000000 0x20 ACCDBLREAD Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. 0 3 COMP Comparator 0x40013000 0 0x1000 registers COMP_LPCOMP 19 COMP 0x20 TASKS_START Start comparator 0x000 write-only 0x00000000 0x20 TASKS_START Start comparator 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop comparator 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop comparator 0 0 Trigger Trigger task 0x1 TASKS_SAMPLE Sample comparator value 0x008 write-only 0x00000000 0x20 TASKS_SAMPLE Sample comparator value 0 0 Trigger Trigger task 0x1 EVENTS_READY COMP is ready and output is valid 0x100 read-write 0x00000000 0x20 EVENTS_READY COMP is ready and output is valid 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DOWN Downward crossing 0x104 read-write 0x00000000 0x20 EVENTS_DOWN Downward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_UP Upward crossing 0x108 read-write 0x00000000 0x20 EVENTS_UP Upward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CROSS Downward or upward crossing 0x10C read-write 0x00000000 0x20 EVENTS_CROSS Downward or upward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 READY_SAMPLE Shortcut between event READY and task SAMPLE 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 READY_STOP Shortcut between event READY and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DOWN_STOP Shortcut between event DOWN and task STOP 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 UP_STOP Shortcut between event UP and task STOP 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 CROSS_STOP Shortcut between event CROSS and task STOP 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 READY Enable or disable interrupt for event READY 0 0 Disabled Disable 0x0 Enabled Enable 0x1 DOWN Enable or disable interrupt for event DOWN 1 1 Disabled Disable 0x0 Enabled Enable 0x1 UP Enable or disable interrupt for event UP 2 2 Disabled Disable 0x0 Enabled Enable 0x1 CROSS Enable or disable interrupt for event CROSS 3 3 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DOWN Write '1' to enable interrupt for event DOWN 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 UP Write '1' to enable interrupt for event UP 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CROSS Write '1' to enable interrupt for event CROSS 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DOWN Write '1' to disable interrupt for event DOWN 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 UP Write '1' to disable interrupt for event UP 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CROSS Write '1' to disable interrupt for event CROSS 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RESULT Compare result 0x400 read-only 0x00000000 0x20 RESULT Result of last compare. Decision point SAMPLE task. 0 0 Below Input voltage is below the threshold (VIN+ < VIN-) 0x0 Above Input voltage is above the threshold (VIN+ > VIN-) 0x1 ENABLE COMP enable 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable COMP 0 1 Disabled Disable 0x0 Enabled Enable 0x2 PSEL Pin select 0x504 read-write 0x00000000 0x20 PSEL Analog pin select 0 2 AnalogInput0 AIN0 selected as analog input 0x0 AnalogInput1 AIN1 selected as analog input 0x1 AnalogInput2 AIN2 selected as analog input 0x2 AnalogInput3 AIN3 selected as analog input 0x3 AnalogInput4 AIN4 selected as analog input 0x4 AnalogInput5 AIN5 selected as analog input 0x5 AnalogInput6 AIN6 selected as analog input 0x6 AnalogInput7 AIN7 selected as analog input 0x7 REFSEL Reference source select for single-ended mode 0x508 read-write 0x00000004 0x20 REFSEL Reference select 0 2 Int1V2 VREF = internal 1.2 V reference (VDD >= 1.7 V) 0x0 Int1V8 VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) 0x1 Int2V4 VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) 0x2 VDD VREF = VDD 0x4 ARef VREF = AREF 0x5 EXTREFSEL External reference select 0x50C read-write 0x00000000 0x20 EXTREFSEL External analog reference select 0 2 AnalogReference0 Use AIN0 as external analog reference 0x0 AnalogReference1 Use AIN1 as external analog reference 0x1 AnalogReference2 Use AIN2 as external analog reference 0x2 AnalogReference3 Use AIN3 as external analog reference 0x3 AnalogReference4 Use AIN4 as external analog reference 0x4 AnalogReference5 Use AIN5 as external analog reference 0x5 AnalogReference6 Use AIN6 as external analog reference 0x6 AnalogReference7 Use AIN7 as external analog reference 0x7 TH Threshold configuration for hysteresis unit 0x530 read-write 0x00000000 0x20 THDOWN VDOWN = (THDOWN+1)/64*VREF 0 5 THUP VUP = (THUP+1)/64*VREF 8 13 MODE Mode configuration 0x534 read-write 0x00000000 0x20 SP Speed and power modes 0 1 Low Low-power mode 0x0 Normal Normal mode 0x1 High High-speed mode 0x2 MAIN Main operation modes 8 8 SE Single-ended mode 0x0 Diff Differential mode 0x1 HYST Comparator hysteresis enable 0x538 read-write 0x00000000 0x20 HYST Comparator hysteresis 0 0 NoHyst Comparator hysteresis disabled 0x0 Hyst50mV Comparator hysteresis enabled 0x1 LPCOMP Low-power comparator 0x40013000 COMP 0 0x1000 registers COMP_LPCOMP 19 LPCOMP 0x20 TASKS_START Start comparator 0x000 write-only 0x00000000 0x20 TASKS_START Start comparator 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop comparator 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop comparator 0 0 Trigger Trigger task 0x1 TASKS_SAMPLE Sample comparator value 0x008 write-only 0x00000000 0x20 TASKS_SAMPLE Sample comparator value 0 0 Trigger Trigger task 0x1 EVENTS_READY LPCOMP is ready and output is valid 0x100 read-write 0x00000000 0x20 EVENTS_READY LPCOMP is ready and output is valid 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DOWN Downward crossing 0x104 read-write 0x00000000 0x20 EVENTS_DOWN Downward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_UP Upward crossing 0x108 read-write 0x00000000 0x20 EVENTS_UP Upward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CROSS Downward or upward crossing 0x10C read-write 0x00000000 0x20 EVENTS_CROSS Downward or upward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 READY_SAMPLE Shortcut between event READY and task SAMPLE 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 READY_STOP Shortcut between event READY and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DOWN_STOP Shortcut between event DOWN and task STOP 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 UP_STOP Shortcut between event UP and task STOP 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 CROSS_STOP Shortcut between event CROSS and task STOP 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DOWN Write '1' to enable interrupt for event DOWN 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 UP Write '1' to enable interrupt for event UP 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CROSS Write '1' to enable interrupt for event CROSS 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DOWN Write '1' to disable interrupt for event DOWN 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 UP Write '1' to disable interrupt for event UP 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CROSS Write '1' to disable interrupt for event CROSS 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RESULT Compare result 0x400 read-only 0x00000000 0x20 RESULT Result of last compare. Decision point SAMPLE task. 0 0 Below Input voltage is below the reference threshold (VIN+ < VIN-) 0x0 Above Input voltage is above the reference threshold (VIN+ > VIN-) 0x1 ENABLE Enable LPCOMP 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable LPCOMP 0 1 Disabled Disable 0x0 Enabled Enable 0x1 PSEL Input pin select 0x504 read-write 0x00000000 0x20 PSEL Analog pin select 0 2 AnalogInput0 AIN0 selected as analog input 0x0 AnalogInput1 AIN1 selected as analog input 0x1 AnalogInput2 AIN2 selected as analog input 0x2 AnalogInput3 AIN3 selected as analog input 0x3 AnalogInput4 AIN4 selected as analog input 0x4 AnalogInput5 AIN5 selected as analog input 0x5 AnalogInput6 AIN6 selected as analog input 0x6 AnalogInput7 AIN7 selected as analog input 0x7 REFSEL Reference select 0x508 read-write 0x00000004 0x20 REFSEL Reference select 0 3 Ref1_8Vdd VDD * 1/8 selected as reference 0x0 Ref2_8Vdd VDD * 2/8 selected as reference 0x1 Ref3_8Vdd VDD * 3/8 selected as reference 0x2 Ref4_8Vdd VDD * 4/8 selected as reference 0x3 Ref5_8Vdd VDD * 5/8 selected as reference 0x4 Ref6_8Vdd VDD * 6/8 selected as reference 0x5 Ref7_8Vdd VDD * 7/8 selected as reference 0x6 ARef External analog reference selected 0x7 Ref1_16Vdd VDD * 1/16 selected as reference 0x8 Ref3_16Vdd VDD * 3/16 selected as reference 0x9 Ref5_16Vdd VDD * 5/16 selected as reference 0xA Ref7_16Vdd VDD * 7/16 selected as reference 0xB Ref9_16Vdd VDD * 9/16 selected as reference 0xC Ref11_16Vdd VDD * 11/16 selected as reference 0xD Ref13_16Vdd VDD * 13/16 selected as reference 0xE Ref15_16Vdd VDD * 15/16 selected as reference 0xF EXTREFSEL External reference select 0x50C read-write 0x00000000 0x20 EXTREFSEL External analog reference select 0 0 AnalogReference0 Use AIN0 as external analog reference 0x0 AnalogReference1 Use AIN1 as external analog reference 0x1 ANADETECT Analog detect configuration 0x520 read-write 0x00000000 0x20 ANADETECT Analog detect configuration 0 1 Cross Generate ANADETECT on crossing, both upward crossing and downward crossing 0x0 Up Generate ANADETECT on upward crossing only 0x1 Down Generate ANADETECT on downward crossing only 0x2 HYST Comparator hysteresis enable 0x538 read-write 0x00000000 0x20 HYST Comparator hysteresis enable 0 0 Disabled Comparator hysteresis disabled 0x0 Enabled Comparator hysteresis enabled 0x1 EGU0 Event generator unit 0 0x40014000 EGU 0 0x1000 registers EGU0_SWI0 20 EGU 0x20 0x10 0x4 TASKS_TRIGGER[%s] Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event 0x000 write-only 0x00000000 0x20 TASKS_TRIGGER Trigger n for triggering the corresponding TRIGGERED[n] event 0 0 Trigger Trigger task 0x1 0x10 0x4 EVENTS_TRIGGERED[%s] Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task 0x100 read-write 0x00000000 0x20 EVENTS_TRIGGERED Event number n generated by triggering the corresponding TRIGGER[n] task 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 TRIGGERED0 Enable or disable interrupt for event TRIGGERED[0] 0 0 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED1 Enable or disable interrupt for event TRIGGERED[1] 1 1 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED2 Enable or disable interrupt for event TRIGGERED[2] 2 2 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED3 Enable or disable interrupt for event TRIGGERED[3] 3 3 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED4 Enable or disable interrupt for event TRIGGERED[4] 4 4 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED5 Enable or disable interrupt for event TRIGGERED[5] 5 5 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED6 Enable or disable interrupt for event TRIGGERED[6] 6 6 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED7 Enable or disable interrupt for event TRIGGERED[7] 7 7 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED8 Enable or disable interrupt for event TRIGGERED[8] 8 8 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED9 Enable or disable interrupt for event TRIGGERED[9] 9 9 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED10 Enable or disable interrupt for event TRIGGERED[10] 10 10 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED11 Enable or disable interrupt for event TRIGGERED[11] 11 11 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED12 Enable or disable interrupt for event TRIGGERED[12] 12 12 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED13 Enable or disable interrupt for event TRIGGERED[13] 13 13 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED14 Enable or disable interrupt for event TRIGGERED[14] 14 14 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED15 Enable or disable interrupt for event TRIGGERED[15] 15 15 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 TRIGGERED0 Write '1' to enable interrupt for event TRIGGERED[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED1 Write '1' to enable interrupt for event TRIGGERED[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED2 Write '1' to enable interrupt for event TRIGGERED[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED3 Write '1' to enable interrupt for event TRIGGERED[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED4 Write '1' to enable interrupt for event TRIGGERED[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED5 Write '1' to enable interrupt for event TRIGGERED[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED6 Write '1' to enable interrupt for event TRIGGERED[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED7 Write '1' to enable interrupt for event TRIGGERED[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED8 Write '1' to enable interrupt for event TRIGGERED[8] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED9 Write '1' to enable interrupt for event TRIGGERED[9] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED10 Write '1' to enable interrupt for event TRIGGERED[10] 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED11 Write '1' to enable interrupt for event TRIGGERED[11] 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED12 Write '1' to enable interrupt for event TRIGGERED[12] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED13 Write '1' to enable interrupt for event TRIGGERED[13] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED14 Write '1' to enable interrupt for event TRIGGERED[14] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED15 Write '1' to enable interrupt for event TRIGGERED[15] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 TRIGGERED0 Write '1' to disable interrupt for event TRIGGERED[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED1 Write '1' to disable interrupt for event TRIGGERED[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED2 Write '1' to disable interrupt for event TRIGGERED[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED3 Write '1' to disable interrupt for event TRIGGERED[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED4 Write '1' to disable interrupt for event TRIGGERED[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED5 Write '1' to disable interrupt for event TRIGGERED[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED6 Write '1' to disable interrupt for event TRIGGERED[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED7 Write '1' to disable interrupt for event TRIGGERED[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED8 Write '1' to disable interrupt for event TRIGGERED[8] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED9 Write '1' to disable interrupt for event TRIGGERED[9] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED10 Write '1' to disable interrupt for event TRIGGERED[10] 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED11 Write '1' to disable interrupt for event TRIGGERED[11] 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED12 Write '1' to disable interrupt for event TRIGGERED[12] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED13 Write '1' to disable interrupt for event TRIGGERED[13] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED14 Write '1' to disable interrupt for event TRIGGERED[14] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED15 Write '1' to disable interrupt for event TRIGGERED[15] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SWI0 Software interrupt 0 0x40014000 EGU0 SWI 0 0x1000 registers EGU0_SWI0 20 SWI 0x20 UNUSED Unused. 0x000 0x00000000 read-only EGU1 Event generator unit 1 0x40015000 EGU1_SWI1 21 SWI1 Software interrupt 1 0x40015000 EGU1 EGU1_SWI1 21 EGU2 Event generator unit 2 0x40016000 EGU2_SWI2 22 SWI2 Software interrupt 2 0x40016000 EGU2 EGU2_SWI2 22 EGU3 Event generator unit 3 0x40017000 EGU3_SWI3 23 SWI3 Software interrupt 3 0x40017000 EGU3 EGU3_SWI3 23 EGU4 Event generator unit 4 0x40018000 EGU4_SWI4 24 SWI4 Software interrupt 4 0x40018000 EGU4 EGU4_SWI4 24 EGU5 Event generator unit 5 0x40019000 EGU5_SWI5 25 SWI5 Software interrupt 5 0x40019000 EGU5 EGU5_SWI5 25 TIMER3 Timer/Counter 3 0x4001A000 TIMER3 26 TIMER4 Timer/Counter 4 0x4001B000 TIMER4 27 PWM0 Pulse width modulation unit 0 0x4001C000 PWM 0 0x1000 registers PWM0 28 PWM 0x20 TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0x004 write-only 0x00000000 0x20 TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0 0 Trigger Trigger task 0x1 0x2 0x4 TASKS_SEQSTART[%s] Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0x008 write-only 0x00000000 0x20 TASKS_SEQSTART Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0 0 Trigger Trigger task 0x1 TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 0x010 write-only 0x00000000 0x20 TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 0 0 Trigger Trigger task 0x1 EVENTS_STOPPED Response to STOP task, emitted when PWM pulses are no longer generated 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED Response to STOP task, emitted when PWM pulses are no longer generated 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x2 0x4 EVENTS_SEQSTARTED[%s] Description collection: First PWM period started on sequence n 0x108 read-write 0x00000000 0x20 EVENTS_SEQSTARTED First PWM period started on sequence n 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x2 0x4 EVENTS_SEQEND[%s] Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0x110 read-write 0x00000000 0x20 EVENTS_SEQEND Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_PWMPERIODEND Emitted at the end of each PWM period 0x118 read-write 0x00000000 0x20 EVENTS_PWMPERIODEND Emitted at the end of each PWM period 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_LOOPSDONE Concatenated sequences have been played the amount of times defined in LOOP.CNT 0x11C read-write 0x00000000 0x20 EVENTS_LOOPSDONE Concatenated sequences have been played the amount of times defined in LOOP.CNT 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 SEQEND0_STOP Shortcut between event SEQEND[0] and task STOP 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 SEQEND1_STOP Shortcut between event SEQEND[1] and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LOOPSDONE_SEQSTART0 Shortcut between event LOOPSDONE and task SEQSTART[0] 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LOOPSDONE_SEQSTART1 Shortcut between event LOOPSDONE and task SEQSTART[1] 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 SEQSTARTED0 Enable or disable interrupt for event SEQSTARTED[0] 2 2 Disabled Disable 0x0 Enabled Enable 0x1 SEQSTARTED1 Enable or disable interrupt for event SEQSTARTED[1] 3 3 Disabled Disable 0x0 Enabled Enable 0x1 SEQEND0 Enable or disable interrupt for event SEQEND[0] 4 4 Disabled Disable 0x0 Enabled Enable 0x1 SEQEND1 Enable or disable interrupt for event SEQEND[1] 5 5 Disabled Disable 0x0 Enabled Enable 0x1 PWMPERIODEND Enable or disable interrupt for event PWMPERIODEND 6 6 Disabled Disable 0x0 Enabled Enable 0x1 LOOPSDONE Enable or disable interrupt for event LOOPSDONE 7 7 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SEQSTARTED0 Write '1' to enable interrupt for event SEQSTARTED[0] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SEQSTARTED1 Write '1' to enable interrupt for event SEQSTARTED[1] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SEQEND0 Write '1' to enable interrupt for event SEQEND[0] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SEQEND1 Write '1' to enable interrupt for event SEQEND[1] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PWMPERIODEND Write '1' to enable interrupt for event PWMPERIODEND 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 LOOPSDONE Write '1' to enable interrupt for event LOOPSDONE 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEQSTARTED0 Write '1' to disable interrupt for event SEQSTARTED[0] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEQSTARTED1 Write '1' to disable interrupt for event SEQSTARTED[1] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEQEND0 Write '1' to disable interrupt for event SEQEND[0] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEQEND1 Write '1' to disable interrupt for event SEQEND[1] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PWMPERIODEND Write '1' to disable interrupt for event PWMPERIODEND 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 LOOPSDONE Write '1' to disable interrupt for event LOOPSDONE 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE PWM module enable register 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable PWM module 0 0 Disabled Disabled 0x0 Enabled Enable 0x1 MODE Selects operating mode of the wave counter 0x504 read-write 0x00000000 0x20 UPDOWN Selects up mode or up-and-down mode for the counter 0 0 Up Up counter, edge-aligned PWM duty cycle 0x0 UpAndDown Up and down counter, center-aligned PWM duty cycle 0x1 COUNTERTOP Value up to which the pulse generator counter counts 0x508 read-write 0x000003FF 0x20 COUNTERTOP Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. 0 14 PRESCALER Configuration for PWM_CLK 0x50C read-write 0x00000000 0x20 PRESCALER Prescaler of PWM_CLK 0 2 DIV_1 Divide by 1 (16 MHz) 0x0 DIV_2 Divide by 2 (8 MHz) 0x1 DIV_4 Divide by 4 (4 MHz) 0x2 DIV_8 Divide by 8 (2 MHz) 0x3 DIV_16 Divide by 16 (1 MHz) 0x4 DIV_32 Divide by 32 (500 kHz) 0x5 DIV_64 Divide by 64 (250 kHz) 0x6 DIV_128 Divide by 128 (125 kHz) 0x7 DECODER Configuration of the decoder 0x510 read-write 0x00000000 0x20 LOAD How a sequence is read from RAM and spread to the compare register 0 1 Common 1st half word (16-bit) used in all PWM channels 0..3 0x0 Grouped 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 0x1 Individual 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 0x2 WaveForm 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP 0x3 MODE Selects source for advancing the active sequence 8 8 RefreshCount SEQ[n].REFRESH is used to determine loading internal compare registers 0x0 NextStep NEXTSTEP task causes a new value to be loaded to internal compare registers 0x1 LOOP Number of playbacks of a loop 0x514 read-write 0x00000000 0x20 CNT Number of playbacks of pattern cycles 0 15 Disabled Looping disabled (stop at the end of the sequence) 0x0000 2 0x020 SEQ[%s] Unspecified PWM_SEQ read-write 0x520 PTR Description cluster: Beginning address in RAM of this sequence 0x000 read-write 0x00000000 0x20 PTR Beginning address in RAM of this sequence 0 31 CNT Description cluster: Number of values (duty cycles) in this sequence 0x004 read-write 0x00000000 0x20 CNT Number of values (duty cycles) in this sequence 0 14 Disabled Sequence is disabled, and shall not be started as it is empty 0x0000 REFRESH Description cluster: Number of additional PWM periods between samples loaded into compare register 0x008 read-write 0x00000001 0x20 CNT Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) 0 23 Continuous Update every PWM period 0x000000 ENDDELAY Description cluster: Time added after the sequence 0x00C read-write 0x00000000 0x20 CNT Time added after the sequence in PWM periods 0 23 PSEL Unspecified PWM_PSEL read-write 0x560 0x4 0x4 OUT[%s] Description collection: Output pin select for PWM channel n 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 PDM Pulse Density Modulation (Digital Microphone) Interface 0x4001D000 0 0x1000 registers PDM 29 PDM 0x20 TASKS_START Starts continuous PDM transfer 0x000 write-only 0x00000000 0x20 TASKS_START Starts continuous PDM transfer 0 0 Trigger Trigger task 0x1 TASKS_STOP Stops PDM transfer 0x004 write-only 0x00000000 0x20 TASKS_STOP Stops PDM transfer 0 0 Trigger Trigger task 0x1 EVENTS_STARTED PDM transfer has started 0x100 read-write 0x00000000 0x20 EVENTS_STARTED PDM transfer has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED PDM transfer has finished 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED PDM transfer has finished 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_END The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0x108 read-write 0x00000000 0x20 EVENTS_END The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STARTED Enable or disable interrupt for event STARTED 0 0 Disabled Disable 0x0 Enabled Enable 0x1 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 END Enable or disable interrupt for event END 2 2 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STARTED Write '1' to enable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 END Write '1' to enable interrupt for event END 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STARTED Write '1' to disable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 END Write '1' to disable interrupt for event END 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE PDM module enable register 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable PDM module 0 0 Disabled Disable 0x0 Enabled Enable 0x1 PDMCLKCTRL PDM clock generator control 0x504 read-write 0x08400000 0x20 FREQ PDM_CLK frequency configuration 0 31 1000K PDM_CLK = 32 MHz / 32 = 1.000 MHz 0x08000000 Default PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. 0x08400000 1067K PDM_CLK = 32 MHz / 30 = 1.067 MHz 0x08800000 1231K PDM_CLK = 32 MHz / 26 = 1.231 MHz 0x09800000 1280K PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. 0x0A000000 1333K PDM_CLK = 32 MHz / 24 = 1.333 MHz 0x0A800000 MODE Defines the routing of the connected PDM microphones' signals 0x508 read-write 0x00000000 0x20 OPERATION Mono or stereo operation 0 0 Stereo Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] 0x0 Mono Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] 0x1 EDGE Defines on which PDM_CLK edge left (or mono) is sampled 1 1 LeftFalling Left (or mono) is sampled on falling edge of PDM_CLK 0x0 LeftRising Left (or mono) is sampled on rising edge of PDM_CLK 0x1 GAINL Left output gain adjustment 0x518 read-write 0x00000028 0x20 GAINL Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust 0 6 MinGain -20 dB gain adjustment (minimum) 0x00 DefaultGain 0 dB gain adjustment 0x28 MaxGain +20 dB gain adjustment (maximum) 0x50 GAINR Right output gain adjustment 0x51C read-write 0x00000028 0x20 GAINR Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0 6 MinGain -20 dB gain adjustment (minimum) 0x00 DefaultGain 0 dB gain adjustment 0x28 MaxGain +20 dB gain adjustment (maximum) 0x50 RATIO Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. 0x520 read-write 0x00000000 0x20 RATIO Selects the ratio between PDM_CLK and output sample rate 0 0 Ratio64 Ratio of 64 0x0 Ratio80 Ratio of 80 0x1 PSEL Unspecified PDM_PSEL read-write 0x540 CLK Pin number configuration for PDM CLK signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 DIN Pin number configuration for PDM DIN signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SAMPLE Unspecified PDM_SAMPLE read-write 0x560 PTR RAM address pointer to write samples to with EasyDMA 0x000 read-write 0x00000000 0x20 SAMPLEPTR Address to write PDM samples to over DMA 0 31 MAXCNT Number of samples to allocate memory for in EasyDMA mode 0x004 read-write 0x00000000 0x20 BUFFSIZE Length of DMA RAM allocation in number of samples 0 14 ACL Access control lists 0x4001E000 0 0x1000 registers ACL 0x20 8 0x010 ACL[%s] Unspecified ACL_ACL read-write 0x800 ADDR Description cluster: Start address of region to protect. The start address must be word-aligned. 0x000 read-writeonce 0x00000000 0x20 ADDR Start address of flash region n. The start address must point to a flash page boundary. 0 31 SIZE Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. 0x004 read-writeonce 0x00000000 0x20 SIZE Size of flash region n in bytes. Must be a multiple of the flash page size. 0 31 PERM Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE 0x008 read-writeonce 0x00000000 0x20 WRITE Configure write and erase permissions for region n. Writing a '0' has no effect. 1 1 Enable Allow write and erase instructions to region n. 0x0 Disable Block write and erase instructions to region n. 0x1 READ Configure read permissions for region n. Writing a '0' has no effect. 2 2 Enable Allow read instructions to region n. 0x0 Disable Block read instructions to region n. 0x1 NVMC Non Volatile Memory Controller 0x4001E000 ACL 0 0x1000 registers NVMC 0x20 READY Ready flag 0x400 read-only 0x00000001 0x20 READY NVMC is ready or busy 0 0 Busy NVMC is busy (on-going write or erase operation) 0x0 Ready NVMC is ready 0x1 READYNEXT Ready flag 0x408 read-only 0x00000001 0x20 READYNEXT NVMC can accept a new write operation 0 0 Busy NVMC cannot accept any write operation 0x0 Ready NVMC is ready 0x1 CONFIG Configuration register 0x504 read-write 0x00000000 0x20 WEN Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. 0 1 Ren Read only access 0x0 Wen Write enabled 0x1 Een Erase enabled 0x2 ERASEPAGE Register for erasing a page in code area 0x508 write-only 0x00000000 0x20 ERASEPAGE Register for starting erase of a page in code area 0 31 ERASEALL Register for erasing all non-volatile user memory 0x50C write-only 0x00000000 0x20 ERASEALL Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. 0 0 NoOperation No operation 0x0 Erase Start chip erase 0x1 ERASEUICR Register for erasing user information configuration registers 0x514 write-only 0x00000000 0x20 ERASEUICR Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. 0 0 NoOperation No operation 0x0 Erase Start erase of UICR 0x1 ERASEPAGEPARTIAL Register for partial erase of a page in code area 0x518 write-only 0x00000000 0x20 ERASEPAGEPARTIAL Register for starting partial erase of a page in code area 0 31 ERASEPAGEPARTIALCFG Register for partial erase configuration 0x51C read-write 0x0000000A 0x20 DURATION Duration of the partial erase in milliseconds 0 6 ICACHECNF I-code cache configuration register 0x540 read-write 0x00000000 0x20 CACHEEN Cache enable 0 0 Disabled Disable cache. Invalidates all cache entries. 0x0 Enabled Enable cache 0x1 CACHEPROFEN Cache profiling enable 8 8 Disabled Disable cache profiling 0x0 Enabled Enable cache profiling 0x1 IHIT I-code cache hit counter 0x548 read-write 0x00000000 0x20 HITS Number of cache hits. Register is writable, but only to '0'. 0 31 IMISS I-code cache miss counter 0x54C read-write 0x00000000 0x20 MISSES Number of cache misses. Register is writable, but only to '0'. 0 31 PPI Programmable Peripheral Interconnect 0x4001F000 0 0x1000 registers PPI 0x20 6 0x008 TASKS_CHG[%s] Channel group tasks PPI_TASKS_CHG write-only 0x000 EN Description cluster: Enable channel group n 0x000 write-only 0x00000000 0x20 EN Enable channel group n 0 0 Trigger Trigger task 0x1 DIS Description cluster: Disable channel group n 0x004 write-only 0x00000000 0x20 DIS Disable channel group n 0 0 Trigger Trigger task 0x1 CHEN Channel enable register 0x500 read-write 0x00000000 0x20 CH0 Enable or disable channel 0 0 0 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH1 Enable or disable channel 1 1 1 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH2 Enable or disable channel 2 2 2 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH3 Enable or disable channel 3 3 3 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH4 Enable or disable channel 4 4 4 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH5 Enable or disable channel 5 5 5 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH6 Enable or disable channel 6 6 6 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH7 Enable or disable channel 7 7 7 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH8 Enable or disable channel 8 8 8 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH9 Enable or disable channel 9 9 9 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH10 Enable or disable channel 10 10 10 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH11 Enable or disable channel 11 11 11 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH12 Enable or disable channel 12 12 12 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH13 Enable or disable channel 13 13 13 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH14 Enable or disable channel 14 14 14 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH15 Enable or disable channel 15 15 15 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH16 Enable or disable channel 16 16 16 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH17 Enable or disable channel 17 17 17 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH18 Enable or disable channel 18 18 18 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH19 Enable or disable channel 19 19 19 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH20 Enable or disable channel 20 20 20 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH21 Enable or disable channel 21 21 21 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH22 Enable or disable channel 22 22 22 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH23 Enable or disable channel 23 23 23 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH24 Enable or disable channel 24 24 24 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH25 Enable or disable channel 25 25 25 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH26 Enable or disable channel 26 26 26 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH27 Enable or disable channel 27 27 27 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH28 Enable or disable channel 28 28 28 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH29 Enable or disable channel 29 29 29 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH30 Enable or disable channel 30 30 30 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH31 Enable or disable channel 31 31 31 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CHENSET Channel enable set register 0x504 read-write 0x00000000 oneToSet 0x20 CH0 Channel 0 enable set register. Writing '0' has no effect. 0 0 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH1 Channel 1 enable set register. Writing '0' has no effect. 1 1 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH2 Channel 2 enable set register. Writing '0' has no effect. 2 2 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH3 Channel 3 enable set register. Writing '0' has no effect. 3 3 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH4 Channel 4 enable set register. Writing '0' has no effect. 4 4 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH5 Channel 5 enable set register. Writing '0' has no effect. 5 5 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH6 Channel 6 enable set register. Writing '0' has no effect. 6 6 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH7 Channel 7 enable set register. Writing '0' has no effect. 7 7 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH8 Channel 8 enable set register. Writing '0' has no effect. 8 8 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH9 Channel 9 enable set register. Writing '0' has no effect. 9 9 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH10 Channel 10 enable set register. Writing '0' has no effect. 10 10 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH11 Channel 11 enable set register. Writing '0' has no effect. 11 11 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH12 Channel 12 enable set register. Writing '0' has no effect. 12 12 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH13 Channel 13 enable set register. Writing '0' has no effect. 13 13 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH14 Channel 14 enable set register. Writing '0' has no effect. 14 14 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH15 Channel 15 enable set register. Writing '0' has no effect. 15 15 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH16 Channel 16 enable set register. Writing '0' has no effect. 16 16 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH17 Channel 17 enable set register. Writing '0' has no effect. 17 17 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH18 Channel 18 enable set register. Writing '0' has no effect. 18 18 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH19 Channel 19 enable set register. Writing '0' has no effect. 19 19 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH20 Channel 20 enable set register. Writing '0' has no effect. 20 20 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH21 Channel 21 enable set register. Writing '0' has no effect. 21 21 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH22 Channel 22 enable set register. Writing '0' has no effect. 22 22 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH23 Channel 23 enable set register. Writing '0' has no effect. 23 23 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH24 Channel 24 enable set register. Writing '0' has no effect. 24 24 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH25 Channel 25 enable set register. Writing '0' has no effect. 25 25 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH26 Channel 26 enable set register. Writing '0' has no effect. 26 26 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH27 Channel 27 enable set register. Writing '0' has no effect. 27 27 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH28 Channel 28 enable set register. Writing '0' has no effect. 28 28 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH29 Channel 29 enable set register. Writing '0' has no effect. 29 29 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH30 Channel 30 enable set register. Writing '0' has no effect. 30 30 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CH31 Channel 31 enable set register. Writing '0' has no effect. 31 31 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Set Write: Enable channel 0x1 CHENCLR Channel enable clear register 0x508 read-write 0x00000000 oneToClear 0x20 CH0 Channel 0 enable clear register. Writing '0' has no effect. 0 0 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH1 Channel 1 enable clear register. Writing '0' has no effect. 1 1 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH2 Channel 2 enable clear register. Writing '0' has no effect. 2 2 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH3 Channel 3 enable clear register. Writing '0' has no effect. 3 3 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH4 Channel 4 enable clear register. Writing '0' has no effect. 4 4 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH5 Channel 5 enable clear register. Writing '0' has no effect. 5 5 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH6 Channel 6 enable clear register. Writing '0' has no effect. 6 6 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH7 Channel 7 enable clear register. Writing '0' has no effect. 7 7 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH8 Channel 8 enable clear register. Writing '0' has no effect. 8 8 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH9 Channel 9 enable clear register. Writing '0' has no effect. 9 9 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH10 Channel 10 enable clear register. Writing '0' has no effect. 10 10 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH11 Channel 11 enable clear register. Writing '0' has no effect. 11 11 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH12 Channel 12 enable clear register. Writing '0' has no effect. 12 12 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH13 Channel 13 enable clear register. Writing '0' has no effect. 13 13 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH14 Channel 14 enable clear register. Writing '0' has no effect. 14 14 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH15 Channel 15 enable clear register. Writing '0' has no effect. 15 15 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH16 Channel 16 enable clear register. Writing '0' has no effect. 16 16 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH17 Channel 17 enable clear register. Writing '0' has no effect. 17 17 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH18 Channel 18 enable clear register. Writing '0' has no effect. 18 18 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH19 Channel 19 enable clear register. Writing '0' has no effect. 19 19 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH20 Channel 20 enable clear register. Writing '0' has no effect. 20 20 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH21 Channel 21 enable clear register. Writing '0' has no effect. 21 21 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH22 Channel 22 enable clear register. Writing '0' has no effect. 22 22 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH23 Channel 23 enable clear register. Writing '0' has no effect. 23 23 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH24 Channel 24 enable clear register. Writing '0' has no effect. 24 24 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH25 Channel 25 enable clear register. Writing '0' has no effect. 25 25 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH26 Channel 26 enable clear register. Writing '0' has no effect. 26 26 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH27 Channel 27 enable clear register. Writing '0' has no effect. 27 27 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH28 Channel 28 enable clear register. Writing '0' has no effect. 28 28 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH29 Channel 29 enable clear register. Writing '0' has no effect. 29 29 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH30 Channel 30 enable clear register. Writing '0' has no effect. 30 30 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 CH31 Channel 31 enable clear register. Writing '0' has no effect. 31 31 read Disabled Read: channel disabled 0x0 Enabled Read: channel enabled 0x1 write Clear Write: disable channel 0x1 20 0x008 CH[%s] PPI Channel PPI_CH read-write 0x510 EEP Description cluster: Channel n event endpoint 0x000 read-write 0x00000000 0x20 EEP Pointer to event register. Accepts only addresses to registers from the Event group. 0 31 TEP Description cluster: Channel n task endpoint 0x004 read-write 0x00000000 0x20 TEP Pointer to task register. Accepts only addresses to registers from the Task group. 0 31 0x6 0x4 CHG[%s] Description collection: Channel group n 0x800 read-write 0x00000000 0x20 CH0 Include or exclude channel 0 0 0 Excluded Exclude 0x0 Included Include 0x1 CH1 Include or exclude channel 1 1 1 Excluded Exclude 0x0 Included Include 0x1 CH2 Include or exclude channel 2 2 2 Excluded Exclude 0x0 Included Include 0x1 CH3 Include or exclude channel 3 3 3 Excluded Exclude 0x0 Included Include 0x1 CH4 Include or exclude channel 4 4 4 Excluded Exclude 0x0 Included Include 0x1 CH5 Include or exclude channel 5 5 5 Excluded Exclude 0x0 Included Include 0x1 CH6 Include or exclude channel 6 6 6 Excluded Exclude 0x0 Included Include 0x1 CH7 Include or exclude channel 7 7 7 Excluded Exclude 0x0 Included Include 0x1 CH8 Include or exclude channel 8 8 8 Excluded Exclude 0x0 Included Include 0x1 CH9 Include or exclude channel 9 9 9 Excluded Exclude 0x0 Included Include 0x1 CH10 Include or exclude channel 10 10 10 Excluded Exclude 0x0 Included Include 0x1 CH11 Include or exclude channel 11 11 11 Excluded Exclude 0x0 Included Include 0x1 CH12 Include or exclude channel 12 12 12 Excluded Exclude 0x0 Included Include 0x1 CH13 Include or exclude channel 13 13 13 Excluded Exclude 0x0 Included Include 0x1 CH14 Include or exclude channel 14 14 14 Excluded Exclude 0x0 Included Include 0x1 CH15 Include or exclude channel 15 15 15 Excluded Exclude 0x0 Included Include 0x1 CH16 Include or exclude channel 16 16 16 Excluded Exclude 0x0 Included Include 0x1 CH17 Include or exclude channel 17 17 17 Excluded Exclude 0x0 Included Include 0x1 CH18 Include or exclude channel 18 18 18 Excluded Exclude 0x0 Included Include 0x1 CH19 Include or exclude channel 19 19 19 Excluded Exclude 0x0 Included Include 0x1 CH20 Include or exclude channel 20 20 20 Excluded Exclude 0x0 Included Include 0x1 CH21 Include or exclude channel 21 21 21 Excluded Exclude 0x0 Included Include 0x1 CH22 Include or exclude channel 22 22 22 Excluded Exclude 0x0 Included Include 0x1 CH23 Include or exclude channel 23 23 23 Excluded Exclude 0x0 Included Include 0x1 CH24 Include or exclude channel 24 24 24 Excluded Exclude 0x0 Included Include 0x1 CH25 Include or exclude channel 25 25 25 Excluded Exclude 0x0 Included Include 0x1 CH26 Include or exclude channel 26 26 26 Excluded Exclude 0x0 Included Include 0x1 CH27 Include or exclude channel 27 27 27 Excluded Exclude 0x0 Included Include 0x1 CH28 Include or exclude channel 28 28 28 Excluded Exclude 0x0 Included Include 0x1 CH29 Include or exclude channel 29 29 29 Excluded Exclude 0x0 Included Include 0x1 CH30 Include or exclude channel 30 30 30 Excluded Exclude 0x0 Included Include 0x1 CH31 Include or exclude channel 31 31 31 Excluded Exclude 0x0 Included Include 0x1 32 0x004 FORK[%s] Fork PPI_FORK read-write 0x910 TEP Description cluster: Channel n task endpoint 0x000 read-write 0x00000000 0x20 TEP Pointer to task register 0 31 MWU Memory Watch Unit 0x40020000 0 0x1000 registers MWU 32 MWU 0x20 4 0x008 EVENTS_REGION[%s] Peripheral events. MWU_EVENTS_REGION read-write 0x100 WA Description cluster: Write access to region n detected 0x000 read-write 0x00000000 0x20 WA Write access to region n detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 RA Description cluster: Read access to region n detected 0x004 read-write 0x00000000 0x20 RA Read access to region n detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 2 0x008 EVENTS_PREGION[%s] Peripheral events. MWU_EVENTS_PREGION read-write 0x160 WA Description cluster: Write access to peripheral region n detected 0x000 read-write 0x00000000 0x20 WA Write access to peripheral region n detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 RA Description cluster: Read access to peripheral region n detected 0x004 read-write 0x00000000 0x20 RA Read access to peripheral region n detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 REGION0WA Enable or disable interrupt for event REGION0WA 0 0 Disabled Disable 0x0 Enabled Enable 0x1 REGION0RA Enable or disable interrupt for event REGION0RA 1 1 Disabled Disable 0x0 Enabled Enable 0x1 REGION1WA Enable or disable interrupt for event REGION1WA 2 2 Disabled Disable 0x0 Enabled Enable 0x1 REGION1RA Enable or disable interrupt for event REGION1RA 3 3 Disabled Disable 0x0 Enabled Enable 0x1 REGION2WA Enable or disable interrupt for event REGION2WA 4 4 Disabled Disable 0x0 Enabled Enable 0x1 REGION2RA Enable or disable interrupt for event REGION2RA 5 5 Disabled Disable 0x0 Enabled Enable 0x1 REGION3WA Enable or disable interrupt for event REGION3WA 6 6 Disabled Disable 0x0 Enabled Enable 0x1 REGION3RA Enable or disable interrupt for event REGION3RA 7 7 Disabled Disable 0x0 Enabled Enable 0x1 PREGION0WA Enable or disable interrupt for event PREGION0WA 24 24 Disabled Disable 0x0 Enabled Enable 0x1 PREGION0RA Enable or disable interrupt for event PREGION0RA 25 25 Disabled Disable 0x0 Enabled Enable 0x1 PREGION1WA Enable or disable interrupt for event PREGION1WA 26 26 Disabled Disable 0x0 Enabled Enable 0x1 PREGION1RA Enable or disable interrupt for event PREGION1RA 27 27 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 REGION0WA Write '1' to enable interrupt for event REGION0WA 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION0RA Write '1' to enable interrupt for event REGION0RA 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION1WA Write '1' to enable interrupt for event REGION1WA 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION1RA Write '1' to enable interrupt for event REGION1RA 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION2WA Write '1' to enable interrupt for event REGION2WA 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION2RA Write '1' to enable interrupt for event REGION2RA 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION3WA Write '1' to enable interrupt for event REGION3WA 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION3RA Write '1' to enable interrupt for event REGION3RA 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PREGION0WA Write '1' to enable interrupt for event PREGION0WA 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PREGION0RA Write '1' to enable interrupt for event PREGION0RA 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PREGION1WA Write '1' to enable interrupt for event PREGION1WA 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PREGION1RA Write '1' to enable interrupt for event PREGION1RA 27 27 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 REGION0WA Write '1' to disable interrupt for event REGION0WA 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION0RA Write '1' to disable interrupt for event REGION0RA 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION1WA Write '1' to disable interrupt for event REGION1WA 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION1RA Write '1' to disable interrupt for event REGION1RA 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION2WA Write '1' to disable interrupt for event REGION2WA 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION2RA Write '1' to disable interrupt for event REGION2RA 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION3WA Write '1' to disable interrupt for event REGION3WA 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION3RA Write '1' to disable interrupt for event REGION3RA 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PREGION0WA Write '1' to disable interrupt for event PREGION0WA 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PREGION0RA Write '1' to disable interrupt for event PREGION0RA 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PREGION1WA Write '1' to disable interrupt for event PREGION1WA 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PREGION1RA Write '1' to disable interrupt for event PREGION1RA 27 27 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 NMIEN Enable or disable interrupt 0x320 read-write 0x00000000 0x20 REGION0WA Enable or disable interrupt for event REGION0WA 0 0 Disabled Disable 0x0 Enabled Enable 0x1 REGION0RA Enable or disable interrupt for event REGION0RA 1 1 Disabled Disable 0x0 Enabled Enable 0x1 REGION1WA Enable or disable interrupt for event REGION1WA 2 2 Disabled Disable 0x0 Enabled Enable 0x1 REGION1RA Enable or disable interrupt for event REGION1RA 3 3 Disabled Disable 0x0 Enabled Enable 0x1 REGION2WA Enable or disable interrupt for event REGION2WA 4 4 Disabled Disable 0x0 Enabled Enable 0x1 REGION2RA Enable or disable interrupt for event REGION2RA 5 5 Disabled Disable 0x0 Enabled Enable 0x1 REGION3WA Enable or disable interrupt for event REGION3WA 6 6 Disabled Disable 0x0 Enabled Enable 0x1 REGION3RA Enable or disable interrupt for event REGION3RA 7 7 Disabled Disable 0x0 Enabled Enable 0x1 PREGION0WA Enable or disable interrupt for event PREGION0WA 24 24 Disabled Disable 0x0 Enabled Enable 0x1 PREGION0RA Enable or disable interrupt for event PREGION0RA 25 25 Disabled Disable 0x0 Enabled Enable 0x1 PREGION1WA Enable or disable interrupt for event PREGION1WA 26 26 Disabled Disable 0x0 Enabled Enable 0x1 PREGION1RA Enable or disable interrupt for event PREGION1RA 27 27 Disabled Disable 0x0 Enabled Enable 0x1 NMIENSET Enable interrupt 0x324 read-write 0x00000000 0x20 REGION0WA Write '1' to enable interrupt for event REGION0WA 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION0RA Write '1' to enable interrupt for event REGION0RA 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION1WA Write '1' to enable interrupt for event REGION1WA 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION1RA Write '1' to enable interrupt for event REGION1RA 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION2WA Write '1' to enable interrupt for event REGION2WA 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION2RA Write '1' to enable interrupt for event REGION2RA 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION3WA Write '1' to enable interrupt for event REGION3WA 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REGION3RA Write '1' to enable interrupt for event REGION3RA 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PREGION0WA Write '1' to enable interrupt for event PREGION0WA 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PREGION0RA Write '1' to enable interrupt for event PREGION0RA 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PREGION1WA Write '1' to enable interrupt for event PREGION1WA 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PREGION1RA Write '1' to enable interrupt for event PREGION1RA 27 27 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 NMIENCLR Disable interrupt 0x328 read-write 0x00000000 0x20 REGION0WA Write '1' to disable interrupt for event REGION0WA 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION0RA Write '1' to disable interrupt for event REGION0RA 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION1WA Write '1' to disable interrupt for event REGION1WA 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION1RA Write '1' to disable interrupt for event REGION1RA 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION2WA Write '1' to disable interrupt for event REGION2WA 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION2RA Write '1' to disable interrupt for event REGION2RA 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION3WA Write '1' to disable interrupt for event REGION3WA 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REGION3RA Write '1' to disable interrupt for event REGION3RA 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PREGION0WA Write '1' to disable interrupt for event PREGION0WA 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PREGION0RA Write '1' to disable interrupt for event PREGION0RA 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PREGION1WA Write '1' to disable interrupt for event PREGION1WA 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PREGION1RA Write '1' to disable interrupt for event PREGION1RA 27 27 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 2 0x008 PERREGION[%s] Unspecified MWU_PERREGION read-write 0x400 SUBSTATWA Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching 0x000 read-write 0x00000000 oneToClear 0x20 SR0 Subregion 0 in region n (write '1' to clear) 0 0 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR1 Subregion 1 in region n (write '1' to clear) 1 1 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR2 Subregion 2 in region n (write '1' to clear) 2 2 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR3 Subregion 3 in region n (write '1' to clear) 3 3 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR4 Subregion 4 in region n (write '1' to clear) 4 4 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR5 Subregion 5 in region n (write '1' to clear) 5 5 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR6 Subregion 6 in region n (write '1' to clear) 6 6 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR7 Subregion 7 in region n (write '1' to clear) 7 7 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR8 Subregion 8 in region n (write '1' to clear) 8 8 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR9 Subregion 9 in region n (write '1' to clear) 9 9 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR10 Subregion 10 in region n (write '1' to clear) 10 10 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR11 Subregion 11 in region n (write '1' to clear) 11 11 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR12 Subregion 12 in region n (write '1' to clear) 12 12 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR13 Subregion 13 in region n (write '1' to clear) 13 13 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR14 Subregion 14 in region n (write '1' to clear) 14 14 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR15 Subregion 15 in region n (write '1' to clear) 15 15 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR16 Subregion 16 in region n (write '1' to clear) 16 16 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR17 Subregion 17 in region n (write '1' to clear) 17 17 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR18 Subregion 18 in region n (write '1' to clear) 18 18 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR19 Subregion 19 in region n (write '1' to clear) 19 19 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR20 Subregion 20 in region n (write '1' to clear) 20 20 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR21 Subregion 21 in region n (write '1' to clear) 21 21 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR22 Subregion 22 in region n (write '1' to clear) 22 22 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR23 Subregion 23 in region n (write '1' to clear) 23 23 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR24 Subregion 24 in region n (write '1' to clear) 24 24 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR25 Subregion 25 in region n (write '1' to clear) 25 25 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR26 Subregion 26 in region n (write '1' to clear) 26 26 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR27 Subregion 27 in region n (write '1' to clear) 27 27 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR28 Subregion 28 in region n (write '1' to clear) 28 28 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR29 Subregion 29 in region n (write '1' to clear) 29 29 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR30 Subregion 30 in region n (write '1' to clear) 30 30 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SR31 Subregion 31 in region n (write '1' to clear) 31 31 NoAccess No write access occurred in this subregion 0x0 Access Write access(es) occurred in this subregion 0x1 SUBSTATRA Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching 0x004 read-write 0x00000000 oneToClear 0x20 SR0 Subregion 0 in region n (write '1' to clear) 0 0 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR1 Subregion 1 in region n (write '1' to clear) 1 1 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR2 Subregion 2 in region n (write '1' to clear) 2 2 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR3 Subregion 3 in region n (write '1' to clear) 3 3 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR4 Subregion 4 in region n (write '1' to clear) 4 4 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR5 Subregion 5 in region n (write '1' to clear) 5 5 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR6 Subregion 6 in region n (write '1' to clear) 6 6 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR7 Subregion 7 in region n (write '1' to clear) 7 7 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR8 Subregion 8 in region n (write '1' to clear) 8 8 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR9 Subregion 9 in region n (write '1' to clear) 9 9 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR10 Subregion 10 in region n (write '1' to clear) 10 10 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR11 Subregion 11 in region n (write '1' to clear) 11 11 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR12 Subregion 12 in region n (write '1' to clear) 12 12 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR13 Subregion 13 in region n (write '1' to clear) 13 13 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR14 Subregion 14 in region n (write '1' to clear) 14 14 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR15 Subregion 15 in region n (write '1' to clear) 15 15 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR16 Subregion 16 in region n (write '1' to clear) 16 16 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR17 Subregion 17 in region n (write '1' to clear) 17 17 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR18 Subregion 18 in region n (write '1' to clear) 18 18 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR19 Subregion 19 in region n (write '1' to clear) 19 19 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR20 Subregion 20 in region n (write '1' to clear) 20 20 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR21 Subregion 21 in region n (write '1' to clear) 21 21 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR22 Subregion 22 in region n (write '1' to clear) 22 22 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR23 Subregion 23 in region n (write '1' to clear) 23 23 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR24 Subregion 24 in region n (write '1' to clear) 24 24 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR25 Subregion 25 in region n (write '1' to clear) 25 25 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR26 Subregion 26 in region n (write '1' to clear) 26 26 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR27 Subregion 27 in region n (write '1' to clear) 27 27 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR28 Subregion 28 in region n (write '1' to clear) 28 28 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR29 Subregion 29 in region n (write '1' to clear) 29 29 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR30 Subregion 30 in region n (write '1' to clear) 30 30 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 SR31 Subregion 31 in region n (write '1' to clear) 31 31 NoAccess No read access occurred in this subregion 0x0 Access Read access(es) occurred in this subregion 0x1 REGIONEN Enable/disable regions watch 0x510 read-write 0x00000000 0x20 RGN0WA Enable/disable write access watch in region[0] 0 0 Disable Disable write access watch in this region 0x0 Enable Enable write access watch in this region 0x1 RGN0RA Enable/disable read access watch in region[0] 1 1 Disable Disable read access watch in this region 0x0 Enable Enable read access watch in this region 0x1 RGN1WA Enable/disable write access watch in region[1] 2 2 Disable Disable write access watch in this region 0x0 Enable Enable write access watch in this region 0x1 RGN1RA Enable/disable read access watch in region[1] 3 3 Disable Disable read access watch in this region 0x0 Enable Enable read access watch in this region 0x1 RGN2WA Enable/disable write access watch in region[2] 4 4 Disable Disable write access watch in this region 0x0 Enable Enable write access watch in this region 0x1 RGN2RA Enable/disable read access watch in region[2] 5 5 Disable Disable read access watch in this region 0x0 Enable Enable read access watch in this region 0x1 RGN3WA Enable/disable write access watch in region[3] 6 6 Disable Disable write access watch in this region 0x0 Enable Enable write access watch in this region 0x1 RGN3RA Enable/disable read access watch in region[3] 7 7 Disable Disable read access watch in this region 0x0 Enable Enable read access watch in this region 0x1 PRGN0WA Enable/disable write access watch in PREGION[0] 24 24 Disable Disable write access watch in this PREGION 0x0 Enable Enable write access watch in this PREGION 0x1 PRGN0RA Enable/disable read access watch in PREGION[0] 25 25 Disable Disable read access watch in this PREGION 0x0 Enable Enable read access watch in this PREGION 0x1 PRGN1WA Enable/disable write access watch in PREGION[1] 26 26 Disable Disable write access watch in this PREGION 0x0 Enable Enable write access watch in this PREGION 0x1 PRGN1RA Enable/disable read access watch in PREGION[1] 27 27 Disable Disable read access watch in this PREGION 0x0 Enable Enable read access watch in this PREGION 0x1 REGIONENSET Enable regions watch 0x514 read-write 0x00000000 0x20 RGN0WA Enable write access watch in region[0] 0 0 read Disabled Write access watch in this region is disabled 0x0 Enabled Write access watch in this region is enabled 0x1 write Set Enable write access watch in this region 0x1 RGN0RA Enable read access watch in region[0] 1 1 read Disabled Read access watch in this region is disabled 0x0 Enabled Read access watch in this region is enabled 0x1 write Set Enable read access watch in this region 0x1 RGN1WA Enable write access watch in region[1] 2 2 read Disabled Write access watch in this region is disabled 0x0 Enabled Write access watch in this region is enabled 0x1 write Set Enable write access watch in this region 0x1 RGN1RA Enable read access watch in region[1] 3 3 read Disabled Read access watch in this region is disabled 0x0 Enabled Read access watch in this region is enabled 0x1 write Set Enable read access watch in this region 0x1 RGN2WA Enable write access watch in region[2] 4 4 read Disabled Write access watch in this region is disabled 0x0 Enabled Write access watch in this region is enabled 0x1 write Set Enable write access watch in this region 0x1 RGN2RA Enable read access watch in region[2] 5 5 read Disabled Read access watch in this region is disabled 0x0 Enabled Read access watch in this region is enabled 0x1 write Set Enable read access watch in this region 0x1 RGN3WA Enable write access watch in region[3] 6 6 read Disabled Write access watch in this region is disabled 0x0 Enabled Write access watch in this region is enabled 0x1 write Set Enable write access watch in this region 0x1 RGN3RA Enable read access watch in region[3] 7 7 read Disabled Read access watch in this region is disabled 0x0 Enabled Read access watch in this region is enabled 0x1 write Set Enable read access watch in this region 0x1 PRGN0WA Enable write access watch in PREGION[0] 24 24 read Disabled Write access watch in this PREGION is disabled 0x0 Enabled Write access watch in this PREGION is enabled 0x1 write Set Enable write access watch in this PREGION 0x1 PRGN0RA Enable read access watch in PREGION[0] 25 25 read Disabled Read access watch in this PREGION is disabled 0x0 Enabled Read access watch in this PREGION is enabled 0x1 write Set Enable read access watch in this PREGION 0x1 PRGN1WA Enable write access watch in PREGION[1] 26 26 read Disabled Write access watch in this PREGION is disabled 0x0 Enabled Write access watch in this PREGION is enabled 0x1 write Set Enable write access watch in this PREGION 0x1 PRGN1RA Enable read access watch in PREGION[1] 27 27 read Disabled Read access watch in this PREGION is disabled 0x0 Enabled Read access watch in this PREGION is enabled 0x1 write Set Enable read access watch in this PREGION 0x1 REGIONENCLR Disable regions watch 0x518 read-write 0x00000000 0x20 RGN0WA Disable write access watch in region[0] 0 0 read Disabled Write access watch in this region is disabled 0x0 Enabled Write access watch in this region is enabled 0x1 write Clear Disable write access watch in this region 0x1 RGN0RA Disable read access watch in region[0] 1 1 read Disabled Read access watch in this region is disabled 0x0 Enabled Read access watch in this region is enabled 0x1 write Clear Disable read access watch in this region 0x1 RGN1WA Disable write access watch in region[1] 2 2 read Disabled Write access watch in this region is disabled 0x0 Enabled Write access watch in this region is enabled 0x1 write Clear Disable write access watch in this region 0x1 RGN1RA Disable read access watch in region[1] 3 3 read Disabled Read access watch in this region is disabled 0x0 Enabled Read access watch in this region is enabled 0x1 write Clear Disable read access watch in this region 0x1 RGN2WA Disable write access watch in region[2] 4 4 read Disabled Write access watch in this region is disabled 0x0 Enabled Write access watch in this region is enabled 0x1 write Clear Disable write access watch in this region 0x1 RGN2RA Disable read access watch in region[2] 5 5 read Disabled Read access watch in this region is disabled 0x0 Enabled Read access watch in this region is enabled 0x1 write Clear Disable read access watch in this region 0x1 RGN3WA Disable write access watch in region[3] 6 6 read Disabled Write access watch in this region is disabled 0x0 Enabled Write access watch in this region is enabled 0x1 write Clear Disable write access watch in this region 0x1 RGN3RA Disable read access watch in region[3] 7 7 read Disabled Read access watch in this region is disabled 0x0 Enabled Read access watch in this region is enabled 0x1 write Clear Disable read access watch in this region 0x1 PRGN0WA Disable write access watch in PREGION[0] 24 24 read Disabled Write access watch in this PREGION is disabled 0x0 Enabled Write access watch in this PREGION is enabled 0x1 write Clear Disable write access watch in this PREGION 0x1 PRGN0RA Disable read access watch in PREGION[0] 25 25 read Disabled Read access watch in this PREGION is disabled 0x0 Enabled Read access watch in this PREGION is enabled 0x1 write Clear Disable read access watch in this PREGION 0x1 PRGN1WA Disable write access watch in PREGION[1] 26 26 read Disabled Write access watch in this PREGION is disabled 0x0 Enabled Write access watch in this PREGION is enabled 0x1 write Clear Disable write access watch in this PREGION 0x1 PRGN1RA Disable read access watch in PREGION[1] 27 27 read Disabled Read access watch in this PREGION is disabled 0x0 Enabled Read access watch in this PREGION is enabled 0x1 write Clear Disable read access watch in this PREGION 0x1 4 0x010 REGION[%s] Unspecified MWU_REGION read-write 0x600 START Description cluster: Start address for region n 0x000 read-write 0x00000000 0x20 START Start address for region 0 31 END Description cluster: End address of region n 0x004 read-write 0x00000000 0x20 END End address of region. 0 31 2 0x010 PREGION[%s] Unspecified MWU_PREGION read-write 0x6C0 START Description cluster: Reserved for future use 0x000 read-only 0x00000000 0x20 START Reserved for future use 0 31 END Description cluster: Reserved for future use 0x004 read-only 0x00000000 0x20 END Reserved for future use 0 31 SUBS Description cluster: Subregions of region n 0x008 read-write 0x00000000 0x20 SR0 Include or exclude subregion 0 in region 0 0 Exclude Exclude 0x0 Include Include 0x1 SR1 Include or exclude subregion 1 in region 1 1 Exclude Exclude 0x0 Include Include 0x1 SR2 Include or exclude subregion 2 in region 2 2 Exclude Exclude 0x0 Include Include 0x1 SR3 Include or exclude subregion 3 in region 3 3 Exclude Exclude 0x0 Include Include 0x1 SR4 Include or exclude subregion 4 in region 4 4 Exclude Exclude 0x0 Include Include 0x1 SR5 Include or exclude subregion 5 in region 5 5 Exclude Exclude 0x0 Include Include 0x1 SR6 Include or exclude subregion 6 in region 6 6 Exclude Exclude 0x0 Include Include 0x1 SR7 Include or exclude subregion 7 in region 7 7 Exclude Exclude 0x0 Include Include 0x1 SR8 Include or exclude subregion 8 in region 8 8 Exclude Exclude 0x0 Include Include 0x1 SR9 Include or exclude subregion 9 in region 9 9 Exclude Exclude 0x0 Include Include 0x1 SR10 Include or exclude subregion 10 in region 10 10 Exclude Exclude 0x0 Include Include 0x1 SR11 Include or exclude subregion 11 in region 11 11 Exclude Exclude 0x0 Include Include 0x1 SR12 Include or exclude subregion 12 in region 12 12 Exclude Exclude 0x0 Include Include 0x1 SR13 Include or exclude subregion 13 in region 13 13 Exclude Exclude 0x0 Include Include 0x1 SR14 Include or exclude subregion 14 in region 14 14 Exclude Exclude 0x0 Include Include 0x1 SR15 Include or exclude subregion 15 in region 15 15 Exclude Exclude 0x0 Include Include 0x1 SR16 Include or exclude subregion 16 in region 16 16 Exclude Exclude 0x0 Include Include 0x1 SR17 Include or exclude subregion 17 in region 17 17 Exclude Exclude 0x0 Include Include 0x1 SR18 Include or exclude subregion 18 in region 18 18 Exclude Exclude 0x0 Include Include 0x1 SR19 Include or exclude subregion 19 in region 19 19 Exclude Exclude 0x0 Include Include 0x1 SR20 Include or exclude subregion 20 in region 20 20 Exclude Exclude 0x0 Include Include 0x1 SR21 Include or exclude subregion 21 in region 21 21 Exclude Exclude 0x0 Include Include 0x1 SR22 Include or exclude subregion 22 in region 22 22 Exclude Exclude 0x0 Include Include 0x1 SR23 Include or exclude subregion 23 in region 23 23 Exclude Exclude 0x0 Include Include 0x1 SR24 Include or exclude subregion 24 in region 24 24 Exclude Exclude 0x0 Include Include 0x1 SR25 Include or exclude subregion 25 in region 25 25 Exclude Exclude 0x0 Include Include 0x1 SR26 Include or exclude subregion 26 in region 26 26 Exclude Exclude 0x0 Include Include 0x1 SR27 Include or exclude subregion 27 in region 27 27 Exclude Exclude 0x0 Include Include 0x1 SR28 Include or exclude subregion 28 in region 28 28 Exclude Exclude 0x0 Include Include 0x1 SR29 Include or exclude subregion 29 in region 29 29 Exclude Exclude 0x0 Include Include 0x1 SR30 Include or exclude subregion 30 in region 30 30 Exclude Exclude 0x0 Include Include 0x1 SR31 Include or exclude subregion 31 in region 31 31 Exclude Exclude 0x0 Include Include 0x1 PWM1 Pulse width modulation unit 1 0x40021000 PWM1 33 PWM2 Pulse width modulation unit 2 0x40022000 PWM2 34 SPI2 Serial Peripheral Interface 2 0x40023000 SPI2_SPIM2_SPIS2 35 SPIM2 Serial Peripheral Interface Master with EasyDMA 2 0x40023000 SPI2 SPI2_SPIM2_SPIS2 35 SPIS2 SPI Slave 2 0x40023000 SPI2 SPI2_SPIM2_SPIS2 35 RTC2 Real time counter 2 0x40024000 RTC2 36 I2S Inter-IC Sound 0x40025000 0 0x1000 registers I2S 37 I2S 0x20 TASKS_START Starts continuous I2S transfer. Also starts MCK generator when this is enabled. 0x000 write-only 0x00000000 0x20 TASKS_START Starts continuous I2S transfer. Also starts MCK generator when this is enabled. 0 0 Trigger Trigger task 0x1 TASKS_STOP Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. 0x004 write-only 0x00000000 0x20 TASKS_STOP Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. 0 0 Trigger Trigger task 0x1 EVENTS_RXPTRUPD The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 0x104 read-write 0x00000000 0x20 EVENTS_RXPTRUPD The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED I2S transfer stopped. 0x108 read-write 0x00000000 0x20 EVENTS_STOPPED I2S transfer stopped. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXPTRUPD The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0x114 read-write 0x00000000 0x20 EVENTS_TXPTRUPD The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 RXPTRUPD Enable or disable interrupt for event RXPTRUPD 1 1 Disabled Disable 0x0 Enabled Enable 0x1 STOPPED Enable or disable interrupt for event STOPPED 2 2 Disabled Disable 0x0 Enabled Enable 0x1 TXPTRUPD Enable or disable interrupt for event TXPTRUPD 5 5 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 RXPTRUPD Write '1' to enable interrupt for event RXPTRUPD 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXPTRUPD Write '1' to enable interrupt for event TXPTRUPD 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 RXPTRUPD Write '1' to disable interrupt for event RXPTRUPD 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXPTRUPD Write '1' to disable interrupt for event TXPTRUPD 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE Enable I2S module. 0x500 read-write 0x00000000 0x20 ENABLE Enable I2S module. 0 0 Disabled Disable 0x0 Enabled Enable 0x1 CONFIG Unspecified I2S_CONFIG read-write 0x504 MODE I2S mode. 0x000 read-write 0x00000000 0x20 MODE I2S mode. 0 0 Master Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. 0x0 Slave Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx 0x1 RXEN Reception (RX) enable. 0x004 read-write 0x00000000 0x20 RXEN Reception (RX) enable. 0 0 Disabled Reception disabled and now data will be written to the RXD.PTR address. 0x0 Enabled Reception enabled. 0x1 TXEN Transmission (TX) enable. 0x008 read-write 0x00000001 0x20 TXEN Transmission (TX) enable. 0 0 Disabled Transmission disabled and now data will be read from the RXD.TXD address. 0x0 Enabled Transmission enabled. 0x1 MCKEN Master clock generator enable. 0x00C read-write 0x00000001 0x20 MCKEN Master clock generator enable. 0 0 Disabled Master clock generator disabled and PSEL.MCK not connected(available as GPIO). 0x0 Enabled Master clock generator running and MCK output on PSEL.MCK. 0x1 MCKFREQ Master clock generator frequency. 0x010 read-write 0x20000000 0x20 MCKFREQ Master clock generator frequency. 0 31 32MDIV8 32 MHz / 8 = 4.0 MHz 0x20000000 32MDIV10 32 MHz / 10 = 3.2 MHz 0x18000000 32MDIV11 32 MHz / 11 = 2.9090909 MHz 0x16000000 32MDIV15 32 MHz / 15 = 2.1333333 MHz 0x11000000 32MDIV16 32 MHz / 16 = 2.0 MHz 0x10000000 32MDIV21 32 MHz / 21 = 1.5238095 0x0C000000 32MDIV23 32 MHz / 23 = 1.3913043 MHz 0x0B000000 32MDIV30 32 MHz / 30 = 1.0666667 MHz 0x08800000 32MDIV31 32 MHz / 31 = 1.0322581 MHz 0x08400000 32MDIV32 32 MHz / 32 = 1.0 MHz 0x08000000 32MDIV42 32 MHz / 42 = 0.7619048 MHz 0x06000000 32MDIV63 32 MHz / 63 = 0.5079365 MHz 0x04100000 32MDIV125 32 MHz / 125 = 0.256 MHz 0x020C0000 RATIO MCK / LRCK ratio. 0x014 read-write 0x00000006 0x20 RATIO MCK / LRCK ratio. 0 3 32X LRCK = MCK / 32 0x0 48X LRCK = MCK / 48 0x1 64X LRCK = MCK / 64 0x2 96X LRCK = MCK / 96 0x3 128X LRCK = MCK / 128 0x4 192X LRCK = MCK / 192 0x5 256X LRCK = MCK / 256 0x6 384X LRCK = MCK / 384 0x7 512X LRCK = MCK / 512 0x8 SWIDTH Sample width. 0x018 read-write 0x00000001 0x20 SWIDTH Sample width. 0 1 8Bit 8 bit. 0x0 16Bit 16 bit. 0x1 24Bit 24 bit. 0x2 ALIGN Alignment of sample within a frame. 0x01C read-write 0x00000000 0x20 ALIGN Alignment of sample within a frame. 0 0 Left Left-aligned. 0x0 Right Right-aligned. 0x1 FORMAT Frame format. 0x020 read-write 0x00000000 0x20 FORMAT Frame format. 0 0 I2S Original I2S format. 0x0 Aligned Alternate (left- or right-aligned) format. 0x1 CHANNELS Enable channels. 0x024 read-write 0x00000000 0x20 CHANNELS Enable channels. 0 1 Stereo Stereo. 0x0 Left Left only. 0x1 Right Right only. 0x2 RXD Unspecified I2S_RXD read-write 0x538 PTR Receive buffer RAM start address. 0x000 read-write 0x00000000 0x20 PTR Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. 0 31 TXD Unspecified I2S_TXD read-write 0x540 PTR Transmit buffer RAM start address. 0x000 read-write 0x00000000 0x20 PTR Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. 0 31 RXTXD Unspecified I2S_RXTXD read-write 0x550 MAXCNT Size of RXD and TXD buffers. 0x000 read-write 0x00000000 0x20 MAXCNT Size of RXD and TXD buffers in number of 32 bit words. 0 13 PSEL Unspecified I2S_PSEL read-write 0x560 MCK Pin select for MCK signal. 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SCK Pin select for SCK signal. 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 LRCK Pin select for LRCK signal. 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDIN Pin select for SDIN signal. 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDOUT Pin select for SDOUT signal. 0x010 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 FPU FPU 0x40026000 0 0x1000 registers FPU 38 FPU 0x20 UNUSED Unused. 0x000 0x00000000 read-only USBD Universal serial bus device 0x40027000 0 0x1000 registers USBD 39 USBD 0x20 0x8 0x4 TASKS_STARTEPIN[%s] Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host 0x004 write-only 0x00000000 0x20 TASKS_STARTEPIN Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host 0 0 Trigger Trigger task 0x1 TASKS_STARTISOIN Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint 0x024 write-only 0x00000000 0x20 TASKS_STARTISOIN Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint 0 0 Trigger Trigger task 0x1 0x8 0x4 TASKS_STARTEPOUT[%s] Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host 0x028 write-only 0x00000000 0x20 TASKS_STARTEPOUT Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host 0 0 Trigger Trigger task 0x1 TASKS_STARTISOOUT Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint 0x048 write-only 0x00000000 0x20 TASKS_STARTISOOUT Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint 0 0 Trigger Trigger task 0x1 TASKS_EP0RCVOUT Allows OUT data stage on control endpoint 0 0x04C write-only 0x00000000 0x20 TASKS_EP0RCVOUT Allows OUT data stage on control endpoint 0 0 0 Trigger Trigger task 0x1 TASKS_EP0STATUS Allows status stage on control endpoint 0 0x050 write-only 0x00000000 0x20 TASKS_EP0STATUS Allows status stage on control endpoint 0 0 0 Trigger Trigger task 0x1 TASKS_EP0STALL Stalls data and status stage on control endpoint 0 0x054 write-only 0x00000000 0x20 TASKS_EP0STALL Stalls data and status stage on control endpoint 0 0 0 Trigger Trigger task 0x1 TASKS_DPDMDRIVE Forces D+ and D- lines into the state defined in the DPDMVALUE register 0x058 write-only 0x00000000 0x20 TASKS_DPDMDRIVE Forces D+ and D- lines into the state defined in the DPDMVALUE register 0 0 Trigger Trigger task 0x1 TASKS_DPDMNODRIVE Stops forcing D+ and D- lines into any state (USB engine takes control) 0x05C write-only 0x00000000 0x20 TASKS_DPDMNODRIVE Stops forcing D+ and D- lines into any state (USB engine takes control) 0 0 Trigger Trigger task 0x1 EVENTS_USBRESET Signals that a USB reset condition has been detected on USB lines 0x100 read-write 0x00000000 0x20 EVENTS_USBRESET Signals that a USB reset condition has been detected on USB lines 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STARTED Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register 0x104 read-write 0x00000000 0x20 EVENTS_STARTED Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x8 0x4 EVENTS_ENDEPIN[%s] Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. 0x108 read-write 0x00000000 0x20 EVENTS_ENDEPIN The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_EP0DATADONE An acknowledged data transfer has taken place on the control endpoint 0x128 read-write 0x00000000 0x20 EVENTS_EP0DATADONE An acknowledged data transfer has taken place on the control endpoint 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDISOIN The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. 0x12C read-write 0x00000000 0x20 EVENTS_ENDISOIN The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x8 0x4 EVENTS_ENDEPOUT[%s] Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. 0x130 read-write 0x00000000 0x20 EVENTS_ENDEPOUT The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDISOOUT The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. 0x150 read-write 0x00000000 0x20 EVENTS_ENDISOOUT The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SOF Signals that a SOF (start of frame) condition has been detected on USB lines 0x154 read-write 0x00000000 0x20 EVENTS_SOF Signals that a SOF (start of frame) condition has been detected on USB lines 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_USBEVENT An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. 0x158 read-write 0x00000000 0x20 EVENTS_USBEVENT An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_EP0SETUP A valid SETUP token has been received (and acknowledged) on the control endpoint 0x15C read-write 0x00000000 0x20 EVENTS_EP0SETUP A valid SETUP token has been received (and acknowledged) on the control endpoint 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_EPDATA A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register 0x160 read-write 0x00000000 0x20 EVENTS_EPDATA A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 EP0DATADONE_STARTEPIN0 Shortcut between event EP0DATADONE and task STARTEPIN[0] 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 EP0DATADONE_STARTEPOUT0 Shortcut between event EP0DATADONE and task STARTEPOUT[0] 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 EP0DATADONE_EP0STATUS Shortcut between event EP0DATADONE and task EP0STATUS 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 ENDEPOUT0_EP0STATUS Shortcut between event ENDEPOUT[0] and task EP0STATUS 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 ENDEPOUT0_EP0RCVOUT Shortcut between event ENDEPOUT[0] and task EP0RCVOUT 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 USBRESET Enable or disable interrupt for event USBRESET 0 0 Disabled Disable 0x0 Enabled Enable 0x1 STARTED Enable or disable interrupt for event STARTED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPIN0 Enable or disable interrupt for event ENDEPIN[0] 2 2 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPIN1 Enable or disable interrupt for event ENDEPIN[1] 3 3 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPIN2 Enable or disable interrupt for event ENDEPIN[2] 4 4 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPIN3 Enable or disable interrupt for event ENDEPIN[3] 5 5 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPIN4 Enable or disable interrupt for event ENDEPIN[4] 6 6 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPIN5 Enable or disable interrupt for event ENDEPIN[5] 7 7 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPIN6 Enable or disable interrupt for event ENDEPIN[6] 8 8 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPIN7 Enable or disable interrupt for event ENDEPIN[7] 9 9 Disabled Disable 0x0 Enabled Enable 0x1 EP0DATADONE Enable or disable interrupt for event EP0DATADONE 10 10 Disabled Disable 0x0 Enabled Enable 0x1 ENDISOIN Enable or disable interrupt for event ENDISOIN 11 11 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPOUT0 Enable or disable interrupt for event ENDEPOUT[0] 12 12 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPOUT1 Enable or disable interrupt for event ENDEPOUT[1] 13 13 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPOUT2 Enable or disable interrupt for event ENDEPOUT[2] 14 14 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPOUT3 Enable or disable interrupt for event ENDEPOUT[3] 15 15 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPOUT4 Enable or disable interrupt for event ENDEPOUT[4] 16 16 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPOUT5 Enable or disable interrupt for event ENDEPOUT[5] 17 17 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPOUT6 Enable or disable interrupt for event ENDEPOUT[6] 18 18 Disabled Disable 0x0 Enabled Enable 0x1 ENDEPOUT7 Enable or disable interrupt for event ENDEPOUT[7] 19 19 Disabled Disable 0x0 Enabled Enable 0x1 ENDISOOUT Enable or disable interrupt for event ENDISOOUT 20 20 Disabled Disable 0x0 Enabled Enable 0x1 SOF Enable or disable interrupt for event SOF 21 21 Disabled Disable 0x0 Enabled Enable 0x1 USBEVENT Enable or disable interrupt for event USBEVENT 22 22 Disabled Disable 0x0 Enabled Enable 0x1 EP0SETUP Enable or disable interrupt for event EP0SETUP 23 23 Disabled Disable 0x0 Enabled Enable 0x1 EPDATA Enable or disable interrupt for event EPDATA 24 24 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 USBRESET Write '1' to enable interrupt for event USBRESET 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STARTED Write '1' to enable interrupt for event STARTED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPIN0 Write '1' to enable interrupt for event ENDEPIN[0] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPIN1 Write '1' to enable interrupt for event ENDEPIN[1] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPIN2 Write '1' to enable interrupt for event ENDEPIN[2] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPIN3 Write '1' to enable interrupt for event ENDEPIN[3] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPIN4 Write '1' to enable interrupt for event ENDEPIN[4] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPIN5 Write '1' to enable interrupt for event ENDEPIN[5] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPIN6 Write '1' to enable interrupt for event ENDEPIN[6] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPIN7 Write '1' to enable interrupt for event ENDEPIN[7] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 EP0DATADONE Write '1' to enable interrupt for event EP0DATADONE 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDISOIN Write '1' to enable interrupt for event ENDISOIN 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPOUT0 Write '1' to enable interrupt for event ENDEPOUT[0] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPOUT1 Write '1' to enable interrupt for event ENDEPOUT[1] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPOUT2 Write '1' to enable interrupt for event ENDEPOUT[2] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPOUT3 Write '1' to enable interrupt for event ENDEPOUT[3] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPOUT4 Write '1' to enable interrupt for event ENDEPOUT[4] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPOUT5 Write '1' to enable interrupt for event ENDEPOUT[5] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPOUT6 Write '1' to enable interrupt for event ENDEPOUT[6] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDEPOUT7 Write '1' to enable interrupt for event ENDEPOUT[7] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDISOOUT Write '1' to enable interrupt for event ENDISOOUT 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SOF Write '1' to enable interrupt for event SOF 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 USBEVENT Write '1' to enable interrupt for event USBEVENT 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 EP0SETUP Write '1' to enable interrupt for event EP0SETUP 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 EPDATA Write '1' to enable interrupt for event EPDATA 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 USBRESET Write '1' to disable interrupt for event USBRESET 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STARTED Write '1' to disable interrupt for event STARTED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPIN0 Write '1' to disable interrupt for event ENDEPIN[0] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPIN1 Write '1' to disable interrupt for event ENDEPIN[1] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPIN2 Write '1' to disable interrupt for event ENDEPIN[2] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPIN3 Write '1' to disable interrupt for event ENDEPIN[3] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPIN4 Write '1' to disable interrupt for event ENDEPIN[4] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPIN5 Write '1' to disable interrupt for event ENDEPIN[5] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPIN6 Write '1' to disable interrupt for event ENDEPIN[6] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPIN7 Write '1' to disable interrupt for event ENDEPIN[7] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 EP0DATADONE Write '1' to disable interrupt for event EP0DATADONE 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDISOIN Write '1' to disable interrupt for event ENDISOIN 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPOUT0 Write '1' to disable interrupt for event ENDEPOUT[0] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPOUT1 Write '1' to disable interrupt for event ENDEPOUT[1] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPOUT2 Write '1' to disable interrupt for event ENDEPOUT[2] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPOUT3 Write '1' to disable interrupt for event ENDEPOUT[3] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPOUT4 Write '1' to disable interrupt for event ENDEPOUT[4] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPOUT5 Write '1' to disable interrupt for event ENDEPOUT[5] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPOUT6 Write '1' to disable interrupt for event ENDEPOUT[6] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDEPOUT7 Write '1' to disable interrupt for event ENDEPOUT[7] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDISOOUT Write '1' to disable interrupt for event ENDISOOUT 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SOF Write '1' to disable interrupt for event SOF 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 USBEVENT Write '1' to disable interrupt for event USBEVENT 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 EP0SETUP Write '1' to disable interrupt for event EP0SETUP 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 EPDATA Write '1' to disable interrupt for event EPDATA 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 EVENTCAUSE Details on what caused the USBEVENT event 0x400 read-write 0x00000000 oneToClear 0x20 ISOOUTCRC CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. 0 0 NotDetected No error detected 0x0 Detected Error detected 0x1 SUSPEND Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. 8 8 NotDetected Suspend not detected 0x0 Detected Suspend detected 0x1 RESUME Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. 9 9 NotDetected Resume not detected 0x0 Detected Resume detected 0x1 USBWUALLOWED USB MAC has been woken up and operational. Write '1' to clear. 10 10 NotAllowed Wake up not allowed 0x0 Allowed Wake up allowed 0x1 READY USB device is ready for normal operation. Write '1' to clear. 11 11 NotDetected USBEVENT was not issued due to USBD peripheral ready 0x0 Ready USBD peripheral is ready 0x1 HALTED Unspecified USBD_HALTED read-write 0x420 0x8 0x4 EPIN[%s] Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0x000 read-only 0x00000000 0x20 GETSTATUS IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0 15 NotHalted Endpoint is not halted 0x0000 Halted Endpoint is halted 0x0001 0x8 0x4 EPOUT[%s] Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0x024 read-only 0x00000000 0x20 GETSTATUS OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0 15 NotHalted Endpoint is not halted 0x0000 Halted Endpoint is halted 0x0001 EPSTATUS Provides information on which endpoint's EasyDMA registers have been captured 0x468 read-write 0x00000000 oneToClear 0x20 EPIN0 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 0 0 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPIN1 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 1 1 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPIN2 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 2 2 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPIN3 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 3 3 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPIN4 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 4 4 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPIN5 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 5 5 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPIN6 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 6 6 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPIN7 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 7 7 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPIN8 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 8 8 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT0 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 16 16 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT1 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 17 17 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT2 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 18 18 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT3 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 19 19 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT4 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 20 20 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT5 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 21 21 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT6 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 22 22 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT7 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 23 23 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPOUT8 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 24 24 NoData EasyDMA registers have not been captured for this endpoint 0x0 DataDone EasyDMA registers have been captured for this endpoint 0x1 EPDATASTATUS Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) 0x46C read-write 0x00000000 oneToClear 0x20 EPIN1 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 1 1 NotDone No acknowledged data transfer on this endpoint 0x0 DataDone Acknowledged data transfer on this endpoint has occurred 0x1 EPIN2 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 2 2 NotDone No acknowledged data transfer on this endpoint 0x0 DataDone Acknowledged data transfer on this endpoint has occurred 0x1 EPIN3 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 3 3 NotDone No acknowledged data transfer on this endpoint 0x0 DataDone Acknowledged data transfer on this endpoint has occurred 0x1 EPIN4 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 4 4 NotDone No acknowledged data transfer on this endpoint 0x0 DataDone Acknowledged data transfer on this endpoint has occurred 0x1 EPIN5 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 5 5 NotDone No acknowledged data transfer on this endpoint 0x0 DataDone Acknowledged data transfer on this endpoint has occurred 0x1 EPIN6 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 6 6 NotDone No acknowledged data transfer on this endpoint 0x0 DataDone Acknowledged data transfer on this endpoint has occurred 0x1 EPIN7 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 7 7 NotDone No acknowledged data transfer on this endpoint 0x0 DataDone Acknowledged data transfer on this endpoint has occurred 0x1 EPOUT1 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 17 17 NotStarted No acknowledged data transfer on this endpoint 0x0 Started Acknowledged data transfer on this endpoint has occurred 0x1 EPOUT2 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 18 18 NotStarted No acknowledged data transfer on this endpoint 0x0 Started Acknowledged data transfer on this endpoint has occurred 0x1 EPOUT3 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 19 19 NotStarted No acknowledged data transfer on this endpoint 0x0 Started Acknowledged data transfer on this endpoint has occurred 0x1 EPOUT4 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 20 20 NotStarted No acknowledged data transfer on this endpoint 0x0 Started Acknowledged data transfer on this endpoint has occurred 0x1 EPOUT5 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 21 21 NotStarted No acknowledged data transfer on this endpoint 0x0 Started Acknowledged data transfer on this endpoint has occurred 0x1 EPOUT6 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 22 22 NotStarted No acknowledged data transfer on this endpoint 0x0 Started Acknowledged data transfer on this endpoint has occurred 0x1 EPOUT7 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 23 23 NotStarted No acknowledged data transfer on this endpoint 0x0 Started Acknowledged data transfer on this endpoint has occurred 0x1 USBADDR Device USB address 0x470 read-only 0x00000000 0x20 ADDR Device USB address 0 6 BMREQUESTTYPE SETUP data, byte 0, bmRequestType 0x480 read-only 0x00000000 0x20 RECIPIENT Data transfer type 0 4 Device Device 0x00 Interface Interface 0x01 Endpoint Endpoint 0x02 Other Other 0x03 TYPE Data transfer type 5 6 Standard Standard 0x0 Class Class 0x1 Vendor Vendor 0x2 DIRECTION Data transfer direction 7 7 HostToDevice Host-to-device 0x0 DeviceToHost Device-to-host 0x1 BREQUEST SETUP data, byte 1, bRequest 0x484 read-only 0x00000000 0x20 BREQUEST SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. 0 7 STD_GET_STATUS Standard request GET_STATUS 0x00 STD_CLEAR_FEATURE Standard request CLEAR_FEATURE 0x01 STD_SET_FEATURE Standard request SET_FEATURE 0x03 STD_SET_ADDRESS Standard request SET_ADDRESS 0x05 STD_GET_DESCRIPTOR Standard request GET_DESCRIPTOR 0x06 STD_SET_DESCRIPTOR Standard request SET_DESCRIPTOR 0x07 STD_GET_CONFIGURATION Standard request GET_CONFIGURATION 0x08 STD_SET_CONFIGURATION Standard request SET_CONFIGURATION 0x09 STD_GET_INTERFACE Standard request GET_INTERFACE 0x0A STD_SET_INTERFACE Standard request SET_INTERFACE 0x0B STD_SYNCH_FRAME Standard request SYNCH_FRAME 0x0C WVALUEL SETUP data, byte 2, LSB of wValue 0x488 read-only 0x00000000 0x20 WVALUEL SETUP data, byte 2, LSB of wValue 0 7 WVALUEH SETUP data, byte 3, MSB of wValue 0x48C read-only 0x00000000 0x20 WVALUEH SETUP data, byte 3, MSB of wValue 0 7 WINDEXL SETUP data, byte 4, LSB of wIndex 0x490 read-only 0x00000000 0x20 WINDEXL SETUP data, byte 4, LSB of wIndex 0 7 WINDEXH SETUP data, byte 5, MSB of wIndex 0x494 read-only 0x00000000 0x20 WINDEXH SETUP data, byte 5, MSB of wIndex 0 7 WLENGTHL SETUP data, byte 6, LSB of wLength 0x498 read-only 0x00000000 0x20 WLENGTHL SETUP data, byte 6, LSB of wLength 0 7 WLENGTHH SETUP data, byte 7, MSB of wLength 0x49C read-only 0x00000000 0x20 WLENGTHH SETUP data, byte 7, MSB of wLength 0 7 SIZE Unspecified USBD_SIZE read-write 0x4A0 0x8 0x4 EPOUT[%s] Description collection: Number of bytes received last in the data stage of this OUT endpoint 0x000 read-write 0x00000000 zeroToClear 0x20 SIZE Number of bytes received last in the data stage of this OUT endpoint 0 6 ISOOUT Number of bytes received last on this ISO OUT data endpoint 0x020 read-only 0x00010000 0x20 SIZE Number of bytes received last on this ISO OUT data endpoint 0 9 ZERO Zero-length data packet received 16 16 Normal No zero-length data received, use value in SIZE 0x0 ZeroData Zero-length data received, ignore value in SIZE 0x1 ENABLE Enable USB 0x500 read-write 0x00000000 0x20 ENABLE Enable USB 0 0 Disabled USB peripheral is disabled 0x0 Enabled USB peripheral is enabled 0x1 USBPULLUP Control of the USB pull-up 0x504 read-write 0x00000000 0x20 CONNECT Control of the USB pull-up on the D+ line 0 0 Disabled Pull-up is disconnected 0x0 Enabled Pull-up is connected to D+ 0x1 DPDMVALUE State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). 0x508 read-write 0x00000000 0x20 STATE State D+ and D- lines will be forced into by the DPDMDRIVE task 0 4 Resume D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) 0x01 J D+ forced high, D- forced low (J state) 0x02 K D+ forced low, D- forced high (K state) 0x04 DTOGGLE Data toggle control and status 0x50C read-write 0x00000100 0x20 EP Select bulk endpoint number 0 2 IO Selects IN or OUT endpoint 7 7 Out Selects OUT endpoint 0x0 In Selects IN endpoint 0x1 VALUE Data toggle value 8 9 Nop No action on data toggle when writing the register with this value 0x0 Data0 Data toggle is DATA0 on endpoint set by EP and IO 0x1 Data1 Data toggle is DATA1 on endpoint set by EP and IO 0x2 EPINEN Endpoint IN enable 0x510 read-write 0x00000001 0x20 IN0 Enable IN endpoint 0 0 0 Disable Disable endpoint IN 0 (no response to IN tokens) 0x0 Enable Enable endpoint IN 0 (response to IN tokens) 0x1 IN1 Enable IN endpoint 1 1 1 Disable Disable endpoint IN 1 (no response to IN tokens) 0x0 Enable Enable endpoint IN 1 (response to IN tokens) 0x1 IN2 Enable IN endpoint 2 2 2 Disable Disable endpoint IN 2 (no response to IN tokens) 0x0 Enable Enable endpoint IN 2 (response to IN tokens) 0x1 IN3 Enable IN endpoint 3 3 3 Disable Disable endpoint IN 3 (no response to IN tokens) 0x0 Enable Enable endpoint IN 3 (response to IN tokens) 0x1 IN4 Enable IN endpoint 4 4 4 Disable Disable endpoint IN 4 (no response to IN tokens) 0x0 Enable Enable endpoint IN 4 (response to IN tokens) 0x1 IN5 Enable IN endpoint 5 5 5 Disable Disable endpoint IN 5 (no response to IN tokens) 0x0 Enable Enable endpoint IN 5 (response to IN tokens) 0x1 IN6 Enable IN endpoint 6 6 6 Disable Disable endpoint IN 6 (no response to IN tokens) 0x0 Enable Enable endpoint IN 6 (response to IN tokens) 0x1 IN7 Enable IN endpoint 7 7 7 Disable Disable endpoint IN 7 (no response to IN tokens) 0x0 Enable Enable endpoint IN 7 (response to IN tokens) 0x1 ISOIN Enable ISO IN endpoint 8 8 Disable Disable ISO IN endpoint 8 0x0 Enable Enable ISO IN endpoint 8 0x1 EPOUTEN Endpoint OUT enable 0x514 read-write 0x00000001 0x20 OUT0 Enable OUT endpoint 0 0 0 Disable Disable endpoint OUT 0 (no response to OUT tokens) 0x0 Enable Enable endpoint OUT 0 (response to OUT tokens) 0x1 OUT1 Enable OUT endpoint 1 1 1 Disable Disable endpoint OUT 1 (no response to OUT tokens) 0x0 Enable Enable endpoint OUT 1 (response to OUT tokens) 0x1 OUT2 Enable OUT endpoint 2 2 2 Disable Disable endpoint OUT 2 (no response to OUT tokens) 0x0 Enable Enable endpoint OUT 2 (response to OUT tokens) 0x1 OUT3 Enable OUT endpoint 3 3 3 Disable Disable endpoint OUT 3 (no response to OUT tokens) 0x0 Enable Enable endpoint OUT 3 (response to OUT tokens) 0x1 OUT4 Enable OUT endpoint 4 4 4 Disable Disable endpoint OUT 4 (no response to OUT tokens) 0x0 Enable Enable endpoint OUT 4 (response to OUT tokens) 0x1 OUT5 Enable OUT endpoint 5 5 5 Disable Disable endpoint OUT 5 (no response to OUT tokens) 0x0 Enable Enable endpoint OUT 5 (response to OUT tokens) 0x1 OUT6 Enable OUT endpoint 6 6 6 Disable Disable endpoint OUT 6 (no response to OUT tokens) 0x0 Enable Enable endpoint OUT 6 (response to OUT tokens) 0x1 OUT7 Enable OUT endpoint 7 7 7 Disable Disable endpoint OUT 7 (no response to OUT tokens) 0x0 Enable Enable endpoint OUT 7 (response to OUT tokens) 0x1 ISOOUT Enable ISO OUT endpoint 8 8 8 Disable Disable ISO OUT endpoint 8 0x0 Enable Enable ISO OUT endpoint 8 0x1 EPSTALL STALL endpoints 0x518 write-only 0x00000000 modifyExternal 0x20 EP Select endpoint number 0 2 IO Selects IN or OUT endpoint 7 7 Out Selects OUT endpoint 0x0 In Selects IN endpoint 0x1 STALL Stall selected endpoint 8 8 UnStall Don't stall selected endpoint 0x0 Stall Stall selected endpoint 0x1 ISOSPLIT Controls the split of ISO buffers 0x51C read-write 0x00000000 0x20 SPLIT Controls the split of ISO buffers 0 15 OneDir Full buffer dedicated to either ISO IN or OUT 0x0000 HalfIN Lower half for IN, upper half for OUT 0x0080 FRAMECNTR Returns the current value of the start of frame counter 0x520 read-only 0x00000000 0x20 FRAMECNTR Returns the current value of the start of frame counter 0 10 LOWPOWER Controls USBD peripheral low power mode during USB suspend 0x52C read-write 0x00000000 0x20 LOWPOWER Controls USBD peripheral low-power mode during USB suspend 0 0 ForceNormal Software must write this value to exit low power mode and before performing a remote wake-up 0x0 LowPower Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral 0x1 ISOINCONFIG Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent 0x530 read-write 0x00000000 0x20 RESPONSE Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent 0 0 NoResp Endpoint does not respond in that case 0x0 ZeroData Endpoint responds with a zero-length data packet in that case 0x1 8 0x014 EPIN[%s] Unspecified USBD_EPIN read-write 0x600 PTR Description cluster: Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Description cluster: Maximum number of bytes to transfer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes to transfer 0 6 AMOUNT Description cluster: Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 6 ISOIN Unspecified USBD_ISOIN read-write 0x6A0 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes to transfer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes to transfer 0 9 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 9 8 0x014 EPOUT[%s] Unspecified USBD_EPOUT read-write 0x700 PTR Description cluster: Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Description cluster: Maximum number of bytes to transfer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes to transfer 0 6 AMOUNT Description cluster: Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 6 ISOOUT Unspecified USBD_ISOOUT read-write 0x7A0 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes to transfer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes to transfer 0 9 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 9 UARTE1 UART with EasyDMA 1 0x40028000 UARTE1 40 QSPI External flash interface 0x40029000 0 0x1000 registers QSPI 41 QSPI 0x20 TASKS_ACTIVATE Activate QSPI interface 0x000 write-only 0x00000000 0x20 TASKS_ACTIVATE Activate QSPI interface 0 0 Trigger Trigger task 0x1 TASKS_READSTART Start transfer from external flash memory to internal RAM 0x004 write-only 0x00000000 0x20 TASKS_READSTART Start transfer from external flash memory to internal RAM 0 0 Trigger Trigger task 0x1 TASKS_WRITESTART Start transfer from internal RAM to external flash memory 0x008 write-only 0x00000000 0x20 TASKS_WRITESTART Start transfer from internal RAM to external flash memory 0 0 Trigger Trigger task 0x1 TASKS_ERASESTART Start external flash memory erase operation 0x00C write-only 0x00000000 0x20 TASKS_ERASESTART Start external flash memory erase operation 0 0 Trigger Trigger task 0x1 TASKS_DEACTIVATE Deactivate QSPI interface 0x010 write-only 0x00000000 0x20 TASKS_DEACTIVATE Deactivate QSPI interface 0 0 Trigger Trigger task 0x1 EVENTS_READY QSPI peripheral is ready. This event will be generated as a response to any QSPI task. 0x100 read-write 0x00000000 0x20 EVENTS_READY QSPI peripheral is ready. This event will be generated as a response to any QSPI task. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 READY Enable or disable interrupt for event READY 0 0 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE Enable QSPI peripheral and acquire the pins selected in PSELn registers 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable QSPI 0 0 Disabled Disable QSPI 0x0 Enabled Enable QSPI 0x1 READ Unspecified QSPI_READ read-write 0x504 SRC Flash memory source address 0x000 read-write 0x00000000 0x20 SRC Word-aligned flash memory source address. 0 31 DST RAM destination address 0x004 read-write 0x00000000 0x20 DST Word-aligned RAM destination address. 0 31 CNT Read transfer length 0x008 read-write 0x00000000 0x20 CNT Read transfer length in number of bytes. The length must be a multiple of 4 bytes. 0 17 WRITE Unspecified QSPI_WRITE read-write 0x510 DST Flash destination address 0x000 read-write 0x00000000 0x20 DST Word-aligned flash destination address. 0 31 SRC RAM source address 0x004 read-write 0x00000000 0x20 SRC Word-aligned RAM source address. 0 31 CNT Write transfer length 0x008 read-write 0x00000000 0x20 CNT Write transfer length in number of bytes. The length must be a multiple of 4 bytes. 0 17 ERASE Unspecified QSPI_ERASE read-write 0x51C PTR Start address of flash block to be erased 0x000 read-write 0x00000000 0x20 PTR Word-aligned start address of block to be erased. 0 31 LEN Size of block to be erased. 0x004 read-write 0x00000000 0x20 LEN LEN 0 1 4KB Erase 4 kB block (flash command 0x20) 0x0 64KB Erase 64 kB block (flash command 0xD8) 0x1 All Erase all (flash command 0xC7) 0x2 PSEL Unspecified QSPI_PSEL read-write 0x524 SCK Pin select for serial clock SCK 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 CSN Pin select for chip select signal CSN. 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 IO0 Pin select for serial data MOSI/IO0. 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 IO1 Pin select for serial data MISO/IO1. 0x010 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 IO2 Pin select for serial data IO2. 0x014 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 IO3 Pin select for serial data IO3. 0x018 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 XIPOFFSET Address offset into the external memory for Execute in Place operation. 0x540 read-write 0x00000000 0x20 XIPOFFSET Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. 0 31 IFCONFIG0 Interface configuration. 0x544 read-write 0x00000000 0x20 READOC Configure number of data lines and opcode used for reading. 0 2 FASTREAD Single data line SPI. FAST_READ (opcode 0x0B). 0x0 READ2O Dual data line SPI. READ2O (opcode 0x3B). 0x1 READ2IO Dual data line SPI. READ2IO (opcode 0xBB). 0x2 READ4O Quad data line SPI. READ4O (opcode 0x6B). 0x3 READ4IO Quad data line SPI. READ4IO (opcode 0xEB). 0x4 WRITEOC Configure number of data lines and opcode used for writing. 3 5 PP Single data line SPI. PP (opcode 0x02). 0x0 PP2O Dual data line SPI. PP2O (opcode 0xA2). 0x1 PP4O Quad data line SPI. PP4O (opcode 0x32). 0x2 PP4IO Quad data line SPI. PP4IO (opcode 0x38). 0x3 ADDRMODE Addressing mode. 6 6 24BIT 24-bit addressing. 0x0 32BIT 32-bit addressing. 0x1 DPMENABLE Enable deep power-down mode (DPM) feature. 7 7 Disable Disable DPM feature. 0x0 Enable Enable DPM feature. 0x1 PPSIZE Page size for commands PP, PP2O, PP4O and PP4IO. 12 12 256Bytes 256 bytes. 0x0 512Bytes 512 bytes. 0x1 IFCONFIG1 Interface configuration. 0x600 read-write 0x00040480 0x20 SCKDELAY Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). 0 7 DPMEN Enter/exit deep power-down mode (DPM) for external flash memory. 24 24 Exit Exit DPM. 0x0 Enter Enter DPM. 0x1 SPIMODE Select SPI mode. 25 25 MODE0 Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). 0x0 MODE3 Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). 0x1 SCKFREQ SCK frequency is given as 32 MHz / (SCKFREQ + 1). 28 31 STATUS Status register. 0x604 read-only 0x00000000 0x20 DPM Deep power-down mode (DPM) status of external flash. 2 2 Disabled External flash is not in DPM. 0x0 Enabled External flash is in DPM. 0x1 READY Ready status. 3 3 READY QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. 0x1 BUSY QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. 0x0 SREG Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. 24 31 DPMDUR Set the duration required to enter/exit deep power-down mode (DPM). 0x614 read-write 0xFFFFFFFF 0x20 ENTER Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. 0 15 EXIT Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. 16 31 ADDRCONF Extended address configuration. 0x624 read-write 0x000000B7 0x20 OPCODE Opcode that enters the 32-bit addressing mode. 0 7 BYTE0 Byte 0 following opcode. 8 15 BYTE1 Byte 1 following byte 0. 16 23 MODE Extended addressing mode. 24 25 NoInstr Do not send any instruction. 0x0 Opcode Send opcode. 0x1 OpByte0 Send opcode, byte0. 0x2 All Send opcode, byte0, byte1. 0x3 WIPWAIT Wait for write complete before sending command. 26 26 Disable No wait. 0x0 Enable Wait. 0x1 WREN Send WREN (write enable opcode 0x06) before instruction. 27 27 Disable Do not send WREN. 0x0 Enable Send WREN. 0x1 CINSTRCONF Custom instruction configuration register. 0x634 read-write 0x00002000 0x20 OPCODE Opcode of Custom instruction. 0 7 LENGTH Length of custom instruction in number of bytes. 8 11 1B Send opcode only. 0x1 2B Send opcode, CINSTRDAT0.BYTE0. 0x2 3B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. 0x3 4B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. 0x4 5B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. 0x5 6B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. 0x6 7B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. 0x7 8B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. 0x8 9B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. 0x9 LIO2 Level of the IO2 pin (if connected) during transmission of custom instruction. 12 12 LIO3 Level of the IO3 pin (if connected) during transmission of custom instruction. 13 13 WIPWAIT Wait for write complete before sending command. 14 14 Disable No wait. 0x0 Enable Wait. 0x1 WREN Send WREN (write enable opcode 0x06) before instruction. 15 15 Disable Do not send WREN. 0x0 Enable Send WREN. 0x1 LFEN Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. 16 16 Disable Long frame mode disabled 0x0 Enable Long frame mode enabled 0x1 LFSTOP Stop (finalize) long frame transaction 17 17 Stop Stop 0x1 CINSTRDAT0 Custom instruction data register 0. 0x638 read-write 0x00000000 0x20 BYTE0 Data byte 0 0 7 BYTE1 Data byte 1 8 15 BYTE2 Data byte 2 16 23 BYTE3 Data byte 3 24 31 CINSTRDAT1 Custom instruction data register 1. 0x63C read-write 0x00000000 0x20 BYTE4 Data byte 4 0 7 BYTE5 Data byte 5 8 15 BYTE6 Data byte 6 16 23 BYTE7 Data byte 7 24 31 IFTIMING SPI interface timing. 0x640 read-write 0x00000200 0x20 RXDELAY Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. 8 10 CRYPTOCELL CRYPTOCELL register interface 0x5002A000 0 0x1000 registers CRYPTOCELL 42 CRYPTOCELL 0x20 ENABLE Enable CRYPTOCELL subsystem. 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable the CRYPTOCELL subsystem. 0 0 Disabled CRYPTOCELL subsystem disabled. 0x0 Enabled CRYPTOCELL subsystem enabled. 0x1 CC_AES CRYPTOCELL AES engine 0x5002B000 0 0x1000 registers CC_AES 0x20 0x8 0x4 AES_KEY_0[%s] Description collection: AES key value to use. The initial AES_KEY_0[0] register holds the least significant bits [31:0] of the key value. 0x400 write-only 0x00000000 0x20 VALUE AES key value. 0 31 0x4 0x4 AES_IV_0[%s] Description collection: AES Initialization Vector (IV) to use. The initial AES_IV_0[0] register holds the least significant bits [31:0] of the IV. 0x440 read-write 0x00000000 0x20 VALUE AES non-tunneling or first tunnel stage IV value. 0 31 0x4 0x4 AES_CTR[%s] Description collection: AES counter (CTR) to use. The initial AES_CTR[0] register holds the least significant bits [31:0] of the CTR. 0x460 read-write 0x00000000 0x20 VALUE AES CTR value. 0 31 AES_BUSY Status register for AES engine activity. 0x470 read-only 0x00000000 0x20 STATUS AES engine status. 0 0 Idle AES engine is idle 0x0 Busy AES engine is busy 0x1 AES_SK Writing to this address trigger sampling of the HW key to the AES_KEY_0 register 0x478 write-only 0x00000000 0x20 AES_SK Sample HW key to AES_KEY_0 registers. 0 0 AES_CMAC_INIT Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations. 0x47C write-only 0x00000000 0x20 ENABLE Generate K1 and K2 for the AES-CMAC operations. 0 0 Enable Initialize AES-CMAC operations. 0x1 AES_REMAINING_BYTES This register should be set with the amount of remaining bytes until the end of the current AES operation. 0x4BC read-write 0x00000000 0x20 VALUE Remaining bytes util the end of the current AES operation. 0 31 AES_CONTROL Control the AES engine behavior. 0x4C0 read-write 0x00000000 0x20 DEC_KEY0 Set AES encrypt or decrypt mode in non-tunneling operations. 0 0 Encrypt Perform AES encryption 0x0 Decrypt Perform AES decryption 0x1 MODE_KEY0 Set the AES mode. 2 4 ECB Electronic codebook mode 0x0 CBC Cipher block chaining mode 0x1 CTR Counter mode 0x2 CBC_MAC Cipher Block Chaining Message Authentication Code 0x3 CMAC Cipher-based Message Authentication Code 0x7 NK_KEY0 Set the AES key length. 12 13 128Bits 128 bits key length 0x0 AES_XOR_CRYPTOKEY This field determines the value that is written to AES_KEY_0, when AES_SK is kicked. 29 29 Disable The value that is written to AES_KEY_0 is the value of the HW cryptokey as is. 0x0 Enable The value that is written to AES_KEY_0 is the value of the HW cryptokey XOR with the current value of AES_KEY_0. 0x1 DIRECT_ACCESS Using direct access and not the DIN-DOUT DMA interface 31 31 Disable Access using the DIN-DOUT DMA interface 0x0 Enable Access using direct access 0x1 AES_HW_FLAGS Hardware configuration of the AES engine. Reset value holds the supported features. 0x4C8 read-only 0x00000108 0x20 SUPPORT_256_192_KEY If this flag is set, the engine support 192 bits and 256 bits key size. 0 0 AES_LARGE_RKEK If this flag is set, the engine support AES_LARGE_RKEK. 1 1 DPA_CNTRMSR_EXIST If this flag is set, the engine support DPA countermeasures. 2 2 CTR_EXIST If this flag is set, the engine support AES CTR mode. 3 3 ONLY_ENCRYPT If this flag is set, the engine only support encrypt operations. 4 4 USE_SBOX_TABLE If this flag is set, the engine uses SBOX tables. 5 5 USE_5_SBOXES If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles. 8 8 AES_SUPPORT_PREV_IV If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation. 9 9 AES_TUNNEL_EXIST If this flag is set, the engine support tunneling operations. 10 10 SECOND_REGS_SET_EXIST If this flag is set, the engine support a second register set for tunneling operations. 11 11 DFA_CNTRMSR_EXIST If this flag is set, the engine support DFA countermeasures. 12 12 AES_CTR_NO_INCREMENT This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks 0x4D8 read-write 0x00000000 0x20 ENABLE This field enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks 0 0 Disable Counter always incremented between blocks 0x0 Enable Do not increment counter between blocks 0x1 AES_SW_RESET Reset the AES engine. 0x4F4 write-only 0x00000000 0x20 RESET Writing any value to this address resets the AES engine. The reset takes 4 CPU clock cycles to complete. 0 0 Enable Reset AES engine. 0x1 AES_CMAC_SIZE0_KICK Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register. 0x524 write-only 0x00000000 0x20 ENABLE Force AES CMAC operation with size 0. 0 0 Disable Normal AES CMAC operation 0x0 Enable Force CMAC operation with size 0 0x1 CC_CHACHA CRYPTOCELL CHACHA engine 0x5002B000 CC_AES 0 0x1000 registers CC_CHACHA 0x20 CHACHA_CONTROL Control the CHACHA engine behavior. 0x380 read-write 0x00000000 0x20 CHACHA_OR_SALSA Run engine in ChaCha or Salsa mode 0 0 ChaCha Run engine in ChaCha mode 0x0 Salsa Run engine in Salsa mode 0x1 INIT Perform initialization for a new message 1 1 Disable Message already initialized 0x0 Enable Initialize new message 0x1 GEN_KEY_POLY1305 Generate the key to use in Poly1305 message authentication code calculation. 2 2 Disable Do not generate Poly1305 key 0x0 Enable Generate Poly1305 key 0x1 KEY_LEN Key length selection. 3 3 256Bits Use 256 bits key length 0x0 128Bits Use 128 bits key length 0x1 NUM_OF_ROUNDS Set number of permutation rounds, default value is 20. 4 5 Default Use 20 rounds of rotation (default) 0x0 12Rounds Use 12 rounds of rotation 0x1 8Rounds Use 8 rounds of rotation 0x2 RESET_BLOCK_CNT Reset block counter for new messages 9 9 Disable Use current block counter value 0x0 Enable Reset block counter value to zero 0x1 USE_IV_96BIT Use 96 bits Initialization Vector (IV) 10 10 Disable Use default size IV of 64 bit 0x0 Enable The IV is 96 bits 0x1 CHACHA_VERSION CHACHA engine HW version 0x384 read-only 0x00000001 0x20 CHACHA_VERSION 0 31 0x8 0x4 CHACHA_KEY[%s] Description collection: CHACHA key value to use. The initial CHACHA_KEY[0] register holds the least significant bits [31:0] of the key value. 0x388 write-only 0x00000000 0x20 VALUE CHACHA key value. 0 31 0x2 0x4 CHACHA_IV[%s] Description collection: CHACHA Initialization Vector (IV) to use. The IV is also known as the nonce. 0x3A8 read-write 0x00000000 0x20 VALUE CHACHA IV value. 0 31 CHACHA_BUSY Status register for CHACHA engine activity. 0x3B0 read-only 0x00000000 0x20 STATUS CHACHA engine status. 0 0 Idle CHACHA engine is idle 0x0 Busy CHACHA engine is busy 0x1 CHACHA_HW_FLAGS Hardware configuration of the CHACHA engine. Reset value holds the supported features. 0x3B4 read-only 0x00000001 0x20 CHACHA_EXISTS If this flag is set, the engine include ChaCha support 0 0 SALSA_EXISTS If this flag is set, the engine include Salsa support 1 1 FAST_CHACHA If this flag is set, the next matrix calculated when the current one is written to data output path. 2 2 CHACHA_BLOCK_CNT_LSB Store the LSB value of the block counter, in order to support suspend/resume of operation 0x3B8 read-write 0x00000000 0x20 VALUE This register holds the ChaCha block counter bits [31:0] and must be read and written during respectively suspend and resume operations. 0 31 CHACHA_BLOCK_CNT_MSB Store the MSB value of the block counter, in order to support suspend/resume of operation 0x3BC read-write 0x00000000 0x20 VALUE This register holds the ChaCha block counter bits [63:32] and must be read and written during respectively suspend and resume operations. 0 31 CHACHA_SW_RESET Reset the CHACHA engine. 0x3C0 write-only 0x00000000 0x20 RESET Writing any value to this address resets the CHACHA engine. The reset takes 4 CPU clock cycles to complete. 0 0 Enable Reset CHACHA engine. 0x1 0x8 0x4 CHACHA_POLY1305_KEY[%s] Description collection: The auto-generated key to use in Poly1305 MAC calculation. The initial CHACHA_POLY1305_KEY[0] register holds the least significant bits [31:0] of the key value. 0x3C4 read-only 0x00000000 0x20 VALUE Poly1305 key value. 0 31 CHACHA_ENDIANNESS CHACHA engine data order configuration. 0x3E4 read-write 0x00000000 0x20 CHACHA_DIN_WORD_ORDER Change the word order of the input data. 0 0 Default Use default word order for 128-bits input, where words are ordered as follows: w0, w1, w2, w3. 0x0 Reverse Reverses the word order for 128-bits input, where words are re-ordered as follows: w3, w2, w1, w0. 0x1 CHACHA_DIN_BYTE_ORDER Change the byte order of the input data. 1 1 Default Use default byte order within each input word, where bytes are ordered as follows: B0, B1, B2, B3. 0x0 Reverse Reverse the byte order within each input word, where bytes are re-ordered as follows: B3, B2, B1, B0. 0x1 CHACHA_CORE_MATRIX_LBE_ORDER Change the quarter of a matrix order in the engine. 2 2 Default Use default quarter of matrix order, where quarters are ordered as follows: q0, q1, q2, q3. Each quarter represents a 128-bits section of the matrix. 0x0 Reverse Reverse the order of matrix quarters, where quarters are re-ordered as follows: q3, q2, q1, q0. Each quarter represents a 128-bits section of the matrix. 0x1 CHACHA_DOUT_WORD_ORDER Change the word order of the output data. 3 3 Default Uses default word order for 128-bits output, where words are ordered as follows: w0, w1, w2, w3. 0x0 Reverse Reverse the word order for 128-bits output, where words are re-ordered as follows: w3, w2, w1, w0. 0x1 CHACHA_DOUT_BYTE_ORDER Change the byte order of the output data. 4 4 Default Use default byte order within each output word, where bytes are ordered as follows: B0, B1, B2, B3. 0x0 Reverse Reverse the byte order within each output word, where bytes are re-ordered as follows: B3, B2, B1, B0. 0x1 CHACHA_DEBUG Debug register for the CHACHA engine 0x3E8 read-only 0x00000000 0x20 FSM_STATE Reflects the debug state of the CHACHA FSM. 0 1 IDLE_STATE CHACHA FSM is in idle state 0x0 INIT_STATE CHACHA FSM is in init state 0x1 ROUNDS_STATE CHACHA FSM is in rounds state 0x2 FINAL_STATE CHACHA FSM is in final state 0x3 CC_CTL CRYPTOCELL CTL interface 0x5002B000 CC_AES 0 0x1000 registers CC_CTL 0x20 CRYPTO_CTL Defines the cryptographic flow. 0x900 write-only 0x00000000 0x20 MODE Configure the cryptographic engine mode. 0 4 Bypass Bypass cryptographic engine 0x00 AESActive Use AES engine 0x01 AESToHashActive Pipe AES engine output to HASH engine input 0x02 AESAndHashActive Process input using both AES and HASH engine in parallell 0x03 HashActive Use HASH engine 0x07 AESMACAndBypassActive Calculate AES MAC and bypass 0x09 AESToHashAndDOUTActive Pipe AES engine output to HASH engine input. The resulting digest output is piped to DOUT buffer. 0x0A ChaChaActive Use CHACHA engine 0x10 CRYPTO_BUSY Status register for cryptographic cores engine activity. 0x910 read-only 0x00000000 0x20 STATUS Cryptographic core engines status. 0 0 Idle Cryptographic core engines are idle 0x0 Busy Cryptographic core engines are busy 0x1 HASH_BUSY Status register for HASH engine activity. 0x91C read-only 0x00000000 0x20 STATUS Hash engine status. 0 0 Idle HASH engine is idle 0x0 Busy HASH engine is busy 0x1 CONTEXT_ID A general-purpose read/write register. 0x930 read-write 0x00000000 0x20 CONTEXT_ID Context ID 0 7 CC_DIN CRYPTOCELL Data IN interface 0x5002B000 CC_AES 0 0x1000 registers CC_DIN 0x20 DIN_BUFFER Used by CPU to write data directly to the DIN buffer, which is then sent to the cryptographic engines for processing. 0xC00 write-only 0x00000000 0x20 DATA This register is mapped into 8 addresses in order to enable a CPU burst. 0 31 DIN_DMA_MEM_BUSY Status register for DIN DMA engine activity when accessing memory. 0xC20 read-only 0x00000000 0x20 STATUS DIN memory DMA engine status. 0 0 Idle DIN memory DMA engine is idle 0x0 Busy DIN memory DMA engine is busy 0x1 SRC_MEM_ADDR Data source address in memory. 0xC28 write-only 0x00000000 0x20 ADDR Source address in memory. 0 31 SRC_MEM_SIZE The number of bytes to be read from memory. Writing to this register triggers the DMA operation. 0xC2C write-only 0x00000000 0x20 SIZE Total number of bytes to read from memory. 0 29 FIRST This field is reserved 30 30 LAST This field is reserved 31 31 SRC_SRAM_ADDR Data source address in RNG SRAM. 0xC30 read-write 0x00000000 0x20 ADDR Source address in RNG SRAM. 0 31 SRC_SRAM_SIZE The number of bytes to be read from RNG SRAM. Writing to this register triggers the DMA operation. 0xC34 write-only 0x00000000 0x20 SIZE Total number of bytes to read from RNG SRAM. 0 31 DIN_DMA_SRAM_BUSY Status register for DIN DMA engine activity when accessing RNG SRAM. 0xC38 read-only 0x00000000 0x20 STATUS DIN RNG SRAM DMA engine status. 0 0 Idle DIN RNG SRAM DMA engine is idle 0x0 Busy DIN RNG SRAM DMA engine is busy 0x1 DIN_DMA_SRAM_ENDIANNESS Configure the endianness of DIN DMA transactions towards RNG SRAM. 0xC3C read-write 0x00000000 0x20 ENDIAN Endianness of DIN DMA transactions towards RNG SRAM. The default value is little-endian. 0 0 LittleEndian Use little-endian format for RNG SRAM DMA transactions 0x0 BigEndian Use big-endian format for RNG SRAM DMA transactions 0x1 DIN_SW_RESET Reset the DIN DMA engine. 0xC44 write-only 0x00000000 0x20 RESET Writing any value to this address resets the DIN DMA engine. The reset takes 4 CPU clock cycles to complete. 0 0 Enable Reset DIN DMA engine. 0x1 DIN_CPU_DATA Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data. 0xC48 write-only 0x00000000 0x20 SIZE When using CPU direct write to the DIN_BUFFER, the size of input data in bytes should be written to this register. 0 15 DIN_WRITE_ALIGN Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). 0xC4C write-only 0x00000000 0x20 LAST Next CPU write to the DIN_BUFFER is the last word. 0 0 Confirm The next CPU write is the last in the sequence. 0x1 DIN_FIFO_EMPTY Register indicating if DIN FIFO is empty and if more data can be accepted. 0xC50 read-only 0x00000001 0x20 STATUS DIN FIFO status 0 0 NotEmpty DIN FIFO is not empty 0x0 Empty DIN FIFO is empty, and more data can be accepted 0x1 DIN_FIFO_RESET Reset the DIN FIFO, effectively clearing the FIFO for new data. 0xC58 write-only 0x00000000 0x20 RESET Writing any value to this address resets the DIN FIFO. 0 0 Enable Reset DIN FIFO. 0x1 CC_DOUT CRYPTOCELL Data OUT interface 0x5002B000 CC_AES 0 0x1000 registers CC_DOUT 0x20 DOUT_BUFFER Cryptographic results directly accessible by the CPU. 0xC00 read-only 0x00000000 0x20 DATA This address can be used by the CPU to read data directly from the DOUT buffer. 0 31 DOUT_DMA_MEM_BUSY Status register for DOUT DMA engine activity when accessing memory. 0xD20 read-only 0x00000000 0x20 STATUS DOUT memory DMA engine status. 0 0 Idle DOUT memory DMA engine is idle 0x0 Busy DOUT memory DMA engine is busy 0x1 DST_MEM_ADDR Data destination address in memory. 0xD28 write-only 0x00000000 0x20 ADDR Destination address in memory. 0 31 DST_MEM_SIZE The number of bytes to be written to memory. 0xD2C write-only 0x00000000 0x20 SIZE Total number of bytes to write to memory. 0 29 FIRST This field is reserved 30 30 LAST This field is reserved 31 31 DST_SRAM_ADDR Data destination address in RNG SRAM. 0xD30 read-write 0x00000000 0x20 ADDR Destination address in RNG SRAM. 0 31 DST_SRAM_SIZE The number of bytes to be written to RNG SRAM. 0xD34 write-only 0x00000000 0x20 SIZE Total number of bytes to write to RNG SRAM. 0 31 DOUT_DMA_SRAM_BUSY Status register for DOUT DMA engine activity when accessing RNG SRAM. 0xD38 read-only 0x00000000 0x20 STATUS DOUT RNG SRAM DMA engine status. 0 0 Idle DOUT RNG SRAM DMA engine is idle 0x0 Busy DOUT RNG SRAM DMA engine is busy 0x1 DOUT_DMA_SRAM_ENDIANNESS Configure the endianness of DOUT DMA transactions towards RNG SRAM. 0xD3C read-write 0x00000000 0x20 ENDIAN Endianness of DOUT DMA transactions towards RNG SRAM. The default value is little-endian. 0 0 LittleEndian Use little-endian format for RNG SRAM DMA transactions 0x0 BigEndian Use big-endian format for RNG SRAM DMA transactions 0x1 DOUT_READ_ALIGN Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). 0xD44 write-only 0x00000000 0x20 LAST Next CPU read from the DOUT_BUFFER is the last word, and the remaining read aligned content can be flushed. 0 0 Flush Flush the remaining read aligned content. 0x1 DOUT_FIFO_EMPTY Register indicating if DOUT FIFO is empty or if more data will come. 0xD50 read-only 0x00000001 0x20 STATUS DOUT FIFO status 0 0 NotEmpty DOUT FIFO is not empty, and more data will come 0x0 Empty DOUT FIFO is empty 0x1 DOUT_SW_RESET Reset the DOUT DMA engine. 0xD58 write-only 0x00000000 0x20 RESET Writing any value to this address resets the DOUT DMA engine. The reset takes 4 CPU clock cycles to complete. 0 0 Enable Reset DOUT DMA engine. 0x1 CC_HASH CRYPTOCELL HASH engine 0x5002B000 CC_AES 0 0x1000 registers CC_HASH 0x20 0x8 0x4 HASH_H[%s] Description collection: HASH_H value registers. The initial HASH_H[0] register holds the least significant bits [31:0] of the value. 0x640 read-write 0x00000000 0x20 VALUE Write the initial hash value before start of digest operation, and read the final hash value result after the digest operation has been completed. 0 31 HASH_PAD_AUTO Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation. 0x684 write-only 0x00000000 0x20 HWPAD Enable automatic padding in hardware. 0 0 Disable Do not enable automatic hardware padding. 0x0 Enable Enable automatic hardware padding. 0x1 HASH_INIT_STATE Configure HASH engine initial state registers. 0x694 write-only 0x00000000 0x20 LOAD Enable loading of data to initial state registers. Digest/IV for HASH/AES_MAC. 0 0 Disable Disable loading of data to initial state registers. 0x0 Enable Enable loading of data to initial state registers. 0x1 HASH_VERSION HASH engine HW version 0x7B0 read-only 0x00000000 0x20 PATCH 0 7 MINOR_VERSION_NUMBER Minor version number 8 11 MAJOR_VERSION_NUMBER Major version number 12 15 HASH_CONTROL Control the HASH engine behavior. 0x7C0 read-write 0x00000000 0x20 MODE Select HASH mode to execute 0 3 SHA1 Select SHA1 mode 0x1 SHA256 Select SHA256 mode 0x2 SHA224 Select SHA224 mode 0xA HASH_PAD Enable the hardware padding feature of the HASH engine. 0x7C4 read-write 0x00000001 0x20 ENABLE Configure hardware padding feature. 0 0 Disable Disable hardware padding feature. 0x0 Enable Enable hardware padding feature. 0x1 HASH_PAD_FORCE Force the hardware padding operation to trigger if the input data length is zero bytes. 0x7C8 read-write 0x00000000 0x20 ENABLE Trigger hardware padding operation. 2 2 Disable Do not force hardware padding to trigger. 0x0 Enable Force hardware padding to trigger. 0x1 HASH_CUR_LEN_0 Bits [31:0] of the number of bytes that have been digested so far. 0x7CC read-write 0x00000000 0x20 VALUE Bits [31:0] of current length of digested data in bytes. 0 31 HASH_CUR_LEN_1 Bits [63:32] of the number of bytes that have been digested so far. 0x7D0 read-write 0x00000000 0x20 VALUE Bits [63:32] of current length of digested data in bytes. 0 31 HASH_HW_FLAGS Hardware configuration of the HASH engine. Reset value holds the supported features. 0x7DC read-only 0x00012001 0x20 CW Indicates the number of concurrent words the hash is using to compute signature. 0 3 One One concurrent word used by hash during signature generation 0x1 Two Two concurrent words used by hash during signature generation 0x2 CH Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. 4 7 One One Hi value is updated at a time. 0x0 All All Hi values are updated at the same time. 0x1 DW Determine the granularity of word size. 8 11 32Bits 32 bits word data. 0x0 64Bits 64 bits word data. 0x1 SHA_512_EXISTS If this flag is set, the engine include SHA-512 support. 12 12 PAD_EXISTS If this flag is set, the engine include pad block support. 13 13 MD5_EXISTS If this flag is set, the engine include MD5 support. 14 14 HMAC_EXISTS If this flag is set, the engine include HMAC support. 15 15 SHA_256_EXISTS If this flag is set, the engine include SHA-256 support. 16 16 HASH_COMPARE_EXISTS If this flag is set, the engine include compare digest logic. 17 17 DUMP_HASH_TO_DOUT_EXISTS If this flag is set, the engine include HASH to DOUT support. 18 18 HASH_SW_RESET Reset the HASH engine. 0x7E4 write-only 0x00000000 0x20 RESET Writing any value to this address resets the HASH engine. The reset takes 4 CPU clock cycles to complete. 0 0 Enable Reset HASH engine. 0x1 HASH_ENDIANNESS Configure the endianness of HASH data and padding generation. 0x7E8 read-write 0x00000001 0x20 ENDIAN Endianness of HASH data and padding generation. The default value is little-endian. 0 0 LittleEndian Use little-endian format for data and padding 0x0 BigEndian Use big-endian format for data and padding 0x1 CC_HOST_RGF CRYPTOCELL HOST register interface 0x5002B000 CC_AES 0 0x1000 registers CC_HOST_RGF 0x20 IRR Interrupt request register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding IMR bit is unmasked, an interrupt is generated. 0xA00 read-only 0x00000000 0x20 SRAM_TO_DIN_INT The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer. 4 4 DOUT_TO_SRAM_INT The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM. 5 5 MEM_TO_DIN_INT The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer. 6 6 DOUT_TO_MEM_INT The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory. 7 7 AHB_ERR_INT The AHB error interrupt status. 8 8 PKA_INT The PKA end of operation interrupt status. 9 9 RNG_INT The RNG interrupt status. 10 10 IMR Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. 0xA04 read-write 0x01FFFFFF 0x20 SRAM_TO_DIN_MASK The RNG SRAM to DIN DMA done interrupt mask. 4 4 IRQEnable Do not mask RNG SRAM to DIN DMA done interrupt i.e. interrupt is generated 0x0 IRQDisable Mask RNG SRAM to DIN DMA done interrupt i.e. no interrupt is generated 0x1 DOUT_TO_SRAM_MASK The DOUT to RNG SRAM DMA done interrupt mask. 5 5 IRQEnable Do not mask DOUT to RNG SRAM DMA done interrupt i.e. interrupt is generated 0x0 IRQDisable Mask DOUT to RNG SRAM DMA done interrupt i.e. no interrupt is generated 0x1 MEM_TO_DIN_MASK The memory to DIN DMA done interrupt mask. 6 6 IRQEnable Do not mask memory to DIN DMA done interrupt i.e. interrupt is generated 0x0 IRQDisable Mask memory to DIN DMA done interrupt i.e. no interrupt is generated 0x1 DOUT_TO_MEM_MASK The DOUT to memory DMA done interrupt mask. 7 7 IRQEnable Do not mask DOUT to memory DMA done interrupt i.e. interrupt is generated 0x0 IRQDisable Mask DOUT to memory DMA done interrupt i.e. no interrupt is generated 0x1 AHB_ERR_MASK The AHB error interrupt mask. 8 8 IRQEnable Do not mask AHB error interrupt i.e. interrupt is generated 0x0 IRQDisable Mask AHB error interrupt i.e. no interrupt is generated 0x1 PKA_MASK The PKA end of operation interrupt mask. 9 9 IRQEnable Do not mask PKA end of operation interrupt i.e. interrupt is generated 0x0 IRQDisable Mask PKA end of operation interrupt i.e. no interrupt is generated 0x1 RNG_MASK The RNG interrupt mask. 10 10 IRQEnable Do not mask RNG interrupt i.e. interrupt is generated 0x0 IRQDisable Mask RNG interrupt i.e. no interrupt is generated 0x1 ICR Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR. 0xA08 write-only 0x00000000 0x20 SRAM_TO_DIN_CLEAR The RNG SRAM to DIN DMA done interrupt clear. 4 4 DOUT_TO_SRAM_CLEAR The DOUT to RNG SRAM DMA done interrupt clear. 5 5 MEM_TO_DIN_CLEAR The memory to DIN DMA done interrupt clear. 6 6 DOUT_TO_MEM_CLEAR The DOUT to memory DMA done interrupt clear. 7 7 AHB_ERR_CLEAR The AHB error interrupt clear. 8 8 PKA_CLEAR The PKA end of operation interrupt clear. 9 9 RNG_CLEAR The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared. 10 10 ENDIANNESS This register defines the endianness of the Host-accessible registers, and can only be written once. 0xA0C read-write 0x00000000 0x20 DOUT_WR_BG DOUT write endianness. 3 3 LittleEndian Configure DOUT write as little-endian 0x0 BigEndian Configure DOUT write as big-endian 0x1 DIN_RD_BG DIN read endianness. 7 7 LittleEndian Configure DIN read as little-endian 0x0 BigEndian Configure DIN read as big-endian 0x1 DOUT_WR_WBG DOUT write word endianness. 11 11 LittleEndian Configure DOUT write word as little-endian 0x0 BigEndian Configure DOUT write word as big-endian 0x1 DIN_RD_WBG DIN read word endianness. 15 15 LittleEndian Configure DIN read word as little-endian 0x0 BigEndian Configure DIN read word as big-endian 0x1 HOST_SIGNATURE This register holds the CRYPTOCELL subsystem signature. See reset value. 0xA24 read-only 0x20E00000 0x20 VALUE Fixed-value identification signature used by host driver to verify CRYPTOCELL presence at this address. 0 31 HOST_BOOT Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features. 0xA28 read-only 0x4622982C 0x20 POWER_GATING_EXISTS_LOCAL If this flag is set, full power gating is implemented 0 0 LARGE_RKEK_LOCAL If this flag is set, large RKEK is supported 1 1 HASH_IN_FUSES_LOCAL If this flag is set, HASH in fuses is supported 2 2 EXT_MEM_SECURED_LOCAL If this flag is set, external secure memory is supported 3 3 RKEK_ECC_EXISTS_LOCAL_N If this flag is set, RKEK ECC is supported 5 5 SRAM_SIZE_LOCAL SRAM size 6 8 DSCRPTR_EXISTS_LOCAL If this flag is set, Descriptors are supported 9 9 PAU_EXISTS_LOCAL If this flag is set, PAU is supported 10 10 RNG_EXISTS_LOCAL If this flag is set, the RNG engine is present 11 11 PKA_EXISTS_LOCAL If this flag is set, the PKA engine is present 12 12 RC4_EXISTS_LOCAL If this flag is set, the RC4 engine is present 13 13 SHA_512_PRSNT_LOCAL If this flag is set, the HASH engine supports SHA512 14 14 SHA_256_PRSNT_LOCAL If this flag is set, the HASH engine supports SHA256 15 15 MD5_PRSNT_LOCAL If this flag is set, the HASH engine supports MD5 16 16 HASH_EXISTS_LOCAL If this flag is set, the HASH engine is present 17 17 C2_EXISTS_LOCAL If this flag is set, the C2 engine is present 18 18 DES_EXISTS_LOCAL If this flag is set, the DES engine is present 19 19 AES_XCBC_MAC_EXISTS_LOCAL If this flag is set, AES XCBC-MAC mode is supported 20 20 AES_CMAC_EXISTS_LOCAL If this flag is set, AES CMAC mode is supported 21 21 AES_CCM_EXISTS_LOCAL If this flag is set, AES CCM mode is supported 22 22 AES_XEX_HW_T_CALC_LOCAL If this flag is set, AES XEX mode T-value calculation in HW is supported 23 23 AES_XEX_EXISTS_LOCAL If this flag is set, AES XEX mode is supported 24 24 CTR_EXISTS_LOCAL If this flag is set, AES CTR mode is supported 25 25 AES_DIN_BYTE_RESOLUTION_LOCAL If this flag is set, the AES engine data input support byte size resolution 26 26 TUNNELING_ENB_LOCAL If this flag is set, the AES engine supports tunneling operations 27 27 SUPPORT_256_192_KEY_LOCAL If this flag is set, the AES engine supports 192/256 bits key sizes 28 28 ONLY_ENCRYPT_LOCAL If this flag is set, the AES engine only support encryption 29 29 AES_EXISTS_LOCAL If this flag is set, the AES engine is present 30 30 HOST_CRYPTOKEY_SEL AES hardware key select. 0xA38 read-write 0x00000000 0x20 HOST_CRYPTOKEY_SEL Select the source of the HW key that is used by the AES engine 0 1 K_DR Use device root key K_DR from CRYPTOCELL AO power domain 0x0 K_PRTL Use hard-coded RTL key K_PRTL 0x1 Session Use provided session key 0x2 HOST_IOT_KPRTL_LOCK This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. 0xA4C read-writeonce 0x00000000 0x20 HOST_IOT_KPRTL_LOCK This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. 0 0 Disabled K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL 0x0 Enabled K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. 0x1 HOST_IOT_KDR0 This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. 0xA50 read-writeonce 0x00000000 0x20 HOST_IOT_KDR0 This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. Write: K_DR bits 31:0. 0 31 NotRetained Read: 128 bits K_DR key value is not yet retained in the CRYPTOCELL AO power domain. 0x00000000 Retained Read: 128 bits K_DR key value is successfully retained in the CRYPTOCELL AO power domain. 0x00000001 HOST_IOT_KDR1 This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0xA54 writeonce 0x00000000 0x20 HOST_IOT_KDR1 K_DR bits 63:32 0 31 HOST_IOT_KDR2 This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0xA58 writeonce 0x00000000 0x20 HOST_IOT_KDR2 K_DR bits 95:64 0 31 HOST_IOT_KDR3 This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0xA5C writeonce 0x00000000 0x20 HOST_IOT_KDR3 K_DR bits 127:96 0 31 HOST_IOT_LCS Controls life-cycle state (LCS) for CRYPTOCELL subsystem 0xA60 read-write 0x00000002 0x20 LCS Life-cycle state value. This field is write-once per reset. 0 2 read-writeonce DebugEnable CC310 operates in debug mode 0x0 Secure CC310 operates in secure mode 0x2 LCS_IS_VALID Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. 8 8 read-only Invalid Valid LCS not yet retained in the CRYPTOCELL AO power domain 0x0 Valid Valid LCS successfully retained in the CRYPTOCELL AO power domain 0x1 CC_MISC CRYPTOCELL MISC interface 0x5002B000 CC_AES 0 0x1000 registers CC_MISC 0x20 AES_CLK Clock control for the AES engine. 0x810 write-only 0x00000000 0x20 ENABLE Enables clock for the AES engine. 0 0 Disable Disable clock for the AES engine. 0x0 Enable Enable clock for the AES engine. 0x1 HASH_CLK Clock control for the HASH engine. 0x818 write-only 0x00000000 0x20 ENABLE Enables clock for the HASH engine. 0 0 Disable Disable clock for the HASH engine. 0x0 Enable Enable clock for the HASH engine. 0x1 PKA_CLK Clock control for the PKA engine. 0x81C write-only 0x00000000 0x20 ENABLE Enables clock for the PKA engine. 0 0 Disable Disable clock for the PKA engine. 0x0 Enable Enable clock for the PKA engine. 0x1 DMA_CLK Clock control for the DMA engines. 0x820 write-only 0x00000000 0x20 ENABLE Enables clock for the DMA engines. 0 0 Disable Disable clock for the DMA engines. 0x0 Enable Enable clock for the DMA engines. 0x1 CLK_STATUS CRYPTOCELL clocks status register. 0x824 read-only 0x00000100 0x20 AES_CLK Status of AES engine clock. 0 0 Disabled Clock for AES engine is disabled 0x0 Enabled Clock for AES engine is enabled 0x1 HASH_CLK Status of HASH engine clock. 2 2 Disabled Clock for HASH engine is disabled 0x0 Enabled Clock for HASH engine is enabled 0x1 PKA_CLK Status of PKA engine clock. 3 3 Disabled Clock for PKA engine is disabled 0x0 Enabled Clock for PKA engine is enabled 0x1 CHACHA_CLK Status of CHACHA engine clock. 7 7 Disabled Clock for CHACHA engine is disabled 0x0 Enabled Clock for CHACHA engine is enabled 0x1 DMA_CLK Status of DMA engines clock. 8 8 Disabled Clocks for DMA engines are disabled 0x0 Enabled Clocks for DMA engines are enabled 0x1 CHACHA_CLK Clock control for the CHACHA engine. 0x858 write-only 0x00000000 0x20 ENABLE Enables clock for the CHACHA engine. 0 0 Disable Disable clock for the CHACHA engine. 0x0 Enable Enable clock for the CHACHA engine. 0x1 CC_PKA CRYPTOCELL PKA engine 0x5002B000 CC_AES 0 0x1000 registers CC_PKA 0x20 0x20 0x4 MEMORY_MAP[%s] Description collection: Register for mapping the virtual register R[n] to a physical address in the PKA SRAM. 0x0 read-write 0x00000000 0x20 ADDR The physical word address used for the virtual register. 1 9 OPCODE Operation code to be executed by the PKA engine. Writing to this register triggers the PKA operation. 0x80 read-write 0x00000000 0x20 TAG Holds the operation tag or the operand C virtual register index. 0 5 REG_R Result register virtual register index. 6 10 DISCARD_R This field controls the interpretation of REG_R. 11 11 Register REG_R is intepreted as a register index. 0x0 Discard Result is discarded. 0x1 REG_B Operand B virtual register index. 12 16 CONST_B This field controls the interpretation of REG_B. 17 17 Register REG_B is intepreted as a register index. 0x0 Constant REG_B is intepreted as a constant. 0x1 REG_A Operand A virtual register index. 18 22 CONST_A This field controls the interpretation of REG_A. 23 23 Register REG_A is intepreted as a register index. 0x0 Constant REG_A is intepreted as a constant. 0x1 LEN The length of the operands. This value serves as an PKA length register index. E.g.: if LEN field value is set to 0, PKA_L[0] holds the size of the operands. 24 26 OPCODE Operation code to be executed by the PKA engine 27 31 Terminate Terminate operation 0x00 AddInc Add or Increment 0x04 SubDecNeg Subtract, Decrement, or Negate 0x05 ModAddInc Modular Add or Modular Increment 0x06 ModSubDecNeg Modular Subtract, Modular Decrement, or Modular Negate 0x07 ANDTST0CLR0 Perform AND, test, or clear 0x08 ORCOPYSET0 Perform OR, copy, or set bits 0x09 XORFLP0INVCMP Perform XOR, flip bits, invert, or compare 0x0A SHR0 Shift right 0 operation 0x0C SHR1 Shift right 1 operation 0x0D SHL0 Shift left 0 operation 0x0E SHL1 Shift left 1 operation 0x0F MulLow Multiply low operation 0x10 ModMul Modular multiply operation 0x11 ModMulN Modular multiply N operation 0x12 ModExp Modular exponentiation operation 0x13 Division Division operation 0x14 ModInv Modular inversion operation 0x15 ModDiv Modular division operation 0x16 MulHigh Multiply high operation 0x17 ModMLAC Modular multiplication acceleration 0x18 ModMLACNR Modular multiplication acceleration where final reduction is omitted 0x19 Reduction Reduction operation 0x1B N_NP_T0_T1_ADDR This register defines the N, Np, T0, and T1 virtual register index. 0x84 read-write 0x000FF820 0x20 N_VIRTUAL_ADDR Register N virtual register index. Default is R0. 0 4 NP_VIRTUAL_ADDR Register Np virtual register index. Default is R1. 5 9 T0_VIRTUAL_ADDR Temporary register 0 virtual register index. Default is R30. 10 14 T1_VIRTUAL_ADDR Temporary register 1 virtual register index. Default is R31. 15 19 PKA_STATUS This register holds the status for the PKA pipeline. 0x88 read-only 0x00001000 0x20 ALU_MSB_4BITS The most significant 4-bits of the operand updated in shift operation. 0 3 ALU_LSB_4BITS The least significant 4-bits of the operand updated in shift operation. 4 7 ALU_SIGN_OUT Indicates the MSB sign of the last operation. 8 8 ALU_CARRY Holds the carry of the last ALU operation. 9 9 ALU_CARRY_MOD Holds the carry of the last modular operation. 10 10 ALU_SUB_IS_ZERO Indicates the last subtraction operation sign. 11 11 ALU_OUT_ZERO Indicates if the result of ALU OUT is zero. 12 12 ALU_MODOVRFLW Modular overflow flag. 13 13 DIV_BY_ZERO Indication if the division is done by zero. 14 14 MODINV_OF_ZERO Indicates the modular inverse of zero. 15 15 OPCODE Opcode of the last operation 16 20 PKA_SW_RESET Reset the PKA engine. 0x8C write-only 0x00000000 0x20 RESET Writing any value to this address resets the PKA engine. The reset takes 4 CPU clock cycles to complete. 0 0 Enable Reset PKA engine. 0x1 0x8 0x4 PKA_L[%s] Description collection: This register holds the operands bit size. 0x90 read-write 0x00000000 0x20 OpSize Operand bit size. 0 12 PKA_PIPE Status register indicating if the PKA pipeline is ready to receive a new OPCODE. 0xB0 read-only 0x00000001 0x20 STATUS PKA pipeline status. 0 0 NotReady PKA pipeline is not ready for a new OPCODE 0x0 Ready PKA pipeline is ready for a new OPCODE 0x1 PKA_DONE Status register indicating if the PKA operation has been completed. 0xB4 read-only 0x00000001 0x20 STATUS PKA operation status. 0 0 Processing PKA operation is processing 0x0 Completed PKA operation is completed and pipeline is empty 0x1 PKA_VERSION PKA engine HW version. Reset value holds the version. 0xC4 read-only 0x16110215 0x20 PKA_VERSION 0 31 PKA_SRAM_WADDR Start address in PKA SRAM for subsequent write transactions. 0xD4 write-only 0x00000000 0x20 ADDR PKA SRAM start address for write transaction 0 31 PKA_SRAM_WDATA Write data to PKA SRAM. Writing to this register triggers a DMA transaction writing data into PKA SRAM. The DMA address offset is automatically incremented during write. 0xD8 write-only 0x00000000 0x20 DATA Data to write to PKA SRAM. 0 31 PKA_SRAM_RDATA Read data from PKA SRAM. Reading from this register triggers a DMA transaction read data from PKA SRAM. The DMA address offset is automatically incremented during read. 0xDC read-only 0x00000000 0x20 DATA Data to read from PKA SRAM 0 31 PKA_SRAM_WCLEAR Register for clearing PKA SRAM write buffer. 0xE0 write-only 0x00000000 0x20 CLEAR Clear the PKA SRAM write buffer. 0 31 PKA_SRAM_RADDR Start address in PKA SRAM for subsequent read transactions. 0xE4 write-only 0x00000000 0x20 ADDR PKA SRAM start address for read transaction 0 31 CC_RNG CRYPTOCELL RNG engine 0x5002B000 CC_AES 0 0x1000 registers CC_RNG 0x20 RNG_IMR Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. 0x100 read-write 0x0000003F 0x20 EHR_VALID_MASK See RNG_ISR for explanation on this interrupt. 0 0 IRQEnable Do not mask EHR interrupt i.e. interrupt is generated 0x0 IRQDisable Mask EHR interrupt i.e. no interrupt is generated 0x1 AUTOCORR_ERR_MASK See RNG_ISR for explanation on this interrupt. 1 1 IRQEnable Do not mask autocorrelation interrupt i.e. interrupt is generated 0x0 IRQDisable Mask autocorrelation interrupt i.e. no interrupt is generated 0x1 CRNGT_ERR_MASK See RNG_ISR for explanation on this interrupt. 2 2 IRQEnable Do not mask the CRNGT error interrupt i.e. interrupt is generated 0x0 IRQDisable Mask the CRNGT error interrupt i.e. no interrupt is generated 0x1 VNC_ERR_MASK See RNG_ISR for explanation on this interrupt. 3 3 IRQEnable Do not mask the von Neumann corrector error interrupt i.e. interrupt is generated 0x0 IRQDisable Mask the von Neumann corrector error interrupt i.e. no interrupt is generated 0x1 WATCHDOG_MASK See RNG_ISR for explanation on this interrupt. 4 4 IRQEnable Do not mask the watchdog interrupt i.e. interrupt is generated 0x0 IRQDisable Mask the watchdog interrupt i.e. no interrupt is generated 0x1 DMA_DONE_MASK See RNG_ISR for explanation on this interrupt. 5 5 IRQEnable Do not mask the RNG DMA completion interrupt i.e. interrupt is generated 0x0 IRQDisable Mask the RNG DMA completion interrupt i.e. no interrupt is generated 0x1 RNG_ISR Interrupt status register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding RNG_IMR bit is unmasked, an interrupt is generated. 0x104 read-only 0x00000000 0x20 EHR_VALID_INT 192-bits have been collected and are ready to be read. 0 0 AUTOCORR_ERR_INT Autocorrelation error. Failure occurs when autocorrelation test has failed four times in a row. Once set, the TRNG ceases to function until next reset. 1 1 CRNGT_ERR_INT Continuous random number generator test error. Failure occurs when two consecutive blocks of 16 collected bits are equal. 2 2 VNC_ERR_INT von Neumann corrector error. Failure occurs if 32 consecutive collected bits are identical, ZERO, or ONE. 3 3 WATCHDOG_INT Maximum number of CPU clock cycles per sample have been exceeded. See RNG_WATCHDOG_VAL for more information. 4 4 DMA_DONE_INT RNG DMA to SRAM is completed. 5 5 RNG_ICR Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in RNG_ISR. 0x108 write-only 0x00000000 0x20 EHR_VALID_CLEAR Writing value '1' clears corresponding bit in RNG_ISR 0 0 AUTOCORR_ERR_CLEAR Cannot be cleared by software! Only RNG reset clears this bit. 1 1 CRNGT_ERR_CLEAR Writing value '1' clears corresponding bit in RNG_ISR 2 2 VNC_ERR_CLEAR Writing value '1' clears corresponding bit in RNG_ISR 3 3 WATCHDOG_CLEAR Writing value '1' clears corresponding bit in RNG_ISR 4 4 DMA_DONE_CLEAR Writing value '1' clears corresponding bit in RNG_ISR 5 5 TRNG_CONFIG TRNG ring oscillator length configuration 0x10C read-write 0x00000000 0x20 ROSC_LEN Set the length of the oscillator ring (= the number of inverters) out of four possible configurations. 0 1 ROSC1 Use shortest ROSC1 ring oscillator configuration. 0x0 ROSC2 Use ROSC2 ring oscillator configuration. 0x1 ROSC3 Use ROSC3 ring oscillator configuration. 0x2 ROSC4 Use longest ROSC4 ring oscillator configuration. 0x3 TRNG_VALID This register indicates if TRNG entropy collection is valid. 0x110 read-only 0x00000000 0x20 EHR_DATA A value of 1 indicates that collection of bits in the TRNG is completed, and data can be read from EHR_DATA registers. 0 0 NotValid Collection of bits not valid. 0x0 Valid Collection of bits valid. 0x1 0x6 0x4 EHR_DATA[%s] Description collection: The entropy holding registers (EHR) hold 192-bits random data collected by the TRNG. The initial EHR_DATA[0] register holds the least significant bits [31:0] of the random data value. 0x114 read-only 0x00000000 0x20 VALUE Random data value. 0 31 NOISE_SOURCE This register controls the ring oscillator circuit used as a noise source. 0x12C read-write 0x00000000 0x20 ENABLE Enable or disable the noise source. 0 0 Disabled Noise source is disabled 0x0 Enabled Noise source is enabled 0x1 SAMPLE_CNT Sample count defining the number of CPU clock cycles between two consecutive noise source samples. 0x130 read-write 0x0000FFFF 0x20 VALUE Number of CPU clock cycles between two consecutive noise source samples. 0 31 AUTOCORR_STATISTIC Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones. 0x134 read-write 0x00000000 0x20 AUTOCORR_TRYS Count each time an autocorrelation test starts. Any write to the field resets the counter. 0 13 AUTOCORR_FAILS Count each time an autocorrelation test fails. Any write to the field resets the counter. 14 21 TRNG_DEBUG Debug register for the TRNG. This register is used to bypass TRNG tests in hardware. 0x138 read-write 0x00000000 0x20 VNC_BYPASS Bypass the von Neumann corrector post-processing test, including the 32 consecutive bits test. 1 1 Disabled von Neumann corrector post-processing is active 0x0 Enabled Bypass the von Neumann corrector 0x1 CRNGT_BYPASS Bypass the Continuous Random Number Generator Test (CRNGT). 2 2 Disabled CRNGT is active 0x0 Enabled Bypass CRNGT 0x1 AUTOCORR_BYPASS Bypass the autocorrelation test. 3 3 Disabled Autocorrelation test is active 0x0 Enabled Bypass the autocorrelation test 0x1 RNG_SW_RESET Reset the RNG engine. 0x140 write-only 0x00000000 0x20 RESET Writing any value to this address resets the RNG engine. The reset takes 4 CPU clock cycles to complete. 0 0 Enable Reset RNG engine. 0x1 RNG_BUSY Status register for RNG engine activity. 0x1B8 read-only 0x00000000 0x20 STATUS RNG engine status. 0 0 Idle RNG engine is idle 0x0 Busy RNG engine is busy 0x1 TRNG_STATUS TRNG status. 1 1 Idle TRNG is idle 0x0 Busy TRNG is busy 0x1 TRNG_RESET Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID. 0x1BC write-only 0x00000000 0x20 RESET Writing any value to this address resets the internal bits counter and registers EHR_DATA and TRNG_VALID. Register NOISE_SOURCE must be disabled in order for the reset to take place. 0 0 Enable Reset TRNG. 0x1 RNG_HW_FLAGS Hardware configuration of RNG engine. Reset value holds the supported features. 0x1C0 read-only 0x0000000F 0x20 EHR_WIDTH Data width supported by the entropy collector 0 0 128Bits 128 bits EHR width 0x0 192Bits 192 bits EHR width 0x1 CRNGT_EXISTS If this flag is set, the engine include support for continuous random number generator test. 1 1 AUTOCORR_EXISTS If this flag is set, the engine include support for autocorrelation test. 2 2 BYPASS_EXISTS If this flag is set, the engine include support for bypassing TRNG tests. 3 3 PRNG_EXISTS If this flag is set, the engine include a pseudo-random number generator. 4 4 KAT_EXISTS If this flag is set, the engine include support for known answer tests. 5 5 RESEEDING_EXISTS If this flag is set, the engine include support for automatic reseeding. 6 6 RNG_USE_5_SBOXES 7 7 Disable 20 SBOX AES 0x0 Enable 5 SBOX AES 0x1 RNG_CLK Control clock for the RNG engine. 0x1C4 write-only 0x00000000 0x20 ENABLE Enables clock for the RNG engine. 0 0 Disable Disable clock for RNG engine. 0x0 Enable Enable clock for RNG engine. 0x1 RNG_DMA Writing to this register enables the RNG DMA engine. 0x1C8 read-write 0x00000000 0x20 ENABLE 0 0 Disable Disable RNG DMA engine 0x0 Enable Enable RNG DMA engine This value is cleared when the RNG DMA engine completes its operation. 0x1 RNG_DMA_ROSC_LEN This register defines which ring oscillator length configuration should be used when using the RNG DMA engine. 0x1CC read-write 0x00000000 0x20 ROSC1 Use shortest ROSC1 ring oscillator configuration. 0 0 Disable Disable ROSC1 0x0 Enable Enable ROSC1 0x1 ROSC2 Use ROSC2 ring oscillator configuration. 1 1 Disable Disable ROSC2 0x0 Enable Enable ROSC2 0x1 ROSC3 Use ROSC3 ring oscillator configuration. 2 2 Disable Disable ROSC3 0x0 Enable Enable ROSC3 0x1 ROSC4 Use longest ROSC4 ring oscillator configuration. 3 3 Disable Disable ROSC4 0x0 Enable Enable ROSC4 0x1 RNG_DMA_SRAM_ADDR This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine. 0x1D0 read-write 0x00000000 0x20 RNG_SRAM_DMA_ADDR Start address of the TRNG data in TRNG SRAM. 0 10 RNG_DMA_SAMPLES_NUM This register defines the number of 192-bits samples that the RNG DMA engine collects per run. 0x1D4 read-write 0x00000000 0x20 RNG_SAMPLES_NUM Defines the number of 192-bits samples that the DMA engine collects per run. 0 7 RNG_WATCHDOG_VAL This register defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. 0x1D8 read-write 0x00000000 0x20 RNG_WATCHDOG_VAL Defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. 0 31 RNG_DMA_BUSY Status register for RNG DMA engine activity. 0x1DC read-only 0x00000000 0x20 STATUS RNG DMA engine status. 0 0 Idle RNG DMA engine is idle 0x0 Busy RNG DMA engine is busy 0x1 ROSC_LEN The active ring oscillator length configuration used by the RNG DMA engine. 1 2 ROSC1 Shortest ROSC1 ring oscillator configuration used. 0x0 ROSC2 ROSC2 ring oscillator configuration used. 0x1 ROSC3 ROSC3 ring oscillator configuration used. 0x2 ROSC4 Longest ROSC4 ring oscillator configuration used. 0x3 NUM_OF_SAMPLES Number of samples already collected using the current ring oscillator configuration. 3 10 CC_RNG_SRAM CRYPTOCELL RNG SRAM interface 0x5002B000 CC_AES 0 0x1000 registers CC_RNG_SRAM 0x20 SRAM_DATA Read/Write data from RNG SRAM 0xF00 read-write 0x00000000 0x20 SRAM_DATA 32 bits DMA read/write from/to RNG SRAM. A 'read' or 'write' operation to this register will trigger the DMA address to be automatically incremented. 0 31 SRAM_ADDR First address given to RNG SRAM DMA for read/write transactions from/to RNG SRAM. 0xF04 write-only 0x00000000 0x20 SRAM_ADDR RNG SRAM starting address 0 14 SRAM_DATA_READY RNG SRAM DMA engine is ready to read/write from/to RNG SRAM. 0xF08 read-only 0x00000001 0x20 SRAM_READY RNG SRAM DMA status. 0 0 Busy DMA is busy 0x0 Idle DMA is idle 0x1 PWM3 Pulse width modulation unit 3 0x4002D000 PWM3 45 SPIM3 Serial Peripheral Interface Master with EasyDMA 3 0x4002F000 SPIM3 47