Nordic Semiconductor Nordic nrf54h20_enga_flpr nRF54h 1 LiliumSOC1 reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 32 32 0x00000000 0xFFFFFFFF NRF_ system_nrf54h20_enga_flpr 480 GLOBAL_FICR_NS Factory Information Configuration Registers 0x0FFFE000 FICR 0 0x800 registers FICR 0x20 BLE Unspecified FICR_BLE read-write 0x00C ADDRTYPE Device address type. 0x000 read-only 0xFFFFFFFF 0x20 TYPE Device address type. 0 0 Public Public address. 0x0 Random Random address. 0x1 0x2 0x4 ADDR[%s] Description collection: 48 bit device address. 0x004 read-only 0xFFFFFFFF 0x20 ADDR Device address [n]. 0 31 0x4 0x4 ER[%s] Description collection: Encryption Root. 0x00C read-only 0xFFFFFFFF 0x20 ER Encryption root word [n]. 0 31 0x4 0x4 IR[%s] Description collection: Identity Root. 0x01C read-only 0xFFFFFFFF 0x20 IR Identity root word [n]. 0 31 NFC Unspecified FICR_NFC read-write 0x040 0x4 0x4 TAGHEADER[%s] Description collection: Default header for NFC Tag. 0x000 read-only 0xFFFFFF5F 0x20 UD0 Unique identifier byte 0 0 7 UD1 Unique identifier byte 1 8 15 UD2 Unique identifier byte 2 16 23 UD3 Unique identifier byte 3 24 31 INFO Device info FICR_INFO read-write 0x050 CONFIGID Configuration identifier 0x000 read-only 0xFFFFFFFF 0x20 HWID Identification number for the HW 0 15 PART Part code 0x004 read-only 0xFFFFFFFF 0x20 PART Part code 0 31 Unspecified Unspecified 0xFFFFFFFF VARIANT Part Variant, Hardware version and Production configuration 0x008 read-only 0xFFFFFFFF 0x20 VARIANT Part Variant, Hardware version and Production configuration, encoded as ASCII 0 31 Unspecified Unspecified 0xFFFFFFFF PACKAGE Package option 0x00C read-only 0xFFFFFFFF 0x20 PACKAGE Package option 0 31 Unspecified Unspecified 0xFFFFFFFF RAM RAM variant 0x010 read-only 0xFFFFFFFF 0x20 RAM RAM variant 0 31 Unspecified Unspecified 0xFFFFFFFF MRAM MRAM variant 0x014 read-only 0xFFFFFFFF 0x20 MRAM MRAM variant 0 31 Unspecified Unspecified 0xFFFFFFFF CODEPAGESIZE Code memory page size in bytes 0x018 read-only 0x00001000 0x20 CODEPAGESIZE Code memory page size in bytes 0 31 Unspecified Unspecified 0xFFFFFFFF CODESIZE Code memory size 0x01C read-only 0x00000100 0x20 CODESIZE Code memory size in number of pages 0 31 Unspecified Unspecified 0xFFFFFFFF DEVICETYPE Device type 0x020 read-only 0x00000000 0x20 DEVICETYPE Device type 0 31 Die Device is an physical DIE 0x00000000 FPGA Device is an FPGA 0xFFFFFFFF TRIM Unspecified FICR_TRIM read-write 0x100 GLOBAL Unspecified FICR_TRIM_GLOBAL read-write 0x284 SAADC Unspecified FICR_TRIM_GLOBAL_SAADC read-write 0x0 CALVREF Trim value for GLOBAL.SAADC.CALVREF 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 0x3 0x4 CALGAIN[%s] Description collection: Trim value for GLOBAL.SAADC.CALGAIN 0x4 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 CALOFFSET Trim value for GLOBAL.SAADC.CALOFFSET 0x10 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 0x6 0x4 LINCALCOEFF[%s] Description collection: Trim value for GLOBAL.SAADC.LINCALCOEFF 0x14 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 CALIREF Trim value for GLOBAL.SAADC.CALIREF 0x2C read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 CALVREFTC Trim value for GLOBAL.SAADC.CALVREFTC 0x30 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 NFCT Unspecified FICR_TRIM_GLOBAL_NFCT read-write 0x38 BIASCFG Trim value for NFCT.BIASCFG 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 CANPLL Unspecified FICR_TRIM_GLOBAL_CANPLL read-write 0x3C TRIM Unspecified FICR_TRIM_GLOBAL_CANPLL_TRIM read-write 0x0 CTUNE Trim value for GLOBAL.CANPLL.CTUNE 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 COMP Unspecified FICR_TRIM_GLOBAL_COMP read-write 0x4C REFTRIM Trim value for GLOBAL.COMP.REFTRIM 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 RCALTRIM Trim value used during production test 0x4 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 APPLICATION Unspecified FICR_TRIM_APPLICATION read-write 0x2D8 HSFLL Unspecified FICR_TRIM_APPLICATION_HSFLL read-write 0x0 TRIM Unspecified FICR_TRIM_APPLICATION_HSFLL_TRIM read-write 0x0 VSUP Trim value for APPLICATION.HSFLL.VSUP 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 0x6 0x4 COARSE[%s] Description collection: Trim value for APPLICATION.HSFLL.COARSE 0x4 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 0x6 0x4 FINE[%s] Description collection: Trim value for APPLICATION.HSFLL.FINE 0x1C read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 MEMCONF Unspecified FICR_TRIM_APPLICATION_MEMCONF read-write 0x34 3 0x004 BLOCKTYPE[%s] Unspecified FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE read-write 0x0 TRIM Description cluster: Trim value for APPLICATION.MEMCONF.TRIM 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 RADIOCORE Unspecified FICR_TRIM_RADIOCORE read-write 0x318 HSFLL Unspecified FICR_TRIM_RADIOCORE_HSFLL read-write 0x0 TRIM Unspecified FICR_TRIM_RADIOCORE_HSFLL_TRIM read-write 0x0 VSUP Trim value for RADIOCORE.HSFLL.VSUP 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 0x6 0x4 COARSE[%s] Description collection: Trim value for RADIOCORE.HSFLL.COARSE 0x4 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 0x6 0x4 FINE[%s] Description collection: Trim value for RADIOCORE.HSFLL.FINE 0x1C read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 MEMCONF Unspecified FICR_TRIM_RADIOCORE_MEMCONF read-write 0x34 3 0x004 BLOCKTYPE[%s] Unspecified FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE read-write 0x0 TRIM Description cluster: Trim value for RADIOCORE.MEMCONF.TRIM 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 RADIO Unspecified FICR_TRIM_RADIOCORE_RADIO read-write 0x40 SPHYNXANA Unspecified FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA read-write 0x0 FSCTRL0 Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL0 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 FSCTRL1 Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL1 0x4 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 FSCTRL2 Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL2 0x8 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 RXCTRL Trim value for RADIOCORE.RADIO.SPHYNXANA.RXCTRL 0xC read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 OVRRXTRIMCODE Trim value for RADIOCORE.RADIO.SPHYNXANA.OVRRXTRIMCODE 0x10 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 RXAGC Unspecified FICR_TRIM_RADIOCORE_RADIO_RXAGC read-write 0x14 CALIBRATION Trim value for RSSICAL and ED154CAL in RADIOCORE.RADIO.RXAGC.CALIBRATION 0x0 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 PVTTOT Trim value for RADIOCORE.RADIO.EXPECTEDPVTTOTRATIO 0x18 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 KDTC Trim value for RADIOCORE.RADIO.ESTKDTCVAL 0x1C read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 TXHFGAIN Trim value for RADIOCORE.RADIO.TXINTERFACEHFGAIN 0x20 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 PVTTOFIX Trim value for RADIOCORE.RADIO.ADPLLSTARTUPCOMMAND6 0x24 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 LOOPGAIN Trim value for RADIOCORE.RADIO.ADPLLSTARTUPCOMMAND5 0x28 read-only 0xFFFFFFFF 0x20 VALUE Trim value 0 31 GLOBAL_USBHSCORE0_NS USBHSCORE 0 0x2F700000 USBHSCORE 0 0x24000 registers USBHSCORE 0x20 GOTGCTL OTG Control and Status Register 0x000 read-write 0x000D0000 0x20 SESREQSCS Mode: Device only. Session Request Success (SesReqScs) 0 0 read-only FAIL Unspecified 0x0 SUCCESS Unspecified 0x1 SESREQ Mode: Device only. Session Request (SesReq) 1 1 NOREQUEST Unspecified 0x0 REQUEST Unspecified 0x1 VBVALIDOVEN Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn) 2 2 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 VBVALIDOVVAL Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal) 3 3 SET0 Unspecified 0x0 SET1 Unspecified 0x1 AVALIDOVEN Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn) 4 4 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 AVALIDOVVAL Mode: Host only A-Peripheral Session Valid OverrideValue (AvalidOvVal) 5 5 VALUE0 Unspecified 0x0 VALUE1 Unspecified 0x1 BVALIDOVEN Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn) 6 6 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 BVALIDOVVAL Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal) 7 7 VALUE0 Unspecified 0x0 VALUE1 Unspecified 0x1 DBNCEFLTRBYPASS Mode: Host and Device 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 CONIDSTS Mode: Host and Device. Connector ID Status (ConIDSts) 16 16 read-only MODEA Unspecified 0x0 MODEB Unspecified 0x1 DBNCTIME Mode: Host only. Long/Short Debounce Time (DbncTime) 17 17 read-only LONG Unspecified 0x0 SHORT Unspecified 0x1 ASESVLD Mode: Host only. A-Session Valid (ASesVld) 18 18 read-only NOTVALID Unspecified 0x0 VALID Unspecified 0x1 BSESVLD Mode: Device only. B-Session Valid (BSesVld) 19 19 read-only NOTVALID Unspecified 0x0 VALID Unspecified 0x1 OTGVER OTG Version (OTGVer) 20 20 VER13 Unspecified 0x0 VER20 Unspecified 0x1 CURMOD Current Mode of Operation (CurMod) 21 21 read-only DEVICEMODE Unspecified 0x0 HOSTMODE Unspecified 0x1 MULTVALIDBC Mode: Host and Device. Multi Valued ID pin (MultValIdBC) 22 26 read-only RID_C Unspecified 0x01 RID_B Unspecified 0x02 RID_A Unspecified 0x04 RID_GND Unspecified 0x08 RID_FLOAT Unspecified 0x10 CHIRPEN Mode: Device Only 27 27 CHIRP_DISABLE Unspecified 0x0 CHIRP_ENABLE Unspecified 0x1 GOTGINT OTG Interrupt Register 0x004 read-write 0x00000000 0x20 SESENDDET Mode: Host and Device. Session End Detected (SesEndDet) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SESREQSUCSTSCHNG Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 HSTNEGSUCSTSCHNG Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 HSTNEGDET Mode:Host and Device. Host Negotiation Detected (HstNegDet) 17 17 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 ADEVTOUTCHG Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg) 18 18 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DBNCEDONE Mode: Host only. Debounce Done (DbnceDone) 19 19 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 MULTVALIPCHNG This bit when set indicates that there is a change in the value of at least one ACA pin value. 20 20 NO_ACA_PIN_CHANGE Unspecified 0x0 ACA_PIN_CHANGE Unspecified 0x1 GAHBCFG AHB Configuration Register 0x008 read-write 0x00000000 0x20 GLBLINTRMSK Mode: Host and device. Global Interrupt Mask (GlblIntrMsk) 0 0 MASK Unspecified 0x0 NOMASK Unspecified 0x1 HBSTLEN Mode: Host and device. Burst Length/Type (HBstLen) 1 4 WORD1ORSINGLE Unspecified 0x0 WORD4ORINCR Unspecified 0x1 WORD8 Unspecified 0x2 WORD16ORINCR4 Unspecified 0x3 WORD32 Unspecified 0x4 WORD64ORINCR8 Unspecified 0x5 WORD128 Unspecified 0x6 WORD256ORINCR16 Unspecified 0x7 WORDX Unspecified 0x8 DMAEN Mode: Host and device. DMA Enable (DMAEn) 5 5 SLAVEMODE Unspecified 0x0 DMAMODE Unspecified 0x1 NPTXFEMPLVL Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) 7 7 HALFEMPTY Unspecified 0x0 EMPTY Unspecified 0x1 REMMEMSUPP Mode: Host and Device. Remote Memory Support (RemMemSupp) 21 21 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 NOTIALLDMAWRIT Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit) 22 22 LASTTRANS Unspecified 0x0 ALLTRANS Unspecified 0x1 AHBSINGLE Mode: Host and Device. AHB Single Support (AHBSingle) 23 23 INCRBURST Unspecified 0x0 SINGLEBURST Unspecified 0x1 GUSBCFG USB Configuration Register 0x00C read-write 0x00001400 0x20 TOUTCAL Mode: Host and Device. HS/FS Timeout Calibration (TOutCal) 0 2 PHYIF Mode: Host and Device. PHY Interface (PHYIf) 3 3 BITS8 Unspecified 0x0 BITS16 Unspecified 0x1 ULPIUTMISEL Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel) 4 4 read-only UTMI Unspecified 0x0 ULPI Unspecified 0x1 FSINTF Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf) 5 5 read-only FS6PIN Unspecified 0x0 FS3PIN Unspecified 0x1 PHYSEL PHYSel 6 6 read-only USB20 Unspecified 0x0 USB11 Unspecified 0x1 USBTRDTIM Mode: Device only. USB Turnaround Time (USBTrdTim) 10 13 TURNTIME16BIT Unspecified 0x5 TURNTIME8BIT Unspecified 0x9 PHYLPWRCLKSEL PHY Low-Power Clock Select (PhyLPwrClkSel) 15 15 INTPLLCLK Unspecified 0x0 EXTCLK Unspecified 0x1 TERMSELDLPULSE Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse) 22 22 TXVALID Unspecified 0x0 TERMSEL Unspecified 0x1 ICUSBCAP Mode: Host and Device. IC_USB-Capable (IC_USBCap) 26 26 read-only NOTSELECTED Unspecified 0x0 SELECTED Unspecified 0x1 TXENDDELAY Mode: Device only. Tx End Delay (TxEndDelay) 28 28 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 FORCEHSTMODE Mode: Host and device. Force Host Mode (ForceHstMode) 29 29 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 FORCEDEVMODE Mode:Host and device. Force Device Mode (ForceDevMode) 30 30 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 CORRUPTTXPKT Mode: Host and device. Corrupt Tx packet (CorruptTxPkt) 31 31 write-only Disabled Unspecified 0x0 Enabled Unspecified 0x1 GRSTCTL Reset Register 0x010 read-write 0x80000000 0x20 CSFTRST Mode: Host and Device. Core Soft Reset (CSftRst) 0 0 NOTACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PIUFSSFTRST Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) 1 1 RESET_INACTIVE Unspecified 0x0 RESET_ACTIVE Unspecified 0x1 FRMCNTRRST Mode: Host only. Host Frame Counter Reset (FrmCntrRst) 2 2 NOTACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RXFFLSH Mode: Host and Device. RxFIFO Flush (RxFFlsh) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFFLSH Mode: Host and Device. TxFIFO Flush (TxFFlsh) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM Mode: Host and Device. TxFIFO Number (TxFNum) 6 10 TXF0 Unspecified 0x00 TXF1 Unspecified 0x01 TXF2 Unspecified 0x02 TXF3 Unspecified 0x03 TXF4 Unspecified 0x04 TXF5 Unspecified 0x05 TXF6 Unspecified 0x06 TXF7 Unspecified 0x07 TXF8 Unspecified 0x08 TXF9 Unspecified 0x09 TXF10 Unspecified 0x0A TXF11 Unspecified 0x0B TXF12 Unspecified 0x0C TXF13 Unspecified 0x0D TXF14 Unspecified 0x0E TXF15 Unspecified 0x0F TXF16 Unspecified 0x10 CSFTRSTDONE Mode: Host and Device 29 29 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DMAREQ Mode: Host and Device. DMA Request Signal (DMAReq) 30 30 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBIDLE Mode: Host and Device. AHB Master Idle (AHBIdle) 31 31 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 GINTSTS Interrupt Register 0x014 read-write 0x00000020 0x20 CURMOD Mode: Host and Device. Current Mode of Operation (CurMod) 0 0 read-only DEVICE Unspecified 0x0 HOST Unspecified 0x1 MODEMIS Mode: Host and Device. Mode Mismatch Interrupt (ModeMis) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OTGINT Mode: Host and Device. OTG Interrupt (OTGInt) 2 2 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SOF Mode: Host and Device. Start of (micro)Frame (Sof) 3 3 INTACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RXFLVL Mode: Host and Device. RxFIFO Non-Empty (RxFLvl) 4 4 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NPTXFEMP Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp) 5 5 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 GINNAKEFF Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff) 6 6 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 GOUTNAKEFF Mode: Device only. Global OUT NAK Effective (GOUTNakEff) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 ERLYSUSP Mode: Device only. Early Suspend (ErlySusp) 10 10 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 USBSUSP Mode: Device only. USB Suspend (USBSusp) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 USBRST Mode: Device only. USB Reset (USBRst) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 ENUMDONE Mode: Device only. Enumeration Done (EnumDone) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 ISOOUTDROP Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EOPF Mode: Device only. End of Periodic Frame Interrupt (EOPF) 15 15 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSTRDONEINT Mode: Device only. Restore Done Interrupt (RstrDoneInt) 16 16 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPMIS Mode: Device only. Endpoint Mismatch Interrupt (EPMis) 17 17 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 IEPINT Mode: Device only. IN Endpoints Interrupt (IEPInt) 18 18 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OEPINT Mode: Device only. OUT Endpoints Interrupt (OEPInt) 19 19 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INCOMPISOIN Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN) 20 20 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INCOMPLP Incomplete Periodic Transfer (incomplP) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 FETSUSP Mode: Device only. Data Fetch Suspended (FetSusp) 22 22 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RESETDET Mode: Device only. Reset detected Interrupt (ResetDet) 23 23 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PRTINT Mode: Host only. Host Port Interrupt (PrtInt) 24 24 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 HCHINT Mode: Host only. Host Channels Interrupt (HChInt) 25 25 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 LPMINT Mode: Host and Device 27 27 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CONIDSTSCHNG Mode: Host and Device. Connector ID Status Change (ConIDStsChng) 28 28 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DISCONNINT Mode: Host only. Disconnect Detected Interrupt (DisconnInt) 29 29 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SESSREQINT Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 WKUPINT Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 GINTMSK Interrupt Mask Register 0x018 read-write 0x00000000 0x20 MODEMISMSK Mode: Host and Device 1 1 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OTGINTMSK Mode: Host and Device 2 2 MASK Unspecified 0x0 NOMASK Unspecified 0x1 SOFMSK Mode: Host and Device 3 3 MASK Unspecified 0x0 NOMASK Unspecified 0x1 RXFLVLMSK Mode: Host and Device 4 4 MASK Unspecified 0x0 NOMASK Unspecified 0x1 NPTXFEMPMSK Mode: Host and Device 5 5 MASK Unspecified 0x0 NOMASK Unspecified 0x1 GINNAKEFFMSK Mode: Device only, 6 6 MASK Unspecified 0x0 NOMASK Unspecified 0x1 GOUTNAKEFFMSK Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk) 7 7 MASK Unspecified 0x0 NOMASK Unspecified 0x1 ERLYSUSPMSK Mode: Device only. Early Suspend Mask (ErlySuspMsk) 10 10 MASK Unspecified 0x0 NOMASK Unspecified 0x1 USBSUSPMSK Mode: Device only. USB Suspend Mask (USBSuspMsk) 11 11 MASK Unspecified 0x0 NOMASK Unspecified 0x1 USBRSTMSK Mode: Device only. USB Reset Mask (USBRstMsk) 12 12 MASK Unspecified 0x0 NOMASK Unspecified 0x1 ENUMDONEMSK Mode: Device only. Enumeration Done Mask (EnumDoneMsk) 13 13 MASK Unspecified 0x0 NOMASK Unspecified 0x1 ISOOUTDROPMSK Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) 14 14 MASK Unspecified 0x0 NOMASK Unspecified 0x1 EOPFMSK Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) 15 15 MASK Unspecified 0x0 NOMASK Unspecified 0x1 RSTRDONEINTMSK Mode: Host and Device 16 16 MASK Unspecified 0x0 NOMASK Unspecified 0x1 EPMISMSK Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk) 17 17 MASK Unspecified 0x0 NOMASK Unspecified 0x1 IEPINTMSK Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk) 18 18 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OEPINTMSK Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk) 19 19 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INCOMPLPMSK Incomplete Periodic Transfer Mask (incomplPMsk) 21 21 MASK Unspecified 0x0 NOMASK Unspecified 0x1 FETSUSPMSK Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk) 22 22 MASK Unspecified 0x0 NOMASK Unspecified 0x1 RESETDETMSK Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk) 23 23 MASK Unspecified 0x0 NOMASK Unspecified 0x1 PRTINTMSK Mode: Host only. Host Port Interrupt Mask (PrtIntMsk) 24 24 MASK Unspecified 0x0 NOMASK Unspecified 0x1 HCHINTMSK Mode: Host only. Host Channels Interrupt Mask (HChIntMsk) 25 25 MASK Unspecified 0x0 NOMASK Unspecified 0x1 LPMINTMSK Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int) 27 27 MASK Unspecified 0x0 NOMASK Unspecified 0x1 CONIDSTSCHNGMSK Mode: Host and Device 28 28 MASK Unspecified 0x0 NOMASK Unspecified 0x1 DISCONNINTMSK Mode: Host and Device 29 29 MASK Unspecified 0x0 NOMASK Unspecified 0x1 SESSREQINTMSK Mode: Host and Device 30 30 MASK Unspecified 0x0 NOMASK Unspecified 0x1 WKUPINTMSK Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) 31 31 MASK Unspecified 0x0 NOMASK Unspecified 0x1 GRXSTSR Receive Status Debug Read Register 0x01C read-write 0x00000000 0x20 CHNUM Channel Number (ChNum) 0 3 read-only CHEP0 Unspecified 0x0 CHEP1 Unspecified 0x1 CHEP2 Unspecified 0x2 CHEP3 Unspecified 0x3 CHEP4 Unspecified 0x4 CHEP5 Unspecified 0x5 CHEP6 Unspecified 0x6 CHEP7 Unspecified 0x7 CHEP8 Unspecified 0x8 CHEP9 Unspecified 0x9 CHEP10 Unspecified 0xA CHEP11 Unspecified 0xB CHEP12 Unspecified 0xC CHEP13 Unspecified 0xD CHEP14 Unspecified 0xE CHEP15 Unspecified 0xF BCNT Byte Count (BCnt) 4 14 read-only DPID Data PID (DPID) 15 16 read-only DATA0 Unspecified 0x0 DATA2 Unspecified 0x1 DATA1 Unspecified 0x2 MDATA Unspecified 0x3 PKTSTS Packet Status (PktSts) indicates the status of the received packet. 17 20 read-only OUTNAK Unspecified 0x1 INOUTDPRX Unspecified 0x2 INOUTTRCOM Unspecified 0x3 DSETUPCOM Unspecified 0x4 DTTOG Unspecified 0x5 DSETUPRX Unspecified 0x6 CHHALT Unspecified 0x7 FN Mode: Device only. Frame Number (FN) 21 24 read-only GRXSTSP Receive Status Read/Pop Register 0x020 read-write 0x00000000 0x20 CHNUM Channel Number (ChNum) 0 3 read-only CHEP0 Unspecified 0x0 CHEP1 Unspecified 0x1 CHEP2 Unspecified 0x2 CHEP3 Unspecified 0x3 CHEP4 Unspecified 0x4 CHEP5 Unspecified 0x5 CHEP6 Unspecified 0x6 CHEP7 Unspecified 0x7 CHEP8 Unspecified 0x8 CHEP9 Unspecified 0x9 CHEP10 Unspecified 0xA CHEP11 Unspecified 0xB CHEP12 Unspecified 0xC CHEP13 Unspecified 0xD CHEP14 Unspecified 0xE CHEP15 Unspecified 0xF BCNT Byte Count (BCnt) 4 14 read-only DPID Data PID (DPID) 15 16 read-only DATA0 Unspecified 0x0 DATA2 Unspecified 0x1 DATA1 Unspecified 0x2 MDATA Unspecified 0x3 PKTSTS Packet Status (PktSts) indicates the status of the received packet. 17 20 read-only OUTNAK Unspecified 0x1 INOUTDPRX Unspecified 0x2 INOUTTRCOM Unspecified 0x3 DSETUPCOM Unspecified 0x4 DTTOG Unspecified 0x5 FN Mode: Device only. Frame Number (FN) 21 24 read-only GRXFSIZ Receive FIFO Size Register 0x024 read-write 0x00000224 0x20 RXFDEP Mode: Host and Device. RxFIFO Depth (RxFDep) 0 9 GNPTXFSIZ Non-periodic Transmit FIFO Size Register 0x028 read-write 0x02000224 0x20 NPTXFSTADDR Non-periodic Transmit RAM Start Address (NPTxFStAddr) 0 9 NPTXFDEP Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep) 16 25 GNPTXSTS Non-periodic Transmit FIFO/Queue Status Register 0x02C read-write 0x00080200 0x20 NPTXFSPCAVAIL Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) 0 15 read-only NPTXQSPCAVAIL Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) 16 23 read-only FULL Unspecified 0x00 QUE1 Unspecified 0x01 QUE2 Unspecified 0x02 QUE3 Unspecified 0x03 QUE4 Unspecified 0x04 QUE5 Unspecified 0x05 QUE6 Unspecified 0x06 QUE7 Unspecified 0x07 QUE8 Unspecified 0x08 NPTXQTOP Top of the Non-periodic Transmit Request Queue (NPTxQTop) 24 30 read-only INOUTTK Unspecified 0x00 ZEROTX Unspecified 0x01 PINGCSPLIT Unspecified 0x02 CHNHALT Unspecified 0x03 GGPIO General Purpose Input/Output Register 0x038 read-write 0x00000000 0x20 GPI General Purpose Input (GPI) 0 15 read-only GPO General Purpose Output (GPO) 16 31 GUID User ID Register 0x03C read-write 0x12345678 0x20 GUID User ID (UserID) 0 31 GSNPSID Synopsys ID Register 0x040 read-write 0x4F54400A 0x20 SYNOPSYSID Release number of the controller being used currently. 0 31 read-only GHWCFG1 User Hardware Configuration 1 Register 0x044 read-write 0xAA555000 0x20 EPDIR This 32-bit field uses two bits per 0 31 read-only GHWCFG2 User Hardware Configuration 2 Register 0x048 read-write 0x228BFC72 0x20 OTGMODE Mode of Operation (OtgMode). - 3b000: 0 2 read-only HNPSRP Unspecified 0x0 SRPOTG Unspecified 0x1 NHNPNSRP Unspecified 0x2 SRPCAPD Unspecified 0x3 NONOTGD Unspecified 0x4 SRPCAPH Unspecified 0x5 NONOTGH Unspecified 0x6 OTGARCH Architecture (OtgArch) 3 4 read-only SLAVEMODE Unspecified 0x0 EXTERNALDMA Unspecified 0x1 INTERNALDMA Unspecified 0x2 SINGPNT Point-to-Point (SingPnt) 5 5 read-only MULTIPOINT Unspecified 0x0 SINGLEPOINT Unspecified 0x1 HSPHYTYPE High-Speed PHY Interface Type (HSPhyType) 6 7 read-only NOHS Unspecified 0x0 UTMIPLUS Unspecified 0x1 ULPI Unspecified 0x2 UTMIPUSULPI Unspecified 0x3 FSPHYTYPE Full-Speed PHY Interface Type (FSPhyType) 8 9 read-only NO_FS Unspecified 0x0 FS Unspecified 0x1 FSPLUSUTMI Unspecified 0x2 FSPLUSULPI Unspecified 0x3 NUMDEVEPS Number of Device Endpoints (NumDevEps) 10 13 read-only ENDPT0 Unspecified 0x0 ENDPT1 Unspecified 0x1 ENDPT2 Unspecified 0x2 ENDPT3 Unspecified 0x3 ENDPT4 Unspecified 0x4 ENDPT5 Unspecified 0x5 ENDPT6 Unspecified 0x6 ENDPT7 Unspecified 0x7 ENDPT8 Unspecified 0x8 ENDPT9 Unspecified 0x9 ENDPT10 Unspecified 0xA ENDPT11 Unspecified 0xB ENDPT12 Unspecified 0xC ENDPT13 Unspecified 0xD ENDPT14 Unspecified 0xE ENDPT15 Unspecified 0xF NUMHSTCHNL Number of Host Channels (NumHstChnl) 14 17 read-only HOSTCH0 Unspecified 0x0 HOSTCH1 Unspecified 0x1 HOSTCH2 Unspecified 0x2 HOSTCH3 Unspecified 0x3 HOSTCH4 Unspecified 0x4 HOSTCH5 Unspecified 0x5 HOSTCH6 Unspecified 0x6 HOSTCH7 Unspecified 0x7 HOSTCH8 Unspecified 0x8 HOSTCH9 Unspecified 0x9 HOSTCH10 Unspecified 0xA HOSTCH11 Unspecified 0xB HOSTCH12 Unspecified 0xC HOSTCH13 Unspecified 0xD HOSTCH14 Unspecified 0xE HOSTCH15 Unspecified 0xF PERIOSUPPORT Periodic OUT Channels Supported in Host Mode (PerioSupport) 18 18 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DYNFIFOSIZING Dynamic FIFO Sizing Enabled (DynFifoSizing) 19 19 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 MULTIPROCINTRPT Multi Processor Interrupt Enabled (MultiProcIntrpt) 20 20 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 NPTXQDEPTH Non-periodic Request Queue Depth (NPTxQDepth) 22 23 read-only TWO Unspecified 0x0 FOUR Unspecified 0x1 EIGHT Unspecified 0x2 PTXQDEPTH Host Mode Periodic Request Queue Depth (PTxQDepth) 24 25 read-only QUE2 Unspecified 0x0 QUE4 Unspecified 0x1 QUE8 Unspecified 0x2 QUE16 Unspecified 0x3 TKNQDEPTH Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) 26 30 read-only GHWCFG3 User Hardware Configuration 3 Register 0x04C read-write 0x0BEAC0E8 0x20 XFERSIZEWIDTH Width of Transfer Size Counters (XferSizeWidth) 0 3 read-only WIDTH11 Unspecified 0x0 WIDTH12 Unspecified 0x1 WIDTH13 Unspecified 0x2 WIDTH14 Unspecified 0x3 WIDTH15 Unspecified 0x4 WIDTH16 Unspecified 0x5 WIDTH17 Unspecified 0x6 WIDTH18 Unspecified 0x7 WIDTH19 Unspecified 0x8 PKTSIZEWIDTH Width of Packet Size Counters (PktSizeWidth) 4 6 read-only BITS4 Unspecified 0x0 BITS5 Unspecified 0x1 BITS6 Unspecified 0x2 BITS7 Unspecified 0x3 BITS8 Unspecified 0x4 BITS9 Unspecified 0x5 BITS10 Unspecified 0x6 OTGEN OTG Function Enabled (OtgEn) 7 7 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 I2CINTSEL I2C Selection (I2CIntSel) 8 8 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 VNDCTLSUPT Vendor Control Interface Support (VndctlSupt) 9 9 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 OPTFEATURE Optional Features Removed (OptFeature) 10 10 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 RSTTYPE Reset Style for Clocked always Blocks in RTL (RstType) 11 11 read-only ASYNCRST Unspecified 0x0 SYNCRST Unspecified 0x1 ADPSUPPORT This bit indicates whether ADP logic is present within or external to the controller 12 12 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 HSICMODE HSIC mode specified for Mode of Operation 13 13 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 BCSUPPORT This bit indicates the controller support for Battery Charger. 14 14 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 LPMMODE LPM mode specified for Mode of Operation. 15 15 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DFIFODEPTH DFIFO Depth (DfifoDepth - EP_LOC_CNT) 16 31 read-only GHWCFG4 User Hardware Configuration 4 Register 0x050 read-write 0x1FF0AA60 0x20 NUMDEVPERIOEPS Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) 0 3 read-only Value0 Unspecified 0x0 Value1 Unspecified 0x1 Value2 Unspecified 0x2 Value3 Unspecified 0x3 Value4 Unspecified 0x4 Value5 Unspecified 0x5 Value6 Unspecified 0x6 Value7 Unspecified 0x7 Value8 Unspecified 0x8 Value9 Unspecified 0x9 Value10 Unspecified 0xA Value11 Unspecified 0xB Value12 Unspecified 0xC Value13 Unspecified 0xD Value14 Unspecified 0xE Value15 Unspecified 0xF PARTIALPWRDN Enable Partial Power Down (PartialPwrDn) 4 4 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 AHBFREQ Minimum AHB Frequency Less Than 60 MHz (AhbFreq) 5 5 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 HIBERNATION Enable Hibernation (Hibernation) 6 6 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EXTENDEDHIBERNATION Enable Hibernation 7 7 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 ENHANCEDLPMSUPT1 Enhanced LPM Support1 (EnhancedLPMSupt1) 9 9 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SERVINTFLOW Service Interval Flow 10 10 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 IPGISOCSUPT Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt) 11 11 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 ACGSUPT Active Clock Gating Support 12 12 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 ENHANCEDLPMSUPT Enhanced LPM Support (EnhancedLPMSupt) 13 13 read-only ENABLED Unspecified 0x1 PHYDATAWIDTH UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width 14 15 read-only WIDTH1 Unspecified 0x0 WIDTH2 Unspecified 0x1 WIDTH3 Unspecified 0x2 NUMCTLEPS Number of Device Mode Control Endpoints in Addition to 16 19 read-only ENDPT0 Unspecified 0x0 ENDPT1 Unspecified 0x1 ENDPT2 Unspecified 0x2 ENDPT3 Unspecified 0x3 ENDPT4 Unspecified 0x4 ENDPT5 Unspecified 0x5 ENDPT6 Unspecified 0x6 ENDPT7 Unspecified 0x7 ENDPT8 Unspecified 0x8 ENDPT9 Unspecified 0x9 ENDPT10 Unspecified 0xA ENDPT11 Unspecified 0xB ENDPT12 Unspecified 0xC ENDPT13 Unspecified 0xD ENDPT14 Unspecified 0xE ENDPT15 Unspecified 0xF IDDGFLTR IDDIG Filter Enable (IddgFltr) 20 20 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 VBUSVALIDFLTR VBUS Valid Filter Enabled (VBusValidFltr) 21 21 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 AVALIDFLTR a_valid Filter Enabled (AValidFltr) 22 22 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 BVALIDFLTR b_valid Filter Enabled (BValidFltr) 23 23 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SESSENDFLTR session_end Filter Enabled (SessEndFltr) 24 24 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DEDFIFOMODE Enable Dedicated Transmit FIFO for device IN Endpoints 25 25 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 INEPS Number of Device Mode IN Endpoints Including Control Endpoints (INEps) 26 29 read-only ENDPT1 Unspecified 0x0 ENDPT2 Unspecified 0x1 ENDPT3 Unspecified 0x2 ENDPT4 Unspecified 0x3 ENDPT5 Unspecified 0x4 ENDPT6 Unspecified 0x5 ENDPT7 Unspecified 0x6 ENDPT8 Unspecified 0x7 ENDPT9 Unspecified 0x8 ENDPT10 Unspecified 0x9 ENDPT11 Unspecified 0xA ENDPT12 Unspecified 0xB ENDPT13 Unspecified 0xC ENDPT14 Unspecified 0xD ENDPT15 Unspecified 0xE ENDPT16 Unspecified 0xF DESCDMAENABLED Scatter/Gather DMA configuration 30 30 read-only DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 DESCDMA Scatter/Gather DMA configuration 31 31 read-only CONFIG1 Unspecified 0x0 CONFIG2 Unspecified 0x1 GLPMCFG LPM Config Register 0x054 read-write 0x00000000 0x20 LPMCAP LPM-Capable (LPMCap) 0 0 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 APPL1RES Mode: Device only. LPM response programmed by application (AppL1Res) 1 1 NYET_RESP Unspecified 0x0 ACK_RESP Unspecified 0x1 HIRD Host-Initiated Resume Duration (HIRD) 2 5 BREMOTEWAKE RemoteWakeEnable (bRemoteWake) 6 6 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 ENBLSLPM Enable utmi_sleep_n (EnblSlpM) 7 7 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 HIRDTHRES BESL/HIRD Threshold (HIRD_Thres) 8 12 COREL1RES LPM Response (CoreL1Res) 13 14 read-only LPMRESP1 Unspecified 0x0 LPMRESP2 Unspecified 0x1 LPMRESP3 Unspecified 0x2 LPMRESP4 Unspecified 0x3 SLPSTS Port Sleep Status (SlpSts) 15 15 read-only CORE_NOT_IN_L1 Unspecified 0x0 CORE_IN_L1 Unspecified 0x1 L1RESUMEOK Sleep State Resume OK (L1ResumeOK) 16 16 read-only NOTOK Unspecified 0x0 OK Unspecified 0x1 LPMCHNLINDX LPM Channel Index 17 20 CH0 Unspecified 0x0 CH1 Unspecified 0x1 CH2 Unspecified 0x2 CH3 Unspecified 0x3 CH4 Unspecified 0x4 CH5 Unspecified 0x5 CH6 Unspecified 0x6 CH7 Unspecified 0x7 CH8 Unspecified 0x8 CH9 Unspecified 0x9 CH10 Unspecified 0xA CH11 Unspecified 0xB CH12 Unspecified 0xC CH13 Unspecified 0xD CH14 Unspecified 0xE CH15 Unspecified 0xF LPMRETRYCNT LPM Retry Count (LPM_Retry_Cnt) 21 23 RETRY0 Unspecified 0x0 RETRY1 Unspecified 0x1 RETRY2 Unspecified 0x2 RETRY3 Unspecified 0x3 RETRY4 Unspecified 0x4 RETRY5 Unspecified 0x5 RETRY6 Unspecified 0x6 RETRY7 Unspecified 0x7 SNDLPM Send LPM Transaction (SndLPM) 24 24 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 LPMRETRYCNTSTS LPM Retry Count Status (LPM_RetryCnt_Sts) 25 27 read-only RETRY_REM0 Unspecified 0x0 RETRY_REM1 Unspecified 0x1 RETRY_REM2 Unspecified 0x2 RETRY_REM3 Unspecified 0x3 RETRY_REM4 Unspecified 0x4 RETRY_REM5 Unspecified 0x5 RETRY_REM6 Unspecified 0x6 RETRY_REM7 Unspecified 0x7 LPMENBESL LPM Enable BESL (LPM_EnBESL) 28 28 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 LPMRESTORESLPSTS LPM Restore Sleep Status (LPM_RestoreSlpSts) 29 29 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 GPWRDN Global Power Down register 0x058 read-write 0x00000010 0x20 PMUINTSEL PMU Interrupt Select (PMUIntSel) 0 0 DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 PMUACTV PMU Active (PMUActv) 1 1 DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 RESTORE Restore 2 2 DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 PWRDNCLMP Power Down Clamp (PwrDnClmp) 3 3 DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 PWRDNRSTN Power Down ResetN (PwrDnRst_n) 4 4 DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 PWRDNSWTCH Power Down Switch (PwrDnSwtch) 5 5 ON Unspecified 0x0 OFF Unspecified 0x1 DISABLEVBUS DisableVBUS 6 6 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 LNSTSCHNG Line State Change (LnStsChng) 7 7 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 LINESTAGECHANGEMSK LineStageChangeMsk 8 8 NOMASK Unspecified 0x0 MASK Unspecified 0x1 RESETDETECTED ResetDetected 9 9 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 RESETDETMSK ResetDetMsk 10 10 NOMASK Unspecified 0x0 MASK Unspecified 0x1 DISCONNECTDETECT DisconnectDetect 11 11 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DISCONNECTDETECTMSK DisconnectDetectMsk 12 12 NOMASK Unspecified 0x0 MASK Unspecified 0x1 CONNECTDET ConnectDet 13 13 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 CONNDETMSK ConnDetMsk 14 14 NOMASK Unspecified 0x0 MASK Unspecified 0x1 SRPDETECT SRPDetect 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SRPDETECTMSK SRPDetectMsk 16 16 NOMASK Unspecified 0x0 MASK Unspecified 0x1 STSCHNGINT Status Change Interrupt (StsChngInt) 17 17 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 STSCHNGINTMSK StsChngIntMsk 18 18 NOMASK Unspecified 0x0 MASK Unspecified 0x1 LINESTATE LineState 19 20 read-only LS1 Unspecified 0x0 LS2 Unspecified 0x1 LS3 Unspecified 0x2 LS4 Unspecified 0x3 IDDIG This bit indicates the status of the signal IDDIG. 21 21 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 BSESSVLD B Session Valid (BSessVld) 22 22 read-only NOTVALID Unspecified 0x0 VALID Unspecified 0x1 MULTVALIDBC MultValIdBC 24 28 read-only RID_0 Unspecified 0x00 RID_C Unspecified 0x01 RID_B Unspecified 0x02 RID_A Unspecified 0x04 RID_GND Unspecified 0x08 RID_A_RID_GND Unspecified 0x0C RID_FLOAT Unspecified 0x10 RID_C_RID_FLOAT Unspecified 0x11 RID_B_RID_FLOAT Unspecified 0x12 RID_1 Unspecified 0x1F GDFIFOCFG Global DFIFO Configuration Register 0x05C read-write 0x0BEA0C00 0x20 GDFIFOCFG GDFIFOCfg 0 15 EPINFOBASEADDR EPInfoBaseAddr 16 31 GINTMSK2 Interrupt Mask Register 2 0x068 read-write 0x00000000 0x20 GINTMSK2 0 31 GINTSTS2 Interrupt Register 2 0x06C read-write 0x00000000 0x20 GINTSTS2 0 31 HPTXFSIZ Host Periodic Transmit FIFO Size Register 0x100 read-write 0x04000424 0x20 PTXFSTADDR Host Periodic TxFIFO Start Address (PTxFStAddr) 0 10 PTXFSIZE Host Periodic TxFIFO Depth (PTxFSize) 16 26 DIEPTXF1 Device IN Endpoint Transmit FIFO Size Register 1 0x104 read-write 0x02000424 0x20 INEPNTXFSTADDR IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) 0 10 INEPNTXFDEP IN Endpoint TxFIFO Depth (INEPnTxFDep) 16 25 DIEPTXF2 Device IN Endpoint Transmit FIFO Size Register 2 0x108 read-write 0x02000624 0x20 INEPNTXFSTADDR IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) 0 10 INEPNTXFDEP IN Endpoint TxFIFO Depth (INEPnTxFDep) 16 25 DIEPTXF3 Device IN Endpoint Transmit FIFO Size Register 3 0x10C read-write 0x02000824 0x20 INEPNTXFSTADDR IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) 0 11 INEPNTXFDEP IN Endpoint TxFIFO Depth (INEPnTxFDep) 16 25 DIEPTXF4 Device IN Endpoint Transmit FIFO Size Register 4 0x110 read-write 0x02000A24 0x20 INEPNTXFSTADDR IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) 0 11 INEPNTXFDEP IN Endpoint TxFIFO Depth (INEPnTxFDep) 16 25 DIEPTXF5 Device IN Endpoint Transmit FIFO Size Register 5 0x114 read-write 0x02000C24 0x20 INEPNTXFSTADDR IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) 0 11 INEPNTXFDEP IN Endpoint TxFIFO Depth (INEPnTxFDep) 16 25 DIEPTXF6 Device IN Endpoint Transmit FIFO Size Register 6 0x118 read-write 0x02000E24 0x20 INEPNTXFSTADDR IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) 0 11 INEPNTXFDEP IN Endpoint TxFIFO Depth (INEPnTxFDep) 16 25 DIEPTXF7 Device IN Endpoint Transmit FIFO Size Register 7 0x11C read-write 0x02001024 0x20 INEPNTXFSTADDR IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) 0 12 INEPNTXFDEP IN Endpoint TxFIFO Depth (INEPnTxFDep) 16 25 HCFG Host Configuration Register 0x400 read-write 0x00000200 0x20 FSLSPCLKSEL FS/LS PHY Clock Select (FSLSPclkSel) 0 1 CLK3060 Unspecified 0x0 CLK48 Unspecified 0x1 CLK6 Unspecified 0x2 FSLSSUPP FS- and LS-Only Support (FSLSSupp) 2 2 HSFSLS Unspecified 0x0 FSLS Unspecified 0x1 ENA32KHZS Enable 32 KHz Suspend mode (Ena32KHzS) 7 7 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 RESVALID Resume Validation Period (ResValid) 8 15 MODECHTIMEN Mode Change Ready Timer Enable (ModeChTimEn) 31 31 ENABLED Unspecified 0x0 DISABLED Unspecified 0x1 HFIR Host Frame Interval Register 0x404 read-write 0x0000EA60 0x20 FRINT Frame Interval (FrInt) 0 15 HFIRRLDCTRL Reload Control (HFIRRldCtrl) 16 16 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 HFNUM Host Frame Number/Frame Time Remaining Register 0x408 read-write 0x00003FFF 0x20 FRNUM Frame Number (FrNum) 0 15 read-only INACTIVE Unspecified 0x0000 ACTIVE Unspecified 0x0001 FRREM Frame Time Remaining (FrRem) 16 31 read-only HAINT Host All Channels Interrupt Register 0x414 read-write 0x00000000 0x20 HAINT Channel Interrupt for channel no. 0 15 read-only INACTIVE Unspecified 0x0000 ACTIVE Unspecified 0x0001 HAINTMSK Host All Channels Interrupt Mask Register 0x418 read-write 0x00000000 0x20 HAINTMSK Channel Interrupt Mask (HAINTMsk) 0 15 UNMASK Unspecified 0x0000 MASK Unspecified 0x0001 HPRT Host Port Control and Status Register 0x440 read-write 0x00000000 0x20 PRTCONNSTS Port Connect Status (PrtConnSts) 0 0 read-only NOTATTACHED Unspecified 0x0 ATTACHED Unspecified 0x1 PRTCONNDET Port Connect Detected (PrtConnDet) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PRTENA Port Enable (PrtEna) 2 2 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 PRTENCHNG Port Enable/Disable Change (PrtEnChng) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PRTOVRCURRACT Port Overcurrent Active (PrtOvrCurrAct) 4 4 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PRTOVRCURRCHNG Port Overcurrent Change (PrtOvrCurrChng) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PRTRES Port Resume (PrtRes) 6 6 NORESUME Unspecified 0x0 RESUME Unspecified 0x1 PRTSUSP Port Suspend (PrtSusp) 7 7 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PRTRST Port Reset (PrtRst) 8 8 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 PRTLNSTS Port Line Status (PrtLnSts) 10 11 read-only PLUSD Unspecified 0x1 MINUSD Unspecified 0x2 PRTPWR Port Power (PrtPwr) 12 12 OFF Unspecified 0x0 ON Unspecified 0x1 PRTTSTCTL Port Test Control (PrtTstCtl) 13 16 DISABLED Unspecified 0x0 TESTJ Unspecified 0x1 TESTK Unspecified 0x2 TESTSN Unspecified 0x3 TESTPM Unspecified 0x4 TESTFENB Unspecified 0x5 PRTSPD Port Speed (PrtSpd) 17 18 read-only HIGHSPD Unspecified 0x0 FULLSPD Unspecified 0x1 LOWSPD Unspecified 0x2 16 0x020 HC[%s] Unspecified USBHSCORE_HC read-write 0x500 CHAR Description cluster: Host Channel n Characteristics Register 0x000 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 EPNUM Endpoint Number (EPNum) 11 14 ENDPT0 Unspecified 0x0 ENDPT1 Unspecified 0x1 ENDPT2 Unspecified 0x2 ENDPT3 Unspecified 0x3 ENDPT4 Unspecified 0x4 ENDPT5 Unspecified 0x5 ENDPT6 Unspecified 0x6 ENDPT7 Unspecified 0x7 ENDPT8 Unspecified 0x8 ENDPT9 Unspecified 0x9 ENDPT10 Unspecified 0xA ENDPT11 Unspecified 0xB ENDPT12 Unspecified 0xC ENDPT13 Unspecified 0xD ENDPT14 Unspecified 0xE ENDPT15 Unspecified 0xF EPDIR Endpoint Direction (EPDir) 15 15 OUT Unspecified 0x0 IN Unspecified 0x1 LSPDDEV Low-Speed Device (LSpdDev) 17 17 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CTRL Unspecified 0x0 ISOC Unspecified 0x1 BULK Unspecified 0x2 INTERR Unspecified 0x3 EC Multi Count (MC) / Error Count (EC) 20 21 TRANSONE Unspecified 0x1 TRANSTWO Unspecified 0x2 TRANSTHREE Unspecified 0x3 DEVADDR Device Address (DevAddr) 22 28 ODDFRM Odd Frame (OddFrm) 29 29 EFRAME Unspecified 0x0 OFRAME Unspecified 0x1 CHDIS Channel Disable (ChDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CHENA Channel Enable (ChEna) 31 31 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 INT Description cluster: Host Channel n Interrupt Register 0x008 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CHHLTD Channel Halted (ChHltd) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STALL STALL Response Received Interrupt (STALL) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAK NAK Response Received Interrupt (NAK) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 ACK ACK Response Received/Transmitted Interrupt (ACK) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYET NYET Response Received Interrupt (NYET) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 XACTERR Transaction Error (XactErr) 7 7 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLERR Babble Error (BblErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 FRMOVRUN Frame Overrun (FrmOvrun). 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DATATGLERR Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear 10 10 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTMSK Description cluster: Host Channel n Interrupt Mask Register 0x00C read-write 0x00000000 0x20 XFERCOMPLMSK Transfer Completed Mask (XferComplMsk) 0 0 MASK Unspecified 0x0 NOMASK Unspecified 0x1 CHHLTDMSK Channel Halted Mask (ChHltdMsk) 1 1 MASK Unspecified 0x0 NOMASK Unspecified 0x1 AHBERRMSK AHB Error Mask (AHBErrMsk) 2 2 MASK Unspecified 0x0 NOMASK Unspecified 0x1 STALLMSK STALL Response Received Interrupt Mask (StallMsk) 3 3 MASK Unspecified 0x0 NOMASK Unspecified 0x1 NAKMSK NAK Response Received Interrupt Mask (NakMsk) 4 4 MASK Unspecified 0x0 NOMASK Unspecified 0x1 ACKMSK ACK Response Received/Transmitted Interrupt Mask (AckMsk) 5 5 MASK Unspecified 0x0 NOMASK Unspecified 0x1 NYETMSK NYET Response Received Interrupt Mask (NyetMsk) 6 6 MASK Unspecified 0x0 NOMASK Unspecified 0x1 XACTERRMSK Transaction Error Mask (XactErrMsk) 7 7 MASK Unspecified 0x0 NOMASK Unspecified 0x1 BBLERRMSK Babble Error Mask (BblErrMsk) 8 8 MASK Unspecified 0x0 NOMASK Unspecified 0x1 FRMOVRUNMSK Frame Overrun Mask (FrmOvrunMsk) 9 9 MASK Unspecified 0x0 NOMASK Unspecified 0x1 DATATGLERRMSK Data Toggle Error Mask (DataTglErrMsk) 10 10 MASK Unspecified 0x0 NOMASK Unspecified 0x1 TSIZ Description cluster: Host Channel n Transfer Size Register 0x010 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 PID PID (Pid) 29 30 DATA0 Unspecified 0x0 DATA2 Unspecified 0x1 DATA1 Unspecified 0x2 MDATA Unspecified 0x3 DOPNG Do Ping (DoPng) 31 31 NOPING Unspecified 0x0 PING Unspecified 0x1 DMA Description cluster: Host Channel n DMA Address Register 0x014 read-write 0x00000000 0x20 DMAADDR In Buffer DMA Mode: 0 31 DCFG Device Configuration Register 0x800 read-write 0x08020000 0x20 DEVSPD Device Speed (DevSpd) 0 1 USBHS20 Unspecified 0x0 USBFS20 Unspecified 0x1 USBLS116 Unspecified 0x2 USBFS1148 Unspecified 0x3 NZSTSOUTHSHK Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) 2 2 SENDOUT Unspecified 0x0 SENDSTALL Unspecified 0x1 ENA32KHZSUSP Enable 32 KHz Suspend mode (Ena32KHzSusp) 3 3 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DEVADDR Device Address (DevAddr) 4 10 PERFRINT Periodic Frame Interval (PerFrInt) 11 12 EOPF80 Unspecified 0x0 EOPF85 Unspecified 0x1 EOPF90 Unspecified 0x2 EOPF95 Unspecified 0x3 XCVRDLY XCVRDLY 14 14 DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 ERRATICINTMSK Erratic Error Interrupt Mask 15 15 NOMASK Unspecified 0x0 MASK Unspecified 0x1 IPGISOCSUPT Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) 17 17 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 PERSCHINTVL Periodic Scheduling Interval (PerSchIntvl) 24 25 MF25 Unspecified 0x0 MF50 Unspecified 0x1 MF75 Unspecified 0x2 RESVALID Resume Validation Period (ResValid) 26 31 DCTL Device Control Register 0x804 read-write 0x00000002 0x20 RMTWKUPSIG Remote Wakeup Signaling (RmtWkUpSig) 0 0 DISABLEDRMWKUP Unspecified 0x0 ENABLERMWKUP Unspecified 0x1 SFTDISCON Soft Disconnect (SftDiscon) 1 1 NODISCONNECT Unspecified 0x0 DISCONNECT Unspecified 0x1 GNPINNAKSTS Global Non-periodic IN NAK Status (GNPINNakSts) 2 2 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 GOUTNAKSTS Global OUT NAK Status (GOUTNakSts) 3 3 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TSTCTL Test Control (TstCtl) 4 6 DISABLED Unspecified 0x0 TESTJ Unspecified 0x1 TESTK Unspecified 0x2 TESTSN Unspecified 0x3 TESTPM Unspecified 0x4 TESTFE Unspecified 0x5 SGNPINNAK Set Global Non-periodic IN NAK (SGNPInNak) 7 7 write-only DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 CGNPINNAK Clear Global Non-periodic IN NAK (CGNPInNak) 8 8 write-only DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 SGOUTNAK Set Global OUT NAK (SGOUTNak) 9 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 CGOUTNAK Clear Global OUT NAK (CGOUTNak) 10 10 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 PWRONPRGDONE Power-On Programming Done (PWROnPrgDone) 11 11 NOTDONE Unspecified 0x0 DONE Unspecified 0x1 IGNRFRMNUM Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 NAKONBBLE NAK on Babble Error (NakOnBble) 16 16 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DEEPSLEEPBESLREJECT DeepSleepBESLReject 18 18 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SERVINT Service Interval based scheduling for Isochronous IN Endpoints 19 19 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DSTS Device Status Register 0x808 read-write 0x00000002 0x20 SUSPSTS Suspend Status (SuspSts) 0 0 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 ENUMSPD Enumerated Speed (EnumSpd) 1 2 read-only HS3060 Unspecified 0x0 FS3060 Unspecified 0x1 LS6 Unspecified 0x2 FS48 Unspecified 0x3 ERRTICERR Erratic Error (ErrticErr) 3 3 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SOFFN Frame or Microframe Number of the Received SOF (SOFFN) 8 21 read-only DEVLNSTS Device Line Status (DevLnSts) 22 23 read-only DIEPMSK Device IN Endpoint Common Interrupt Mask Register 0x810 read-write 0x00000000 0x20 XFERCOMPLMSK Transfer Completed Interrupt Mask (XferComplMsk) 0 0 MASK Unspecified 0x0 NOMASK Unspecified 0x1 EPDISBLDMSK Endpoint Disabled Interrupt Mask (EPDisbldMsk) 1 1 MASK Unspecified 0x0 NOMASK Unspecified 0x1 AHBERRMSK AHB Error Mask (AHBErrMsk) 2 2 MASK Unspecified 0x0 NOMASK Unspecified 0x1 TIMEOUTMSK Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) 3 3 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INTKNTXFEMPMSK IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) 4 4 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INTKNEPMISMSK IN Token received with EP Mismatch Mask (INTknEPMisMsk) 5 5 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPNAKEFFMSK IN Endpoint NAK Effective Mask (INEPNakEffMsk) 6 6 MASK Unspecified 0x0 NOMASK Unspecified 0x1 TXFIFOUNDRNMSK Fifo Underrun Mask (TxfifoUndrnMsk) 8 8 MASK Unspecified 0x0 NOMASK Unspecified 0x1 NAKMSK NAK interrupt Mask (NAKMsk) 13 13 MASK Unspecified 0x0 NOMASK Unspecified 0x1 DOEPMSK Device OUT Endpoint Common Interrupt Mask Register 0x814 read-write 0x00000000 0x20 XFERCOMPLMSK Transfer Completed Interrupt Mask (XferComplMsk) 0 0 MASK Unspecified 0x0 NOMASK Unspecified 0x1 EPDISBLDMSK Endpoint Disabled Interrupt Mask (EPDisbldMsk) 1 1 MASK Unspecified 0x0 NOMASK Unspecified 0x1 AHBERRMSK AHB Error (AHBErrMsk) 2 2 MASK Unspecified 0x0 NOMASK Unspecified 0x1 SETUPMSK SETUP Phase Done Mask (SetUPMsk) 3 3 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTTKNEPDISMSK OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) 4 4 MASK Unspecified 0x0 NOMASK Unspecified 0x1 STSPHSERCVDMSK Status Phase Received Mask (StsPhseRcvdMsk) 5 5 MASK Unspecified 0x0 NOMASK Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received Mask (Back2BackSETup) 6 6 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTPKTERRMSK OUT Packet Error Mask (OutPktErrMsk) 8 8 MASK Unspecified 0x0 NOMASK Unspecified 0x1 BBLEERRMSK Babble Error interrupt Mask (BbleErrMsk) 12 12 MASK Unspecified 0x0 NOMASK Unspecified 0x1 NAKMSK NAK interrupt Mask (NAKMsk) 13 13 MASK Unspecified 0x0 NOMASK Unspecified 0x1 NYETMSK NYET interrupt Mask (NYETMsk) 14 14 MASK Unspecified 0x0 NOMASK Unspecified 0x1 DAINT Device All Endpoints Interrupt Register 0x818 read-write 0x00000000 0x20 INEPINT0 IN Endpoint 0 Interrupt Bit 0 0 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT1 IN Endpoint 1 Interrupt Bit 1 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT2 IN Endpoint 2 Interrupt Bit 2 2 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT3 IN Endpoint 3 Interrupt Bit 3 3 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT4 IN Endpoint 4 Interrupt Bit 4 4 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT5 IN Endpoint 5 Interrupt Bit 5 5 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT6 IN Endpoint 6 Interrupt Bit 6 6 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT7 IN Endpoint 7 Interrupt Bit 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT8 IN Endpoint 8 Interrupt Bit 8 8 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT9 IN Endpoint 9 Interrupt Bit 9 9 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT10 IN Endpoint 10 Interrupt Bit 10 10 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPINT11 IN Endpoint 11 Interrupt Bit 11 11 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT0 OUT Endpoint 0 Interrupt Bit 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT1 OUT Endpoint 1 Interrupt Bit 17 17 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT2 OUT Endpoint 2 Interrupt Bit 18 18 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT3 OUT Endpoint 3 Interrupt Bit 19 19 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT4 OUT Endpoint 4 Interrupt Bit 20 20 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT5 OUT Endpoint 5 Interrupt Bit 21 21 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT12 OUT Endpoint 12 Interrupt Bit 28 28 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT13 OUT Endpoint 13 Interrupt Bit 29 29 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT14 OUT Endpoint 14 Interrupt Bit 30 30 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTEPINT15 OUT Endpoint 15 Interrupt Bit 31 31 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DAINTMSK Device All Endpoints Interrupt Mask Register 0x81C read-write 0x00000000 0x20 INEPMSK0 IN Endpoint 0 Interrupt mask Bit 0 0 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK1 IN Endpoint 1 Interrupt mask Bit 1 1 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK2 IN Endpoint 2 Interrupt mask Bit 2 2 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK3 IN Endpoint 3 Interrupt mask Bit 3 3 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK4 IN Endpoint 4 Interrupt mask Bit 4 4 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK5 IN Endpoint 5 Interrupt mask Bit 5 5 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK6 IN Endpoint 6 Interrupt mask Bit 6 6 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK7 IN Endpoint 7 Interrupt mask Bit 7 7 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK8 IN Endpoint 8 Interrupt mask Bit 8 8 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK9 IN Endpoint 9 Interrupt mask Bit 9 9 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK10 IN Endpoint 10 Interrupt mask Bit 10 10 MASK Unspecified 0x0 NOMASK Unspecified 0x1 INEPMSK11 IN Endpoint 11 Interrupt mask Bit 11 11 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK0 OUT Endpoint 0 Interrupt mask Bit 16 16 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK1 OUT Endpoint 1 Interrupt mask Bit 17 17 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK2 OUT Endpoint 2 Interrupt mask Bit 18 18 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK3 OUT Endpoint 3 Interrupt mask Bit 19 19 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK4 OUT Endpoint 4 Interrupt mask Bit 20 20 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK5 OUT Endpoint 5 Interrupt mask Bit 21 21 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK12 OUT Endpoint 12 Interrupt mask Bit 28 28 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK13 OUT Endpoint 13 Interrupt mask Bit 29 29 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK14 OUT Endpoint 14 Interrupt mask Bit 30 30 MASK Unspecified 0x0 NOMASK Unspecified 0x1 OUTEPMSK15 OUT Endpoint 15 Interrupt mask Bit 31 31 MASK Unspecified 0x0 NOMASK Unspecified 0x1 DVBUSDIS Device VBUS Discharge Time Register 0x828 read-write 0x000017D7 0x20 DVBUSDIS Device VBUS Discharge Time (DVBUSDis) 0 15 DVBUSPULSE Device VBUS Pulsing Time Register 0x82C read-write 0x000005B8 0x20 DVBUSPULSE Device VBUS Pulsing Time (DVBUSPulse) 0 11 DTHRCTL Device Threshold Control Register 0x830 read-write 0x08100020 0x20 NONISOTHREN Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) 0 0 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 ISOTHREN ISO IN Endpoints Threshold Enable. (ISOThrEn) 1 1 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 TXTHRLEN Transmit Threshold Length (TxThrLen) 2 10 AHBTHRRATIO AHB Threshold Ratio (AHBThrRatio) 11 12 THRESZERO Unspecified 0x0 THRESONE Unspecified 0x1 THRESTWO Unspecified 0x2 THRESTHREE Unspecified 0x3 RXTHREN Receive Threshold Enable (RxThrEn) 16 16 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 RXTHRLEN Receive Threshold Length (RxThrLen) 17 25 ARBPRKEN Arbiter Parking Enable (ArbPrkEn) 27 27 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DIEPEMPMSK Device IN Endpoint FIFO Empty Interrupt Mask Register 0x834 read-write 0x00000000 0x20 INEPTXFEMPMSK IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) 0 15 EP0_MASK Unspecified 0x0001 EP1_MASK Unspecified 0x0002 EP2_MASK Unspecified 0x0004 EP3_MASK Unspecified 0x0008 EP4_MASK Unspecified 0x0010 EP5_MASK Unspecified 0x0020 EP6_MASK Unspecified 0x0040 EP7_MASK Unspecified 0x0080 EP8_MASK Unspecified 0x0100 EP9_MASK Unspecified 0x0200 EP10_MASK Unspecified 0x0400 EP11_MASK Unspecified 0x0800 EP12_MASK Unspecified 0x1000 EP13_MASK Unspecified 0x2000 EP14_MASK Unspecified 0x4000 EP15_MASK Unspecified 0x8000 DIEPCTL0 Device Control IN Endpoint 0 Control Register 0x900 read-write 0x00008000 0x20 MPS Maximum Packet Size (MPS) 0 1 BYTES64 Unspecified 0x0 BYTES32 Unspecified 0x1 BYTES16 Unspecified 0x2 BYTES8 Unspecified 0x3 USBACTEP USB Active Endpoint (USBActEP) 15 15 read-only ACTIVE0 Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 read-only ACTIVE Unspecified 0x0 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only NOCLEAR Unspecified 0x0 CLEAR Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only NOSET Unspecified 0x0 SET Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT0 Device IN Endpoint 0 Interrupt Register 0x908 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ0 Device IN Endpoint 0 Transfer Size Register 0x910 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 6 PKTCNT Packet Count (PktCnt) 19 20 DIEPDMA0 Device IN Endpoint 0 DMA Address Register 0x914 read-write 0x00000000 0x20 DMAADDR DMAAddr 0 31 DTXFSTS0 Device IN Endpoint Transmit FIFO Status Register 0 0x918 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL1 Device Control IN Endpoint 1 Control Register 0x920 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT1 Device IN Endpoint 1 Interrupt Register 0x928 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ1 Device IN Endpoint 1 Transfer Size Register 0x930 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA1 Device IN Endpoint 1 DMA Address Register 0x934 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS1 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 1 of the Device controller. 0x938 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL2 Device Control IN Endpoint 2 Control Register 0x940 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT2 Device IN Endpoint 2 Interrupt Register 0x948 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ2 Device IN Endpoint 2 Transfer Size Register 0x950 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA2 Device IN Endpoint 2 DMA Address Register 0x954 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS2 Device IN Endpoint Transmit FIFO Status Register 2 0x958 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL3 Device Control IN Endpoint 3 Control Register 0x960 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT3 Device IN Endpoint 3 Interrupt Register 0x968 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ3 Device IN Endpoint 3 Transfer Size Register 0x970 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA3 Device IN Endpoint 3 DMA Address Register 0x974 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS3 Device IN Endpoint Transmit FIFO Status Register 3 0x978 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL4 Device Control IN Endpoint 4 Control Register 0x980 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT4 Device IN Endpoint 4 Interrupt Register 0x988 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ4 Device IN Endpoint 4 Transfer Size Register 0x990 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA4 Device IN Endpoint 4 DMA Address Register 0x994 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS4 Device IN Endpoint Transmit FIFO Status Register 4 0x998 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL5 Device Control IN Endpoint 5 Control Register 0x9A0 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT5 Device IN Endpoint 5 Interrupt Register 0x9A8 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ5 Device IN Endpoint 5 Transfer Size Register 0x9B0 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA5 Device IN Endpoint 5 DMA Address Register 0x9B4 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS5 Device IN Endpoint Transmit FIFO Status Register 5 0x9B8 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL6 Device Control IN Endpoint 6 Control Register 0x9C0 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT6 Device IN Endpoint 6 Interrupt Register 0x9C8 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ6 Device IN Endpoint 6 Transfer Size Register 0x9D0 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA6 Device IN Endpoint 6 DMA Address Register 0x9D4 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS6 Device IN Endpoint Transmit FIFO Status Register 6 0x9D8 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL7 Device Control IN Endpoint 7 Control Register 0x9E0 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT7 Device IN Endpoint 7 Interrupt Register 0x9E8 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ7 Device IN Endpoint 7 Transfer Size Register 0x9F0 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA7 Device IN Endpoint 7 DMA Address Register 0x9F4 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS7 Device IN Endpoint Transmit FIFO Status Register 7 0x9F8 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL8 Device Control IN Endpoint 8 Control Register 0xA00 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT8 Device IN Endpoint 8 Interrupt Register 0xA08 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ8 Device IN Endpoint 8 Transfer Size Register 0xA10 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA8 Device IN Endpoint 8 DMA Address Register 0xA14 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS8 Device IN Endpoint Transmit FIFO Status Register 8 0xA18 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL9 Device Control IN Endpoint 9 Control Register 0xA20 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT9 Device IN Endpoint 9 Interrupt Register 0xA28 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ9 Device IN Endpoint 9 Transfer Size Register 0xA30 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA9 Device IN Endpoint 9 DMA Address Register 0xA34 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS9 Device IN Endpoint Transmit FIFO Status Register 9 0xA38 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL10 Device Control IN Endpoint 10 Control Register 0xA40 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT10 Device IN Endpoint 10 Interrupt Register 0xA48 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ10 Device IN Endpoint 10 Transfer Size Register 0xA50 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA10 Device IN Endpoint 10 DMA Address Register 0xA54 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS10 Device IN Endpoint Transmit FIFO Status Register 10 0xA58 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DIEPCTL11 Device Control IN Endpoint 11 Control Register 0xA60 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only DATA0EVENFRM Unspecified 0x0 DATA1ODDFRM Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUP Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFNUM TxFIFO Number (TxFNum) 22 25 TXFIFO0 Unspecified 0x0 TXFIFO1 Unspecified 0x1 TXFIFO2 Unspecified 0x2 TXFIFO3 Unspecified 0x3 TXFIFO4 Unspecified 0x4 TXFIFO5 Unspecified 0x5 TXFIFO6 Unspecified 0x6 TXFIFO7 Unspecified 0x7 TXFIFO8 Unspecified 0x8 TXFIFO9 Unspecified 0x9 TXFIFO10 Unspecified 0xA TXFIFO11 Unspecified 0xB TXFIFO12 Unspecified 0xC TXFIFO13 Unspecified 0xD TXFIFO14 Unspecified 0xE TXFIFO15 Unspecified 0xF CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID SetD0PID 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID SetD1PID 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPINT11 Device IN Endpoint 11 Interrupt Register 0xA68 read-write 0x00000080 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TIMEOUT Timeout Condition (TimeOUT) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNTXFEMP IN Token Received When TxFIFO is Empty (INTknTXFEmp) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INTKNEPMIS IN Token Received with EP Mismatch (INTknEPMis) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 INEPNAKEFF IN Endpoint NAK Effective (INEPNakEff) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFEMP Transmit FIFO Empty (TxFEmp) 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXFIFOUNDRN Fifo Underrun (TxfifoUndrn) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DIEPTSIZ11 Device IN Endpoint 11 Transfer Size Register 0xA70 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 MC MC 29 30 PACKETONE Unspecified 0x1 PACKETTWO Unspecified 0x2 PACKETTHREE Unspecified 0x3 DIEPDMA11 Device IN Endpoint 11 DMA Address Register 0xA74 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DTXFSTS11 Device IN Endpoint Transmit FIFO Status Register 11 0xA78 read-write 0x00000200 0x20 INEPTXFSPCAVAIL IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) 0 15 read-only DOEPCTL0 Device Control OUT Endpoint 0 Control Register 0xB00 read-write 0x00008000 0x20 MPS Maximum Packet Size (MPS) 0 1 read-only BYTE64 Unspecified 0x0 BYTE32 Unspecified 0x1 BYTE16 Unspecified 0x2 BYTE8 Unspecified 0x3 USBACTEP USB Active Endpoint (USBActEP) 15 15 read-only ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 read-only ACTIVE Unspecified 0x0 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only NOCLEAR Unspecified 0x0 CLEAR Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only NOSET Unspecified 0x0 SET Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 read-only INACTIVE Unspecified 0x0 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT0 Device OUT Endpoint 0 Interrupt Register 0xB08 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ0 Device OUT Endpoint 0 Transfer Size Register 0xB10 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 6 PKTCNT Packet Count (PktCnt) 19 19 SUPCNT SETUP Packet Count (SUPCnt) 29 30 ONEPACKET Unspecified 0x1 TWOPACKET Unspecified 0x2 THREEPACKET Unspecified 0x3 DOEPDMA0 Device OUT Endpoint 0 DMA Address Register 0xB14 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL1 Device Control OUT Endpoint 1 Control Register 0xB20 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT1 Device OUT Endpoint 1 Interrupt Register 0xB28 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ1 Device OUT Endpoint 1 Transfer Size Register 0xB30 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA1 Device OUT Endpoint 1 DMA Address Register 0xB34 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL2 Device Control OUT Endpoint 2 Control Register 0xB40 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT2 Device OUT Endpoint 2 Interrupt Register 0xB48 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ2 Device OUT Endpoint 2 Transfer Size Register 0xB50 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA2 Device OUT Endpoint 2 DMA Address Register 0xB54 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL3 Device Control OUT Endpoint 3 Control Register 0xB60 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT3 Device OUT Endpoint 3 Interrupt Register 0xB68 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ3 Device OUT Endpoint 3 Transfer Size Register 0xB70 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA3 Device OUT Endpoint 3 DMA Address Register 0xB74 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL4 Device Control OUT Endpoint 4 Control Register 0xB80 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT4 Device OUT Endpoint 4 Interrupt Register 0xB88 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ4 Device OUT Endpoint 4 Transfer Size Register 0xB90 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA4 Device OUT Endpoint 4 DMA Address Register 0xB94 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL5 Device Control OUT Endpoint 5 Control Register 0xBA0 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT5 Device OUT Endpoint 5 Interrupt Register 0xBA8 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ5 Device OUT Endpoint 5 Transfer Size Register 0xBB0 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA5 Device OUT Endpoint 5 DMA Address Register 0xBB4 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL12 Device Control OUT Endpoint 12 Control Register 0xC80 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT12 Device OUT Endpoint 12 Interrupt Register 0xC88 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ12 Device OUT Endpoint 12 Transfer Size Register 0xC90 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA12 Device OUT Endpoint 12 DMA Address Register 0xC94 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL13 Device Control OUT Endpoint 13 Control Register 0xCA0 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT13 Device OUT Endpoint 13 Interrupt Register 0xCA8 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ13 Device OUT Endpoint 13 Transfer Size Register 0xCB0 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA13 Device OUT Endpoint 13 DMA Address Register 0xCB4 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL14 Device Control OUT Endpoint 14 Control Register 0xCC0 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT14 Device OUT Endpoint 14 Interrupt Register 0xCC8 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ14 Device OUT Endpoint 14 Transfer Size Register 0xCD0 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA14 Device OUT Endpoint 14 DMA Address Register 0xCD4 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 DOEPCTL15 Device Control OUT Endpoint 15 Control Register 0xCE0 read-write 0x00000000 0x20 MPS Maximum Packet Size (MPS) 0 10 USBACTEP USB Active Endpoint (USBActEP) 15 15 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 DPID Endpoint Data PID (DPID) 16 16 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKSTS NAK Status (NAKSts) 17 17 read-only NONNAK Unspecified 0x0 NAK Unspecified 0x1 EPTYPE Endpoint Type (EPType) 18 19 CONTROL Unspecified 0x0 ISOCHRONOUS Unspecified 0x1 BULK Unspecified 0x2 INTERRUPT Unspecified 0x3 STALL STALL Handshake (Stall) 21 21 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 CNAK Clear NAK (CNAK) 26 26 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SNAK Set NAK (SNAK) 27 27 write-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETD0PID Set DATA0 PID (SetD0PID) 28 28 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SETD1PID Set DATA1 PID (SetD1PID) 29 29 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 EPDIS Endpoint Disable (EPDis) 30 30 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPENA Endpoint Enable (EPEna) 31 31 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DOEPINT15 Device OUT Endpoint 15 Interrupt Register 0xCE8 read-write 0x00000000 0x20 XFERCOMPL Transfer Completed Interrupt (XferCompl) 0 0 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 EPDISBLD Endpoint Disabled Interrupt (EPDisbld) 1 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AHBERR AHB Error (AHBErr) 2 2 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SETUP SETUP Phase Done (SetUp) 3 3 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTTKNEPDIS OUT Token Received When Endpoint Disabled (OUTTknEPdis) 4 4 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STSPHSERCVD Status Phase Received for Control Write (StsPhseRcvd) 5 5 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BACK2BACKSETUP Back-to-Back SETUP Packets Received (Back2BackSETup) 6 6 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 OUTPKTERR OUT Packet Error (OutPktErr) 8 8 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BNAINTR BNA (Buffer Not Available) Interrupt (BNAIntr) 9 9 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 PKTDRPSTS Packet Drop Status (PktDrpSts) 11 11 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BBLEERR NAK Interrupt (BbleErr) 12 12 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NAKINTRPT NAK Interrupt (NAKInterrupt) 13 13 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 NYETINTRPT NYET Interrupt (NYETIntrpt) 14 14 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STUPPKTRCVD Setup Packet Received 15 15 NOT_RCVD Unspecified 0x0 RCVD Unspecified 0x1 DOEPTSIZ15 Device OUT Endpoint 15 Transfer Size Register 0xCF0 read-write 0x00000000 0x20 XFERSIZE Transfer Size (XferSize) 0 18 PKTCNT Packet Count (PktCnt) 19 28 RXDPID RxDPID 29 30 read-only DATA0 Unspecified 0x0 DATA2PACKET1 Unspecified 0x1 DATA1PACKET2 Unspecified 0x2 MDATAPACKET3 Unspecified 0x3 DOEPDMA15 Device OUT Endpoint 15 DMA Address Register 0xCF4 read-write 0x00000000 0x20 DMAADDR Holds the start address of the external memory for storing or fetching endpoint 0 31 PCGCCTL Power and Clock Gating Control Register 0xE00 read-write 0x880A0000 0x20 STOPPCLK Stop Pclk (StopPclk) 0 0 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 RSTPDWNMODULE Reset Power-Down Modules (RstPdwnModule) 3 3 ON Unspecified 0x0 OFF Unspecified 0x1 ENBLL1GATING Enable Sleep Clock Gating 5 5 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 PHYSLEEP PHY In Sleep 6 6 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 L1SUSPENDED L1 Deep Sleep 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RESTOREMODE Restore Mode (RestoreMode) 9 9 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 ESSREGRESTORED Essential Register Values Restored (EssRegRestored) 13 13 write-only NOT_RESTORED Unspecified 0x0 RESTORED Unspecified 0x1 RESTOREVALUE Restore Value (RestoreValue) 14 31 16 0x1004 DWCOTGDFIFO[%s] Unspecified USBHSCORE_DWCOTGDFIFO read-write 0x1000 0x401 0x4 DATA[%s] Description collection: Data buffer for FIFO n 0x0000 read-write 0x00000000 0x20 DWCOTGDFIFODIRECTACCESS Unspecified USBHSCORE_DWCOTGDFIFODIRECTACCESS read-write 0x20000 0x1001 0x4 DATA[%s] Description collection: Data buffer FIFO Direct Access 0x00000 read-write 0x00000000 0x20 GLOBAL_USBHSCORE0_S USBHSCORE 1 0x2F700000 GLOBAL_USBHSCORE0_NS GLOBAL_I3CCORE120_NS I3CCORE 0 0x2FBE0000 I3CCORE 0 0x1000 registers I3CCORE 0x20 CORE Unspecified I3CCORE_CORE read-write 0x000 DEVICECTRL DWC_mipi_i3c control Register 0x000 read-write 0x00000000 0x20 IBAINCLUDE I3C Broadcast Address include 0 0 NOT_INCLUDED Unspecified 0x0 INCLUDED Unspecified 0x1 I2CSLAVEPRESENT I2C Slave Present 7 7 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 HOTJOINCTRL Hot-Join ACK/NACK Control 8 8 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 IDLECNTMULTPLIER Idle Count Multiplier 24 25 MultiplyBy1 Unspecified 0x0 MultiplyBy2 Unspecified 0x1 MultiplyBy4 Unspecified 0x2 MultiplyBy8 Unspecified 0x3 ADAPTIVEI2CI3C This field is used in Slave mode of operation. 27 27 DMAENABLE DMA Handshake Interface Enable 28 28 DISABLE The DMA handshake control has no significance. 0x0 ENABLE Enables the DMA handshake control to interact with external DMA. 0x1 ABORT DWC_mipi_i3c Abort 29 29 RESUME DWC_mipi_i3c Resume 30 30 ENABLE Controls whether or not DWC_mipi_i3c is enabled. 31 31 DISABLE Disables the DWC_mipi_i3c controller 0x0 ENABLE Enables the DWC_mipi_i3c controller. 0x1 DEVICEADDR In the master mode of operation this Register is used to program the Device Dynamic Addresses and its respective valid bit. 0x004 read-write 0x80000000 0x20 STATICADDR Device Static Address. 0 6 STATICADDRVALID Static Address Valid. 15 15 INVALID Unspecified 0x0 VALID Unspecified 0x1 DYNAMICADDR Device Dynamic Address. 16 22 DYNAMICADDRVALID Dynamic Address Valid 31 31 INVALID Unspecified 0x0 VALID Unspecified 0x1 HWCAPABILITY Hardware Capability register 0x008 read-write 0x000E187B 0x20 DEVICEROLECONFIG Reflects the IC_DEVICE_ROLE Configurable Parameter. 0 2 read-only MASTER Master Only 0x1 PMASTERSLAVE Programmable Master-Slave 0x2 SECONDARYMASTER Secondary Master 0x3 SLAVE Slave Only 0x4 HDRDDREN Reflects the IC_SPEED_HDR_DDR Configurable Parameter. 3 3 read-only NOTSUPPORTED HDR-DDR not supported 0x0 SUPPORTED HDR-DDR supported 0x1 HDRTSEN Reflects the IC_SPEED_HDR_TS Configurable Parameter. 4 4 read-only NOTSUPPORTED HDR-TS not supported 0x0 SUPPORTED HDR-TS supported 0x1 CLOCKPERIOD Reflects the IC_CLK_PERIOD Configurable Parameter 5 10 read-only HDRTXCLOCKPERIOD Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter. 11 16 read-only DMAEN Reflects the IC_HAS_DMA Configurable Parameter. 17 17 read-only SLVHJCAP Reflects the IC_SLV_HJ Configurable Parameter. 18 18 read-only SLVIBICAP Reflects the IC_SLV_IBI Configurable Parameter. 19 19 read-only COMMANDQUEUEPORT Command Queue Port. 0x00C read-write 0x00000000 0x20 COMMAND 32 bit command 0 31 write-only RESPONSEQUEUEPORT Response Queue Port 0x010 read-write 0x00000000 0x20 RESPONSE 32 bit Response 0 31 read-only RXDATAPORT Receive Data Port Register 0x014 read-write 0x00000000 0x20 RXDATAPORT Receive Data Port. 0 31 read-only TXDATAPORT Transmit Data Port Register 0x014 read-write 0x00000000 RXDATAPORT 0x20 TXDATAPORT Transmit Data Port 0 31 write-only IBIQUEUEDATA In-Band Interrupt Queue Data Register 0x018 read-write 0x00000000 0x20 IBIDATA In-Band Interrupt Data 0 31 read-only IBIQUEUESTATUS In-Band Interrupt Queue Status Register 0x018 read-write 0x00000000 IBIQUEUEDATA 0x20 DATALENGTH In-Band Interrupt data length. 0 7 read-only IBIID IBI Identifier. 8 15 read-only IBIACK The acknowledge bit of the IBI Received Status (IBISTS) bitfield. 31 31 read-only ACK Responded with ACK 0x0 NACK Responded with NACK 0x1 QUEUETHLDCTRL Queue Threshold Control Register 0x01C read-write 0x01000101 0x20 CMDEMPTYBUFTHLD Command Buffer Empty Threshold Value. 0 7 RESPBUFTHLD Response Buffer Threshold Value. 8 15 IBISTATUSTHLD In-Band Interrupt Status Threshold Value. 24 31 DATABUFFERTHLDCTRL Data Buffer Threshold Control Register 0x020 read-write 0x01010101 0x20 TXEMPTYBUFTHLD Transmit Buffer Threshold Value 0 2 THRESHOLD1 Unspecified 0x0 THRESHOLD14 Unspecified 0x1 THRESHOLD18 Unspecified 0x2 THRESHOLD116 Unspecified 0x3 THRESHOLD132 Unspecified 0x4 THRESHOLD164 Unspecified 0x5 RXBUFTHLD Receive Buffer Threshold Value 8 10 THRESHOLD1 Unspecified 0x0 THRESHOLD4 Unspecified 0x1 THRESHOLD8 Unspecified 0x2 THRESHOLD16 Unspecified 0x3 THRESHOLD32 Unspecified 0x4 THRESHOLD64 Unspecified 0x5 TXSTARTTHLD Transfer Start Threshold Value 16 18 THRESHOLD1 Unspecified 0x0 THRESHOLD4 Unspecified 0x1 THRESHOLD8 Unspecified 0x2 THRESHOLD16 Unspecified 0x3 THRESHOLD32 Unspecified 0x4 THRESHOLD64 Unspecified 0x5 RXSTARTTHLD Receive Start Threshold Value 24 26 THRESHOLD1 Unspecified 0x0 THRESHOLD4 Unspecified 0x1 THRESHOLD8 Unspecified 0x2 THRESHOLD16 Unspecified 0x3 THRESHOLD32 Unspecified 0x4 THRESHOLD64 Unspecified 0x5 IBIQUEUECTRL This Register is used to control whether or not to intimate the application if an IBI request is rejected (Nacked). 0x024 read-write 0x00000000 0x20 NOTIFYHJREJECTED Notify Rejected Hot-Join Control. 0 0 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 NOTIFYMRREJECTED Notify Rejected Master Request Control. 1 1 DISABLED Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. 0x0 ENABLED Writes IBI Status to the IBI FIFO (hence notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. 0x1 NOTIFYSIRREJECTED Notify Rejected Slave Interrupt Request Control. 3 3 DISABLED Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. 0x0 ENABLED Writes IBI Status to the IBI FIFO (hence notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. 0x1 IBIMRREQREJECT IBI Master Request Rejection Control Register. 0x02C read-write 0x00000000 0x20 MRREQREJECT In-band Master Request Reject. 0 31 ACK ACK Master Request. 0x00000000 NACK NACK and send Directed DISEC CCC to disable the interrupting slave. 0x00000001 IBISIRREQREJECT IBI SIR Request Rejection Control 0x030 read-write 0x00000000 0x20 SIRREQREJECT In-band Slave Interrupt Request Reject 0 31 ACK ACK the SIR Request. 0x00000000 NACK NACK and send directed auto disable CCC. 0x00000001 RESETCTRL This Register is used for general software reset and for individual buffer reset. 0x034 read-write 0x00000000 0x20 SOFTRST Core Software Reset. 0 0 CMDQUEUERST Command Queue Software Reset 1 1 RESPQUEUERST Response Queue Software Reset 2 2 TXFIFORST Transmit Buffer Software Reset 3 3 RXFIFORST Receive Buffer Software Reset. 4 4 IBIQUEUERST IBI Queue Software Reset. 5 5 BUSRESETTYPE Bus Reset type 29 30 EXIT Exit Pattern. 0x0 SCL_LOW_RESET SCL_LOW_RESET Pattern. 0x3 BUSRESET Bus Reset. 31 31 SLVEVENTSTATUS This register indicates the status/values of some events/controls that are relavant to slave mode of operation. 0x038 read-write 0x0000000B 0x20 SIREN Slave Interrupt Request Enable. 0 0 read-only MREN Master Request Enable. 1 1 read-only HJEN Hot-Join Interrupt Enable 3 3 ACTIVITYSTATE Activity State Status. 4 5 read-only ENTAS0 Unspecified 0x0 ENTAS1 Unspecified 0x1 ENTAS2 Unspecified 0x2 ENTAS3 Unspecified 0x3 MRLUPDATED MRL Updated Status. 6 6 MWLUPDATED MWL Updated Status. 7 7 INTRSTATUS Interrupt Status Register 0x03C read-write 0x00000000 0x20 TXTHLDSTS Transmit Buffer Threshold Status 0 0 read-only RXTHLDSTS Receive Buffer Threshold Status. 1 1 read-only IBITHLDSTS IBI Buffer Threshold Status. 2 2 read-only CMDQUEUEREADYSTS Command Queue Ready. 3 3 read-only RESPREADYSTS Response Queue Ready Status. 4 4 read-only TRANSFERABORTSTS Transfer Abort Status. 5 5 CCCUPDATEDSTS CCC Table Updated Status. 6 6 DYNADDRASSGNSTS Dynamic Address Assigned Status. 8 8 TRANSFERERRSTS Transfer Error Status. 9 9 DEFSLVSTS Define Slave CCC Received Status. 10 10 READREQRECVSTS Read Request Received. 11 11 IBIUPDATEDSTS IBI status is updated. 12 12 BUSOWNERUPDATEDSTS This interrupt is set when the role of the controller changes from being a Master to Slave or vice versa. 13 13 BUSRESETDONESTS Bus Reset Pattern Generation Done Status. 15 15 INTRSTATUSEN Interrupt Status Enable Register. 0x040 read-write 0x00000000 0x20 TXTHLDSTSEN Transmit Buffer Threshold Status Enable. 0 0 RXTHLDSTSEN Receive Buffer Threshold Status Enable 1 1 IBITHLDSTSEN IBI Buffer Threshold Status Enable. 2 2 CMDQUEUEREADYSTSEN Command Queue Ready Status Enable 3 3 RESPREADYSTSEN Response Queue Ready Status Enable 4 4 TRANSFERABORTSTSEN Transfer Abort Status Enable. 5 5 CCCUPDATEDSTSEN CCC Table Updated Status Enable. 6 6 DYNADDRASSGNSTSEN Dynamic Address Assigned Status Enable 8 8 TRANSFERERRSTSEN Transfer Error Status Enable 9 9 DEFSLVSTSEN Define Slave CCC Received Status Enable 10 10 READREQRECVSTSEN Read Request Received Status Enable 11 11 IBIUPDATEDSTSEN IBI Updated Status Enable 12 12 BUSOWNERUPDATEDSTSEN Bus owner Updated Status Enable 13 13 BUSRESETDONESTSEN Bus Reset Pattern Generation Done Status Enable. 15 15 INTRSIGNALEN Interrupt Signal Enable Register 0x044 read-write 0x00000000 0x20 TXTHLDSIGNALEN Transmit Buffer Threshold Signal Enable 0 0 RXTHLDSIGNALEN Receive Buffer Threshold Signal Enable 1 1 IBITHLDSIGNALEN IBI Buffer Threshold Signal Enable 2 2 CMDQUEUEREADYSIGNALEN Command Queue Ready Signal Enable 3 3 RESPREADYSIGNALEN Response Queue Ready Signal Enable 4 4 TRANSFERABORTSIGNALEN Transfer Abort Signal Enable 5 5 CCCUPDATEDSIGNALEN CCC Table Updated Signal Enable 6 6 DYNADDRASSGNSIGNALEN Dynamic Address Assigned Signal Enable 8 8 TRANSFERERRSIGNALEN Transfer Error Signal Enable 9 9 DEFSLVSIGNALEN Define Slave CCC Received Signal Enable 10 10 READREQRECVSIGNALEN Read Request Received Signal Enable 11 11 IBIUPDATEDSIGNALEN IBI Updated Signal Enable 12 12 BUSOWNERUPDATEDSIGNALEN Bus owner Updated Signal Enable 13 13 BUSRESETDONESIGNALEN Bus Reset Pattern Generation Done Signal Enable. 15 15 INTRFORCE Interrupt Force Enable Register 0x048 read-write 0x00000000 0x20 TXTHLDFORCEEN Transmit Buffer Threshold Force Enable 0 0 write-only RXTHLDFORCEEN Receive Buffer Threshold Force Enable 1 1 write-only IBITHLDFORCEEN IBI Buffer Threshold Force Enable 2 2 write-only CMDQUEUEREADYFORCEEN Command Queue Ready Force Enable 3 3 write-only RESPREADYFORCEEN Response Queue Ready Force Enable 4 4 write-only TRANSFERABORTFORCEEN Transfer Abort Force Enable 5 5 write-only CCCUPDATEDFORCEEN CCC Table Updated Force Enable 6 6 write-only DYNADDRASSGNFORCEEN Dynamic Address Assigned Force Enable 8 8 write-only TRANSFERERRFORCEEN Transfer Error Force Enable 9 9 write-only DEFSLVFORCEEN Define Slave CCC Received Force Enable 10 10 write-only READREQFORCEEN Read Request Received Force Enable 11 11 write-only IBIUPDATEDFORCEEN IBI Updated Force Enable 12 12 write-only BUSOWNERUPDATEDFORCEEN Bus owner Updated Force Enable 13 13 write-only BUSRESETDONEFORCEEN Bus Reset Pattern Generation Done Force Enable. 15 15 write-only QUEUESTATUSLEVEL Queue Status Level Register. 0x04C read-write 0x00000010 0x20 CMDQUEUEEMPTYLOC Command Queue Empty Locations. 0 7 read-only RESPBUFBLR Response Buffer Level Value. 8 15 read-only IBIBUFBLR IBI Buffer Level Value. 16 23 read-only IBISTSCNT IBI Buffer Status Count. 24 28 read-only DATABUFFERSTATUSLEVEL Data Buffer Status Level Register. 0x050 read-write 0x00000040 0x20 TXBUFEMPTYLOC Transmit Buffer Empty Level Value. 0 7 read-only RXBUFBLR Receive Buffer Level Value. 16 23 read-only PRESENTSTATEM The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Master). 0x054 read-write 0x10000003 0x20 SCLLINESIGNALLEVEL This bit is used to check the SCL line level to recover from errors and for debugging. 0 0 read-only SDALINESIGNALLEVEL This bit is used to check the SDA line level to recover from errors and for debugging. 1 1 read-only CURRENTMASTER This Bit is used to check whether the Master is Current Master or not. 2 2 read-only NOT_BUS_OWNER Master is not Current Master 0x0 BUS_OWNER Master is Current Master 0x1 CMTFRSTS Transfer Type Status 8 13 read-only IDLE Controller is in Idle state, waiting for commands from application or Slave initated In-band Interrupt. 0x00 BCCCWTRANSFER Broadcast CCC Write Transfer. 0x01 DCCCWTRANSFER Directed CCC Write Transfer. 0x02 DCCCRTRANSFER Directed CCC Read Transfer. 0x03 ENTDAATRANSFER ENTDAA Address Assignment Transfer. 0x04 SETDASATRANSFER SETDASA Address Assignment Transfer. 0x05 SDRWTRANSFER Private I3C SDR Write Transfer. 0x06 SDRRTRANSFER Private I3C SDR Read Transfer. 0x07 SDRWTRANSFERI2C Private I2C SDR Write Transfer. 0x08 SDRRTRANSFERI2C Private I2C SDR Read Transfer. 0x09 TSWTRANSFER Private HDR Ternary Symbol(TS) Write Transfer. 0x0A TSRTRANSFER Private HDR Ternary Symbol(TS) Read Transfer. 0x0B DDRWTRANSFER Private HDR Double-Data Rate(DDR) Write Transfer. 0x0C DDRRTRANSFER Private HDR Double-Data Rate(DDR) Read Transfer. 0x0D IBITRANSFER Servicing In-Band Interrupt Transfer. 0x0E HALT Halt state. Controller is in Halt State, waiting for the application to resume through DEVICE_CTRL Register. 0x0F CMTFRSTSTS Current Master Transfer State Status. 16 21 read-only IDLE Controller is Idle state, waiting for commands from application or Slave initated In-band Interrupt. 0x00 START START Generation State. 0x01 RESTART RESTART Generation State. 0x02 STOP STOP Genration State. 0x03 STARTH START Hold Generation for the Slave Initiated START State. 0x04 BWADDRGEN Broadcast Write Address Header(7h7E,W) Generation State. 0x05 BRADDRGEN Broadcast Read Address Header(7h7E,R) Generation State. 0x06 DAA Dynamic Address Assignment State. 0x07 ADDRGEN Slave Address Generation State. 0x08 CCCBYTEGEN CCC Byte Generation State. 0x0B HDRCMDGEN HDR Command Generation State. 0x0C WTRANSFER Write Data Transfer State. 0x0D RTRANSFER Read Data Transfer State. 0x0E RIBI In-Band Interrupt(SIR) Read Data State. 0x0F IBIAUTODISABLE In-Band Interrupt Auto-Disable State 0x10 DDRCRCGEN HDR-DDR CRC Data Generation/Receive State. 0x11 CLKEXTEND Clock Extension State. 0x12 HALT Halt State. 0x13 CMDTID This field reflects the Transaction-ID of the current executing command. 24 27 read-only MASTERIDLE This field reflects whether the Master Controller is in Idle state or not. 28 28 read-only MST_NOT_IDLE Unspecified 0x0 MST_IDLE Unspecified 0x1 PRESENTSTATES The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Slave). 0x054 read-write 0x10000003 PRESENTSTATEM 0x20 SCLLINESIGNALLEVEL This bit is used to check the SCL line level to recover from errors and for debugging. 0 0 read-only SDALINESIGNALLEVEL This bit is used to check the SDA line level to recover from errors and for debugging. 1 1 read-only CURRENTMASTER This Bit is used to check whether the Master is Current Master or not. 2 2 read-only NOT_BUS_OWNER Master is not Current Master 0x0 BUS_OWNER Master is Current Master 0x1 CMTFRSTS Transfer Type Status 8 13 read-only SLAVEIDLE Controller is in Idle state. 0x00 SLAVEHOTJOIN Hot-Join transfer state. 0x01 SLAVEIBITRANSFER IBI transfer state. 0x02 SLAVEWTRANSFER Master write transfer ongoing. 0x03 SLAVERPREFETCH Read data prefetch state. 0x04 SLAVERTRANSFER Master read transfer ongoing. 0x05 SLAVEHALT Slave controller in Halt State waiting for resume from application. 0x06 CMTFRSTSTS Current Master Transfer State Status. 16 21 read-only CMDTID This field reflects the Transaction-ID of the current executing command. 24 27 read-only MASTERIDLE This field reflects whether the Master Controller is in Idle state or not. 28 28 read-only MST_NOT_IDLE Unspecified 0x0 MST_IDLE Unspecified 0x1 CCCDEVICESTATUS Device Operating Status Register. 0x058 read-write 0x00000000 0x20 PENDINGINTR Pending Interrupt 0 3 read-only PROTOCOLERR Protocol Error 5 5 read-only ACTIVITYMODE Activity Mode 6 7 read-only UNDERFLOWERR Underflow error 8 8 read-only SLAVEBUSY Slave Busy 9 9 read-only OVERFLOWERR Overflow Error 10 10 read-only DATANOTREADY Data not ready 11 11 read-only BUFFERNOTAVAIL Buffer not available 12 12 read-only FRAMEERROR Frame Error 13 13 read-only DEVICEADDRTABLEPOINTER Pointer for Device Address Table 0x05C read-write 0x000A02C0 0x20 PDEVADDRTABLESTARTADDR Start Address of Device Address Table. 0 15 read-only DEVADDRTABLEDEPTH Depth of Device Address Table 16 31 read-only DEVCHARTABLEPOINTER Pointer for Device Characteristics Table 0x060 read-write 0x00028200 0x20 PDEVCHARTABLESTARTADDR Start Address of Device Characteristics Table. 0 11 read-only DEVCHARTABLEDEPTH Depth of Device Characteristics Table 12 18 read-only PRESENTDEVCHARTABLEINDX Current index of Device Characteristics Table. 19 22 VENDORSPECIFICREGPOINTER Pointer for Vendor Specific Registers. 0x06C read-write 0x000000B0 0x20 PVENDORREGSTARTADDR Start Address of Vendor specific registers. 0 15 read-only SLVMIPIIDVALUE I3C MIPI Manufacturer ID Register. 0x070 read-write 0x00000000 0x20 SLVPROVIDSEL Specifies the Provisional ID Type Selector (PID[32]). 0 0 SLVMIPIMFGID Specifies the MIPI Manufacturer ID. 1 15 SLVPIDVALUE I3C Normal Provisional ID Register. 0x074 read-write 0x00000000 0x20 SLVPIDDCR Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]). 0 11 SLVINSTID This field is used to program the instance ID of the Slave. 12 15 SLVPARTID Specifies the Part ID of DWC_mipi_i3c device (PID[31:16]) 16 31 SLVCHARCTRL I3C Slave Characteristic Register. 0x078 read-write 0x00070062 0x20 MAXDATASPEEDLIMIT Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]). 0 0 IBIREQUESTCAPABLE IBI Request Capable field in Bus Characteristic Register (BCR[1]). 1 1 read-only IBIPAYLOAD IBI Payload field in Bus Characteristic Register (BCR[2]). 2 2 read-only OFFLINECAPABLE Offline Capable field in Bus Characteristic Register (BCR[3]). 3 3 read-only BRIDGEIDENTIFIER Bridge Identifier field in Bus Characteristic Register (BCR[4]). 4 4 read-only HDRCAPABLE SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]). 5 5 DEVICEROLE Device Role field in Bus Characteristic Register (BCR[7:6]). 6 7 DCR I3C Device Characteristic Value. 8 15 HDRCAP I3C Device HDR Capability Register Value. 16 23 read-only SLVMAXLEN I3C Max Write/Read Length Register. 0x07C read-write 0x00FF00FF 0x20 MWL I3C Device Max Write Length 0 15 read-only MRL I3C Device Max Read Length. 16 31 read-only MAXREADTURNAROUND MXDS Maximum Read Turnaround Time. 0x080 read-write 0x00000000 0x20 MXDSMAXRDTURN Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Slave. 0 23 read-only MAXDATASPEED The values in this register are returned by the slave as GETACCMST CCC data. 0x084 read-write 0x00000000 0x20 MXDSMAXWRSPEED Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device to DWC_mipi_i3c Slave device 0 2 12M5HZ 12.5MHz 0x0 8MHZ 8MHZ 0x1 6MHZ 6MHz 0x2 4MHZ 4MHz 0x3 2MHZ 2MHz 0x4 MXDSMAXRDSPEED Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c Slave Device to Master Device 8 10 12M5HZ 12.5MHz 0x0 8MHZ 8MHZ 0x1 6MHZ 6MHz 0x2 4MHZ 4MHz 0x3 2MHZ 2MHz 0x4 MXDSCLKDATATURN Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave device 16 18 8NS 8ns 0x0 9NS 9ns 0x1 10NS 10ns 0x2 11NS 11ns 0x3 12NS 12ns 0x4 SLVINTRREQ This register is used in slave mode of operation. 0x08C read-write 0x00000000 0x20 SIR Slave Interrupt Request 0 0 SIRCTRL Slave Interrupt Request Control 1 2 SEND Send the Assigned Dynamic Address 0x0 MR Master Request 3 3 IBISTS IBI Completion Status 8 9 read-only ACCEPTED IBI accepted by the Master (ACK response received) 0x1 NOATTEMPT IBI Not Attempted 0x3 SLVTSXSYMBLTIMING TSP/TSL Symbol Timing Register 0x090 read-write 0x0000003F 0x20 SLVTSXSYMBLCNT TSP/TSL Symbol Count Value. 0 5 DEVICECTRLEXTENDED Device Control Extended register. 0x0B0 read-write 0x00000000 0x20 DEVOPERATIONMODE This bit is used to select the Device Operation Mode before the controller is enabled. 0 1 MASTER Unspecified 0x0 SLAVE Unspecified 0x1 REQMSTACKCTRL In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC from current master. 3 3 ACK ACK GETACCMST CCC 0x0 NACK NACK GETACCMST CCC 0x1 SCLI3CODTIMING SCL I3C Open Drain Timing Register 0x0B4 read-write 0x000A0010 0x20 I3CODLCNT I3C Open Drain Low Count. 0 7 I3CODHCNT I3C Open Drain High Count. 16 23 SCLI3CPPTIMING SCL I3C Push Pull Timing Register 0x0B8 read-write 0x000A000A 0x20 I3CPPLCNT I3C Push Pull Low Count. 0 7 I3CPPHCNT I3C Push Pull High Count. 16 23 SCLI2CFMTIMING SCL I2C Fast Mode Timing Register 0x0BC read-write 0x00100010 0x20 I2CFMLCNT I2C Fast Mode Low Count 0 15 I2CFMHCNT I2C Fast Mode High Count 16 31 SCLI2CFMPTIMING SCL I2C Fast Mode Plus Timing Register 0x0C0 read-write 0x00100010 0x20 I2CFMPLCNT I2C Fast Mode Plus Low Count 0 15 I2CFMPHCNT I2C Fast Mode Plus High Count 16 23 SCLEXTLCNTTIMING SCL Extended Low Count Timing Register. 0x0C8 read-write 0x20202020 0x20 I3CEXTLCNT1 I3C Extended Low Count Register 1 0 7 I3CEXTLCNT2 I3C Extended Low Count Register 2 8 15 I3CEXTLCNT3 I3C Extended Low Count Register 3 16 23 I3CEXTLCNT4 I3C Extended Low Count Register 4 24 31 SCLEXTTERMNLCNTTIMING SCL Termination Bit Low Count Timing Register 0x0CC read-write 0x00030000 0x20 I3CEXTTERMNLCNT I3C Read Termination Bit Low count. 0 3 I3CTSSKEWCNT I3C HDR Ternary Skew Count. 16 19 SDAHOLDSWITCHDLYTIMING SDA Hold and Mode Switch Delay Timing Register 0x0D0 read-write 0x00010000 0x20 SDATXHOLD This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with 16 18 BUSFREEAVAILTIMING Bus Free and Available Timing Register 0x0D4 read-write 0x00200020 0x20 BUSFREETIME This register field is used only in Master mode of operation 0 15 BUSAVAILABLETIME This register field is used only in Slave mode of operation 16 31 BUSIDLETIMING Bus Idle Timing Register 0x0D8 read-write 0x00000020 0x20 BUSIDLETIME Bus Idle Count Value. 0 19 SCLLOWMSTEXTTIMEOUT The SCL Low Master Extended Timeout register is used to define the duration of the SCL Low Bus Reset Pattern. 0x0DC read-write 0x003567E0 0x20 SCLLOWMSTTIMEOUTCOUNT This count defines the number of core clock periods to count for generation of the SCL Low Bus Reset Pattern. 0 25 I3CVERID This register reflects the current release number of DWC_mipi_i3c 0x0E0 read-write 0x3130302A 0x20 I3CVERID Current release number 0 31 read-only I3CVERTYPE This register reflects the current release type of DWC_mipi_i3c. 0x0E4 read-write 0x6C633033 0x20 I3CVERTYPE Current release type 0 31 read-only QUEUESIZECAPABILITY This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c. 0x0E8 read-write 0x00022355 0x20 TXBUFSIZE Transmit Data Buffer Size 0 3 read-only 2DWORD 2 DWORDS 0x0 4DWORD 4 DWORDS 0x1 8DWORD 8 DWORDS 0x2 16DWORD 16 DWORDS 0x3 32DWORD 32 DWORDS 0x4 64DWORD 64 DWORDS 0x5 RXBUFSIZE Receive Data Buffer Size 4 7 read-only 2DWORD 2 DWORDS 0x0 4DWORD 4 DWORDS 0x1 8DWORD 8 DWORDS 0x2 16DWORD 16 DWORDS 0x3 32DWORD 32 DWORDS 0x4 64DWORD 64 DWORDS 0x5 CMDBUFSIZE Command Queue Size 8 11 read-only 2DWORD 2 DWORDS 0x0 4DWORD 4 DWORDS 0x1 8DWORD 8 DWORDS 0x2 16DWORD 16 DWORDS 0x3 RESPBUFSIZE Response Queue Size 12 15 read-only 2DWORD 2 DWORDS 0x0 4DWORD 4 DWORDS 0x1 8DWORD 8 DWORDS 0x2 16DWORD 16 DWORDS 0x3 IBIBUFSIZE IBI Queue Size 16 19 read-only 2DWORD 2 DWORDS 0x0 4DWORD 4 DWORDS 0x1 8DWORD 8 DWORDS 0x2 16DWORD 16 DWORDS 0x3 10 0x010 DEVCHARTABLE[%s] Unspecified DEVCHARTABLE read-write 0x200 LOC1 Description cluster: Device Characteristic Table Location-1 of Device [n] 0x0 read-write 0x00000000 0x20 LSBPROVISIONALID The LSB 32-bit value of Provisional-ID 0 31 read-only LOC2 Description cluster: Device Characteristic Table Location-2 of Device [n] 0x4 read-write 0x00000000 0x20 MSBPROVISIONALID The MSB 16-bit value of Provisional-ID 0 15 read-only LOC3 Description cluster: Device Characteristic Table Location-3 of Device [n] 0x8 read-write 0x00000000 0x20 DCR Device Characteristic Value 0 7 read-only BCR Bus Characteristic Value 8 15 read-only LOC4 Description cluster: Device Characteristic Table Location-4 of Device [n] 0xC read-write 0x00000000 0x20 DEVDYNAMICADDR Device Dynamic Address assigned. 0 7 read-only 0x20 0x4 SECDEVCHARTABLE[%s] Description collection: Secondary Master Device Characteristic Table Location of Device [n] 0x200 read-write 0x00000000 0x20 DYNAMICADDR The Dynamic Addr of Device [n] 0 7 read-only DCRTYPE The DCR TYPE of Device [n] 8 15 read-only BCRTYPE The BCR TYPE of Device [n] 16 23 read-only STATICADDR The Static Addr of Device [n] 24 31 read-only 0xA 0x4 DEVADDRTABLELOC[%s] Description collection: Device Address Table of Device [n] 0x2C0 read-write 0x00000000 0x20 DEVSTATICADDR Device Static Address. 0 6 DEVDYNAMICADDR Device Dynamic Address with parity. 16 23 DEVNACKRETRYCNT This field is used to set the Device NACK Retry count for the particular device. 29 30 LEGACYI2CDEVICE Legacy I2C device or not. 31 31 DMA Unspecified I3CCORE_DMA read-write 0x900 CH0 Unspecified I3CCORE_DMA_CH0 read-write 0x000 SAR0 This register contains the source address of the DMA transfer. 0x000 read-write 0x00000000 0x20 SAR Current Source Address of DMA transfer. 0 31 DAR0 This register contains the destination address of the DMA transfer. 0x008 read-write 0x00000000 0x20 DAR Current Destination address of DMA transfer. 0 31 CTL00 This register contains fields that control the DMA transfer. 0x018 read-write 0x02504821 0x20 INTEN Interrupt Enable Bit. 0 0 INTERRUPT_DISABLE Unspecified 0x0 INTERRUPT_ENABLE Unspecified 0x1 DSTTRWIDTH Destination Transfer Width. 1 3 DST_TR_WIDTH_0 Unspecified 0x0 DST_TR_WIDTH_1 Unspecified 0x1 DST_TR_WIDTH_2 Unspecified 0x2 DST_TR_WIDTH_3 Unspecified 0x3 DST_TR_WIDTH_4 Unspecified 0x4 DST_TR_WIDTH_5 Unspecified 0x5 DST_TR_WIDTH_6 Unspecified 0x6 DST_TR_WIDTH_7 Unspecified 0x7 RSVDSRCTRWIDTH Reserved field - read-only 4 6 read-only DINC Destination Address Increment. 7 8 DINC_0 Unspecified 0x0 DINC_1 Unspecified 0x1 DINC_2 Unspecified 0x2 DINC_3 Unspecified 0x3 SINC Source Address Increment. 9 10 SINC_0 Unspecified 0x0 SINC_1 Unspecified 0x1 SINC_2 Unspecified 0x2 SINC_3 Unspecified 0x3 DESTMSIZE Destination Burst Transaction Length. 11 13 DEST_MSIZE_0 Unspecified 0x0 DEST_MSIZE_1 Unspecified 0x1 DEST_MSIZE_2 Unspecified 0x2 DEST_MSIZE_3 Unspecified 0x3 DEST_MSIZE_4 Unspecified 0x4 DEST_MSIZE_5 Unspecified 0x5 DEST_MSIZE_6 Unspecified 0x6 DEST_MSIZE_7 Unspecified 0x7 SRCMSIZE Source Burst Transaction Length. 14 16 SRC_MSIZE_0 Unspecified 0x0 SRC_MSIZE_1 Unspecified 0x1 SRC_MSIZE_2 Unspecified 0x2 SRC_MSIZE_3 Unspecified 0x3 SRC_MSIZE_4 Unspecified 0x4 SRC_MSIZE_5 Unspecified 0x5 SRC_MSIZE_6 Unspecified 0x6 SRC_MSIZE_7 Unspecified 0x7 RSVDSRCGATHEREN Reserved field - read-only 17 17 read-only DSTSCATTEREN Destination scatter enable. 18 18 DST_SCATTER_DISABLE Unspecified 0x0 DST_SCATTER_ENABLE Unspecified 0x1 RSVDCTL Reserved field - read-only 19 19 read-only TTFC Transfer Type and Flow Control. 20 22 TT_FC_0 Unspecified 0x0 TT_FC_1 Unspecified 0x1 TT_FC_2 Unspecified 0x2 TT_FC_3 Unspecified 0x3 TT_FC_4 Unspecified 0x4 TT_FC_5 Unspecified 0x5 TT_FC_6 Unspecified 0x6 TT_FC_7 Unspecified 0x7 RSVDDMS Reserved field - read-only 23 24 read-only RSVDSMS Reserved field - read-only 25 26 read-only RSVDLLPDSTEN Reserved field - read-only 27 27 read-only RSVDLLPSRCEN Reserved field - read-only 28 28 read-only RSVD1CTL Reserved field - read-only 29 31 read-only CTL01 This register contains fields that control the DMA transfer. 0x01C read-write 0x00000002 0x20 BLOCKTS Block Transfer Size. 0 4 RSVD2CTL Reserved field - read-only 5 11 read-only DONE Done bit. 12 12 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 CFG0L This register contains fields that configure the DMA transfer. 0x040 read-write 0x00000E00 0x20 RSVDCFG Reserved field - read-only 0 4 read-only CHPRIOR Channel Priority. 5 7 CH_PRIOR_0 Unspecified 0x0 CH_PRIOR_1 Unspecified 0x1 CH_PRIOR_2 Unspecified 0x2 CH_PRIOR_3 Unspecified 0x3 CH_PRIOR_4 Unspecified 0x4 CH_PRIOR_5 Unspecified 0x5 CH_PRIOR_6 Unspecified 0x6 CH_PRIOR_7 Unspecified 0x7 CHSUSP Channel Suspend. 8 8 NOT_SUSPENDED Unspecified 0x0 SUSPENDED Unspecified 0x1 FIFOEMPTY Channel FIFO status. 9 9 read-only NOT_EMPTY Unspecified 0x0 EMPTY Unspecified 0x1 HSSELDST Destination Software or Hardware Handshaking Select. 10 10 HARDWARE_HS Unspecified 0x0 SOFTWARE_HS Unspecified 0x1 HSSELSRC Source Software or Hardware Handshaking Select. 11 11 HARDWARE_HS Unspecified 0x0 SOFTWARE_HS Unspecified 0x1 RSVDLOCKCHL Reserved field - read-only 12 13 read-only RSVDLOCKBL Reserved field - read-only 14 15 read-only RSVDLOCKCH Reserved field - read-only 16 16 read-only RSVDLOCKB Reserved field - read-only 17 17 read-only DSTHSPOL Destination Handshaking Interface Polarity. 18 18 ACTIVE_HIGH Unspecified 0x0 ACTIVE_LOW Unspecified 0x1 SRCHSPOL Source Handshaking Interface Polarity. 19 19 ACTIVE_HIGH Unspecified 0x0 ACTIVE_LOW Unspecified 0x1 MAXABRST Maximum AMBA Burst Length. 20 29 RSVDRELOADSRC Reserved field - read-only 30 30 read-only RSVDRELOADDST Reserved field- read-only 31 31 read-only CFG0H This register contains fields that configure the DMA transfer. 0x044 read-write 0x00000004 0x20 FCMODE Flow Control Mode. 0 0 FCMODE_0 Unspecified 0x0 FCMODE_1 Unspecified 0x1 FIFOMODE FIFO Mode Select. 1 1 FIFO_MODE_0 Unspecified 0x0 FIFO_MODE_1 Unspecified 0x1 PROTCTL Protection Control bits used to drive the AHB HPROT[3:1] bus. 2 4 RSVDDSUPDEN Reserved field- read-only 5 5 read-only RSVDSSUPDEN Reserved field- read-only 6 6 read-only SRCPER Source Hardware Interface. 7 7 RSVD1CFG Reserved field - read-only 8 10 read-only DESTPER Destination hardware interface. 11 11 RSVD2CFG Reserved field - read-only 12 14 read-only RSVD3CFG Reserved field - read-only 15 31 read-only DSR0 Destination Scatter register. 0x050 read-write 0x00000000 0x20 DSI Destination Scatter Interval. 0 19 DSC Destination Scatter Count. 20 24 CH1 Unspecified I3CCORE_DMA_CH1 read-write 0x058 SAR1 This register contains the source address of the DMA transfer. 0x000 read-write 0x00000000 0x20 SAR Current Source Address of DMA transfer. 0 31 DAR1 This register contains the destination address of the DMA transfer. 0x008 read-write 0x00000000 0x20 DAR Current Destination address of DMA transfer. 0 31 CTL1L This register contains fields that control the DMA transfer. 0x018 read-write 0x00F04805 0x20 INTEN Interrupt Enable Bit. 0 0 INTERRUPT_DISABLE Unspecified 0x0 INTERRUPT_ENABLE Unspecified 0x1 RSVDDSTTRWIDTH Reserved field - read-only 1 3 read-only SRCTRWIDTH Source Transfer Width. 4 6 SRC_TR_WIDTH_0 Unspecified 0x0 SRC_TR_WIDTH_1 Unspecified 0x1 SRC_TR_WIDTH_2 Unspecified 0x2 SRC_TR_WIDTH_3 Unspecified 0x3 SRC_TR_WIDTH_4 Unspecified 0x4 SRC_TR_WIDTH_5 Unspecified 0x5 SRC_TR_WIDTH_6 Unspecified 0x6 SRC_TR_WIDTH_7 Unspecified 0x7 DINC Destination Address Increment. 7 8 DINC_0 Unspecified 0x0 DINC_1 Unspecified 0x1 DINC_2 Unspecified 0x2 DINC_3 Unspecified 0x3 SINC Source Address Increment. 9 10 SINC_0 Unspecified 0x0 SINC_1 Unspecified 0x1 SINC_2 Unspecified 0x2 SINC_3 Unspecified 0x3 DESTMSIZE Destination Burst Transaction Length. 11 13 DEST_MSIZE_0 Unspecified 0x0 DEST_MSIZE_1 Unspecified 0x1 DEST_MSIZE_2 Unspecified 0x2 DEST_MSIZE_3 Unspecified 0x3 DEST_MSIZE_4 Unspecified 0x4 DEST_MSIZE_5 Unspecified 0x5 DEST_MSIZE_6 Unspecified 0x6 DEST_MSIZE_7 Unspecified 0x7 SRCMSIZE Source Burst Transaction Length. 14 16 SRC_MSIZE_0 Unspecified 0x0 SRC_MSIZE_1 Unspecified 0x1 SRC_MSIZE_2 Unspecified 0x2 SRC_MSIZE_3 Unspecified 0x3 SRC_MSIZE_4 Unspecified 0x4 SRC_MSIZE_5 Unspecified 0x5 SRC_MSIZE_6 Unspecified 0x6 SRC_MSIZE_7 Unspecified 0x7 SRCGATHEREN Source gather enable. 17 17 SRC_GATHER_DISABLE Unspecified 0x0 SRC_GATHER_ENABLE Unspecified 0x1 RSVDDSTSCATTEREN Reserved field - read-only 18 18 read-only RSVDCTL Reserved field - read-only 19 19 read-only TTFC Transfer Type and Flow Control. 20 22 TT_FC_0 Unspecified 0x0 TT_FC_1 Unspecified 0x1 TT_FC_2 Unspecified 0x2 TT_FC_3 Unspecified 0x3 TT_FC_4 Unspecified 0x4 TT_FC_5 Unspecified 0x5 TT_FC_6 Unspecified 0x6 TT_FC_7 Unspecified 0x7 RSVDDMS Reserved field - read-only 23 24 read-only RSVDSMS Reserved field - read-only 25 26 read-only RSVDLLPDSTEN Reserved field - read-only 27 27 read-only RSVDLLPSRCEN Reserved field - read-only 28 28 read-only RSVD1CTL Reserved field - read-only 29 31 read-only CTL1H This register contains fields that control the DMA transfer. 0x01C read-write 0x00000002 0x20 BLOCKTS Block Transfer Size. 0 4 RSVD2CTL Reserved field - read-only 5 11 read-only DONE Done bit. 12 12 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 CFG1L This register contains fields that configure the DMA transfer. 0x040 read-write 0x00000E20 0x20 RSVDCFG Reserved field - read-only 0 4 read-only CHPRIOR Channel Priority. 5 7 CH_PRIOR_0 Unspecified 0x0 CH_PRIOR_1 Unspecified 0x1 CH_PRIOR_2 Unspecified 0x2 CH_PRIOR_3 Unspecified 0x3 CH_PRIOR_4 Unspecified 0x4 CH_PRIOR_5 Unspecified 0x5 CH_PRIOR_6 Unspecified 0x6 CH_PRIOR_7 Unspecified 0x7 CHSUSP Channel Suspend. 8 8 NOT_SUSPENDED Unspecified 0x0 SUSPENDED Unspecified 0x1 FIFOEMPTY Channel FIFO status. 9 9 read-only NOT_EMPTY Unspecified 0x0 EMPTY Unspecified 0x1 HSSELDST Destination Software or Hardware Handshaking Select. 10 10 HARDWARE_HS Unspecified 0x0 SOFTWARE_HS Unspecified 0x1 HSSELSRC Source Software or Hardware Handshaking Select. 11 11 HARDWARE_HS Unspecified 0x0 SOFTWARE_HS Unspecified 0x1 RSVDLOCKCHL Reserved field - read-only 12 13 read-only RSVDLOCKBL Reserved field - read-only 14 15 read-only RSVDLOCKCH Reserved field - read-only 16 16 read-only RSVDLOCKB Reserved field - read-only 17 17 read-only DSTHSPOL Destination Handshaking Interface Polarity. 18 18 ACTIVE_HIGH Unspecified 0x0 ACTIVE_LOW Unspecified 0x1 SRCHSPOL Source Handshaking Interface Polarity. 19 19 ACTIVE_HIGH Unspecified 0x0 ACTIVE_LOW Unspecified 0x1 MAXABRST Maximum AMBA Burst Length. 20 29 RSVDRELOADSRC Reserved field - read-only 30 30 read-only RSVDRELOADDST Reserved field- read-only 31 31 read-only CFG1H This register contains fields that configure the DMA transfer. 0x044 read-write 0x00000004 0x20 FCMODE Flow Control Mode. 0 0 FCMODE_0 Unspecified 0x0 FCMODE_1 Unspecified 0x1 FIFOMODE FIFO Mode Select. 1 1 FIFO_MODE_0 Unspecified 0x0 FIFO_MODE_1 Unspecified 0x1 PROTCTL Protection Control bits used to drive the AHB HPROT[3:1] bus. 2 4 RSVDDSUPDEN Reserved field- read-only 5 5 read-only RSVDSSUPDEN Reserved field- read-only 6 6 read-only SRCPER Source Hardware Interface. 7 7 RSVD1CFG Reserved field - read-only 8 10 read-only DESTPER Destination hardware interface. 11 11 SGR1 Source Gather register 0x048 read-write 0x00000000 0x20 SGI Source Gather Interval. 0 19 SGC Source Gather Count. 20 24 INT Unspecified I3CCORE_DMA_INT read-write 0x2C0 RAWTFR Interrupt events are stored in this Raw Interrupt Status register before masking. 0x000 read-write 0x00000000 0x20 RAW Raw Status for IntTfr Interrupt 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RAWBLOCK Interrupt events are stored in this Raw Interrupt Status register before masking. 0x008 read-write 0x00000000 0x20 RAW Raw Status for IntBlock Interrupt 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RAWSRCTRAN Interrupt events are stored in this Raw Interrupt Status register before masking. 0x010 read-write 0x00000000 0x20 RAW Raw Status for IntSrcTran Interrupt 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RAWDSTTRAN Interrupt events are stored in this Raw Interrupt Status register before masking. 0x018 read-write 0x00000000 0x20 RAW Raw Status for IntDstTran Interrupt 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RAWERR Interrupt events are stored in this Raw Interrupt Status register before masking. 0x020 read-write 0x00000000 0x20 RAW Raw Status for IntErr Interrupt 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STATUSTFR Channel DMA Transfer complete interrupt event from all channels is stored in this Interrupt Status register after masking. 0x028 read-write 0x00000000 0x20 STATUS Status for IntTfr Interrupt 0 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STATUSBLOCK Channel Block complete interrupt event from all channels is stored in this Interrupt Status register after masking. 0x030 read-write 0x00000000 0x20 STATUS Status for IntBlock Interrupt 0 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STATUSSRCTRAN Channel Source Transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. 0x038 read-write 0x00000000 0x20 STATUS Status for IntSrcTran Interrupt 0 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STATUSDSTTRAN Channel destination transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. 0x040 read-write 0x00000000 0x20 STATUS Status for IntDstTran Interrupt 0 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 STATUSERR Channel Error interrupt event from all channels is stored in this Interrupt Status register after masking. 0x048 read-write 0x00000000 0x20 STATUS Status for IntErr Interrupt 0 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 MASKTFR The contents of the Raw Status register RawTfr is masked with the contents of the Mask register MaskTfr. 0x050 read-write 0x00000000 0x20 INTMASK Mask for IntTfr Interrupt 0 1 MASK Unspecified 0x0 UNMASK Unspecified 0x1 RSVDMASKTFR Reserved field - read-only 2 7 read-only INTMASKWE Interrupt Mask Write Enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 MASKBLOCK The contents of the Raw Status register RawBlock is masked with the contents of the Mask register MaskBlock. 0x058 read-write 0x00000000 0x20 INTMASK Mask for IntBlock Interrupt 0 1 MASK Unspecified 0x0 UNMASK Unspecified 0x1 RSVDMASKBLOCK Reserved field- read-only 2 7 read-only INTMASKWE Interrupt Mask Write Enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 MASKSRCTRAN The contents of the Raw Status register RawSrcTran is masked with the contents of the Mask register MaskSrcTran. 0x060 read-write 0x00000000 0x20 INTMASK Mask for IntSrcTran Interrupt 0 1 MASK Unspecified 0x0 UNMASK Unspecified 0x1 RSVDMASKSRCTRAN Reserved field- read-only 2 7 read-only INTMASKWE Interrupt Mask Write Enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 MASKDSTTRAN The contents of the Raw Status register RawDstTran is masked with the contents of the Mask register MaskDstTran. 0x068 read-write 0x00000000 0x20 INTMASK Mask for IntDstTran Interrupt 0 1 MASK Unspecified 0x0 UNMASK Unspecified 0x1 RSVDMASKDSTTRAN Reserved field - read-only 2 7 read-only INTMASKWE Interrupt Mask Write Enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 MASKERR The contents of the Raw Status register RawErr is masked with the contents of the Mask register MaskErr. 0x070 read-write 0x00000000 0x20 INTMASK Mask for IntErr Interrupt 0 1 MASK Unspecified 0x0 UNMASK Unspecified 0x1 RSVDMASKERR Reserved field- read-only 2 7 read-only INTMASKWE Interrupt Mask Write Enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 CLEARTFR Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. 0x078 read-write 0x00000000 0x20 CLEAR Clear for IntTfr Interrupt 0 1 write-only NOT_CLEAR Unspecified 0x0 CLEAR Unspecified 0x1 CLEARBLOCK Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. 0x080 read-write 0x00000000 0x20 CLEAR Clear for IntBlock Interrupt 0 1 write-only CLEARSRCTRAN Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. 0x088 read-write 0x00000000 0x20 CLEAR Clear for IntSrcTran Interrupt 0 1 write-only NOT_CLEAR Unspecified 0x0 CLEAR Unspecified 0x1 CLEARDSTTRAN Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. 0x090 read-write 0x00000000 0x20 CLEAR Clear for IntDstTran Interrupt 0 1 write-only NOT_CLEAR Unspecified 0x0 CLEAR Unspecified 0x1 CLEARERR Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. 0x098 read-write 0x00000000 0x20 CLEAR Clear for IntErr Interrupt 0 1 write-only NOT_CLEAR Unspecified 0x0 CLEAR Unspecified 0x1 STATUSINT The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr is ORed to produce a single bit for each interrupt type in the Combined Status register (StatusInt). 0x0A0 read-write 0x00000000 0x20 TFR OR of the contents of StatusTfr register 0 0 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 BLOCK OR of the contents of StatusBlock register 1 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SRCT OR of the contents of StatusSrcTran 2 2 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DSTT OR of the contents of StatusDstTran 3 3 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 ERR OR of the contents of StatusErr 4 4 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 SWHANDSHAKE Unspecified I3CCORE_DMA_SWHANDSHAKE read-write 0x368 REQSRCREG A bit is assigned for each channel in this register. 0x000 read-write 0x00000000 0x20 SRCREQ Source Software Transaction Request 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSVDREQSRCREG Reserved field - read-only 2 7 read-only SRCREQWE Source Software Transaction Request write enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 REQDSTREG A bit is assigned for each channel in this register. 0x008 read-write 0x00000000 0x20 DSTREQ Destination Software Transaction Request 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSVDREQDSTREG Reserved field - read-only 2 7 read-only DSTREQWE Destination Software Transaction Request write enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SGLRQSRCREG A bit is assigned for each channel in this register. 0x010 read-write 0x00000000 0x20 SRCSGLREQ Source Single Transaction Request 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSVDSGLRQSRCREG Reserved field - read-only 2 7 read-only SRCSGLREQWE Source Single Transaction Request write enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SGLRQDSTREG A bit is assigned for each channel in this register. 0x018 read-write 0x00000000 0x20 DSTSGLREQ Destination Single Transaction Request 0 1 INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSVDSGLRQDSTREG Reserved field - read-only 2 7 read-only DSTSGLREQWE Destination Single Transaction Request write enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 LSTSRCREG A bit is assigned for each channel in this register. 0x020 read-write 0x00000000 0x20 LSTSRC Source Last Transaction Request register 0 1 NOT_LAST Unspecified 0x0 LAST Unspecified 0x1 RSVDLSTSRCREG Reserved field- read-only 2 7 read-only LSTSRCWE Source Last Transaction Request write enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 LSTDSTREG A bit is assigned for each channel in this register. 0x028 read-write 0x00000000 0x20 LSTDST Destination Last Transaction Request 0 1 NOT_LAST Unspecified 0x0 LAST Unspecified 0x1 RSVDLSTDSTREG Reserved field - read-only 2 7 read-only LSTDSTWE Source Last Transaction Request write enable 8 9 write-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 MISC Unspecified I3CCORE_DMA_MISC read-write 0x398 DMACFGREG This register is used to enable the DW_ahb_dmac, which must be done before any channel activity can begin. 0x000 read-write 0x00000000 0x20 DMAEN DW_ahb_dmac Enable bit. 0 0 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 CHENREG This is the DW_ahb_dmac Channel Enable Register. 0x008 read-write 0x00000000 0x20 CHEN Channel Enable. 0 1 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 RSVDCHENREG Reserved field - read-only 2 7 read-only CHENWE Channel enable register 8 9 write-only DMAIDREG This is the DW_ahb_dmac ID register, which is a read-only register that reads back the coreConsultant-configured hardcoded ID number, DMAH_ID_NUM. 0x010 read-write 0x00000000 0x20 DMAID Hardcoded DW_ahb_dmac peripheral ID. 0 31 read-only DMATESTREG This register is used to put the AHB slave interface into test mode, during which the readback value of the writable registers match the value written, assuming the DW_ahb_dmac configuration has not optimized the same registers. 0x018 read-write 0x00000000 0x20 TESTSLVIF DMA Test register 0 0 NORMAL_MODE Unspecified 0x0 TEST_MODE Unspecified 0x1 DMALPTIMEOUTREG This register holds the timeout value of Low Power Counter. 0x020 read-write 0x00000008 0x20 DMALPTIMEOUT This field holds timeout value of low power counter register. 0 3 DMACOMPPARAMS6L DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information about the component parameter settings for Channel 7. 0x034 read-write 0x00000000 0x20 CH7DTW The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter. 0 2 read-only NO_HARDCODE Unspecified 0x0 DTW_8 Unspecified 0x1 DTW_16 Unspecified 0x2 DTW_32 Unspecified 0x3 DTW_64 Unspecified 0x4 DTW_128 Unspecified 0x5 DTW_256 Unspecified 0x6 CH7STW The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter. 3 5 read-only NO_HARDCODE Unspecified 0x0 STW_8 Unspecified 0x1 STW_16 Unspecified 0x2 STW_32 Unspecified 0x3 STW_64 Unspecified 0x4 STW_128 Unspecified 0x5 STW_256 Unspecified 0x6 CH7STATDST The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant parameter. 6 6 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH7STATSRC The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant parameter. 7 7 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH7DSTSCAEN The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant parameter. 8 8 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH7SRCGATEN The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant parameter. 9 9 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH7LOCKEN The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parameter. 10 10 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH7MULTIBLKEN The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant parameter. 11 11 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH7CTLWBEN The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant parameter. 12 12 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH7HCLLP The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant parameter. 13 13 read-only PROGRAMMABLE Unspecified 0x0 HARDCODED Unspecified 0x1 CH7FC The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter. 14 15 read-only FC_DMA Unspecified 0x0 FC_SRC Unspecified 0x1 FC_DST Unspecified 0x2 FC_ANY Unspecified 0x3 CH7MAXMULTSIZE The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant parameter. 16 18 read-only MAX_MULT_SIZE_4 Unspecified 0x0 MAX_MULT_SIZE_8 Unspecified 0x1 MAX_MULT_SIZE_16 Unspecified 0x2 MAX_MULT_SIZE_32 Unspecified 0x3 MAX_MULT_SIZE_64 Unspecified 0x4 MAX_MULT_SIZE_128 Unspecified 0x5 MAX_MULT_SIZE_256 Unspecified 0x6 CH7DMS The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter. 19 21 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH7LMS The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter. 22 24 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH7SMS The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter. 25 27 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH7FIFODEPTH The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant parameter. 28 30 read-only FIFO_DEPTH_8 Unspecified 0x0 FIFO_DEPTH_16 Unspecified 0x1 FIFO_DEPTH_32 Unspecified 0x2 FIFO_DEPTH_64 Unspecified 0x3 FIFO_DEPTH_128 Unspecified 0x4 FIFO_DEPTH_256 Unspecified 0x5 DMACOMPPARAMS5L DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. 0x038 read-write 0x00000000 0x20 CH6DTW The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter. 0 2 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH6STW The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter. 3 5 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH6STATDST The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant parameter. 6 6 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH6STATSRC The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant parameter. 7 7 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH6DSTSCAEN The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant parameter. 8 8 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH6SRCGATEN The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant parameter. 9 9 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH6LOCKEN The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parameter. 10 10 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH6MULTIBLKEN The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant parameter. 11 11 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH6CTLWBEN The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant parameter. 12 12 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH6HCLLP The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant parameter. 13 13 read-only PROGRAMMABLE Unspecified 0x0 HARDCODED Unspecified 0x1 CH6FC The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter. 14 15 read-only FC_DMA Unspecified 0x0 FC_SRC Unspecified 0x1 FC_DST Unspecified 0x2 FC_ANY Unspecified 0x3 CH6MAXMULTSIZE The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant parameter. 16 18 read-only MAX_MULT_SIZE_4 Unspecified 0x0 MAX_MULT_SIZE_8 Unspecified 0x1 MAX_MULT_SIZE_16 Unspecified 0x2 MAX_MULT_SIZE_32 Unspecified 0x3 MAX_MULT_SIZE_64 Unspecified 0x4 MAX_MULT_SIZE_128 Unspecified 0x5 MAX_MULT_SIZE_256 Unspecified 0x6 CH6DMS The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter. 19 21 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH6LMS The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter. 22 24 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH6SMS The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter. 25 27 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH6FIFODEPTH The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant parameter. 28 30 read-only IFO_DEPTH_8 Unspecified 0x0 FIFO_DEPTH_16 Unspecified 0x1 FIFO_DEPTH_32 Unspecified 0x2 FIFO_DEPTH_64 Unspecified 0x3 FIFO_DEPTH_128 Unspecified 0x4 FIFO_DEPTH_256 Unspecified 0x5 DMACOMPPARAMS5H DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. 0x03C read-write 0x00000000 0x20 CH5DTW The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter. 0 2 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH5STW The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter. 3 5 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH5STATDST The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant parameter. 6 6 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH5STATSRC The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant parameter. 7 7 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH5DSTSCAEN The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant parameter. 8 8 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH5SRCGATEN The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant parameter. 9 9 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH5LOCKEN The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parameter. 10 10 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH5MULTIBLKEN The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant parameter. 11 11 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH5CTLWBEN The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant parameter. 12 12 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH5HCLLP The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant parameter. 13 13 read-only PROGRAMMABLE Unspecified 0x0 HARDCODED Unspecified 0x1 CH5FC The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter. 14 15 read-only FC_DMA Unspecified 0x0 FC_SRC Unspecified 0x1 FC_DST Unspecified 0x2 FC_ANY Unspecified 0x3 CH5MAXMULTSIZE The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant parameter. 16 18 read-only MAX_MULT_SIZE_4 Unspecified 0x0 MAX_MULT_SIZE_8 Unspecified 0x1 MAX_MULT_SIZE_16 Unspecified 0x2 MAX_MULT_SIZE_32 Unspecified 0x3 MAX_MULT_SIZE_64 Unspecified 0x4 MAX_MULT_SIZE_128 Unspecified 0x5 MAX_MULT_SIZE_256 Unspecified 0x6 CH5DMS The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter. 19 21 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH5LMS The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter. 22 24 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH5SMS The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter. 25 27 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH5FIFODEPTH The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant parameter. 28 30 read-only FIFO_DEPTH_8 Unspecified 0x0 FIFO_DEPTH_16 Unspecified 0x1 FIFO_DEPTH_32 Unspecified 0x2 FIFO_DEPTH_64 Unspecified 0x3 FIFO_DEPTH_128 Unspecified 0x4 FIFO_DEPTH_256 Unspecified 0x5 DMACOMPPARAMS4L DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. 0x040 read-write 0x00000000 0x20 CH4DTW The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter. 0 2 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH4STW The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter. 3 5 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH4STATDST The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant parameter. 6 6 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH4STATSRC The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant parameter. 7 7 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH4DSTSCAEN The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant parameter. 8 8 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH4SRCGATEN The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant parameter. 9 9 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH4LOCKEN The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parameter. 10 10 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH4MULTIBLKEN The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant parameter. 11 11 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH4CTLWBEN The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant parameter. 12 12 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH4HCLLP The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant parameter. 13 13 read-only PROGRAMMABLE Unspecified 0x0 HARDCODED Unspecified 0x1 CH4FC The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter. 14 15 read-only FC_DMA Unspecified 0x0 FC_SRC Unspecified 0x1 FC_DST Unspecified 0x2 FC_ANY Unspecified 0x3 CH4MAXMULTSIZE The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant parameter. 16 18 read-only MAX_MULT_SIZE_4 Unspecified 0x0 MAX_MULT_SIZE_8 Unspecified 0x1 MAX_MULT_SIZE_16 Unspecified 0x2 MAX_MULT_SIZE_32 Unspecified 0x3 MAX_MULT_SIZE_64 Unspecified 0x4 MAX_MULT_SIZE_128 Unspecified 0x5 MAX_MULT_SIZE_256 Unspecified 0x6 CH4DMS The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter. 19 21 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH4LMS The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter. 22 24 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH4SMS The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter. 25 27 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH4FIFODEPTH The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant parameter. 28 30 read-only FIFO_DEPTH_8 Unspecified 0x0 FIFO_DEPTH_16 Unspecified 0x1 FIFO_DEPTH_32 Unspecified 0x2 FIFO_DEPTH_64 Unspecified 0x3 FIFO_DEPTH_128 Unspecified 0x4 FIFO_DEPTH_256 Unspecified 0x5 DMACOMPPARAMS4H DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. 0x044 read-write 0x00000000 0x20 CH3DTW The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter. 0 2 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH3STW The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter. 3 5 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH3STATDST The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant parameter. 6 6 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH3STATSRC The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant parameter. 7 7 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH3DSTSCAEN The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant parameter. 8 8 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH3SRCGATEN The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant parameter. 9 9 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH3LOCKEN The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parameter. 10 10 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH3MULTIBLKEN The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant parameter. 11 11 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH3CTLWBEN The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant parameter. 12 12 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH3HCLLP The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant parameter. 13 13 read-only PROGRAMMABLE Unspecified 0x0 HARDCODED Unspecified 0x1 CH3FC The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter. 14 15 read-only FC_DMA Unspecified 0x0 FC_SRC Unspecified 0x1 FC_DST Unspecified 0x2 FC_ANY Unspecified 0x3 CH3MAXMULTSIZE The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant parameter. 16 18 read-only MAX_MULT_SIZE_4 Unspecified 0x0 MAX_MULT_SIZE_8 Unspecified 0x1 MAX_MULT_SIZE_16 Unspecified 0x2 MAX_MULT_SIZE_32 Unspecified 0x3 MAX_MULT_SIZE_64 Unspecified 0x4 MAX_MULT_SIZE_128 Unspecified 0x5 MAX_MULT_SIZE_256 Unspecified 0x6 CH3DMS The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter. 19 21 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH3LMS The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter. 22 24 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH3SMS The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter. 25 27 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH3FIFODEPTH The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant parameter. 28 30 read-only FIFO_DEPTH_8 Unspecified 0x0 FIFO_DEPTH_16 Unspecified 0x1 FIFO_DEPTH_32 Unspecified 0x2 FIFO_DEPTH_64 Unspecified 0x3 FIFO_DEPTH_128 Unspecified 0x4 FIFO_DEPTH_256 Unspecified 0x5 DMACOMPPARAMS3L DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. 0x048 read-write 0x00000000 0x20 CH2DTW The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter. 0 2 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH2STW The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter. 3 5 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH2STATDST The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant parameter. 6 6 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH2STATSRC The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant parameter. 7 7 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH2DSTSCAEN The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant parameter. 8 8 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH2SRCGATEN The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant parameter. 9 9 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH2LOCKEN The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parameter. 10 10 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH2MULTIBLKEN The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant parameter. 11 11 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH2CTLWBEN The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant parameter. 12 12 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH2HCLLP The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant parameter. 13 13 read-only PROGRAMMABLE Unspecified 0x0 HARDCODED Unspecified 0x1 CH2FC The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter. 14 15 read-only FC_DMA Unspecified 0x0 FC_SRC Unspecified 0x1 FC_DST Unspecified 0x2 FC_ANY Unspecified 0x3 CH2MAXMULTSIZE The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant parameter. 16 18 read-only MAX_MULT_SIZE_4 Unspecified 0x0 MAX_MULT_SIZE_8 Unspecified 0x1 MAX_MULT_SIZE_16 Unspecified 0x2 MAX_MULT_SIZE_32 Unspecified 0x3 MAX_MULT_SIZE_64 Unspecified 0x4 MAX_MULT_SIZE_128 Unspecified 0x5 MAX_MULT_SIZE_256 Unspecified 0x6 CH2DMS The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter. 19 21 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH2LMS The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter. 22 24 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMALE Unspecified 0x4 CH2SMS The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter. 25 27 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMALE Unspecified 0x4 CH2FIFODEPTH The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant parameter. 28 30 read-only FIFO_DEPTH_8 Unspecified 0x0 FIFO_DEPTH_16 Unspecified 0x1 FIFO_DEPTH_32 Unspecified 0x2 FIFO_DEPTH_64 Unspecified 0x3 FIFO_DEPTH_128 Unspecified 0x4 FIFO_DEPTH_256 Unspecified 0x5 DMACOMPPARAMS3H DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. 0x04C read-write 0x1109A203 0x20 CH1DTW The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter. 0 2 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH1STW The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter. 3 5 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH1STATDST The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant parameter. 6 6 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH1STATSRC The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant parameter. 7 7 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH1DSTSCAEN The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant parameter. 8 8 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH1SRCGATEN The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant parameter. 9 9 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH1LOCKEN The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parameter. 10 10 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH1MULTIBLKEN The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant parameter. 11 11 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH1CTLWBEN The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant parameter. 12 12 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH1HCLLP The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant parameter. 13 13 read-only PROGRAMMABLE Unspecified 0x0 HARDCODED Unspecified 0x1 CH1FC The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter. 14 15 read-only FC_DMA Unspecified 0x0 FC_SRC Unspecified 0x1 FC_DST Unspecified 0x2 FC_ANY Unspecified 0x3 CH1MAXMULTSIZE The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant parameter. 16 18 read-only MAX_MULT_SIZE_4 Unspecified 0x0 MAX_MULT_SIZE_8 Unspecified 0x1 MAX_MULT_SIZE_16 Unspecified 0x2 MAX_MULT_SIZE_32 Unspecified 0x3 MAX_MULT_SIZE_64 Unspecified 0x4 MAX_MULT_SIZE_128 Unspecified 0x5 MAX_MULT_SIZE_256 Unspecified 0x6 CH1DMS The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter. 19 21 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH1LMS The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter. 22 24 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH1SMS The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter. 25 27 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH1FIFODEPTH The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant parameter. 28 30 read-only FIFO_DEPTH_8 Unspecified 0x0 FIFO_DEPTH_16 Unspecified 0x1 FIFO_DEPTH_32 Unspecified 0x2 FIFO_DEPTH_64 Unspecified 0x3 FIFO_DEPTH_128 Unspecified 0x4 FIFO_DEPTH_256 Unspecified 0x5 DMACOMPPARAMS2L DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. 0x050 read-write 0x13016118 0x20 CH0DTW The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter. 0 2 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH0STW The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter. 3 5 read-only TRANS_WIDTH_PROGRAMMABLE Unspecified 0x0 TRANS_WIDTH_8 Unspecified 0x1 TRANS_WIDTH_16 Unspecified 0x2 TRANS_WIDTH_32 Unspecified 0x3 TRANS_WIDTH_64 Unspecified 0x4 TRANS_WIDTH_128 Unspecified 0x5 TRANS_WIDTH_256 Unspecified 0x6 CH0STATDST The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant parameter. 6 6 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH0STATSRC The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant parameter. 7 7 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH0DSTSCAEN The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant parameter. 8 8 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH0SRCGATEN The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant parameter. 9 9 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH0LOCKEN The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parameter. 10 10 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH0MULTIBLKEN The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant parameter. 11 11 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH0CTLWBEN The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant parameter. 12 12 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 CH0HCLLP The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant parameter. 13 13 read-only PROGRAMMABLE Unspecified 0x0 HARDCODED Unspecified 0x1 CH0FC The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter. 14 15 read-only FC_DMA Unspecified 0x0 FC_SRC Unspecified 0x1 FC_DST Unspecified 0x2 FC_ANY Unspecified 0x3 CH0MAXMULTSIZE The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant parameter. 16 18 read-only MAX_MULT_SIZE_4 Unspecified 0x0 MAX_MULT_SIZE_8 Unspecified 0x1 MAX_MULT_SIZE_16 Unspecified 0x2 MAX_MULT_SIZE_32 Unspecified 0x3 MAX_MULT_SIZE_64 Unspecified 0x4 MAX_MULT_SIZE_128 Unspecified 0x5 MAX_MULT_SIZE_256 Unspecified 0x6 CH0DMS The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter. 19 21 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH0LMS The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter. 22 24 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH0SMS The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter. 25 27 read-only MASTER_1 Unspecified 0x0 MASTER_2 Unspecified 0x1 MASTER_3 Unspecified 0x2 MASTER_4 Unspecified 0x3 PROGRAMMABLE Unspecified 0x4 CH0FIFODEPTH The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant parameter. 28 30 read-only FIFO_DEPTH_8 Unspecified 0x0 FIFO_DEPTH_16 Unspecified 0x1 FIFO_DEPTH_32 Unspecified 0x2 FIFO_DEPTH_64 Unspecified 0x3 FIFO_DEPTH_128 Unspecified 0x4 FIFO_DEPTH_256 Unspecified 0x5 DMACOMPPARAMS2H DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. 0x054 read-write 0x00000000 0x20 CHOMULTIBLKTYPE The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsultant parameter. 0 3 read-only PROGRAMMABLE Unspecified 0x0 CONT_RELOAD Unspecified 0x1 RELOAD_CONT Unspecified 0x2 RELOAD_RELOAD Unspecified 0x3 CONT_LLP Unspecified 0x4 RELOAD_LLP Unspecified 0x5 CNT_LLP Unspecified 0x6 LLP_RELOAD Unspecified 0x7 LLP_LLP Unspecified 0x8 CH1MULTIBLKTYPE The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsultant parameter. 4 7 read-only PROGRAMMABLE Unspecified 0x0 CONT_RELOAD Unspecified 0x1 RELOAD_CONT Unspecified 0x2 RELOAD_RELOAD Unspecified 0x3 CONT_LLP Unspecified 0x4 RELOAD_LLP Unspecified 0x5 CNT_LLP Unspecified 0x6 LLP_RELOAD Unspecified 0x7 LLP_LLP Unspecified 0x8 CH2MULTIBLKTYPE The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsultant parameter. 8 11 read-only PROGRAMMABLE Unspecified 0x0 CONT_RELOAD Unspecified 0x1 RELOAD_CONT Unspecified 0x2 RELOAD_RELOAD Unspecified 0x3 CONT_LLP Unspecified 0x4 RELOAD_LLP Unspecified 0x5 CNT_LLP Unspecified 0x6 LLP_RELOAD Unspecified 0x7 LLP_LLP Unspecified 0x8 CH3MULTIBLKTYPE The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsultant parameter. 12 15 read-only PROGRAMMABLE Unspecified 0x0 CONT_RELOAD Unspecified 0x1 RELOAD_CONT Unspecified 0x2 RELOAD_RELOAD Unspecified 0x3 CONT_LLP Unspecified 0x4 RELOAD_LLP Unspecified 0x5 CNT_LLP Unspecified 0x6 LLP_RELOAD Unspecified 0x7 LLP_LLP Unspecified 0x8 CH4MULTIBLKTYPE The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsultant parameter. 16 19 read-only PROGRAMMABLE Unspecified 0x0 CONT_RELOAD Unspecified 0x1 RELOAD_CONT Unspecified 0x2 RELOAD_RELOAD Unspecified 0x3 CONT_LLP Unspecified 0x4 RELOAD_LLP Unspecified 0x5 CNT_LLP Unspecified 0x6 LLP_RELOAD Unspecified 0x7 LLP_LLP Unspecified 0x8 CH5MULTIBLKTYPE The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsultant parameter. 20 23 read-only PROGRAMMABLE Unspecified 0x0 CONT_RELOAD Unspecified 0x1 RELOAD_CONT Unspecified 0x2 RELOAD_RELOAD Unspecified 0x3 CONT_LLP Unspecified 0x4 RELOAD_LLP Unspecified 0x5 CNT_LLP Unspecified 0x6 LLP_RELOAD Unspecified 0x7 LLP_LLP Unspecified 0x8 CH6MULTIBLKTYPE The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsultant parameter. 24 27 read-only PROGRAMMABLE Unspecified 0x0 CONT_RELOAD Unspecified 0x1 RELOAD_CONT Unspecified 0x2 RELOAD_RELOAD Unspecified 0x3 CONT_LLP Unspecified 0x4 RELOAD_LLP Unspecified 0x5 CNT_LLP Unspecified 0x6 LLP_RELOAD Unspecified 0x7 LLP_LLP Unspecified 0x8 CH7MULTIBLKTYPE The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsultant parameter. 28 31 read-only PROGRAMMABLE Unspecified 0x0 CONT_RELOAD Unspecified 0x1 RELOAD_CONT Unspecified 0x2 RELOAD_RELOAD Unspecified 0x3 CONT_LLP Unspecified 0x4 RELOAD_LLP Unspecified 0x5 CNT_LLP Unspecified 0x6 LLP_RELOAD Unspecified 0x7 LLP_LLP Unspecified 0x8 DMACOMPPARAMS1L DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. 0x058 read-write 0x33333333 0x20 CHOMAXBLKSIZE The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsultant parameter. 0 3 read-only MAX_BLOCK_SIZE_3 Unspecified 0x0 MAX_BLOCK_SIZE_7 Unspecified 0x1 MAX_BLOCK_SIZE_15 Unspecified 0x2 MAX_BLOCK_SIZE_31 Unspecified 0x3 MAX_BLOCK_SIZE_63 Unspecified 0x4 MAX_BLOCK_SIZE_127 Unspecified 0x5 MAX_BLOCK_SIZE_255 Unspecified 0x6 MAX_BLOCK_SIZE_511 Unspecified 0x7 MAX_BLOCK_SIZE_1023 Unspecified 0x8 MAX_BLOCK_SIZE_2047 Unspecified 0x9 MAX_BLOCK_SIZE_4095 Unspecified 0xA CH1MAXBLKSIZE The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsultant parameter. 4 7 read-only MAX_BLOCK_SIZE_3 Unspecified 0x0 MAX_BLOCK_SIZE_7 Unspecified 0x1 MAX_BLOCK_SIZE_15 Unspecified 0x2 MAX_BLOCK_SIZE_31 Unspecified 0x3 MAX_BLOCK_SIZE_63 Unspecified 0x4 MAX_BLOCK_SIZE_127 Unspecified 0x5 MAX_BLOCK_SIZE_255 Unspecified 0x6 MAX_BLOCK_SIZE_511 Unspecified 0x7 MAX_BLOCK_SIZE_1023 Unspecified 0x8 MAX_BLOCK_SIZE_2047 Unspecified 0x9 MAX_BLOCK_SIZE_4095 Unspecified 0xA CH2MAXBLKSIZE The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsultant parameter. 8 11 read-only MAX_BLOCK_SIZE_3 Unspecified 0x0 MAX_BLOCK_SIZE_7 Unspecified 0x1 MAX_BLOCK_SIZE_15 Unspecified 0x2 MAX_BLOCK_SIZE_31 Unspecified 0x3 MAX_BLOCK_SIZE_63 Unspecified 0x4 MAX_BLOCK_SIZE_127 Unspecified 0x5 MAX_BLOCK_SIZE_255 Unspecified 0x6 MAX_BLOCK_SIZE_511 Unspecified 0x7 MAX_BLOCK_SIZE_1023 Unspecified 0x8 MAX_BLOCK_SIZE_2047 Unspecified 0x9 MAX_BLOCK_SIZE_4095 Unspecified 0xA CH3MAXBLKSIZE The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsultant parameter. 12 15 read-only MAX_BLOCK_SIZE_3 Unspecified 0x0 MAX_BLOCK_SIZE_7 Unspecified 0x1 MAX_BLOCK_SIZE_15 Unspecified 0x2 MAX_BLOCK_SIZE_31 Unspecified 0x3 MAX_BLOCK_SIZE_63 Unspecified 0x4 MAX_BLOCK_SIZE_127 Unspecified 0x5 MAX_BLOCK_SIZE_255 Unspecified 0x6 MAX_BLOCK_SIZE_511 Unspecified 0x7 MAX_BLOCK_SIZE_1023 Unspecified 0x8 MAX_BLOCK_SIZE_2047 Unspecified 0x9 MAX_BLOCK_SIZE_4095 Unspecified 0xA CH4MAXBLKSIZE The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsultant parameter. 16 19 read-only MAX_BLOCK_SIZE_3 Unspecified 0x0 MAX_BLOCK_SIZE_7 Unspecified 0x1 MAX_BLOCK_SIZE_15 Unspecified 0x2 MAX_BLOCK_SIZE_31 Unspecified 0x3 MAX_BLOCK_SIZE_63 Unspecified 0x4 MAX_BLOCK_SIZE_127 Unspecified 0x5 MAX_BLOCK_SIZE_255 Unspecified 0x6 MAX_BLOCK_SIZE_511 Unspecified 0x7 MAX_BLOCK_SIZE_1023 Unspecified 0x8 MAX_BLOCK_SIZE_2047 Unspecified 0x9 MAX_BLOCK_SIZE_4095 Unspecified 0xA CH5MAXBLKSIZE The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsultant parameter. 20 23 read-only MAX_BLOCK_SIZE_3 Unspecified 0x0 MAX_BLOCK_SIZE_7 Unspecified 0x1 MAX_BLOCK_SIZE_15 Unspecified 0x2 MAX_BLOCK_SIZE_31 Unspecified 0x3 MAX_BLOCK_SIZE_63 Unspecified 0x4 MAX_BLOCK_SIZE_127 Unspecified 0x5 MAX_BLOCK_SIZE_255 Unspecified 0x6 MAX_BLOCK_SIZE_511 Unspecified 0x7 MAX_BLOCK_SIZE_1023 Unspecified 0x8 MAX_BLOCK_SIZE_2047 Unspecified 0x9 MAX_BLOCK_SIZE_4095 Unspecified 0xA CH6MAXBLKSIZE The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsultant parameter. 24 27 read-only MAX_BLOCK_SIZE_3 Unspecified 0x0 MAX_BLOCK_SIZE_7 Unspecified 0x1 MAX_BLOCK_SIZE_15 Unspecified 0x2 MAX_BLOCK_SIZE_31 Unspecified 0x3 MAX_BLOCK_SIZE_63 Unspecified 0x4 MAX_BLOCK_SIZE_127 Unspecified 0x5 MAX_BLOCK_SIZE_255 Unspecified 0x6 MAX_BLOCK_SIZE_511 Unspecified 0x7 MAX_BLOCK_SIZE_1023 Unspecified 0x8 MAX_BLOCK_SIZE_2047 Unspecified 0x9 MAX_BLOCK_SIZE_4095 Unspecified 0xA CH7MAXBLKSIZE The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsultant parameter. 28 31 read-only MAX_BLOCK_SIZE_3 Unspecified 0x0 MAX_BLOCK_SIZE_7 Unspecified 0x1 MAX_BLOCK_SIZE_15 Unspecified 0x2 MAX_BLOCK_SIZE_31 Unspecified 0x3 MAX_BLOCK_SIZE_63 Unspecified 0x4 MAX_BLOCK_SIZE_127 Unspecified 0x5 MAX_BLOCK_SIZE_255 Unspecified 0x6 MAX_BLOCK_SIZE_511 Unspecified 0x7 MAX_BLOCK_SIZE_1023 Unspecified 0x8 MAX_BLOCK_SIZE_2047 Unspecified 0x9 MAX_BLOCK_SIZE_4095 Unspecified 0xA DMACOMPPARAMS1H DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. 0x05C read-write 0x3120090C 0x20 BIGENDIAN The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant parameter. 0 0 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 INTRIO The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter. 1 2 read-only ALL_INT Unspecified 0x0 TYPE_INT Unspecified 0x1 COMBINED_INT Unspecified 0x2 MAXABRST The value of this register is derived from the DMAH_MABRST coreConsultant parameter. 3 3 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 RSVDDMACOMPPARAMS1 Reserved field- read-only 4 7 read-only NUMCHANNELS The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant parameter. 8 10 read-only NUM_CHANNEL_1 Unspecified 0x0 NUM_CHANNEL_2 Unspecified 0x1 NUM_CHANNEL_3 Unspecified 0x2 NUM_CHANNEL_4 Unspecified 0x3 NUM_CHANNEL_5 Unspecified 0x4 NUM_CHANNEL_6 Unspecified 0x5 NUM_CHANNEL_7 Unspecified 0x6 NUM_CHANNEL_8 Unspecified 0x7 NUMMASTERINT The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant parameter. 11 12 read-only NUM_MST_INTERFACE_1 Unspecified 0x0 NUM_MST_INTERFACE_2 Unspecified 0x1 NUM_MST_INTERFACE_3 Unspecified 0x2 NUM_MST_INTERFACE_4 Unspecified 0x3 SHDATAWIDTH The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant parameter. 13 14 read-only DATA_BUS_WIDTH_32 Unspecified 0x0 DATA_BUS_WIDTH_64 Unspecified 0x1 DATA_BUS_WIDTH_128 Unspecified 0x2 DATA_BUS_WIDTH_256 Unspecified 0x3 M4HDATAWIDTH The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant parameter. 15 16 read-only DATA_BUS_WIDTH_32 Unspecified 0x0 DATA_BUS_WIDTH_64 Unspecified 0x1 DATA_BUS_WIDTH_128 Unspecified 0x2 DATA_BUS_WIDTH_256 Unspecified 0x3 M3HDATAWIDTH The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant parameter. 17 18 read-only DATA_BUS_WIDTH_32 Unspecified 0x0 DATA_BUS_WIDTH_64 Unspecified 0x1 DATA_BUS_WIDTH_128 Unspecified 0x2 DATA_BUS_WIDTH_256 Unspecified 0x3 M2HDATAWIDTH The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant parameter. 19 20 read-only DATA_BUS_WIDTH_32 Unspecified 0x0 DATA_BUS_WIDTH_64 Unspecified 0x1 DATA_BUS_WIDTH_128 Unspecified 0x2 DATA_BUS_WIDTH_256 Unspecified 0x3 M1HDATAWIDTH The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant parameter. 21 22 read-only DATA_BUS_WIDTH_32 Unspecified 0x0 DATA_BUS_WIDTH_64 Unspecified 0x1 DATA_BUS_WIDTH_128 Unspecified 0x2 DATA_BUS_WIDTH_256 Unspecified 0x3 NUMHSINT The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant parameter. 23 27 read-only HS_INTERFACE_0 Unspecified 0x00 HS_INTERFACE_1 Unspecified 0x01 HS_INTERFACE_2 Unspecified 0x02 HS_INTERFACE_3 Unspecified 0x03 HS_INTERFACE_4 Unspecified 0x04 HS_INTERFACE_5 Unspecified 0x05 HS_INTERFACE_6 Unspecified 0x06 HS_INTERFACE_7 Unspecified 0x07 HS_INTERFACE_8 Unspecified 0x08 HS_INTERFACE_9 Unspecified 0x09 HS_INTERFACE_a Unspecified 0x0A HS_INTERFACE_b Unspecified 0x0B HS_INTERFACE_c Unspecified 0x0C HS_INTERFACE_d Unspecified 0x0D HS_INTERFACE_e Unspecified 0x0E HS_INTERFACE_f Unspecified 0x0F HS_INTERFACE_10 Unspecified 0x10 ADDENCODEDPARAMS The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant parameter. 28 28 read-only FALSE Unspecified 0x0 TRUE Unspecified 0x1 STATICENDIANSELECT The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsultant parameter. 29 29 read-only DMACOMPSID0 This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the component type. 0x060 read-write 0x44571110 0x20 DMACOMPTYPE DMA Component Type Number = `h44571110. 0 31 read-only DMACOMPSID1 This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the version of the packaged component. 0x064 read-write 0x3232322A 0x20 DMACOMPVERSION DMA Component Version. 0 31 read-only GLOBAL_I3CCORE121_NS I3CCORE 1 0x2FBE1000 GLOBAL_DMU120_NS DMU 0x2FBEF800 DMU 0 0x1000 registers DMU 0x20 DMUCR DMU Core Release 0x3C0 read-only 0x00000000 0x20 REL Core Release 1 1 STEP Step of Core Release 2 2 SUBSTEP Sub-step of Core Release 3 3 YEAR Time Stamp Year 4 4 MON Time Stamp Month 6 6 DAY Time Stamp Day 8 8 DMUI DMU Internals 0x3C4 read-write 0x00070000 0x20 TXR TX Service Request line of DMU 0 0 NotRequested No TX DMA service requested 0x0 Requested TX DMA Service requested 0x1 RX0R RX0 Service Request line of DMU 1 1 NotRequested No RX0 DMA service requested 0x0 Requested RX0 DMA Service requested 0x1 RX1R RX1 Service Request line of DMU 2 2 NotRequested No RX1 DMA service requested 0x0 Requested RX1 DMA Service requested 0x1 TXER TX Event Service Request line of DMU 3 3 NotRequested No TX Event DMA service requested 0x0 Requested TX Event DMA Service requested 0x1 TFQPIP TX FIFO/Queue Put Index Previous 8 12 ENA DMU is enabled 15 15 Disabled DMU is disabled 0x0 Enabled DMU is enabled and can process DMA data 0x1 DEHS Detect Element Handler State 16 18 DTX Detect DMU Element Service 20 20 Disabled Queueing of DMU Element does not activate interrupt flag 0x0 Enabled Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS 0x1 DRX0 Detect DMU Element Service 21 21 Disabled Queueing of DMU Element does not activate interrupt flag 0x0 Enabled Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS 0x1 DRX1 Detect DMU Element Service 22 22 Disabled Queueing of DMU Element does not activate interrupt flag 0x0 Enabled Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS 0x1 DTXE Detect DMU Element Service 23 23 Disabled Queueing of DMU Element does not activate interrupt flag 0x0 Enabled Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS 0x1 EHS Element Handler State 24 26 wait4cce wait for bit MCAN:CCCR.CCE getting zero 0x0 wait4sa wait for Start Address 0x1 wait4ta wait for Trigger Address 0x2 transfer wait for transfer of Element word 0x3 ack2mcan acknowledge to MCAN 0x4 recovery exception recovery 0x5 TX Actual DMU Element Service 28 28 NotServed DMU Virtual Buffer is currently not served 0x0 Served DMU Virtual Buffer is currently served 0x1 RX0 Actual DMU Element Service 29 29 NotServed DMU Virtual Buffer is currently not served 0x0 Served DMU Virtual Buffer is currently served 0x1 RX1 Actual DMU Element Service 30 30 NotServed DMU Virtual Buffer is currently not served 0x0 Served DMU Virtual Buffer is currently served 0x1 TXE Actual DMU Element Service 31 31 NotServed DMU Virtual Buffer is currently not served 0x0 Served DMU Virtual Buffer is currently served 0x1 DMUQC DMU Queueing Counter 0x3C8 read-write 0x00000000 0x20 TXEEC TX Element Enqueueing Counter 0 7 RX0EDC RX0 Element Dequeueing Counter 8 15 RX1EDC RX1 Element Dequeueing Counter 16 23 TXEEDC TX Event Element Dequeueing Counter 24 31 DMUIR DMU Interrupt Register 0x3CC read-write 0x00000000 0x20 TXENSA TX Element Not Start Address 0 0 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal write access 0x0 Generated Write to TX Element begins without using start address, exception recovery started. 0x1 TXEIE TX Element Illegal Enqueueing 1 1 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal enqueueing 0x0 Generated Start of enqueueing without request detected, exception recovery started. 0x1 TXEIAS TX Element Illegal Access Sequence 2 2 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal addressing sequence detected 0x0 Generated Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. 0x1 TXEIDLC TX Element Illegal DLC 3 3 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal DLC detected 0x0 Generated DLC exceeds Tx Buffer element size of MCAN, exception recovery started. 0x1 TXEWATA TX Element Write After Trigger Address 4 4 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No write after Trigger Address 0x0 Generated Write after Trigger address detected 0x1 TXEIR TX Element Illegal Read 5 5 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No read access 0x0 Generated Illegal read access to DMU TX Element section detected, exception recovery started. 0x1 TXEE A successful enqueueing of a Tx message with the DMU TX Element section sets this flag. 6 6 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Tx message enqueued 0x0 Generated Tx message successfully enqueued 0x1 RX0ENSA RX0 Element Not Start Address 7 7 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal read access 0x0 Generated Read from RX0 Element begins without using start address, exception recovery started. 0x1 RX0EID RX0 Element Illegal Dequeueing 8 8 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal dequeueing 0x0 Generated Start of dequeueing without request detected, exception recovery started, 0x1 RX0EIAS RX0 Element Illegal Access Sequence 9 9 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal addressing sequence detected 0x0 Generated Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. 0x1 RX0EIW RX0 Element Illegal Write 10 10 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No write access detected 0x0 Generated Illegal write access to DMU RX0 Element detected, exception recovery started. 0x1 RX0ED RX0 Element Dequeued 11 11 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Rx message dequeued 0x0 Generated Rx message successfully dequeued 0x1 RX0EIO RX0 Element Illegal Overwrite by timestamp 12 12 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal overwrite detected 0x0 Generated DMU has internally overwritten the last element word of a SYNC message 0x1 BEU Bus Error Uncorrected 15 15 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No read slave error detected when reading from Message RAM 0x0 Generated Read slave error detected 0x1 RX1ENSA RX1 Element Not Start Address 16 16 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal read access 0x0 Generated Read from RX1 Element begins without using start address, exception recovery started. 0x1 RX1EID RX1 Element Illegal Dequeueing 17 17 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal dequeueing 0x0 Generated Start of dequeueing without request detected, exception recovery started, 0x1 RX1EIAS RX0 Element Illegal Access Sequence 18 18 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal addressing sequence detected 0x0 Generated Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. 0x1 RX1EIW RX1 Element Illegal Write 19 19 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No write access detected 0x0 Generated Illegal write access to DMU RX1 Element detected, exception recovery started. 0x1 RX1ED RX0 Element Dequeued 20 20 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Rx message dequeued 0x0 Generated Rx message successfully dequeued 0x1 RX1EIO RX1 Element Illegal Overwrite by timestamp 21 21 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal overwrite detected 0x0 Generated DMU has internally overwritten the last element word of a SYNC message 0x1 TXEENSA TX Event Element Not Start Address 24 24 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal read access 0x0 Generated Read from TX Event Element begins without using start address, exception recovery started. 0x1 TXEEID TX Event Element Illegal Dequeueing 25 25 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal dequeueing 0x0 Generated Start of dequeueing without request detected, exception recovery started. 0x1 TXEEIAS TX Event Element Illegal Access Sequence 26 26 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No illegal addressing sequence detected 0x0 Generated Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. 0x1 TXEEIW TX Event Element Illegal Write 27 27 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No write access detected 0x0 Generated Illegal write access to DMU TX Event Element detected, exception recovery started. 0x1 TXEED TX Event Element Dequeued 28 28 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No TX Event Element dequeued 0x0 Generated TX Event Element successfully dequeued 0x1 DT Debug Trigger 29 29 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Debug point not reached 0x0 Generated Debug point reached 0x1 IAC Illegal Access while in Configuration mode 30 30 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Illegal Access while CCE mode 0x0 Generated Illegal Access while CCE mode 0x1 DMUIE DMU Interrupt Enable 0x3D0 read-write 0x00000000 0x20 TXENSAE TX Element Not Start Address Enable 0 0 Disabled Flag does not activate the interrupt line DMU 0x0 Enabled the interrupt line DMU will be activated 0x1 DMUC DMU Configuration 0x3D4 read-write 0x00000000 0x20 TTS Transfer Timestamp 0 0 Disabled No timestamp will be transferred via DMU Virtual Buffer 0x0 Enabled Timestamp of message will be transferred from TSU via DMU Virtual Buffer 0x1 GLOBAL_MCAN120_NS MCAN 0x2FBEF800 GLOBAL_DMU120_NS MCAN 0 0x1000 registers MCAN 0x20 ENDN Endian Register 0x004 read-only 0x00000000 0x20 ETV Endianness Test Value 0 31 DBTP Data Bit Timing and Prescaler Register 0x00C read-write 0x00000000 0x20 DSJW Data (Re)Synchronization Jump Width 0 3 DTSEG2 Data time segment after sample point 4 7 DTSEG1 Data time segment before sample point 8 12 DBRP Data Bit Rate Prescaler 16 20 TDC Transmitter Delay Compensation 23 23 Disabled Unspecified 0x0 Enabled Unspecified 0x1 TEST Test Register 0x010 read-write 0x00000000 0x20 LBCK Loop Back Mode 4 4 Disabled Loop Back Mode is disabled 0x0 Enabled Loop Back Mode is enabled 0x1 TX Control of Transmit Pin 5 6 CanCore controlled by the CAN Core, updated at the end of the CAN bit time 0x0 Monitored Sample Point can be monitored at pin m_can_tx 0x1 Dominant Dominant (0) level at pin m_can_tx 0x2 Recessive Recessive (1) at pin m_can_tx 0x3 RX Receive Pin 7 7 Dominant The CAN bus is dominant (m_can_rx = 0) 0x0 Recessive The CAN bus is recessive (m_can_rx = '1') 0x1 TXBNP Tx Buffer Number Prepared 8 12 PVAL Prepared Valid 13 13 NotValid Value of TXBNP not valid 0x0 Valid Value of TXBNP valid 0x1 TXBNS Tx Buffer Number Started 16 20 SVAL Started Valid 21 21 NotValid Value of TXBNP not valid 0x0 Valid Value of TXBNP valid 0x1 RWD RAM Watchdog 0x014 read-write 0x00000000 0x20 WDC Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled. 0 7 WDV Actual Message RAM Watchdog Counter Value. 8 15 CCCR CC Control Register 0x018 read-write 0x00000000 0x20 INIT Initialization 0 0 Normal Normal Operation 0x0 Initialization Initialization is started 0x1 CCE Configuration Change Enable 1 1 Disabled The CPU has no write access to the protected configuration registers 0x0 Enabled The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') 0x1 ASM Restricted Operation Mode 2 2 Disabled Normal CAN operation 0x0 Enabled Restricted Operation Mode active 0x1 CSA Clock Stop Acknowledge 3 3 Disabled No clock stop acknowledged 0x0 Enabled MCAN may be set in power down by stopping m_can_hclk and m_can_cclk 0x1 CSR Clock Stop Request 4 4 Disabled No clock stop is requested 0x0 Enabled Clock stop requested. 0x1 MON Bus Monitoring Mode 5 5 Disabled Bus Monitoring Mode is disabled 0x0 Enabled Bus Monitoring Mode is enabled 0x1 DAR Disable Automatic Retransmission 6 6 Enabled Automatic retransmission of messages not transmitted successfully enabled 0x0 Disabled Automatic retransmission disabled 0x1 TEST Test Mode Enable 7 7 Disabled Normal operation, register TEST holds reset values 0x0 Enabled Test Mode, write access to register TEST enabled 0x1 FDOE FD Operation Enable 8 8 Disabled FD operation disabled 0x0 Enabled FD operation enabled 0x1 BRSE Bit Rate Switch Enable 9 9 Disabled Bit rate switching for transmissions disabled 0x0 Enabled Bit rate switching for transmissions enabled 0x1 WMM Wide Message Marker 11 11 Disabled 8-bit Message Marker used 0x0 Enabled 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO 0x1 PXHD Protocol Exception Handling Disable 12 12 Enabled Protocol exception handling enabled 0x0 Disabled Protocol exception handling disabled 0x1 EFBI Edge Filtering during Bus Integration 13 13 Disabled Edge filtering disabled 0x0 Enabled Two consecutive dominant tq required to detect an edge for hard synchronization 0x1 TXP Transmit Pause 14 14 Disabled Transmit pause disabled 0x0 Enabled Transmit pause enabled 0x1 NISO Non ISO Operation 15 15 Disabled CAN FD frame format according to ISO 11898-1:2015 0x0 Enabled CAN FD frame format according to Bosch CAN FD Specification V1.0 0x1 NBTP Nominal Bit Timing and Prescaler Register 0x01C read-write 0x00000000 0x20 NTSEG2 Nominal Time segment after sample point 0 6 NTSEG1 Nominal Time segment before sample point 8 15 NBRP Nominal Bit Rate Prescaler 16 24 NSJW Nominal (Re)Synchronization Jump Width 25 31 TSCC Timestamp Counter Configuration 0x020 read-write 0x00000000 0x20 TSS Timestamp Select 0 1 Zero Timestamp counter value always 0x0000 0x0 Increment Timestamp counter value incremented according to TCP 0x1 External External timestamp counter value used 0x2 Zero0 Same as Zero 0x3 TCP Timestamp Counter Prescaler 16 19 TSCV Timestamp Counter Value 0x024 read-write 0x00000000 0x20 TSC Timestamp Counter 0 15 TOCC Timeout Counter Configuration 0x028 read-write 0x00000000 0x20 ETOC Enable Timeout Counter 0 0 Disabled Timeout Counter disabled 0x0 Enabled Timeout Counter enabled 0x1 TOS Timeout Select 1 2 Continuous Continuous operation 0x0 TxEvent Timeout controlled by Tx Event FIFO 0x1 RxFifo0 Timeout controlled by Rx FIFO 0 0x2 RxFifo1 Timeout controlled by Rx FIFO 1 0x3 TOP Timeout Period 16 31 TOCV Timeout Counter Value 0x02C read-write 0x00000000 0x20 TOC Timeout Counter 0 15 ECR Error Counter Register 0x040 read-write 0x00000000 0x20 TEC Transmit Error Counter 0 7 REC Receive Error Counter 8 14 RP Receive Error Passive 15 15 Below The Receive Error Counter is below the error passive level of 128 0x0 Reached The Receive Error Counter has reached the error passive level of 128 0x1 CEL CAN Error Logging 16 23 PSR Protocol Status Register 0x044 read-write 0x00000000 0x20 LEC Last Error Code 0 2 NoError No error occurred since LEC has been reset by successful reception or transmission. 0x0 StuffError More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 FormError A fixed format part of a received frame has the wrong format. 0x2 AckError The message transmitted by the MCAN was not acknowledged by another node. 0x3 Bit1Error During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. 0x4 Bit0Error During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 0x5 CRCError The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 0x6 NoChange Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. 0x7 ACT Activity 3 4 Synchronizing Node is synchronizing on CAN communication 0x0 Idle Node is neither receiver nor tr ansmitter 0x1 Receiver Node is operating as receiver 0x2 Transmitter Node is operating as transmitter 0x3 EP Error Passive 5 5 Active The MCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 0x0 Passive The MCAN is in the Error_Passive state 0x1 EW Warning Status 6 6 Below Both error counters are below the Error_Warning limit of 96 0x0 Reached At least one of error counter has reached the Error_Warning limit of 96 0x1 BO Bus_Off Status 7 7 On The MCAN is not Bus_Off 0x0 Off The MCAN is in Bus_Off state 0x1 DLEC Data Phase Last Error Code 8 10 RESI ESI flag of last received CAN FD Message 11 11 NotReceived Last received CAN FD message did not ha ve its ESI flag set 0x0 Received Last received CAN FD message had its ESI flag set 0x1 RBRS BRS flag of last received CAN FD Message 12 12 NotReceived Last received CAN FD message did not ha ve its BRS flag set 0x0 Received Last received CAN FD message had its BRS flag set 0x1 RFDF Received a CAN FD Message 13 13 NotReceived Since this bit was reset by the CPU, no CAN FD message has been received 0x0 Received Message in CAN FD format with FDF flag set has been received 0x1 PXE Protocol Exception Event 14 14 NotTriggered No protocol exception event occurred since last read access 0x0 Triggered Protocol exception event occurred 0x1 TDCV Transmitter Delay Compensation Value 16 22 TDCR Transmitter Delay Compensation Register 0x048 read-write 0x00000000 0x20 TDCF Transmitter Delay Compensation Filter Window Length 0 6 TDCO Transmitter Delay Compensation SSP Offset 8 14 IR Interrupt Register 0x050 read-write 0x00000000 0x20 RF0N Rx FIFO 0 New Message 0 0 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No new message written to Rx FIFO 0 0x0 Generated New message written to Rx FIFO 0 0x1 RF0W Rx FIFO 0 Watermark Reached 1 1 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Rx FIFO 0 fill level below watermark 0x0 Generated Rx FIFO 0 fill level reached watermark 0x1 RF0F Rx FIFO 0 Full 2 2 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Rx FIFO 0 not full 0x0 Generated Rx FIFO 0 full 0x1 RF0L Rx FIFO 0 Message Lost 3 3 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Rx FIFO 0 message lost 0x0 Generated Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero 0x1 RF1N Rx FIFO 1 New Message 4 4 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No new message written to Rx FIFO 1 0x0 Generated New message written to Rx FIFO 1 0x1 RF1W Rx FIFO 1 Watermark Reached 5 5 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Rx FIFO 1 fill level below watermark 0x0 Generated Rx FIFO 1 fill level reached watermark 0x1 RF1F Rx FIFO 1 Full 6 6 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Rx FIFO 1 not full 0x0 Generated Rx FIFO 1 full 0x1 RF1L Rx FIFO 1 Message Lost 7 7 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Rx FIFO 1 message lost 0x0 Generated Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero 0x1 HPM High Priority Message 8 8 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No high priority message received 0x0 Generated High priority message received 0x1 TC Transmission Completed 9 9 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No transmission completed 0x0 Generated Transmission completed 0x1 TCF Transmission Cancellation Finished 10 10 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No transmission cancellation finished 0x0 Generated Transmission cancellation finished 0x1 TFE Tx FIFO Empty 11 11 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Tx FIFO non-empty 0x0 Generated Tx FIFO empty 0x1 TEFN Tx Event FIFO New Entry 12 12 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Tx Event FIFO unchanged 0x0 Generated Tx Handler wrote Tx Event FIFO element 0x1 TEFW Tx Event FIFO Watermark Reached 13 13 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Tx Event FIFO fill level below watermark 0x0 Generated Tx Event FIFO fill level reached watermark 0x1 TEFF Tx Event FIFO Full 14 14 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Tx Event FIFO not full 0x0 Generated Tx Event FIFO full 0x1 TEFL Tx Event FIFO Element Lost 15 15 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Tx Event FIFO element lost 0x0 Generated Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero 0x1 TSW Timestamp Wraparound 16 16 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No timestamp counter wrap-around 0x0 Generated Timestamp counter wrapped around 0x1 MRAF Message RAM Access Failure 17 17 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Message RAM access failure occurred 0x0 Generated Message RAM access failure occurred 0x1 TOO Timeout Occurred 18 18 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No timeout 0x0 Generated Timeout reached 0x1 DRX Message stored to Dedicated Rx Buffer 19 19 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Rx Buffer updated 0x0 Generated At least one received message stored into an Rx Buff er 0x1 BEU Bus Error Uncorrected 21 21 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No read slave error detected when reading from Message RAM 0x0 Generated Read slave error detected 0x1 ELO Error Logging Overflow 22 22 Clear Write '1' to clear interrupt flag 0x1 NotGenerated CAN Error Logging Counter did not overflow 0x0 Generated Overflow of CAN Error Logging Counter occurred 0x1 EP Error Passive 23 23 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Error_Passive status unchanged 0x0 Generated Error_Passive status changed 0x1 EW Warning Status 24 24 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Error_Warning status unchanged 0x0 Generated Error_Warning status changed 0x1 BO Bus_Off Status 25 25 Clear Write '1' to clear interrupt flag 0x1 NotGenerated Bus_Off status unchanged 0x0 Generated Bus_Off status changed 0x1 WDI Watchdog Interrupt 26 26 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No Message RAM Watchdog event occurred 0x0 Generated Message RAM Watchdog event due to missing READY 0x1 PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 27 27 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No protocol error in arbitration phase 0x0 Generated Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) 0x1 PED Protocol Error in Data Phase (Data Bit Time is used) 28 28 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No protocol error in data phase 0x0 Generated Protocol error in data phase detected (PSR.DLEC ≠ 0,7) 0x1 ARA Access to Reserved Address 29 29 Clear Write '1' to clear interrupt flag 0x1 NotGenerated No access to reserved address occurred 0x0 Generated Access to reserved address occurred 0x1 IE Interrupt Enable 0x054 read-write 0x00000000 0x20 RF0NE Rx FIFO 0 New Message Interrupt Enable 0 0 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 RF0FE Rx FIFO 0 Full Interrupt Enable 2 2 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 RF0LE Rx FIFO 0 Message Lost Interrupt Enable 3 3 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 RF1NE Rx FIFO 1 New Message Interrupt Enable 4 4 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable 5 5 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 RF1FE Rx FIFO 1 Full Interrupt Enable 6 6 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 RF1LE Rx FIFO 1 Message Lost Interrupt Enable 7 7 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 HPME High Priority Message Interrupt Enable 8 8 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TCE Transmission Completed Interrupt Enable 9 9 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TCFE Transmission Cancellation Finished Interrupt Enable 10 10 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TFEE Tx FIFO Empty Interrupt Enable 11 11 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TEFNE Tx Event FIFO New Entry Interrupt Enable 12 12 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 13 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TEFFE Tx Event FIFO Full Interrupt Enable 14 14 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TEFLE Tx Event FIFO Event Lost Interrupt Enable 15 15 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TSWE Timestamp Wraparound Interrupt Enable 16 16 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 MRAFE Message RAM Access Failure Interrupt Enable 17 17 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 TOOE Timeout Occurred Interrupt Enable 18 18 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 DRXE Message stored to Dedicated Rx Buffer Interrupt Enable 19 19 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 BEUE Bus Error Uncorrected Interrupt Enable 21 21 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 ELOE Error Logging Overflow Interrupt Enable 22 22 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 EPE Error Passive Interrupt Enable 23 23 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 EWE Warning Status Interrupt Enable 24 24 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 BOE Bus_Off Status Interrupt Enable 25 25 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 WDIE Watchdog Interrupt Enable 26 26 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 PEAE Protocol Error in Arbitration Phase Enable 27 27 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 PEDE Protocol Error in Data Phase Enable 28 28 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 ARAE Access to Reserved Address Enable 29 29 Disable Interrupt disabled. 0x0 Enable Interrupt enabled. 0x1 ILS Interrupt Line Select 0x058 read-write 0x00000000 0x20 RF0NL Rx FIFO 0 New Message Interrupt Line 0 0 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 RF0FL Rx FIFO 0 Full Interrupt Line 2 2 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 3 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 RF1NL Rx FIFO 1 New Message Interrupt Line 4 4 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 5 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 RF1FL Rx FIFO 1 Full Interrupt Line 6 6 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 7 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 HPML High Priority Message Interrupt Line 8 8 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TCL Transmission Completed Interrupt Line 9 9 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TCFL Transmission Cancellation Finished Interrupt Line 10 10 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TFEL Tx FIFO Empty Interrupt Line 11 11 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 12 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 13 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TEFFL Tx Event FIFO Full Interrupt Line 14 14 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TEFLL Tx Event FIFO Event Lost Interrupt Line 15 15 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TSWL Timestamp Wraparound Interrupt Line 16 16 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 MRAFL Message RAM Access Failure Interrupt Line 17 17 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 TOOL Timeout Occurred Interrupt Line 18 18 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 19 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 BEUL Bus Error Uncorrected Interrupt Line 21 21 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 ELOL Error Logging Overflow Interrupt Line 22 22 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 EPL Error Passive Interrupt Line 23 23 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 EWL Warning Status Interrupt Line 24 24 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 BOL Bus_Off Status Interrupt Line 25 25 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 WDIL Watchdog Interrupt Line 26 26 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 PEAL Protocol Error in Arbitration Phase Line 27 27 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 PEDL Protocol Error in Data Phase Line 28 28 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 ARAL Access to Reserved Address Line 29 29 Assigned0 Interrupt assigned to interrupt line CORE0. 0x0 Assigned1 Interrupt assigned to interrupt line CORE1. 0x1 ILE Interrupt Line Enable 0x05C read-write 0x00000000 0x20 EINT0 Enable Interrupt Line 0 0 0 Disable Interrupt line CORE0 disabled. 0x0 Enable Interrupt line CORE0 enabled. 0x1 EINT1 Enable Interrupt Line 1 1 1 Disable Interrupt line CORE1 disabled. 0x0 Enable Interrupt line CORE1 enabled. 0x1 GFC Global Filter Configuration 0x080 read-write 0x00000000 0x20 RRFE Reject Remote Frames Extended 0 0 Filter Filter remote frames with 29-bit extended IDs. 0x0 Reject Reject all remote frames with 29-bit extended IDs. 0x1 RRFS Reject Remote Frames Standard 1 1 Filter Filter remote frames with 11-bit standard IDs. 0x0 Reject Reject all remote frames with 11-bit standard IDs. 0x1 ANFE Accept Non-matching Frames Extended 2 3 Accept0 Accept in Rx FIFO 0. 0x0 Accept1 Accept in Rx FIFO 1. 0x1 Reject0 Reject in both Rx FIFOs. 0x2 Reject1 Reject in both Rx FIFOs. 0x3 ANFS 4 5 Accept0 Accept in Rx FIFO 0. 0x0 Accept1 Accept in Rx FIFO 1. 0x1 Reject0 Reject in both Rx FIFOs. 0x2 Reject1 Reject in both Rx FIFOs. 0x3 SIDFC Standard ID Filter Configuration 0x084 read-write 0x00000000 0x20 FLSSA Filter List Standard Start Address 2 15 LSS List Size Standard 16 23 XIDFC Extended ID Filter Configuration 0x088 read-write 0x00000000 0x20 FLESA Filter List Extended Start Address 2 15 LSE List Size Extended 16 22 XIDAM Extended ID AND Mask 0x090 read-write 0x00000000 0x20 EIDM Extended ID Mask 0 28 HPMS High Priority Message Status 0x094 read-only 0x00000000 0x20 BIDX Buffer Index 0 5 MSI Message Storage Indicator 6 7 NotSelected No FIFO selected. 0x0 Lost FIFO message lost. 0x1 Stored0 Message stored in FIFO 0. 0x2 Stored1 Message stored in FIFO 1. 0x3 FIDX Filter Index 8 14 FLST Filter List 15 15 Standard Standard Filter List. 0x0 Extended Extended Filter List. 0x1 NDAT1 New Data 1 0x098 read-write 0x00000000 0x20 ND New Data 0 31 NotUpdated Rx Buffer not updated. 0x00000000 Updated Rx Buffer updated from new message. 0x00000001 NDAT2 New Data 2 0x09C read-write 0x00000000 0x20 ND New Data 0 31 NotUpdated Rx Buffer not updated. 0x00000000 Updated Rx Buffer updated from new message. 0x00000001 RXF0C Rx FIFO 0 Configuration 0x0A0 read-write 0x00000000 0x20 F0SA Rx FIFO 0 Start Address 2 15 F0S Rx FIFO 0 Size 16 22 F0WM Rx FIFO 0 Watermark 24 30 F0OM FIFO 0 Operation Mode 31 31 Blocking FIFO 0 blocking mode. 0x0 Overwrite FIFO 0 overwrite mode. 0x1 RXF0S Rx FIFO 0 Status 0x0A4 read-only 0x00000000 0x20 F0FL Rx FIFO 0 Fill Leve 0 6 F0GI Rx FIFO 0 Get Index 8 13 F0PI Rx FIFO 0 Put Index 16 21 F0F Rx FIFO 0 Full 24 24 NotFull Rx FIFO 0 not full. 0x0 Full Rx FIFO 0 full. 0x1 RF0L Rx FIFO 0 Message Lost 25 25 NotLost No Rx FIFO 0 message lost. 0x0 Lost Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. 0x1 RXF0A Rx FIFO 0 Acknowledge 0x0A8 read-write 0x00000000 0x20 F0AI Rx FIFO 0 Acknowledge Index 0 5 RXBC Rx Buffer Configuration 0x0AC read-write 0x00000000 0x20 RBSA Rx Buffer Start Address 2 15 RXF1C Rx FIFO 1 Configuration 0x0B0 read-write 0x00000000 0x20 F1SA Rx FIFO 1 Start Address 2 15 F1S Rx FIFO 1 Size 16 22 F1WM Rx FIFO 1 Watermark 24 30 F1OM FIFO 1 Operation Mode 31 31 BlockingMode FIFO 1 blocking mode 0x0 OwerwriteMode FIFO 1 overwrite mode 0x1 RXF1S Rx FIFO 1 Status 0x0B4 read-only 0x00000000 0x20 F1FL Rx FIFO 1 Fill Level 0 6 F1GI Rx FIFO 1 Get Index 8 13 F1PI Rx FIFO 1 Put Index 16 21 F1F Rx FIFO 1 Full 24 24 NotFull Rx FIFO 1 not full 0x0 Full Rx FIFO 1 full 0x1 RF1L Rx FIFO 1 Message Lost 25 25 NoMessageLost No Rx FIFO 1 message lost 0x0 MessageLost Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero 0x1 DMS Debug Message Status 30 31 Idle Idle state, wait for reception of debug messages, DMA request is cleared 0x0 ReceivedMesA Debug message A received 0x1 ReceivedMesAB Debug messages A, B received 0x2 ReceivedMesABC Debug messages A, B, C received, DMA request is set 0x3 RXF1A Rx FIFO 1 Acknowledge 0x0B8 read-write 0x00000000 0x20 F1AI Rx FIFO 1 Acknowledge Index 0 5 RXESC Rx Buffer / FIFO Element Size Configuration 0x0BC read-write 0x00000000 0x20 F0DS Rx FIFO 0 Data Field Size 0 2 DataField8B 8 byte data field 0x0 DataField12B 12 byte data field 0x1 DataField16B 16 byte data field 0x2 DataField20B 20 byte data field 0x3 DataField24B 24 byte data field 0x4 DataField32B 32 byte data field 0x5 DataField48B 48 byte data field 0x6 DataField64B 64 byte data field 0x7 F1DS Rx FIFO 1 Data Field Size 4 6 DataField8B 8 byte data field 0x0 DataField12B 12 byte data field 0x1 DataField16B 16 byte data field 0x2 DataField20B 20 byte data field 0x3 DataField24B 24 byte data field 0x4 DataField32B 32 byte data field 0x5 DataField48B 48 byte data field 0x6 DataField64B 64 byte data field 0x7 RBDS Rx Buffer Data Field Size 8 10 DataField8B 8 byte data field 0x0 DataField12B 12 byte data field 0x1 DataField16B 16 byte data field 0x2 DataField20B 20 byte data field 0x3 DataField24B 24 byte data field 0x4 DataField32B 32 byte data field 0x5 DataField48B 48 byte data field 0x6 DataField64B 64 byte data field 0x7 TXBC Tx Buffer Configuration 0x0C0 read-write 0x00000000 0x20 TBSA Tx Buffers Start Address 2 15 NDTB Number of Dedicated Transmit Buffers 16 21 TFQS Transmit FIFO/Queue Size 24 29 TFQM Tx FIFO/Queue Mode 30 30 TxFIFO Tx FIFO operation 0x0 TxQueue Tx Queue operation 0x1 TXFQS Tx FIFO/Queue Status 0x0C4 read-only 0x00000000 0x20 TFFL Tx FIFO Free Level 0 5 TFGI Tx FIFO Get Index 8 12 TFQPI Tx FIFO/Queue Put Index 16 20 TFQF Tx FIFO/Queue Full 21 21 NotFull Tx FIFO/Queue not full 0x0 Full Tx FIFO/Queue full 0x1 TXESC Tx Buffer Element Size Configuration 0x0C8 read-write 0x00000000 0x20 TBDS Tx Buffer Data Field Size 0 2 DataField8B 8 byte data field 0x0 DataField12B 12 byte data field 0x1 DataField16B 16 byte data field 0x2 DataField20B 20 byte data field 0x3 DataField24B 24 byte data field 0x4 DataField32B 32 byte data field 0x5 DataField48B 48 byte data field 0x6 DataField64B 64 byte data field 0x7 TXBRP Tx Buffer Request Pending 0x0CC read-only 0x00000000 0x20 TRP Transmission Request Pending 0 31 NoRequest No transmission request pending 0x00000000 Request Transmission request pending 0x00000001 TXBAR Tx Buffer Add Request 0x0D0 read-write 0x00000000 0x20 AR Add Request 0 31 NoRequest No transmission request added 0x00000000 Request Transmission requested added 0x00000001 TXBCR Tx Buffer Cancellation Request 0x0D4 read-write 0x00000000 0x20 CR Cancellation Request 0 31 NoCancellation No cancellation pending 0x00000000 Cancellation Cancellation pending 0x00000001 TXBTO Tx Buffer Transmission Occurred 0x0D8 read-only 0x00000000 0x20 TO Transmission Occurred 0 31 NoTransmittion No transmission occurred 0x00000000 Transmittion Transmission occurred 0x00000001 TXBCF Tx Buffer Cancellation Finished 0x0DC read-only 0x00000000 0x20 CF Cancellation Finished 0 31 NoCancellation No transmit buffer cancellation 0x00000000 CancellationFinished Transmit buffer cancellation finished 0x00000001 TXBTIE Tx Buffer Transmission Interrupt Enable 0x0E0 read-write 0x00000000 0x20 TIE Transmission Interrupt Enable 0 31 Disable Transmission interrupt disabled 0x00000000 Enable Transmission interrupt enable 0x00000001 TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0x0E4 read-write 0x00000000 0x20 CFIE Cancellation Finished Interrupt Enable 0 31 Disable Cancellation finished interrupt disabled 0x00000000 Enable Cancellation finished interrupt enabled 0x00000001 TXEFC Tx Event FIFO Configuration 0x0F0 read-write 0x00000000 0x20 EFSA Event FIFO Start Address 2 15 EFS Event FIFO Size 16 21 EFWM Event FIFO Watermark 24 29 TXEFS Tx Event FIFO Status 0x0F4 read-only 0x00000000 0x20 EFFL Event FIFO Fill Level 0 5 EFGI Event FIFO Get Index 8 12 EFPI Event FIFO Put Index 16 20 EFF Event FIFO Full 24 24 NotFull Tx Event FIFO not full 0x0 Full Tx Event FIFO full 0x1 TEFL Tx Event FIFO Element Lost 25 25 NotLost No Tx Event FIFO element lost 0x0 Lost Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero. 0x1 TXEFA Tx Event FIFO Acknowledge 0x0F8 read-write 0x00000000 0x20 EFAI Event FIFO Acknowledge Index 0 4 GLOBAL_STMDATA_NS System Trace Macrocell data buffer 0 0xA0000000 STMDATA 0 0x10000000 registers STMDATA 0x20 16 0x2000000 DOMAIN[%s] Unspecified DOMAIN read-write 0x000 0x1000000 0x1 NSDATA[%s] Description collection: NonSecure STM output data buffer for domain n. Writes to this region generates trace packets with id n+96. 0x000 read-write 0x00 uint8_t 0x8 0x1000000 0x1 SDATA[%s] Description collection: Secure STM output data buffer for domain n. Writes to this region generates trace packets with id n+32. 0x1000000 read-write 0x00 uint8_t 0x8 GLOBAL_STMDATA_S System Trace Macrocell data buffer 1 0xA0000000 GLOBAL_STMDATA_NS GLOBAL_TDDCONF_NS TDDCONF 0 0xBF001000 TDDCONF 0 0x1000 registers TDDCONF 0x20 SYSPWRUPREQ System power-up request 0x400 read-write 0x00000000 0x20 ACTIVE Activate power-up request 0 0 NotActive Power-up request not active 0x0 Active Power-up request active 0x1 DBGPWRUPREQ Debug power-up request 0x404 read-write 0x00000000 0x20 ACTIVE Activate power-up request 0 0 NotActive Power-up request not active 0x0 Active Power-up request active 0x1 TRACEPORTSPEED Trace port trace clock speed 0x408 read-write 0x00000000 0x20 SPEED Trace clock speed 0 1 DEBUGPOWERREQSTATUS Combined effective system status of both SWJ-DP and TDDCONF registers originated power requests 0x40C read-only 0x00000000 0x20 SYSPWRUPREQUESTED System powerup request status 0 0 NoPowerReq Power not requested 0x0 PowerReq Power requested 0x1 DBGPWRUPREQUESTED Debug domain powerup request status 1 1 NoPowerReq Power not requested 0x0 PowerReq Power requested 0x1 GLOBAL_TDDCONF_S TDDCONF 1 0xBF001000 GLOBAL_TDDCONF_NS GLOBAL_STM_NS System Trace Macrocell 0xBF042000 STM 0 0x1000 registers STM 0x20 DMACTLR Controls the DMA transfer request mechanism. 0xC10 read-write 0x00000000 0x20 SENS Determines the sensitivity of the DMA request to the current buffer level in the STM 2 3 LT25 Buffer is <25 percent full. 0x0 LT50 Buffer is <50 percent full. 0x1 LT75 Buffer is <75 percent full. 0x2 LT100 Buffer is <100 percent full. 0x3 HEMASTR Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2. 0xDF4 read-only 0x00000000 0x20 MASTER The STPv2 master number that hardware event traces should be associated with. 0 16 HEFEAT1R Indicates the features of the STM. 0xDF8 read-only 0x00000000 0x20 HETER STMHETER support 0 0 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 HEERR Hardware event error detection support 2 2 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 HEMASTR STMHEMASTR support 3 3 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 NUMHE The number of hardware events supported by the STM 15 23 HEIDR Indicates the features of hardware event tracing in the STM. 0xDFC read-only 0x00000000 0x20 CLASS The CLASS field identifies the programmers model 0 3 HardwareEventControl Hardware Event Control programmers model 0x1 CLASSREV The CLASSREV field identifies the revision of the programmers model 4 7 VENDSPEC The VENDSPEC field identifies any vendor specific modifications or mappings 8 11 TCSR Controls the STM settings. 0xE80 read-write 0x00000000 0x20 EN Global STM enable 0 0 Disabled The STM is disabled. 0x0 Enabled The STM is enabled. 0x1 TSEN Enable or disable timestamp bundling. 1 1 Disabled Time stamps are disabled. Requests for timestamp generation are ignored, and stimulus port writes selecting timestamping are treated as if it were not selected. 0x0 Enabled Time stamps are enabled. If stimulus writes select timestamping, a timestamp is output according to STPv2. 0x1 SYNCEN STMSYNCR is implemented so this value is Read As One. 2 2 Disabled The STM Sync feature is disabled. 0x0 Enabled The STM Sync feature is enabled. 0x1 COMPEN Compression Enable for Stimulus Ports. 5 5 Disabled Compression disabled, data transfers are transmitted at the size of the transaction. 0x0 Enabled Compression enabled, data transfers are compressed to save bandwidth. 0x1 TRACEID ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing. 16 22 BUSY STM is busy, for example the STM trace FIFO is not empty. 23 23 Ready STM is not busy. 0x0 Busy STM is busy. 0x1 AUXCR Used for implementation defined STM controls. 0xE94 read-write 0x00000000 0x20 FIFOAF FIFO Auto-flush. 0 0 Disabled Auto-flush is disabled. 0x0 Enabled Auto-flush is enabled. The STM automatically drains all data it has even if the ATB interface is not fully utilized. 0x1 ASYNCPE Is ASYNC priority higher than trace? 1 1 Lower ASYNC priority is always lower than trace. 0x0 Escalate ASYNC priority escalates on second synchronization request. 0x1 PRIORINVDIS Controls arbitration between AXI and HW during flush. 2 2 Enabled Priority inversion, when AXI flush is finished, HW gets priority until HW flush is done. 0x0 Disabled Priority inversion disabled, AXI always has priority over HW. 0x1 CLKON Provides override control for architectural clock gate enable. 3 3 Disabled No override, clock gate is controlled by the state of STM. 0x0 Enabled Override, clock is enabled. 0x1 AFREADYHIGH Provides override control for the AFREADY output 4 4 Disabled No override, AFREADY is controlled by the state of STM. 0x0 Enabled Override, AFREADY is driven HIGH. 0x1 SPFEAT1R Indicates the features of the STM. 0xEA0 read-write 0x00000000 0x20 PROT Indicates the implemented STM protocol. 0 3 STPV2 STM implements the STPV2 protocol. 0x1 TS Timestamp support. 4 5 Absolute Absolute timestamps implemented. 0x1 TSFREQ Timestamp frequency indication configuration. 6 6 NotImplemented STMTSFREQR is read-only. 0x0 Implemented STMTSFREQR is read-write. 0x1 FORCETS Timestamp force configuration. 7 7 NotImplemented STMTSSTIMR bit 0 is read-only. 0x0 Implemented STMTSSTIMR bit 0 is read-write. 0x1 TRACEBUS Trace bus support. 10 13 TRIGCTL Trigger control support. 14 15 TSPRESCALE Timestamp prescale support 16 17 NotImplemented Timestamp prescale is not implemented. 0x0 Implemented Timestamp prescale is implemented. 0x1 HWTEN STMTCSR.HWTEN support 18 19 NotImplemented STMTCSR.HWTEN is not implemented 0x1 SYNCEN STMTCSR.SYNCEN support 20 21 ReadAsOne STMTCSR.SYNCEN implemented but always reads as b1 0x2 SWOEN STMTCSR.SWOEN support 22 23 NotImplemented STMTCSR.SWOEN not implemented 0x1 SPFEAT2R Indicates the features of the STM. 0xEA4 read-write 0x00000000 0x20 SPTER STMSPTER support. 0 1 Implemented STMSPTER is implemented. 0x2 SPER STMSPER presence. 2 2 Implemented STMSPER is implemented. 0x0 NotImplemented STMSPER is not implemented. 0x1 SPCOMP Data compression on stimulus ports support. 4 5 Programmable Data compression support is programmable. STMTCSR.COMPEN is implemented. 0x3 SPOVERRIDE Timestamp force configuration. 6 6 NotImplemented STMSPOVERRIDER and STMSPMOVERRIDER is not implemented. 0x0 Implemented STMSPOVERRIDER and STMSPMOVERRIDER is implemented. 0x1 PRIVMASK STMPRIVMASKR support. 7 8 NotImplemented STMPRIVMASKR is not implemented. 0x1 SPTRTYPE Stimulus port transaction type support. 9 10 InvariantAndGuaranteed Both invariant timing and guaranteed transactions are supported. 0x2 DSIZE Fundamental data size. 12 15 Bits32 32-bit data. 0x0 SPTYPE Stimulus port type support 18 19 OnlyExtended Only extended stimulus ports are implemented. 0x1 SPFEAT3R Indicates the features of the STM. 0xEA8 read-write 0x00000000 0x20 NUMMAST The number of stimulus ports masters implemented, minus 1. 0 6 Masters128 Example: 128 masters implemented. 0x3F ITTRIGGER Integration Test for Cross-Trigger Outputs Register. 0xEE8 write-only 0x00000000 0x20 TRIGOUTSPTE_W Sets the value of the TRIGOUTSPTE output in integration mode. 0 0 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 TRIGOUTSW_W Sets the value of the TRIGOUTSW output in integration mode. 1 1 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 TRIGOUTHETE_W Sets the value of the TRIGOUTHETE output in integration mode. 2 2 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 ASYNCOUT_W Sets the value of the ASYNCOUT output in integration mode. 3 3 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 ITATBDATA0 Controls the value of the ATDATAM output in integration mode. 0xEEC write-only 0x00000000 0x20 ATDATAM0_W Sets the value of the ATDATAM[0]. 0 0 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 ATDATAM7_W Sets the value of the ATDATAM[7] output. 1 1 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 ATDATAM15_W Sets the value of the ATDATAM[15]. 2 2 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 ATDATAM23_W Sets the value of the ATDATAM[23]. 3 3 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 ATDATAM31_W Sets the value of the ATDATAM[31]. 4 4 Low Drive logic 0 on output. 0x0 High Drive logic 1 on output. 0x1 ITATBCTR2 Controls the value of the ATDATAM output in integration mode. 0xEF0 write-only 0x00000000 0x20 ATREADYM_R Reads the value of the ATREADYM input. 0 0 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 AFVALIDM_R Reads the value of the AFVALIDM input. 1 1 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ITATBID Controls the value of the ATIDM output in integration mode. 0xEF4 write-only 0x00000000 0x20 ATIDM_W_0 Sets the value of pin 0 of the ATIDM output. 0 0 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ATIDM_W_1 Sets the value of pin 1 of the ATIDM output. 1 1 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ATIDM_W_2 Sets the value of pin 2 of the ATIDM output. 2 2 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ATIDM_W_3 Sets the value of pin 3 of the ATIDM output. 3 3 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ATIDM_W_4 Sets the value of pin 4 of the ATIDM output. 4 4 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ATIDM_W_5 Sets the value of pin 5 of the ATIDM output. 5 5 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ATIDM_W_6 Sets the value of pin 6 of the ATIDM output. 6 6 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ITATBCTR0 Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mode. 0xEF8 write-only 0x00000000 0x20 ATVALIDM_W Sets the value of the ATVALIDM output. 0 0 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 AFREADYM_W Sets the value of the AFREADYM_W output. 1 1 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ATBYTESM_W_0 Sets the value of pin 0 of the ATBYTESM output. 8 8 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ATBYTESM_W_1 Sets the value of pin 1 of the ATBYTESM output. 9 9 Low Pin is at logic 0. 0x0 High Pin is at logic 1. 0x1 ITCTRL Used to enable topology detection. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. 0xF00 read-write 0x00000000 0x20 INTEGRATIONMODE Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. 0 0 Disabled Integration mode is disabled. 0x0 Enabled Integration mode is Enabled. 0x1 LAR This is used to enable write access to device registers. 0xFB0 read-write 0x00000000 0x20 ACCESS A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. 0 31 UnLock Unlock register interface. 0xC5ACCE55 LSR This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register. 0xFB4 read-write 0x00000000 0x20 PRESENT Indicates that a lock control mechanism exists for this device. 0 0 NotImplemented No lock control mechanism exists, writes to the Lock Access Register are ignored. 0x0 Implemented Lock control mechanism is present. 0x1 LOCKED Returns the current status of the Lock. 1 1 UnLocked Write access is allowed to this device. 0x0 Locked Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. 0x1 TYPE Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. 2 2 Bits32 This component implements a 32-bit Lock Access Register. 0x0 Bits8 This component implements an 8-bit Lock Access Register. 0x1 AUTHSTATUS Indicates the current level of tracing permitted by the system 0xFB8 read-write 0x00000000 0x20 NSID Non-secure Invasive Debug 0 1 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 NSNID Non-secure Non-Invasive Debug 2 3 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 SID Secure Invasive Debug 4 5 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 SNID Secure Non-Invasive Debug 6 7 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 DEVID Indicates the capabilities of the STM. 0xFC8 read-only 0x00000000 0x20 NUMSP This value indicates the number of stimulus ports implemented. 0 16 Max Maximum 65,536 stimulus ports can be implemented. 0x10000 DEVTYPE Controls the single-shot comparator. 0xFCC read-only 0x00000000 0x20 MAJOR The main type of the component 0 3 TraceSource Peripheral is a trace source. 0x3 SUB The sub-type of the component 4 7 StimulusTrace Peripheral is a stimulus trace source. 0x6 PIDR4 Coresight peripheral identification registers. 0xFD0 read-write 0x00000000 0x20 PIDR_0 Coresight peripheral identification registers. 0xFE0 read-write 0x00000000 0x20 PIDR_1 Coresight peripheral identification registers. 0xFE4 read-write 0x00000000 0x20 PIDR_2 Coresight peripheral identification registers. 0xFE8 read-write 0x00000000 0x20 PIDR_3 Coresight peripheral identification registers. 0xFEC read-write 0x00000000 0x20 CIDR_0 Coresight component identification registers. 0xFF0 read-write 0x00000000 0x20 CIDR_1 Coresight component identification registers. 0xFF4 read-write 0x00000000 0x20 CIDR_2 Coresight component identification registers. 0xFF8 read-write 0x00000000 0x20 CIDR_3 Coresight component identification registers. 0xFFC read-write 0x00000000 0x20 GLOBAL_TPIU_NS Trace Port Interface Unit 0xBF043000 TPIU 0 0x1000 registers TPIU 0x20 SUPPORTEDPORTSIZES Each bit location is a single port size that is supported on the device. 0x000 read-write 0x00000000 0x20 PORT_SIZE_1 Indicates whether the TPIU supports port size of 1-bit. 0 0 NotSupported Port size 1 is not supported. 0x0 Supported Port size 1 is supported. 0x1 PORT_SIZE_2 Indicates whether the TPIU supports port size of 2-bit. 1 1 NotSupported Port size 2 is not supported. 0x0 Supported Port size 2 is supported. 0x1 PORT_SIZE_3 Indicates whether the TPIU supports port size of 3-bit. 2 2 NotSupported Port size 3 is not supported. 0x0 Supported Port size 3 is supported. 0x1 PORT_SIZE_4 Indicates whether the TPIU supports port size of 4-bit. 3 3 NotSupported Port size 4 is not supported. 0x0 Supported Port size 4 is supported. 0x1 PORT_SIZE_5 Indicates whether the TPIU supports port size of 5-bit. 4 4 NotSupported Port size 5 is not supported. 0x0 Supported Port size 5 is supported. 0x1 PORT_SIZE_6 Indicates whether the TPIU supports port size of 6-bit. 5 5 NotSupported Port size 6 is not supported. 0x0 Supported Port size 6 is supported. 0x1 PORT_SIZE_7 Indicates whether the TPIU supports port size of 7-bit. 6 6 NotSupported Port size 7 is not supported. 0x0 Supported Port size 7 is supported. 0x1 PORT_SIZE_8 Indicates whether the TPIU supports port size of 8-bit. 7 7 NotSupported Port size 8 is not supported. 0x0 Supported Port size 8 is supported. 0x1 PORT_SIZE_9 Indicates whether the TPIU supports port size of 9-bit. 8 8 NotSupported Port size 9 is not supported. 0x0 Supported Port size 9 is supported. 0x1 PORT_SIZE_10 Indicates whether the TPIU supports port size of 10-bit. 9 9 NotSupported Port size 10 is not supported. 0x0 Supported Port size 10 is supported. 0x1 PORT_SIZE_11 Indicates whether the TPIU supports port size of 11-bit. 10 10 NotSupported Port size 11 is not supported. 0x0 Supported Port size 11 is supported. 0x1 PORT_SIZE_12 Indicates whether the TPIU supports port size of 12-bit. 11 11 NotSupported Port size 12 is not supported. 0x0 Supported Port size 12 is supported. 0x1 PORT_SIZE_13 Indicates whether the TPIU supports port size of 13-bit. 12 12 NotSupported Port size 13 is not supported. 0x0 Supported Port size 13 is supported. 0x1 PORT_SIZE_14 Indicates whether the TPIU supports port size of 14-bit. 13 13 NotSupported Port size 14 is not supported. 0x0 Supported Port size 14 is supported. 0x1 PORT_SIZE_15 Indicates whether the TPIU supports port size of 15-bit. 14 14 NotSupported Port size 15 is not supported. 0x0 Supported Port size 15 is supported. 0x1 PORT_SIZE_16 Indicates whether the TPIU supports port size of 16-bit. 15 15 NotSupported Port size 16 is not supported. 0x0 Supported Port size 16 is supported. 0x1 PORT_SIZE_17 Indicates whether the TPIU supports port size of 17-bit. 16 16 NotSupported Port size 17 is not supported. 0x0 Supported Port size 17 is supported. 0x1 PORT_SIZE_18 Indicates whether the TPIU supports port size of 18-bit. 17 17 NotSupported Port size 18 is not supported. 0x0 Supported Port size 18 is supported. 0x1 PORT_SIZE_19 Indicates whether the TPIU supports port size of 19-bit. 18 18 NotSupported Port size 19 is not supported. 0x0 Supported Port size 19 is supported. 0x1 PORT_SIZE_20 Indicates whether the TPIU supports port size of 20-bit. 19 19 NotSupported Port size 20 is not supported. 0x0 Supported Port size 20 is supported. 0x1 PORT_SIZE_21 Indicates whether the TPIU supports port size of 21-bit. 20 20 NotSupported Port size 21 is not supported. 0x0 Supported Port size 21 is supported. 0x1 PORT_SIZE_22 Indicates whether the TPIU supports port size of 22-bit. 21 21 NotSupported Port size 22 is not supported. 0x0 Supported Port size 22 is supported. 0x1 PORT_SIZE_23 Indicates whether the TPIU supports port size of 23-bit. 22 22 NotSupported Port size 23 is not supported. 0x0 Supported Port size 23 is supported. 0x1 PORT_SIZE_24 Indicates whether the TPIU supports port size of 24-bit. 23 23 NotSupported Port size 24 is not supported. 0x0 Supported Port size 24 is supported. 0x1 PORT_SIZE_25 Indicates whether the TPIU supports port size of 25-bit. 24 24 NotSupported Port size 25 is not supported. 0x0 Supported Port size 25 is supported. 0x1 PORT_SIZE_26 Indicates whether the TPIU supports port size of 26-bit. 25 25 NotSupported Port size 26 is not supported. 0x0 Supported Port size 26 is supported. 0x1 PORT_SIZE_27 Indicates whether the TPIU supports port size of 27-bit. 26 26 NotSupported Port size 27 is not supported. 0x0 Supported Port size 27 is supported. 0x1 PORT_SIZE_28 Indicates whether the TPIU supports port size of 28-bit. 27 27 NotSupported Port size 28 is not supported. 0x0 Supported Port size 28 is supported. 0x1 PORT_SIZE_29 Indicates whether the TPIU supports port size of 29-bit. 28 28 NotSupported Port size 29 is not supported. 0x0 Supported Port size 29 is supported. 0x1 PORT_SIZE_30 Indicates whether the TPIU supports port size of 30-bit. 29 29 NotSupported Port size 30 is not supported. 0x0 Supported Port size 30 is supported. 0x1 PORT_SIZE_31 Indicates whether the TPIU supports port size of 31-bit. 30 30 NotSupported Port size 31 is not supported. 0x0 Supported Port size 31 is supported. 0x1 PORT_SIZE_32 Indicates whether the TPIU supports port size of 32-bit. 31 31 NotSupported Port size 32 is not supported. 0x0 Supported Port size 32 is supported. 0x1 CURRENTPORTSIZE Each bit location is a single port size. One bit can be set, and indicates the current port size. 0x004 read-write 0x00000000 0x20 PORT_SIZE_1 Indicates which port size is currently selected. 0 0 NotSelected Port size 1 is not selected. 0x0 Selected Port size 1 is selected. 0x1 PORT_SIZE_2 Indicates which port size is currently selected. 1 1 NotSelected Port size 2 is not selected. 0x0 Selected Port size 2 is selected. 0x1 PORT_SIZE_3 Indicates which port size is currently selected. 2 2 NotSelected Port size 3 is not selected. 0x0 Selected Port size 3 is selected. 0x1 PORT_SIZE_4 Indicates which port size is currently selected. 3 3 NotSelected Port size 4 is not selected. 0x0 Selected Port size 4 is selected. 0x1 PORT_SIZE_5 Indicates which port size is currently selected. 4 4 NotSelected Port size 5 is not selected. 0x0 Selected Port size 5 is selected. 0x1 PORT_SIZE_6 Indicates which port size is currently selected. 5 5 NotSelected Port size 6 is not selected. 0x0 Selected Port size 6 is selected. 0x1 PORT_SIZE_7 Indicates which port size is currently selected. 6 6 NotSelected Port size 7 is not selected. 0x0 Selected Port size 7 is selected. 0x1 PORT_SIZE_8 Indicates which port size is currently selected. 7 7 NotSelected Port size 8 is not selected. 0x0 Selected Port size 8 is selected. 0x1 PORT_SIZE_9 Indicates which port size is currently selected. 8 8 NotSelected Port size 9 is not selected. 0x0 Selected Port size 9 is selected. 0x1 PORT_SIZE_10 Indicates which port size is currently selected. 9 9 NotSelected Port size 10 is not selected. 0x0 Selected Port size 10 is selected. 0x1 PORT_SIZE_11 Indicates which port size is currently selected. 10 10 NotSelected Port size 11 is not selected. 0x0 Selected Port size 11 is selected. 0x1 PORT_SIZE_12 Indicates which port size is currently selected. 11 11 NotSelected Port size 12 is not selected. 0x0 Selected Port size 12 is selected. 0x1 PORT_SIZE_13 Indicates which port size is currently selected. 12 12 NotSelected Port size 13 is not selected. 0x0 Selected Port size 13 is selected. 0x1 PORT_SIZE_14 Indicates which port size is currently selected. 13 13 NotSelected Port size 14 is not selected. 0x0 Selected Port size 14 is selected. 0x1 PORT_SIZE_15 Indicates which port size is currently selected. 14 14 NotSelected Port size 15 is not selected. 0x0 Selected Port size 15 is selected. 0x1 PORT_SIZE_16 Indicates which port size is currently selected. 15 15 NotSelected Port size 16 is not selected. 0x0 Selected Port size 16 is selected. 0x1 PORT_SIZE_17 Indicates which port size is currently selected. 16 16 NotSelected Port size 17 is not selected. 0x0 Selected Port size 17 is selected. 0x1 PORT_SIZE_18 Indicates which port size is currently selected. 17 17 NotSelected Port size 18 is not selected. 0x0 Selected Port size 18 is selected. 0x1 PORT_SIZE_19 Indicates which port size is currently selected. 18 18 NotSelected Port size 19 is not selected. 0x0 Selected Port size 19 is selected. 0x1 PORT_SIZE_20 Indicates which port size is currently selected. 19 19 NotSelected Port size 20 is not selected. 0x0 Selected Port size 20 is selected. 0x1 PORT_SIZE_21 Indicates which port size is currently selected. 20 20 NotSelected Port size 21 is not selected. 0x0 Selected Port size 21 is selected. 0x1 PORT_SIZE_22 Indicates which port size is currently selected. 21 21 NotSelected Port size 22 is not selected. 0x0 Selected Port size 22 is selected. 0x1 PORT_SIZE_23 Indicates which port size is currently selected. 22 22 NotSelected Port size 23 is not selected. 0x0 Selected Port size 23 is selected. 0x1 PORT_SIZE_24 Indicates which port size is currently selected. 23 23 NotSelected Port size 24 is not selected. 0x0 Selected Port size 24 is selected. 0x1 PORT_SIZE_25 Indicates which port size is currently selected. 24 24 NotSelected Port size 25 is not selected. 0x0 Selected Port size 25 is selected. 0x1 PORT_SIZE_26 Indicates which port size is currently selected. 25 25 NotSelected Port size 26 is not selected. 0x0 Selected Port size 26 is selected. 0x1 PORT_SIZE_27 Indicates which port size is currently selected. 26 26 NotSelected Port size 27 is not selected. 0x0 Selected Port size 27 is selected. 0x1 PORT_SIZE_28 Indicates which port size is currently selected. 27 27 NotSelected Port size 28 is not selected. 0x0 Selected Port size 28 is selected. 0x1 PORT_SIZE_29 Indicates which port size is currently selected. 28 28 NotSelected Port size 29 is not selected. 0x0 Selected Port size 29 is selected. 0x1 PORT_SIZE_30 Indicates which port size is currently selected. 29 29 NotSelected Port size 30 is not selected. 0x0 Selected Port size 30 is selected. 0x1 PORT_SIZE_31 Indicates which port size is currently selected. 30 30 NotSelected Port size 31 is not selected. 0x0 Selected Port size 31 is selected. 0x1 PORT_SIZE_32 Indicates which port size is currently selected. 31 31 NotSelected Port size 32 is not selected. 0x0 Selected Port size 32 is selected. 0x1 SUPPORTEDTRIGGERMODES The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system. 0x100 read-write 0x00000000 0x20 MULT_0 Indicates whether multiplying the trigger counter by 2^(0+1) is supported. 0 0 NotSelected Multiplying the trigger counter by 2^(0+1) is supported. 0x0 Selected Multiplying the trigger counter by 2^(0+1) is supported. 0x1 MULT_1 Indicates whether multiplying the trigger counter by 2^(1+1) is supported. 1 1 NotSelected Multiplying the trigger counter by 2^(1+1) is supported. 0x0 Selected Multiplying the trigger counter by 2^(1+1) is supported. 0x1 MULT_2 Indicates whether multiplying the trigger counter by 2^(2+1) is supported. 2 2 NotSelected Multiplying the trigger counter by 2^(2+1) is supported. 0x0 Selected Multiplying the trigger counter by 2^(2+1) is supported. 0x1 MULT_3 Indicates whether multiplying the trigger counter by 2^(3+1) is supported. 3 3 NotSelected Multiplying the trigger counter by 2^(3+1) is supported. 0x0 Selected Multiplying the trigger counter by 2^(3+1) is supported. 0x1 MULT_4 Indicates whether multiplying the trigger counter by 2^(4+1) is supported. 4 4 NotSelected Multiplying the trigger counter by 2^(4+1) is supported. 0x0 Selected Multiplying the trigger counter by 2^(4+1) is supported. 0x1 TCOUNT8 Indicates whether an 8-bit wide counter register is implemented. 8 8 NotImplemented An 8-bit wide counter register is implemented. 0x0 Implemented An 8-bit wide counter register is implemented. 0x1 TRIGGERED A trigger has occurred and the counter has reached 0. 16 16 NotOccured Trigger has not occurred. 0x0 Occured Trigger has occurred. 0x1 TRGRUN A trigger has occurred but the counter is not at 0. 17 17 NotOccured Either a trigger has not occurred or the counter is at 0. 0x0 Occured A trigger has occurred but the counter is not at 0. 0x1 TRIGGERCOUNTERVALUE The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices. 0x104 read-write 0x00000000 0x20 TrigCount 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. 0 7 TRIGGERMULTIPLIER The Trigger_multiplier register contains the selectors for the trigger counter multiplier. 0x108 read-write 0x00000000 0x20 MULT_0 Multiply the Trigger Counter by 2^n. 0 0 Disabled Multiplier disabled. 0x0 Enabled Multiplier enabled. 0x1 MULT_1 Multiply the Trigger Counter by 2^n. 1 1 Disabled Multiplier disabled. 0x0 Enabled Multiplier enabled. 0x1 MULT_2 Multiply the Trigger Counter by 2^n. 2 2 Disabled Multiplier disabled. 0x0 Enabled Multiplier enabled. 0x1 MULT_3 Multiply the Trigger Counter by 2^n. 3 3 Disabled Multiplier disabled. 0x0 Enabled Multiplier enabled. 0x1 MULT_4 Multiply the Trigger Counter by 2^n. 4 4 Disabled Multiplier disabled. 0x0 Enabled Multiplier enabled. 0x1 SUPPPORTEDTESTPATTERNMODES The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device. 0x200 read-write 0x00000000 0x20 PATW1 Indicates whether the walking 1s pattern is supported as output over the trace port. 0 0 NotSupported Test pattern is not supported. 0x0 Supported Test pattern is supported. 0x1 PATW0 Indicates whether the walking 0s pattern is supported as output over the trace port. 1 1 NotSupported Test pattern is not supported. 0x0 Supported Test pattern is supported. 0x1 PATA5 Indicates whether the AA/55 pattern is supported as output over the trace port. 2 2 NotSupported Test pattern is not supported. 0x0 Supported Test pattern is supported. 0x1 PATF0 Indicates whether the FF/00 pattern is supported as output over the trace port. 3 3 NotSupported Test pattern is not supported. 0x0 Supported Test pattern is supported. 0x1 PTIMEEN Indicates whether timed mode is supported. 16 16 NotSupported Mode is not supported. 0x0 Supported Mode is supported. 0x1 PCONTEN Indicates whether continuous mode is supported. 17 17 NotSupported Mode is not supported. 0x0 Supported Mode is supported. 0x1 CURRENTTESTPATTERNMODES Current_test_pattern_mode indicates the current test pattern or mode selected. 0x204 read-write 0x00000000 0x20 PATW1 Indicates whether the walking 1s pattern is supported as output over the trace port. 0 0 Disabled Test pattern is disabled. 0x0 Enabled Test pattern is enabled. 0x1 PATW0 Indicates whether the walking 0s pattern is supported as output over the trace port. 1 1 Disabled Test pattern is disabled. 0x0 Enabled Test pattern is enabled. 0x1 PATA5 Indicates whether the AA/55 pattern is supported as output over the trace port. 2 2 Disabled Test pattern is disabled. 0x0 Enabled Test pattern is enabled. 0x1 PATF0 Indicates whether the FF/00 pattern is supported as output over the trace port. 3 3 Disabled Test pattern is disabled. 0x0 Enabled Test pattern is enabled. 0x1 PTIMEEN Indicates whether timed mode is supported. 16 16 Disabled Mode is disabled. 0x0 Enabled Mode is enabled. 0x1 PCONTEN Indicates whether continuous mode is supported. 17 17 Disabled Mode is disabled. 0x0 Enabled Mode is enabled. 0x1 TPRCR The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. 0x208 read-write 0x00000000 0x20 PATTCOUNT 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern. 0 7 FFSR The FFSR register indicates the current status of the formatter and flush features available in the TPIU. 0x300 read-write 0x00000000 0x20 FLINPROG Flush in progress. 0 0 NotInProgress A flush is not in progress. 0x0 InProgress A flush is in progress. 0x1 FTSTOPPED The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. 1 1 Running Formatter has not stopped. 0x0 Stopped Formatter has stopped. 0x1 TCPRESENT Indicates whether the TRACECTL pin is available for use. 2 2 NotPresent TRACECTL pin is not present. 0x0 Present TRACECTL pin is present. 0x1 FFCR The FFCR register controls the generation of stop, trigger, and flush events. 0x304 read-write 0x00000000 0x20 ENFTC Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present. 0 0 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 ENFCONT Is embedded in trigger packets and indicates that no cycle is using sync packets. 1 1 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 FONFLIN Enables the use of the flushin connection. 4 4 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 FONTRIG Initiates a manual flush of data in the system when a trigger event occurs. 5 5 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 FONMANR Generates a flush. This bit is set to 0 when this flush is serviced. 6 6 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 FONMANW Generates a flush. This bit is set to 1 when this flush is serviced. 7 7 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 TRIGIN Indicates a trigger when trigin is asserted. 8 8 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 TRIGEVT Indicates a trigger on a trigger event. 9 9 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 TRIGFL Indicates a trigger when flush completion on afreadys is returned. 10 10 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 STOPFL Forces the FIFO to drain off any part-completed packets. 12 12 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 STOPTRIG Stops the formatter after a trigger event is observed. Reset to disabled or 0. 13 13 Disabled The formatting feature is disabled. 0x0 Enabled The formatting feature is enabled. 0x1 FSCR The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size. 0x308 read-write 0x00000000 0x20 CYCCOUNT 12-bit counter reload value. Indicates the number of complete frames between full synchronization packets. 0 11 EXTCTLINPORT Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution. 0x400 read-write 0x00000000 0x20 EXTCTLIN_0 EXTCTL inputs. 0 0 Low Input EXTCTL0 is low. 0x0 High Input EXTCTL0 is high. 0x1 EXTCTLIN_1 EXTCTL inputs. 1 1 Low Input EXTCTL1 is low. 0x0 High Input EXTCTL1 is high. 0x1 EXTCTLIN_2 EXTCTL inputs. 2 2 Low Input EXTCTL2 is low. 0x0 High Input EXTCTL2 is high. 0x1 EXTCTLIN_3 EXTCTL inputs. 3 3 Low Input EXTCTL3 is low. 0x0 High Input EXTCTL3 is high. 0x1 EXTCTLIN_4 EXTCTL inputs. 4 4 Low Input EXTCTL4 is low. 0x0 High Input EXTCTL4 is high. 0x1 EXTCTLIN_5 EXTCTL inputs. 5 5 Low Input EXTCTL5 is low. 0x0 High Input EXTCTL5 is high. 0x1 EXTCTLIN_6 EXTCTL inputs. 6 6 Low Input EXTCTL6 is low. 0x0 High Input EXTCTL6 is high. 0x1 EXTCTLIN_7 EXTCTL inputs. 7 7 Low Input EXTCTL7 is low. 0x0 High Input EXTCTL7 is high. 0x1 EXTCTLOUTPORT Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. 0x404 read-write 0x00000000 0x20 EXTCTLOUT_0 EXTCTL outputs. 0 0 Low Output EXTCTL0 is low. 0x0 High Output EXTCTL0 is high. 0x1 EXTCTLOUT_1 EXTCTL outputs. 1 1 Low Output EXTCTL1 is low. 0x0 High Output EXTCTL1 is high. 0x1 EXTCTLOUT_2 EXTCTL outputs. 2 2 Low Output EXTCTL2 is low. 0x0 High Output EXTCTL2 is high. 0x1 EXTCTLOUT_3 EXTCTL outputs. 3 3 Low Output EXTCTL3 is low. 0x0 High Output EXTCTL3 is high. 0x1 EXTCTLOUT_4 EXTCTL outputs. 4 4 Low Output EXTCTL4 is low. 0x0 High Output EXTCTL4 is high. 0x1 EXTCTLOUT_5 EXTCTL outputs. 5 5 Low Output EXTCTL5 is low. 0x0 High Output EXTCTL5 is high. 0x1 EXTCTLOUT_6 EXTCTL outputs. 6 6 Low Output EXTCTL6 is low. 0x0 High Output EXTCTL6 is high. 0x1 EXTCTLOUT_7 EXTCTL outputs. 7 7 Low Output EXTCTL7 is low. 0x0 High Output EXTCTL7 is high. 0x1 ITTRFLINACK The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. 0xEE4 read-write 0x00000000 0x20 TRIGINACK Sets the value of triginack. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 FLUSHINACK Sets the value of flushinack. 1 1 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITTRFLIN The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. 0xEE8 read-write 0x00000000 0x20 TRIGIN Reads the value of trigin. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 FLUSHIN Reads the value of flushin. 1 1 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITATBDATA0 The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH. 0xEEC read-write 0x00000000 0x20 ATDATA_0 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_1 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 1 1 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_2 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 2 2 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_3 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 3 3 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_4 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 4 4 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITATBCTR2 Enables control of the atreadys and afvalids outputs of the TPIU. 0xEF0 read-write 0x00000000 0x20 ATREADY Sets the value of afvalid. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 AFVALID Sets the value of atready. 1 1 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITATBCTR1 The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH. 0xEF4 read-write 0x00000000 0x20 ATID Reads the value of atids. 0 6 Low Pin is logic 0. 0x00 High Pin is logic 1. 0x01 ITATBCTR0 The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH. 0xEF8 read-write 0x00000000 0x20 ATVALID Reads the value of atvalids. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 AFREADY Reads the value of afreadys. 2 2 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATBYTES Reads the value of atbytess. 8 9 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITCTRL Used to enable topology detection. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. 0xF00 read-write 0x00000000 0x20 INTEGRATIONMODE Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. 0 0 Disabled Integration mode is disabled. 0x0 Enabled Integration mode is Enabled. 0x1 CLAIMSET Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. 0xFA0 read-write 0x00000000 0x20 BIT_0 Set claim bit 0 and check if bit is implemented or not. 0 0 read NotImplemented Claim bit 0 is not implemented. 0x0 Implemented Claim bit 0 is implemented. 0x1 write Set Set claim bit 0. 0x1 BIT_1 Set claim bit 1 and check if bit is implemented or not. 1 1 read NotImplemented Claim bit 1 is not implemented. 0x0 Implemented Claim bit 1 is implemented. 0x1 write Set Set claim bit 1. 0x1 BIT_2 Set claim bit 2 and check if bit is implemented or not. 2 2 read NotImplemented Claim bit 2 is not implemented. 0x0 Implemented Claim bit 2 is implemented. 0x1 write Set Set claim bit 2. 0x1 BIT_3 Set claim bit 3 and check if bit is implemented or not. 3 3 read NotImplemented Claim bit 3 is not implemented. 0x0 Implemented Claim bit 3 is implemented. 0x1 write Set Set claim bit 3. 0x1 CLAIMCLR Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. 0xFA4 read-write 0x00000000 0x20 BIT_0 Read or clear claim bit 0. 0 0 read Cleared Claim bit 0 is not set. 0x0 Set Claim bit 0 is set. 0x1 write Clear Clear claim bit 0. 0x1 BIT_1 Read or clear claim bit 1. 1 1 read Cleared Claim bit 1 is not set. 0x0 Set Claim bit 1 is set. 0x1 write Clear Clear claim bit 1. 0x1 BIT_2 Read or clear claim bit 2. 2 2 read Cleared Claim bit 2 is not set. 0x0 Set Claim bit 2 is set. 0x1 write Clear Clear claim bit 2. 0x1 BIT_3 Read or clear claim bit 3. 3 3 read Cleared Claim bit 3 is not set. 0x0 Set Claim bit 3 is set. 0x1 write Clear Clear claim bit 3. 0x1 LAR This is used to enable write access to device registers. 0xFB0 read-write 0x00000000 0x20 ACCESS A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. 0 31 UnLock Unlock register interface. 0xC5ACCE55 LSR This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register. 0xFB4 read-write 0x00000000 0x20 PRESENT Indicates that a lock control mechanism exists for this device. 0 0 NotImplemented No lock control mechanism exists, writes to the Lock Access Register are ignored. 0x0 Implemented Lock control mechanism is present. 0x1 LOCKED Returns the current status of the Lock. 1 1 UnLocked Write access is allowed to this device. 0x0 Locked Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. 0x1 TYPE Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. 2 2 Bits32 This component implements a 32-bit Lock Access Register. 0x0 Bits8 This component implements an 8-bit Lock Access Register. 0x1 AUTHSTATUS Indicates the current level of tracing permitted by the system 0xFB8 read-write 0x00000000 0x20 NSID Non-secure Invasive Debug 0 1 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 NSNID Non-secure Non-Invasive Debug 2 3 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 SID Secure Invasive Debug 4 5 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 SNID Secure Non-Invasive Debug 6 7 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 DEVID Indicates the capabilities of the component. 0xFC8 read-only 0x00000000 0x20 MUXNUM Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB. Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. 0 4 CLKRELAT Indicates the relationship between atclk and traceclkin. 5 5 Synchronous atclk and traceclkin are synchronous. 0x0 ASynchronous atclk and traceclkin are asynchronous. 0x1 FIFOSIZE FIFO size in powers of 2. 6 8 Entries4 FIFO size of 4 entries, that is, 16 bytes. 0x2 TCLKDATA Indicates whether trace clock plus data is supported. 9 9 Supported Trace clock and data is supported. 0x0 NotSupported Trace clock and data is not supported. 0x1 SWOMAN Indicates whether Serial Wire Output, Manchester encoded format, is supported. 10 10 NotSupported Serial Wire Output, Manchester encoded format, is not supported. 0x0 Supported Serial Wire Output, Manchester encoded format, is supported. 0x1 SWOUARTNRZ Indicates whether Serial Wire Output, UART or NRZ, is supported. 11 11 NotSupported Serial Wire Output, UART or NRZ, is not supported. 0x0 Supported Serial Wire Output, UART or NRZ, is supported. 0x1 DEVTYPE The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. 0xFCC read-only 0x00000000 0x20 MAJOR The main type of the component 0 3 TraceSource Peripheral is a trace sink. 0x1 SUB The sub-type of the component 4 7 TracePort Indicates that this component is a trace port component. 0x1 PIDR4 Coresight peripheral identification registers. 0xFD0 read-write 0x00000000 0x20 PIDR_0 Coresight peripheral identification registers. 0xFE0 read-write 0x00000000 0x20 PIDR_1 Coresight peripheral identification registers. 0xFE4 read-write 0x00000000 0x20 PIDR_2 Coresight peripheral identification registers. 0xFE8 read-write 0x00000000 0x20 PIDR_3 Coresight peripheral identification registers. 0xFEC read-write 0x00000000 0x20 CIDR_0 Coresight component identification registers. 0xFF0 read-write 0x00000000 0x20 CIDR_1 Coresight component identification registers. 0xFF4 read-write 0x00000000 0x20 CIDR_2 Coresight component identification registers. 0xFF8 read-write 0x00000000 0x20 CIDR_3 Coresight component identification registers. 0xFFC read-write 0x00000000 0x20 GLOBAL_CTI210_NS Cross-Trigger Interface control 0 0xBF046000 CTI 0 0x1000 registers CTI 0x20 CTICONTROL CTI Control register 0x000 read-write 0x00000000 0x20 GLBEN Enables or disables the CTI. 0 0 Disabled All cross-triggering mapping logic functionality is disabled. 0x0 Enabled Cross-triggering mapping logic functionality is enabled. 0x1 CTIINTACK CTI Interrupt Acknowledge register 0x010 write-only 0x00000000 0x20 INTACK_0 Acknowledges the ctitrigout 0 output. 0 0 write Acknowledge Clears the ctitrigout. 0x1 INTACK_1 Acknowledges the ctitrigout 1 output. 1 1 write Acknowledge Clears the ctitrigout. 0x1 INTACK_2 Acknowledges the ctitrigout 2 output. 2 2 write Acknowledge Clears the ctitrigout. 0x1 INTACK_3 Acknowledges the ctitrigout 3 output. 3 3 write Acknowledge Clears the ctitrigout. 0x1 INTACK_4 Acknowledges the ctitrigout 4 output. 4 4 write Acknowledge Clears the ctitrigout. 0x1 INTACK_5 Acknowledges the ctitrigout 5 output. 5 5 write Acknowledge Clears the ctitrigout. 0x1 INTACK_6 Acknowledges the ctitrigout 6 output. 6 6 write Acknowledge Clears the ctitrigout. 0x1 INTACK_7 Acknowledges the ctitrigout 7 output. 7 7 write Acknowledge Clears the ctitrigout. 0x1 CTIAPPSET CTI Application Trigger Set register 0x014 read-write 0x00000000 0x20 APPSET_0 Application trigger event for channel 0. 0 0 read Inactive Application trigger 0 is inactive. 0x0 Active Application trigger 0 is active. 0x1 write Activate Generate channel event for channel 0. 0x1 APPSET_1 Application trigger event for channel 1. 1 1 read Inactive Application trigger 1 is inactive. 0x0 Active Application trigger 1 is active. 0x1 write Activate Generate channel event for channel 1. 0x1 APPSET_2 Application trigger event for channel 2. 2 2 read Inactive Application trigger 2 is inactive. 0x0 Active Application trigger 2 is active. 0x1 write Activate Generate channel event for channel 2. 0x1 APPSET_3 Application trigger event for channel 3. 3 3 read Inactive Application trigger 3 is inactive. 0x0 Active Application trigger 3 is active. 0x1 write Activate Generate channel event for channel 3. 0x1 CTIAPPCLEAR CTI Application Trigger Clear register 0x018 write-only 0x00000000 0x20 APPCLEAR_0 Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. 0 0 write Clear Clears the event for channel 0. 0x1 APPCLEAR_1 Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. 1 1 write Clear Clears the event for channel 1. 0x1 APPCLEAR_2 Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. 2 2 write Clear Clears the event for channel 2. 0x1 APPCLEAR_3 Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. 3 3 write Clear Clears the event for channel 3. 0x1 CTIAPPPULSE CTI Application Pulse register 0x01C write-only 0x00000000 0x20 APPULSE_0 Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. 0 0 write Generate Generates an event pulse on channel 0. 0x1 APPULSE_1 Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. 1 1 write Generate Generates an event pulse on channel 1. 0x1 APPULSE_2 Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. 2 2 write Generate Generates an event pulse on channel 2. 0x1 APPULSE_3 Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. 3 3 write Generate Generates an event pulse on channel 3. 0x1 0x8 0x4 CTIINEN[%s] Description collection: CTI Trigger to Channel Enable register 0x020 read-write 0x00000000 0x20 TRIGINEN_0 Enables a cross trigger event to channel 0 when a ctitrigin input is activated. 0 0 Disabled Input trigger n events are ignored by channel 0. 0x0 Enabled When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. 0x1 TRIGINEN_1 Enables a cross trigger event to channel 1 when a ctitrigin input is activated. 1 1 Disabled Input trigger n events are ignored by channel 1. 0x0 Enabled When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. 0x1 TRIGINEN_2 Enables a cross trigger event to channel 2 when a ctitrigin input is activated. 2 2 Disabled Input trigger n events are ignored by channel 2. 0x0 Enabled When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. 0x1 TRIGINEN_3 Enables a cross trigger event to channel 3 when a ctitrigin input is activated. 3 3 Disabled Input trigger n events are ignored by channel 3. 0x0 Enabled When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. 0x1 0x8 0x4 CTIOUTEN[%s] Description collection: CTI Channel to Trigger Enable register 0x0A0 read-write 0x00000000 0x20 TRIGOUTEN_0 Enables a cross trigger event to ctitrigout when channel 0 is activated. 0 0 Disabled Channel 0 is ignored by output trigger n. 0x0 Enabled When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). 0x1 TRIGOUTEN_1 Enables a cross trigger event to ctitrigout when channel 1 is activated. 1 1 Disabled Channel 1 is ignored by output trigger n. 0x0 Enabled When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). 0x1 TRIGOUTEN_2 Enables a cross trigger event to ctitrigout when channel 2 is activated. 2 2 Disabled Channel 2 is ignored by output trigger n. 0x0 Enabled When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). 0x1 TRIGOUTEN_3 Enables a cross trigger event to ctitrigout when channel 3 is activated. 3 3 Disabled Channel 3 is ignored by output trigger n. 0x0 Enabled When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). 0x1 CTITRIGINSTATUS CTI Trigger In Status register 0x130 read-only 0x00000000 0x20 TRIGINSTATUS_0 Shows the status of ctitrigin0 input. 0 0 Active Ctitrigin 0 is active. 0x1 Inactive Ctitrigin 0 is inactive. 0x0 TRIGINSTATUS_1 Shows the status of ctitrigin1 input. 1 1 Active Ctitrigin 1 is active. 0x1 Inactive Ctitrigin 1 is inactive. 0x0 TRIGINSTATUS_2 Shows the status of ctitrigin2 input. 2 2 Active Ctitrigin 2 is active. 0x1 Inactive Ctitrigin 2 is inactive. 0x0 TRIGINSTATUS_3 Shows the status of ctitrigin3 input. 3 3 Active Ctitrigin 3 is active. 0x1 Inactive Ctitrigin 3 is inactive. 0x0 TRIGINSTATUS_4 Shows the status of ctitrigin4 input. 4 4 Active Ctitrigin 4 is active. 0x1 Inactive Ctitrigin 4 is inactive. 0x0 TRIGINSTATUS_5 Shows the status of ctitrigin5 input. 5 5 Active Ctitrigin 5 is active. 0x1 Inactive Ctitrigin 5 is inactive. 0x0 TRIGINSTATUS_6 Shows the status of ctitrigin6 input. 6 6 Active Ctitrigin 6 is active. 0x1 Inactive Ctitrigin 6 is inactive. 0x0 TRIGINSTATUS_7 Shows the status of ctitrigin7 input. 7 7 Active Ctitrigin 7 is active. 0x1 Inactive Ctitrigin 7 is inactive. 0x0 CTITRIGOUTSTATUS CTI Trigger Out Status register 0x134 read-only 0x00000000 0x20 TRIGOUTSTATUS_0 Shows the status of ctitrigout0 output. 0 0 Active Ctitrigout 0 is active. 0x1 Inactive Ctitrigout 0 is inactive. 0x0 TRIGOUTSTATUS_1 Shows the status of ctitrigout1 output. 1 1 Active Ctitrigout 1 is active. 0x1 Inactive Ctitrigout 1 is inactive. 0x0 TRIGOUTSTATUS_2 Shows the status of ctitrigout2 output. 2 2 Active Ctitrigout 2 is active. 0x1 Inactive Ctitrigout 2 is inactive. 0x0 TRIGOUTSTATUS_3 Shows the status of ctitrigout3 output. 3 3 Active Ctitrigout 3 is active. 0x1 Inactive Ctitrigout 3 is inactive. 0x0 TRIGOUTSTATUS_4 Shows the status of ctitrigout4 output. 4 4 Active Ctitrigout 4 is active. 0x1 Inactive Ctitrigout 4 is inactive. 0x0 TRIGOUTSTATUS_5 Shows the status of ctitrigout5 output. 5 5 Active Ctitrigout 5 is active. 0x1 Inactive Ctitrigout 5 is inactive. 0x0 TRIGOUTSTATUS_6 Shows the status of ctitrigout6 output. 6 6 Active Ctitrigout 6 is active. 0x1 Inactive Ctitrigout 6 is inactive. 0x0 TRIGOUTSTATUS_7 Shows the status of ctitrigout7 output. 7 7 Active Ctitrigout 7 is active. 0x1 Inactive Ctitrigout 7 is inactive. 0x0 CTICHINSTATUS CTI Channel In Status register 0x138 read-only 0x00000000 0x20 CTICHINSTATUS_0 Shows the status of the ctitrigin 0 input. 0 0 Active Ctichin 0 is active. 0x1 Inactive Ctichin 0 is inactive. 0x0 CTICHINSTATUS_1 Shows the status of the ctitrigin 1 input. 1 1 Active Ctichin 1 is active. 0x1 Inactive Ctichin 1 is inactive. 0x0 CTICHINSTATUS_2 Shows the status of the ctitrigin 2 input. 2 2 Active Ctichin 2 is active. 0x1 Inactive Ctichin 2 is inactive. 0x0 CTICHINSTATUS_3 Shows the status of the ctitrigin 3 input. 3 3 Active Ctichin 3 is active. 0x1 Inactive Ctichin 3 is inactive. 0x0 CTIGATE Enable CTI Channel Gate register 0x140 read-write 0x0000000F 0x20 CTIGATEEN_0 Enable ctichout0. 0 0 Enabled Enable ctichout channel 0 propagation. 0x1 Disabled Disable ctichout channel 0 propagation. 0x0 CTIGATEEN_1 Enable ctichout1. 1 1 Enabled Enable ctichout channel 1 propagation. 0x1 Disabled Disable ctichout channel 1 propagation. 0x0 CTIGATEEN_2 Enable ctichout2. 2 2 Enabled Enable ctichout channel 2 propagation. 0x1 Disabled Disable ctichout channel 2 propagation. 0x0 CTIGATEEN_3 Enable ctichout3. 3 3 Enabled Enable ctichout channel 3 propagation. 0x1 Disabled Disable ctichout channel 3 propagation. 0x0 DEVARCH Device Architecture register 0xFBC read-only 0x47701A14 0x20 Architecture Contains the CTI device architecture. 0 0 DEVID Device Configuration register 0xFC8 read-only 0x00040800 0x20 EXTMUXNUM Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. 0 4 NUMTRIG Number of ECT triggers available. 8 15 NUMCH Number of ECT channels available. 16 19 DEVTYPE Device Type Identifier register 0xFCC read-only 0x00000014 0x20 MAJOR Major classification of the type of the debug component as specified in the Arm Architecture Specification for this debug and trace component. 0 3 Controller Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. 0x4 SUB Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within the major classification as specified in the MAJOR field. 4 7 Crosstrigger Indicates that this component is a sub-triggering component. 0x1 PIDR4 Peripheral ID4 Register 0xFD0 read-only 0x00000004 0x20 DES_2 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0 3 Code JEDEC continuation code. 0x4 SIZE Always 0b0000. Indicates that the device only occupies 4KB of memory. 4 7 PIDR5 Peripheral ID5 register 0xFD4 read-only 0x00000000 0x20 PIDR6 Peripheral ID6 register 0xFD8 read-only 0x00000000 0x20 PIDR7 Peripheral ID7 register 0xFDC read-only 0x00000000 0x20 PIDR0 Peripheral ID0 Register 0xFE0 read-only 0x00000021 0x20 PART_0 Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. 0 7 PartnumberL Indicates bits[7:0] of the part number of the component. 0x21 PIDR1 Peripheral ID1 Register 0xFE4 read-only 0x000000BD 0x20 PART_1 Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. 0 3 PartnumberH Indicates bits[11:8] of the part number of the component. 0xD DES_0 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 4 7 Arm Arm. Bits[3:0] of the JEDEC JEP106 Identity Code 0xB PIDR2 Peripheral ID2 Register 0xFE8 read-only 0x0000000B 0x20 DES_1 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0 2 Arm Arm. Bits[6:4] of the JEDEC JEP106 Identity Code 0x3 JEDEC Always 1. Indicates that the JEDEC-assigned designer ID is used. 3 3 REVISION Peripheral revision 4 7 Rev0p0 This device is at r0p0 0x0 PIDR3 Peripheral ID3 Register 0xFEC read-only 0x00000000 0x20 CMOD Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. 0 3 Unmodified Indicates that the customer has not modified this component. 0x0 REVAND Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. 4 7 NoErrata Indicates that there are no errata fixes to this component. 0x0 CIDR0 Component ID0 Register 0xFF0 read-only 0x0000000D 0x20 PRMBL_0 Preamble[0]. Contains bits[7:0] of the component identification code. 0 7 Value Bits[7:0] of the identification code. 0x0D CIDR1 Component ID1 Register 0xFF4 read-only 0x00000090 0x20 PRMBL_1 Preamble[1]. Contains bits[11:8] of the component identification code. 0 3 Value Bits[11:8] of the identification code. 0x0 CLASS Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code 4 7 Coresight Indicates that the component is a CoreSight component. 0x9 CIDR2 Component ID2 Register 0xFF8 read-only 0x00000005 0x20 PRMBL_2 Preamble[2]. Contains bits[23:16] of the component identification code. 0 7 Value Bits[23:16] of the identification code. 0x05 CIDR3 Component ID3 Register 0xFFC read-only 0x000000B1 0x20 PRMBL_3 Preamble[3]. Contains bits[31:24] of the component identification code. 0 7 Value Bits[31:24] of the identification code. 0xB1 GLOBAL_CTI211_NS Cross-Trigger Interface control 1 0xBF047000 GLOBAL_ATBREPLICATOR210_NS ATB Replicator module 0 0xBF048000 ATBREPLICATOR 0 0x1000 registers ATBREPLICATOR 0x20 IDFILTER0 The IDFILTER0 register enables the programming of ID filtering for master port 0. 0x000 read-write 0x00000000 0x20 ID0_00_0F Enable or disable ID filtering for IDs 0x00_0x0F. 0 0 NotFiltered Transactions with these IDs are passed on to ATB master port 0. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID0_10_1F Enable or disable ID filtering for IDs 0x10_0x1F. 1 1 NotFiltered Transactions with these IDs are passed on to ATB master port 0. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID0_20_2F Enable or disable ID filtering for IDs 0x20_0x2F. 2 2 NotFiltered Transactions with these IDs are passed on to ATB master port 0. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID0_30_3F Enable or disable ID filtering for IDs 0x30_0x3F. 3 3 NotFiltered Transactions with these IDs are passed on to ATB master port 0. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID0_40_4F Enable or disable ID filtering for IDs 0x40_0x4F. 4 4 NotFiltered Transactions with these IDs are passed on to ATB master port 0. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID0_50_5F Enable or disable ID filtering for IDs 0x50_0x5F. 5 5 NotFiltered Transactions with these IDs are passed on to ATB master port 0. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID0_60_6F Enable or disable ID filtering for IDs 0x60_0x6F. 6 6 NotFiltered Transactions with these IDs are passed on to ATB master port 0. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID0_70_7F Enable or disable ID filtering for IDs 0x70_0x7F. 7 7 NotFiltered Transactions with these IDs are passed on to ATB master port 0. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 IDFILTER1 The IDFILTER1 register enables the programming of ID filtering for master port 1. 0x004 read-write 0x00000000 0x20 ID1_00_0F Enable or disable ID filtering for IDs 0x00_0x0F. 0 0 NotFiltered Transactions with these IDs are passed on to ATB master port 1. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID1_10_1F Enable or disable ID filtering for IDs 0x10_0x1F. 1 1 NotFiltered Transactions with these IDs are passed on to ATB master port 1. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID1_20_2F Enable or disable ID filtering for IDs 0x20_0x2F. 2 2 NotFiltered Transactions with these IDs are passed on to ATB master port 1. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID1_30_3F Enable or disable ID filtering for IDs 0x30_0x3F. 3 3 NotFiltered Transactions with these IDs are passed on to ATB master port 1. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID1_40_4F Enable or disable ID filtering for IDs 0x40_0x4F. 4 4 NotFiltered Transactions with these IDs are passed on to ATB master port 1. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID1_50_5F Enable or disable ID filtering for IDs 0x50_0x5F. 5 5 NotFiltered Transactions with these IDs are passed on to ATB master port 1. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID1_60_6F Enable or disable ID filtering for IDs 0x60_0x6F. 6 6 NotFiltered Transactions with these IDs are passed on to ATB master port 1. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ID1_70_7F Enable or disable ID filtering for IDs 0x70_0x7F. 7 7 NotFiltered Transactions with these IDs are passed on to ATB master port 1. 0x0 Selected Transactions with these IDs are discarded by the replicator. 0x1 ITATBCTR1 The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode. 0xEF8 read-write 0x00000000 0x20 ATREADYM0 Reads the value of the atreadym0 input. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATREADYM1 Reads the value of the atreadym1 input. 1 1 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATVALIDS Reads the value of the atvalids input. 3 3 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITATBCTR0 The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode. 0xEFC read-write 0x00000000 0x20 ATVALIDM0 Sets the value of the atvalidm0 output. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATVALIDM1 Sets the value of the atvalidm1 output. 2 2 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATREADYS Sets the value of the atreadys output. 3 3 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITCTRL The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. 0xF00 read-write 0x00000000 0x20 IME Integration Mode Enable. 0 0 Disabled Integration mode disabled. 0x0 Enabled Integration mode enabled. 0x1 CLAIMSET Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. 0xFA0 read-write 0x00000000 0x20 BIT_0 Set claim bit 0 and check if bit is implemented or not. 0 0 read NotImplemented Claim bit 0 is not implemented. 0x0 Implemented Claim bit 0 is implemented. 0x1 write Set Set claim bit 0. 0x1 BIT_1 Set claim bit 1 and check if bit is implemented or not. 1 1 read NotImplemented Claim bit 1 is not implemented. 0x0 Implemented Claim bit 1 is implemented. 0x1 write Set Set claim bit 1. 0x1 BIT_2 Set claim bit 2 and check if bit is implemented or not. 2 2 read NotImplemented Claim bit 2 is not implemented. 0x0 Implemented Claim bit 2 is implemented. 0x1 write Set Set claim bit 2. 0x1 BIT_3 Set claim bit 3 and check if bit is implemented or not. 3 3 read NotImplemented Claim bit 3 is not implemented. 0x0 Implemented Claim bit 3 is implemented. 0x1 write Set Set claim bit 3. 0x1 CLAIMCLR Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. 0xFA4 read-write 0x00000000 0x20 BIT_0 Read or clear claim bit 0. 0 0 read Cleared Claim bit 0 is not set. 0x0 Set Claim bit 0 is set. 0x1 write Clear Clear claim bit 0. 0x1 BIT_1 Read or clear claim bit 1. 1 1 read Cleared Claim bit 1 is not set. 0x0 Set Claim bit 1 is set. 0x1 write Clear Clear claim bit 1. 0x1 BIT_2 Read or clear claim bit 2. 2 2 read Cleared Claim bit 2 is not set. 0x0 Set Claim bit 2 is set. 0x1 write Clear Clear claim bit 2. 0x1 BIT_3 Read or clear claim bit 3. 3 3 read Cleared Claim bit 3 is not set. 0x0 Set Claim bit 3 is set. 0x1 write Clear Clear claim bit 3. 0x1 LAR This is used to enable write access to device registers. 0xFB0 read-write 0x00000000 0x20 ACCESS A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. 0 31 UnLock Unlock register interface. 0xC5ACCE55 LSR This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register. 0xFB4 read-write 0x00000000 0x20 PRESENT Indicates that a lock control mechanism exists for this device. 0 0 NotImplemented No lock control mechanism exists, writes to the Lock Access Register are ignored. 0x0 Implemented Lock control mechanism is present. 0x1 LOCKED Returns the current status of the Lock. 1 1 UnLocked Write access is allowed to this device. 0x0 Locked Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. 0x1 TYPE Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. 2 2 Bits32 This component implements a 32-bit Lock Access Register. 0x0 Bits8 This component implements an 8-bit Lock Access Register. 0x1 AUTHSTATUS Indicates the current level of tracing permitted by the system 0xFB8 read-write 0x00000000 0x20 NSID Non-secure Invasive Debug 0 1 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 NSNID Non-secure Non-Invasive Debug 2 3 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 SID Secure Invasive Debug 4 5 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 SNID Secure Non-Invasive Debug 6 7 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 DEVID Indicates the capabilities of the component. 0xFC8 read-only 0x00000000 0x20 PORTNUM Indicates the number of master ports implemented. 0 3 DEVTYPE The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. 0xFCC read-only 0x00000000 0x20 MAJOR The main type of the component 0 3 InputOutputDevice Indicates that this component has ATB inputs and outputs. 0x2 SUB The sub-type of the component 4 7 Replicator Indicates that this component replicates trace from a single source to multiple targets. 0x2 PIDR4 Coresight peripheral identification registers. 0xFD0 read-write 0x00000000 0x20 PIDR_0 Coresight peripheral identification registers. 0xFE0 read-write 0x00000000 0x20 PIDR_1 Coresight peripheral identification registers. 0xFE4 read-write 0x00000000 0x20 PIDR_2 Coresight peripheral identification registers. 0xFE8 read-write 0x00000000 0x20 PIDR_3 Coresight peripheral identification registers. 0xFEC read-write 0x00000000 0x20 CIDR_0 Coresight component identification registers. 0xFF0 read-write 0x00000000 0x20 CIDR_1 Coresight component identification registers. 0xFF4 read-write 0x00000000 0x20 CIDR_2 Coresight component identification registers. 0xFF8 read-write 0x00000000 0x20 CIDR_3 Coresight component identification registers. 0xFFC read-write 0x00000000 0x20 GLOBAL_ATBREPLICATOR211_NS ATB Replicator module 1 0xBF049000 GLOBAL_ATBREPLICATOR212_NS ATB Replicator module 2 0xBF04A000 GLOBAL_ATBREPLICATOR213_NS ATB Replicator module 3 0xBF04B000 GLOBAL_ATBFUNNEL210_NS ATB funnel module 0 0xBF04C000 ATBFUNNEL 0 0x1000 registers ATBFUNNEL 0x20 CTRLREG The IDFILTER0 register enables the programming of ID filtering for master port 0. 0x000 read-write 0x00000000 0x20 ENS_0 Enable slave port 0. 0 0 Disabled Slave port disabled. This excludes the port from the priority selection scheme. 0x0 Enabled Slave port enabled. 0x1 ENS_1 Enable slave port 1. 1 1 Disabled Slave port disabled. This excludes the port from the priority selection scheme. 0x0 Enabled Slave port enabled. 0x1 ENS_2 Enable slave port 2. 2 2 Disabled Slave port disabled. This excludes the port from the priority selection scheme. 0x0 Enabled Slave port enabled. 0x1 ENS_3 Enable slave port 3. 3 3 Disabled Slave port disabled. This excludes the port from the priority selection scheme. 0x0 Enabled Slave port enabled. 0x1 ENS_4 Enable slave port 4. 4 4 Disabled Slave port disabled. This excludes the port from the priority selection scheme. 0x0 Enabled Slave port enabled. 0x1 ENS_5 Enable slave port 5. 5 5 Disabled Slave port disabled. This excludes the port from the priority selection scheme. 0x0 Enabled Slave port enabled. 0x1 ENS_6 Enable slave port 6. 6 6 Disabled Slave port disabled. This excludes the port from the priority selection scheme. 0x0 Enabled Slave port enabled. 0x1 ENS_7 Enable slave port 7. 7 7 Disabled Slave port disabled. This excludes the port from the priority selection scheme. 0x0 Enabled Slave port enabled. 0x1 HT Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this setting to minimize switching. When a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. The ATB funnel holds for the minimum hold time and one additional transaction. The actual hold time is the register value plus 1. The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. 8 11 PRIORITYCTRLREG The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is a priority for each particular slave interface. 0x004 read-write 0x00000000 0x20 PRIPORT0 Priority value of port number 0. 0 2 PRIPORT1 Priority value of port number 1. 3 5 PRIPORT2 Priority value of port number 2. 6 8 PRIPORT3 Priority value of port number 3. 9 11 PRIPORT4 Priority value of port number 4. 12 14 PRIPORT5 Priority value of port number 5. 15 17 PRIPORT6 Priority value of port number 6. 18 20 PRIPORT7 Priority value of port number 7. 21 23 ITATBDATA0 The ITATBDATA0 register performs different functions depending on whether the access is a read or a write. 0xEEC read-write 0x00000000 0x20 ATDATA_0 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_1 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 1 1 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_2 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 2 2 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_3 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 3 3 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_4 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 4 4 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_5 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 5 5 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_6 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 6 6 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_7 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 7 7 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_8 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 8 8 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_9 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 9 9 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_10 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 10 10 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_11 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 11 11 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_12 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 12 12 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_13 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 13 13 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_14 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 14 14 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_15 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 15 15 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATDATA_16 A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. 16 16 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITATBCTR2 The ITATBCTR2 register performs different functions depending on whether the access is a read or a write. 0xEF0 read-write 0x00000000 0x20 ATREADY A read access returns the value of atreadym. A write access outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 AFVALID A read access returns the value of afvalidm. A write access outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n. 1 1 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITATBCTR1 The ITATBCTR1 register performs different functions depending on whether the access is a read or a write. 0xEF4 read-write 0x00000000 0x20 ATVALIDM0 A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000 defines n. A write outputs the value to the atidm port. 0 6 Low Pin is logic 0. 0x00 High Pin is logic 1. 0x01 ITATBCTR0 The ITATBCTR0 register performs different functions depending on whether the access is a read or a write. 0xEF8 read-write 0x00000000 0x20 ATVALID A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n. A write outputs the value to atvalidm. 0 0 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 AFREADY A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. A write outputs the value to afreadym. 2 2 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ATBYTES A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. A write outputs the value to atbytesm. 8 9 Low Pin is logic 0. 0x0 High Pin is logic 1. 0x1 ITCTRL The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. 0xF00 read-write 0x00000000 0x20 IME Integration Mode Enable. 0 0 Disabled Integration mode disabled. 0x0 Enabled Integration mode enabled. 0x1 CLAIMSET Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. 0xFA0 read-write 0x00000000 0x20 BIT_0 Set claim bit 0 and check if bit is implemented or not. 0 0 read NotImplemented Claim bit 0 is not implemented. 0x0 Implemented Claim bit 0 is implemented. 0x1 write Set Set claim bit 0. 0x1 BIT_1 Set claim bit 1 and check if bit is implemented or not. 1 1 read NotImplemented Claim bit 1 is not implemented. 0x0 Implemented Claim bit 1 is implemented. 0x1 write Set Set claim bit 1. 0x1 BIT_2 Set claim bit 2 and check if bit is implemented or not. 2 2 read NotImplemented Claim bit 2 is not implemented. 0x0 Implemented Claim bit 2 is implemented. 0x1 write Set Set claim bit 2. 0x1 BIT_3 Set claim bit 3 and check if bit is implemented or not. 3 3 read NotImplemented Claim bit 3 is not implemented. 0x0 Implemented Claim bit 3 is implemented. 0x1 write Set Set claim bit 3. 0x1 CLAIMCLR Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. 0xFA4 read-write 0x00000000 0x20 BIT_0 Read or clear claim bit 0. 0 0 read Cleared Claim bit 0 is not set. 0x0 Set Claim bit 0 is set. 0x1 write Clear Clear claim bit 0. 0x1 BIT_1 Read or clear claim bit 1. 1 1 read Cleared Claim bit 1 is not set. 0x0 Set Claim bit 1 is set. 0x1 write Clear Clear claim bit 1. 0x1 BIT_2 Read or clear claim bit 2. 2 2 read Cleared Claim bit 2 is not set. 0x0 Set Claim bit 2 is set. 0x1 write Clear Clear claim bit 2. 0x1 BIT_3 Read or clear claim bit 3. 3 3 read Cleared Claim bit 3 is not set. 0x0 Set Claim bit 3 is set. 0x1 write Clear Clear claim bit 3. 0x1 LAR This is used to enable write access to device registers. 0xFB0 read-write 0x00000000 0x20 ACCESS A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. 0 31 UnLock Unlock register interface. 0xC5ACCE55 LSR This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register. 0xFB4 read-write 0x00000000 0x20 PRESENT Indicates that a lock control mechanism exists for this device. 0 0 NotImplemented No lock control mechanism exists, writes to the Lock Access Register are ignored. 0x0 Implemented Lock control mechanism is present. 0x1 LOCKED Returns the current status of the Lock. 1 1 UnLocked Write access is allowed to this device. 0x0 Locked Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. 0x1 TYPE Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. 2 2 Bits32 This component implements a 32-bit Lock Access Register. 0x0 Bits8 This component implements an 8-bit Lock Access Register. 0x1 AUTHSTATUS Indicates the current level of tracing permitted by the system 0xFB8 read-write 0x00000000 0x20 NSID Non-secure Invasive Debug 0 1 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 NSNID Non-secure Non-Invasive Debug 2 3 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 SID Secure Invasive Debug 4 5 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 SNID Secure Non-Invasive Debug 6 7 NotImplemented The feature is not implemented. 0x0 Implemented The feature is implemented. 0x1 DEVID Indicates the capabilities of the component. 0xFC8 read-only 0x00000000 0x20 PORTCOUNT Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. 0 3 DEVTYPE The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. 0xFCC read-only 0x00000000 0x20 MAJOR The main type of the component 0 3 InputOutputDevice Indicates that this component has ATB inputs and outputs. 0x2 SUB The sub-type of the component 4 7 Replicator This component arbitrates ATB inputs mapping to ATB outputs. 0x1 PIDR4 Coresight peripheral identification registers. 0xFD0 read-write 0x00000000 0x20 PIDR_0 Coresight peripheral identification registers. 0xFE0 read-write 0x00000000 0x20 PIDR_1 Coresight peripheral identification registers. 0xFE4 read-write 0x00000000 0x20 PIDR_2 Coresight peripheral identification registers. 0xFE8 read-write 0x00000000 0x20 PIDR_3 Coresight peripheral identification registers. 0xFEC read-write 0x00000000 0x20 CIDR_0 Coresight component identification registers. 0xFF0 read-write 0x00000000 0x20 CIDR_1 Coresight component identification registers. 0xFF4 read-write 0x00000000 0x20 CIDR_2 Coresight component identification registers. 0xFF8 read-write 0x00000000 0x20 CIDR_3 Coresight component identification registers. 0xFFC read-write 0x00000000 0x20 GLOBAL_ATBFUNNEL211_NS ATB funnel module 1 0xBF04D000 GLOBAL_ATBFUNNEL212_NS ATB funnel module 2 0xBF04E000 GLOBAL_ATBFUNNEL213_NS ATB funnel module 3 0xBF04F000 VPRCLIC_NS VPR CLIC registers 0 0x4F8D5000 CLIC 0 0x3000 registers VPRCLIC_0 0 VPRCLIC_1 1 VPRCLIC_2 2 VPRCLIC_3 3 VPRCLIC_4 4 VPRCLIC_5 5 VPRCLIC_6 6 VPRCLIC_7 7 VPRCLIC_8 8 VPRCLIC_9 9 VPRCLIC_10 10 VPRCLIC_11 11 VPRCLIC_12 12 VPRCLIC_13 13 VPRCLIC_14 14 VPRCLIC_15 15 VPRCLIC_16 16 VPRCLIC_17 17 VPRCLIC_18 18 VPRCLIC_19 19 VPRCLIC_20 20 VPRCLIC_21 21 VPRCLIC_22 22 VPRCLIC_23 23 VPRCLIC_24 24 VPRCLIC_25 25 VPRCLIC_26 26 VPRCLIC_27 27 VPRCLIC_28 28 VPRCLIC_29 29 VPRCLIC_30 30 VPRCLIC_31 31 CLIC 0x20 CLIC Unspecified CLIC_CLIC read-write 0x000 CLICCFG CLIC configuration. 0x0000 read-only 0x00000005 0x20 NVBITS Selective interrupt hardware vectoring. 0 0 Implemented Selective interrupt hardware vectoring is implemented 0x1 NLBITS Interrupt level encoding. 1 4 Two 2 bits = 3 interrupt levels 0x2 NMBITS Interrupt privilege mode. 5 6 ModeM All interrupts are M-mode only 0x0 CLICINFO CLIC information. 0x0004 read-only 0x00001FFF 0x20 NUMINTERRUPTS Maximum number of interrupts supported. 0 12 VERSION Version 13 20 NUMTRIGGER Number of maximum interrupt triggers supported 25 30 0x1E0 0x4 CLICINT[%s] Description collection: Interrupt control register for IRQ number [n]. 0x1000 read-write 0x3FC3FEFE 0x20 IP Interrupt Pending bit. 0 0 NotPending Interrupt not pending 0x0 Pending Interrupt pending 0x1 READ1 Read as 1, write ignored. 1 7 read-only IE Interrupt enable bit. 8 8 Disabled Interrupt disabled 0x0 Enabled Interrupt enabled 0x1 READ2 Read as 1, write ignored. 9 15 read-only SHV Selective Hardware Vectoring. 16 16 read-only Vectored Hardware vectored 0x1 TRIG Trigger type and polarity for each interrupt input. 17 18 read-only EdgeTriggered Interrupts are edge-triggered 0x1 MODE Privilege mode. 22 23 read-only MachineMode Machine mode 0x3 PRIORITY Interrupt priority level 24 31 PRIOLEVEL0 Priority level 0 0x3F PRIOLEVEL1 Priority level 1 0x7F PRIOLEVEL2 Priority level 2 0xBF PRIOLEVEL3 Priority level 3 0xFF VPRCLIC_S VPR CLIC registers 1 0x5F8D5000 VPRCLIC_0 0 VPRCLIC_1 1 VPRCLIC_2 2 VPRCLIC_3 3 VPRCLIC_4 4 VPRCLIC_5 5 VPRCLIC_6 6 VPRCLIC_7 7 VPRCLIC_8 8 VPRCLIC_9 9 VPRCLIC_10 10 VPRCLIC_11 11 VPRCLIC_12 12 VPRCLIC_13 13 VPRCLIC_14 14 VPRCLIC_15 15 VPRCLIC_16 16 VPRCLIC_17 17 VPRCLIC_18 18 VPRCLIC_19 19 VPRCLIC_20 20 VPRCLIC_21 21 VPRCLIC_22 22 VPRCLIC_23 23 VPRCLIC_24 24 VPRCLIC_25 25 VPRCLIC_26 26 VPRCLIC_27 27 VPRCLIC_28 28 VPRCLIC_29 29 VPRCLIC_30 30 VPRCLIC_31 31 VPRTIM_NS VTIM CSR registers 0x00000000 0 0x1000 registers VPRTIM 32 VTIM 0x20 UNUSED Unused. 0x000 0x00000000 read-only GLOBAL_GPIOTE130_NS GPIO Tasks and Events 0 0x4F934000 GPIOTE 0 0x1000 registers GPIOTE130_0 104 GPIOTE130_1 105 GPIOTE 0x20 0x8 0x4 TASKS_OUT[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0x000 write-only 0x00000000 0x20 TASKS_OUT Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0 0 Trigger Trigger task 0x1 0x8 0x4 TASKS_SET[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0x030 write-only 0x00000000 0x20 TASKS_SET Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0 0 Trigger Trigger task 0x1 0x8 0x4 TASKS_CLR[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0x060 write-only 0x00000000 0x20 TASKS_CLR Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0 0 Trigger Trigger task 0x1 0x8 0x4 SUBSCRIBE_OUT[%s] Description collection: Subscribe configuration for task OUT[n] 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task OUT[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x8 0x4 SUBSCRIBE_SET[%s] Description collection: Subscribe configuration for task SET[n] 0x0B0 read-write 0x00000000 0x20 CHIDX DPPI channel that task SET[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x8 0x4 SUBSCRIBE_CLR[%s] Description collection: Subscribe configuration for task CLR[n] 0x0E0 read-write 0x00000000 0x20 CHIDX DPPI channel that task CLR[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x8 0x4 EVENTS_IN[%s] Description collection: Event from pin specified in CONFIG[n].PSEL 0x100 read-write 0x00000000 0x20 EVENTS_IN Event from pin specified in CONFIG[n].PSEL 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 4 0x008 EVENTS_PORT[%s] Peripheral events. GLOBAL_GPIOTE_EVENTS_PORT read-write 0x140 NONSECURE Description cluster: Non-secure port event from owner n 0x000 read-write 0x00000000 0x20 NONSECURE Non-secure port event from owner n 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SECURE Description cluster: Secure port event from owner n 0x004 read-write 0x00000000 0x20 SECURE Secure port event from owner n 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x8 0x4 PUBLISH_IN[%s] Description collection: Publish configuration for event IN[n] 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event IN[n] will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 4 0x008 PUBLISH_PORT[%s] Publish configuration for events GLOBAL_GPIOTE_PUBLISH_PORT read-write 0x1C0 NONSECURE Description cluster: Publish configuration for event PORT[n].NONSECURE 0x000 read-write 0x00000000 0x20 CHIDX DPPI channel that event PORT[n].NONSECURE will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SECURE Description cluster: Publish configuration for event PORT[n].SECURE 0x004 read-write 0x00000000 0x20 CHIDX DPPI channel that event PORT[n].SECURE will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 INTENSET0 Enable interrupt 0x304 read-write 0x00000000 0x20 IN0 Write '1' to enable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN1 Write '1' to enable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN2 Write '1' to enable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN3 Write '1' to enable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN4 Write '1' to enable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN5 Write '1' to enable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN6 Write '1' to enable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN7 Write '1' to enable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT0NONSECURE Write '1' to enable interrupt for event PORT0NONSECURE 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT0SECURE Write '1' to enable interrupt for event PORT0SECURE 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT1NONSECURE Write '1' to enable interrupt for event PORT1NONSECURE 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT1SECURE Write '1' to enable interrupt for event PORT1SECURE 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT2NONSECURE Write '1' to enable interrupt for event PORT2NONSECURE 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT2SECURE Write '1' to enable interrupt for event PORT2SECURE 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT3NONSECURE Write '1' to enable interrupt for event PORT3NONSECURE 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT3SECURE Write '1' to enable interrupt for event PORT3SECURE 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR0 Disable interrupt 0x308 read-write 0x00000000 0x20 IN0 Write '1' to disable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN1 Write '1' to disable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN2 Write '1' to disable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN3 Write '1' to disable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN4 Write '1' to disable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN5 Write '1' to disable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN6 Write '1' to disable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN7 Write '1' to disable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT0NONSECURE Write '1' to disable interrupt for event PORT0NONSECURE 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT0SECURE Write '1' to disable interrupt for event PORT0SECURE 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT1NONSECURE Write '1' to disable interrupt for event PORT1NONSECURE 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT1SECURE Write '1' to disable interrupt for event PORT1SECURE 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT2NONSECURE Write '1' to disable interrupt for event PORT2NONSECURE 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT2SECURE Write '1' to disable interrupt for event PORT2SECURE 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT3NONSECURE Write '1' to disable interrupt for event PORT3NONSECURE 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT3SECURE Write '1' to disable interrupt for event PORT3SECURE 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTENSET1 Enable interrupt 0x314 read-write 0x00000000 0x20 IN0 Write '1' to enable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN1 Write '1' to enable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN2 Write '1' to enable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN3 Write '1' to enable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN4 Write '1' to enable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN5 Write '1' to enable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN6 Write '1' to enable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 IN7 Write '1' to enable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT0NONSECURE Write '1' to enable interrupt for event PORT0NONSECURE 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT0SECURE Write '1' to enable interrupt for event PORT0SECURE 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT1NONSECURE Write '1' to enable interrupt for event PORT1NONSECURE 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT1SECURE Write '1' to enable interrupt for event PORT1SECURE 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT2NONSECURE Write '1' to enable interrupt for event PORT2NONSECURE 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT2SECURE Write '1' to enable interrupt for event PORT2SECURE 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT3NONSECURE Write '1' to enable interrupt for event PORT3NONSECURE 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PORT3SECURE Write '1' to enable interrupt for event PORT3SECURE 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR1 Disable interrupt 0x318 read-write 0x00000000 0x20 IN0 Write '1' to disable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN1 Write '1' to disable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN2 Write '1' to disable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN3 Write '1' to disable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN4 Write '1' to disable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN5 Write '1' to disable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN6 Write '1' to disable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 IN7 Write '1' to disable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT0NONSECURE Write '1' to disable interrupt for event PORT0NONSECURE 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT0SECURE Write '1' to disable interrupt for event PORT0SECURE 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT1NONSECURE Write '1' to disable interrupt for event PORT1NONSECURE 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT1SECURE Write '1' to disable interrupt for event PORT1SECURE 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT2NONSECURE Write '1' to disable interrupt for event PORT2NONSECURE 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT2SECURE Write '1' to disable interrupt for event PORT2SECURE 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT3NONSECURE Write '1' to disable interrupt for event PORT3NONSECURE 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PORT3SECURE Write '1' to disable interrupt for event PORT3SECURE 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 LATENCY Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. 0x504 read-write 0x00000001 0x20 LATENCY Latency setting 0 0 LowPower Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section 0x0 LowLatency Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section 0x1 0x8 0x4 CONFIG[%s] Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event 0x510 read-write 0x00000000 0x20 MODE Mode 0 1 Disabled Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. 0x0 Event Event mode 0x1 Task Task mode 0x3 PSEL GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event 4 8 PORT Port number 9 12 POLARITY When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. 16 17 None Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. 0x0 LoToHi Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. 0x1 HiToLo Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. 0x2 Toggle Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. 0x3 OUTINIT When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. 20 20 Low Task mode: Initial value of pin before task triggering is low 0x0 High Task mode: Initial value of pin before task triggering is high 0x1 GLOBAL_GPIOTE130_S GPIO Tasks and Events 1 0x5F934000 GPIOTE130_0 104 GPIOTE130_1 105 GLOBAL_GRTC_NS Global Real-time counter 0 0x4F99C000 GRTC 0 0x1000 registers GRTC_0 108 GRTC_1 109 GRTC 0x20 0x10 0x4 TASKS_CAPTURE[%s] Description collection: Capture the counter value to CC[n] register 0x000 write-only 0x00000000 0x20 TASKS_CAPTURE Capture the counter value to CC[n] register 0 0 Trigger Trigger task 0x1 0x10 0x4 SUBSCRIBE_CAPTURE[%s] Description collection: Subscribe configuration for task CAPTURE[n] 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task CAPTURE[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x10 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x100 read-write 0x00000000 0x20 EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SYSCOUNTERVALID The SYSCOUNTER is in active state and value is valid 0x168 read-write 0x00000000 0x20 EVENTS_SYSCOUNTERVALID The SYSCOUNTER is in active state and value is valid 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x10 0x4 PUBLISH_COMPARE[%s] Description collection: Publish configuration for event COMPARE[n] 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event COMPARE[n] will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 INTEN0 Enable or disable interrupt 0x300 read-write 0x00000000 0x20 COMPARE0 Enable or disable interrupt for event COMPARE[0] 0 0 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE1 Enable or disable interrupt for event COMPARE[1] 1 1 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE2 Enable or disable interrupt for event COMPARE[2] 2 2 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE3 Enable or disable interrupt for event COMPARE[3] 3 3 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE4 Enable or disable interrupt for event COMPARE[4] 4 4 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE5 Enable or disable interrupt for event COMPARE[5] 5 5 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE6 Enable or disable interrupt for event COMPARE[6] 6 6 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE7 Enable or disable interrupt for event COMPARE[7] 7 7 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE8 Enable or disable interrupt for event COMPARE[8] 8 8 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE9 Enable or disable interrupt for event COMPARE[9] 9 9 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE10 Enable or disable interrupt for event COMPARE[10] 10 10 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE11 Enable or disable interrupt for event COMPARE[11] 11 11 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE12 Enable or disable interrupt for event COMPARE[12] 12 12 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE13 Enable or disable interrupt for event COMPARE[13] 13 13 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE14 Enable or disable interrupt for event COMPARE[14] 14 14 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE15 Enable or disable interrupt for event COMPARE[15] 15 15 Disabled Disable 0x0 Enabled Enable 0x1 SYSCOUNTERVALID Enable or disable interrupt for event SYSCOUNTERVALID 26 26 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET0 Enable interrupt 0x304 read-write 0x00000000 0x20 COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE4 Write '1' to enable interrupt for event COMPARE[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE5 Write '1' to enable interrupt for event COMPARE[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE6 Write '1' to enable interrupt for event COMPARE[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE7 Write '1' to enable interrupt for event COMPARE[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE8 Write '1' to enable interrupt for event COMPARE[8] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE9 Write '1' to enable interrupt for event COMPARE[9] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE10 Write '1' to enable interrupt for event COMPARE[10] 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE11 Write '1' to enable interrupt for event COMPARE[11] 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE12 Write '1' to enable interrupt for event COMPARE[12] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE13 Write '1' to enable interrupt for event COMPARE[13] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE14 Write '1' to enable interrupt for event COMPARE[14] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE15 Write '1' to enable interrupt for event COMPARE[15] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SYSCOUNTERVALID Write '1' to enable interrupt for event SYSCOUNTERVALID 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR0 Disable interrupt 0x308 read-write 0x00000000 0x20 COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE4 Write '1' to disable interrupt for event COMPARE[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE5 Write '1' to disable interrupt for event COMPARE[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE6 Write '1' to disable interrupt for event COMPARE[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE7 Write '1' to disable interrupt for event COMPARE[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE8 Write '1' to disable interrupt for event COMPARE[8] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE9 Write '1' to disable interrupt for event COMPARE[9] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE10 Write '1' to disable interrupt for event COMPARE[10] 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE11 Write '1' to disable interrupt for event COMPARE[11] 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE12 Write '1' to disable interrupt for event COMPARE[12] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE13 Write '1' to disable interrupt for event COMPARE[13] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE14 Write '1' to disable interrupt for event COMPARE[14] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE15 Write '1' to disable interrupt for event COMPARE[15] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SYSCOUNTERVALID Write '1' to disable interrupt for event SYSCOUNTERVALID 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND0 Pending interrupts 0x30C read-only 0x00000000 0x20 COMPARE0 Read pending status of interrupt for event COMPARE[0] 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE1 Read pending status of interrupt for event COMPARE[1] 1 1 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE2 Read pending status of interrupt for event COMPARE[2] 2 2 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE3 Read pending status of interrupt for event COMPARE[3] 3 3 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE4 Read pending status of interrupt for event COMPARE[4] 4 4 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE5 Read pending status of interrupt for event COMPARE[5] 5 5 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE6 Read pending status of interrupt for event COMPARE[6] 6 6 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE7 Read pending status of interrupt for event COMPARE[7] 7 7 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE8 Read pending status of interrupt for event COMPARE[8] 8 8 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE9 Read pending status of interrupt for event COMPARE[9] 9 9 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE10 Read pending status of interrupt for event COMPARE[10] 10 10 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE11 Read pending status of interrupt for event COMPARE[11] 11 11 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE12 Read pending status of interrupt for event COMPARE[12] 12 12 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE13 Read pending status of interrupt for event COMPARE[13] 13 13 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE14 Read pending status of interrupt for event COMPARE[14] 14 14 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE15 Read pending status of interrupt for event COMPARE[15] 15 15 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 SYSCOUNTERVALID Read pending status of interrupt for event SYSCOUNTERVALID 26 26 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 INTEN1 Enable or disable interrupt 0x310 read-write 0x00000000 0x20 COMPARE0 Enable or disable interrupt for event COMPARE[0] 0 0 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE1 Enable or disable interrupt for event COMPARE[1] 1 1 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE2 Enable or disable interrupt for event COMPARE[2] 2 2 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE3 Enable or disable interrupt for event COMPARE[3] 3 3 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE4 Enable or disable interrupt for event COMPARE[4] 4 4 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE5 Enable or disable interrupt for event COMPARE[5] 5 5 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE6 Enable or disable interrupt for event COMPARE[6] 6 6 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE7 Enable or disable interrupt for event COMPARE[7] 7 7 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE8 Enable or disable interrupt for event COMPARE[8] 8 8 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE9 Enable or disable interrupt for event COMPARE[9] 9 9 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE10 Enable or disable interrupt for event COMPARE[10] 10 10 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE11 Enable or disable interrupt for event COMPARE[11] 11 11 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE12 Enable or disable interrupt for event COMPARE[12] 12 12 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE13 Enable or disable interrupt for event COMPARE[13] 13 13 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE14 Enable or disable interrupt for event COMPARE[14] 14 14 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE15 Enable or disable interrupt for event COMPARE[15] 15 15 Disabled Disable 0x0 Enabled Enable 0x1 SYSCOUNTERVALID Enable or disable interrupt for event SYSCOUNTERVALID 26 26 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET1 Enable interrupt 0x314 read-write 0x00000000 0x20 COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE4 Write '1' to enable interrupt for event COMPARE[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE5 Write '1' to enable interrupt for event COMPARE[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE6 Write '1' to enable interrupt for event COMPARE[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE7 Write '1' to enable interrupt for event COMPARE[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE8 Write '1' to enable interrupt for event COMPARE[8] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE9 Write '1' to enable interrupt for event COMPARE[9] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE10 Write '1' to enable interrupt for event COMPARE[10] 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE11 Write '1' to enable interrupt for event COMPARE[11] 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE12 Write '1' to enable interrupt for event COMPARE[12] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE13 Write '1' to enable interrupt for event COMPARE[13] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE14 Write '1' to enable interrupt for event COMPARE[14] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE15 Write '1' to enable interrupt for event COMPARE[15] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SYSCOUNTERVALID Write '1' to enable interrupt for event SYSCOUNTERVALID 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR1 Disable interrupt 0x318 read-write 0x00000000 0x20 COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE4 Write '1' to disable interrupt for event COMPARE[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE5 Write '1' to disable interrupt for event COMPARE[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE6 Write '1' to disable interrupt for event COMPARE[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE7 Write '1' to disable interrupt for event COMPARE[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE8 Write '1' to disable interrupt for event COMPARE[8] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE9 Write '1' to disable interrupt for event COMPARE[9] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE10 Write '1' to disable interrupt for event COMPARE[10] 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE11 Write '1' to disable interrupt for event COMPARE[11] 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE12 Write '1' to disable interrupt for event COMPARE[12] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE13 Write '1' to disable interrupt for event COMPARE[13] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE14 Write '1' to disable interrupt for event COMPARE[14] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE15 Write '1' to disable interrupt for event COMPARE[15] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SYSCOUNTERVALID Write '1' to disable interrupt for event SYSCOUNTERVALID 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND1 Pending interrupts 0x31C read-only 0x00000000 0x20 COMPARE0 Read pending status of interrupt for event COMPARE[0] 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE1 Read pending status of interrupt for event COMPARE[1] 1 1 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE2 Read pending status of interrupt for event COMPARE[2] 2 2 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE3 Read pending status of interrupt for event COMPARE[3] 3 3 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE4 Read pending status of interrupt for event COMPARE[4] 4 4 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE5 Read pending status of interrupt for event COMPARE[5] 5 5 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE6 Read pending status of interrupt for event COMPARE[6] 6 6 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE7 Read pending status of interrupt for event COMPARE[7] 7 7 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE8 Read pending status of interrupt for event COMPARE[8] 8 8 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE9 Read pending status of interrupt for event COMPARE[9] 9 9 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE10 Read pending status of interrupt for event COMPARE[10] 10 10 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE11 Read pending status of interrupt for event COMPARE[11] 11 11 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE12 Read pending status of interrupt for event COMPARE[12] 12 12 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE13 Read pending status of interrupt for event COMPARE[13] 13 13 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE14 Read pending status of interrupt for event COMPARE[14] 14 14 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 COMPARE15 Read pending status of interrupt for event COMPARE[15] 15 15 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 SYSCOUNTERVALID Read pending status of interrupt for event SYSCOUNTERVALID 26 26 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 MODE Counter mode selection 0x510 read-write 0x00000000 0x20 AUTOEN Automatic enable to keep the SYSCOUNTER active. 0 0 Default Default configuration to keep the SYSCOUNTER active. 0x0 CpuActive In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER active. 0x1 SYSCOUNTEREN Enable the SYSCOUNTER 1 1 Disabled SYSCOUNTER disabled 0x0 Enabled SYSCOUNTER enabled 0x1 SYSCOUNTERL The lower 32-bits of the SYSCOUNTER 0x514 read-only 0x00000000 0x20 VALUE The lower 32-bits of the SYSCOUNTER value. 0 31 SYSCOUNTERH The higher 20-bits of the SYSCOUNTER 0x518 read-only 0x00000000 0x20 VALUE The higher 20-bits of the SYSCOUNTER value. 0 19 OVERFLOW The SYSCOUNTERL overflow indication after reading it. 31 31 NoOverflow SYSCOUNTERL is not overflown 0x0 Overflow SYSCOUNTERL overflown 0x1 16 0x010 CC[%s] Unspecified GLOBAL_GRTC_CC read-write 0x520 CCL Description cluster: The lower 32-bits of Capture/Compare register CC[n] 0x000 read-write 0x00000000 0x20 CCL Capture/Compare low value in 1 us 0 31 CCH Description cluster: The higher 32-bits of Capture/Compare register CC[n] 0x004 read-write 0x00000000 0x20 CCH Capture/Compare high value in 1 us 0 19 CCADD Description cluster: Count to add to CC[n] 0x008 read-write 0x00000000 0x20 VALUE Count to add to CC[n] 0 30 REFERENCE Configure the Capture/Compare register 31 31 SYSCOUNTER Adds SYSCOUNTER value. 0x0 CC Adds CC value. 0x1 CCEN Description cluster: Configure Capture/Compare register CC[n] 0x00C read-write 0x00000000 0x20 ACTIVE Configure the Capture/Compare register 0 0 Disable Capture/Compare register CC[n] Disabled. 0x0 Enable Capture/Compare register CC[n] enabled. 0x1 KEEPRUNNING Request to keep the SYSCOUNTER in the active state and prevent going to sleep 0x6A0 read-write 0x00000000 0x20 DOMAIN_0 Request from the Domain [0] 0 0 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_1 Request from the Domain [1] 1 1 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_2 Request from the Domain [2] 2 2 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_3 Request from the Domain [3] 3 3 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_4 Request from the Domain [4] 4 4 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_5 Request from the Domain [5] 5 5 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_6 Request from the Domain [6] 6 6 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_7 Request from the Domain [7] 7 7 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_8 Request from the Domain [8] 8 8 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_9 Request from the Domain [9] 9 9 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_10 Request from the Domain [10] 10 10 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_11 Request from the Domain [11] 11 11 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_12 Request from the Domain [12] 12 12 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_13 Request from the Domain [13] 13 13 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_14 Request from the Domain [14] 14 14 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 DOMAIN_15 Request from the Domain [15] 15 15 NotActive Allow SYSCOUNTER to go to sleep 0x0 Active Keep SYSCOUNTER active 0x1 TIMEOUT Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER 0x6A4 read-write 0x00000000 0x20 VALUE Number of 32Ki cycles 0 15 INTERVAL Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. 0x6A8 read-write 0x00000000 0x20 VALUE Count to add to CC[0] 0 15 GLOBAL_GRTC_S Global Real-time counter 1 0x5F99C000 GRTC_0 108 GRTC_1 109 GLOBAL_TBM_NS Trace buffer monitor 0 0xBF003000 TBM 0 0x1000 registers TBM 127 TBM 0x20 TASKS_START Start counter 0x000 write-only 0x00000000 0x20 TASKS_START Start counter 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop counter, clear counter value 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop counter, clear counter value 0 0 Trigger Trigger task 0x1 TASKS_FLUSH Stop counter, keep current counter value 0x008 write-only 0x00000000 0x20 TASKS_FLUSH Stop counter, keep current counter value 0 0 Trigger Trigger task 0x1 EVENTS_HALFFULL Counter value equals half-full 0x100 read-write 0x00000000 0x20 EVENTS_HALFFULL Counter value equals half-full 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_FULL Counter value equals full 0x104 read-write 0x00000000 0x20 EVENTS_FULL Counter value equals full 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_FLUSH Counter stopped due to flush 0x108 read-write 0x00000000 0x20 EVENTS_FLUSH Counter stopped due to flush 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 HALFFULL Enable or disable interrupt for event HALFFULL 0 0 Disabled Disable 0x0 Enabled Enable 0x1 FULL Enable or disable interrupt for event FULL 1 1 Disabled Disable 0x0 Enabled Enable 0x1 FLUSH Enable or disable interrupt for event FLUSH 2 2 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 HALFFULL Write '1' to enable interrupt for event HALFFULL 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 FULL Write '1' to enable interrupt for event FULL 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 FLUSH Write '1' to enable interrupt for event FLUSH 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 HALFFULL Write '1' to disable interrupt for event HALFFULL 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 FULL Write '1' to disable interrupt for event FULL 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 FLUSH Write '1' to disable interrupt for event FLUSH 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND Pending interrupts 0x30C read-only 0x00000000 0x20 HALFFULL Read pending status of interrupt for event HALFFULL 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 FULL Read pending status of interrupt for event FULL 1 1 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 FLUSH Read pending status of interrupt for event FLUSH 2 2 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 BUFFERSIZE System RAM trace buffer total size in bytes 0x400 read-write 0x000001FF 0x20 BUFFERSIZE Must only be configured in STOP mode. Must be multiple of 16 bytes to make half-buffer size always 64 bit word aligned. BUFFERSIZE LSB byte always fixed as 0xF to 16 bytes boundary. Minimum BUFFERSIZE value 0x00F i.e. 16 bytes, maximum value 0xFFF i.e. 4096 bytes. 0 11 Min 16 bytes 0x00F Max 4096 bytes 0xFFF COUNT Counter current value 0x404 read-only 0x00000000 0x20 COUNT Counter current value 0 11 GLOBAL_TBM_S Trace buffer monitor 1 0xBF003000 GLOBAL_TBM_NS TBM 127 GLOBAL_USBHS_NS USBHS 0 0x4F086000 USBHS 0 0x1000 registers USBHS 134 USBHS 0x20 TASKS_START Start the USB peripheral. 0x000 write-only 0x00000000 0x20 TASKS_START Start the USB peripheral. 0 0 Trigger Trigger task 0x1 EVENTS_CORE Event indicating that interrupt triggered at USBHS core 0x100 read-write 0x00000000 0x20 EVENTS_CORE Event indicating that interrupt triggered at USBHS core 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 CORE Enable or disable interrupt for event CORE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 CORE Write '1' to enable interrupt for event CORE 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 CORE Write '1' to disable interrupt for event CORE 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND Pending interrupts 0x30C read-only 0x00000000 0x20 CORE Read pending status of interrupt for event CORE 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ENABLE Enable USB peripheral. 0x400 read-write 0x00000000 0x20 CORE Enable USB Controller 0 0 Disabled USB Controller disabled. 0x0 Enabled USB Controller enabled. 0x1 PHY Enable USB PHY 1 1 Disabled USB PHY disabled. 0x0 Enabled USB PHY enabled. 0x1 GLOBAL_USBHS_S USBHS 1 0x5F086000 USBHS 134 GLOBAL_EXMIF_NS External Memory Interface 0 0x4F095000 EXMIF 0 0x1000 registers EXMIF 149 EXMIF 0x20 TASKS_START Start operation. 0x000 write-only 0x00000000 0x20 TASKS_START Start operation. 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop operation. 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop operation. 0 0 Trigger Trigger task 0x1 EVENTS_CORE Event indicating that interrupt triggered at EXMIF core 0x100 read-write 0x00000000 0x20 EVENTS_CORE Event indicating that interrupt triggered at EXMIF core 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 CORE Enable or disable interrupt for event CORE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 CORE Write '1' to enable interrupt for event CORE 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 CORE Write '1' to disable interrupt for event CORE 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND Pending interrupts 0x30C read-only 0x00000000 0x20 CORE Read pending status of interrupt for event CORE 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 EXTCONF1 Configuration for external memory device 1. EXTCONF1 read-write 0x400 OFFSET Address offset for external memory device 1. 0x0 read-write 0x00000000 0x20 OFFSET External memory Offset. 0 31 SIZE Upper address range for external memory device 1. 0x4 read-write 0x0FFFFFFF 0x20 SIZE Upper limit address. 0 31 ENABLE Enable or disable external memory access. 0x10 read-write 0x00000000 0x20 ENABLE Enable or disable external memory access from AXI interface. 0 0 Disabled Disable external memory. 0x0 Enabled Enable external memory. 0x1 EXTCONF2 Configuration for external memory device 2. EXTCONF2 EXTCONF1 read-write 0x400 OFFSET Address offset for external memory device 2. 0x8 read-write 0x00000000 0x20 OFFSET External memory Offset. 0 31 SIZE Upper address range for external memory device 2. 0xC read-write 0x0FFFFFFF 0x20 SIZE Upper limit address. 0 31 ENABLE Enable or disable external memory access. 0x20 read-write 0x00000000 0x20 ENABLE Enable or disable external memory access from AXI interface. 0 0 Disabled Disable external memory. 0x0 Enabled Enable external memory. 0x1 STRUCT1 Unspecified STRUCT1 EXTCONF1 read-write 0x400 LOCKEDACCESS Enable or disable locked APB access to serial memory controller. 0x14 read-write 0x00000000 0x20 ENABLE Enable or disable locked APB access to SSI. 0 0 Disabled Disable locked APB access. 0x0 Enabled Enable locked APB access. 0x1 RESET Reset the external memory. 0x1C read-write 0x00000000 0x20 RESET 0 0 Clear Reset is cleared. 0x0 Set Reset is set. 0x1 CORE Unspecified GLOBAL_EXMIF_CORE read-write 0x500 SSICADDRESS Unspecified GLOBAL_EXMIF_CORE_SSICADDRESS read-write 0x000 CTRLR0 This register controls the serial data transfer. 0x000 read-write 0x00004007 0x20 DFS Data Frame Size. 0 4 DFS_01_BIT Unspecified 0x00 DFS_02_BIT Unspecified 0x01 DFS_03_BIT Unspecified 0x02 DFS_04_BIT Unspecified 0x03 DFS_05_BIT Unspecified 0x04 DFS_06_BIT Unspecified 0x05 DFS_07_BIT Unspecified 0x06 DFS_08_BIT Unspecified 0x07 DFS_09_BIT Unspecified 0x08 DFS_10_BIT Unspecified 0x09 DFS_11_BIT Unspecified 0x0A DFS_12_BIT Unspecified 0x0B DFS_13_BIT Unspecified 0x0C DFS_14_BIT Unspecified 0x0D DFS_15_BIT Unspecified 0x0E DFS_16_BIT Unspecified 0x0F DFS_17_BIT Unspecified 0x10 DFS_18_BIT Unspecified 0x11 DFS_19_BIT Unspecified 0x12 DFS_20_BIT Unspecified 0x13 DFS_21_BIT Unspecified 0x14 DFS_22_BIT Unspecified 0x15 DFS_23_BIT Unspecified 0x16 DFS_24_BIT Unspecified 0x17 DFS_25_BIT Unspecified 0x18 DFS_26_BIT Unspecified 0x19 DFS_27_BIT Unspecified 0x1A DFS_28_BIT Unspecified 0x1B DFS_29_BIT Unspecified 0x1C DFS_30_BIT Unspecified 0x1D DFS_31_BIT Unspecified 0x1E DFS_32_BIT Unspecified 0x1F RSVDCTRLR05 Reserved bits - read as zero 5 5 read-only FRF Frame Format. 6 7 SPI Unspecified 0x0 SSP Unspecified 0x1 MICROWIRE Unspecified 0x2 SCPH Serial Clock Phase. 8 8 MIDDLE_BIT Unspecified 0x0 START_BIT Unspecified 0x1 SCPOL Serial Clock Polarity. 9 9 INACTIVE_HIGH Unspecified 0x0 INACTIVE_LOW Unspecified 0x1 TMOD Transfer Mode. 10 11 TX_AND_RX Unspecified 0x0 TX_ONLY Unspecified 0x1 RX_ONLY Unspecified 0x2 EEPROM_READ Unspecified 0x3 SLVOE Slave Output Enable. 12 12 ENABLED Unspecified 0x0 DISABLED Unspecified 0x1 SRL Shift Register Loop. 13 13 NORMAL_MODE Unspecified 0x0 TESTING_MODE Unspecified 0x1 SSTE Slave Select Toggle Enable. 14 14 TOGGLE_DISABLE Unspecified 0x0 TOGGLE_EN Unspecified 0x1 RSVDCTRLR015 Reserved bits - read as zero 15 15 read-only CFS Control Frame Size. 16 19 SIZE_01_BIT Unspecified 0x0 SIZE_02_BIT Unspecified 0x1 SIZE_03_BIT Unspecified 0x2 SIZE_04_BIT Unspecified 0x3 SIZE_05_BIT Unspecified 0x4 SIZE_06_BIT Unspecified 0x5 SIZE_07_BIT Unspecified 0x6 SIZE_08_BIT Unspecified 0x7 SIZE_09_BIT Unspecified 0x8 SIZE_10_BIT Unspecified 0x9 SIZE_11_BIT Unspecified 0xA SIZE_12_BIT Unspecified 0xB SIZE_13_BIT Unspecified 0xC SIZE_14_BIT Unspecified 0xD SIZE_15_BIT Unspecified 0xE SIZE_16_BIT Unspecified 0xF RSVDCTRLR02021 Reserved bits - read as zero 20 21 read-only SPIFRF SPI Frame Format 22 23 SPI_STANDARD Unspecified 0x0 SPI_DUAL Unspecified 0x1 SPI_QUAD Unspecified 0x2 SPI_OCTAL Unspecified 0x3 SPIHYPERBUSEN SPI Hyperbus Frame format enable. 24 24 DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 SPIDWSEN Enable Dynamic wait states in SPI mode of operation. 25 25 read-only DISABLE Unspecified 0x0 ENABLE Unspecified 0x1 RSVDCTRLR02631 Reserved bits - read as zero 26 30 read-only SSIISMST This field selects if DWC_ssi is working in Master or Slave mode 31 31 read-only SLAVE Unspecified 0x0 MASTER Unspecified 0x1 CTRLR1 This register exists only when the DWC_ssi is configured as a master device. 0x004 read-write 0x00000000 0x20 NDF Number of Data Frames. 0 15 RSVDCTRLR1 Reserved bits - read as zero 16 31 read-only SSIENR This register enables and disables the DWC_ssi. 0x008 read-write 0x00000000 0x20 SSICEN SSI Enable. 0 0 DISABLE Unspecified 0x0 ENABLED Unspecified 0x1 RSVDSSIENR Reserved bits - read as zero 1 31 read-only MWCR This register controls the direction of the data word for the half-duplex Microwire serial protocol. 0x00C read-write 0x00000000 0x20 MWMOD Microwire Transfer Mode. 0 0 NON_SEQUENTIAL Unspecified 0x0 SEQUENTIAL Unspecified 0x1 MDD Microwire Control. 1 1 RECEIVE Unspecified 0x0 TRANSMIT Unspecified 0x1 MHS Microwire Handshaking. 2 2 DISABLE Unspecified 0x0 ENABLED Unspecified 0x1 RSVDMWCR Reserved bits - read as zero 3 31 read-only SER This register is valid only when the DWC_ssi is configured as a master device. 0x010 read-write 0x00000000 0x20 SER Slave Select Enable Flag. 0 1 NOTSELECTED Unspecified 0x0 SELECTED Unspecified 0x1 RSVDSER Reserved bits - read as zero 2 31 read-only BAUDR This register is valid only when the DWC_ssi is configured as a master device. 0x014 read-write 0x00000000 0x20 RSVDBAUDR0 Reserved bits - read as zero 0 0 read-only SCKDV SSI Clock Divider. 1 15 RSVDBAUDR1631 Reserved bits - read as zero 16 31 read-only TXFTLR This register controls the threshold value for the transmit FIFO memory.. 0x018 read-write 0x00000000 0x20 TFT Transmit FIFO Threshold. 0 4 RSVDTXFTLR Reserved bits - read as zero 5 15 read-only TXFTHR Transfer start FIFO level. 16 20 RSVDTXFTHR Reserved bits - read as zero 21 31 read-only RXFTLR This register controls the threshold value for the receive FIFO memory.. 0x01C read-write 0x00000000 0x20 RFT Receive FIFO Threshold. 0 4 RSVDRXFTLR Reserved bits - read as zero 5 31 read-only TXFLR This register contains the number of valid data entries in the transmit FIFO memory. 0x020 read-write 0x00000000 0x20 TXTFL Transmit FIFO Level. 0 5 read-only RSVDTXFLR Reserved bits - read as zero 6 31 read-only RXFLR This register contains the number of valid data entries in the receive FIFO memory. 0x024 read-write 0x00000000 0x20 RXTFL Receive FIFO Level. 0 5 read-only RSVDRXFLR Reserved bits - read as zero 6 31 read-only SR This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. 0x028 read-write 0x00000006 0x20 BUSY SSI Busy Flag. 0 0 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TFNF Transmit FIFO Not Full. 1 1 read-only FULL Unspecified 0x0 NOT_FULL Unspecified 0x1 TFE Transmit FIFO Empty. 2 2 read-only NOT_EMPTY Unspecified 0x0 EMPTY Unspecified 0x1 RFNE Receive FIFO Not Empty. 3 3 read-only EMPTY Unspecified 0x0 NOT_EMPTY Unspecified 0x1 RFF Receive FIFO Full. 4 4 read-only NOT_FULL Unspecified 0x0 FULL Unspecified 0x1 TXE Transmission Error. 5 5 read-only NO_ERROR Unspecified 0x0 TX_ERROR Unspecified 0x1 DCOL Data Collision Error. 6 6 read-only NO_ERROR_CONDITION Unspecified 0x0 TX_COLLISION_ERROR Unspecified 0x1 RSVDSR Reserved bits - read as zero 7 14 read-only CMPLTDDF Completed Data frames 15 31 read-only IMR This read/write register masks or enables all interrupts generated by the DWC_ssi. 0x02C read-write 0x000000FF 0x20 TXEIM Transmit FIFO Empty Interrupt Mask 0 0 MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 TXOIM Transmit FIFO Overflow Interrupt Mask 1 1 MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 RXUIM Receive FIFO Underflow Interrupt Mask 2 2 MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 RXOIM Receive FIFO Overflow Interrupt Mask 3 3 MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 RXFIM Receive FIFO Full Interrupt Mask 4 4 MASKED ssi_rxf_intr interrupt is masked 0x0 UNMASKED ssi_rxf_intr interrupt is not masked 0x1 MSTIM Multi-Master Contention Interrupt Mask. 5 5 MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 XRXOIM XIP Receive FIFO Overflow Interrupt Mask 6 6 MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 TXUIM Transmit FIFO Underflow Interrupt Mask 7 7 MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 AXIEM AXI Error Interrupt Mask 8 8 read-only MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 RSVD9IMR Reserved bits - read as zero 9 9 read-only SPITEM SPI Transmit Error Interrupt Mask 10 10 read-only MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 DONEM SSI Done Interrupt Mask 11 11 read-only MASKED Unspecified 0x0 UNMASKED Unspecified 0x1 RSVD1232IMR Reserved bits - read as zero 12 31 read-only ISR This register reports the status of the DWC_ssi interrupts after they have been masked. 0x030 read-write 0x00000000 0x20 TXEIS Transmit FIFO Empty Interrupt Status 0 0 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXOIS Transmit FIFO Overflow Interrupt Status 1 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RXUIS Receive FIFO Underflow Interrupt Status 2 2 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RXOIS Receive FIFO Overflow Interrupt Status 3 3 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RXFIS Receive FIFO Full Interrupt Status 4 4 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 MSTIS Multi-Master Contention Interrupt Status. 5 5 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 XRXOIS XIP Receive FIFO Overflow Interrupt Status 6 6 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXUIS Transmit FIFO Underflow Interrupt Status 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AXIES AXI Error Interrupt Status 8 8 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSVD9RISR Reserved bits - read as zero 9 9 read-only SPITES SPI Transmit Error Interrupt 10 10 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DONES SSI Done Interrupt Status 11 11 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSVD1232RISR Reserved bits - read as zero 12 31 read-only RISR Raw Interrupt Status Register 0x034 read-write 0x00000000 0x20 TXEIR Transmit FIFO Empty Raw Interrupt Status 0 0 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXOIR Transmit FIFO Overflow Raw Interrupt Status 1 1 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RXUIR Receive FIFO Underflow Raw Interrupt Status 2 2 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RXOIR Receive FIFO Overflow Raw Interrupt Status 3 3 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RXFIR Receive FIFO Full Raw Interrupt Status 4 4 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 MSTIR Multi-Master Contention Raw Interrupt Status. 5 5 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 XRXOIR XIP Receive FIFO Overflow Raw Interrupt Status 6 6 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 TXUIR Transmit FIFO Underflow Interrupt Raw Status 7 7 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 AXIER AXI Error Interrupt Raw Status 8 8 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSVD9RISR Reserved bits - read as zero 9 9 read-only SPITER SPI Transmit Error Interrupt status. 10 10 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 DONER SSI Done Interrupt Raw Status 11 11 read-only INACTIVE Unspecified 0x0 ACTIVE Unspecified 0x1 RSVD1232RISR Reserved bits - read as zero 12 31 read-only TXEICR Transmit FIFO Error Interrupt Clear Register 0x038 read-write 0x00000000 0x20 TXEICR Clear Transmit FIFO Overflow/Underflow Interrupt. 0 0 read-only RSVDTXEICR Reserved bits - read as zero 1 31 read-only RXOICR Receive FIFO Overflow Interrupt Clear Register 0x03C read-write 0x00000000 0x20 RXOICR Clear Receive FIFO Overflow Interrupt. 0 0 read-only RSVDRXOICR Reserved bits - read as zero 1 31 read-only RXUICR Receive FIFO Underflow Interrupt Clear Register 0x040 read-write 0x00000000 0x20 RXUICR Clear Receive FIFO Underflow Interrupt. 0 0 read-only RSVDRXUICR Reserved bits - read as zero 1 31 read-only MSTICR Multi-Master Interrupt Clear Register 0x044 read-write 0x00000000 0x20 MSTICR Clear Multi-Master Contention Interrupt. 0 0 read-only RSVDMSTICR Reserved bits - read as zero 1 31 read-only ICR Interrupt Clear Register 0x048 read-write 0x00000000 0x20 ICR Clear Interrupts. 0 0 read-only RSVDICR Reserved bits - read as zero 1 31 read-only IDR This register contains the peripherals identification code, which is written into the register at configuration time using coreConsultant. 0x058 read-write 0x00010003 0x20 IDCODE Identification code. 0 31 read-only SSICVERSIONID This read-only register stores the specific DWC_ssi component version. 0x05C read-write 0x3130332A 0x20 SSICCOMPVERSION Contains the hex representation of the Synopsys component version. 0 31 read-only 0x24 0x4 DR[%s] Description collection: The DWC_ssi data register is a 32-bit read/write buffer for the transmit/receive FIFOs. 0x060 read-write 0x00000000 0x20 DR Data Register. 0 31 RXSAMPLEDELAY This register is only valid when the DWC_ssi is configured with rxd sample delay logic (SSIC_HAS_RX_SAMPLE_DELAY==1). 0x0F0 read-write 0x00000000 0x20 RSD Receive Data (rxd) Sample Delay. 0 7 RSVD0RXSAMPLEDLY Reserved bits - read as zero 8 15 read-only SE Receive Data (rxd) Sampling Edge. 16 16 RSVD1RXSAMPLEDLY Reserved bits - read as zero 17 31 read-only SPICTRLR0 This register is used to control the serial data transfer in enhanced SPI mode of operation. 0x0F4 read-write 0x00000A00 0x20 TRANSTYPE Address and instruction transfer format. 0 1 TT0 Unspecified 0x0 TT1 Unspecified 0x1 TT2 Unspecified 0x2 TT3 Unspecified 0x3 ADDRL This bit defines Length of Address to be transmitted. 2 5 ADDR_L0 Unspecified 0x0 ADDR_L4 Unspecified 0x1 ADDR_L8 Unspecified 0x2 ADDR_L12 Unspecified 0x3 ADDR_L16 Unspecified 0x4 ADDR_L20 Unspecified 0x5 ADDR_L24 Unspecified 0x6 ADDR_L28 Unspecified 0x7 ADDR_L32 Unspecified 0x8 ADDR_L36 Unspecified 0x9 ADDR_L40 Unspecified 0xA ADDR_L44 Unspecified 0xB ADDR_L48 Unspecified 0xC ADDR_L52 Unspecified 0xD ADDR_L56 Unspecified 0xE ADDR_L60 Unspecified 0xF RSVDSPICTRLR06 Reserved bits - read as zero 6 6 read-only XIPMDBITEN Mode bits enable in XIP mode. 7 7 read-only INSTL Dual/Quad/Octal mode instruction length in bits. 8 9 INST_L0 Unspecified 0x0 INST_L4 Unspecified 0x1 INST_L8 Unspecified 0x2 INST_L16 Unspecified 0x3 RSVDSPICTRLR010 Reserved bits - read as zero 10 10 read-only WAITCYCLES Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. 11 15 SPIDDREN SPI DDR Enable bit. 16 16 INSTDDREN Instruction DDR Enable bit. 17 17 SPIRXDSEN Read data strobe enable bit. 18 18 XIPDFSHC Fix DFS for XIP transfers. 19 19 read-only XIPINSTEN XIP instruction enable bit. 20 20 read-only SSICXIPCONTXFEREN Enable continuous transfer in XIP mode. 21 21 read-only RSVDSPICTRLR02223 Reserved bits - read as zero 22 23 read-only SPIDMEN SPI data mask enable bit. 24 24 SPIRXDSSIGEN Enable rxds signaling during address and command phase of Hyperbus transfer. 25 25 XIPMBL XIP Mode bits length. 26 27 read-only MBL_2 Unspecified 0x0 MBL_4 Unspecified 0x1 MBL_8 Unspecified 0x2 MBL_16 Unspecified 0x3 RSVDSPICTRLR028 Reserved bits - read as zero 28 28 read-only XIPPREFETCHEN Enables XIP pre-fetch functionality in DWC_ssi. 29 29 read-only CLKSTRETCHEN Enables clock stretching capability in SPI transfers. 30 30 RSVDSPICTRLR0 Reserved bits - read as zero 31 31 read-only DDRDRIVEEDGE This Register is valid only when SSIC_HAS_DDR is equal to 1. 0x0F8 read-write 0x00000000 0x20 TDE TXD Drive edge register which decided the driving edge of transmit data. 0 7 RSVDDDRDRIVEEDGE Reserved bits - read as zero 8 31 read-only XIPMODEBITS This register carries the mode bits which are sent in the XIP mode of operation after address phase. 0x0FC read-write 0x00000000 0x20 XIPMDBITS XIP mode bits to be sent after address phase of XIP transfer. 0 15 RSVDXIPMDBITS Reserved bits - read as zero 16 31 read-only SSICXIPADDRESS Unspecified GLOBAL_EXMIF_CORE_SSICXIPADDRESS read-write 0x100 XIPINCRINST This Register is valid only when SSIC_XIP_EN is equal to 1. 0x000 read-write 0x00000000 0x20 INCRINST XIP INCR transfer opcode. 0 15 RSVDINCRINST Reserved bits - read as zero 16 31 read-only XIPWRAPINST This Register is valid only when SSIC_XIP_EN is equal to 1. 0x004 read-write 0x00000000 0x20 WRAPINST XIP WRAP transfer opcode. 0 15 RSVDWRAPINST Reserved bits - read as zero 16 31 read-only XIPCTRL This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1. 0x008 read-write 0x08000401 0x20 FRF SPI Frame Format 0 1 RSVD Unspecified 0x0 SPI_DUAL Unspecified 0x1 SPI_QUAD Unspecified 0x2 SPI_OCTAL Unspecified 0x3 TRANSTYPE Address and instruction transfer format. 2 3 TT0 Unspecified 0x0 TT1 Unspecified 0x1 TT2 Unspecified 0x2 TT3 Unspecified 0x3 ADDRL This bit defines Length of Address to be transmitted. 4 7 ADDR_L0 Unspecified 0x0 ADDR_L4 Unspecified 0x1 ADDR_L8 Unspecified 0x2 ADDR_L12 Unspecified 0x3 ADDR_L16 Unspecified 0x4 ADDR_L20 Unspecified 0x5 ADDR_L24 Unspecified 0x6 ADDR_L28 Unspecified 0x7 ADDR_L32 Unspecified 0x8 ADDR_L36 Unspecified 0x9 ADDR_L40 Unspecified 0xA ADDR_L44 Unspecified 0xB ADDR_L48 Unspecified 0xC ADDR_L52 Unspecified 0xD ADDR_L56 Unspecified 0xE ADDR_L60 Unspecified 0xF RSVDXIPCTRL8 Reserved bits - read as zero 8 8 read-only INSTL Dual/Quad/Octal mode instruction length in bits. 9 10 INST_L0 Unspecified 0x0 INST_L4 Unspecified 0x1 INST_L8 Unspecified 0x2 INST_L16 Unspecified 0x3 RSVDSPICTRLR011 Reserved bits - read as zero 11 11 read-only MDBITSEN Mode bits enable in XIP mode. 12 12 WAITCYCLES Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. 13 17 DFSHC Fix DFS for XIP transfers. 18 18 DDREN SPI DDR Enable bit. 19 19 INSTDDREN Instruction DDR Enable bit. 20 20 RXDSEN Read data strobe enable bit. 21 21 INSTEN XIP instruction enable bit. 22 22 CONTXFEREN Enable continuous transfer in XIP mode. 23 23 read-only XIPHYPERBUSEN SPI Hyperbus Frame format enable for XIP transfers. 24 24 RXDSSIGEN Enable rxds signaling during address and command phase of Hyperbus transfer. 25 25 XIPMBL XIP Mode bits length. 26 27 MBL_2 Unspecified 0x0 MBL_4 Unspecified 0x1 MBL_8 Unspecified 0x2 MBL_16 Unspecified 0x3 RSVDXIPCTRL28 Reserved bits - read as zero 28 28 read-only XIPPREFETCHEN Enables XIP pre-fetch functionality in DWC_ssi. 29 29 RSVDXIPCTRL Reserved bits - read as zero 30 31 read-only XRXOICR XIP Receive FIFO Overflow Interrupt Clear Register 0x010 read-write 0x00000000 0x20 XRXOICR Clear XIP Receive FIFO Overflow Interrupt. 0 0 read-only RSVDXRXOICR Reserved bits - read as zero 1 31 read-only XIPWRITEINCRINST This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. 0x040 read-write 0x00000000 0x20 INCRWRITEINST XIP Write INCR transfer opcode. 0 15 RSVDINCRINST16TO31 Reserved bits - Read Only 16 31 read-only XIPWRITEWRAPINST This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. 0x044 read-write 0x00000000 0x20 WRAPWRITEINST XIP Write WRAP transfer opcode. 0 15 RSVDWRAPINST16TO31 Reserved bits - Read Only 16 31 read-only XIPWRITECTRL This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1. 0x048 read-write 0x00000002 0x20 WRFRF SPI Frame Format 0 1 RSVD Unspecified 0x0 SPI_DUAL Unspecified 0x1 SPI_QUAD Unspecified 0x2 SPI_OCTAL Unspecified 0x3 WRTRANSTYPE Address and instruction transfer format. 2 3 TT0 Unspecified 0x0 TT1 Unspecified 0x1 TT2 Unspecified 0x2 TT3 Unspecified 0x3 WRADDRL This bit defines Length of Address to be transmitted. 4 7 ADDR_L0 Unspecified 0x0 ADDR_L4 Unspecified 0x1 ADDR_L8 Unspecified 0x2 ADDR_L12 Unspecified 0x3 ADDR_L16 Unspecified 0x4 ADDR_L20 Unspecified 0x5 ADDR_L24 Unspecified 0x6 ADDR_L28 Unspecified 0x7 ADDR_L32 Unspecified 0x8 WRINSTL Dual/Quad/Octal mode instruction length in bits. 8 9 INST_L0 Unspecified 0x0 INST_L4 Unspecified 0x1 INST_L8 Unspecified 0x2 INST_L16 Unspecified 0x3 WRSPIDDREN SPI DDR Enable bit. 10 10 WRINSTDDREN Instruction DDR Enable bit. 11 11 XIPWRHYPERBUSEN SPI Hyperbus Frame format enable for XIP Write transfers. 12 12 XIPWRRXDSSIGEN Enable rxds signaling during address and command phase of Hyperbus transfer. 13 13 RSVDXIPWRITECTRL14TO15 Reserved bits - Read Only 14 15 read-only XIPWRWAITCYCLES Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. 16 20 RSVDXIPWRITECTRL21TO31 Reserved bits - Read Only 21 31 read-only GLOBAL_EXMIF_S External Memory Interface 1 0x5F095000 EXMIF 149 GLOBAL_SECDOMBELLBOARD_NS BELLBOARD public registers 0 0x4F099000 BELLBOARDPUBLIC 0 0x1000 registers BELLBOARDPUBLIC 0x20 0x20 0x4 TASKS_TRIGGER[%s] Description collection: Task TRIGGER[n] 0x000 write-only 0x00000000 0x20 TASKS_TRIGGER Task TRIGGER[n] 0 0 Trigger Trigger task 0x1 GLOBAL_SECDOMBELLBOARD_S BELLBOARD public registers 1 0x5F099000 GLOBAL_VPR120_NS VPR peripheral registers 0 0x4F8C9000 VPRPUBLIC 0 0x1000 registers VPRPUBLIC 0x20 0x20 0x4 TASKS_TRIGGER[%s] Description collection: VPR task [n] register 0x000 write-only 0x00000000 0x20 TASKS_TRIGGER VPR task [n] register 0 0 Trigger Trigger task 0x1 GLOBAL_VPR120_S VPR peripheral registers 1 0x5F8C9000 GLOBAL_IPCT120_NS IPCT APB registers 0 0x4F8D1000 IPCT 0 0x1000 registers IPCT120_0 209 IPCT 0x20 0x8 0x4 TASKS_SEND[%s] Description collection: Trigger event on IPCT source channel n if there are no active signals present on that channel 0x000 write-only 0x00000000 0x20 TASKS_SEND Trigger event on IPCT source channel n if there are no active signals present on that channel 0 0 Trigger Trigger task 0x1 0x8 0x4 TASKS_ACK[%s] Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that channel will re-trigger the RECEIVE[n] event. The flush can happen automatically by configuring the SHORTS register accordingly. 0x040 write-only 0x00000000 0x20 TASKS_ACK Flush IPCT sink channel n. Any pending IPCT signal on that channel will re-trigger the RECEIVE[n] event. The flush can happen automatically by configuring the SHORTS register accordingly. 0 0 Trigger Trigger task 0x1 0x8 0x4 SUBSCRIBE_SEND[%s] Description collection: Subscribe configuration for task SEND[n] 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task SEND[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x8 0x4 SUBSCRIBE_ACK[%s] Description collection: Subscribe configuration for task ACK[n] 0x0C0 read-write 0x00000000 0x20 CHIDX DPPI channel that task ACK[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x8 0x4 EVENTS_RECEIVE[%s] Description collection: Event received on IPCT sink channel n 0x100 read-write 0x00000000 0x20 EVENTS_RECEIVE Event received on IPCT sink channel n 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x8 0x4 EVENTS_ACKED[%s] Description collection: Event received when hardware handshake of SEND task for IPCT source channel n is complete and a new signal can be triggered on that channel. 0x140 read-write 0x00000000 0x20 EVENTS_ACKED Event received when hardware handshake of SEND task for IPCT source channel n is complete and a new signal can be triggered on that channel. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x8 0x4 PUBLISH_RECEIVE[%s] Description collection: Publish configuration for event RECEIVE[n] 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event RECEIVE[n] will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 0x8 0x4 PUBLISH_ACKED[%s] Description collection: Publish configuration for event ACKED[n] 0x1C0 read-write 0x00000000 0x20 CHIDX DPPI channel that event ACKED[n] will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 RECEIVE0_ACK0 Shortcut between event RECEIVE[0] and task ACK[0] 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RECEIVE1_ACK1 Shortcut between event RECEIVE[1] and task ACK[1] 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RECEIVE2_ACK2 Shortcut between event RECEIVE[2] and task ACK[2] 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RECEIVE3_ACK3 Shortcut between event RECEIVE[3] and task ACK[3] 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RECEIVE4_ACK4 Shortcut between event RECEIVE[4] and task ACK[4] 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RECEIVE5_ACK5 Shortcut between event RECEIVE[5] and task ACK[5] 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RECEIVE6_ACK6 Shortcut between event RECEIVE[6] and task ACK[6] 6 6 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 RECEIVE7_ACK7 Shortcut between event RECEIVE[7] and task ACK[7] 7 7 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 RECEIVE0 Enable or disable interrupt for event RECEIVE[0] 0 0 Disabled Disable 0x0 Enabled Enable 0x1 RECEIVE1 Enable or disable interrupt for event RECEIVE[1] 1 1 Disabled Disable 0x0 Enabled Enable 0x1 RECEIVE2 Enable or disable interrupt for event RECEIVE[2] 2 2 Disabled Disable 0x0 Enabled Enable 0x1 RECEIVE3 Enable or disable interrupt for event RECEIVE[3] 3 3 Disabled Disable 0x0 Enabled Enable 0x1 RECEIVE4 Enable or disable interrupt for event RECEIVE[4] 4 4 Disabled Disable 0x0 Enabled Enable 0x1 RECEIVE5 Enable or disable interrupt for event RECEIVE[5] 5 5 Disabled Disable 0x0 Enabled Enable 0x1 RECEIVE6 Enable or disable interrupt for event RECEIVE[6] 6 6 Disabled Disable 0x0 Enabled Enable 0x1 RECEIVE7 Enable or disable interrupt for event RECEIVE[7] 7 7 Disabled Disable 0x0 Enabled Enable 0x1 ACKED0 Enable or disable interrupt for event ACKED[0] 16 16 Disabled Disable 0x0 Enabled Enable 0x1 ACKED1 Enable or disable interrupt for event ACKED[1] 17 17 Disabled Disable 0x0 Enabled Enable 0x1 ACKED2 Enable or disable interrupt for event ACKED[2] 18 18 Disabled Disable 0x0 Enabled Enable 0x1 ACKED3 Enable or disable interrupt for event ACKED[3] 19 19 Disabled Disable 0x0 Enabled Enable 0x1 ACKED4 Enable or disable interrupt for event ACKED[4] 20 20 Disabled Disable 0x0 Enabled Enable 0x1 ACKED5 Enable or disable interrupt for event ACKED[5] 21 21 Disabled Disable 0x0 Enabled Enable 0x1 ACKED6 Enable or disable interrupt for event ACKED[6] 22 22 Disabled Disable 0x0 Enabled Enable 0x1 ACKED7 Enable or disable interrupt for event ACKED[7] 23 23 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 RECEIVE0 Write '1' to enable interrupt for event RECEIVE[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RECEIVE1 Write '1' to enable interrupt for event RECEIVE[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RECEIVE2 Write '1' to enable interrupt for event RECEIVE[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RECEIVE3 Write '1' to enable interrupt for event RECEIVE[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RECEIVE4 Write '1' to enable interrupt for event RECEIVE[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RECEIVE5 Write '1' to enable interrupt for event RECEIVE[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RECEIVE6 Write '1' to enable interrupt for event RECEIVE[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RECEIVE7 Write '1' to enable interrupt for event RECEIVE[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACKED0 Write '1' to enable interrupt for event ACKED[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACKED1 Write '1' to enable interrupt for event ACKED[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACKED2 Write '1' to enable interrupt for event ACKED[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACKED3 Write '1' to enable interrupt for event ACKED[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACKED4 Write '1' to enable interrupt for event ACKED[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACKED5 Write '1' to enable interrupt for event ACKED[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACKED6 Write '1' to enable interrupt for event ACKED[6] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACKED7 Write '1' to enable interrupt for event ACKED[7] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 RECEIVE0 Write '1' to disable interrupt for event RECEIVE[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RECEIVE1 Write '1' to disable interrupt for event RECEIVE[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RECEIVE2 Write '1' to disable interrupt for event RECEIVE[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RECEIVE3 Write '1' to disable interrupt for event RECEIVE[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RECEIVE4 Write '1' to disable interrupt for event RECEIVE[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RECEIVE5 Write '1' to disable interrupt for event RECEIVE[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RECEIVE6 Write '1' to disable interrupt for event RECEIVE[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RECEIVE7 Write '1' to disable interrupt for event RECEIVE[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACKED0 Write '1' to disable interrupt for event ACKED[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACKED1 Write '1' to disable interrupt for event ACKED[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACKED2 Write '1' to disable interrupt for event ACKED[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACKED3 Write '1' to disable interrupt for event ACKED[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACKED4 Write '1' to disable interrupt for event ACKED[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACKED5 Write '1' to disable interrupt for event ACKED[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACKED6 Write '1' to disable interrupt for event ACKED[6] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACKED7 Write '1' to disable interrupt for event ACKED[7] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND Pending interrupts 0x30C read-only 0x00000000 0x20 RECEIVE0 Read pending status of interrupt for event RECEIVE[0] 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 RECEIVE1 Read pending status of interrupt for event RECEIVE[1] 1 1 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 RECEIVE2 Read pending status of interrupt for event RECEIVE[2] 2 2 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 RECEIVE3 Read pending status of interrupt for event RECEIVE[3] 3 3 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 RECEIVE4 Read pending status of interrupt for event RECEIVE[4] 4 4 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 RECEIVE5 Read pending status of interrupt for event RECEIVE[5] 5 5 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 RECEIVE6 Read pending status of interrupt for event RECEIVE[6] 6 6 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 RECEIVE7 Read pending status of interrupt for event RECEIVE[7] 7 7 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ACKED0 Read pending status of interrupt for event ACKED[0] 16 16 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ACKED1 Read pending status of interrupt for event ACKED[1] 17 17 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ACKED2 Read pending status of interrupt for event ACKED[2] 18 18 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ACKED3 Read pending status of interrupt for event ACKED[3] 19 19 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ACKED4 Read pending status of interrupt for event ACKED[4] 20 20 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ACKED5 Read pending status of interrupt for event ACKED[5] 21 21 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ACKED6 Read pending status of interrupt for event ACKED[6] 22 22 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ACKED7 Read pending status of interrupt for event ACKED[7] 23 23 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 OVERFLOW Unspecified GLOBAL_IPCT_OVERFLOW read-write 0x400 SEND Overflow status for SEND tasks Write 0 to clear 0x000 read-write 0x00000000 0x20 SEND_0 Overflow status for SEND[0] task 0 0 Overflow Task overflow has happened 0x1 NoOverflow Task overflow has not happened 0x0 SEND_1 Overflow status for SEND[1] task 1 1 Overflow Task overflow has happened 0x1 NoOverflow Task overflow has not happened 0x0 SEND_2 Overflow status for SEND[2] task 2 2 Overflow Task overflow has happened 0x1 NoOverflow Task overflow has not happened 0x0 SEND_3 Overflow status for SEND[3] task 3 3 Overflow Task overflow has happened 0x1 NoOverflow Task overflow has not happened 0x0 SEND_4 Overflow status for SEND[4] task 4 4 Overflow Task overflow has happened 0x1 NoOverflow Task overflow has not happened 0x0 SEND_5 Overflow status for SEND[5] task 5 5 Overflow Task overflow has happened 0x1 NoOverflow Task overflow has not happened 0x0 SEND_6 Overflow status for SEND[6] task 6 6 Overflow Task overflow has happened 0x1 NoOverflow Task overflow has not happened 0x0 SEND_7 Overflow status for SEND[7] task 7 7 Overflow Task overflow has happened 0x1 NoOverflow Task overflow has not happened 0x0 GLOBAL_IPCT120_S IPCT APB registers 1 0x5F8D1000 IPCT120_0 209 GLOBAL_MUTEX120_NS MUTEX 0 0x4F8D2000 MUTEX 0 0x1000 registers MUTEX 0x20 0x20 0x4 MUTEX[%s] Description collection: Mutex register 0x400 read-write 0x00000000 0x20 MUTEX Mutex register n 0 0 Unlocked Mutex n is in unlocked state 0x0 Locked Mutex n is in locked state 0x1 GLOBAL_I3C120_NS I3C 0 0x4F8D3000 I3C 0 0x1000 registers I3C120 211 I3C 0x20 EVENTS_CORE Event indicating that interrupt triggered at I3C core 0x100 read-write 0x00000000 0x20 EVENTS_CORE Event indicating that interrupt triggered at I3C core 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DMA Event indicating that interrupt triggered at I3C DMA 0x104 read-write 0x00000000 0x20 EVENTS_DMA Event indicating that interrupt triggered at I3C DMA 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 CORE Enable or disable interrupt for event CORE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 DMA Enable or disable interrupt for event DMA 1 1 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 CORE Write '1' to enable interrupt for event CORE 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DMA Write '1' to enable interrupt for event DMA 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 CORE Write '1' to disable interrupt for event CORE 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DMA Write '1' to disable interrupt for event DMA 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND Pending interrupts 0x30C read-only 0x00000000 0x20 CORE Read pending status of interrupt for event CORE 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 DMA Read pending status of interrupt for event DMA 1 1 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ENABLE Enable I3C peripheral. 0x400 read-write 0x00000000 0x20 EN Enable 0 0 Disabled I3C peripheral disabled. 0x0 Enabled I3C peripheral enabled. 0x1 CDR Unspecified I3C_CDR read-write 0x404 STARTOFFSET Start offset of recovered clock 0x000 read-write 0x00000004 0x20 VAL Value 0 15 MAXCYCLERATIO Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock 0x004 read-write 0x00000028 0x20 VAL Value 0 15 MAXSKEW Maximum skew between SCL and SCL in CDR clock cycles 0x008 read-write 0x00000005 0x20 VAL Value 0 7 SLAVEIF0 I3C slave interface 0 0x410 read-write 0x00000000 0x20 MODEI2C I2C or I3C mode select signal 0 0 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 ACTMODE Slave activity mode for GETSTATUS CCC 1 2 PENDINGINT Pending interrupt information for GETSTATUS CCC 3 6 STATICADDREN Slave static address valid 7 7 DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 STATICADDR Slave static address 8 14 SLAVEMAXRDSPEED Slave maximum read data rate 15 17 SLAVEMAXWRSPEED Slave maximum write write rate 18 20 SLAVECLKDATATURNTIME Slave maximum clock data turnaround time 21 23 SLAVEDCR Device Characteristic Register value 24 31 SLAVEIF1 I3C slave interface 1 0x414 read-write 0x00000000 0x20 WAKEUP Slave wakeup signal 0 0 read-only DISABLED Unspecified 0x0 ENABLED Unspecified 0x1 SLAVEPID0 Slave Device Provisioned ID 0 0x418 read-write 0x00000000 0x20 ADDMEANING Additional Meaning 0 11 INSTANCEID Instance ID 12 15 PARTID Part ID 16 31 SLAVEPID1 Slave Device Provisioned ID 1 0x41C read-write 0x00000000 0x20 PROVID Provisional ID Type Selector 0 0 MIPIMID MIPI Manufacturer ID 1 15 KEEPSDA Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. 0x420 read-write 0x00000000 0x20 ENABLE Enable or disable the SDA high-keeper 0 0 Disabled High-keeper disabled. 0x0 Enabled High-keeper enabled. 0x1 KEEPSCL Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. 0x424 read-write 0x00000000 0x20 ENABLE Enable or disable the SCL high-keeper 0 0 Disabled High-keeper disabled. 0x0 Enabled High-keeper enabled. 0x1 GLOBAL_I3C120_S I3C 1 0x5F8D3000 I3C120 211 GLOBAL_VPR121_NS VPR peripheral registers 0 0x4F8D4000 VPR 0 0x1000 registers VPR121 212 VPR 0x20 0x20 0x4 TASKS_TRIGGER[%s] Description collection: VPR task [n] register 0x000 write-only 0x00000000 0x20 TASKS_TRIGGER VPR task [n] register 0 0 Trigger Trigger task 0x1 0x20 0x4 SUBSCRIBE_TRIGGER[%s] Description collection: Subscribe configuration for task TASKS_TRIGGER[n] 0x080 read-write 0x00000000 0x20 EN Subscription enable bit 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x20 0x4 EVENTS_TRIGGERED[%s] Description collection: VPR event [n] register 0x100 read-write 0x00000000 0x20 EVENTS_TRIGGERED VPR event [n] register 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x20 0x4 PUBLISH_TRIGGERED[%s] Description collection: Publish configuration for event EVENTS_TRIGGERED[n] 0x180 read-write 0x00000000 0x20 EN Publication enable bit 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 TRIGGERED0 Enable or disable interrupt for event TRIGGERED[0] 0 0 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED1 Enable or disable interrupt for event TRIGGERED[1] 1 1 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED2 Enable or disable interrupt for event TRIGGERED[2] 2 2 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED3 Enable or disable interrupt for event TRIGGERED[3] 3 3 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED4 Enable or disable interrupt for event TRIGGERED[4] 4 4 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED5 Enable or disable interrupt for event TRIGGERED[5] 5 5 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED6 Enable or disable interrupt for event TRIGGERED[6] 6 6 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED7 Enable or disable interrupt for event TRIGGERED[7] 7 7 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED8 Enable or disable interrupt for event TRIGGERED[8] 8 8 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED9 Enable or disable interrupt for event TRIGGERED[9] 9 9 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED10 Enable or disable interrupt for event TRIGGERED[10] 10 10 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED11 Enable or disable interrupt for event TRIGGERED[11] 11 11 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED12 Enable or disable interrupt for event TRIGGERED[12] 12 12 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED13 Enable or disable interrupt for event TRIGGERED[13] 13 13 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED14 Enable or disable interrupt for event TRIGGERED[14] 14 14 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED15 Enable or disable interrupt for event TRIGGERED[15] 15 15 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED16 Enable or disable interrupt for event TRIGGERED[16] 16 16 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED17 Enable or disable interrupt for event TRIGGERED[17] 17 17 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED18 Enable or disable interrupt for event TRIGGERED[18] 18 18 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED19 Enable or disable interrupt for event TRIGGERED[19] 19 19 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED20 Enable or disable interrupt for event TRIGGERED[20] 20 20 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED21 Enable or disable interrupt for event TRIGGERED[21] 21 21 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED22 Enable or disable interrupt for event TRIGGERED[22] 22 22 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED23 Enable or disable interrupt for event TRIGGERED[23] 23 23 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED24 Enable or disable interrupt for event TRIGGERED[24] 24 24 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED25 Enable or disable interrupt for event TRIGGERED[25] 25 25 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED26 Enable or disable interrupt for event TRIGGERED[26] 26 26 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED27 Enable or disable interrupt for event TRIGGERED[27] 27 27 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED28 Enable or disable interrupt for event TRIGGERED[28] 28 28 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED29 Enable or disable interrupt for event TRIGGERED[29] 29 29 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED30 Enable or disable interrupt for event TRIGGERED[30] 30 30 Disabled Disable 0x0 Enabled Enable 0x1 TRIGGERED31 Enable or disable interrupt for event TRIGGERED[31] 31 31 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 TRIGGERED0 Write '1' to enable interrupt for event TRIGGERED[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED1 Write '1' to enable interrupt for event TRIGGERED[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED2 Write '1' to enable interrupt for event TRIGGERED[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED3 Write '1' to enable interrupt for event TRIGGERED[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED4 Write '1' to enable interrupt for event TRIGGERED[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED5 Write '1' to enable interrupt for event TRIGGERED[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED6 Write '1' to enable interrupt for event TRIGGERED[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED7 Write '1' to enable interrupt for event TRIGGERED[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED8 Write '1' to enable interrupt for event TRIGGERED[8] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED9 Write '1' to enable interrupt for event TRIGGERED[9] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED10 Write '1' to enable interrupt for event TRIGGERED[10] 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED11 Write '1' to enable interrupt for event TRIGGERED[11] 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED12 Write '1' to enable interrupt for event TRIGGERED[12] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED13 Write '1' to enable interrupt for event TRIGGERED[13] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED14 Write '1' to enable interrupt for event TRIGGERED[14] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED15 Write '1' to enable interrupt for event TRIGGERED[15] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED16 Write '1' to enable interrupt for event TRIGGERED[16] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED17 Write '1' to enable interrupt for event TRIGGERED[17] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED18 Write '1' to enable interrupt for event TRIGGERED[18] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED19 Write '1' to enable interrupt for event TRIGGERED[19] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED20 Write '1' to enable interrupt for event TRIGGERED[20] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED21 Write '1' to enable interrupt for event TRIGGERED[21] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED22 Write '1' to enable interrupt for event TRIGGERED[22] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED23 Write '1' to enable interrupt for event TRIGGERED[23] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED24 Write '1' to enable interrupt for event TRIGGERED[24] 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED25 Write '1' to enable interrupt for event TRIGGERED[25] 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED26 Write '1' to enable interrupt for event TRIGGERED[26] 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED27 Write '1' to enable interrupt for event TRIGGERED[27] 27 27 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED28 Write '1' to enable interrupt for event TRIGGERED[28] 28 28 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED29 Write '1' to enable interrupt for event TRIGGERED[29] 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED30 Write '1' to enable interrupt for event TRIGGERED[30] 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TRIGGERED31 Write '1' to enable interrupt for event TRIGGERED[31] 31 31 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 TRIGGERED0 Write '1' to disable interrupt for event TRIGGERED[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED1 Write '1' to disable interrupt for event TRIGGERED[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED2 Write '1' to disable interrupt for event TRIGGERED[2] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED3 Write '1' to disable interrupt for event TRIGGERED[3] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED4 Write '1' to disable interrupt for event TRIGGERED[4] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED5 Write '1' to disable interrupt for event TRIGGERED[5] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED6 Write '1' to disable interrupt for event TRIGGERED[6] 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED7 Write '1' to disable interrupt for event TRIGGERED[7] 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED8 Write '1' to disable interrupt for event TRIGGERED[8] 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED9 Write '1' to disable interrupt for event TRIGGERED[9] 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED10 Write '1' to disable interrupt for event TRIGGERED[10] 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED11 Write '1' to disable interrupt for event TRIGGERED[11] 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED12 Write '1' to disable interrupt for event TRIGGERED[12] 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED13 Write '1' to disable interrupt for event TRIGGERED[13] 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED14 Write '1' to disable interrupt for event TRIGGERED[14] 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED15 Write '1' to disable interrupt for event TRIGGERED[15] 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED16 Write '1' to disable interrupt for event TRIGGERED[16] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED17 Write '1' to disable interrupt for event TRIGGERED[17] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED18 Write '1' to disable interrupt for event TRIGGERED[18] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED19 Write '1' to disable interrupt for event TRIGGERED[19] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED20 Write '1' to disable interrupt for event TRIGGERED[20] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED21 Write '1' to disable interrupt for event TRIGGERED[21] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED22 Write '1' to disable interrupt for event TRIGGERED[22] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED23 Write '1' to disable interrupt for event TRIGGERED[23] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED24 Write '1' to disable interrupt for event TRIGGERED[24] 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED25 Write '1' to disable interrupt for event TRIGGERED[25] 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED26 Write '1' to disable interrupt for event TRIGGERED[26] 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED27 Write '1' to disable interrupt for event TRIGGERED[27] 27 27 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED28 Write '1' to disable interrupt for event TRIGGERED[28] 28 28 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED29 Write '1' to disable interrupt for event TRIGGERED[29] 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED30 Write '1' to disable interrupt for event TRIGGERED[30] 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TRIGGERED31 Write '1' to disable interrupt for event TRIGGERED[31] 31 31 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND Pending interrupts 0x30C read-only 0x00000000 0x20 TRIGGERED0 Read pending status of interrupt for event TRIGGERED[0] 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED1 Read pending status of interrupt for event TRIGGERED[1] 1 1 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED2 Read pending status of interrupt for event TRIGGERED[2] 2 2 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED3 Read pending status of interrupt for event TRIGGERED[3] 3 3 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED4 Read pending status of interrupt for event TRIGGERED[4] 4 4 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED5 Read pending status of interrupt for event TRIGGERED[5] 5 5 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED6 Read pending status of interrupt for event TRIGGERED[6] 6 6 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED7 Read pending status of interrupt for event TRIGGERED[7] 7 7 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED8 Read pending status of interrupt for event TRIGGERED[8] 8 8 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED9 Read pending status of interrupt for event TRIGGERED[9] 9 9 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED10 Read pending status of interrupt for event TRIGGERED[10] 10 10 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED11 Read pending status of interrupt for event TRIGGERED[11] 11 11 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED12 Read pending status of interrupt for event TRIGGERED[12] 12 12 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED13 Read pending status of interrupt for event TRIGGERED[13] 13 13 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED14 Read pending status of interrupt for event TRIGGERED[14] 14 14 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED15 Read pending status of interrupt for event TRIGGERED[15] 15 15 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED16 Read pending status of interrupt for event TRIGGERED[16] 16 16 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED17 Read pending status of interrupt for event TRIGGERED[17] 17 17 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED18 Read pending status of interrupt for event TRIGGERED[18] 18 18 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED19 Read pending status of interrupt for event TRIGGERED[19] 19 19 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED20 Read pending status of interrupt for event TRIGGERED[20] 20 20 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED21 Read pending status of interrupt for event TRIGGERED[21] 21 21 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED22 Read pending status of interrupt for event TRIGGERED[22] 22 22 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED23 Read pending status of interrupt for event TRIGGERED[23] 23 23 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED24 Read pending status of interrupt for event TRIGGERED[24] 24 24 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED25 Read pending status of interrupt for event TRIGGERED[25] 25 25 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED26 Read pending status of interrupt for event TRIGGERED[26] 26 26 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED27 Read pending status of interrupt for event TRIGGERED[27] 27 27 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED28 Read pending status of interrupt for event TRIGGERED[28] 28 28 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED29 Read pending status of interrupt for event TRIGGERED[29] 29 29 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED30 Read pending status of interrupt for event TRIGGERED[30] 30 30 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 TRIGGERED31 Read pending status of interrupt for event TRIGGERED[31] 31 31 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 DEBUGIF Unspecified VPR_DEBUGIF read-write 0x400 DATA0 Abstract Data 0. Read/write data for argument 0 0x10 read-write 0x00000000 0x20 DATA0 Abstract Data 0 0 31 DATA1 Abstract Data 1. Read/write data for argument 1 0x14 read-write 0x00000000 0x20 DATA1 Abstract Data 1 0 31 DMCONTROL Debug Module Control 0x40 read-write 0x00000000 0x20 DMACTIVE Reset signal for the debug module. 0 0 Disabled Reset the debug module itself 0x0 Enabled Normal operation 0x1 NDMRESET Reset signal output from the debug module to the system. 1 1 Inactive Reset inactive 0x0 Active Reset active 0x1 CLRRESETHALTREQ Clear the halt on reset request. 2 2 write-only NoOperation No operation when written 0. 0x0 Clear Clears the halt on reset request 0x1 SETRESETHALTREQ Set the halt on reset request. 3 3 write-only NoOperation No operation when written 0. 0x0 Clear Sets the halt on reset request 0x1 HARTSELHI The high 10 bits of hartsel. 6 15 write-only HARTSELLO The low 10 bits of hartsel. 16 25 write-only HASEL Definition of currently selected harts. 26 26 write-only Single Single hart selected. 0x0 Multiple Multiple harts selected 0x1 ACKHAVERESET Clear the havereset. 28 28 write-only NoOperation No operation when written 0. 0x0 Clear Clears the havereset for selected harts. 0x1 HARTRESET Reset harts. 29 29 Deasserted Reset de-asserted. 0x0 Asserted Reset asserted. 0x1 RESUMEREQ Resume currently selected harts. 30 30 write-only NoOperation No operation when written 0. 0x0 Resumed Currently selected harts resumed. 0x1 HALTREQ Halt currently selected harts. 31 31 write-only Clear Clears halt request bit for all currently selected harts. 0x0 Halt Currently selected harts halted. 0x1 DMSTATUS Debug Module Status 0x44 read-only 0x00400082 0x20 VERSION Version of the debug module. 0 3 NotPresent Debug module not present. 0x0 V011 There is a Debug Module and it conforms to version 0.11 of this specifcation. 0x1 V013 There is a Debug Module and it conforms to version 0.13 of this specifcation. 0x2 NonConform There is a Debug Module but it does not conform to any available version of the spec. 0xF CONFSTRPTRVALID Configuration string. 4 4 NotRelevant The confstrptr0..confstrptr3 holds information which is not relevant to the configuration string. 0x0 Address The confstrptr0..confstrptr3 holds the address of the configuration string. 0x1 HASRESETHALTREQ Halt-on-reset support status. 5 5 No Halt-on-reset is supported. 0x0 Yes Halt-on-reset is not supported. 0x1 AUTHBUSY Authentication busy status. 6 6 No The authentication module is ready. 0x0 Yes The authentication module is busy. 0x1 AUTHENTICATED Authentication status. 7 7 No Authentication required before using the debug module. 0x0 Yes Authentication passed. 0x1 ANYHALTED Any currently selected harts halted status. 8 8 No None of the currently selected harts halted. 0x0 Yes Any of the currently selected harts halted. 0x1 ALLHALTED All currently selected harts halted status. 9 9 No Not all of the currently selected harts halted. 0x0 Yes All of the currently selected harts halted. 0x1 ANYRUNNING Any currently selected harts running status. 10 10 No None of the currently selected harts running. 0x0 Yes Any of the currently selected harts running. 0x1 ALLRUNNING All currently selected harts running status. 11 11 No Not all of the currently selected harts running. 0x0 Yes All of the currently selected harts running. 0x1 ANYUNAVAIL Any currently selected harts unavailable status. 12 12 No None of the currently selected harts unavailable. 0x0 Yes Any of the currently selected harts unavailable. 0x1 ALLUNAVAIL All currently selected harts unavailable status. 13 13 No Not all of the currently selected harts unavailable. 0x0 Yes All of the currently selected harts unavailable. 0x1 ANYNONEXISTENT Any currently selected harts nonexistent status. 14 14 No None of the currently selected harts nonexistent. 0x0 Yes Any of the currently selected harts nonexistent. 0x1 ALLNONEXISTENT All currently selected harts nonexistent status. 15 15 No Not all of the currently selected harts nonexistent. 0x0 Yes All of the currently selected harts nonexistent. 0x1 ANYRESUMEACK Any currently selected harts acknowledged last resume request. 16 16 No None of the currently selected harts acknowledged last resume request. 0x0 Yes Any of the currently selected harts acknowledged last resume request. 0x1 ALLRESUMEACK All currently selected harts acknowledged last resume 17 17 No Not all of the currently selected harts acknowledged last resume request. 0x0 Yes All of the currently selected harts acknowledged last resume request. 0x1 ANYHAVERESET Any currently selected harts have been reset and reset is not acknowledged. 18 18 No None of the currently selected harts have been reset and reset is not acknowledget. 0x0 Yes Any of the currently selected harts have been reset and reset is not acknowledge. 0x1 ALLHAVERESET All currently selected harts have been reset and reset is not acknowledge 19 19 No Not all of the currently selected harts have been reset and reset is not acknowledge. 0x0 Yes All of the currently selected harts have been reset and reset is not acknowledge. 0x1 IMPEBREAK Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. 22 22 No No implicit ebreak instruction. 0x0 Yes Implicit ebreak instruction. 0x1 HARTINFO Hart Information 0x48 read-write 0x00000000 0x20 DATAADDR Data Address 0 11 read-only DATASIZE Data Size 12 15 read-only DATAACCESS Data Access 16 16 read-only No The data registers are shadowed in the hart by CSRs. Each CSR is DXLEN bits in size, and corresponds to a single argument. 0x0 Yes The data registers are shadowed in the hart's memory map. Each register takes up 4 bytes in the memory map. 0x1 NSCRATCH Number of dscratch registers 20 23 read-only HALTSUM1 Halt Summary 1 0x4C read-write 0x00000000 0x20 HALTSUM1 Halt Summary 1 0 31 read-only HAWINDOWSEL Hart Array Window Select 0x50 read-write 0x00000000 0x20 HAWINDOWSEL The high bits of this field may be tied to 0, depending on how large the array mask register is. E.g. on a system with 48 harts only bit 0 of this field may actually be writable. 0 14 read-only HAWINDOW Hart Array Window 0x54 read-write 0x00000000 0x20 MASKDATA Mask data. 0 31 ABSTRACTCS Abstract Control and Status 0x58 read-write 0x01000002 0x20 DATACOUNT Number of data registers that are implemented as part of the abstract command interface. Valid sizes are 1..12. 0 3 read-only CMDERR Command error when the abstract command fails. 8 10 NoError No error. 0x0 Busy An abstract command was executing while command, abstractcs, or abstractauto was written, or when one of the data or progbuf registers was read or written. This status is only written if cmderr contains 0 0x1 NotSupported The requested command is notsupported, regardless of whether the hart is running or not. 0x2 Exception An exception occurred while executing the command (e.g. while executing theProgram Buffer). 0x3 HaltResume The abstract command couldn't execute because the hart wasn't in the required state (running/halted). or unavailable. 0x4 Bus The abstract command failed due to abus error (e.g. alignment, access size, or timeout). 0x5 Other The command failed for another reason. 0x7 BUSY Abstract command execution status. 12 12 read-only NotBusy Not busy. 0x0 Busy An abstract command is currently being executed. This bit is set as soon as command is written, and is not cleared until that command has completed. 0x1 PROGBUFSIZE Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. 24 28 read-only ABSTRACTCMD Abstract command 0x5C write-only 0x00000000 0x20 CONTROL This Field is interpreted in a command specific manner, described for each abstract command. 0 23 CMDTYPE The type determines the overall functionality of this abstract command. 24 31 REGACCESS Register Access Command 0x00 QUICKACCESS Quick Access Command 0x01 MEMACCESS Memory Access Command 0x02 ABSTRACTAUTO Abstract Command Autoexec 0x60 read-write 0x00000000 0x20 AUTOEXECDATA When a bit in this field is 1, read or write accesses to the corresponding data word cause the command in command to be executed again. 0 11 read-only AUTOEXECPROGBUF When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause the command in command to be executed again. 16 31 read-only 0x4 0x4 CONFSTRPTR[%s] Description collection: Configuration String Pointer [n] 0x64 read-write 0x00000000 0x20 ADDR Address 0 31 read-only NEXTDM Next Debug Module 0x74 read-write 0x00000000 0x20 ADDR Address 0 31 read-only 0x10 0x4 PROGBUF[%s] Description collection: Program Buffer [n] 0x80 read-write 0x00000000 0x20 DATA Data 0 31 read-only AUTHDATA Authentication Data 0xC0 read-write 0x00000000 0x20 DATA Data 0 31 read-only HALTSUM2 Halt Summary 2 0xD0 read-write 0x00000000 0x20 HALTSUM2 Halt Summary 2 0 31 read-only HALTSUM3 Halt Summary 3 0xD4 read-write 0x00000000 0x20 HALTSUM3 Halt Summary 3 0 31 read-only SBADDRESS3 System Bus Addres 127:96 0xDC read-write 0x00000000 0x20 ADDRESS Accesses bits 127:96 of the physical address in sbaddress (if the system address bus is that wide). 0 31 read-only SBCS System Bus Access Control and Status 0xE0 read-write 0x20000000 0x20 SBACCESS8 0 0 read-only sbaccess8 8-bit system bus accesses are supported. 0x1 SBACCESS16 1 1 read-only sbaccess16 16-bit system bus accesses are supported. 0x1 SBACCESS32 2 2 read-only sbaccess32 32-bit system bus accesses are supported. 0x1 SBACCESS64 3 3 read-only sbaccess64 64-bit system bus accesses are supported. 0x1 SBACCESS128 4 4 read-only sbaccess128 128-bit system bus accesses are supported. 0x1 SBASIZE Width of system bus addresses in bits. (0 indicates there is no bus access support.) 5 11 read-only SBERROR 12 14 read-only Normal There was no bus error. 0x0 Timeout There was a timeout. 0x1 Address A bad address was accessed. 0x2 Alignment There was an alignment error. 0x3 Size An access of unsupported size was requested. 0x4 Other Other. 0x7 SBREADONDATA 15 15 read-only sbreadondata Every read from sbdata0 automatically triggers a system bus read at the (possibly autoincremented) address. 0x1 SBAUTOINCREMENT 16 16 read-only sbautoincrement sbaddress is incremented by the access size (in bytes) selected in sbaccess after every system bus access. 0x1 SBACCESS 17 19 read-only size8 8-bit. 0x0 size16 16-bit. 0x1 size32 32-bit. 0x2 size64 64-bit. 0x3 size128 128-bit. 0x4 SBREADONADDR 20 20 read-only sbreadonaddr Every write to sbaddress0 automatically triggers a system bus read at the new address. 0x1 SBBUSY 21 21 read-only notbusy System bus master is not busy. 0x0 busy System bus master is busy. 0x1 SBBUSYERROR 22 22 read-only noerror No error. 0x0 error Debugger access attempted while one in progress. 0x1 SBVERSION 29 31 read-only version0 The System Bus interface conforms to mainline drafts of thia RISC-V External Debug Support spec older than 1 January, 2018. 0x0 version1 The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRAFT. Other values are reserved for future versions. 0x1 SBADDRESS0 System Bus Addres 31:0 0xE4 read-write 0x00000000 0x20 ADDRESS Accesses bits 31:0 of the physical address in sbaddress. 0 31 read-only SBADDRESS1 System Bus Addres 63:32 0xE8 read-write 0x00000000 0x20 ADDRESS Accesses bits 63:32 of the physical address in sbaddress (if the system address bus is that wide). 0 31 read-only SBADDRESS2 System Bus Addres 95:64 0xEC read-write 0x00000000 0x20 ADDRESS Accesses bits 95:64 of the physical address in sbaddress (if the system address bus is that wide). 0 31 read-only SBDATA0 System Bus Data 31:0 0xF0 read-write 0x00000000 0x20 DATA Accesses bits 31:0 of sbdata 0 31 read-only SBDATA1 System Bus Data 63:32 0xF4 read-write 0x00000000 0x20 DATA Accesses bits 63:32 of sbdata (if the system bus is that wide). 0 31 read-only SBDATA2 System Bus Data 95:64 0xF8 read-write 0x00000000 0x20 DATA Accesses bits 95:64 of sbdata (if the system bus is that wide). 0 31 read-only SBDATA3 System Bus Data 127:96 0xFC read-write 0x00000000 0x20 DATA Accesses bits 127:96 of sbdata (if the system bus is that wide). 0 31 read-only HALTSUM0 Halt summary 0 0x100 read-write 0x00000000 0x20 HALTSUM0 Halt summary 0 0 31 read-only CPURUN State of the CPU after a core reset 0x800 read-write 0x00000000 0x20 EN Controls CPU running state after a core reset. 0 0 Stopped CPU stopped. If this is the CPU state after a core reset, setting this bit will change the CPU state to CPU running. 0x0 Running CPU running. If this is the CPU state after a core reset, clearing this bit will change the CPU state to CPU stopped after a core reset. 0x1 INITPC Initial value of the PC at CPU start. 0x808 read-write 0x00000000 0x20 INITPC Initial value of the PC at CPU start. 0 31 GLOBAL_VPR121_S VPR peripheral registers 1 0x5F8D4000 VPR121 212 GLOBAL_CAN_NS Controller Area Network 0 0x4F8D8000 CAN 0 0x1000 registers CAN 216 CAN 0x20 TASKS_START Start the CAN peripheral. 0x000 write-only 0x00000000 0x20 TASKS_START Start the CAN peripheral. 0 0 Trigger Trigger task 0x1 TASKS_STOPREQ Request to stop the CAN peripheral 0x004 write-only 0x00000000 0x20 TASKS_STOPREQ Request to stop the CAN peripheral 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop the CAN peripheral 0x008 write-only 0x00000000 0x20 TASKS_STOP Stop the CAN peripheral 0 0 Trigger Trigger task 0x1 0x2 0x4 EVENTS_CORE[%s] Description collection: Event indicating that interrupt n triggered at CAN core 0x100 read-write 0x00000000 0x20 EVENTS_CORE Event indicating that interrupt n triggered at CAN core 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DMU Event indicating that interrupt triggered at CAN DMU 0x108 read-write 0x00000000 0x20 EVENTS_DMU Event indicating that interrupt triggered at CAN DMU 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DMA Event indicating that interrupt triggered at CAN DMA 0x10C read-write 0x00000000 0x20 EVENTS_DMA Event indicating that interrupt triggered at CAN DMA 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_READYFORSTOP Event indicating that the CAN is ready to be stopped 0x110 read-write 0x00000000 0x20 EVENTS_READYFORSTOP Event indicating that the CAN is ready to be stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 READYFORSTOP_STOP Shortcut between event READYFORSTOP and task STOP 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 CORE0 Enable or disable interrupt for event CORE[0] 0 0 Disabled Disable 0x0 Enabled Enable 0x1 CORE1 Enable or disable interrupt for event CORE[1] 1 1 Disabled Disable 0x0 Enabled Enable 0x1 DMU Enable or disable interrupt for event DMU 2 2 Disabled Disable 0x0 Enabled Enable 0x1 DMA Enable or disable interrupt for event DMA 3 3 Disabled Disable 0x0 Enabled Enable 0x1 READYFORSTOP Enable or disable interrupt for event READYFORSTOP 4 4 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 CORE0 Write '1' to enable interrupt for event CORE[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CORE1 Write '1' to enable interrupt for event CORE[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DMU Write '1' to enable interrupt for event DMU 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DMA Write '1' to enable interrupt for event DMA 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 READYFORSTOP Write '1' to enable interrupt for event READYFORSTOP 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 CORE0 Write '1' to disable interrupt for event CORE[0] 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CORE1 Write '1' to disable interrupt for event CORE[1] 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DMU Write '1' to disable interrupt for event DMU 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DMA Write '1' to disable interrupt for event DMA 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 READYFORSTOP Write '1' to disable interrupt for event READYFORSTOP 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND Pending interrupts 0x30C read-only 0x00000000 0x20 CORE0 Read pending status of interrupt for event CORE[0] 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 CORE1 Read pending status of interrupt for event CORE[1] 1 1 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 DMU Read pending status of interrupt for event DMU 2 2 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 DMA Read pending status of interrupt for event DMA 3 3 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 READYFORSTOP Read pending status of interrupt for event READYFORSTOP 4 4 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 GLOBAL_CAN_S Controller Area Network 1 0x5F8D8000 CAN 216 GLOBAL_I3C121_NS I3C 2 0x4F8DE000 I3C121 222 GLOBAL_I3C121_S I3C 3 0x5F8DE000 I3C121 222 GLOBAL_DPPIC120_NS Distributed programmable peripheral interconnect controller 0 0x4F8E1000 DPPIC 0 0x1000 registers DPPIC 0x20 2 0x008 TASKS_CHG[%s] Channel group tasks DPPIC_TASKS_CHG write-only 0x000 EN Description cluster: Enable channel group n 0x000 write-only 0x00000000 0x20 EN Enable channel group n 0 0 Trigger Trigger task 0x1 DIS Description cluster: Disable channel group n 0x004 write-only 0x00000000 0x20 DIS Disable channel group n 0 0 Trigger Trigger task 0x1 2 0x008 SUBSCRIBE_CHG[%s] Subscribe configuration for tasks DPPIC_SUBSCRIBE_CHG read-write 0x080 EN Description cluster: Subscribe configuration for task CHG[n].EN 0x000 read-write 0x00000000 0x20 CHIDX DPPI channel that task CHG[n].EN will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 DIS Description cluster: Subscribe configuration for task CHG[n].DIS 0x004 read-write 0x00000000 0x20 CHIDX DPPI channel that task CHG[n].DIS will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 CHEN Channel enable register 0x500 read-write 0x00000000 0x20 CH0 Enable or disable channel 0 0 0 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH1 Enable or disable channel 1 1 1 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH2 Enable or disable channel 2 2 2 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH3 Enable or disable channel 3 3 3 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH4 Enable or disable channel 4 4 4 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH5 Enable or disable channel 5 5 5 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH6 Enable or disable channel 6 6 6 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH7 Enable or disable channel 7 7 7 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH8 Enable or disable channel 8 8 8 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH9 Enable or disable channel 9 9 9 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH10 Enable or disable channel 10 10 10 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH11 Enable or disable channel 11 11 11 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH12 Enable or disable channel 12 12 12 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH13 Enable or disable channel 13 13 13 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH14 Enable or disable channel 14 14 14 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CH15 Enable or disable channel 15 15 15 Disabled Disable channel 0x0 Enabled Enable channel 0x1 CHENSET Channel enable set register 0x504 read-write 0x00000000 oneToSet 0x20 CH0 Channel 0 enable set register. Writing 0 has no effect. 0 0 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH1 Channel 1 enable set register. Writing 0 has no effect. 1 1 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH2 Channel 2 enable set register. Writing 0 has no effect. 2 2 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH3 Channel 3 enable set register. Writing 0 has no effect. 3 3 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH4 Channel 4 enable set register. Writing 0 has no effect. 4 4 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH5 Channel 5 enable set register. Writing 0 has no effect. 5 5 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH6 Channel 6 enable set register. Writing 0 has no effect. 6 6 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH7 Channel 7 enable set register. Writing 0 has no effect. 7 7 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH8 Channel 8 enable set register. Writing 0 has no effect. 8 8 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH9 Channel 9 enable set register. Writing 0 has no effect. 9 9 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH10 Channel 10 enable set register. Writing 0 has no effect. 10 10 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH11 Channel 11 enable set register. Writing 0 has no effect. 11 11 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH12 Channel 12 enable set register. Writing 0 has no effect. 12 12 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH13 Channel 13 enable set register. Writing 0 has no effect. 13 13 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH14 Channel 14 enable set register. Writing 0 has no effect. 14 14 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CH15 Channel 15 enable set register. Writing 0 has no effect. 15 15 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Set Write: Enable channel 0x1 CHENCLR Channel enable clear register 0x508 read-write 0x00000000 oneToClear 0x20 CH0 Channel 0 enable clear register. Writing 0 has no effect. 0 0 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH1 Channel 1 enable clear register. Writing 0 has no effect. 1 1 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH2 Channel 2 enable clear register. Writing 0 has no effect. 2 2 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH3 Channel 3 enable clear register. Writing 0 has no effect. 3 3 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH4 Channel 4 enable clear register. Writing 0 has no effect. 4 4 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH5 Channel 5 enable clear register. Writing 0 has no effect. 5 5 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH6 Channel 6 enable clear register. Writing 0 has no effect. 6 6 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH7 Channel 7 enable clear register. Writing 0 has no effect. 7 7 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH8 Channel 8 enable clear register. Writing 0 has no effect. 8 8 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH9 Channel 9 enable clear register. Writing 0 has no effect. 9 9 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH10 Channel 10 enable clear register. Writing 0 has no effect. 10 10 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH11 Channel 11 enable clear register. Writing 0 has no effect. 11 11 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH12 Channel 12 enable clear register. Writing 0 has no effect. 12 12 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH13 Channel 13 enable clear register. Writing 0 has no effect. 13 13 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH14 Channel 14 enable clear register. Writing 0 has no effect. 14 14 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 CH15 Channel 15 enable clear register. Writing 0 has no effect. 15 15 read Disabled Read: Channel disabled 0x0 Enabled Read: Channel enabled 0x1 write Clear Write: Disable channel 0x1 0x2 0x4 CHG[%s] Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled 0x800 read-write 0x00000000 0x20 CH0 Include or exclude channel 0 0 0 Excluded Exclude 0x0 Included Include 0x1 CH1 Include or exclude channel 1 1 1 Excluded Exclude 0x0 Included Include 0x1 CH2 Include or exclude channel 2 2 2 Excluded Exclude 0x0 Included Include 0x1 CH3 Include or exclude channel 3 3 3 Excluded Exclude 0x0 Included Include 0x1 CH4 Include or exclude channel 4 4 4 Excluded Exclude 0x0 Included Include 0x1 CH5 Include or exclude channel 5 5 5 Excluded Exclude 0x0 Included Include 0x1 CH6 Include or exclude channel 6 6 6 Excluded Exclude 0x0 Included Include 0x1 CH7 Include or exclude channel 7 7 7 Excluded Exclude 0x0 Included Include 0x1 CH8 Include or exclude channel 8 8 8 Excluded Exclude 0x0 Included Include 0x1 CH9 Include or exclude channel 9 9 9 Excluded Exclude 0x0 Included Include 0x1 CH10 Include or exclude channel 10 10 10 Excluded Exclude 0x0 Included Include 0x1 CH11 Include or exclude channel 11 11 11 Excluded Exclude 0x0 Included Include 0x1 CH12 Include or exclude channel 12 12 12 Excluded Exclude 0x0 Included Include 0x1 CH13 Include or exclude channel 13 13 13 Excluded Exclude 0x0 Included Include 0x1 CH14 Include or exclude channel 14 14 14 Excluded Exclude 0x0 Included Include 0x1 CH15 Include or exclude channel 15 15 15 Excluded Exclude 0x0 Included Include 0x1 GLOBAL_DPPIC120_S Distributed programmable peripheral interconnect controller 1 0x5F8E1000 GLOBAL_TIMER120_NS Timer/Counter 0 0x4F8E2000 TIMER 0 0x1000 registers TIMER120 226 TIMER 0x20 TASKS_START Start Timer 0x000 write-only 0x00000000 0x20 TASKS_START Start Timer 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop Timer 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop Timer 0 0 Trigger Trigger task 0x1 TASKS_COUNT Increment Timer (Counter mode only) 0x008 write-only 0x00000000 0x20 TASKS_COUNT Increment Timer (Counter mode only) 0 0 Trigger Trigger task 0x1 TASKS_CLEAR Clear time 0x00C write-only 0x00000000 0x20 TASKS_CLEAR Clear time 0 0 Trigger Trigger task 0x1 TASKS_SHUTDOWN Deprecated register - Shut down timer 0x010 write-only 0x00000000 0x20 TASKS_SHUTDOWN Deprecated field - Shut down timer 0 0 Trigger Trigger task 0x1 0x8 0x4 TASKS_CAPTURE[%s] Description collection: Capture Timer value to CC[n] register 0x040 write-only 0x00000000 0x20 TASKS_CAPTURE Capture Timer value to CC[n] register 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_COUNT Subscribe configuration for task COUNT 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task COUNT will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_CLEAR Subscribe configuration for task CLEAR 0x08C read-write 0x00000000 0x20 CHIDX DPPI channel that task CLEAR will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_SHUTDOWN Deprecated register - Subscribe configuration for task SHUTDOWN 0x090 read-write 0x00000000 0x20 CHIDX DPPI channel that task SHUTDOWN will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x8 0x4 SUBSCRIBE_CAPTURE[%s] Description collection: Subscribe configuration for task CAPTURE[n] 0x0C0 read-write 0x00000000 0x20 CHIDX DPPI channel that task CAPTURE[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x8 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x140 read-write 0x00000000 0x20 EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x8 0x4 PUBLISH_COMPARE[%s] Description collection: Publish configuration for event COMPARE[n] 0x1C0 read-write 0x00000000 0x20 CHIDX DPPI channel that event COMPARE[n] will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 COMPARE0_CLEAR Shortcut between event COMPARE[0] and task CLEAR 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE1_CLEAR Shortcut between event COMPARE[1] and task CLEAR 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE2_CLEAR Shortcut between event COMPARE[2] and task CLEAR 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE3_CLEAR Shortcut between event COMPARE[3] and task CLEAR 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE4_CLEAR Shortcut between event COMPARE[4] and task CLEAR 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE5_CLEAR Shortcut between event COMPARE[5] and task CLEAR 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE6_CLEAR Shortcut between event COMPARE[6] and task CLEAR 6 6 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE7_CLEAR Shortcut between event COMPARE[7] and task CLEAR 7 7 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE0_STOP Shortcut between event COMPARE[0] and task STOP 16 16 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE1_STOP Shortcut between event COMPARE[1] and task STOP 17 17 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE2_STOP Shortcut between event COMPARE[2] and task STOP 18 18 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE3_STOP Shortcut between event COMPARE[3] and task STOP 19 19 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE4_STOP Shortcut between event COMPARE[4] and task STOP 20 20 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE5_STOP Shortcut between event COMPARE[5] and task STOP 21 21 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE6_STOP Shortcut between event COMPARE[6] and task STOP 22 22 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE7_STOP Shortcut between event COMPARE[7] and task STOP 23 23 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 COMPARE0 Enable or disable interrupt for event COMPARE[0] 16 16 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE1 Enable or disable interrupt for event COMPARE[1] 17 17 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE2 Enable or disable interrupt for event COMPARE[2] 18 18 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE3 Enable or disable interrupt for event COMPARE[3] 19 19 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE4 Enable or disable interrupt for event COMPARE[4] 20 20 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE5 Enable or disable interrupt for event COMPARE[5] 21 21 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE6 Enable or disable interrupt for event COMPARE[6] 22 22 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE7 Enable or disable interrupt for event COMPARE[7] 23 23 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE4 Write '1' to enable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE5 Write '1' to enable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE6 Write '1' to enable interrupt for event COMPARE[6] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE7 Write '1' to enable interrupt for event COMPARE[7] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE4 Write '1' to disable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE5 Write '1' to disable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE6 Write '1' to disable interrupt for event COMPARE[6] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE7 Write '1' to disable interrupt for event COMPARE[7] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 MODE Timer mode selection 0x504 read-write 0x00000000 0x20 MODE Timer mode 0 1 Timer Select Timer mode 0x0 Counter Deprecated enumerator - Select Counter mode 0x1 LowPowerCounter Select Low Power Counter mode 0x2 BITMODE Configure the number of bits used by the TIMER 0x508 read-write 0x00000000 0x20 BITMODE Timer bit width 0 1 16Bit 16 bit timer bit width 0x0 08Bit 8 bit timer bit width 0x1 24Bit 24 bit timer bit width 0x2 32Bit 32 bit timer bit width 0x3 PRESCALER Timer prescaler register 0x510 read-write 0x00000004 0x20 PRESCALER Prescaler value 0 3 0x8 0x4 CC[%s] Description collection: Capture/Compare register n 0x540 read-write 0x00000000 0x20 CC Capture/Compare value 0 31 0x8 0x4 ONESHOTEN[%s] Description collection: Enable one-shot operation for Capture/Compare channel n 0x580 read-write 0x00000000 0x20 ONESHOTEN Enable one-shot operation 0 0 Disable Disable one-shot operation 0x0 Enable Enable one-shot operation 0x1 GLOBAL_TIMER120_S Timer/Counter 1 0x5F8E2000 TIMER120 226 GLOBAL_TIMER121_NS Timer/Counter 2 0x4F8E3000 TIMER121 227 GLOBAL_TIMER121_S Timer/Counter 3 0x5F8E3000 TIMER121 227 GLOBAL_PWM120_NS Pulse width modulation unit 0 0x4F8E4000 PWM 0 0x1000 registers PWM120 228 PWM 0x20 TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0x004 write-only 0x00000000 0x20 TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0 0 Trigger Trigger task 0x1 0x2 0x4 TASKS_SEQSTART[%s] Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0x008 write-only 0x00000000 0x20 TASKS_SEQSTART Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0 0 Trigger Trigger task 0x1 TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 0x010 write-only 0x00000000 0x20 TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 0 0 Trigger Trigger task 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x2 0x4 SUBSCRIBE_SEQSTART[%s] Description collection: Subscribe configuration for task SEQSTART[n] 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task SEQSTART[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_NEXTSTEP Subscribe configuration for task NEXTSTEP 0x090 read-write 0x00000000 0x20 CHIDX DPPI channel that task NEXTSTEP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_STOPPED Response to STOP task, emitted when PWM pulses are no longer generated 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED Response to STOP task, emitted when PWM pulses are no longer generated 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x2 0x4 EVENTS_SEQSTARTED[%s] Description collection: First PWM period started on sequence n 0x108 read-write 0x00000000 0x20 EVENTS_SEQSTARTED First PWM period started on sequence n 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x2 0x4 EVENTS_SEQEND[%s] Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0x110 read-write 0x00000000 0x20 EVENTS_SEQEND Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_PWMPERIODEND Emitted at the end of each PWM period 0x118 read-write 0x00000000 0x20 EVENTS_PWMPERIODEND Emitted at the end of each PWM period 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_LOOPSDONE Concatenated sequences have been played the amount of times defined in LOOP.CNT 0x11C read-write 0x00000000 0x20 EVENTS_LOOPSDONE Concatenated sequences have been played the amount of times defined in LOOP.CNT 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 0x2 0x4 PUBLISH_SEQSTARTED[%s] Description collection: Publish configuration for event SEQSTARTED[n] 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event SEQSTARTED[n] will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 0x2 0x4 PUBLISH_SEQEND[%s] Description collection: Publish configuration for event SEQEND[n] 0x190 read-write 0x00000000 0x20 CHIDX DPPI channel that event SEQEND[n] will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_PWMPERIODEND Publish configuration for event PWMPERIODEND 0x198 read-write 0x00000000 0x20 CHIDX DPPI channel that event PWMPERIODEND will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_LOOPSDONE Publish configuration for event LOOPSDONE 0x19C read-write 0x00000000 0x20 CHIDX DPPI channel that event LOOPSDONE will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 SEQEND0_STOP Shortcut between event SEQEND[n] and task STOP 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 SEQEND1_STOP Shortcut between event SEQEND[n] and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LOOPSDONE_SEQSTART0 Shortcut between event LOOPSDONE and task SEQSTART[n] 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LOOPSDONE_SEQSTART1 Shortcut between event LOOPSDONE and task SEQSTART[n] 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 SEQSTARTED0 Enable or disable interrupt for event SEQSTARTED[0] 2 2 Disabled Disable 0x0 Enabled Enable 0x1 SEQSTARTED1 Enable or disable interrupt for event SEQSTARTED[1] 3 3 Disabled Disable 0x0 Enabled Enable 0x1 SEQEND0 Enable or disable interrupt for event SEQEND[0] 4 4 Disabled Disable 0x0 Enabled Enable 0x1 SEQEND1 Enable or disable interrupt for event SEQEND[1] 5 5 Disabled Disable 0x0 Enabled Enable 0x1 PWMPERIODEND Enable or disable interrupt for event PWMPERIODEND 6 6 Disabled Disable 0x0 Enabled Enable 0x1 LOOPSDONE Enable or disable interrupt for event LOOPSDONE 7 7 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SEQSTARTED0 Write '1' to enable interrupt for event SEQSTARTED[0] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SEQSTARTED1 Write '1' to enable interrupt for event SEQSTARTED[1] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SEQEND0 Write '1' to enable interrupt for event SEQEND[0] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SEQEND1 Write '1' to enable interrupt for event SEQEND[1] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 PWMPERIODEND Write '1' to enable interrupt for event PWMPERIODEND 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 LOOPSDONE Write '1' to enable interrupt for event LOOPSDONE 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEQSTARTED0 Write '1' to disable interrupt for event SEQSTARTED[0] 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEQSTARTED1 Write '1' to disable interrupt for event SEQSTARTED[1] 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEQEND0 Write '1' to disable interrupt for event SEQEND[0] 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEQEND1 Write '1' to disable interrupt for event SEQEND[1] 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 PWMPERIODEND Write '1' to disable interrupt for event PWMPERIODEND 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 LOOPSDONE Write '1' to disable interrupt for event LOOPSDONE 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE PWM module enable register 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable PWM module 0 0 Disabled Disabled 0x0 Enabled Enable 0x1 MODE Selects operating mode of the wave counter 0x504 read-write 0x00000000 0x20 UPDOWN Selects up mode or up-and-down mode for the counter 0 0 Up Up counter, edge-aligned PWM duty cycle 0x0 UpAndDown Up and down counter, center-aligned PWM duty cycle 0x1 COUNTERTOP Value up to which the pulse generator counter counts 0x508 read-write 0x000003FF 0x20 COUNTERTOP Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. 0 14 PRESCALER Configuration for PWM_CLK 0x50C read-write 0x00000000 0x20 PRESCALER Prescaler of PWM_CLK 0 2 DIV_1 Divide by 1 (16 MHz) 0x0 DIV_2 Divide by 2 (8 MHz) 0x1 DIV_4 Divide by 4 (4 MHz) 0x2 DIV_8 Divide by 8 (2 MHz) 0x3 DIV_16 Divide by 16 (1 MHz) 0x4 DIV_32 Divide by 32 (500 kHz) 0x5 DIV_64 Divide by 64 (250 kHz) 0x6 DIV_128 Divide by 128 (125 kHz) 0x7 DECODER Configuration of the decoder 0x510 read-write 0x00000000 0x20 LOAD How a sequence is read from RAM and spread to the compare register 0 1 Common 1st half word (16-bit) used in all PWM channels 0..3 0x0 Grouped 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 0x1 Individual 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 0x2 WaveForm 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP 0x3 MODE Selects source for advancing the active sequence 8 8 RefreshCount SEQ[n].REFRESH is used to determine loading internal compare registers 0x0 NextStep NEXTSTEP task causes a new value to be loaded to internal compare registers 0x1 LOOP Number of playbacks of a loop 0x514 read-write 0x00000000 0x20 CNT Number of playbacks of pattern cycles 0 15 Disabled Looping disabled (stop at the end of the sequence) 0x0000 2 0x020 SEQ[%s] Unspecified PWM_SEQ read-write 0x520 PTR Description cluster: Beginning address in RAM of this sequence 0x000 read-write 0x00000000 0x20 PTR Beginning address in RAM of this sequence 0 31 CNT Description cluster: Number of values (duty cycles) in this sequence 0x004 read-write 0x00000000 0x20 CNT Number of values (duty cycles) in this sequence 0 14 Disabled Sequence is disabled, and shall not be started as it is empty 0x0000 REFRESH Description cluster: Number of additional PWM periods between samples loaded into compare register 0x008 read-write 0x00000001 0x20 CNT Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) 0 23 Continuous Update every PWM period 0x000000 ENDDELAY Description cluster: Time added after the sequence 0x00C read-write 0x00000000 0x20 CNT Time added after the sequence in PWM periods 0 23 PSEL Unspecified PWM_PSEL read-write 0x560 0x4 0x4 OUT[%s] Description collection: Output pin select for PWM channel n 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 GLOBAL_PWM120_S Pulse width modulation unit 1 0x5F8E4000 PWM120 228 GLOBAL_SPIS120_NS SPI Slave 0 0x4F8E5000 SPIS 0 0x1000 registers SPIS120_UARTE120 229 SPIS 0x20 TASKS_ACQUIRE Acquire SPI semaphore 0x024 write-only 0x00000000 0x20 TASKS_ACQUIRE Acquire SPI semaphore 0 0 Trigger Trigger task 0x1 TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0x028 write-only 0x00000000 0x20 TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0 0 Trigger Trigger task 0x1 SUBSCRIBE_ACQUIRE Subscribe configuration for task ACQUIRE 0x0A4 read-write 0x00000000 0x20 CHIDX DPPI channel that task ACQUIRE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_RELEASE Subscribe configuration for task RELEASE 0x0A8 read-write 0x00000000 0x20 CHIDX DPPI channel that task RELEASE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_END Granted transaction completed 0x104 read-write 0x00000000 0x20 EVENTS_END Granted transaction completed 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write 0x00000000 0x20 EVENTS_ENDRX End of RXD buffer reached 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ACQUIRED Semaphore acquired 0x128 read-write 0x00000000 0x20 EVENTS_ACQUIRED Semaphore acquired 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0x174 read-write 0x00000000 0x20 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0x178 read-write 0x00000000 0x20 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_END Publish configuration for event END 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event END will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ENDRX Publish configuration for event ENDRX 0x190 read-write 0x00000000 0x20 CHIDX DPPI channel that event ENDRX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ACQUIRED Publish configuration for event ACQUIRED 0x1A8 read-write 0x00000000 0x20 CHIDX DPPI channel that event ACQUIRED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXBUSERROR Publish configuration for event RXBUSERROR 0x1F4 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXBUSERROR Publish configuration for event TXBUSERROR 0x1F8 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 END_ACQUIRE Shortcut between event END and task ACQUIRE 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 END Write '1' to enable interrupt for event END 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACQUIRED Write '1' to enable interrupt for event ACQUIRED 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXBUSERROR Write '1' to enable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXBUSERROR Write '1' to enable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 END Write '1' to disable interrupt for event END 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACQUIRED Write '1' to disable interrupt for event ACQUIRED 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXBUSERROR Write '1' to disable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXBUSERROR Write '1' to disable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SEMSTAT Semaphore status register 0x400 read-only 0x00000001 0x20 SEMSTAT Semaphore status 0 1 Free Semaphore is free 0x0 CPU Semaphore is assigned to CPU 0x1 SPIS Semaphore is assigned to SPI slave 0x2 CPUPending Semaphore is assigned to SPI but a handover to the CPU is pending 0x3 STATUS Status from last transaction 0x440 read-write 0x00000000 0x20 OVERREAD TX buffer over-read detected, and prevented 0 0 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 write Clear Write: clear error on writing '1' 0x1 OVERFLOW RX buffer overflow detected, and prevented 1 1 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 write Clear Write: clear error on writing '1' 0x1 ENABLE Enable SPI slave 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable SPI slave 0 3 Disabled Disable SPI slave 0x0 Enabled Enable SPI slave 0x2 PSEL Unspecified SPIS_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MISO Pin select for MISO signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MOSI Pin select for MOSI signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 CSN Pin select for CSN signal 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD Unspecified SPIS_RXD read-write 0x534 PTR RXD data pointer 0x000 read-write 0x00000000 0x20 PTR RXD data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in receive buffer 0 14 AMOUNT Number of bytes received in last granted transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes received in the last granted transaction 0 14 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 TXD Unspecified SPIS_TXD read-write 0x544 PTR TXD data pointer 0x000 read-write 0x00000000 0x20 PTR TXD data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in transmit buffer 0 14 AMOUNT Number of bytes transmitted in last granted transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transmitted in last granted transaction 0 14 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 CONFIG Configuration register 0x554 read-write 0x00000000 0x20 ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0x0 LsbFirst Least significant bit shifted out first 0x1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0x0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 0x1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0x0 ActiveLow Active low 0x1 DEF Default character. Character clocked out in case of an ignored transaction. 0x55C read-write 0x00000000 0x20 DEF Default character. Character clocked out in case of an ignored transaction. 0 7 DMA Unspecified SPIS_DMA read-write 0x5B0 RX Unspecified SPIS_DMA_RX read-write 0x000 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 TX Unspecified SPIS_DMA_TX read-write 0x008 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 ORC Over-read character 0x5C0 read-write 0x00000000 0x20 ORC Over-read character. Character clocked out after an over-read of the transmit buffer. 0 7 GLOBAL_UARTE120_NS UART with EasyDMA 0 0x4F8E5000 GLOBAL_SPIS120_NS UARTE 0 0x1000 registers SPIS120_UARTE120 229 UARTE 0x20 TASKS_STARTRX Start UART receiver 0x000 write-only 0x00000000 0x20 TASKS_STARTRX Start UART receiver 0 0 Trigger Trigger task 0x1 TASKS_STOPRX Stop UART receiver 0x004 write-only 0x00000000 0x20 TASKS_STOPRX Stop UART receiver 0 0 Trigger Trigger task 0x1 TASKS_STARTTX Start UART transmitter 0x008 write-only 0x00000000 0x20 TASKS_STARTTX Start UART transmitter 0 0 Trigger Trigger task 0x1 TASKS_STOPTX Stop UART transmitter 0x00C write-only 0x00000000 0x20 TASKS_STOPTX Stop UART transmitter 0 0 Trigger Trigger task 0x1 TASKS_FLUSHRX Flush RX FIFO into RX buffer 0x02C write-only 0x00000000 0x20 TASKS_FLUSHRX Flush RX FIFO into RX buffer 0 0 Trigger Trigger task 0x1 SUBSCRIBE_STARTRX Subscribe configuration for task STARTRX 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task STARTRX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOPRX Subscribe configuration for task STOPRX 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOPRX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STARTTX Subscribe configuration for task STARTTX 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task STARTTX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOPTX Subscribe configuration for task STOPTX 0x08C read-write 0x00000000 0x20 CHIDX DPPI channel that task STOPTX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_FLUSHRX Subscribe configuration for task FLUSHRX 0x0AC read-write 0x00000000 0x20 CHIDX DPPI channel that task FLUSHRX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_CTS CTS is activated (set low). Clear To Send. 0x100 read-write 0x00000000 0x20 EVENTS_CTS CTS is activated (set low). Clear To Send. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0x104 read-write 0x00000000 0x20 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0x108 read-write 0x00000000 0x20 EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDRX Receive buffer is filled up 0x110 read-write 0x00000000 0x20 EVENTS_ENDRX Receive buffer is filled up 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXDRDY Data sent from TXD 0x11C read-write 0x00000000 0x20 EVENTS_TXDRDY Data sent from TXD 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDTX Last TX byte transmitted 0x120 read-write 0x00000000 0x20 EVENTS_ENDTX Last TX byte transmitted 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR Error detected 0x124 read-write 0x00000000 0x20 EVENTS_ERROR Error detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXTO Receiver timeout 0x144 read-write 0x00000000 0x20 EVENTS_RXTO Receiver timeout 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXSTARTED UART receiver has started 0x14C read-write 0x00000000 0x20 EVENTS_RXSTARTED UART receiver has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXSTARTED UART transmitter has started 0x150 read-write 0x00000000 0x20 EVENTS_TXSTARTED UART transmitter has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXSTOPPED Transmitter stopped 0x158 read-write 0x00000000 0x20 EVENTS_TXSTOPPED Transmitter stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0x174 read-write 0x00000000 0x20 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0x178 read-write 0x00000000 0x20 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_CTS Publish configuration for event CTS 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event CTS will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_NCTS Publish configuration for event NCTS 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event NCTS will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXDRDY Publish configuration for event RXDRDY 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXDRDY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ENDRX Publish configuration for event ENDRX 0x190 read-write 0x00000000 0x20 CHIDX DPPI channel that event ENDRX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXDRDY Publish configuration for event TXDRDY 0x19C read-write 0x00000000 0x20 CHIDX DPPI channel that event TXDRDY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ENDTX Publish configuration for event ENDTX 0x1A0 read-write 0x00000000 0x20 CHIDX DPPI channel that event ENDTX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ERROR Publish configuration for event ERROR 0x1A4 read-write 0x00000000 0x20 CHIDX DPPI channel that event ERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXTO Publish configuration for event RXTO 0x1C4 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXTO will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXSTARTED Publish configuration for event RXSTARTED 0x1CC read-write 0x00000000 0x20 CHIDX DPPI channel that event RXSTARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXSTARTED Publish configuration for event TXSTARTED 0x1D0 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXSTARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXSTOPPED Publish configuration for event TXSTOPPED 0x1D8 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXSTOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXBUSERROR Publish configuration for event RXBUSERROR 0x1F4 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXBUSERROR Publish configuration for event TXBUSERROR 0x1F8 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 ENDRX_STARTRX Shortcut between event ENDRX and task STARTRX 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 ENDRX_STOPRX Shortcut between event ENDRX and task STOPRX 6 6 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 CTS Enable or disable interrupt for event CTS 0 0 Disabled Disable 0x0 Enabled Enable 0x1 NCTS Enable or disable interrupt for event NCTS 1 1 Disabled Disable 0x0 Enabled Enable 0x1 RXDRDY Enable or disable interrupt for event RXDRDY 2 2 Disabled Disable 0x0 Enabled Enable 0x1 ENDRX Enable or disable interrupt for event ENDRX 4 4 Disabled Disable 0x0 Enabled Enable 0x1 TXDRDY Enable or disable interrupt for event TXDRDY 7 7 Disabled Disable 0x0 Enabled Enable 0x1 ENDTX Enable or disable interrupt for event ENDTX 8 8 Disabled Disable 0x0 Enabled Enable 0x1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0x0 Enabled Enable 0x1 RXTO Enable or disable interrupt for event RXTO 17 17 Disabled Disable 0x0 Enabled Enable 0x1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0x0 Enabled Enable 0x1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0x0 Enabled Enable 0x1 TXSTOPPED Enable or disable interrupt for event TXSTOPPED 22 22 Disabled Disable 0x0 Enabled Enable 0x1 RXBUSERROR Enable or disable interrupt for event RXBUSERROR 29 29 Disabled Disable 0x0 Enabled Enable 0x1 TXBUSERROR Enable or disable interrupt for event TXBUSERROR 30 30 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 CTS Write '1' to enable interrupt for event CTS 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 NCTS Write '1' to enable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXDRDY Write '1' to enable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXDRDY Write '1' to enable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDTX Write '1' to enable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXTO Write '1' to enable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXSTOPPED Write '1' to enable interrupt for event TXSTOPPED 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXBUSERROR Write '1' to enable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXBUSERROR Write '1' to enable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 CTS Write '1' to disable interrupt for event CTS 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 NCTS Write '1' to disable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXDRDY Write '1' to disable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXDRDY Write '1' to disable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDTX Write '1' to disable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXTO Write '1' to disable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXSTOPPED Write '1' to disable interrupt for event TXSTOPPED 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXBUSERROR Write '1' to disable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXBUSERROR Write '1' to disable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSRC Error source 0x480 read-write 0x00000000 oneToClear 0x20 OVERRUN Overrun error 0 0 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 PARITY Parity error 1 1 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 FRAMING Framing error occurred 2 2 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 BREAK Break condition 3 3 read NotPresent Read: error not present 0x0 Present Read: error present 0x1 ENABLE Enable UART 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable UARTE 0 3 Disabled Disable UARTE 0x0 Enabled Enable UARTE 0x8 PSEL Unspecified UARTE_PSEL read-write 0x508 RTS Pin select for RTS signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 TXD Pin select for TXD signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 CTS Pin select for CTS signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD Pin select for RXD signal 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 BAUDRATE Baud rate. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 BAUDRATE Baud rate 0 31 Baud1200 1200 baud (actual rate: 1205) 0x0004F000 Baud2400 2400 baud (actual rate: 2396) 0x0009D000 Baud4800 4800 baud (actual rate: 4808) 0x0013B000 Baud9600 9600 baud (actual rate: 9598) 0x00275000 Baud14400 14400 baud (actual rate: 14401) 0x003AF000 Baud19200 19200 baud (actual rate: 19208) 0x004EA000 Baud28800 28800 baud (actual rate: 28777) 0x0075C000 Baud31250 31250 baud 0x00800000 Baud38400 38400 baud (actual rate: 38369) 0x009D0000 Baud56000 56000 baud (actual rate: 55944) 0x00E50000 Baud57600 57600 baud (actual rate: 57554) 0x00EB0000 Baud76800 76800 baud (actual rate: 76923) 0x013A9000 Baud115200 115200 baud (actual rate: 115108) 0x01D60000 Baud230400 230400 baud (actual rate: 231884) 0x03B00000 Baud250000 250000 baud 0x04000000 Baud460800 460800 baud (actual rate: 457143) 0x07400000 Baud921600 921600 baud (actual rate: 941176) 0x0F000000 Baud1M 1 megabaud 0x10000000 RXD RXD EasyDMA channel UARTE_RXD read-write 0x534 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in receive buffer 0 14 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 14 TXD TXD EasyDMA channel UARTE_TXD read-write 0x544 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in transmit buffer 0 14 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 14 CONFIG Configuration of parity and hardware flow control 0x56C read-write 0x00000000 0x20 HWFC Hardware flow control 0 0 Disabled Disabled 0x0 Enabled Enabled 0x1 PARITY Parity 1 3 Excluded Exclude parity bit 0x0 Included Include even parity bit 0x7 STOP Stop bits 4 4 One One stop bit 0x0 Two Two stop bits 0x1 PARITYTYPE Even or odd parity type 8 8 Even Even parity 0x0 Odd Odd parity 0x1 DMA Unspecified UARTE_DMA read-write 0x5B0 RX Unspecified UARTE_DMA_RX read-write 0x000 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 TX Unspecified UARTE_DMA_TX read-write 0x008 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 GLOBAL_SPIS120_S SPI Slave 1 0x5F8E5000 SPIS120_UARTE120 229 GLOBAL_UARTE120_S UART with EasyDMA 1 0x5F8E5000 GLOBAL_SPIS120_S SPIS120_UARTE120 229 GLOBAL_SPIM120_NS Serial Peripheral Interface Master with EasyDMA 0 0x4F8E6000 SPIM 0 0x1000 registers SPIM120 230 SPIM 0x20 TASKS_START Start SPI transaction 0x010 write-only 0x00000000 0x20 TASKS_START Start SPI transaction 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop SPI transaction 0x014 write-only 0x00000000 0x20 TASKS_STOP Stop SPI transaction 0 0 Trigger Trigger task 0x1 TASKS_SUSPEND Suspend SPI transaction 0x01C write-only 0x00000000 0x20 TASKS_SUSPEND Suspend SPI transaction 0 0 Trigger Trigger task 0x1 TASKS_RESUME Resume SPI transaction 0x020 write-only 0x00000000 0x20 TASKS_RESUME Resume SPI transaction 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x090 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x094 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_SUSPEND Subscribe configuration for task SUSPEND 0x09C read-write 0x00000000 0x20 CHIDX DPPI channel that task SUSPEND will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_RESUME Subscribe configuration for task RESUME 0x0A0 read-write 0x00000000 0x20 CHIDX DPPI channel that task RESUME will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_STOPPED SPI transaction has stopped 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED SPI transaction has stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write 0x00000000 0x20 EVENTS_ENDRX End of RXD buffer reached 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_END End of RXD buffer and TXD buffer reached 0x118 read-write 0x00000000 0x20 EVENTS_END End of RXD buffer and TXD buffer reached 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDTX End of TXD buffer reached 0x120 read-write 0x00000000 0x20 EVENTS_ENDTX End of TXD buffer reached 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STARTED Transaction started 0x14C read-write 0x00000000 0x20 EVENTS_STARTED Transaction started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0x174 read-write 0x00000000 0x20 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0x178 read-write 0x00000000 0x20 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ENDRX Publish configuration for event ENDRX 0x190 read-write 0x00000000 0x20 CHIDX DPPI channel that event ENDRX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_END Publish configuration for event END 0x198 read-write 0x00000000 0x20 CHIDX DPPI channel that event END will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ENDTX Publish configuration for event ENDTX 0x1A0 read-write 0x00000000 0x20 CHIDX DPPI channel that event ENDTX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_STARTED Publish configuration for event STARTED 0x1CC read-write 0x00000000 0x20 CHIDX DPPI channel that event STARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXBUSERROR Publish configuration for event RXBUSERROR 0x1F4 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXBUSERROR Publish configuration for event TXBUSERROR 0x1F8 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 END_START Shortcut between event END and task START 17 17 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 END Write '1' to enable interrupt for event END 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDTX Write '1' to enable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STARTED Write '1' to enable interrupt for event STARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXBUSERROR Write '1' to enable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXBUSERROR Write '1' to enable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 END Write '1' to disable interrupt for event END 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDTX Write '1' to disable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STARTED Write '1' to disable interrupt for event STARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXBUSERROR Write '1' to disable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXBUSERROR Write '1' to disable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STALLSTAT Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. 0x400 read-write 0x00000000 0x20 TX Stall status for EasyDMA RAM reads 0 0 NOSTALL No stall 0x0 STALL A stall has occurred 0x1 RX Stall status for EasyDMA RAM writes 1 1 NOSTALL No stall 0x0 STALL A stall has occurred 0x1 ENABLE Enable SPIM 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable SPIM 0 3 Disabled Disable SPIM 0x0 Enabled Enable SPIM 0x7 PSEL Unspecified SPIM_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MOSI Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MISO Pin select for MISO signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 CSN Pin select for CSN 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 FREQUENCY SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 FREQUENCY SPI master data rate 0 31 K125 125 kbps 0x02000000 K250 250 kbps 0x04000000 K500 500 kbps 0x08000000 M1 1 Mbps 0x10000000 M2 2 Mbps 0x20000000 M4 4 Mbps 0x40000000 M8 8 Mbps 0x80000000 M16 16 Mbps 0x0A000000 M32 32 Mbps 0x14000000 RXD RXD EasyDMA channel SPIM_RXD read-write 0x534 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in receive buffer 0 14 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 14 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 TXD TXD EasyDMA channel SPIM_TXD read-write 0x544 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Number of bytes in transmit buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in transmit buffer 0 14 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction 0 14 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 CONFIG Configuration register 0x554 read-write 0x00000000 0x20 ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0x0 LsbFirst Least significant bit shifted out first 0x1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0x0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 0x1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0x0 ActiveLow Active low 0x1 IFTIMING Unspecified SPIM_IFTIMING read-write 0x560 RXDELAY Sample delay for input serial data on MISO 0x000 read-write 0x00000002 0x20 RXDELAY Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. 0 2 CSNDUR Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. 0x004 read-write 0x00000002 0x20 CSNDUR Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). 0 7 CSNPOL Polarity of CSN output 0x568 read-write 0x00000000 0x20 CSNPOL Polarity of CSN output 0 0 LOW Active low (idle state high) 0x0 HIGH Active high (idle state low) 0x1 PSELDCX Pin select for DCX signal 0x56C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 DCXCNT DCX configuration 0x570 read-write 0x00000000 0x20 DCXCNT This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. 0 3 DMA Unspecified SPIM_DMA read-write 0x5B0 RX Unspecified SPIM_DMA_RX read-write 0x000 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 TX Unspecified SPIM_DMA_TX read-write 0x008 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 ORC Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT 0x5C0 read-write 0x00000000 0x20 ORC Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. 0 7 GLOBAL_SPIM120_S Serial Peripheral Interface Master with EasyDMA 1 0x5F8E6000 SPIM120 230 GLOBAL_SPIM121_NS Serial Peripheral Interface Master with EasyDMA 2 0x4F8E7000 SPIM121 231 GLOBAL_SPIM121_S Serial Peripheral Interface Master with EasyDMA 3 0x5F8E7000 SPIM121 231 GLOBAL_VPR130_NS VPR peripheral registers 2 0x4F908000 VPR130 264 GLOBAL_VPR130_S VPR peripheral registers 3 0x5F908000 VPR130 264 GLOBAL_IPCT130_NS IPCT APB registers 2 0x4F921000 IPCT130_0 289 GLOBAL_IPCT130_S IPCT APB registers 3 0x5F921000 IPCT130_0 289 GLOBAL_DPPIC130_NS Distributed programmable peripheral interconnect controller 2 0x4F922000 GLOBAL_DPPIC130_S Distributed programmable peripheral interconnect controller 3 0x5F922000 GLOBAL_MUTEX130_NS MUTEX 1 0x4F927000 GLOBAL_RTC130_NS Real-time counter 0 0x4F928000 RTC 0 0x1000 registers RTC130 296 RTC 0x20 TASKS_START Start RTC counter 0x000 write-only 0x00000000 0x20 TASKS_START Start RTC counter 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop RTC counter 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop RTC counter 0 0 Trigger Trigger task 0x1 TASKS_CLEAR Clear RTC counter 0x008 write-only 0x00000000 0x20 TASKS_CLEAR Clear RTC counter 0 0 Trigger Trigger task 0x1 TASKS_TRIGOVRFLW Set counter to: maximum value - 0xF 0x00C write-only 0x00000000 0x20 TASKS_TRIGOVRFLW Set counter to: maximum value - 0xF 0 0 Trigger Trigger task 0x1 0x8 0x4 TASKS_CAPTURE[%s] Description collection: Capture RTC counter to CC[n] register 0x040 write-only 0x00000000 0x20 TASKS_CAPTURE Capture RTC counter to CC[n] register 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_CLEAR Subscribe configuration for task CLEAR 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task CLEAR will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_TRIGOVRFLW Subscribe configuration for task TRIGOVRFLW 0x08C read-write 0x00000000 0x20 CHIDX DPPI channel that task TRIGOVRFLW will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 0x8 0x4 SUBSCRIBE_CAPTURE[%s] Description collection: Subscribe configuration for task CAPTURE[n] 0x0C0 read-write 0x00000000 0x20 CHIDX DPPI channel that task CAPTURE[n] will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_TICK Event on counter increment 0x100 read-write 0x00000000 0x20 EVENTS_TICK Event on counter increment 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_OVRFLW Event on counter overflow 0x104 read-write 0x00000000 0x20 EVENTS_OVRFLW Event on counter overflow 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 0x8 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x140 read-write 0x00000000 0x20 EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_TICK Publish configuration for event TICK 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event TICK will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_OVRFLW Publish configuration for event OVRFLW 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event OVRFLW will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 0x8 0x4 PUBLISH_COMPARE[%s] Description collection: Publish configuration for event COMPARE[n] 0x1C0 read-write 0x00000000 0x20 CHIDX DPPI channel that event COMPARE[n] will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 COMPARE0_CLEAR Shortcut between event COMPARE[0] and task CLEAR 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE1_CLEAR Shortcut between event COMPARE[1] and task CLEAR 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE2_CLEAR Shortcut between event COMPARE[2] and task CLEAR 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE3_CLEAR Shortcut between event COMPARE[3] and task CLEAR 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE4_CLEAR Shortcut between event COMPARE[4] and task CLEAR 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE5_CLEAR Shortcut between event COMPARE[5] and task CLEAR 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE6_CLEAR Shortcut between event COMPARE[6] and task CLEAR 6 6 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 COMPARE7_CLEAR Shortcut between event COMPARE[7] and task CLEAR 7 7 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 TICK Write '1' to enable interrupt for event TICK 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 OVRFLW Write '1' to enable interrupt for event OVRFLW 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE4 Write '1' to enable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE5 Write '1' to enable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE6 Write '1' to enable interrupt for event COMPARE[6] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE7 Write '1' to enable interrupt for event COMPARE[7] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 TICK Write '1' to disable interrupt for event TICK 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 OVRFLW Write '1' to disable interrupt for event OVRFLW 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE4 Write '1' to disable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE5 Write '1' to disable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE6 Write '1' to disable interrupt for event COMPARE[6] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE7 Write '1' to disable interrupt for event COMPARE[7] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 EVTEN Enable or disable event routing 0x340 read-write 0x00000000 0x20 TICK Enable or disable event routing for event TICK 0 0 Disabled Disable 0x0 Enabled Enable 0x1 OVRFLW Enable or disable event routing for event OVRFLW 1 1 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE0 Enable or disable event routing for event COMPARE[0] 16 16 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE1 Enable or disable event routing for event COMPARE[1] 17 17 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE2 Enable or disable event routing for event COMPARE[2] 18 18 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE3 Enable or disable event routing for event COMPARE[3] 19 19 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE4 Enable or disable event routing for event COMPARE[4] 20 20 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE5 Enable or disable event routing for event COMPARE[5] 21 21 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE6 Enable or disable event routing for event COMPARE[6] 22 22 Disabled Disable 0x0 Enabled Enable 0x1 COMPARE7 Enable or disable event routing for event COMPARE[7] 23 23 Disabled Disable 0x0 Enabled Enable 0x1 EVTENSET Enable event routing 0x344 read-write 0x00000000 0x20 TICK Write '1' to enable event routing for event TICK 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 OVRFLW Write '1' to enable event routing for event OVRFLW 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE0 Write '1' to enable event routing for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE1 Write '1' to enable event routing for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE2 Write '1' to enable event routing for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE3 Write '1' to enable event routing for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE4 Write '1' to enable event routing for event COMPARE[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE5 Write '1' to enable event routing for event COMPARE[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE6 Write '1' to enable event routing for event COMPARE[6] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COMPARE7 Write '1' to enable event routing for event COMPARE[7] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 EVTENCLR Disable event routing 0x348 read-write 0x00000000 0x20 TICK Write '1' to disable event routing for event TICK 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 OVRFLW Write '1' to disable event routing for event OVRFLW 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE0 Write '1' to disable event routing for event COMPARE[0] 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE1 Write '1' to disable event routing for event COMPARE[1] 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE2 Write '1' to disable event routing for event COMPARE[2] 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE3 Write '1' to disable event routing for event COMPARE[3] 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE4 Write '1' to disable event routing for event COMPARE[4] 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE5 Write '1' to disable event routing for event COMPARE[5] 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE6 Write '1' to disable event routing for event COMPARE[6] 22 22 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COMPARE7 Write '1' to disable event routing for event COMPARE[7] 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COUNTER Current counter value 0x504 read-only 0x00000000 0x20 COUNTER Counter value 0 23 PRESCALER 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. 0x508 read-write 0x00000000 0x20 PRESCALER Prescaler value 0 11 0x8 0x4 CC[%s] Description collection: Compare register n 0x540 read-write 0x00000000 0x20 COMPARE Compare value 0 23 GLOBAL_RTC130_S Real-time counter 1 0x5F928000 RTC130 296 GLOBAL_RTC131_NS Real-time counter 2 0x4F929000 RTC131 297 GLOBAL_RTC131_S Real-time counter 3 0x5F929000 RTC131 297 GLOBAL_WDT131_NS Watchdog Timer 0 0x4F92B000 WDT 0 0x1000 registers WDT131 299 WDT 0x20 TASKS_START Start WDT 0x000 write-only 0x00000000 0x20 TASKS_START Start WDT 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop WDT 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop WDT 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_TIMEOUT Watchdog timeout 0x100 read-write 0x00000000 0x20 EVENTS_TIMEOUT Watchdog timeout 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED Watchdog stopped 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED Watchdog stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_TIMEOUT Publish configuration for event TIMEOUT 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event TIMEOUT will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 TIMEOUT Write '1' to enable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 TIMEOUT Write '1' to disable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 NMIENSET Enable interrupt 0x324 read-write 0x00000000 0x20 TIMEOUT Write '1' to enable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 NMIENCLR Disable interrupt 0x328 read-write 0x00000000 0x20 TIMEOUT Write '1' to disable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RUNSTATUS Run status 0x400 read-only 0x00000000 0x20 RUNSTATUSWDT Indicates whether or not WDT is running 0 0 NotRunning Watchdog is not running 0x0 Running Watchdog is running 0x1 REQSTATUS Request status 0x404 read-only 0x00000001 0x20 RR0 Request status for RR[0] register 0 0 DisabledOrRequested RR[0] register is not enabled, or are already requesting reload 0x0 EnabledAndUnrequested RR[0] register is enabled, and are not yet requesting reload 0x1 RR1 Request status for RR[1] register 1 1 DisabledOrRequested RR[1] register is not enabled, or are already requesting reload 0x0 EnabledAndUnrequested RR[1] register is enabled, and are not yet requesting reload 0x1 RR2 Request status for RR[2] register 2 2 DisabledOrRequested RR[2] register is not enabled, or are already requesting reload 0x0 EnabledAndUnrequested RR[2] register is enabled, and are not yet requesting reload 0x1 RR3 Request status for RR[3] register 3 3 DisabledOrRequested RR[3] register is not enabled, or are already requesting reload 0x0 EnabledAndUnrequested RR[3] register is enabled, and are not yet requesting reload 0x1 RR4 Request status for RR[4] register 4 4 DisabledOrRequested RR[4] register is not enabled, or are already requesting reload 0x0 EnabledAndUnrequested RR[4] register is enabled, and are not yet requesting reload 0x1 RR5 Request status for RR[5] register 5 5 DisabledOrRequested RR[5] register is not enabled, or are already requesting reload 0x0 EnabledAndUnrequested RR[5] register is enabled, and are not yet requesting reload 0x1 RR6 Request status for RR[6] register 6 6 DisabledOrRequested RR[6] register is not enabled, or are already requesting reload 0x0 EnabledAndUnrequested RR[6] register is enabled, and are not yet requesting reload 0x1 RR7 Request status for RR[7] register 7 7 DisabledOrRequested RR[7] register is not enabled, or are already requesting reload 0x0 EnabledAndUnrequested RR[7] register is enabled, and are not yet requesting reload 0x1 CRV Counter reload value 0x504 read-write 0xFFFFFFFF 0x20 CRV Counter reload value in number of cycles of the 32.768 kHz clock 0 31 RREN Enable register for reload request registers 0x508 read-write 0x00000001 0x20 RR0 Enable or disable RR[0] register 0 0 Disabled Disable RR[0] register 0x0 Enabled Enable RR[0] register 0x1 RR1 Enable or disable RR[1] register 1 1 Disabled Disable RR[1] register 0x0 Enabled Enable RR[1] register 0x1 RR2 Enable or disable RR[2] register 2 2 Disabled Disable RR[2] register 0x0 Enabled Enable RR[2] register 0x1 RR3 Enable or disable RR[3] register 3 3 Disabled Disable RR[3] register 0x0 Enabled Enable RR[3] register 0x1 RR4 Enable or disable RR[4] register 4 4 Disabled Disable RR[4] register 0x0 Enabled Enable RR[4] register 0x1 RR5 Enable or disable RR[5] register 5 5 Disabled Disable RR[5] register 0x0 Enabled Enable RR[5] register 0x1 RR6 Enable or disable RR[6] register 6 6 Disabled Disable RR[6] register 0x0 Enabled Enable RR[6] register 0x1 RR7 Enable or disable RR[7] register 7 7 Disabled Disable RR[7] register 0x0 Enabled Enable RR[7] register 0x1 CONFIG Configuration register 0x50C read-write 0x00000001 0x20 SLEEP Configure WDT to either be paused, or kept running, while the CPU is sleeping 0 0 Pause Pause WDT while the CPU is sleeping 0x0 Run Keep WDT running while the CPU is sleeping 0x1 HALT Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger 3 3 Pause Pause WDT while the CPU is halted by the debugger 0x0 Run Keep WDT running while the CPU is halted by the debugger 0x1 STOPEN Allow stopping WDT 6 6 Disable Do not allow stopping WDT 0x0 Enable Allow stopping WDT 0x1 TSEN Task stop enable 0x520 write-only 0x00000000 0x20 TSEN Allow stopping WDT 0 31 Enable Value to allow stopping WDT 0x6E524635 0x8 0x4 RR[%s] Description collection: Reload request n 0x600 write-only 0x00000000 0x20 RR Reload request register 0 31 Reload Value to request a reload of the watchdog timer 0x6E524635 GLOBAL_WDT131_S Watchdog Timer 1 0x5F92B000 WDT131 299 GLOBAL_WDT132_NS Watchdog Timer 2 0x4F92C000 WDT132 300 GLOBAL_WDT132_S Watchdog Timer 3 0x5F92C000 WDT132 300 GLOBAL_P0_NS GPIO Port 0 0x4F938000 GPIO 0 0x200 registers GPIO 0x20 OUT Write GPIO port 0x000 read-write 0x00000000 0x20 PIN0 Pin 0 0 0 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN1 Pin 1 1 1 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN2 Pin 2 2 2 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN3 Pin 3 3 3 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN4 Pin 4 4 4 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN5 Pin 5 5 5 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN6 Pin 6 6 6 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN7 Pin 7 7 7 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN8 Pin 8 8 8 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN9 Pin 9 9 9 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN10 Pin 10 10 10 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN11 Pin 11 11 11 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN12 Pin 12 12 12 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN13 Pin 13 13 13 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN14 Pin 14 14 14 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN15 Pin 15 15 15 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN16 Pin 16 16 16 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN17 Pin 17 17 17 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN18 Pin 18 18 18 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN19 Pin 19 19 19 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN20 Pin 20 20 20 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN21 Pin 21 21 21 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN22 Pin 22 22 22 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN23 Pin 23 23 23 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN24 Pin 24 24 24 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN25 Pin 25 25 25 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN26 Pin 26 26 26 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN27 Pin 27 27 27 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN28 Pin 28 28 28 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN29 Pin 29 29 29 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN30 Pin 30 30 30 Low Pin driver is low 0x0 High Pin driver is high 0x1 PIN31 Pin 31 31 31 Low Pin driver is low 0x0 High Pin driver is high 0x1 OUTSET Set individual bits in GPIO port 0x004 read-write 0x00000000 oneToSet 0x20 PIN0 Pin 0 0 0 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 0x1 OUTCLR Clear individual bits in GPIO port 0x008 read-write 0x00000000 oneToClear 0x20 PIN0 Pin 0 0 0 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0x0 High Read: pin driver is high 0x1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 0x1 IN Read GPIO port 0x00C read-only 0x00000000 0x20 PIN0 Pin 0 0 0 Low Pin input is low 0x0 High Pin input is high 0x1 PIN1 Pin 1 1 1 Low Pin input is low 0x0 High Pin input is high 0x1 PIN2 Pin 2 2 2 Low Pin input is low 0x0 High Pin input is high 0x1 PIN3 Pin 3 3 3 Low Pin input is low 0x0 High Pin input is high 0x1 PIN4 Pin 4 4 4 Low Pin input is low 0x0 High Pin input is high 0x1 PIN5 Pin 5 5 5 Low Pin input is low 0x0 High Pin input is high 0x1 PIN6 Pin 6 6 6 Low Pin input is low 0x0 High Pin input is high 0x1 PIN7 Pin 7 7 7 Low Pin input is low 0x0 High Pin input is high 0x1 PIN8 Pin 8 8 8 Low Pin input is low 0x0 High Pin input is high 0x1 PIN9 Pin 9 9 9 Low Pin input is low 0x0 High Pin input is high 0x1 PIN10 Pin 10 10 10 Low Pin input is low 0x0 High Pin input is high 0x1 PIN11 Pin 11 11 11 Low Pin input is low 0x0 High Pin input is high 0x1 PIN12 Pin 12 12 12 Low Pin input is low 0x0 High Pin input is high 0x1 PIN13 Pin 13 13 13 Low Pin input is low 0x0 High Pin input is high 0x1 PIN14 Pin 14 14 14 Low Pin input is low 0x0 High Pin input is high 0x1 PIN15 Pin 15 15 15 Low Pin input is low 0x0 High Pin input is high 0x1 PIN16 Pin 16 16 16 Low Pin input is low 0x0 High Pin input is high 0x1 PIN17 Pin 17 17 17 Low Pin input is low 0x0 High Pin input is high 0x1 PIN18 Pin 18 18 18 Low Pin input is low 0x0 High Pin input is high 0x1 PIN19 Pin 19 19 19 Low Pin input is low 0x0 High Pin input is high 0x1 PIN20 Pin 20 20 20 Low Pin input is low 0x0 High Pin input is high 0x1 PIN21 Pin 21 21 21 Low Pin input is low 0x0 High Pin input is high 0x1 PIN22 Pin 22 22 22 Low Pin input is low 0x0 High Pin input is high 0x1 PIN23 Pin 23 23 23 Low Pin input is low 0x0 High Pin input is high 0x1 PIN24 Pin 24 24 24 Low Pin input is low 0x0 High Pin input is high 0x1 PIN25 Pin 25 25 25 Low Pin input is low 0x0 High Pin input is high 0x1 PIN26 Pin 26 26 26 Low Pin input is low 0x0 High Pin input is high 0x1 PIN27 Pin 27 27 27 Low Pin input is low 0x0 High Pin input is high 0x1 PIN28 Pin 28 28 28 Low Pin input is low 0x0 High Pin input is high 0x1 PIN29 Pin 29 29 29 Low Pin input is low 0x0 High Pin input is high 0x1 PIN30 Pin 30 30 30 Low Pin input is low 0x0 High Pin input is high 0x1 PIN31 Pin 31 31 31 Low Pin input is low 0x0 High Pin input is high 0x1 DIR Direction of GPIO pins 0x010 read-write 0x00000000 0x20 PIN0 Pin 0 0 0 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN1 Pin 1 1 1 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN2 Pin 2 2 2 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN3 Pin 3 3 3 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN4 Pin 4 4 4 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN5 Pin 5 5 5 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN6 Pin 6 6 6 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN7 Pin 7 7 7 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN8 Pin 8 8 8 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN9 Pin 9 9 9 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN10 Pin 10 10 10 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN11 Pin 11 11 11 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN12 Pin 12 12 12 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN13 Pin 13 13 13 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN14 Pin 14 14 14 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN15 Pin 15 15 15 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN16 Pin 16 16 16 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN17 Pin 17 17 17 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN18 Pin 18 18 18 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN19 Pin 19 19 19 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN20 Pin 20 20 20 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN21 Pin 21 21 21 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN22 Pin 22 22 22 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN23 Pin 23 23 23 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN24 Pin 24 24 24 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN25 Pin 25 25 25 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN26 Pin 26 26 26 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN27 Pin 27 27 27 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN28 Pin 28 28 28 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN29 Pin 29 29 29 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN30 Pin 30 30 30 Input Pin set as input 0x0 Output Pin set as output 0x1 PIN31 Pin 31 31 31 Input Pin set as input 0x0 Output Pin set as output 0x1 DIRSET DIR set register 0x014 read-write 0x00000000 oneToSet 0x20 PIN0 Set as output pin 0 0 0 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN1 Set as output pin 1 1 1 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN2 Set as output pin 2 2 2 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN3 Set as output pin 3 3 3 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN4 Set as output pin 4 4 4 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN5 Set as output pin 5 5 5 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN6 Set as output pin 6 6 6 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN7 Set as output pin 7 7 7 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN8 Set as output pin 8 8 8 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN9 Set as output pin 9 9 9 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN10 Set as output pin 10 10 10 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN11 Set as output pin 11 11 11 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN12 Set as output pin 12 12 12 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN13 Set as output pin 13 13 13 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN14 Set as output pin 14 14 14 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN15 Set as output pin 15 15 15 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN16 Set as output pin 16 16 16 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN17 Set as output pin 17 17 17 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN18 Set as output pin 18 18 18 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN19 Set as output pin 19 19 19 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN20 Set as output pin 20 20 20 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN21 Set as output pin 21 21 21 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN22 Set as output pin 22 22 22 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN23 Set as output pin 23 23 23 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN24 Set as output pin 24 24 24 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN25 Set as output pin 25 25 25 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN26 Set as output pin 26 26 26 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN27 Set as output pin 27 27 27 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN28 Set as output pin 28 28 28 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN29 Set as output pin 29 29 29 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN30 Set as output pin 30 30 30 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 PIN31 Set as output pin 31 31 31 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 0x1 DIRCLR DIR clear register 0x018 read-write 0x00000000 oneToClear 0x20 PIN0 Set as input pin 0 0 0 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN1 Set as input pin 1 1 1 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN2 Set as input pin 2 2 2 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN3 Set as input pin 3 3 3 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN4 Set as input pin 4 4 4 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN5 Set as input pin 5 5 5 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN6 Set as input pin 6 6 6 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN7 Set as input pin 7 7 7 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN8 Set as input pin 8 8 8 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN9 Set as input pin 9 9 9 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN10 Set as input pin 10 10 10 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN11 Set as input pin 11 11 11 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN12 Set as input pin 12 12 12 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN13 Set as input pin 13 13 13 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN14 Set as input pin 14 14 14 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN15 Set as input pin 15 15 15 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN16 Set as input pin 16 16 16 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN17 Set as input pin 17 17 17 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN18 Set as input pin 18 18 18 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN19 Set as input pin 19 19 19 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN20 Set as input pin 20 20 20 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN21 Set as input pin 21 21 21 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN22 Set as input pin 22 22 22 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN23 Set as input pin 23 23 23 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN24 Set as input pin 24 24 24 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN25 Set as input pin 25 25 25 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN26 Set as input pin 26 26 26 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN27 Set as input pin 27 27 27 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN28 Set as input pin 28 28 28 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN29 Set as input pin 29 29 29 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN30 Set as input pin 30 30 30 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 PIN31 Set as input pin 31 31 31 read Input Read: pin set as input 0x0 Output Read: pin set as output 0x1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 0x1 LATCH Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers 0x020 read-write 0x00000000 0x20 PIN0 Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. 0 0 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN1 Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. 1 1 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN2 Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. 2 2 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN3 Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. 3 3 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN4 Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. 4 4 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN5 Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. 5 5 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN6 Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. 6 6 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN7 Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. 7 7 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN8 Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. 8 8 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN9 Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. 9 9 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN10 Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. 10 10 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN11 Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. 11 11 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN12 Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. 12 12 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN13 Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. 13 13 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN14 Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. 14 14 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN15 Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. 15 15 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN16 Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. 16 16 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN17 Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. 17 17 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN18 Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. 18 18 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN19 Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. 19 19 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN20 Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. 20 20 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN21 Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. 21 21 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN22 Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. 22 22 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN23 Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. 23 23 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN24 Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. 24 24 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN25 Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. 25 25 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN26 Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. 26 26 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN27 Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. 27 27 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN28 Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. 28 28 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN29 Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. 29 29 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN30 Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. 30 30 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 PIN31 Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. 31 31 NotLatched Criteria has not been met 0x0 Latched Criteria has been met 0x1 DETECTMODE Select between default DETECT signal behavior and LDETECT mode 0x024 read-write 0x00000000 0x20 DETECTMODE Select between default DETECT signal behavior and LDETECT mode 0 0 Default DETECT directly connected to PIN DETECT signals 0x0 LDETECT Use the latched LDETECT behavior 0x1 RETAIN Enable retention for those GPIO registers marked as retained 0x028 read-write 0x0000000C 0x20 APPLICAION Enable retention for GPIO registers for Application domain 2 2 Disabled Retention disabled 0x0 Enabled Retention enabled 0x1 RADIOCORE Enable retention for GPIO registers for Radio core 3 3 Disabled Retention disabled 0x0 Enabled Retention enabled 0x1 PORTCNF Unspecified GPIO_PORTCNF read-write 0x030 DRIVECTRL Drive control for impedance matching of the pins in this port 0x00 read-write 0x00000000 0x20 IMPEDANCE50 Enable 50 ohms impedance to the pins in this port 0 0 Disable Disabled 0x0 Enable Enable 0x1 IMPEDANCE100 Enable 100 ohms impedance to the pins in this port 1 1 Disable Disabled 0x0 Enable Enable 0x1 IMPEDANCE200 Enable 200 ohms impedance to the pins in this port 2 2 Disable Disabled 0x0 Enable Enable 0x1 IMPEDANCE400 Enable 400 ohms impedance to the pins in this port 3 3 Disable Disabled 0x0 Enable Enable 0x1 IMPEDANCE800 Enable 800 ohms impedance to the pins in this port 4 4 Disable Disabled 0x0 Enable Enable 0x1 IMPEDANCE1600 Enable 1600 ohms impedance to the pins in this port 5 5 Disable Disabled 0x0 Enable Enable 0x1 0x20 0x4 PIN_CNF[%s] Description collection: Pin n configuration of GPIO pin 0x080 read-write 0x00000002 0x20 DIR Pin direction. Same physical register as DIR register 0 0 Input Configure pin as an input pin 0x0 Output Configure pin as an output pin 0x1 INPUT Connect or disconnect input buffer 1 1 Connect Connect input buffer 0x0 Disconnect Disconnect input buffer 0x1 PULL Pull configuration 2 3 Disabled No pull 0x0 Pulldown Pull down on pin 0x1 Pullup Pull up on pin 0x3 DRIVE0 Drive configuration for '0' 8 9 S0 Standard '0' 0x0 H0 High drive '0' 0x1 D0 Disconnect '0'(normally used for wired-or connections) 0x2 E0 Extra high drive '0' 0x3 DRIVE1 Drive configuration for '1' 10 11 S1 Standard '1' 0x0 H1 High drive '1' 0x1 D1 Disconnect '1'(normally used for wired-or connections) 0x2 E1 Extra high drive '1' 0x3 SENSE Pin sensing mechanism 16 17 Disabled Disabled 0x0 High Sense for high level 0x2 Low Sense for low level 0x3 CLOCKPIN Enable clock on the pin. 31 31 Disabled Clock disabled 0x0 Enabled Clock enabled 0x1 GLOBAL_P1_NS GPIO Port 1 0x4F938200 GLOBAL_P2_NS GPIO Port 2 0x4F938400 GLOBAL_P6_NS GPIO Port 3 0x4F938C00 GLOBAL_P7_NS GPIO Port 4 0x4F938E00 GLOBAL_P0_S GPIO Port 5 0x5F938000 GLOBAL_P1_S GPIO Port 6 0x5F938200 GLOBAL_P2_S GPIO Port 7 0x5F938400 GLOBAL_P6_S GPIO Port 8 0x5F938C00 GLOBAL_P7_S GPIO Port 9 0x5F938E00 GLOBAL_P9_NS GPIO Port 10 0x4F939200 GLOBAL_P9_S GPIO Port 11 0x5F939200 GLOBAL_DPPIC131_NS Distributed programmable peripheral interconnect controller 4 0x4F981000 GLOBAL_DPPIC131_S Distributed programmable peripheral interconnect controller 5 0x5F981000 GLOBAL_SAADC_NS Analog to Digital Converter 0 0x4F982000 SAADC 0 0x1000 registers SAADC 386 SAADC 0x20 TASKS_START Start the ADC and prepare the result buffer in RAM 0x000 write-only 0x00000000 0x20 TASKS_START Start the ADC and prepare the result buffer in RAM 0 0 Trigger Trigger task 0x1 TASKS_SAMPLE Take one ADC sample, if scan is enabled all channels are sampled 0x004 write-only 0x00000000 0x20 TASKS_SAMPLE Take one ADC sample, if scan is enabled all channels are sampled 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop the ADC and terminate any on-going conversion 0x008 write-only 0x00000000 0x20 TASKS_STOP Stop the ADC and terminate any on-going conversion 0 0 Trigger Trigger task 0x1 TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0x00C write-only 0x00000000 0x20 TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_SAMPLE Subscribe configuration for task SAMPLE 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task SAMPLE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_CALIBRATEOFFSET Subscribe configuration for task CALIBRATEOFFSET 0x08C read-write 0x00000000 0x20 CHIDX DPPI channel that task CALIBRATEOFFSET will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_STARTED The ADC has started 0x100 read-write 0x00000000 0x20 EVENTS_STARTED The ADC has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_END The ADC has filled up the Result buffer 0x104 read-write 0x00000000 0x20 EVENTS_END The ADC has filled up the Result buffer 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DONE A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 0x108 read-write 0x00000000 0x20 EVENTS_DONE A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RESULTDONE A result is ready to get transferred to RAM. 0x10C read-write 0x00000000 0x20 EVENTS_RESULTDONE A result is ready to get transferred to RAM. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CALIBRATEDONE Calibration is complete 0x110 read-write 0x00000000 0x20 EVENTS_CALIBRATEDONE Calibration is complete 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED The ADC has stopped 0x114 read-write 0x00000000 0x20 EVENTS_STOPPED The ADC has stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 8 0x008 EVENTS_CH[%s] Peripheral events. GLOBAL_SAADC_EVENTS_CH read-write 0x118 LIMITH Description cluster: Last results is equal or above CH[n].LIMIT.HIGH 0x000 read-write 0x00000000 0x20 LIMITH Last results is equal or above CH[n].LIMIT.HIGH 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 LIMITL Description cluster: Last results is equal or below CH[n].LIMIT.LOW 0x004 read-write 0x00000000 0x20 LIMITL Last results is equal or below CH[n].LIMIT.LOW 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_STARTED Publish configuration for event STARTED 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event STARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_END Publish configuration for event END 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event END will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_DONE Publish configuration for event DONE 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event DONE will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RESULTDONE Publish configuration for event RESULTDONE 0x18C read-write 0x00000000 0x20 CHIDX DPPI channel that event RESULTDONE will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_CALIBRATEDONE Publish configuration for event CALIBRATEDONE 0x190 read-write 0x00000000 0x20 CHIDX DPPI channel that event CALIBRATEDONE will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x194 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 8 0x008 PUBLISH_CH[%s] Publish configuration for events GLOBAL_SAADC_PUBLISH_CH read-write 0x198 LIMITH Description cluster: Publish configuration for event CH[n].LIMITH 0x000 read-write 0x00000000 0x20 CHIDX DPPI channel that event CH[n].LIMITH will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 LIMITL Description cluster: Publish configuration for event CH[n].LIMITL 0x004 read-write 0x00000000 0x20 CHIDX DPPI channel that event CH[n].LIMITL will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STARTED Enable or disable interrupt for event STARTED 0 0 Disabled Disable 0x0 Enabled Enable 0x1 END Enable or disable interrupt for event END 1 1 Disabled Disable 0x0 Enabled Enable 0x1 DONE Enable or disable interrupt for event DONE 2 2 Disabled Disable 0x0 Enabled Enable 0x1 RESULTDONE Enable or disable interrupt for event RESULTDONE 3 3 Disabled Disable 0x0 Enabled Enable 0x1 CALIBRATEDONE Enable or disable interrupt for event CALIBRATEDONE 4 4 Disabled Disable 0x0 Enabled Enable 0x1 STOPPED Enable or disable interrupt for event STOPPED 5 5 Disabled Disable 0x0 Enabled Enable 0x1 CH0LIMITH Enable or disable interrupt for event CH0LIMITH 6 6 Disabled Disable 0x0 Enabled Enable 0x1 CH0LIMITL Enable or disable interrupt for event CH0LIMITL 7 7 Disabled Disable 0x0 Enabled Enable 0x1 CH1LIMITH Enable or disable interrupt for event CH1LIMITH 8 8 Disabled Disable 0x0 Enabled Enable 0x1 CH1LIMITL Enable or disable interrupt for event CH1LIMITL 9 9 Disabled Disable 0x0 Enabled Enable 0x1 CH2LIMITH Enable or disable interrupt for event CH2LIMITH 10 10 Disabled Disable 0x0 Enabled Enable 0x1 CH2LIMITL Enable or disable interrupt for event CH2LIMITL 11 11 Disabled Disable 0x0 Enabled Enable 0x1 CH3LIMITH Enable or disable interrupt for event CH3LIMITH 12 12 Disabled Disable 0x0 Enabled Enable 0x1 CH3LIMITL Enable or disable interrupt for event CH3LIMITL 13 13 Disabled Disable 0x0 Enabled Enable 0x1 CH4LIMITH Enable or disable interrupt for event CH4LIMITH 14 14 Disabled Disable 0x0 Enabled Enable 0x1 CH4LIMITL Enable or disable interrupt for event CH4LIMITL 15 15 Disabled Disable 0x0 Enabled Enable 0x1 CH5LIMITH Enable or disable interrupt for event CH5LIMITH 16 16 Disabled Disable 0x0 Enabled Enable 0x1 CH5LIMITL Enable or disable interrupt for event CH5LIMITL 17 17 Disabled Disable 0x0 Enabled Enable 0x1 CH6LIMITH Enable or disable interrupt for event CH6LIMITH 18 18 Disabled Disable 0x0 Enabled Enable 0x1 CH6LIMITL Enable or disable interrupt for event CH6LIMITL 19 19 Disabled Disable 0x0 Enabled Enable 0x1 CH7LIMITH Enable or disable interrupt for event CH7LIMITH 20 20 Disabled Disable 0x0 Enabled Enable 0x1 CH7LIMITL Enable or disable interrupt for event CH7LIMITL 21 21 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STARTED Write '1' to enable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 END Write '1' to enable interrupt for event END 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DONE Write '1' to enable interrupt for event DONE 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RESULTDONE Write '1' to enable interrupt for event RESULTDONE 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CALIBRATEDONE Write '1' to enable interrupt for event CALIBRATEDONE 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH0LIMITH Write '1' to enable interrupt for event CH0LIMITH 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH0LIMITL Write '1' to enable interrupt for event CH0LIMITL 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH1LIMITH Write '1' to enable interrupt for event CH1LIMITH 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH1LIMITL Write '1' to enable interrupt for event CH1LIMITL 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH2LIMITH Write '1' to enable interrupt for event CH2LIMITH 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH2LIMITL Write '1' to enable interrupt for event CH2LIMITL 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH3LIMITH Write '1' to enable interrupt for event CH3LIMITH 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH3LIMITL Write '1' to enable interrupt for event CH3LIMITL 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH4LIMITH Write '1' to enable interrupt for event CH4LIMITH 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH4LIMITL Write '1' to enable interrupt for event CH4LIMITL 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH5LIMITH Write '1' to enable interrupt for event CH5LIMITH 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH5LIMITL Write '1' to enable interrupt for event CH5LIMITL 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH6LIMITH Write '1' to enable interrupt for event CH6LIMITH 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH6LIMITL Write '1' to enable interrupt for event CH6LIMITL 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH7LIMITH Write '1' to enable interrupt for event CH7LIMITH 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CH7LIMITL Write '1' to enable interrupt for event CH7LIMITL 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STARTED Write '1' to disable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 END Write '1' to disable interrupt for event END 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DONE Write '1' to disable interrupt for event DONE 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RESULTDONE Write '1' to disable interrupt for event RESULTDONE 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CALIBRATEDONE Write '1' to disable interrupt for event CALIBRATEDONE 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH0LIMITH Write '1' to disable interrupt for event CH0LIMITH 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH0LIMITL Write '1' to disable interrupt for event CH0LIMITL 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH1LIMITH Write '1' to disable interrupt for event CH1LIMITH 8 8 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH1LIMITL Write '1' to disable interrupt for event CH1LIMITL 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH2LIMITH Write '1' to disable interrupt for event CH2LIMITH 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH2LIMITL Write '1' to disable interrupt for event CH2LIMITL 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH3LIMITH Write '1' to disable interrupt for event CH3LIMITH 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH3LIMITL Write '1' to disable interrupt for event CH3LIMITL 13 13 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH4LIMITH Write '1' to disable interrupt for event CH4LIMITH 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH4LIMITL Write '1' to disable interrupt for event CH4LIMITL 15 15 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH5LIMITH Write '1' to disable interrupt for event CH5LIMITH 16 16 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH5LIMITL Write '1' to disable interrupt for event CH5LIMITL 17 17 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH6LIMITH Write '1' to disable interrupt for event CH6LIMITH 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH6LIMITL Write '1' to disable interrupt for event CH6LIMITL 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH7LIMITH Write '1' to disable interrupt for event CH7LIMITH 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CH7LIMITL Write '1' to disable interrupt for event CH7LIMITL 21 21 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STATUS Status 0x400 read-only 0x00000000 0x20 STATUS Status 0 0 Ready ADC is ready. No on-going conversion. 0x0 Busy ADC is busy. Single conversion in progress. 0x1 TRIM Unspecified GLOBAL_SAADC_TRIM read-write 0x440 0x6 0x4 LINCALCOEFF[%s] Description collection: Linearity calibration coefficient 0x000 read-write 0x00000000 0x20 VAL value 0 15 ENABLE Enable or disable ADC 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable ADC 0 0 Disabled Disable ADC 0x0 Enabled Enable ADC 0x1 8 0x010 CH[%s] Unspecified GLOBAL_SAADC_CH read-write 0x510 PSELP Description cluster: Input positive pin selection for CH[n] 0x000 read-write 0x00000000 0x20 PSELP Analog positive input channel 0 4 NC Not connected 0x00 AnalogInput0 AIN0 0x01 AnalogInput1 AIN1 0x02 AnalogInput2 AIN2 0x03 AnalogInput3 AIN3 0x04 AnalogInput4 AIN4 0x05 AnalogInput5 AIN5 0x06 AnalogInput6 AIN6 0x07 AnalogInput7 AIN7 0x08 AnalogInput8 AIN8 0x11 AnalogInput9 AIN9 0x12 AnalogInput10 AIN10 0x13 AnalogInput11 AIN11 0x14 AnalogInput12 AIN12 0x15 AnalogInput13 AIN13 0x16 PSELN Description cluster: Input negative pin selection for CH[n] 0x004 read-write 0x00000000 0x20 PSELN Analog negative input, enables differential channel 0 4 NC Not connected 0x00 AnalogInput0 AIN0 0x01 AnalogInput1 AIN1 0x02 AnalogInput2 AIN2 0x03 AnalogInput3 AIN3 0x04 AnalogInput4 AIN4 0x05 AnalogInput5 AIN5 0x06 AnalogInput6 AIN6 0x07 AnalogInput7 AIN7 0x08 AnalogInput8 AIN8 0x11 AnalogInput9 AIN9 0x12 AnalogInput10 AIN10 0x13 AnalogInput11 AIN11 0x14 AnalogInput12 AIN12 0x15 AnalogInput13 AIN13 0x16 CONFIG Description cluster: Input configuration for CH[n] 0x008 read-write 0x00020000 0x20 RESP Positive channel resistor control 0 1 Bypass Bypass resistor ladder 0x0 Pulldown Pull-down to GND 0x1 Pullup Pull-up to VDD_AO_1V8 0x2 VDDAO1V8div2 Set input at VDD_AO_1V8/2 0x3 RESN Negative channel resistor control 4 5 Bypass Bypass resistor ladder 0x0 Pulldown Pull-down to GND 0x1 Pullup Pull-up to VDD_AO_1V8 0x2 VDDAO1V8div2 Set input at VDD_AO_1V8/2 0x3 GAIN Gain control 8 9 Gain2_3 2/3 0x0 Gain1 1 0x1 Gain2 2 0x2 Gain4 4 0x3 BURST Enable burst mode 11 11 Disabled Burst mode is disabled (normal operation) 0x0 Enabled Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. 0x1 REFSEL Reference control 12 12 Internal Internal reference (1.024 V) 0x0 External External reference given at PADC_EXT_REF_1V2 0x1 MODE Enable differential mode 15 15 SE Single ended, PSELN will be ignored, negative input to ADC shorted to GND 0x0 Diff Differential 0x1 TACQ Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is ((TACQ+1) x 125 ns) 16 24 TCONV Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) 28 30 LIMIT Description cluster: High/low limits for event monitoring a channel 0x00C read-write 0x7FFF8000 0x20 LOW Low level limit 0 15 HIGH High level limit 16 31 RESOLUTION Resolution configuration 0x5F0 read-write 0x00000001 0x20 VAL Set the resolution 0 2 8bit 8 bit 0x0 10bit 10 bit 0x1 12bit 12 bit 0x2 14bit 14 bit 0x3 OVERSAMPLE Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 0x5F4 read-write 0x00000000 0x20 OVERSAMPLE Oversample control 0 3 Bypass Bypass oversampling 0x0 Over2x Oversample 2x 0x1 Over4x Oversample 4x 0x2 Over8x Oversample 8x 0x3 Over16x Oversample 16x 0x4 Over32x Oversample 32x 0x5 Over64x Oversample 64x 0x6 Over128x Oversample 128x 0x7 Over256x Oversample 256x 0x8 SAMPLERATE Controls normal or continuous sample rate 0x5F8 read-write 0x00000000 0x20 CC Capture and compare value. Sample rate is 16 MHz/CC 0 10 MODE Select mode for sample rate control 12 12 Task Rate is controlled from SAMPLE task 0x0 Timers Rate is controlled from local timer (use CC to control the rate) 0x1 RESULT RESULT EasyDMA channel GLOBAL_SAADC_RESULT read-write 0x62C PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of buffer bytes to transfer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of buffer bytes to transfer 0 14 AMOUNT Number of buffer bytes transferred since last START 0x008 read-only 0x00000000 0x20 AMOUNT Number of buffer bytes transferred since last START. This register can be read after an END or STOPPED event. 0 14 GLOBAL_SAADC_S Analog to Digital Converter 1 0x5F982000 SAADC 386 GLOBAL_COMP_NS Comparator 0 0x4F983000 COMP 0 0x1000 registers COMP_LPCOMP 387 COMP 0x20 TASKS_START Start comparator 0x000 write-only 0x00000000 0x20 TASKS_START Start comparator 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop comparator 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop comparator 0 0 Trigger Trigger task 0x1 TASKS_SAMPLE Sample comparator value 0x008 write-only 0x00000000 0x20 TASKS_SAMPLE Sample comparator value 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_SAMPLE Subscribe configuration for task SAMPLE 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task SAMPLE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_READY COMP is ready and output is valid 0x100 read-write 0x00000000 0x20 EVENTS_READY COMP is ready and output is valid 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DOWN Downward crossing 0x104 read-write 0x00000000 0x20 EVENTS_DOWN Downward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_UP Upward crossing 0x108 read-write 0x00000000 0x20 EVENTS_UP Upward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CROSS Downward or upward crossing 0x10C read-write 0x00000000 0x20 EVENTS_CROSS Downward or upward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_READY Publish configuration for event READY 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event READY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_DOWN Publish configuration for event DOWN 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event DOWN will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_UP Publish configuration for event UP 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event UP will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_CROSS Publish configuration for event CROSS 0x18C read-write 0x00000000 0x20 CHIDX DPPI channel that event CROSS will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 READY_SAMPLE Shortcut between event READY and task SAMPLE 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 READY_STOP Shortcut between event READY and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DOWN_STOP Shortcut between event DOWN and task STOP 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 UP_STOP Shortcut between event UP and task STOP 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 CROSS_STOP Shortcut between event CROSS and task STOP 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 READY Enable or disable interrupt for event READY 0 0 Disabled Disable 0x0 Enabled Enable 0x1 DOWN Enable or disable interrupt for event DOWN 1 1 Disabled Disable 0x0 Enabled Enable 0x1 UP Enable or disable interrupt for event UP 2 2 Disabled Disable 0x0 Enabled Enable 0x1 CROSS Enable or disable interrupt for event CROSS 3 3 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DOWN Write '1' to enable interrupt for event DOWN 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 UP Write '1' to enable interrupt for event UP 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CROSS Write '1' to enable interrupt for event CROSS 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DOWN Write '1' to disable interrupt for event DOWN 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 UP Write '1' to disable interrupt for event UP 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CROSS Write '1' to disable interrupt for event CROSS 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RESULT Compare result 0x400 read-only 0x00000000 0x20 RESULT Result of last compare. Decision point SAMPLE task. 0 0 Below Input voltage is below the threshold (VIN+ < VIN-) 0x0 Above Input voltage is above the threshold (VIN+ > VIN-) 0x1 ENABLE COMP enable 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable COMP 0 1 Disabled Disable 0x0 Enabled Enable 0x2 PSEL Pin select 0x504 read-write 0x00000000 0x20 PSEL Analog pin select 0 3 AnalogInput0 AIN0 selected as analog input 0x0 AnalogInput1 AIN1 selected as analog input 0x1 AnalogInput2 AIN2 selected as analog input 0x2 AnalogInput3 AIN3 selected as analog input 0x3 AnalogInput4 AIN4 selected as analog input 0x4 AnalogInput5 AIN5 selected as analog input 0x5 AnalogInput6 AIN6 selected as analog input 0x6 AnalogInput7 AIN7 selected as analog input 0x7 AnalogInput8 AIN8 selected as analog input 0x8 AnalogInput9 AIN9 selected as analog input 0x9 REFSEL Reference source select for single-ended mode 0x508 read-write 0x00000004 0x20 REFSEL Reference select 0 2 Int1V2 VREF = internal 1.2 V reference (AVDD_AO_1V8 >= 1.7 V) 0x0 AVDDAO1V8 VREF = AVDD_AO_1V8 0x4 ARef VREF = AREF 0x5 EXTREFSEL External reference select 0x50C read-write 0x00000000 0x20 EXTREFSEL External analog reference select 0 3 AnalogReference0 Use AIN0 as external analog reference 0x0 AnalogReference1 Use AIN1 as external analog reference 0x1 AnalogReference2 Use AIN2 as external analog reference 0x2 AnalogReference3 Use AIN3 as external analog reference 0x3 AnalogReference4 Use AIN4 as external analog reference 0x4 AnalogReference5 Use AIN5 as external analog reference 0x5 AnalogReference6 Use AIN6 as external analog reference 0x6 AnalogReference7 Use AIN7 as external analog reference 0x7 AnalogReference8 Use AIN8 as external analog reference 0x8 AnalogReference9 Use AIN9 as external analog reference 0x9 CONFIGVOLTLVL Configure voltage level for analog input 0x518 read-write 0x00000000 0x20 EN Enable 3.3V on analog input 0 0 Disable Disable 0x0 Enable Enable 0x1 TH Threshold configuration for hysteresis unit 0x530 read-write 0x00002020 0x20 THDOWN VDOWN = (THDOWN+1)/64*VREF 0 5 THUP VUP = (THUP+1)/64*VREF 8 13 MODE Mode configuration 0x534 read-write 0x00000000 0x20 SP Speed and power modes 0 0 Low Low-power mode 0x0 High High-speed mode 0x1 MAIN Main operation modes 8 8 SE Single-ended mode 0x0 Diff Differential mode 0x1 HYST Comparator hysteresis enable 0x538 read-write 0x00000000 0x20 HYST Comparator hysteresis 0 0 NoHyst Comparator hysteresis disabled 0x0 Hyst40mV Comparator hysteresis enabled 0x1 ISOURCE Current source select on analog input 0x53C read-write 0x00000000 0x20 ISOURCE Current source select on analog input 0 1 Off Current source disabled 0x0 Ien2uA5 Current source enabled (+/- 2.5 uA) 0x1 Ien5uA Current source enabled (+/- 5 uA) 0x2 Ien10uA Current source enabled (+/- 10 uA) 0x3 GLOBAL_LPCOMP_NS Low-power comparator 0 0x4F983000 GLOBAL_COMP_NS LPCOMP 0 0x1000 registers COMP_LPCOMP 387 LPCOMP 0x20 TASKS_START Start comparator 0x000 write-only 0x00000000 0x20 TASKS_START Start comparator 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop comparator 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop comparator 0 0 Trigger Trigger task 0x1 TASKS_SAMPLE Sample comparator value 0x008 write-only 0x00000000 0x20 TASKS_SAMPLE Sample comparator value 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_SAMPLE Subscribe configuration for task SAMPLE 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task SAMPLE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_READY LPCOMP is ready and output is valid 0x100 read-write 0x00000000 0x20 EVENTS_READY LPCOMP is ready and output is valid 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DOWN Downward crossing 0x104 read-write 0x00000000 0x20 EVENTS_DOWN Downward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_UP Upward crossing 0x108 read-write 0x00000000 0x20 EVENTS_UP Upward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_CROSS Downward or upward crossing 0x10C read-write 0x00000000 0x20 EVENTS_CROSS Downward or upward crossing 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_READY Publish configuration for event READY 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event READY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_DOWN Publish configuration for event DOWN 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event DOWN will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_UP Publish configuration for event UP 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event UP will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_CROSS Publish configuration for event CROSS 0x18C read-write 0x00000000 0x20 CHIDX DPPI channel that event CROSS will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 READY_SAMPLE Shortcut between event READY and task SAMPLE 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 READY_STOP Shortcut between event READY and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DOWN_STOP Shortcut between event DOWN and task STOP 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 UP_STOP Shortcut between event UP and task STOP 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 CROSS_STOP Shortcut between event CROSS and task STOP 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DOWN Write '1' to enable interrupt for event DOWN 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 UP Write '1' to enable interrupt for event UP 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 CROSS Write '1' to enable interrupt for event CROSS 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DOWN Write '1' to disable interrupt for event DOWN 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 UP Write '1' to disable interrupt for event UP 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 CROSS Write '1' to disable interrupt for event CROSS 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RESULT Compare result 0x400 read-only 0x00000000 0x20 RESULT Result of last compare. Decision point SAMPLE task. 0 0 Below Input voltage is below the reference threshold (VIN+ < VIN-) 0x0 Above Input voltage is above the reference threshold (VIN+ > VIN-) 0x1 ENABLE Enable LPCOMP 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable LPCOMP 0 1 Disabled Disable 0x0 Enabled Enable 0x1 PSEL Input pin select 0x504 read-write 0x00000000 0x20 PSEL Analog pin select 0 3 AnalogInput0 AIN0 selected as analog input 0x0 AnalogInput1 AIN1 selected as analog input 0x1 AnalogInput2 AIN2 selected as analog input 0x2 AnalogInput3 AIN3 selected as analog input 0x3 AnalogInput4 AIN4 selected as analog input 0x4 AnalogInput5 AIN5 selected as analog input 0x5 AnalogInput6 AIN6 selected as analog input 0x6 AnalogInput7 AIN7 selected as analog input 0x7 AnalogInput8 AIN8 selected as analog input 0x8 AnalogInput9 AIN9 selected as analog input 0x9 REFSEL Reference select 0x508 read-write 0x00000004 0x20 REFSEL Reference select 0 3 Ref1_8Vdd VDD * 1/8 selected as reference 0x0 Ref2_8Vdd VDD * 2/8 selected as reference 0x1 Ref3_8Vdd VDD * 3/8 selected as reference 0x2 Ref4_8Vdd VDD * 4/8 selected as reference 0x3 Ref5_8Vdd VDD * 5/8 selected as reference 0x4 Ref6_8Vdd VDD * 6/8 selected as reference 0x5 Ref7_8Vdd VDD * 7/8 selected as reference 0x6 ARef External analog reference selected 0x7 Ref1_16Vdd VDD * 1/16 selected as reference 0x8 Ref3_16Vdd VDD * 3/16 selected as reference 0x9 Ref5_16Vdd VDD * 5/16 selected as reference 0xA Ref7_16Vdd VDD * 7/16 selected as reference 0xB Ref9_16Vdd VDD * 9/16 selected as reference 0xC Ref11_16Vdd VDD * 11/16 selected as reference 0xD Ref13_16Vdd VDD * 13/16 selected as reference 0xE Ref15_16Vdd VDD * 15/16 selected as reference 0xF EXTREFSEL External reference select 0x50C read-write 0x00000000 0x20 EXTREFSEL External analog reference select 0 0 AnalogReference0 Use AIN0 as external analog reference 0x0 AnalogReference1 Use AIN1 as external analog reference 0x1 CONFIGVOLTLVL Configure voltage level for analog input 0x518 read-write 0x00000000 0x20 EN Enable 3.3V on analog input 0 0 Disable Disable 0x0 Enable Enable 0x1 ANADETECT Analog detect configuration 0x520 read-write 0x00000000 0x20 ANADETECT Analog detect configuration 0 1 Cross Generate ANADETECT on crossing, both upward crossing and downward crossing 0x0 Up Generate ANADETECT on upward crossing only 0x1 Down Generate ANADETECT on downward crossing only 0x2 HYST Comparator hysteresis enable 0x538 read-write 0x00000000 0x20 HYST Comparator hysteresis enable 0 0 Disabled Comparator hysteresis disabled 0x0 Enabled Comparator hysteresis enabled 0x1 GLOBAL_COMP_S Comparator 1 0x5F983000 COMP_LPCOMP 387 GLOBAL_LPCOMP_S Low-power comparator 1 0x5F983000 GLOBAL_COMP_S COMP_LPCOMP 387 GLOBAL_TEMP_NS Temperature Sensor 0 0x4F984000 TEMP 0 0x1000 registers TEMP 388 TEMP 0x20 TASKS_START Start temperature measurement 0x000 write-only 0x00000000 0x20 TASKS_START Start temperature measurement 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop temperature measurement 0x004 write-only 0x00000000 0x20 TASKS_STOP Stop temperature measurement 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_DATARDY Temperature measurement complete, data ready 0x100 read-write 0x00000000 0x20 EVENTS_DATARDY Temperature measurement complete, data ready 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_DATARDY Publish configuration for event DATARDY 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event DATARDY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 DATARDY Write '1' to enable interrupt for event DATARDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 DATARDY Write '1' to disable interrupt for event DATARDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TEMP Temperature in degC (0.25deg steps) 0x508 read-only 0x00000000 int32_t 0x20 TEMP Temperature in degC (0.25deg steps) 0 31 A0 Slope of 1st piece wise linear function 0x520 read-write 0x000002D9 0x20 A0 Slope of 1st piece wise linear function 0 11 A1 Slope of 2nd piece wise linear function 0x524 read-write 0x00000322 0x20 A1 Slope of 2nd piece wise linear function 0 11 A2 Slope of 3rd piece wise linear function 0x528 read-write 0x00000355 0x20 A2 Slope of 3rd piece wise linear function 0 11 A3 Slope of 4th piece wise linear function 0x52C read-write 0x000003DF 0x20 A3 Slope of 4th piece wise linear function 0 11 A4 Slope of 5th piece wise linear function 0x530 read-write 0x0000044E 0x20 A4 Slope of 5th piece wise linear function 0 11 A5 Slope of 6th piece wise linear function 0x534 read-write 0x000004B7 0x20 A5 Slope of 6th piece wise linear function 0 11 A6 Slope of 7th piece wise linear function 0x538 read-write 0x000004B7 0x20 A6 Slope of 7th piece wise linear function 0 11 B0 y-intercept of 1st piece wise linear function 0x540 read-write 0x00000FC7 0x20 B0 y-intercept of 1st piece wise linear function 0 11 B1 y-intercept of 2nd piece wise linear function 0x544 read-write 0x00000F71 0x20 B1 y-intercept of 2nd piece wise linear function 0 11 B2 y-intercept of 3rd piece wise linear function 0x548 read-write 0x00000F6C 0x20 B2 y-intercept of 3rd piece wise linear function 0 11 B3 y-intercept of 4th piece wise linear function 0x54C read-write 0x00000FCB 0x20 B3 y-intercept of 4th piece wise linear function 0 11 B4 y-intercept of 5th piece wise linear function 0x550 read-write 0x0000004B 0x20 B4 y-intercept of 5th piece wise linear function 0 11 B5 y-intercept of 6th piece wise linear function 0x554 read-write 0x000000F6 0x20 B5 y-intercept of 6th piece wise linear function 0 11 B6 y-intercept of 7th piece wise linear function 0x558 read-write 0x000000F6 0x20 B6 y-intercept of 7th piece wise linear function 0 11 T0 End point of 1st piece wise linear function 0x560 read-write 0x000000E1 0x20 T0 End point of 1st piece wise linear function 0 7 T1 End point of 2nd piece wise linear function 0x564 read-write 0x000000F9 0x20 T1 End point of 2nd piece wise linear function 0 7 T2 End point of 3rd piece wise linear function 0x568 read-write 0x00000010 0x20 T2 End point of 3rd piece wise linear function 0 7 T3 End point of 4th piece wise linear function 0x56C read-write 0x00000026 0x20 T3 End point of 4th piece wise linear function 0 7 T4 End point of 5th piece wise linear function 0x570 read-write 0x0000003F 0x20 T4 End point of 5th piece wise linear function 0 7 T5 End point of 6th piece wise linear function 0x574 read-write 0x00000078 0x20 T5 End point of 6th piece wise linear function 0 7 GLOBAL_TEMP_S Temperature Sensor 1 0x5F984000 TEMP 388 GLOBAL_NFCT_NS NFC-A compatible radio NFC-A compatible radio 0 0x4F985000 NFCT 0 0x1000 registers NFCT 389 NFCT 0x20 TASKS_ACTIVATE Activate NFCT peripheral for incoming and outgoing frames, change state to activated 0x000 write-only 0x00000000 0x20 TASKS_ACTIVATE Activate NFCT peripheral for incoming and outgoing frames, change state to activated 0 0 Trigger Trigger task 0x1 TASKS_DISABLE Disable NFCT peripheral 0x004 write-only 0x00000000 0x20 TASKS_DISABLE Disable NFCT peripheral 0 0 Trigger Trigger task 0x1 TASKS_SENSE Enable NFC sense field mode, change state to sense mode 0x008 write-only 0x00000000 0x20 TASKS_SENSE Enable NFC sense field mode, change state to sense mode 0 0 Trigger Trigger task 0x1 TASKS_STARTTX Start transmission of an outgoing frame, change state to transmit 0x00C write-only 0x00000000 0x20 TASKS_STARTTX Start transmission of an outgoing frame, change state to transmit 0 0 Trigger Trigger task 0x1 TASKS_STOPTX Stops an issued transmission of a frame 0x010 write-only 0x00000000 0x20 TASKS_STOPTX Stops an issued transmission of a frame 0 0 Trigger Trigger task 0x1 TASKS_ENABLERXDATA Initializes the EasyDMA for receive. 0x01C write-only 0x00000000 0x20 TASKS_ENABLERXDATA Initializes the EasyDMA for receive. 0 0 Trigger Trigger task 0x1 TASKS_GOIDLE Force state machine to IDLE state 0x024 write-only 0x00000000 0x20 TASKS_GOIDLE Force state machine to IDLE state 0 0 Trigger Trigger task 0x1 TASKS_GOSLEEP Force state machine to SLEEP_A state 0x028 write-only 0x00000000 0x20 TASKS_GOSLEEP Force state machine to SLEEP_A state 0 0 Trigger Trigger task 0x1 SUBSCRIBE_ACTIVATE Subscribe configuration for task ACTIVATE 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task ACTIVATE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_DISABLE Subscribe configuration for task DISABLE 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task DISABLE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_SENSE Subscribe configuration for task SENSE 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task SENSE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STARTTX Subscribe configuration for task STARTTX 0x08C read-write 0x00000000 0x20 CHIDX DPPI channel that task STARTTX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOPTX Subscribe configuration for task STOPTX 0x090 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOPTX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_ENABLERXDATA Subscribe configuration for task ENABLERXDATA 0x09C read-write 0x00000000 0x20 CHIDX DPPI channel that task ENABLERXDATA will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_GOIDLE Subscribe configuration for task GOIDLE 0x0A4 read-write 0x00000000 0x20 CHIDX DPPI channel that task GOIDLE will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_GOSLEEP Subscribe configuration for task GOSLEEP 0x0A8 read-write 0x00000000 0x20 CHIDX DPPI channel that task GOSLEEP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_READY The NFCT peripheral is ready to receive and send frames 0x100 read-write 0x00000000 0x20 EVENTS_READY The NFCT peripheral is ready to receive and send frames 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_FIELDDETECTED Remote NFC field detected 0x104 read-write 0x00000000 0x20 EVENTS_FIELDDETECTED Remote NFC field detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_FIELDLOST Remote NFC field lost 0x108 read-write 0x00000000 0x20 EVENTS_FIELDLOST Remote NFC field lost 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXFRAMESTART Marks the start of the first symbol of a transmitted frame 0x10C read-write 0x00000000 0x20 EVENTS_TXFRAMESTART Marks the start of the first symbol of a transmitted frame 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXFRAMEEND Marks the end of the last transmitted on-air symbol of a frame 0x110 read-write 0x00000000 0x20 EVENTS_TXFRAMEEND Marks the end of the last transmitted on-air symbol of a frame 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXFRAMESTART Marks the end of the first symbol of a received frame 0x114 read-write 0x00000000 0x20 EVENTS_RXFRAMESTART Marks the end of the first symbol of a received frame 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXFRAMEEND Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer 0x118 read-write 0x00000000 0x20 EVENTS_RXFRAMEEND Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR NFC error reported. The ERRORSTATUS register contains details on the source of the error. 0x11C read-write 0x00000000 0x20 EVENTS_ERROR NFC error reported. The ERRORSTATUS register contains details on the source of the error. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXERROR NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. 0x128 read-write 0x00000000 0x20 EVENTS_RXERROR NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDRX RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. 0x12C read-write 0x00000000 0x20 EVENTS_ENDRX RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ENDTX Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer 0x130 read-write 0x00000000 0x20 EVENTS_ENDTX Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_AUTOCOLRESSTARTED Auto collision resolution process has started 0x138 read-write 0x00000000 0x20 EVENTS_AUTOCOLRESSTARTED Auto collision resolution process has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_COLLISION NFC auto collision resolution error reported. 0x148 read-write 0x00000000 0x20 EVENTS_COLLISION NFC auto collision resolution error reported. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SELECTED NFC auto collision resolution successfully completed 0x14C read-write 0x00000000 0x20 EVENTS_SELECTED NFC auto collision resolution successfully completed 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STARTED EasyDMA is ready to receive or send frames. 0x150 read-write 0x00000000 0x20 EVENTS_STARTED EasyDMA is ready to receive or send frames. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_READY Publish configuration for event READY 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event READY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_FIELDDETECTED Publish configuration for event FIELDDETECTED 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event FIELDDETECTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_FIELDLOST Publish configuration for event FIELDLOST 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event FIELDLOST will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXFRAMESTART Publish configuration for event TXFRAMESTART 0x18C read-write 0x00000000 0x20 CHIDX DPPI channel that event TXFRAMESTART will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXFRAMEEND Publish configuration for event TXFRAMEEND 0x190 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXFRAMEEND will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXFRAMESTART Publish configuration for event RXFRAMESTART 0x194 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXFRAMESTART will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXFRAMEEND Publish configuration for event RXFRAMEEND 0x198 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXFRAMEEND will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ERROR Publish configuration for event ERROR 0x19C read-write 0x00000000 0x20 CHIDX DPPI channel that event ERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXERROR Publish configuration for event RXERROR 0x1A8 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ENDRX Publish configuration for event ENDRX 0x1AC read-write 0x00000000 0x20 CHIDX DPPI channel that event ENDRX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ENDTX Publish configuration for event ENDTX 0x1B0 read-write 0x00000000 0x20 CHIDX DPPI channel that event ENDTX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_AUTOCOLRESSTARTED Publish configuration for event AUTOCOLRESSTARTED 0x1B8 read-write 0x00000000 0x20 CHIDX DPPI channel that event AUTOCOLRESSTARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_COLLISION Publish configuration for event COLLISION 0x1C8 read-write 0x00000000 0x20 CHIDX DPPI channel that event COLLISION will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_SELECTED Publish configuration for event SELECTED 0x1CC read-write 0x00000000 0x20 CHIDX DPPI channel that event SELECTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_STARTED Publish configuration for event STARTED 0x1D0 read-write 0x00000000 0x20 CHIDX DPPI channel that event STARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 FIELDDETECTED_ACTIVATE Shortcut between event FIELDDETECTED and task ACTIVATE 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 FIELDLOST_SENSE Shortcut between event FIELDLOST and task SENSE 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 TXFRAMEEND_ENABLERXDATA Shortcut between event TXFRAMEEND and task ENABLERXDATA 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 READY Enable or disable interrupt for event READY 0 0 Disabled Disable 0x0 Enabled Enable 0x1 FIELDDETECTED Enable or disable interrupt for event FIELDDETECTED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 FIELDLOST Enable or disable interrupt for event FIELDLOST 2 2 Disabled Disable 0x0 Enabled Enable 0x1 TXFRAMESTART Enable or disable interrupt for event TXFRAMESTART 3 3 Disabled Disable 0x0 Enabled Enable 0x1 TXFRAMEEND Enable or disable interrupt for event TXFRAMEEND 4 4 Disabled Disable 0x0 Enabled Enable 0x1 RXFRAMESTART Enable or disable interrupt for event RXFRAMESTART 5 5 Disabled Disable 0x0 Enabled Enable 0x1 RXFRAMEEND Enable or disable interrupt for event RXFRAMEEND 6 6 Disabled Disable 0x0 Enabled Enable 0x1 ERROR Enable or disable interrupt for event ERROR 7 7 Disabled Disable 0x0 Enabled Enable 0x1 RXERROR Enable or disable interrupt for event RXERROR 10 10 Disabled Disable 0x0 Enabled Enable 0x1 ENDRX Enable or disable interrupt for event ENDRX 11 11 Disabled Disable 0x0 Enabled Enable 0x1 ENDTX Enable or disable interrupt for event ENDTX 12 12 Disabled Disable 0x0 Enabled Enable 0x1 AUTOCOLRESSTARTED Enable or disable interrupt for event AUTOCOLRESSTARTED 14 14 Disabled Disable 0x0 Enabled Enable 0x1 COLLISION Enable or disable interrupt for event COLLISION 18 18 Disabled Disable 0x0 Enabled Enable 0x1 SELECTED Enable or disable interrupt for event SELECTED 19 19 Disabled Disable 0x0 Enabled Enable 0x1 STARTED Enable or disable interrupt for event STARTED 20 20 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 FIELDDETECTED Write '1' to enable interrupt for event FIELDDETECTED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 FIELDLOST Write '1' to enable interrupt for event FIELDLOST 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXFRAMESTART Write '1' to enable interrupt for event TXFRAMESTART 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXFRAMEEND Write '1' to enable interrupt for event TXFRAMEEND 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXFRAMESTART Write '1' to enable interrupt for event RXFRAMESTART 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXFRAMEEND Write '1' to enable interrupt for event RXFRAMEEND 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXERROR Write '1' to enable interrupt for event RXERROR 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDRX Write '1' to enable interrupt for event ENDRX 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ENDTX Write '1' to enable interrupt for event ENDTX 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 AUTOCOLRESSTARTED Write '1' to enable interrupt for event AUTOCOLRESSTARTED 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 COLLISION Write '1' to enable interrupt for event COLLISION 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SELECTED Write '1' to enable interrupt for event SELECTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STARTED Write '1' to enable interrupt for event STARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 FIELDDETECTED Write '1' to disable interrupt for event FIELDDETECTED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 FIELDLOST Write '1' to disable interrupt for event FIELDLOST 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXFRAMESTART Write '1' to disable interrupt for event TXFRAMESTART 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXFRAMEEND Write '1' to disable interrupt for event TXFRAMEEND 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXFRAMESTART Write '1' to disable interrupt for event RXFRAMESTART 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXFRAMEEND Write '1' to disable interrupt for event RXFRAMEEND 6 6 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXERROR Write '1' to disable interrupt for event RXERROR 10 10 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDRX Write '1' to disable interrupt for event ENDRX 11 11 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENDTX Write '1' to disable interrupt for event ENDTX 12 12 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 AUTOCOLRESSTARTED Write '1' to disable interrupt for event AUTOCOLRESSTARTED 14 14 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 COLLISION Write '1' to disable interrupt for event COLLISION 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SELECTED Write '1' to disable interrupt for event SELECTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STARTED Write '1' to disable interrupt for event STARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSTATUS NFC Error Status register 0x404 read-write 0x00000000 oneToClear 0x20 FRAMEDELAYTIMEOUT No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX 0 0 FRAMESTATUS Unspecified GLOBAL_NFCT_FRAMESTATUS read-write 0x40C RX Result of last incoming frame 0x000 read-write 0x00000000 oneToClear 0x20 CRCERROR No valid end of frame (EoF) detected 0 0 CRCCorrect Valid CRC detected 0x0 CRCError CRC received does not match local check 0x1 PARITYSTATUS Parity status of received frame 2 2 ParityOK Frame received with parity OK 0x0 ParityError Frame received with parity error 0x1 OVERRUN Overrun detected 3 3 NoOverrun No overrun detected 0x0 Overrun Overrun error 0x1 NFCTAGSTATE Current operating state of NFC tag 0x410 read-only 0x00000000 0x20 NFCTAGSTATE NfcTag state 0 2 Disabled Disabled or sense 0x0 RampUp RampUp 0x2 Idle Idle 0x3 Receive Receive 0x4 FrameDelay FrameDelay 0x5 Transmit Transmit 0x6 SLEEPSTATE Sleep state during automatic collision resolution 0x420 read-only 0x00000000 0x20 SLEEPSTATE Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. 0 0 Idle State is IDLE. 0x0 SleepA State is SLEEP_A. 0x1 FIELDPRESENT Indicates the presence or not of a valid field 0x43C read-only 0x00000000 0x20 FIELDPRESENT Indicates if a valid field is present. Available only in the activated state. 0 0 NoField No valid field detected 0x0 FieldPresent Valid field detected 0x1 LOCKDETECT Indicates if the low level has locked to the field 1 1 NotLocked Not locked to field 0x0 Locked Locked to field 0x1 FRAMEDELAYMIN Minimum frame delay 0x504 read-write 0x00000480 0x20 FRAMEDELAYMIN Minimum frame delay in number of 13.56 MHz clock cycles 0 15 FRAMEDELAYMAX Maximum frame delay 0x508 read-write 0x00001000 0x20 FRAMEDELAYMAX Maximum frame delay in number of 13.56 MHz clock cycles 0 19 FRAMEDELAYMODE Configuration register for the Frame Delay Timer 0x50C read-write 0x00000001 0x20 FRAMEDELAYMODE Configuration register for the Frame Delay Timer 0 1 FreeRun Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. 0x0 Window Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX 0x1 ExactVal Frame is transmitted exactly at FRAMEDELAYMAX 0x2 WindowGrid Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX 0x3 TXD Unspecified GLOBAL_NFCT_TXD read-write 0x518 FRAMECONFIG Configuration of outgoing frames 0x000 read-write 0x00000017 0x20 PARITY Indicates if parity is added to the frame 0 0 NoParity Parity is not added to TX frames 0x0 Parity Parity is added to TX frames 0x1 DISCARDMODE Discarding unused bits at start or end of a frame 1 1 DiscardEnd Unused bits are discarded at end of frame (EoF) 0x0 DiscardStart Unused bits are discarded at start of frame (SoF) 0x1 SOF Adding SoF or not in TX frames 2 2 NoSoF SoF symbol not added 0x0 SoF SoF symbol added 0x1 CRCMODETX CRC mode for outgoing frames 4 4 NoCRCTX CRC is not added to the frame 0x0 CRC16TX 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame 0x1 AMOUNT Size of outgoing frame 0x004 read-write 0x00000000 0x20 TXDATABITS Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). 0 2 TXDATABYTES Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. 3 11 RXD Unspecified GLOBAL_NFCT_RXD read-write 0x520 FRAMECONFIG Configuration of incoming frames 0x000 read-write 0x00000015 0x20 PARITY Indicates if parity expected in RX frame 0 0 NoParity Parity is not expected in RX frames 0x0 Parity Parity is expected in RX frames 0x1 SOF SoF expected or not in RX frames 2 2 NoSoF SoF symbol is not expected in RX frames 0x0 SoF SoF symbol is expected in RX frames 0x1 CRCMODERX CRC mode for incoming frames 4 4 NoCRCRX CRC is not expected in RX frames 0x0 CRC16RX Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated 0x1 AMOUNT Size of last incoming frame 0x004 read-only 0x00000000 0x20 RXDATABITS Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). 0 2 RXDATABYTES Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) 3 11 MODULATIONCTRL Enables the modulation output to a GPIO pin which can be connected to a second external antenna. 0x52C read-write 0x00000001 0x20 MODULATIONCTRL Configuration of modulation control. 0 1 Invalid Invalid, defaults to same behaviour as for Internal 0x0 Internal Use internal modulator only 0x1 ModToGpio Output digital modulation signal to a GPIO pin. 0x2 InternalAndModToGpio Use internal modulator and output digital modulation signal to a GPIO pin. 0x3 MODULATIONPSEL Pin select for Modulation control 0x538 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MODE Configure EasyDMA mode 0x550 read-write 0x00000001 0x20 LPOP Enable low-power operation, or use low-latency 0 1 LowLat Low-latency operation 0x0 LowPower Low-power operation 0x1 FullLowPower Full Low-power operation 0x3 NFCID1_LAST Last NFCID1 part (4, 7 or 10 bytes ID) 0x590 read-write 0x00006363 0x20 NFCID1_Z NFCID1 byte Z (very last byte sent) 0 7 NFCID1_Y NFCID1 byte Y 8 15 NFCID1_X NFCID1 byte X 16 23 NFCID1_W NFCID1 byte W 24 31 NFCID1_2ND_LAST Second last NFCID1 part (7 or 10 bytes ID) 0x594 read-write 0x00000000 0x20 NFCID1_V NFCID1 byte V 0 7 NFCID1_U NFCID1 byte U 8 15 NFCID1_T NFCID1 byte T 16 23 NFCID1_3RD_LAST Third last NFCID1 part (10 bytes ID) 0x598 read-write 0x00000000 0x20 NFCID1_S NFCID1 byte S 0 7 NFCID1_R NFCID1 byte R 8 15 NFCID1_Q NFCID1 byte Q 16 23 AUTOCOLRESCONFIG Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. 0x59C read-write 0x00000002 0x20 MODE Enables/disables auto collision resolution 0 0 Enabled Auto collision resolution enabled 0x0 Disabled Auto collision resolution disabled 0x1 SENSRES NFC-A SENS_RES auto-response settings 0x5A0 read-write 0x00000001 0x20 BITFRAMESDD Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 0 4 SDD00000 SDD pattern 00000 0x00 SDD00001 SDD pattern 00001 0x01 SDD00010 SDD pattern 00010 0x02 SDD00100 SDD pattern 00100 0x04 SDD01000 SDD pattern 01000 0x08 SDD10000 SDD pattern 10000 0x10 RFU5 Reserved for future use. Shall be 0. 5 5 NFCIDSIZE NFCID1 size. This value is used by the auto collision resolution engine. 6 7 NFCID1Single NFCID1 size: single (4 bytes) 0x0 NFCID1Double NFCID1 size: double (7 bytes) 0x1 NFCID1Triple NFCID1 size: triple (10 bytes) 0x2 PLATFCONFIG Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 8 11 RFU74 Reserved for future use. Shall be 0. 12 15 SELRES NFC-A SEL_RES auto-response settings 0x5A4 read-write 0x00000000 0x20 RFU10 Reserved for future use. Shall be 0. 0 1 CASCADE Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) 2 2 RFU43 Reserved for future use. Shall be 0. 3 4 PROTOCOL Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 5 6 RFU7 Reserved for future use. Shall be 0. 7 7 PACKETPTR Packet pointer for TXD and RXD data storage in Data RAM 0xA60 read-write 0x00000000 0x20 PTR Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. 0 31 MAXLEN Size of the RAM buffer allocated to TXD and RXD data storage each 0xA64 read-write 0x00000000 0x20 MAXLEN Size of the RAM buffer allocated to TXD and RXD data storage each 0 8 GLOBAL_NFCT_S NFC-A compatible radio NFC-A compatible radio 1 0x5F985000 NFCT 389 GLOBAL_DPPIC132_NS Distributed programmable peripheral interconnect controller 6 0x4F991000 GLOBAL_DPPIC132_S Distributed programmable peripheral interconnect controller 7 0x5F991000 GLOBAL_I2S130_NS Inter-IC Sound 0 0x4F992000 I2S 0 0x1000 registers I2S130 402 I2S 0x20 TASKS_START Starts continuous I2S transfer. Also starts MCK generator when this is enabled 0x000 write-only 0x00000000 0x20 TASKS_START Starts continuous I2S transfer. Also starts MCK generator when this is enabled 0 0 Trigger Trigger task 0x1 TASKS_STOP Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. 0x004 write-only 0x00000000 0x20 TASKS_STOP Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_RXPTRUPD The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. 0x104 read-write 0x00000000 0x20 EVENTS_RXPTRUPD The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED I2S transfer stopped. 0x108 read-write 0x00000000 0x20 EVENTS_STOPPED I2S transfer stopped. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXPTRUPD The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0x114 read-write 0x00000000 0x20 EVENTS_TXPTRUPD The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_FRAMESTART Frame start event, generated on the active edge of LRCK 0x11C read-write 0x00000000 0x20 EVENTS_FRAMESTART Frame start event, generated on the active edge of LRCK 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_RXPTRUPD Publish configuration for event RXPTRUPD 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXPTRUPD will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXPTRUPD Publish configuration for event TXPTRUPD 0x194 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXPTRUPD will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_FRAMESTART Publish configuration for event FRAMESTART 0x19C read-write 0x00000000 0x20 CHIDX DPPI channel that event FRAMESTART will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 RXPTRUPD Enable or disable interrupt for event RXPTRUPD 1 1 Disabled Disable 0x0 Enabled Enable 0x1 STOPPED Enable or disable interrupt for event STOPPED 2 2 Disabled Disable 0x0 Enabled Enable 0x1 TXPTRUPD Enable or disable interrupt for event TXPTRUPD 5 5 Disabled Disable 0x0 Enabled Enable 0x1 FRAMESTART Enable or disable interrupt for event FRAMESTART 7 7 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 RXPTRUPD Write '1' to enable interrupt for event RXPTRUPD 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXPTRUPD Write '1' to enable interrupt for event TXPTRUPD 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 FRAMESTART Write '1' to enable interrupt for event FRAMESTART 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 RXPTRUPD Write '1' to disable interrupt for event RXPTRUPD 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXPTRUPD Write '1' to disable interrupt for event TXPTRUPD 5 5 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 FRAMESTART Write '1' to disable interrupt for event FRAMESTART 7 7 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE Enable I2S module 0x500 read-write 0x00000000 0x20 ENABLE Enable I2S module 0 0 Disabled Disable 0x0 Enabled Enable 0x1 CONFIG Unspecified I2S_CONFIG read-write 0x504 MODE I2S mode 0x000 read-write 0x00000000 0x20 MODE I2S mode 0 0 Master Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. 0x0 Slave Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx 0x1 RXEN Reception (RX) enable 0x004 read-write 0x00000000 0x20 RXEN Reception (RX) enable 0 0 Disabled Reception disabled and now data will be written to the RXD.PTR address. 0x0 Enabled Reception enabled. 0x1 TXEN Transmission (TX) enable 0x008 read-write 0x00000001 0x20 TXEN Transmission (TX) enable 0 0 Disabled Transmission disabled and now data will be read from the RXD.TXD address. 0x0 Enabled Transmission enabled. 0x1 MCKEN Master clock generator enable 0x00C read-write 0x00000001 0x20 MCKEN Master clock generator enable 0 0 Disabled Master clock generator disabled and PSEL.MCK not connected(available as GPIO). 0x0 Enabled Master clock generator running and MCK output on PSEL.MCK. 0x1 MCKFREQ I2S clock generator control 0x010 read-write 0x20000000 0x20 MCKFREQ I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. 0 31 32MDIV2 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. 0x80000000 32MDIV3 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. 0x50000000 32MDIV4 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. 0x40000000 32MDIV5 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. 0x30000000 32MDIV6 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. 0x28000000 32MDIV8 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. 0x20000000 32MDIV10 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. 0x18000000 32MDIV11 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. 0x16000000 32MDIV15 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. 0x11000000 32MDIV16 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. 0x10000000 32MDIV21 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. 0x0C000000 32MDIV23 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. 0x0B000000 32MDIV30 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. 0x08800000 32MDIV31 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. 0x08400000 32MDIV32 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. 0x08000000 32MDIV42 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. 0x06000000 32MDIV63 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. 0x04100000 32MDIV125 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. 0x020C0000 RATIO MCK / LRCK ratio 0x014 read-write 0x00000006 0x20 RATIO MCK / LRCK ratio 0 3 32X LRCK = MCK / 32 0x0 48X LRCK = MCK / 48 0x1 64X LRCK = MCK / 64 0x2 96X LRCK = MCK / 96 0x3 128X LRCK = MCK / 128 0x4 192X LRCK = MCK / 192 0x5 256X LRCK = MCK / 256 0x6 384X LRCK = MCK / 384 0x7 512X LRCK = MCK / 512 0x8 SWIDTH Sample width 0x018 read-write 0x00000001 0x20 SWIDTH Sample and half-frame width 0 2 8Bit 8 bit sample. 0x0 16Bit 16 bit sample. 0x1 24Bit 24 bit sample. 0x2 32Bit 32 bit sample. 0x3 8BitIn16 8 bit sample in a 16-bit half-frame. 0x4 8BitIn32 8 bit sample in a 32-bit half-frame. 0x5 16BitIn32 16 bit sample in a 32-bit half-frame. 0x6 24BitIn32 24 bit sample in a 32-bit half-frame. 0x7 ALIGN Alignment of sample within a frame 0x01C read-write 0x00000000 0x20 ALIGN Alignment of sample within a frame 0 0 Left Left-aligned. 0x0 Right Right-aligned. 0x1 FORMAT Frame format 0x020 read-write 0x00000000 0x20 FORMAT Frame format 0 0 I2S Original I2S format. 0x0 Aligned Alternate (left- or right-aligned) format. 0x1 CHANNELS Enable channels 0x024 read-write 0x00000000 0x20 CHANNELS Enable channels 0 1 Stereo Stereo. 0x0 Left Left only. 0x1 Right Right only. 0x2 CLKCONFIG Clock source selection for the I2S module 0x028 read-write 0x00000000 0x20 CLKSRC Clock source selection 0 0 PCLK32M 32MHz peripheral clock 0x0 ACLK Audio PLL clock 0x1 BYPASS Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. 8 8 Disable Disable bypass 0x0 Enable Enable bypass 0x1 RXD Unspecified I2S_RXD read-write 0x538 PTR Receive buffer RAM start address. 0x000 read-write 0x00000000 0x20 PTR Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. 0 31 TXD Unspecified I2S_TXD read-write 0x540 PTR Transmit buffer RAM start address 0x000 read-write 0x00000000 0x20 PTR Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. 0 31 RXTXD Unspecified I2S_RXTXD read-write 0x550 MAXCNT Size of RXD and TXD buffers 0x000 read-write 0x00000000 0x20 MAXCNT Size of RXD and TXD buffers in number of 32 bit words 0 13 PSEL Unspecified I2S_PSEL read-write 0x560 MCK Pin select for MCK signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SCK Pin select for SCK signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 LRCK Pin select for LRCK signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDIN Pin select for SDIN signal 0x00C read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDOUT Pin select for SDOUT signal 0x010 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 GLOBAL_I2S130_S Inter-IC Sound 1 0x5F992000 I2S130 402 GLOBAL_PDM_NS Pulse Density Modulation (Digital Microphone) Interface 0 0x4F993000 PDM 0 0x1000 registers PDM 403 PDM 0x20 TASKS_START Starts continuous PDM transfer 0x000 write-only 0x00000000 0x20 TASKS_START Starts continuous PDM transfer 0 0 Trigger Trigger task 0x1 TASKS_STOP Stops PDM transfer 0x004 write-only 0x00000000 0x20 TASKS_STOP Stops PDM transfer 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_STARTED PDM transfer has started 0x100 read-write 0x00000000 0x20 EVENTS_STARTED PDM transfer has started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED PDM transfer has finished 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED PDM transfer has finished 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_END The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0x108 read-write 0x00000000 0x20 EVENTS_END The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_STARTED Publish configuration for event STARTED 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event STARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_END Publish configuration for event END 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event END will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STARTED Enable or disable interrupt for event STARTED 0 0 Disabled Disable 0x0 Enabled Enable 0x1 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 END Enable or disable interrupt for event END 2 2 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STARTED Write '1' to enable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 END Write '1' to enable interrupt for event END 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STARTED Write '1' to disable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 END Write '1' to disable interrupt for event END 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 INTPEND Pending interrupts 0x30C read-only 0x00000000 0x20 STARTED Read pending status of interrupt for event STARTED 0 0 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 STOPPED Read pending status of interrupt for event STOPPED 1 1 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 END Read pending status of interrupt for event END 2 2 read NotPending Read: Not pending 0x0 Pending Read: Pending 0x1 ENABLE PDM module enable register 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable PDM module 0 0 Disabled Disable 0x0 Enabled Enable 0x1 PDMCLKCTRL PDM clock generator control 0x504 read-write 0x08400000 0x20 FREQ PDM_CLK frequency configuration. Enumerations are deprecated, use PDMCLKCTRL equation to find the register value. The 12 least significant bits of the register are ignored and shall be set to zero. 0 31 1000K PDM_CLK = 32 MHz / 32 = 1.000 MHz 0x08000000 Default PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. 0x08400000 1067K PDM_CLK = 32 MHz / 30 = 1.067 MHz 0x08800000 1231K PDM_CLK = 32 MHz / 26 = 1.231 MHz 0x09800000 1280K PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. 0x0A000000 1333K PDM_CLK = 32 MHz / 24 = 1.333 MHz 0x0A800000 MODE Defines the routing of the connected PDM microphones' signals 0x508 read-write 0x00000000 0x20 OPERATION Mono or stereo operation 0 0 Stereo Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] 0x0 Mono Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] 0x1 EDGE Defines on which PDM_CLK edge left (or mono) is sampled 1 1 LeftFalling Left (or mono) is sampled on falling edge of PDM_CLK 0x0 LeftRising Left (or mono) is sampled on rising edge of PDM_CLK 0x1 GAINL Left output gain adjustment 0x518 read-write 0x00000028 0x20 GAINL Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust 0 6 MinGain -20 dB gain adjustment (minimum) 0x00 DefaultGain 0 dB gain adjustment 0x28 MaxGain +20 dB gain adjustment (maximum) 0x50 GAINR Right output gain adjustment 0x51C read-write 0x00000028 0x20 GAINR Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0 6 MinGain -20 dB gain adjustment (minimum) 0x00 DefaultGain 0 dB gain adjustment 0x28 MaxGain +20 dB gain adjustment (maximum) 0x50 RATIO Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. 0x520 read-write 0x00000000 0x20 RATIO Selects the ratio between PDM_CLK and output sample rate 0 0 Ratio64 Ratio of 64 0x0 Ratio80 Ratio of 80 0x1 PSEL Unspecified GLOBAL_PDM_PSEL read-write 0x540 CLK Pin number configuration for PDM CLK signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 DIN Pin number configuration for PDM DIN signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 MCLKCONFIG Master clock generator configuration 0x54C read-write 0x00000000 0x20 SRC Master clock source selection 0 0 PCLK32M 32 MHz peripheral clock 0x0 ACLK Audio PLL clock 0x1 SAMPLE Unspecified GLOBAL_PDM_SAMPLE read-write 0x560 PTR RAM address pointer to write samples to with EasyDMA 0x000 read-write 0x00000000 0x20 SAMPLEPTR Address to write PDM samples to over DMA 0 31 MAXCNT Number of samples to allocate memory for in EasyDMA mode 0x004 read-write 0x00000000 0x20 BUFFSIZE Length of DMA RAM allocation in number of samples 0 14 DMA Unspecified GLOBAL_PDM_DMA read-write 0x700 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 GLOBAL_PDM_S Pulse Density Modulation (Digital Microphone) Interface 1 0x5F993000 PDM 403 GLOBAL_QDEC130_NS Quadrature Decoder 0 0x4F994000 QDEC 0 0x1000 registers QDEC130 404 QDEC 0x20 TASKS_START Task starting the quadrature decoder 0x000 write-only 0x00000000 0x20 TASKS_START Task starting the quadrature decoder 0 0 Trigger Trigger task 0x1 TASKS_STOP Task stopping the quadrature decoder 0x004 write-only 0x00000000 0x20 TASKS_STOP Task stopping the quadrature decoder 0 0 Trigger Trigger task 0x1 TASKS_READCLRACC Read and clear ACC and ACCDBL 0x008 write-only 0x00000000 0x20 TASKS_READCLRACC Read and clear ACC and ACCDBL 0 0 Trigger Trigger task 0x1 TASKS_RDCLRACC Read and clear ACC 0x00C write-only 0x00000000 0x20 TASKS_RDCLRACC Read and clear ACC 0 0 Trigger Trigger task 0x1 TASKS_RDCLRDBL Read and clear ACCDBL 0x010 write-only 0x00000000 0x20 TASKS_RDCLRDBL Read and clear ACCDBL 0 0 Trigger Trigger task 0x1 SUBSCRIBE_START Subscribe configuration for task START 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task START will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x084 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_READCLRACC Subscribe configuration for task READCLRACC 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task READCLRACC will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_RDCLRACC Subscribe configuration for task RDCLRACC 0x08C read-write 0x00000000 0x20 CHIDX DPPI channel that task RDCLRACC will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_RDCLRDBL Subscribe configuration for task RDCLRDBL 0x090 read-write 0x00000000 0x20 CHIDX DPPI channel that task RDCLRDBL will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_SAMPLERDY Event being generated for every new sample value written to the SAMPLE register 0x100 read-write 0x00000000 0x20 EVENTS_SAMPLERDY Event being generated for every new sample value written to the SAMPLE register 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_REPORTRDY Non-null report ready 0x104 read-write 0x00000000 0x20 EVENTS_REPORTRDY Non-null report ready 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ACCOF ACC or ACCDBL register overflow 0x108 read-write 0x00000000 0x20 EVENTS_ACCOF ACC or ACCDBL register overflow 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_DBLRDY Double displacement(s) detected 0x10C read-write 0x00000000 0x20 EVENTS_DBLRDY Double displacement(s) detected 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_STOPPED QDEC has been stopped 0x110 read-write 0x00000000 0x20 EVENTS_STOPPED QDEC has been stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_SAMPLERDY Publish configuration for event SAMPLERDY 0x180 read-write 0x00000000 0x20 CHIDX DPPI channel that event SAMPLERDY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_REPORTRDY Publish configuration for event REPORTRDY 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event REPORTRDY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ACCOF Publish configuration for event ACCOF 0x188 read-write 0x00000000 0x20 CHIDX DPPI channel that event ACCOF will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_DBLRDY Publish configuration for event DBLRDY 0x18C read-write 0x00000000 0x20 CHIDX DPPI channel that event DBLRDY will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x190 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 REPORTRDY_READCLRACC Shortcut between event REPORTRDY and task READCLRACC 0 0 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 SAMPLERDY_STOP Shortcut between event SAMPLERDY and task STOP 1 1 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 REPORTRDY_RDCLRACC Shortcut between event REPORTRDY and task RDCLRACC 2 2 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 REPORTRDY_STOP Shortcut between event REPORTRDY and task STOP 3 3 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DBLRDY_RDCLRDBL Shortcut between event DBLRDY and task RDCLRDBL 4 4 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 DBLRDY_STOP Shortcut between event DBLRDY and task STOP 5 5 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 SAMPLERDY_READCLRACC Shortcut between event SAMPLERDY and task READCLRACC 6 6 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 SAMPLERDY Write '1' to enable interrupt for event SAMPLERDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 REPORTRDY Write '1' to enable interrupt for event REPORTRDY 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ACCOF Write '1' to enable interrupt for event ACCOF 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 DBLRDY Write '1' to enable interrupt for event DBLRDY 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 STOPPED Write '1' to enable interrupt for event STOPPED 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 SAMPLERDY Write '1' to disable interrupt for event SAMPLERDY 0 0 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 REPORTRDY Write '1' to disable interrupt for event REPORTRDY 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ACCOF Write '1' to disable interrupt for event ACCOF 2 2 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 DBLRDY Write '1' to disable interrupt for event DBLRDY 3 3 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 STOPPED Write '1' to disable interrupt for event STOPPED 4 4 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ENABLE Enable the quadrature decoder 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable the quadrature decoder 0 0 Disabled Disable 0x0 Enabled Enable 0x1 LEDPOL LED output pin polarity 0x504 read-write 0x00000000 0x20 LEDPOL LED output pin polarity 0 0 ActiveLow Led active on output pin low 0x0 ActiveHigh Led active on output pin high 0x1 SAMPLEPER Sample period 0x508 read-write 0x00000000 0x20 SAMPLEPER Sample period. The SAMPLE register will be updated for every new sample 0 3 128us 128 us 0x0 256us 256 us 0x1 512us 512 us 0x2 1024us 1024 us 0x3 2048us 2048 us 0x4 4096us 4096 us 0x5 8192us 8192 us 0x6 16384us 16384 us 0x7 32ms 32768 us 0x8 65ms 65536 us 0x9 131ms 131072 us 0xA SAMPLE Motion sample value 0x50C read-only 0x00000000 int32_t 0x20 SAMPLE Last motion sample 0 31 REPORTPER Number of samples to be taken before REPORTRDY and DBLRDY events can be generated 0x510 read-write 0x00000000 0x20 REPORTPER Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. 0 3 10Smpl 10 samples/report 0x0 40Smpl 40 samples/report 0x1 80Smpl 80 samples/report 0x2 120Smpl 120 samples/report 0x3 160Smpl 160 samples/report 0x4 200Smpl 200 samples/report 0x5 240Smpl 240 samples/report 0x6 280Smpl 280 samples/report 0x7 1Smpl 1 sample/report 0x8 ACC Register accumulating the valid transitions 0x514 read-only 0x00000000 int32_t 0x20 ACC Register accumulating all valid samples (not double transition) read from the SAMPLE register. 0 31 ACCREAD Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task 0x518 read-only 0x00000000 int32_t 0x20 ACCREAD Snapshot of the ACC register. 0 31 PSEL Unspecified QDEC_PSEL read-write 0x51C LED Pin select for LED signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 A Pin select for A signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 B Pin select for B signal 0x008 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 DBFEN Enable input debounce filters 0x528 read-write 0x00000000 0x20 DBFEN Enable input debounce filters 0 0 Disabled Debounce input filters disabled 0x0 Enabled Debounce input filters enabled 0x1 LEDPRE Time period the LED is switched ON prior to sampling 0x540 read-write 0x00000010 0x20 LEDPRE Period in us the LED is switched on prior to sampling 0 8 ACCDBL Register accumulating the number of detected double transitions 0x544 read-only 0x00000000 0x20 ACCDBL Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). 0 3 ACCDBLREAD Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task 0x548 read-only 0x00000000 0x20 ACCDBLREAD Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. 0 3 GLOBAL_QDEC130_S Quadrature Decoder 1 0x5F994000 QDEC130 404 GLOBAL_QDEC131_NS Quadrature Decoder 2 0x4F995000 QDEC131 405 GLOBAL_QDEC131_S Quadrature Decoder 3 0x5F995000 QDEC131 405 GLOBAL_I2S131_NS Inter-IC Sound 2 0x4F997000 I2S131 407 GLOBAL_I2S131_S Inter-IC Sound 3 0x5F997000 I2S131 407 GLOBAL_DPPIC133_NS Distributed programmable peripheral interconnect controller 8 0x4F9A1000 GLOBAL_DPPIC133_S Distributed programmable peripheral interconnect controller 9 0x5F9A1000 GLOBAL_TIMER130_NS Timer/Counter 4 0x4F9A2000 TIMER130 418 GLOBAL_TIMER130_S Timer/Counter 5 0x5F9A2000 TIMER130 418 GLOBAL_TIMER131_NS Timer/Counter 6 0x4F9A3000 TIMER131 419 GLOBAL_TIMER131_S Timer/Counter 7 0x5F9A3000 TIMER131 419 GLOBAL_PWM130_NS Pulse width modulation unit 2 0x4F9A4000 PWM130 420 GLOBAL_PWM130_S Pulse width modulation unit 3 0x5F9A4000 PWM130 420 GLOBAL_SPIM130_NS Serial Peripheral Interface Master with EasyDMA 4 0x4F9A5000 SERIAL0 421 GLOBAL_SPIS130_NS SPI Slave 2 0x4F9A5000 GLOBAL_SPIM130_NS SERIAL0 421 GLOBAL_TWIM130_NS I2C compatible Two-Wire Master Interface with EasyDMA 0 0x4F9A5000 GLOBAL_SPIM130_NS TWIM 0 0x1000 registers SERIAL0 421 TWIM 0x20 TASKS_STARTRX Start TWI receive sequence 0x000 write-only 0x00000000 0x20 TASKS_STARTRX Start TWI receive sequence 0 0 Trigger Trigger task 0x1 TASKS_STARTTX Start TWI transmit sequence 0x008 write-only 0x00000000 0x20 TASKS_STARTTX Start TWI transmit sequence 0 0 Trigger Trigger task 0x1 TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0x014 write-only 0x00000000 0x20 TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0 0 Trigger Trigger task 0x1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only 0x00000000 0x20 TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_RESUME Resume TWI transaction 0x020 write-only 0x00000000 0x20 TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 0x1 SUBSCRIBE_STARTRX Subscribe configuration for task STARTRX 0x080 read-write 0x00000000 0x20 CHIDX DPPI channel that task STARTRX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STARTTX Subscribe configuration for task STARTTX 0x088 read-write 0x00000000 0x20 CHIDX DPPI channel that task STARTTX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x094 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_SUSPEND Subscribe configuration for task SUSPEND 0x09C read-write 0x00000000 0x20 CHIDX DPPI channel that task SUSPEND will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_RESUME Subscribe configuration for task RESUME 0x0A0 read-write 0x00000000 0x20 CHIDX DPPI channel that task RESUME will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_STOPPED TWI stopped 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR TWI error 0x124 read-write 0x00000000 0x20 EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_SUSPENDED SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write 0x00000000 0x20 EVENTS_SUSPENDED SUSPEND task has been issued, TWI traffic is now suspended. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXSTARTED Receive sequence started 0x14C read-write 0x00000000 0x20 EVENTS_RXSTARTED Receive sequence started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write 0x00000000 0x20 EVENTS_TXSTARTED Transmit sequence started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_LASTRX Byte boundary, starting to receive the last byte 0x15C read-write 0x00000000 0x20 EVENTS_LASTRX Byte boundary, starting to receive the last byte 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0x160 read-write 0x00000000 0x20 EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0x174 read-write 0x00000000 0x20 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0x178 read-write 0x00000000 0x20 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ERROR Publish configuration for event ERROR 0x1A4 read-write 0x00000000 0x20 CHIDX DPPI channel that event ERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_SUSPENDED Publish configuration for event SUSPENDED 0x1C8 read-write 0x00000000 0x20 CHIDX DPPI channel that event SUSPENDED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXSTARTED Publish configuration for event RXSTARTED 0x1CC read-write 0x00000000 0x20 CHIDX DPPI channel that event RXSTARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXSTARTED Publish configuration for event TXSTARTED 0x1D0 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXSTARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_LASTRX Publish configuration for event LASTRX 0x1DC read-write 0x00000000 0x20 CHIDX DPPI channel that event LASTRX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_LASTTX Publish configuration for event LASTTX 0x1E0 read-write 0x00000000 0x20 CHIDX DPPI channel that event LASTTX will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXBUSERROR Publish configuration for event RXBUSERROR 0x1F4 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXBUSERROR Publish configuration for event TXBUSERROR 0x1F8 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 LASTTX_STARTRX Shortcut between event LASTTX and task STARTRX 7 7 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTTX_SUSPEND Shortcut between event LASTTX and task SUSPEND 8 8 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTTX_STOP Shortcut between event LASTTX and task STOP 9 9 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTRX_STARTTX Shortcut between event LASTRX and task STARTTX 10 10 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 LASTRX_STOP Shortcut between event LASTRX and task STOP 12 12 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0x0 Enabled Enable 0x1 SUSPENDED Enable or disable interrupt for event SUSPENDED 18 18 Disabled Disable 0x0 Enabled Enable 0x1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0x0 Enabled Enable 0x1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0x0 Enabled Enable 0x1 LASTRX Enable or disable interrupt for event LASTRX 23 23 Disabled Disable 0x0 Enabled Enable 0x1 LASTTX Enable or disable interrupt for event LASTTX 24 24 Disabled Disable 0x0 Enabled Enable 0x1 RXBUSERROR Enable or disable interrupt for event RXBUSERROR 29 29 Disabled Disable 0x0 Enabled Enable 0x1 TXBUSERROR Enable or disable interrupt for event TXBUSERROR 30 30 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 SUSPENDED Write '1' to enable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 LASTRX Write '1' to enable interrupt for event LASTRX 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 LASTTX Write '1' to enable interrupt for event LASTTX 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXBUSERROR Write '1' to enable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXBUSERROR Write '1' to enable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 SUSPENDED Write '1' to disable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 LASTRX Write '1' to disable interrupt for event LASTRX 23 23 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 LASTTX Write '1' to disable interrupt for event LASTTX 24 24 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXBUSERROR Write '1' to disable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXBUSERROR Write '1' to disable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSRC Error source 0x4C4 read-write 0x00000000 oneToClear 0x20 OVERRUN Overrun error 0 0 NotReceived Error did not occur 0x0 Received Error occurred 0x1 ANACK NACK received after sending the address (write '1' to clear) 1 1 NotReceived Error did not occur 0x0 Received Error occurred 0x1 DNACK NACK received after sending a data byte (write '1' to clear) 2 2 NotReceived Error did not occur 0x0 Received Error occurred 0x1 ENABLE Enable TWIM 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable TWIM 0 3 Disabled Disable TWIM 0x0 Enabled Enable TWIM 0x6 PSEL Unspecified TWIM_PSEL read-write 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 FREQUENCY TWI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 0x20 FREQUENCY TWI master clock frequency 0 31 K100 100 kbps 0x01980000 K250 250 kbps 0x04000000 K400 400 kbps 0x06400000 K1000 1000 kbps 0x0FF00000 RXD RXD EasyDMA channel TWIM_RXD read-write 0x534 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in receive buffer 0 14 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 14 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 2 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 TXD TXD EasyDMA channel TWIM_TXD read-write 0x544 PTR Data pointer 0x000 read-write 0x00000000 0x20 PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in transmit buffer 0 14 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 14 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 2 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 ADDRESS Address used in the TWI transfer 0x588 read-write 0x00000000 0x20 ADDRESS Address used in the TWI transfer 0 6 DMA Unspecified TWIM_DMA read-write 0x5B0 RX Unspecified TWIM_DMA_RX read-write 0x000 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 TX Unspecified TWIM_DMA_TX read-write 0x008 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 GLOBAL_TWIS130_NS I2C compatible Two-Wire Slave Interface with EasyDMA 0 0x4F9A5000 GLOBAL_SPIM130_NS TWIS 0 0x1000 registers SERIAL0 421 TWIS 0x20 TASKS_STOP Stop TWI transaction 0x014 write-only 0x00000000 0x20 TASKS_STOP Stop TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only 0x00000000 0x20 TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_RESUME Resume TWI transaction 0x020 write-only 0x00000000 0x20 TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 0x1 TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0x030 write-only 0x00000000 0x20 TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0 0 Trigger Trigger task 0x1 TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0x034 write-only 0x00000000 0x20 TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0 0 Trigger Trigger task 0x1 SUBSCRIBE_STOP Subscribe configuration for task STOP 0x094 read-write 0x00000000 0x20 CHIDX DPPI channel that task STOP will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_SUSPEND Subscribe configuration for task SUSPEND 0x09C read-write 0x00000000 0x20 CHIDX DPPI channel that task SUSPEND will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_RESUME Subscribe configuration for task RESUME 0x0A0 read-write 0x00000000 0x20 CHIDX DPPI channel that task RESUME will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_PREPARERX Subscribe configuration for task PREPARERX 0x0B0 read-write 0x00000000 0x20 CHIDX DPPI channel that task PREPARERX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 SUBSCRIBE_PREPARETX Subscribe configuration for task PREPARETX 0x0B4 read-write 0x00000000 0x20 CHIDX DPPI channel that task PREPARETX will subscribe to 0 7 EN 31 31 Disabled Disable subscription 0x0 Enabled Enable subscription 0x1 EVENTS_STOPPED TWI stopped 0x104 read-write 0x00000000 0x20 EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_ERROR TWI error 0x124 read-write 0x00000000 0x20 EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXSTARTED Receive sequence started 0x14C read-write 0x00000000 0x20 EVENTS_RXSTARTED Receive sequence started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write 0x00000000 0x20 EVENTS_TXSTARTED Transmit sequence started 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_WRITE Write command received 0x164 read-write 0x00000000 0x20 EVENTS_WRITE Write command received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_READ Read command received 0x168 read-write 0x00000000 0x20 EVENTS_READ Read command received 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0x174 read-write 0x00000000 0x20 EVENTS_RXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0x178 read-write 0x00000000 0x20 EVENTS_TXBUSERROR This event is generated if an error occurs during the bus transfer. 0 0 NotGenerated Event not generated 0x0 Generated Event generated 0x1 PUBLISH_STOPPED Publish configuration for event STOPPED 0x184 read-write 0x00000000 0x20 CHIDX DPPI channel that event STOPPED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_ERROR Publish configuration for event ERROR 0x1A4 read-write 0x00000000 0x20 CHIDX DPPI channel that event ERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXSTARTED Publish configuration for event RXSTARTED 0x1CC read-write 0x00000000 0x20 CHIDX DPPI channel that event RXSTARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXSTARTED Publish configuration for event TXSTARTED 0x1D0 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXSTARTED will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_WRITE Publish configuration for event WRITE 0x1E4 read-write 0x00000000 0x20 CHIDX DPPI channel that event WRITE will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_READ Publish configuration for event READ 0x1E8 read-write 0x00000000 0x20 CHIDX DPPI channel that event READ will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_RXBUSERROR Publish configuration for event RXBUSERROR 0x1F4 read-write 0x00000000 0x20 CHIDX DPPI channel that event RXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 PUBLISH_TXBUSERROR Publish configuration for event TXBUSERROR 0x1F8 read-write 0x00000000 0x20 CHIDX DPPI channel that event TXBUSERROR will publish to 0 7 EN 31 31 Disabled Disable publishing 0x0 Enabled Enable publishing 0x1 SHORTS Shortcuts between local events and tasks 0x200 read-write 0x00000000 0x20 WRITE_SUSPEND Shortcut between event WRITE and task SUSPEND 13 13 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 READ_SUSPEND Shortcut between event READ and task SUSPEND 14 14 Disabled Disable shortcut 0x0 Enabled Enable shortcut 0x1 INTEN Enable or disable interrupt 0x300 read-write 0x00000000 0x20 STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0x0 Enabled Enable 0x1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0x0 Enabled Enable 0x1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0x0 Enabled Enable 0x1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0x0 Enabled Enable 0x1 WRITE Enable or disable interrupt for event WRITE 25 25 Disabled Disable 0x0 Enabled Enable 0x1 READ Enable or disable interrupt for event READ 26 26 Disabled Disable 0x0 Enabled Enable 0x1 RXBUSERROR Enable or disable interrupt for event RXBUSERROR 29 29 Disabled Disable 0x0 Enabled Enable 0x1 TXBUSERROR Enable or disable interrupt for event TXBUSERROR 30 30 Disabled Disable 0x0 Enabled Enable 0x1 INTENSET Enable interrupt 0x304 read-write 0x00000000 0x20 STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 WRITE Write '1' to enable interrupt for event WRITE 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 READ Write '1' to enable interrupt for event READ 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 RXBUSERROR Write '1' to enable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 TXBUSERROR Write '1' to enable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Set Enable 0x1 INTENCLR Disable interrupt 0x308 read-write 0x00000000 0x20 STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 WRITE Write '1' to disable interrupt for event WRITE 25 25 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 READ Write '1' to disable interrupt for event READ 26 26 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 RXBUSERROR Write '1' to disable interrupt for event RXBUSERROR 29 29 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 TXBUSERROR Write '1' to disable interrupt for event TXBUSERROR 30 30 read Disabled Read: Disabled 0x0 Enabled Read: Enabled 0x1 write Clear Disable 0x1 ERRORSRC Error source 0x4D0 read-write 0x00000000 oneToClear 0x20 OVERFLOW RX buffer overflow detected, and prevented 0 0 NotDetected Error did not occur 0x0 Detected Error occurred 0x1 DNACK NACK sent after receiving a data byte 2 2 NotReceived Error did not occur 0x0 Received Error occurred 0x1 OVERREAD TX buffer over-read detected, and prevented 3 3 NotDetected Error did not occur 0x0 Detected Error occurred 0x1 MATCH Status register indicating which address had a match 0x4D4 read-only 0x00000000 0x20 MATCH Indication of which address in ADDRESS that matched the incoming address 0 0 ENABLE Enable TWIS 0x500 read-write 0x00000000 0x20 ENABLE Enable or disable TWIS 0 3 Disabled Disable TWIS 0x0 Enabled Enable TWIS 0x9 PSEL Unspecified TWIS_PSEL read-write 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF 0x20 PIN Pin number 0 4 PORT Port number 5 8 CONNECT Connection 31 31 Disconnected Disconnect 0x1 Connected Connect 0x0 RXD RXD EasyDMA channel TWIS_RXD read-write 0x534 PTR RXD Data pointer 0x000 read-write 0x00000000 0x20 PTR RXD Data pointer 0 31 MAXCNT Maximum number of bytes in RXD buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in RXD buffer 0 14 AMOUNT Number of bytes transferred in the last RXD transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last RXD transaction 0 14 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 TXD TXD EasyDMA channel TWIS_TXD read-write 0x544 PTR TXD Data pointer 0x000 read-write 0x00000000 0x20 PTR TXD Data pointer 0 31 MAXCNT Maximum number of bytes in TXD buffer 0x004 read-write 0x00000000 0x20 MAXCNT Maximum number of bytes in TXD buffer 0 14 AMOUNT Number of bytes transferred in the last TXD transaction 0x008 read-only 0x00000000 0x20 AMOUNT Number of bytes transferred in the last TXD transaction 0 14 LIST EasyDMA list type 0x00C read-write 0x00000000 0x20 LIST List type 0 1 Disabled Disable EasyDMA list 0x0 ArrayList Use array list 0x1 0x2 0x4 ADDRESS[%s] Description collection: TWI slave address n 0x588 read-write 0x00000000 0x20 ADDRESS TWI slave address 0 6 CONFIG Configuration register for the address match mechanism 0x594 read-write 0x00000001 0x20 ADDRESS0 Enable or disable address matching on ADDRESS[0] 0 0 Disabled Disabled 0x0 Enabled Enabled 0x1 ADDRESS1 Enable or disable address matching on ADDRESS[1] 1 1 Disabled Disabled 0x0 Enabled Enabled 0x1 DMA Unspecified TWIS_DMA read-write 0x5B0 RX Unspecified TWIS_DMA_RX read-write 0x000 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 TX Unspecified TWIS_DMA_TX read-write 0x008 TERMINATEONBUSERROR Terminate the transaction if a BUSERROR event is detected. 0x000 read-write 0x00000000 0x20 ENABLE 0 0 Disabled Disable 0x0 Enabled Enable 0x1 BUSERRORADDRESS Address of transaction that generated the last BUSERROR event. 0x004 read-only 0x00000000 0x20 ADDRESS 0 31 ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0x5C0 read-write 0x00000000 0x20 ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0 7 GLOBAL_UARTE130_NS UART with EasyDMA 2 0x4F9A5000 GLOBAL_SPIM130_NS SERIAL0 421 GLOBAL_SPIM130_S Serial Peripheral Interface Master with EasyDMA 5 0x5F9A5000 SERIAL0 421 GLOBAL_SPIS130_S SPI Slave 3 0x5F9A5000 GLOBAL_SPIM130_S SERIAL0 421 GLOBAL_TWIM130_S I2C compatible Two-Wire Master Interface with EasyDMA 1 0x5F9A5000 GLOBAL_SPIM130_S SERIAL0 421 GLOBAL_TWIS130_S I2C compatible Two-Wire Slave Interface with EasyDMA 1 0x5F9A5000 GLOBAL_SPIM130_S SERIAL0 421 GLOBAL_UARTE130_S UART with EasyDMA 3 0x5F9A5000 GLOBAL_SPIM130_S SERIAL0 421 GLOBAL_SPIM131_NS Serial Peripheral Interface Master with EasyDMA 6 0x4F9A6000 SERIAL1 422 GLOBAL_SPIS131_NS SPI Slave 4 0x4F9A6000 GLOBAL_SPIM131_NS SERIAL1 422 GLOBAL_TWIM131_NS I2C compatible Two-Wire Master Interface with EasyDMA 2 0x4F9A6000 GLOBAL_SPIM131_NS SERIAL1 422 GLOBAL_TWIS131_NS I2C compatible Two-Wire Slave Interface with EasyDMA 2 0x4F9A6000 GLOBAL_SPIM131_NS SERIAL1 422 GLOBAL_UARTE131_NS UART with EasyDMA 4 0x4F9A6000 GLOBAL_SPIM131_NS SERIAL1 422 GLOBAL_SPIM131_S Serial Peripheral Interface Master with EasyDMA 7 0x5F9A6000 SERIAL1 422 GLOBAL_SPIS131_S SPI Slave 5 0x5F9A6000 GLOBAL_SPIM131_S SERIAL1 422 GLOBAL_TWIM131_S I2C compatible Two-Wire Master Interface with EasyDMA 3 0x5F9A6000 GLOBAL_SPIM131_S SERIAL1 422 GLOBAL_TWIS131_S I2C compatible Two-Wire Slave Interface with EasyDMA 3 0x5F9A6000 GLOBAL_SPIM131_S SERIAL1 422 GLOBAL_UARTE131_S UART with EasyDMA 5 0x5F9A6000 GLOBAL_SPIM131_S SERIAL1 422 GLOBAL_DPPIC134_NS Distributed programmable peripheral interconnect controller 10 0x4F9B1000 GLOBAL_DPPIC134_S Distributed programmable peripheral interconnect controller 11 0x5F9B1000 GLOBAL_TIMER132_NS Timer/Counter 8 0x4F9B2000 TIMER132 434 GLOBAL_TIMER132_S Timer/Counter 9 0x5F9B2000 TIMER132 434 GLOBAL_TIMER133_NS Timer/Counter 10 0x4F9B3000 TIMER133 435 GLOBAL_TIMER133_S Timer/Counter 11 0x5F9B3000 TIMER133 435 GLOBAL_PWM131_NS Pulse width modulation unit 4 0x4F9B4000 PWM131 436 GLOBAL_PWM131_S Pulse width modulation unit 5 0x5F9B4000 PWM131 436 GLOBAL_SPIM132_NS Serial Peripheral Interface Master with EasyDMA 8 0x4F9B5000 SERIAL2 437 GLOBAL_SPIS132_NS SPI Slave 6 0x4F9B5000 GLOBAL_SPIM132_NS SERIAL2 437 GLOBAL_TWIM132_NS I2C compatible Two-Wire Master Interface with EasyDMA 4 0x4F9B5000 GLOBAL_SPIM132_NS SERIAL2 437 GLOBAL_TWIS132_NS I2C compatible Two-Wire Slave Interface with EasyDMA 4 0x4F9B5000 GLOBAL_SPIM132_NS SERIAL2 437 GLOBAL_UARTE132_NS UART with EasyDMA 6 0x4F9B5000 GLOBAL_SPIM132_NS SERIAL2 437 GLOBAL_SPIM132_S Serial Peripheral Interface Master with EasyDMA 9 0x5F9B5000 SERIAL2 437 GLOBAL_SPIS132_S SPI Slave 7 0x5F9B5000 GLOBAL_SPIM132_S SERIAL2 437 GLOBAL_TWIM132_S I2C compatible Two-Wire Master Interface with EasyDMA 5 0x5F9B5000 GLOBAL_SPIM132_S SERIAL2 437 GLOBAL_TWIS132_S I2C compatible Two-Wire Slave Interface with EasyDMA 5 0x5F9B5000 GLOBAL_SPIM132_S SERIAL2 437 GLOBAL_UARTE132_S UART with EasyDMA 7 0x5F9B5000 GLOBAL_SPIM132_S SERIAL2 437 GLOBAL_SPIM133_NS Serial Peripheral Interface Master with EasyDMA 10 0x4F9B6000 SERIAL3 438 GLOBAL_SPIS133_NS SPI Slave 8 0x4F9B6000 GLOBAL_SPIM133_NS SERIAL3 438 GLOBAL_TWIM133_NS I2C compatible Two-Wire Master Interface with EasyDMA 6 0x4F9B6000 GLOBAL_SPIM133_NS SERIAL3 438 GLOBAL_TWIS133_NS I2C compatible Two-Wire Slave Interface with EasyDMA 6 0x4F9B6000 GLOBAL_SPIM133_NS SERIAL3 438 GLOBAL_UARTE133_NS UART with EasyDMA 8 0x4F9B6000 GLOBAL_SPIM133_NS SERIAL3 438 GLOBAL_SPIM133_S Serial Peripheral Interface Master with EasyDMA 11 0x5F9B6000 SERIAL3 438 GLOBAL_SPIS133_S SPI Slave 9 0x5F9B6000 GLOBAL_SPIM133_S SERIAL3 438 GLOBAL_TWIM133_S I2C compatible Two-Wire Master Interface with EasyDMA 7 0x5F9B6000 GLOBAL_SPIM133_S SERIAL3 438 GLOBAL_TWIS133_S I2C compatible Two-Wire Slave Interface with EasyDMA 7 0x5F9B6000 GLOBAL_SPIM133_S SERIAL3 438 GLOBAL_UARTE133_S UART with EasyDMA 9 0x5F9B6000 GLOBAL_SPIM133_S SERIAL3 438 GLOBAL_DPPIC135_NS Distributed programmable peripheral interconnect controller 12 0x4F9C1000 GLOBAL_DPPIC135_S Distributed programmable peripheral interconnect controller 13 0x5F9C1000 GLOBAL_TIMER134_NS Timer/Counter 12 0x4F9C2000 TIMER134 450 GLOBAL_TIMER134_S Timer/Counter 13 0x5F9C2000 TIMER134 450 GLOBAL_TIMER135_NS Timer/Counter 14 0x4F9C3000 TIMER135 451 GLOBAL_TIMER135_S Timer/Counter 15 0x5F9C3000 TIMER135 451 GLOBAL_PWM132_NS Pulse width modulation unit 6 0x4F9C4000 PWM132 452 GLOBAL_PWM132_S Pulse width modulation unit 7 0x5F9C4000 PWM132 452 GLOBAL_SPIM134_NS Serial Peripheral Interface Master with EasyDMA 12 0x4F9C5000 SERIAL4 453 GLOBAL_SPIS134_NS SPI Slave 10 0x4F9C5000 GLOBAL_SPIM134_NS SERIAL4 453 GLOBAL_TWIM134_NS I2C compatible Two-Wire Master Interface with EasyDMA 8 0x4F9C5000 GLOBAL_SPIM134_NS SERIAL4 453 GLOBAL_TWIS134_NS I2C compatible Two-Wire Slave Interface with EasyDMA 8 0x4F9C5000 GLOBAL_SPIM134_NS SERIAL4 453 GLOBAL_UARTE134_NS UART with EasyDMA 10 0x4F9C5000 GLOBAL_SPIM134_NS SERIAL4 453 GLOBAL_SPIM134_S Serial Peripheral Interface Master with EasyDMA 13 0x5F9C5000 SERIAL4 453 GLOBAL_SPIS134_S SPI Slave 11 0x5F9C5000 GLOBAL_SPIM134_S SERIAL4 453 GLOBAL_TWIM134_S I2C compatible Two-Wire Master Interface with EasyDMA 9 0x5F9C5000 GLOBAL_SPIM134_S SERIAL4 453 GLOBAL_TWIS134_S I2C compatible Two-Wire Slave Interface with EasyDMA 9 0x5F9C5000 GLOBAL_SPIM134_S SERIAL4 453 GLOBAL_UARTE134_S UART with EasyDMA 11 0x5F9C5000 GLOBAL_SPIM134_S SERIAL4 453 GLOBAL_SPIM135_NS Serial Peripheral Interface Master with EasyDMA 14 0x4F9C6000 SERIAL5 454 GLOBAL_SPIS135_NS SPI Slave 12 0x4F9C6000 GLOBAL_SPIM135_NS SERIAL5 454 GLOBAL_TWIM135_NS I2C compatible Two-Wire Master Interface with EasyDMA 10 0x4F9C6000 GLOBAL_SPIM135_NS SERIAL5 454 GLOBAL_TWIS135_NS I2C compatible Two-Wire Slave Interface with EasyDMA 10 0x4F9C6000 GLOBAL_SPIM135_NS SERIAL5 454 GLOBAL_UARTE135_NS UART with EasyDMA 12 0x4F9C6000 GLOBAL_SPIM135_NS SERIAL5 454 GLOBAL_SPIM135_S Serial Peripheral Interface Master with EasyDMA 15 0x5F9C6000 SERIAL5 454 GLOBAL_SPIS135_S SPI Slave 13 0x5F9C6000 GLOBAL_SPIM135_S SERIAL5 454 GLOBAL_TWIM135_S I2C compatible Two-Wire Master Interface with EasyDMA 11 0x5F9C6000 GLOBAL_SPIM135_S SERIAL5 454 GLOBAL_TWIS135_S I2C compatible Two-Wire Slave Interface with EasyDMA 11 0x5F9C6000 GLOBAL_SPIM135_S SERIAL5 454 GLOBAL_UARTE135_S UART with EasyDMA 13 0x5F9C6000 GLOBAL_SPIM135_S SERIAL5 454 GLOBAL_DPPIC136_NS Distributed programmable peripheral interconnect controller 14 0x4F9D1000 GLOBAL_DPPIC136_S Distributed programmable peripheral interconnect controller 15 0x5F9D1000 GLOBAL_TIMER136_NS Timer/Counter 16 0x4F9D2000 TIMER136 466 GLOBAL_TIMER136_S Timer/Counter 17 0x5F9D2000 TIMER136 466 GLOBAL_TIMER137_NS Timer/Counter 18 0x4F9D3000 TIMER137 467 GLOBAL_TIMER137_S Timer/Counter 19 0x5F9D3000 TIMER137 467 GLOBAL_PWM133_NS Pulse width modulation unit 8 0x4F9D4000 PWM133 468 GLOBAL_PWM133_S Pulse width modulation unit 9 0x5F9D4000 PWM133 468 GLOBAL_SPIM136_NS Serial Peripheral Interface Master with EasyDMA 16 0x4F9D5000 SERIAL6 469 GLOBAL_SPIS136_NS SPI Slave 14 0x4F9D5000 GLOBAL_SPIM136_NS SERIAL6 469 GLOBAL_TWIM136_NS I2C compatible Two-Wire Master Interface with EasyDMA 12 0x4F9D5000 GLOBAL_SPIM136_NS SERIAL6 469 GLOBAL_TWIS136_NS I2C compatible Two-Wire Slave Interface with EasyDMA 12 0x4F9D5000 GLOBAL_SPIM136_NS SERIAL6 469 GLOBAL_UARTE136_NS UART with EasyDMA 14 0x4F9D5000 GLOBAL_SPIM136_NS SERIAL6 469 GLOBAL_SPIM136_S Serial Peripheral Interface Master with EasyDMA 17 0x5F9D5000 SERIAL6 469 GLOBAL_SPIS136_S SPI Slave 15 0x5F9D5000 GLOBAL_SPIM136_S SERIAL6 469 GLOBAL_TWIM136_S I2C compatible Two-Wire Master Interface with EasyDMA 13 0x5F9D5000 GLOBAL_SPIM136_S SERIAL6 469 GLOBAL_TWIS136_S I2C compatible Two-Wire Slave Interface with EasyDMA 13 0x5F9D5000 GLOBAL_SPIM136_S SERIAL6 469 GLOBAL_UARTE136_S UART with EasyDMA 15 0x5F9D5000 GLOBAL_SPIM136_S SERIAL6 469 GLOBAL_SPIM137_NS Serial Peripheral Interface Master with EasyDMA 18 0x4F9D6000 SERIAL7 470 GLOBAL_SPIS137_NS SPI Slave 16 0x4F9D6000 GLOBAL_SPIM137_NS SERIAL7 470 GLOBAL_TWIM137_NS I2C compatible Two-Wire Master Interface with EasyDMA 14 0x4F9D6000 GLOBAL_SPIM137_NS SERIAL7 470 GLOBAL_TWIS137_NS I2C compatible Two-Wire Slave Interface with EasyDMA 14 0x4F9D6000 GLOBAL_SPIM137_NS SERIAL7 470 GLOBAL_UARTE137_NS UART with EasyDMA 16 0x4F9D6000 GLOBAL_SPIM137_NS SERIAL7 470 GLOBAL_SPIM137_S Serial Peripheral Interface Master with EasyDMA 19 0x5F9D6000 SERIAL7 470 GLOBAL_SPIS137_S SPI Slave 17 0x5F9D6000 GLOBAL_SPIM137_S SERIAL7 470 GLOBAL_TWIM137_S I2C compatible Two-Wire Master Interface with EasyDMA 15 0x5F9D6000 GLOBAL_SPIM137_S SERIAL7 470 GLOBAL_TWIS137_S I2C compatible Two-Wire Slave Interface with EasyDMA 15 0x5F9D6000 GLOBAL_SPIM137_S SERIAL7 470 GLOBAL_UARTE137_S UART with EasyDMA 17 0x5F9D6000 GLOBAL_SPIM137_S SERIAL7 470