/*
 * Instance header file for PIC32CX1025SG61128
 *
 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

/* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */
#ifndef _PIC32CXSG61_RAMECC_INSTANCE_
#define _PIC32CXSG61_RAMECC_INSTANCE_


/* ========== Instance Parameter definitions for RAMECC peripheral ========== */
#define RAMECC_INSTANCE_ID                       (48)       /* Instance index for RAMECC */
#define RAMECC_RAMADDR_BITS                      (13)       /* Number of RAM address bits */
#define RAMECC_RAMBANK_NUM                       (4)        /* Number of RAM banks */

#endif /* _PIC32CXSG61_RAMECC_INSTANCE_ */