/* * Instance header file for PIC32CX1025SG60128 * * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * */ /* file generated from device description file (ATDF) version 2023-03-17T09:48:46Z */ #ifndef _PIC32CXSG60_TCC3_INSTANCE_ #define _PIC32CXSG60_TCC3_INSTANCE_ /* ========== Instance Parameter definitions for TCC3 peripheral ========== */ #define TCC3_CC_NUM (2) /* Number of Compare/Capture units */ #define TCC3_DITHERING (0) /* Dithering feature implemented */ #define TCC3_DMAC_ID_MC0 (39) /* Indexes of DMA Match/Compare 0 trigger */ #define TCC3_DMAC_ID_MC1 (40) /* Indexes of DMA Match/Compare 1 trigger */ #define TCC3_DMAC_ID_OVF (38) /* DMA overflow/underflow/retrigger trigger */ #define TCC3_DTI (0) /* Dead-Time-Insertion feature implemented */ #define TCC3_EXT (0) /* Coding of implemented extended features */ #define TCC3_GCLK_ID (29) /* Index of Generic Clock */ #define TCC3_INSTANCE_ID (68) /* Instance index for TCC3 */ #define TCC3_MASTER_SLAVE_MODE (0) /* TCC type 0 : NA, 1 : Master, 2 : Slave */ #define TCC3_OTMX (0) /* Output Matrix feature implemented */ #define TCC3_OW_NUM (2) /* Number of Output Waveforms */ #define TCC3_PG (0) /* Pattern Generation feature implemented */ #define TCC3_SIZE (16) #define TCC3_SWAP (0) /* DTI outputs swap feature implemented */ #endif /* _PIC32CXSG60_TCC3_INSTANCE_ */