/*
 * Instance header file for PIC32CX1025SG41128
 *
 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

/* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */
#ifndef _PIC32CXSG41_CAN0_INSTANCE_
#define _PIC32CXSG41_CAN0_INSTANCE_


/* ========== Instance Parameter definitions for CAN0 peripheral ========== */
#define CAN0_DMAC_ID_DEBUG                       (20)       /* DMA CAN Debug Req */
#define CAN0_GCLK_ID                             (27)       /* Index of Generic Clock */
#define CAN0_INSTANCE_ID                         (64)       /* Instance index for CAN0 */
#define CAN0_MSG_RAM_ADDR                        (0x20000000) 
#define CAN0_QOS_RESET_VAL                       (1)        /* QOS reset value */

#endif /* _PIC32CXSG41_CAN0_INSTANCE_ */