Cypress Semiconductor Cypress tviic2d6m TVIIC2D6M 1.0 TVIIC2D6M (c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company)\n or an affiliate of Cypress Semiconductor Corporation.\n \n SPDX-License-Identifier: Apache-2.0\n \n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n \n http://www.apache.org/licenses/LICENSE-2.0\n \n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an "AS IS" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License. CM7 r0p1 little true true 1 3 0 8 32 0x00000000 0xFFFFFFFF PERI Peripheral interconnect 0x40000000 0 65536 registers TIMEOUT_CTL Timeout control 0x200 32 read-write 0xFFFF 0xFFFF TIMEOUT This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. [15:0] read-write TR_CMD Trigger command 0x220 32 read-write 0x0 0xE0001FFF TR_SEL Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. [7:0] read-write GROUP_SEL Specifies the trigger group: '0'-'15': trigger multiplexer groups. '16'-'31': trigger 1-to-1 groups. [12:8] read-write TR_EDGE Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. '1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. [29:29] read-write OUT_SEL Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. Note: this field is not used for trigger 1-to-1 groups. [30:30] read-write ACTIVATE SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. Note: when ACTIVATE is '1', SW should not modify the other register fields. SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write. [31:31] read-write ECC_CTL ECC control 0x2000 32 read-write 0x10000 0xFF0507FF WORD_ADDR Specifies the word address where the parity is injected. - On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [10:0] read-write ECC_EN Enable ECC: '0': Disabled (on write ECC parity bits will not be correctly written). '1': Enabled. [16:16] read-write ECC_INJ_EN Enable error injection for PERI protection structure SRAM. When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. [18:18] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:24] read-write 11 64 GR[%s] Peripheral group structure 0x00004000 CLOCK_CTL Clock control 0x0 32 read-write 0x0 0xFF00 INT8_DIV Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write SL_CTL Slave control 0x10 32 read-write 0xFFFF 0xFFFF ENABLED_0 Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [0:0] read-write ENABLED_1 Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [1:1] read-write ENABLED_2 Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, PCLK group MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [2:2] read-write ENABLED_3 N/A [3:3] read-write ENABLED_4 N/A [4:4] read-write ENABLED_5 N/A [5:5] read-write ENABLED_6 N/A [6:6] read-write ENABLED_7 N/A [7:7] read-write ENABLED_8 N/A [8:8] read-write ENABLED_9 N/A [9:9] read-write ENABLED_10 N/A [10:10] read-write ENABLED_11 N/A [11:11] read-write ENABLED_12 N/A [12:12] read-write ENABLED_13 N/A [13:13] read-write ENABLED_14 N/A [14:14] read-write ENABLED_15 N/A [15:15] read-write 14 1024 TR_GR[%s] Trigger group 0x00008000 256 4 TR_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x13FF TR_SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. [7:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write 8 1024 TR_1TO1_GR[%s] Trigger 1-to-1 group 0x0000C000 256 4 TR_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x1301 TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. [0:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write PERI_MS Peripheral interconnect, master interface 0x40020000 0 131072 registers 16 64 PPU_PR[%s] Programmable protection structure pair 0x00000000 SL_ADDR Slave region, base address 0x0 32 read-write 0x0 0x0 ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. [31:2] read-write SL_SIZE Slave region, size 0x4 32 read-write 0x0 0x80000000 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. [31:31] read-write SL_ATT0 Slave attributes 0 0x10 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-write PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-write PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-write PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-write PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-write PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-write PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write SL_ATT1 Slave attributes 1 0x14 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-write PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-write PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-write PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-write PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-write PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-write PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-write PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-write PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write SL_ATT2 Slave attributes 2 0x18 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-write PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-write PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-write PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-write PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-write PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-write PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-write PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-write PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-write PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-write PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-write PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-write PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-write PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-write PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-write PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-write PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write MS_ADDR Master region, base address 0x20 32 read-only 0x0 0xFFFFFFC0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. [31:6] read-only MS_SIZE Master region, size 0x24 32 read-only 0x85000000 0x9F000000 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. [28:24] read-only VALID Master region enable: '1': Enabled. [31:31] read-only MS_ATT0 Master attributes 0 0x30 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-only PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-only PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-only PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-only PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-only PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-only PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write MS_ATT1 Master attributes 1 0x34 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-only PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-only PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-only PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-only PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-only PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-only PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-only PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-only PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write MS_ATT2 Master attributes 2 0x38 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-only PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-only PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-only PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-only PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-only PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-only PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-only PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-only PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write MS_ATT3 Master attributes 3 0x3C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-only PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-only PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-only PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-only PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-only PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-only PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-only PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-only PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write 633 64 PPU_FX[%s] Fixed protection structure pair 0x00000800 SL_ADDR Slave region, base address 0x0 32 read-only 0x0 0xFFFFFFFC ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. [31:2] read-only SL_SIZE Slave region, size 0x4 32 read-only 0x80000000 0x9F000000 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-only VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. [31:31] read-only SL_ATT0 Slave attributes 0 0x10 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-write PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-write PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-write PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-write PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-write PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-write PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write SL_ATT1 Slave attributes 1 0x14 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-write PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-write PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-write PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-write PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-write PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-write PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-write PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-write PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write SL_ATT2 Slave attributes 2 0x18 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-write PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-write PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-write PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-write PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-write PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-write PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-write PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-write PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-write PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-write PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-write PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-write PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-write PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-write PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-write PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-write PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write MS_ADDR Master region, base address 0x20 32 read-only 0x0 0xFFFFFFC0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. [31:6] read-only MS_SIZE Master region, size 0x24 32 read-only 0x85000000 0x9F000000 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. [28:24] read-only VALID Master region enable: '1': Enabled. [31:31] read-only MS_ATT0 Master attributes 0 0x30 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-only PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-only PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-only PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-only PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-only PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-only PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write MS_ATT1 Master attributes 1 0x34 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-only PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-only PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-only PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-only PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-only PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-only PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-only PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-only PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write MS_ATT2 Master attributes 2 0x38 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-only PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-only PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-only PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-only PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-only PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-only PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-only PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-only PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write MS_ATT3 Master attributes 3 0x3C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-only PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-only PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-only PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-only PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-only PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-only PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-only PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-only PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write PERI_PCLK Peripheral PCLK groups 0x40040000 0 131072 registers 2 8192 GR[%s] PERI clock domains 0x00000000 DIV_CMD Divider command 0x0 32 read-write 0x3FF03FF 0xC3FF03FF DIV_SEL (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. [7:0] read-write TYPE_SEL Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [9:8] read-write PA_DIV_SEL (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_pclk_root[i]' is used as reference. [23:16] read-write PA_TYPE_SEL Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [25:24] read-write DISABLE Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. [30:30] read-write ENABLE Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_pclk_root[i]' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_pclk_root[i]'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_pclk_root[i]' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. [31:31] read-write 256 4 CLOCK_CTL[%s] Clock control 0xC00 32 read-write 0x3FF 0x3FF DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_pclk_root[i]' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. [7:0] read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [9:8] read-write 256 4 DIV_8_CTL[%s] Divider control (for 8.0 divider) 0x1000 32 read-write 0x0 0xFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write 256 4 DIV_16_CTL[%s] Divider control (for 16.0 divider) 0x1400 32 read-write 0x0 0xFFFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 256 4 DIV_16_5_CTL[%s] Divider control (for 16.5 divider) 0x1800 32 read-write 0x0 0xFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 255 4 DIV_24_5_CTL[%s] Divider control (for 24.5 divider) 0x1C00 32 read-write 0x0 0xFFFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [31:8] read-write CRYPTO Cryptography component 0x40100000 0 65536 registers CTL Control 0x0 32 read-write 0x10002 0x800300F3 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'. [7:4] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_INJ_EN Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. [17:17] read-write ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. When the IP is enabled, the IP register buffer is set to '0'. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 RAM_PWR_CTL SRAM power control 0x8 32 read-write 0x3 0x3 PWR_MODE Set power mode for memory buffer SRAM. [1:0] read-write OFF See CM4_PWR_CTL 0 RSVD undefined 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 RAM_PWR_DELAY_CTL SRAM power delay control 0xC 32 read-write 0x96 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write ECC_CTL ECC control 0x10 32 read-write 0x0 0xFE001FFF WORD_ADDR Specifies the word address where the parity is injected. - On a 32-bit write access to this SRAM address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [12:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write ERROR_STATUS0 Error status 0 0x20 32 read-only 0x0 0x0 DATA32 Specifies error description information. - For INSTR_OPC_ERROR/ INSTR_CC_ERROR/ INSTR_DEV_KEY_ERROR: - Violating instruction (from instruction FIFO). - For BUS_ERROR: - Violating transfer, address. [31:0] read-only ERROR_STATUS1 Error status 1 0x24 32 read-write 0x0 0x80000000 DATA24 Specifies error description information. - For BUS_ERROR: - Violating transfer, read attribute (DATA[0]). - Violating transfer, size attribute (DATA[5:4]). '0': 8-bit transfer, '1': 16 bits transfer, '2': 32-bit transfer. [23:0] read-only IDX Error source: '0': INSTR_OPC_ERROR (instruction FIFO decoder error). '1': INSTR_CC_ERROR (instruction FIFO decoder, VU CC error). '2': BUS_ERROR (bus master interface AHB-Lite bus error). '3': TR_AP_DETECT_ERROR. '4': TR_RC_DETECT_ERROR. '5': INSTR_DEV_KEY_ERROR. '6'-'7': Undefined. [26:24] read-only VALID Specifies if ERROR_STATUS0 and ERROR_STATUS1 specify valid error information. No new error information is captured as long as VALID is '1'; i.e. the error information of the first detected error is NOT overwritten. [31:31] read-write INTR Interrupt register 0x100 32 read-write 0x0 0x3F001F INSTR_FF_LEVEL This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated. [0:0] read-write INSTR_FF_OVERFLOW This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO). [1:1] read-write TR_INITIALIZED This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized. [2:2] read-write TR_DATA_AVAILABLE This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size. [3:3] read-write PR_DATA_AVAILABLE This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value. [4:4] read-write INSTR_OPC_ERROR This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode). When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. [16:16] read-write INSTR_CC_ERROR This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions. When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. [17:17] read-write BUS_ERROR This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface. When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. [18:18] read-write TR_AP_DETECT_ERROR This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value. [19:19] read-write TR_RC_DETECT_ERROR This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value. [20:20] read-write INSTR_DEV_KEY_ERROR This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'. [21:21] read-write INTR_SET Interrupt set register 0x104 32 read-write 0x0 0x3F001F INSTR_FF_LEVEL SW writes a '1' to this field to set the corresponding field in interrupt request register. [0:0] read-write INSTR_FF_OVERFLOW SW writes a '1' to this field to set the corresponding field in interrupt request register. [1:1] read-write TR_INITIALIZED SW writes a '1' to this field to set the corresponding field in interrupt request register. [2:2] read-write TR_DATA_AVAILABLE SW writes a '1' to this field to set the corresponding field in interrupt request register. [3:3] read-write PR_DATA_AVAILABLE SW writes a '1' to this field to set the corresponding field in interrupt request register. [4:4] read-write INSTR_OPC_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [16:16] read-write INSTR_CC_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [17:17] read-write BUS_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [18:18] read-write TR_AP_DETECT_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [19:19] read-write TR_RC_DETECT_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [20:20] read-write INSTR_DEV_KEY_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [21:21] read-write INTR_MASK Interrupt mask register 0x108 32 read-write 0x0 0x3F001F INSTR_FF_LEVEL Mask bit for corresponding field in interrupt request register. [0:0] read-write INSTR_FF_OVERFLOW Mask bit for corresponding field in interrupt request register. [1:1] read-write TR_INITIALIZED Mask bit for corresponding field in interrupt request register. [2:2] read-write TR_DATA_AVAILABLE Mask bit for corresponding field in interrupt request register. [3:3] read-write PR_DATA_AVAILABLE Mask bit for corresponding field in interrupt request register. [4:4] read-write INSTR_OPC_ERROR Mask bit for corresponding field in interrupt request register. [16:16] read-write INSTR_CC_ERROR Mask bit for corresponding field in interrupt request register. [17:17] read-write BUS_ERROR Mask bit for corresponding field in interrupt request register. [18:18] read-write TR_AP_DETECT_ERROR Mask bit for corresponding field in interrupt request register. [19:19] read-write TR_RC_DETECT_ERROR Mask bit for corresponding field in interrupt request register. [20:20] read-write INSTR_DEV_KEY_ERROR Mask bit for corresponding field in interrupt request register. [21:21] read-write INTR_MASKED Interrupt masked register 0x10C 32 read-only 0x0 0x3F001F INSTR_FF_LEVEL Logical and of corresponding request and mask bits. [0:0] read-only INSTR_FF_OVERFLOW Logical and of corresponding request and mask bits. [1:1] read-only TR_INITIALIZED Logical and of corresponding request and mask bits. [2:2] read-only TR_DATA_AVAILABLE Logical and of corresponding request and mask bits. [3:3] read-only PR_DATA_AVAILABLE Logical and of corresponding request and mask bits. [4:4] read-only INSTR_OPC_ERROR Logical and of corresponding request and mask bits. [16:16] read-only INSTR_CC_ERROR Logical and of corresponding request and mask bits. [17:17] read-only BUS_ERROR Logical and of corresponding request and mask bits. [18:18] read-only TR_AP_DETECT_ERROR Logical and of corresponding request and mask bits. [19:19] read-only TR_RC_DETECT_ERROR Logical and of corresponding request and mask bits. [20:20] read-only INSTR_DEV_KEY_ERROR Logical and of corresponding request and mask bits. [21:21] read-only PR_LFSR_CTL0 Pseudo random LFSR control 0 0x200 32 read-write 0xD8959BC9 0xFFFFFFFF LFSR32 State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from '0'. The three PR_LFSR_CTL registers represents the state of a 32-bit, 31-bit and 29-bit LFSR. Individually, these LFSRs generate a pseudo random bit sequence that repeats itself after (2^32)-1, (2^31)-1 and (2^29)-1 bits. The numbers (2^32)-1, (2^31)-1 and (2^29)-1 are relatively prime (their greatest common denominator is '1'). The three bit sequence are combined (XOR'd) into a single bitstream to create a pseudo random bit sequence that repeats itself after ((2^32)-1) * ((2^31)-1) * ((2*29)-1) bits. The following polynomials are used: - 32-bit irreducible polynomial: x^32+x^30+x^26+x^25+1. - 31-bit irreducible polynomial: x^31+x^28+1. - 29-bit irreducible polynomial: x^29+x^27+1. [31:0] read-write PR_LFSR_CTL1 Pseudo random LFSR control 1 0x204 32 read-write 0x2BB911F8 0x7FFFFFFF LFSR31 State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0. [30:0] read-write PR_LFSR_CTL2 Pseudo random LFSR control 2 0x208 32 read-write 0x60C31B7 0x1FFFFFFF LFSR29 State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0. [28:0] read-write PR_MAX_CTL Pseudo random maximum control 0x20C 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA32 Maximum value of to be generated random number [31:0] read-write PR_CMD Pseudo random command 0x210 32 read-write 0x0 0x1 START Pseudo random command. On a generated number, HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1. [0:0] read-write PR_RESULT Pseudo random result 0x218 32 read-write 0x0 0xFFFFFFFF DATA32 Result of a pseudo random number generation operation. The resulting value DATA is in the range [0, PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated. Note that SW can write this field. This functionality can be used prevent information leakage. [31:0] read-write TR_CTL0 True random control 0 0x280 32 read-write 0x30000 0x31FFFFFF SAMPLE_CLOCK_DIV Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. 'clk_sys'. '0': sample clock is 'clk_sys'. '1': sample clock is 'clk_sys'/2. ... '255': sample clock is 'clk_sys'/256. [7:0] read-write RED_CLOCK_DIV Specifies the clock divider that is used to produce reduced bits. '0': 1 reduced bit is produced for each sample. '1': 1 reduced bit is produced for each 2 samples. ... '255': 1 reduced bit is produced for each 256 samples. The reduced bits are considered random bits and shifted into TR_RESULT0.DATA32. [15:8] read-write INIT_DELAY Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1, 255]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of '3'. Field encoding is as follows: '0': 1 sample is dropped. '1': 2 samples are dropped. ... '255': 256 samples are dropped. The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed. [23:16] read-write VON_NEUMANN_CORR Specifies if the 'von Neumann corrector' is disabled or enabled: '0': disabled. '1': enabled. The 'von Neumann corrector' post-processes the reduced bits to remove a '0' or '1' bias. The corrector operates on reduced bit pairs ('oldest bit, newest bit'): '00': no bit is produced. '01': '0' bit is produced (oldest bit). '10': '1' bit is produced (oldest bit). '11': no bit is produced. Note that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit). [24:24] read-write STOP_ON_AP_DETECT Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'): '0': Functionality is NOT stopped. '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). [28:28] read-write STOP_ON_RC_DETECT Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'): '0': Functionality is NOT stopped. '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). [29:29] read-write TR_CTL1 True random control 1 0x284 32 read-write 0x0 0x3F RO11_EN FW sets this field to '1' to enable the ring oscillator with 11 inverters. [0:0] read-write RO15_EN FW sets this field to '1' to enable the ring oscillator with 15 inverters. [1:1] read-write GARO15_EN FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters. [2:2] read-write GARO31_EN FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial. [3:3] read-write FIRO15_EN FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters. [4:4] read-write FIRO31_EN FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial. [5:5] read-write TR_CTL2 True random control 2 0x288 32 read-write 0x0 0x3F SIZE Bit size of generated random number in TR_RESULT. Legal range is in [0, 32]. [5:0] read-write TR_STATUS True random status 0x28C 32 read-only 0x0 0x1 INITIALIZED Reflects the state of the true random number generator: '0': Not initialized (TR_CTL0.INIT_DELAY has NOT passed). '1': Initialized (TR_CTL0.INIT_DELAY has passed). [0:0] read-only TR_CMD True random command 0x290 32 read-write 0x0 0x1 START True random command. On completion of the command, HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when: - A random number is generated in TR_RESULT. - All ring oscillators are off (per TR_CTL1). - A repetition count (RC) or adaptive proportion (AP) error is detected during the random number generation (INTR.TR_RC/AP_DETECT_ERROR). Note: On completion of the command, SW should check TR_CTL1 and INTR.TR_RC/AP_DETECT_ERROR to ensure that no unexpected error occurred during random number generation. [0:0] read-write TR_RESULT True random result 0x298 32 read-write 0x0 0xFFFFFFFF DATA32 Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated. Note that SW can write this field. This functionality can be used prevent information leakage. [31:0] read-write TR_GARO_CTL True random GARO control 0x2A0 32 read-write 0x0 0x7FFFFFFF POLYNOMIAL31 Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. [30:0] read-write TR_FIRO_CTL True random FIRO control 0x2A4 32 read-write 0x0 0x7FFFFFFF POLYNOMIAL31 Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. [30:0] read-write TR_MON_CTL True random monitor control 0x2C0 32 read-write 0x2 0x3 BITSTREAM_SEL Selection of the bitstream: '0': DAS bitstream. '1': RED bitstream. '2': TR bitstream. '3': Undefined. [1:0] read-write TR_MON_CMD True random monitor command 0x2C8 32 read-write 0x0 0x3 START_AP Adaptive proportion (AP) test enable: '0': Stopped. '1': Started. On a AP detection, HW sets this field to '0' and sets INTR.TR_AP_DETECT to '1. [0:0] read-write START_RC Repetition count (RC) test enable: '0': Disabled. '1': Enabled. On a RC detection, HW sets this field to '0' and sets INTR.TR_RC_DETECT to '1. [1:1] read-write TR_MON_RC_CTL True random monitor RC control 0x2D0 32 read-write 0xFF 0xFF CUTOFF_COUNT8 Cutoff count (legal range is [1, 255]): '0': Illegal. '1': 1 repetition. ... '255': 255 repetitions. [7:0] read-write TR_MON_RC_STATUS0 True random monitor RC status 0 0x2D8 32 read-only 0x0 0x1 BIT Current active bit value: '0': '0'. '1': '1'. This field is only valid when TR_MON_RC_STATUS1.REP_COUNT is NOT equal to '0'. [0:0] read-only TR_MON_RC_STATUS1 True random monitor RC status 1 0x2DC 32 read-only 0x0 0xFF REP_COUNT Number of repetitions of the current active bit counter: '0': 0 repetitions. ... '255': 255 repetitions. [7:0] read-only TR_MON_AP_CTL True random monitor AP control 0x2E0 32 read-write 0xFFFFFFFF 0xFFFFFFFF CUTOFF_COUNT16 Cutoff count (legal range is [1, 65535]). '0': Illegal. '1': 1 occurrence. ... '65535': 65535 occurrences. [15:0] read-write WINDOW_SIZE Window size (minus 1) : '0': 1 bit. ... '65535': 65536 bits. [31:16] read-write TR_MON_AP_STATUS0 True random monitor AP status 0 0x2E8 32 read-only 0x0 0x1 BIT Current active bit value: '0': '0'. '1': '1'. This field is only valid when TR_MON_AP_STATUS1.OCC_COUNT is NOT equal to '0'. [0:0] read-only TR_MON_AP_STATUS1 True random monitor AP status 1 0x2EC 32 read-only 0x0 0xFFFFFFFF OCC_COUNT Number of occurrences of the current active bit counter: '0': 0 occurrences ... '65535': 65535 occurrences [15:0] read-only WINDOW_INDEX Counter to keep track of the current index in the window (counts from '0' to TR_MON_AP_CTL.WINDOW_SIZE to '0'). [31:16] read-only STATUS Status 0x1004 32 read-only 0x0 0x80000000 BUSY Reflects the state of the IP: '0': Idle/no busy. '1': Busy: - Instruction is pending in the instruction FIFO. - Instruction is busy in a IP component (e.g. SHA1, SHA2, SHA3, DES, TDES, AES, CHACHA, ...). - Store FIFO is busy. - TR or PR command is busy. [31:31] read-only INSTR_FF_CTL Instruction FIFO control 0x1040 32 read-write 0x20000 0x30007 EVENT_LEVEL Event level. When the number of entries in the instruction FIFO is less than the amount of this field, an event is generated: - 'event' = INSTR_FF_STATUS.USED < EVENT_LEVEL. [2:0] read-write CLEAR When '1', the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. HW sets this field to '1' on when a INSTR_OPC_ERROR, INSTR_CC_ERROR or BUS_ERROR interrupt cause is activated. [16:16] read-write BLOCK This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register): '0': The write is ignored/dropped and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1'. '1': The write is blocked, resulting in AHB-Lite wait states and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1' (this cause may be masked out). The instruction is written to the FIFO as soon as a FIFO entry becomes available. The maximum time is roughly the time of the execution of the slowest/longest instruction. Note that this setting may 'lock up' /stall the CPU. When the CPU is 'locked up'/stalled it can not respond to any system interrupts. As a result, the interrupt latency is increased. Note that this may not be an issue if the associated CPU is only performing cryptography functionality, e.g. the CM0+ during boot time. [17:17] read-write INSTR_FF_STATUS Instruction FIFO status 0x1044 32 read-only 0x0 0x1000F USED Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8. [3:0] read-only EVENT Instruction FIFO event. [16:16] read-only INSTR_FF_WR Instruction FIFO write 0x1048 32 write-only 0x0 0xFFFFFFFF DATA32 Instruction or instruction operand data that is written to the instruction FIFO. [31:0] write-only LOAD0_FF_STATUS Load 0 FIFO status 0x10C0 32 read-only 0x0 0x8000001F USED5 Number of Bytes in the FIFO. The value of this field is in the range [0, 19]. [4:0] read-only BUSY Reflects the state of the FIFO: '0': FIFO load engine is idle and a new FIFO instruction can be accepted. '1': FIFO load engine is busy and NO new FIFO instruction can be accepted. [31:31] read-only LOAD1_FF_STATUS Load 1 FIFO status 0x10D0 32 read-only 0x0 0x8000001F USED5 See LOAD1_FF_STATUS.USED. [4:0] read-only BUSY See LOAD1_FF_STATUS.BUSY. [31:31] read-only STORE_FF_STATUS Store FIFO status 0x10F0 32 read-only 0x0 0x8000001F USED5 Number of Bytes in the FIFO. The value of this field is in the range [0, 16]. [4:0] read-only BUSY Reflects the state of the FIFO: '0': FIFO store engine is idle and a new FIFO instruction can be accepted (USED is '0'). '1': FIFO store engine is busy and NO new FIFO instruction can be accepted. [31:31] read-only AES_CTL AES control 0x1100 32 read-write 0x0 0x3 KEY_SIZE AES key size: '0': 128-bit key, 10 rounds AES (inverse) cipher operation. '1': 192-bit key, 12 rounds AES (inverse) cipher operation. '2': 256-bit key, 14 rounds AES (inverse) cipher operation. '3': Undefined [1:0] read-write AES128 N/A 0 AES192 N/A 1 AES256 N/A 2 RESULT Result 0x1180 32 read-write 0x0 0xFFFFFFFF DATA BLOCK_CMP operation (DATA[0]): '0': source 0 equals source 1. '1': source 0 does NOT equal source 1. CRC operation (DATA[31:0]). State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. Note that SW can write this field. This functionality can be used prevent information leakage. [31:0] read-write CRC_CTL CRC control 0x1400 32 read-write 0x0 0x101 DATA_REVERSE Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): '0': Most significant bit (bit 1) first. '1': Least significant bit (bit 0) first. [0:0] read-write REM_REVERSE Specifies whether the remainder is bit reversed (reversal is performed after XORing): '0': No. '1': Yes. [8:8] read-write CRC_DATA_CTL CRC data control 0x1410 32 read-write 0x0 0xFF DATA_XOR Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. [7:0] read-write CRC_POL_CTL CRC polynomial control 0x1420 32 read-write 0x0 0xFFFFFFFF POLYNOMIAL CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). [31:0] read-write CRC_REM_CTL CRC remainder control 0x1440 32 read-write 0x0 0xFFFFFFFF REM_XOR Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. [31:0] read-write CRC_REM_RESULT CRC remainder result 0x1448 32 read-only 0x0 0xFFFFFFFF REM Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: '0': the more significant bits (bit 31 and down) contain the remainder. '1': the less significant bits (bit 0 and up) contain the remainder. Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_REM_CTL0.REM_REVERSE and CRC_REM_CTL1.REM_XOR. [31:0] read-only VU_CTL0 Vector unit control 0 0x1480 32 read-write 0x0 0x1 ALWAYS_EXECUTE Specifies if a conditional instruction is executed or not, when its condition code evaluates to false/'0'. '0': The instruction is NOT executed. As a result, the instruction may be handled faster than when it is executed. '1': The instruction is executed, but the execution result (including status field information) is not reflected in the IP. The instruction is handled just as fast as when it is executed. Note: a conditional instruction with a condition code that evaluates to false/'0' does not affect the architectural state: VU_STATUS fields, memory or register-file data. Note: Always execution is useful to prevent/complicate differential timing and differential power attacks. [0:0] read-write VU_CTL1 Vector unit control 1 0x1484 32 read-write 0x0 0xFFFFFF00 ADDR24 Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8], VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2], a vector operand memory address VU_OPERAND_ADDR[31:0] is calculated as follows: - VU_OPERAND_ADDR[31:15] = ADDR[31:15] - VU_OPERAND_ADDR[14:8] = (ADDR[14:8] & MASK[14:8]) | (offset[14:8] & ~MASK[14:8]) - VU_OPERAND_ADDR[7:2] = offset[7:2] - VU_OPERAND_ADDR[1:0] = 0 (always word aligned) The vector unit operand memory region uses either the IP's memory buffer or system memory. For best performance, the IP's memory buffer should be used and ADDR should be set to MEM_BUFF and MASK should specify the IP memory buffer size. If a vector operand memory address is mapped on a memory hole, read accesses return a '0' and write accesses are ignored. [31:8] read-write VU_CTL2 Vector unit control 2 0x1488 32 read-write 0x7F00 0x7F00 MASK Specifies the size of the vector operand memory region. Legal values: '0b0000000': 32 KB memory region (VU_VTL1.ADDR[14:8] ignored). '0b1000000': 16 KB memory region (VU_VTL1.ADDR[13:8] ignored). '0b1100000': 8 KB memory region (VU_VTL1.ADDR[12:8] ignored). '0b1110000': 4 KB memory region (VU_VTL1.ADDR[11:8] ignored). '0b1111000': 2 KB memory region (VU_VTL1.ADDR[10:8] ignored). '0b1111100': 1 KB memory region (VU_VTL1.ADDR[9:8] ignored). '0b1111110': 512 B memory region (VU_VTL1.ADDR[8] ignored). '0b1111111': 256 B memory region. Note: the default specifies a 256 B memory region. [14:8] read-write VU_STATUS Vector unit status 0x1490 32 read-only 0x0 0xF CARRY STATUS CARRY field. [0:0] read-only EVEN STATUS EVEN field. [1:1] read-only ZERO STATUS ZERO field. [2:2] read-only ONE STATUS ONE field. [3:3] read-only 16 4 VU_RF_DATA[%s] Vector unit register-file 0x14C0 32 read-only 0x0 0xFFFFFFFF DATA32 Vector unit register-file data. A register-file register has the following layout: DATA[28:16]: data (typically used as a word offset in vector unit operand memory). DATA[12:0]: bit size minus 1. [31:0] read-only DEV_KEY_ADDR0_CTL Device key address 0 control 0x2000 32 read-write 0x0 0x80000000 VALID Specifies if the address in the associated DEV_KEY_ADDR0 is valid: '0': Address not valid; i.e. no device key specified. '1': Address valid; i.e. device key specified. Note: A LOAD_DEV_KEY instruction requires that the device key's valid field is '1'. [31:31] read-write DEV_KEY_ADDR0 Device key address 0 0x2004 32 read-write 0x0 0xFFFFFFFF ADDR32 Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5. [31:0] read-write DEV_KEY_ADDR1_CTL Device key address 1 control 0x2020 32 read-write 0x0 0x80000000 VALID See DEV_KEY_ADDR0_CTL. [31:31] read-write DEV_KEY_ADDR1 Device key address 1 control 0x2024 32 read-write 0x0 0xFFFFFFFF ADDR32 See DEV_KEY_ADDR0. [31:0] read-write DEV_KEY_STATUS Device key status 0x2080 32 read-only 0x0 0x1 LOADED Specifies if a device key is present in the IP register buffer blocks 4 and 5. HW sets this field to '1' on successful completion of a LOAD_DEV_KEY instruction. HW clears this field to '0' when a CLEAR instruction is executed (the CLEAR instruction also sets the IP register buffer to '0'). [0:0] read-only DEV_KEY_CTL0 Device key control 0 0x2100 32 read-write 0x0 0x1 ALLOWED Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory: '0': Not allowed. '1': Allowed. Note: For successful completion of a LOAD_DEV_KEY instruction, both the associated DEV_KEY_ADDR_CTL.VALID and DEV_KEY_CTL.ALLOWED fields must be '1'. On successful instruction completion, DEV_KEY_STATUS.LOADED is set to '1'. On unsuccessful completion, the instruction FIFO is cleared and the IP is locked; an Active reset or an IP reset (CTL.ENABLED), which reinitializes the IP, is required. Note: A LOAD_DEV_KEY loads the device key from memory with protection context '0'. [0:0] read-write DEV_KEY_CTL1 Device key control 1 0x2120 32 read-write 0x0 0x1 ALLOWED See DEV_KEY_CTL0. [0:0] read-write CPUSS CPU subsystem (CPUSS) 0x40200000 0 65536 registers NvicMux0 CPU User Interrupt #0 0 NvicMux1 CPU User Interrupt #1 1 NvicMux2 CPU User Interrupt #2 2 NvicMux3 CPU User Interrupt #3 3 NvicMux4 CPU User Interrupt #4 4 NvicMux5 CPU User Interrupt #5 5 NvicMux6 CPU User Interrupt #6 6 NvicMux7 CPU User Interrupt #7 7 Internal0 Internal SW Interrupt #0 8 Internal1 Internal SW Interrupt #1 9 Internal2 Internal SW Interrupt #2 10 Internal3 Internal SW Interrupt #3 11 Internal4 Internal SW Interrupt #4 12 Internal5 Internal SW Interrupt #5 13 Internal6 Internal SW Interrupt #6 14 Internal7 Internal SW Interrupt #7 15 IDENTITY Identity 0x0 32 read-only 0x0 0x0 P This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. [0:0] read-only NS This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. [1:1] read-only PC This field specifies the protection context of the transfer that reads the register. [7:4] read-only MS This field specifies the bus master identifier of the transfer that reads the register. [11:8] read-only CM7_0_STATUS CM7 0 status 0x4 32 read-only 0x13 0x1E13 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only PWR_DONE After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req [4:4] read-only TCMC_CM7_1_MS Outstanding transactions from CM7 1. '0': There are no outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from CM7 1. '1': There are outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from CM7 1. Do not switch the CM7 power off. [9:9] read-only TCMC_EXT_MS_2_TO_0 Outstanding transactions from external AXI masters 2 to 0. '0': There are no outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from external AXI masters 2 to 0. '1': There are outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from external AXI masters 2 to 0. Do not switch the CM7 power off. [10:10] read-only TCMC_EXT_MS_3 Outstanding transactions from external AXI master 3. '0': There are no outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from external AXI master 3. '1': There are outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from external AXI master 3. Do not switch the CM7 power off. [11:11] read-only TCMC_AHB_MS Ongoing AHB transaction. '0': There is no ongoing transaction to the CM7 I/D-TCM slave port (AHBS) from an AHB master. '1': There is an ongoing transaction to the CM7 I/D-TCM slave port (AHBS) from an AHB master. Do not switch the CM7 power off. [12:12] read-only FAST_0_CLOCK_CTL Fast 0 clock control 0x8 32 read-write 0x0 0xFFF8 FRAC_DIV Fractional division by (FRAC_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf<x>' cycle longer than other clock periods. [7:3] read-write INT_DIV Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). [15:8] read-write CM7_0_CTL CM7 0 control 0xC 32 read-write 0x1F 0x9FFF0F1F PPB_LOCK Write disable for specific CPU registers: Bit 0: ITCMR register. '0': enabled; '1': disabled. Bit 1: DTCMR register. '0': enabled; '1': disabled. Bit 2: AHBPCR register. '0': enabled; '1': disabled. Bit 3: VTOR register. '0': enabled; '1': disabled. [3:0] read-write CPU_WAIT When this signal is '1' out of reset, it forces the CPU into a quiescent state that delays its boot-up sequence and instruction execution until this signal is driven '0'. This allows the TCMs to be loaded by the system before the CPU performs any TCM accesses. The CPU AHBS interface functions while CPU_WAIT is '1' and services transactions initiated by the system (e.g. DMA controller) to load the TCMs. [4:4] read-write INIT_TCM_EN TCM enable initialization after reset: Bit 0: ITCM. '0': disabled; '1': enabled. Bit 1: DTCM. '0': disabled; '1': enabled. [9:8] read-write INIT_RMW_EN TCM read-modify-write enable initialization after reset: Bit 0: ITCM. '0': disabled; '1': enabled. Bit 1: DTCM. '0': disabled; '1': enabled. Note: When TCM ECC is enabled, the read-modify-write functionality should be enabled. This prevents partial (sub-word) writes to the TCM. [11:10] read-write ITCM_ECC_EN ITCM ECC enable: '0': Disabled. '1': Enabled. [16:16] read-write ITCM_ECC_INJ_EN ITCM ECC error injection enable: '0': Disabled. '1': Enabled. [17:17] read-write ITCM_READ_WS ITCM read wait states (writes have no wait states). '0': 0 wait states. '1': 1 wait state. [18:18] read-write ITCM_ECC_CHECK_DIS Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0. [19:19] read-write DTCM_ECC_EN DTCM ECC enable: '0': Disabled. '1': Enabled. [20:20] read-write DTCM_ECC_INJ_EN DTCM ECC error injection enable: '0': Disabled. '1': Enabled. [21:21] read-write DTCM_READ_WS DTCM read wait states (writes have no wait states). '0': 0 wait states. '1': 1 wait state. [22:22] read-write TCMC_EN CM7 TCMC access control: '0': Disable access to the CM7 I/D-TCM slave port (AHBS). Access attempts will get a bus error response. '1': Enable access to the CM7 I/D-TCM slave port (AHBS). Before switching the CM7 power off, set this field to 0, and confirm that there are no outstanding AXI transactions and no ongoing AHB transactions to the CM7 TCMs, by checking that bits TCMC_* in CM7_x_STATUS are '0'. [23:23] read-write IOC_MASK CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. [24:24] read-write DZC_MASK CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [25:25] read-write OFC_MASK CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [26:26] read-write UFC_MASK CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [27:27] read-write IXC_MASK CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. [28:28] read-write IDC_MASK CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. [31:31] read-write 16 4 CM7_0_INT_STATUS[%s] CM7 0 interrupt status 0x100 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM7_0 activated system interrupt index for CPU interrupt. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM7_0_VECTOR_TABLE_BASE CM7 0 vector table base 0x200 32 read-write 0x1000000 0xFFFFFF80 ADDR25 The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset). This is the location of the system ROM memory. The system ROM is mirrored at 0x0000:0000. This is required for the CM0+ boot process (the CM0+ VTOR and reset exception handler address is at fixed address 0x0000:00000 after reset). The system ROM requires mirroring as the CM7 CPUs' ITCMs are located at base address 0x0000:0000 and effectively cut a hole in the system ROM mirror address space (but the 0x0100:0000 address space is not affected). [31:7] read-write 4 4 CM7_0_NMI_CTL[%s] CM7 0 NMI control 0x240 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [9:0] read-write UDB_PWR_CTL UDB power control 0x300 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Set Power mode for UDBs [1:0] read-write OFF See CM7_0_PWR_CTL 0 RESET See CM7_0_PWR_CTL 1 RETAINED See CM7_0_PWR_CTL 2 ENABLED See CM7_0_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only UDB_PWR_DELAY_CTL UDB power control 0x304 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write TRC_DBG_CLOCK_CTL Trace and debug clock control 0x320 32 read-write 0x200 0xFF00 INT_DIV Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write CM7_1_STATUS CM7 1status 0x404 32 read-only 0x13 0x1D13 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only PWR_DONE After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req [4:4] read-only TCMC_CM7_0_MS Outstanding transactions from CM7 0. '0': There are no outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from CM7 0. '1': There are outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from CM7 0. Do not switch the CM7 power off. [8:8] read-only TCMC_EXT_MS_2_TO_0 Refer CM7_0_STATUS description. [10:10] read-only TCMC_EXT_MS_3 Refer CM7_0_STATUS description. [11:11] read-only TCMC_AHB_MS Refer CM7_0_STATUS description. [12:12] read-only FAST_1_CLOCK_CTL Fast 1 clock control 0x408 32 read-write 0x0 0xFFF8 FRAC_DIV Refer FAST_0_CLOCK_CTL description. [7:3] read-write INT_DIV Refer FAST_0_CLOCK_CTL description. [15:8] read-write CM7_1_CTL CM7 1 control 0x40C 32 read-write 0x1F 0x9FFF0F1F PPB_LOCK Refer CM7_0_CTL description. [3:0] read-write CPU_WAIT Refer CM7_0_CTL description. [4:4] read-write INIT_TCM_EN Refer CM7_0_CTL description. [9:8] read-write INIT_RMW_EN Refer CM7_0_CTL description. [11:10] read-write ITCM_ECC_EN Refer CM7_0_CTL description. [16:16] read-write ITCM_ECC_INJ_EN Refer CM7_0_CTL description. [17:17] read-write ITCM_READ_WS Refer CM7_0_CTL description. [18:18] read-write ITCM_ECC_CHECK_DIS Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0. [19:19] read-write DTCM_ECC_EN Refer CM7_0_CTL description. [20:20] read-write DTCM_ECC_INJ_EN Refer CM7_0_CTL description. [21:21] read-write DTCM_READ_WS Refer CM7_0_CTL description. [22:22] read-write TCMC_EN Refer CM7_0_CTL description. [23:23] read-write IOC_MASK Refer CM7_0_CTL description. [24:24] read-write DZC_MASK Refer CM7_0_CTL description. [25:25] read-write OFC_MASK Refer CM7_0_CTL description. [26:26] read-write UFC_MASK Refer CM7_0_CTL description. [27:27] read-write IXC_MASK Refer CM7_0_CTL description. [28:28] read-write IDC_MASK Refer CM7_0_CTL description. [31:31] read-write 16 4 CM7_1_INT_STATUS[%s] CM7 1 interrupt status 0x500 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM7_1 activated system interrupt index for CPU interrupt 0. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM7_1_VECTOR_TABLE_BASE CM7 1 vector table base 0x600 32 read-write 0x1000000 0xFFFFFF80 ADDR25 The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset). This is the location of the system ROM memory. The system ROM is mirrored at 0x0000:0000. This is required for the CM0+ boot process (the CM0+ VTOR and reset exception handler address is at fixed address 0x0000:00000 after reset). The system ROM requires mirroring as the CM7 CPUs' ITCMs are located at base address 0x0000:0000 and effectively cut a hole in the system ROM mirror address space (but the 0x0100:0000 address space is not affected). [31:7] read-write 4 4 CM7_1_NMI_CTL[%s] CM7 1 NMI control 0x640 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX Refer CM7_0_NMI_CTL description. [9:0] read-write CM0_CTL CM0+ control 0x1000 32 read-write 0xFA050002 0xFFFF0003 SLV_STALL Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. [0:0] read-write ENABLED Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM7 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). [1:1] read-write VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM0_STATUS CM0+ status 0x1004 32 read-only 0x0 0x3 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only SLOW_CLOCK_CTL Slow clock control 0x1008 32 read-write 0x0 0xFF00 INT_DIV Specifies the slow clock divider (from the memory/AXI clock 'clk_mem' to the slow clock 'clk_slow'). Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write PERI_CLOCK_CTL Peripheral interconnect clock control 0x100C 32 read-write 0x0 0xFF00 INT_DIV Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write MEM_CLOCK_CTL Memory clock control 0x1010 32 read-write 0x0 0xFF00 INT_DIV Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write CM0_INT0_STATUS CM0+ interrupt 0 status 0x1100 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 0. Multiple system interrupts can be mapped on the same CPU interrupt.The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. [9:0] read-only SYSTEM_INT_VALID Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. [31:31] read-only CM0_INT1_STATUS CM0+ interrupt 1 status 0x1104 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT2_STATUS CM0+ interrupt 2 status 0x1108 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT3_STATUS CM0+ interrupt 3 status 0x110C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT4_STATUS CM0+ interrupt 4 status 0x1110 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT5_STATUS CM0+ interrupt 5 status 0x1114 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT6_STATUS CM0+ interrupt 6 status 0x1118 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT7_STATUS CM0+ interrupt 7 status 0x111C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_VECTOR_TABLE_BASE CM0+ vector table base 0x1120 32 read-write 0x0 0xFFFFFF00 ADDR24 The default CM0+ vector table base address is 0x0000:0000 (CM0+ VTOR and reset exception handler address after reset). This is the location of the mirror system ROM memory. This register is provided for SW purposes. It 'survives' a CM0+ warm reset cycle (CM0_CTL.ENABLED). Note: the use of the mirror system ROM memory can be disabled using the protection infrastructure (SMPU). [31:8] read-write 4 4 CM0_NMI_CTL[%s] CM0+ NMI control 0x1140 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [9:0] read-write CM7_0_PWR_CTL CM7 0 power control 0x1200 32 read-write 0xFA050000 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF Switch CM7_0 off Power off, clock off, isolate, reset and no retain. 0 RESET Reset CM7_0 Clock off, no isolated, no retain and reset. Note: The CM7_0 CPU has a AIRCR.SYSRESETREQ register field that allows the CM7_0 to reset the complete device (RESET only resets the CM7_0), resulting in a warm boot. 1 RETAINED Put CM7_0 in Retained mode This can only become effective if CM7_0 is in SleepDeep mode. Check PWR_DONE flag to see if CM7_0 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain. 2 ENABLED Switch CM7_0 on. Power on, clock on, no isolate, no reset and no retain. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM7_0_PWR_DELAY_CTL CM7 0 power delay control 0x1204 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write CM7_1_PWR_CTL CM7 1 power control 0x1210 32 read-write 0xFA050000 0xFFFF0003 PWR_MODE Refer CM7_0_PWR_CTL description. [1:0] read-write OFF Refer CM7_0_PWR_CTL description. 0 RESET Refer CM7_0_PWR_CTL description. 1 RETAINED Refer CM7_0_PWR_CTL description. 2 ENABLED Refer CM7_0_PWR_CTL description. 3 VECTKEYSTAT Refer CM7_0_PWR_CTL description. [31:16] read-only CM7_1_PWR_DELAY_CTL CM7 1 power delay control 0x1214 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write RAM0_CTL0 RAM 0 control 0x1300 32 read-write 0x30001 0xF0303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow') intefrace. The number of wait states is expressed in 'clk_mem' clock domain cycles. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast_0/1') interface. The number of wait states is expressed in 'clk_mem' clock domain cycles. [9:8] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_AUTO_CORRECT HW ECC autocorrect functionality: '0': Disabled. '1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. [17:17] read-write ECC_INJ_EN Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM, the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0. Note: Parity injection invalidates the write buffer for this word address. If only a part of 64-bit data is written and consistency should be maintained, RAMC#_STATUS WB_EMPTY=1 should be checked before. [18:18] read-write ECC_CHECK_DIS Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0. [19:19] read-write RAM0_STATUS RAM 0 status 0x1304 32 read-only 0x1 0x1 WB_EMPTY Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. '0': Write buffer NOT empty. '1': Write buffer empty. Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). [0:0] read-only 16 4 RAM0_PWR_MACRO_CTL[%s] RAM 0 power control 0x1340 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. 2 ENABLED Enable SRAM for regular operation. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only RAM1_CTL0 RAM 1 control 0x1380 32 read-write 0x30001 0xF0303 SLOW_WS Refer RAM0_CTL0 descriotion. [1:0] read-write FAST_WS Refer RAM0_CTL0 descriotion. [9:8] read-write ECC_EN Refer RAM0_CTL0 descriotion. [16:16] read-write ECC_AUTO_CORRECT Refer RAM0_CTL0 descriotion. [17:17] read-write ECC_INJ_EN Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM, the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0. Note: Parity injection invalidates the write buffer for this word address. If only a part of 64-bit data is written and consistency should be maintained, RAMC#_STATUS WB_EMPTY=1 should be checked before. [18:18] read-write ECC_CHECK_DIS Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0. [19:19] read-write RAM1_STATUS RAM 1 status 0x1384 32 read-only 0x1 0x1 WB_EMPTY Refer RAM0_STATUS description. [0:0] read-only RAM1_PWR_CTL RAM 1 power control 0x1388 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF Refer RAM0_PWR_MACRO_CTL description. 0 RSVD Undefined. 1 RETAINED Refer RAM0_PWR_MACRO_CTL description. 2 ENABLED Refer RAM0_PWR_MACRO_CTL description. 3 VECTKEYSTAT Refer RAM0_PWR_MACRO_CTL description. [31:16] read-only RAM2_CTL0 RAM 2 control 0x13A0 32 read-write 0x30001 0xF0303 SLOW_WS Refer RAM0_CTL0 descriotion. [1:0] read-write FAST_WS Refer RAM0_CTL0 descriotion. [9:8] read-write ECC_EN Refer RAM0_CTL0 descriotion. [16:16] read-write ECC_AUTO_CORRECT Refer RAM0_CTL0 descriotion. [17:17] read-write ECC_INJ_EN Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM, the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0. Note: Parity injection invalidates the write buffer for this word address. If only a part of 64-bit data is written and consistency should be maintained, RAMC#_STATUS WB_EMPTY=1 should be checked before. [18:18] read-write ECC_CHECK_DIS Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0. [19:19] read-write RAM2_STATUS RAM 2 status 0x13A4 32 read-only 0x1 0x1 WB_EMPTY Refer RAM0_STATUS description. [0:0] read-only RAM2_PWR_CTL RAM 2 power control 0x13A8 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF Refer RAM0_PWR_MACRO_CTL description. 0 RSVD Undefined. 1 RETAINED Refer RAM0_PWR_MACRO_CTL description. 2 ENABLED Refer RAM0_PWR_MACRO_CTL description. 3 VECTKEYSTAT Refer RAM0_PWR_MACRO_CTL description. [31:16] read-only RAM_PWR_DELAY_CTL Power up delay used for all SRAM power domains 0x13C0 32 read-write 0x96 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write ROM_CTL ROM control 0x13C4 32 read-write 0x1 0x303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_mem' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_mem' clock domain frequency determines this field's value such that the timing paths minimum duration is met. ROM_CTL.SLOW_WS = '0' when clk_mem <=100 MHz. ROM_CTL.SLOW_WS = '1' when 100MHz < clk_mem <=200MHz. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_mem' clock domain cycles. ROM_CTL.FAST_WS = '0' when clk_mem <= 200MHz. [9:8] read-write ECC_CTL ECC control 0x13C8 32 read-write 0x0 0xFFFFFFFF WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2/ITCM/DTCM ECC_INJ_EN bit is '1', the parity (PARITY) is injected. This field needs to be written with the offset address within the memory, divided by the ECC word width in bytes (for RAM0/RAM1/RAM2/ITCM this is 8, for DTCM this is 4). For example, if the RAM0 start address is 0x2800000, and an error is to be injected to address 0x28000080, then this field needs to configured to 0x000010. [23:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. For the DTCM which has only 7 parity bits, PARITY[6:0] is used as ECC parity. [31:24] read-write PRODUCT_ID Product identifier and version (same as CoreSight RomTables) 0x1400 32 read-only 0x0 0xFFF FAMILY_ID Family ID. Common ID for a product family. [11:0] read-only MAJOR_REV Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) [19:16] read-only MINOR_REV Minir Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) [23:20] read-only DP_STATUS Debug port status 0x1410 32 read-only 0x4 0x7 SWJ_CONNECTED Specifies if the SWJ debug port is connected; i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active. [0:0] read-only SWJ_DEBUG_EN Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled. [1:1] read-only SWJ_JTAG_SEL Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected. [2:2] read-only AP_CTL Access port control 0x1414 32 read-write 0x0 0x70007 CM0_ENABLE Enables the CM0 AP interface: '0': Disabled. '1': Enabled. [0:0] read-write CM7_ENABLE Enables the CM7_0 and CM7_1 AP interface: '0': Disabled. '1': Enabled. [1:1] read-write SYS_ENABLE Enables the system AP interface: '0': Disabled. '1': Enabled. [2:2] read-write CM0_DISABLE Disables the CM0 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. [16:16] read-write CM7_DISABLE Disables the CM7_0 and CM7_1 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM7_DISABLE is '0' and CM7_ENABLE is '1'. [17:17] read-write SYS_DISABLE Disables the system AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. [18:18] read-write BUFF_CTL Buffer control 0x1500 32 read-write 0x1 0x1 WRITE_BUFF Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. [0:0] read-write SYSTICK_CTL SysTick timer control 0x1600 32 read-write 0x40000147 0xC3FFFFFF TENMS Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. [23:0] read-write CLOCK_SOURCE Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. [25:24] read-write SKEW Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise. [30:30] read-write NOREF Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. [31:31] read-write MBIST_STAT Memory BIST status 0x1704 32 read-only 0x0 0x3 SFP_READY Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. [0:0] read-only SFP_FAIL Report status of the BIST run, only valid if SFP_READY=1 [1:1] read-only CAL_SUP_SET Calibration support set and read 0x1800 32 read-write 0x0 0xFFFFFFFF DATA Read without side effect, write 1 to set [31:0] read-write CAL_SUP_CLR Calibration support clear and reset 0x1804 32 read-write 0x0 0xFFFFFFFF DATA Read side effect: when read all bits are cleared, write 1 to clear a specific bit Note: no exception for the debug host, it also causes the read side effect [31:0] read-write CM0_PC_CTL CM0+ protection context control 0x2000 32 read-write 0x0 0xF VALID Valid fields for the protection context handler CM0_PCi_HANDLER registers: Bit 0: Valid field for CM0_PC0_HANDLER. Bit 1: Valid field for CM0_PC1_HANDLER. Bit 2: Valid field for CM0_PC2_HANDLER. Bit 3: Valid field for CM0_PC3_HANDLER. [3:0] read-write CM0_PC0_HANDLER CM0+ protection context 0 handler 0x2040 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. [31:0] read-write CM0_PC1_HANDLER CM0+ protection context 1 handler 0x2044 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 1 handler. [31:0] read-write CM0_PC2_HANDLER CM0+ protection context 2 handler 0x2048 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 2 handler. [31:0] read-write CM0_PC3_HANDLER CM0+ protection context 3 handler 0x204C 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 3 handler. [31:0] read-write PROTECTION Protection status 0x20C4 32 read-write 0x0 0x7 STATE Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transistions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field. [2:0] read-write UNKNOWN N/A 0 VIRGIN N/A 1 NORMAL N/A 2 SECURE N/A 3 DEAD N/A 4 TRIM_ROM_CTL ROM trim control 0x2100 32 read-write 0x0 0xFFFFFFFF TRIM N/A [31:0] read-write TRIM_RAM_CTL RAM trim control for less than 100MHz SRAMs 0x2104 32 read-write 0x0 0xFFFFFFFF TRIM N/A [31:0] read-write TRIM_RAM200_CTL RAM trim control for 100MHz - 200MHz SRAMs 0x2108 32 read-write 0x0 0xFFFFFFFF TRIM See TRIM_RAM_CTL for description. System SRAM memories (SRAM0,1,2) are connected to this register. System SRAM0 uses bias control power switch,so bits [7:5] of this register controls the bias pins of the SRAM0 power switch. [31:0] read-write TRIM_RAM350_CTL RAM trim control for more than 200MHz SRAMs 0x210C 32 read-write 0x0 0xFFFFFFFF TRIM See TRIM_RAM_CTL for description. CM7 Cache and TCM memories are connected to this register. All CM7 cache and TCM SRAM macros are controlled using bias control power switches, so bits [7:5] of this register controls the bias pins of the CM7 cache and TCM SRAM power switches. [31:0] read-write 1023 4 CM0_SYSTEM_INT_CTL[%s] CM0+ system interrupt control 0x8000 32 read-write 0x0 0x80000000 CM0_CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. [2:0] read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. [31:31] read-write 1023 4 CM7_0_SYSTEM_INT_CTL[%s] CM7 0 system interrupt control 0xA000 32 read-write 0x0 0x80000000 CPU_INT_IDX CPU interrupt index (legal range [0, 15]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. [3:0] read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. [31:31] read-write 1023 4 CM7_1_SYSTEM_INT_CTL[%s] CM7 1 system interrupt control 0xC000 32 read-write 0x0 0x80000000 CPU_INT_IDX Refer CM7_0_SYSTEM_INT_CTL description. [3:0] read-write CPU_INT_VALID Refer CM7_0_SYSTEM_INT_CTL description. [31:31] read-write FAULT Fault structures 0x40210000 0 65536 registers 4 256 STRUCT[%s] Fault structure 0x00000000 CTL Fault control 0x0 32 read-write 0x0 0x7 TR_EN Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). [0:0] read-write OUT_EN IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. [1:1] read-write RESET_REQ_EN Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. [2:2] read-write STATUS Fault status 0xC 32 read-write 0x0 0x80000000 IDX The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. The description of the encoded meaning of this field is comes from the Fault assignment in the Product Spreadsheet. [6:0] read-write VALID Valid indication: '0': Invalid. '1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: - STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) [31:31] read-write 4 4 DATA[%s] Fault data 0x10 32 read-write 0x0 0x0 DATA Captured fault source data. Note: the DATA registers can only be written when STATUS.VALID is '0'. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. [31:0] read-write PENDING0 Fault pending 0 0x40 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. Bit 4: DMA controller MPU. ... Bit 15: DAP MPU. Bit 16: CM4 system bus MPU. Bit 17: CM4 code bus MPU (for non FLASH controller accesses). Bit 18: CM4 code bus MPU (for FLASH controller accesses). [31:0] read-only PENDING1 Fault pending 1 0x44 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 16 - 31: See STATUS register. [31:0] read-only PENDING2 Fault pending 2 0x48 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0 - 31: See STATUS register. [31:0] read-only MASK0 Fault mask 0 0x50 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 31 to 0. [31:0] read-write MASK1 Fault mask 1 0x54 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 63 to 32. [31:0] read-write MASK2 Fault mask 2 0x58 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 95 to 64. [31:0] read-write INTR Interrupt 0xC0 32 read-write 0x0 0x1 FAULT This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source data. SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). [0:0] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x1 FAULT SW writes a '1' to this field to set the corresponding field in the INTR register. [0:0] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x1 FAULT Mask bit for corresponding field in the INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x1 FAULT Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only IPC IPC 0x40220000 0 65536 registers 8 32 STRUCT[%s] IPC structure 0x00000000 ACQUIRE IPC acquire 0x0 32 read-only 0x0 0x80000000 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock. [0:0] read-only NS Secure/non-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only SUCCESS Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). [31:31] read-only RELEASE IPC release 0x4 32 write-only 0x0 0xFFFF INTR_RELEASE Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only NOTIFY IPC notification 0x8 32 write-only 0x0 0xFFFF INTR_NOTIFY This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only DATA0 IPC data 0 0xC 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write DATA1 IPC data 1 0x10 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write LOCK_STATUS IPC lock status 0x1C 32 read-only 0x0 0x80000000 P This field specifies the user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS This field specifies the secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only ACQUIRED Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. [31:31] read-only 8 32 INTR_STRUCT[%s] IPC interrupt structure 0x00001000 INTR Interrupt 0x0 32 read-write 0x0 0xFFFFFFFF RELEASE These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [15:0] read-write NOTIFY These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [31:16] read-write INTR_SET Interrupt set 0x4 32 read-write 0x0 0xFFFFFFFF RELEASE SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write NOTIFY SW writes a '1' to this field to set the corresponding field in the INTR register. [31:16] read-write INTR_MASK Interrupt mask 0x8 32 read-write 0x0 0xFFFFFFFF RELEASE Mask bit for corresponding field in the INTR register. [15:0] read-write NOTIFY Mask bit for corresponding field in the INTR register. [31:16] read-write INTR_MASKED Interrupt masked 0xC 32 read-only 0x0 0xFFFFFFFF RELEASE Logical and of corresponding request and mask bits. [15:0] read-only NOTIFY Logical and of corresponding INTR and INTR_MASK fields. [31:16] read-only PROT Protection 0x40230000 0 65536 registers SMPU SMPU 0x00000000 MS0_CTL Master 0 protection context control 0x0 32 read-write 0x303 0xFFFF0303 P Privileged setting ('0': user mode; '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities. [0:0] read-write NS Security setting ('0': secure mode; '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters. [1:1] read-write PRIO Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. [9:8] read-write PC_MASK_0 Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. [16:16] read-only PC_MASK_15_TO_1 Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). [31:17] read-write MS1_CTL Master 1 protection context control 0x4 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS2_CTL Master 2 protection context control 0x8 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS3_CTL Master 3 protection context control 0xC 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS4_CTL Master 4 protection context control 0x10 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS5_CTL Master 5 protection context control 0x14 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS6_CTL Master 6 protection context control 0x18 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS7_CTL Master 7 protection context control 0x1C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS8_CTL Master 8 protection context control 0x20 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS9_CTL Master 9 protection context control 0x24 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS10_CTL Master 10 protection context control 0x28 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS11_CTL Master 11 protection context control 0x2C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS12_CTL Master 12 protection context control 0x30 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS13_CTL Master 13 protection context control 0x34 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS14_CTL Master 14 protection context control 0x38 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS15_CTL Master 15 protection context control 0x3C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write 16 64 SMPU_STRUCT[%s] SMPU structure 0x00002000 ADDR0 SMPU region address 0 (slave structure) 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT0 SMPU region attributes 0 (slave structure) 0x4 32 read-write 0x100 0x80000100 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write ADDR1 SMPU region address 1 (master structure) 0x20 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. [7:0] read-only ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only. [31:8] read-only ATT1 SMPU region attributes 1 (master structure) 0x24 32 read-write 0x7000109 0x9F00012D UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. [0:0] read-only UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. [2:2] read-only PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. [3:3] read-only PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. [5:5] read-only NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only. [28:24] read-only PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. [31:31] read-write 16 1024 MPU[%s] MPU 0x00004000 MS_CTL Master control 0x0 32 read-write 0x0 0xF000F PC Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: * On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: IF (the new PC is the same as MS_CTL.PC) PC is not affected; PC_SAVED is not affected. ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) An AHB-Lite bus error is generated for the exception handler fetch; PC is not affected; PC_SAVED is not affected. ELSE PC = 'new PC'; PC_SAVED = PC (push operation). * On entry of any other exception/interrupt handler: PC = PC_SAVED; PC_SAVED is not affected (pop operation). Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. [3:0] read-write PC_SAVED Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. Note: this field is ONLY used by the CM0+. [19:16] read-write 127 4 MS_CTL_READ_MIR[%s] Master control read mirror 0x4 32 read-only 0x0 0xF000F PC Read-only mirror of MS_CTL.PC [3:0] read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED [19:16] read-only 8 32 MPU_STRUCT[%s] MPU structure 0x00000200 ADDR MPU region address 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT MPU region attrributes 0x4 32 read-write 0x0 0x80000000 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write FLASHC Flash controller 0x40240000 0 65536 registers FLASH_CTL Control 0x0 32 read-write 0x1000000 0x177330F WS FLASH macro wait states (same for main and work interfaces): '0': 0 wait states. ... '15': 15 wait states [3:0] read-write MAIN_MAP N/A [8:8] read-write WORK_MAP N/A [9:9] read-write MAIN_BANK_MODE N/A [12:12] read-write WORK_BANK_MODE N/A [13:13] read-write MAIN_ECC_EN N/A [16:16] read-write MAIN_ECC_INJ_EN N/A [17:17] read-write MAIN_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error or a FLASH macro main interface internal error): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (or debug i.e. SYS_AP/CM0_AP/CM7_0/1_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS, CM7_0_STATUS and CM7_1_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro main interface internal error. - FLASH macro main interface non-recoverable ECC error. - FLASH macro main interface recoverable ECC error. [18:18] read-write WORK_ECC_EN N/A [20:20] read-write WORK_ECC_INJ_EN N/A [21:21] read-write WORK_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error or a FLASH macro work interface internal error): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (or debug i.e. SYS_AP/CM0_AP/CM7_0/1_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS, CM7_0_STATUS and CM7_1_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro work interface internal error. - FLASH macro work interface non-recoverable ECC error. - FLASH macro work interface recoverable ECC error. [22:22] read-write WORK_SEQ_RD_EN Enable sequential read mode for Work Flash for read accesses on the AXI port. 0: Sequential read mode for Work Flash is disabled. 1: Sequential read mode for Work Flash is enabled. This speeds up subsequent AXI read accesses to the same page (64 bytes) of the Work Flash. Setting this field to '1' has a side effect on the round-robin arbitration of the Work Flash macro between the different ports. When this field is set to '1', then as soon as the arbitration of the Work Flash is given to the AXI port, it is not released before the current AXI read burst either has been completed or leaves the current Work Flash page (64 bytes). This means that AHB masters accessing the Work Flash that have the same priority as the AXI port will not get their fair share of the Work Flash bandwidth. While an AHB master can perform one Work Flash access per round-robin cycle (4 bytes), an AXI master can read a whole AXI burst, or up to the next Work Flash page boundary. So if this field is set to '1', and an AHB master requires a high Work Flash bandwidth, then it should have a higher priority than the AXI masters accessing the Work Flash. [24:24] read-write FLASH_PWR_CTL Flash power control 0x4 32 read-write 0x3 0x3 ENABLE Controls 'enable' pin of the Flash memory. [0:0] read-write ENABLE_HV Controls 'enable_hv' pin of the Flash memory. [1:1] read-write FLASH_CMD Command 0x8 32 read-write 0x0 0x3 INV Invalidation of ALL caches (for CM0+) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches LRU structures are also reset to their default state. [0:0] read-write BUFF_INV Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. [1:1] read-write ECC_CTL ECC control 0x2A0 32 read-write 0x0 0xFFFFFFFF WORD_ADDR N/A [23:0] read-write PARITY N/A [31:24] read-write FM_SRAM_ECC_CTL0 eCT Flash SRAM ECC control 0 0x2B0 32 read-write 0x0 0xFFFFFFFF ECC_INJ_DATA 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. [31:0] read-write FM_SRAM_ECC_CTL1 eCT Flash SRAM ECC control 1 0x2B4 32 read-write 0x0 0x7F ECC_INJ_PARITY 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. [6:0] read-write FM_SRAM_ECC_CTL2 eCT Flash SRAM ECC control 2 0x2B8 32 read-only 0x0 0xFFFFFFFF CORRECTED_DATA 32-bit corrected data output of the ECC syndrome logic. [31:0] read-only FM_SRAM_ECC_CTL3 eCT Flash SRAM ECC control 3 0x2BC 32 read-write 0x1 0x111 ECC_ENABLE ECC generation/check enable for eCT Flash SRAM memory. [0:0] read-write ECC_INJ_EN eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: 1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. 2. Set the ECC_INJ_EN bit to '1'. 3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. 4. Check the corrected data in FM_SRAM_ECC_CTL2. 5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if corrupted data was written in step 1). 6. If not finished, start over at 1 with different data. [4:4] read-write ECC_TEST_FAIL Status of ECC test. 1: ECC test failed because eCT Flash macro is busy and using the SRAM. 0: ECC was performed. [8:8] read-only CM0_CA_CTL0 CM0+ cache control 0x400 32 read-write 0xC0000001 0xC7030003 RAM_ECC_EN Enable ECC checking for cache accesses: 0: Disabled. 1: Enabled. [0:0] read-write RAM_ECC_INJ_EN Enable error injection for cache. When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[24:0] word address. [1:1] read-write WAY Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. [17:16] read-write SET_ADDR Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. [26:24] read-write PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. [30:30] read-write CA_EN Cache enable: 0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). 1: Enabled.G269 [31:31] read-write CM0_CA_CTL1 CM0+ cache control 0x404 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Specifies power mode for CM0 cache. The following sequnece should be followed for truning OFF/ON the cache SRAM. Turn OFF sequence: a) Write CM0_CA_CTL0 to disable cache. b) Write CM0_CA_CTL1 to turn OFF cache SRAM. Turn ON sequence: a) Write CM0_CA_CTL1 to turn ON cache SRAM. b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. c) Write CM0_CA_CTL0 to enable cache. [1:0] read-write OFF Power OFF the CM0 cache SRAM. 0 RSVD Undefined 1 RETAINED Put CM0 cache SRAM in retained mode. 2 ENABLED Enable/Turn ON the CM0 cache SRAM. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM0_CA_CTL2 CM0+ cache control 0x408 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM0_CA_STATUS0 CM0+ cache status 0 0x440 32 read-only 0x0 0xFFFFFFFF VALID32 Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS1 CM0+ cache status 1 0x444 32 read-only 0x0 0x0 TAG Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS2 CM0+ cache status 2 0x448 32 read-only 0x0 0x0 LRU Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3. [5:0] read-only CM0_STATUS CM0+ interface status 0x460 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ (or debug access via SYS_AP/CM0_AP) access. SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM0_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CM7_0_STATUS CM7 #0 interface status 0x4E0 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_0 (or debug access via SYS_AP/CM7_0_AP) access. SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM7_0_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CM7_1_STATUS CM7 #1 interface status 0x560 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_1 (or debug access via SYS_AP/CM7_1_AP) access. SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM7_1_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CRYPTO_BUFF_CTL Cryptography buffer control 0x580 32 read-write 0x40000000 0x40000000 PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. [30:30] read-write DW0_BUFF_CTL Datawire 0 buffer control 0x600 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write DW1_BUFF_CTL Datawire 1 buffer control 0x680 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write DMAC_BUFF_CTL DMA controller buffer control 0x700 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write SLOW0_MS_BUFF_CTL Slow external master 0 buffer control 0x780 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write SLOW1_MS_BUFF_CTL Slow external master 1 buffer control 0x800 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write FM_CTL_ECT Flash Macro Registers 0x0000F000 FM_CTL Flash Macro Control 0x0 32 read-write 0x0 0x8000001F FM_MODE Flash macro mode selection: d0: Read/Idle - Normal mode, read array enabled d1: Not Used - the 1st analog POR is done by enable/enable_hv d2 - POR FUR Download - Downloads critical Flash initialization data from OTP (BG, rd, redu, etc....) d3 - POR IRAM MMR Download - Downloads from OTP region the MMR / IRAM into to the 8051 RDL shadows d4 - POR SW Download - Downloads from OTP region the SW code into to the 8051 MCU SRAM d5 - POR Code_Work Prepare - Loads the Code and Work Flash MG's to be ready for user mode operation d6 - Not Used d7 - Program 32b (WORK) - Used as program confirm command for 32 (Work) bits program d8 - Program 64b (CODE) - Used as program confirm command for 64 (Code) bits program d9 - Program 256b (CODE) - Used as program confirm command for 256 (Code) bits program d10: Program Page (CODE) - Used as program confirm command for page program for Code flash d11: Not Used d12 - Sector Erase - Erase for all kinds of sectors (Code/Work/SMS) d13 - Blank check Entry (UBC) d14 - Blank Check Read 32bit (WORK) - Blank check mode d15 - Blank check Exit d16 - Not Used d17 - Erase Suspend - Suspend command to the Erase operation d18 - Erase Resume - Resume command to Erase suspended operation d19 - Not Used d20- Not Used d21- Not Used d22- Not Used d23- Not Used d24- Not Used d25- Not Used d26- Not Used d27- Not Used d28- Not Used d29- Not Used d30: Not Used d31: Not Used [4:0] read-write EMB_START '0': not active '1': starts the actual embedded operation [31:31] read-write FM_CODE_MARGIN Flash Macro Margin Mode on Code Flash 0x4 32 read-write 0x3943 0xE000FFFF MARGIN_DCS_TRIM see above table to set the DCS reference current value to be used during Margin mode. (default set to 5uS = 0x143) which gives a Margin to the Erase side. 7uA would probably be used for Margin to the PGM side [8:0] read-write MARGIN_DCS_TRIM_EN 0: internal device defaults used from Margin reads reference current 1: MARGIN_DCS_TRIM configuration is used during Margin read [9:9] read-write MARGIN_RDREG_TRIM rdreg_c trim to be used in Margin mode if enabled by MARGIN_MODE_RDREG_CHNG_EN [15:10] read-write MARGIN_PGM_ERS_B 0: ERS Margin is checked 1: PGM Margin is checked [29:29] read-write MARGIN_MODE_RDREG_CHNG_EN when set will also use the MARGIN_RDREG_TRIM from above. Default is not to use [30:30] read-write MARGIN_MODE_EN when set puts the s40ect Flash IP In Margin mode [31:31] read-write FM_ADDR Flash Macro Address 0x8 32 write-only 0x0 0xFFFFFFFF FM_ADDR Code or Work Flash Address to be used during write operations (PGM/ERS) [31:0] write-only INTR Interrupt 0x20 32 read-write 0x0 0x1 INTR Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. [0:0] read-write INTR_SET Interrupt Set 0x24 32 read-write 0x0 0x1 INTR_SET Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt Mask 0x28 32 read-write 0x0 0x1 INTR_MASK Mask for corresponding field in the INTR register [0:0] read-write INTR_MASKED Interrupt Masked 0x2C 32 read-only 0x0 0x1 INTR_MASKED Logical and of corresponding request and mask fields. [0:0] read-only ECC_OVERRIDE ECC Data In override information and control bits 0x30 32 write-only 0x0 0xC00000FF ECC_OVERRIDE_SYNDROME The override syndrome itself to be used in case one of the enables are set. It will take [7:0] in the case of Code flash and [6:0] in the case of work flash, to bypass the internal generated syndrome [7:0] write-only ECC_OVERRIDE_WORK 0: no override. Using internal ECC engine to calculate the ECC of the Work Flash [30:30] write-only ECC_OVERRIDE_CODE 0: no override. Using internal ECC engine to calculate the ECC of the Code Flash [31:31] write-only FM_DATA Flash macro data_in[31 to 0] both Code and Work Flash 0x40 32 write-only 0x0 0xFFFFFFFF FM_DATA Pgm command data in going to the internal write buffer (WBUF). [31:0] write-only BOOKMARK Bookmark register - keeps the current FW HV seq 0x64 32 read-write 0x0 0xFFFFFFFF BOOKMARK Used by FW. Keeps the Current HV cycle sequence [31:0] read-write MAIN_FLASH_SAFETY Main (Code) Flash Security enable 0x400 32 read-write 0x0 0x1 MAINFLASHWRITEENABLE '0': Main Flash embedded operations are blocked '1': Main Flash embedded operations are enabled [0:0] read-write STATUS Status read from Flash Macro 0x404 32 read-only 0x80000000 0xF800007F PGM_CODE Indicates if active PGM operation to the Code flash is taking place 0: not running 1: running [0:0] read-only PGM_WORK Indicates if active PGM operation to the Work flash is taking place 0: not running 1: running [1:1] read-only ERASE_CODE Indicates if active Erase operation to the Code flash is taking place 0: not running 1: running [2:2] read-only ERASE_WORK Indicates if active Erase operation to the Work flash is taking place 0: not running 1: running [3:3] read-only ERS_SUSPEND Indicates if Erase operation (Code/Work) is currently being suspended 0: not suspended 1: suspended [4:4] read-only BLANK_CHECK_WORK Indicates if Blank Check mode is currently running on the work flash 0: not running 1: running [5:5] read-only BLANK_CHCEK_PASS Indicates the Blank check command result is PASS (Blank) 0: Not Blank 1: Blank (PASS) [6:6] read-only POR_1B_ECC_CORRECTED Indicates internal ECC found 1b error while downloading info in POR from NVM to VM and fixed it. Valid after 2nd, 3rd and 4th POR phases (FUR, IREM & MMR, SW DOWNLOAD). If Set it is not cleaned till additional POR (rst_hf_ac_t) 0: No error 1: 1b ECC Error corrected in POR [27:27] read-only POR_2B_ECC_ERROR Indicates an internal ECC error of 2b while downloading info in POR from NVM to VM. Valid after 2nd, 3rd and 4th POR phases (FUR, IREM & MMR, SW DOWNLOAD). If Set it is not cleaned till additional POR (rst_hf_ac_t) 0: No error 1: ECC 2b Error in POR [28:28] read-only NATIVE_POR Indicates a Native Flash state (UV) or sorted one. Valid only after 2nd phase of POR (FUR DOWNLOAD). Comment: not a retained flop, therefore reset (rst_hf_act_n) puts it back to 0. If Set it is not cleaned till additional POR (rst_hf_ac_t) 0: SORTED DEVICE (Non - Native) 1: NATIVE [29:29] read-only HANG After embedded operation (pgm/erase) this flag will tell if it was successful or failed 0: PASS 1: FAIL [30:30] read-only BUSY Whenever the device is in embedded mode the RDY goes low. Should be the same as c_interrupt pin of the IP (but inverted) 1: busy in embedded 0: rdy (high also in erase suspend) [31:31] read-only WORK_FLASH_SAFETY Work Flash Security enable 0x500 32 read-write 0x0 0x1 WORKFLASHWRITEENABLE 0: Work Flash embedded operations are blocked 1: Work Flash embedded operations are enabled [0:0] read-write SRSS SRSS Core Registers (ver3p3) 0x40260000 0 65536 registers PWR_LVD_STATUS High Voltage / Low Voltage Detector (HVLVD) Status Register 0x40 32 read-only 0x0 0x1 HVLVD1_OUT HVLVD1 output. 0: below voltage threshold 1: above voltage threshold [0:0] read-only PWR_LVD_STATUS2 High Voltage / Low Voltage Detector (HVLVD) Status Register #2 0x44 32 read-only 0x0 0x1 HVLVD2_OUT HVLVD2 output. 0: below voltage threshold 1: above voltage threshold [0:0] read-only 16 4 CLK_DSI_SELECT[%s] Clock DSI Select Register 0x100 32 read-write 0x0 0x1F DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. [4:0] read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO0 ILO0 - Internal Low-speed Oscillator #0 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 ILO1 ILO1 - Internal Low-speed Oscillator #1, if present. 20 CLK_OUTPUT_FAST Fast Clock Output Select Register 0x140 32 read-write 0x0 0xFFF0FFF FAST_SEL0 Select signal for fast clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL0 Selects the clock path chosen by PATH_SEL0 field 5 HFCLK_SEL0 Selects the output of the HFCLK_SEL0 mux 6 SLOW_SEL0 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 7 PATH_SEL0 Selects a clock path to use in fast clock output #0 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) [7:4] read-write HFCLK_SEL0 Selects a HFCLK tree for use in fast clock output #0 [11:8] read-write FAST_SEL1 Select signal for fast clock output #1 [19:16] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL1 Selects the clock path chosen by PATH_SEL1 field 5 HFCLK_SEL1 Selects the output of the HFCLK_SEL1 mux 6 SLOW_SEL1 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 7 PATH_SEL1 Selects a clock path to use in fast clock output #1 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) [23:20] read-write HFCLK_SEL1 Selects a HFCLK tree for use in fast clock output #1 logic [27:24] read-write CLK_OUTPUT_SLOW Slow Clock Output Select Register 0x144 32 read-write 0x0 0xFF SLOW_SEL0 Select signal for slow clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO0 Internal Low Speed Oscillator (ILO0) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 ILO1 Internal Low Speed Oscillator (ILO1), if present on the product. 9 ECO_PRESCALER ECO Prescaler (ECO_PRESCALER) 10 LPECO LPECO 11 LPECO_PRESCALER LPECO Prescaler (LPECO_PRESCALER) 12 SLOW_SEL1 Select signal for slow clock output #1 [7:4] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO0 Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 ILO1 Internal Low Speed Oscillator (ILO1), if present on the product. 9 ECO_PRESCALER ECO Prescaler (ECO_PRESCALER) 10 LPECO LPECO 11 LPECO_PRESCALER LPECO Prescaler (LPECO_PRESCALER) 12 CLK_CAL_CNT1 Clock Calibration Counter 1 0x148 32 read-write 0x80000000 0x80FFFFFF CAL_COUNTER1 Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. [23:0] read-write CAL_COUNTER_DONE Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up [31:31] read-only CLK_CAL_CNT2 Clock Calibration Counter 2 0x14C 32 read-only 0x0 0xFFFFFF CAL_COUNTER2 Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) [23:0] read-only SRSS_INTR SRSS Interrupt Register 0x200 32 read-write 0x0 0x26 HVLVD1 Interrupt for low voltage detector HVLVD1 [1:1] read-write HVLVD2 Interrupt for low voltage detector HVLVD2 [2:2] read-write CLK_CAL Clock calibration counter is done. This field is reset during DEEPSLEEP mode. [5:5] read-write SRSS_INTR_SET SRSS Interrupt Set Register 0x204 32 read-write 0x0 0x26 HVLVD1 Set interrupt for low voltage detector HVLVD1 [1:1] read-write HVLVD2 Set interrupt for low voltage detector HVLVD2 [2:2] read-write CLK_CAL Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. [5:5] read-write SRSS_INTR_MASK SRSS Interrupt Mask Register 0x208 32 read-write 0x0 0x26 HVLVD1 Mask for low voltage detector HVLVD1 [1:1] read-write HVLVD2 Mask for low voltage detector HVLVD2 [2:2] read-write CLK_CAL Mask for clock calibration done [5:5] read-write SRSS_INTR_MASKED SRSS Interrupt Masked Register 0x20C 32 read-only 0x0 0x26 HVLVD1 Logical and of corresponding request and mask bits. [1:1] read-only HVLVD2 Logical and of corresponding request and mask bits. [2:2] read-only CLK_CAL Logical and of corresponding request and mask bits. [5:5] read-only PWR_CTL Power Mode Control 0x1000 32 read-only 0x0 0x33 POWER_MODE Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. [1:0] read-only RESET System is resetting. 0 ACTIVE At least one CPU is running. 1 SLEEP No CPUs are running. Peripherals may be running. 2 DEEPSLEEP Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. 3 DEBUG_SESSION Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) [4:4] read-only NO_SESSION No debug session active 0 SESSION_ACTIVE Debug session is active. Power modes behave differently to keep the debug session active. 1 LPM_READY Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES, HIBERNATE wakeup, or supply supervision reset wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. [5:5] read-only PWR_CTL2 Power Mode Control 2 0x1004 32 read-write 0x0 0x9F731117 LINREG_DIS Explicitly disable the linear Core Regulator. Write zero for Traveo II devices. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: Linear Core Regulator is not explicitly disabled. Hardware disables it automatically for internal sequences, including for DEEPSLEEP, HIBERNATE, and XRES low power modes. 1: Linear Core Regulator is explicitly disabled. Only use this for special cases when another source supplies vccd during ACTIVE and SLEEP modes. This setting is only legal when another source supplies vccd, but there is no special hardware protection for this case. [0:0] read-write LINREG_OK Status of the linear Core Regulator. [1:1] read-only LINREG_LPMODE Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. 1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. [2:2] read-write DPSLP_REG_DIS Explicity disable the DeepSleep regulator, including circuits shared with the Active Regulator. This register must not be set except as part of a Cypress-provided sequence or API, such as the PMIC case described below. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. If the DeepSleep regulator is disabled, it is not supported to enable it again later by clearing this bit. 0: DeepSleep Regulator is not explicitly disabled. This is the normal setting, and hardware automatically controls the DeepSleep regulator for most sequences, including for HIBERNATE and XRES low power modes. This setting must be used if the Active Linear Regulator is used, because some circuitry is shared. 1: DeepSleep Regulator is explicitly disabled. Only use this for special cases when another source supplies vccdpslp during DEEPSLEEP mode and there is no future intention to use the Active Regulator for ACTIVE/SLEEP modes. For example, this setting is used as part of a Cypress-provided handover sequence to a PMIC that operates in ACTIVE, SLEEP, and DEEPSLEEP and disables both the Active Linear Regulator and DeepSleep Regulator. [4:4] read-write RET_REG_DIS Explicitly disable the Retention regulator. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: Retention Regulator is not explicitly disabled. Hardware disables it automatically for internal sequences, including for HIBERNATE and XRES low power modes. Hardware keeps the Retention Regulator enabled during ACTIVE/SLEEP modes, so it is ready to enter DEEPSLEEP at any time. 1: Retention Regulator is explicitly disabled. Only use this for special cases when another source supplies vccret during DEEPSLEEP mode. This setting is only legal when another source supplies vccret, but there is no special hardware protection for this case. [8:8] read-write NWELL_REG_DIS Explicitly disable the Nwell regulator. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: Nwell Regulator is on. Hardware disables it automatically for internal sequences, including for HIBERNATE and XRES low power modes. Hardware keeps the Nwell Regulator enabled during ACTIVE/SLEEP modes, so it is ready to enter DEEPSLEEP at any time. 1: Nwell Regulator is explicitly disabled. Only use this for special cases when another source supplies vnwell during DEEPSLEEP mode. This setting is only legal when another source supplies vnwell, but there is no special hardware protection for this case. [12:12] read-write REFV_DIS N/A [16:16] read-write REFV_OK Indicates that the normal mode of the voltage reference is ready. [17:17] read-only REFVBUF_DIS Disable the voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. [20:20] read-write REFVBUF_OK Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFVBUF_DIS=1. [21:21] read-only REFVBUF_LPMODE Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. [22:22] read-write REFI_DIS N/A [24:24] read-write REFI_OK Indicates that the current reference is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS=1. [25:25] read-only REFI_LPMODE Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. 1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. [26:26] read-write PORBOD_LPMODE Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. [27:27] read-write BGREF_LPMODE Control the circuit-level power mode of the Bandgap Reference circuits. 0: Bandgap Reference circuits operate in higher current mode. 1: Bandgap Reference circuits operate in low power. Refer to documentation for restrictions. HT-variant: This register will not set unless CLK_ILO0_CONFIG.ILO0_ENABLE==1. When disabling low power operation, keep ILO0 enabled for at least 5 cycles after clearing this bit to allow for internal synchronization. [28:28] read-write PLL_LS_BYPASS Bypass level shifter inside the PLL. Unused, if no PLL is present in the product. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. [31:31] read-write PWR_HIBERNATE HIBERNATE Mode Register 0x1008 32 read-write 0x0 0xEFFEFFFF TOKEN Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. [7:0] read-write UNLOCK This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. [15:8] read-write FREEZE Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. Supply supervision is disabled during HIBERNATE mode. HIBERNATE peripherals ignore resets (excluding XRES) while FREEZE==1. [17:17] read-write MASK_HIBALARM Obsolete. Use PWR_HIB_WAKE_CTL.HIB_WAKE_RTC for new designs. [18:18] read-write MASK_HIBWDT Obsolete. Use PWR_HIB_WAKE_CTL.HIB_WAKE_WDT for new designs. [19:19] read-write POLARITY_HIBPIN Obsolete. Use PWR_HIB_WAKE_CTL2.HIB_WAKE_SRC for new designs. [23:20] read-write MASK_HIBPIN Obsolete. Use PWR_HIB_WAKE_CTL.HIB_WAKE_SRC for new designs. [27:24] read-write SENSE_MODE Power mode when wakeups are sensitive. The default of this field is 0 for software compatibility with other products. It is recommended to set this field to 1 for new/updated software. 0: Wakeups are sensitive only during HIBERNATE mode. A wakeup pulse that comes just before HIBERNATE entry may be missed. Backward compatible. 1: Wakeups are sensitive in HIBERNATE and higher modes. Before entering HIBERNATE, software must clear all unmasked, pending wakeups in PWR_HIB_WAKE_CAUSE register. An unmasked, pending wakeup causes HIBERNATE wakeup, even if it was pending from before HIBERNATE entry. This prevents missed wakeups. [29:29] read-write HIBERNATE_DISABLE Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. [30:30] read-write HIBERNATE Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. [31:31] read-write PWR_BUCK_CTL Buck Control Register 0x1010 32 read-write 0x5 0xC0000007 BUCK_OUT1_SEL Voltage output selection for vccbuck1 output. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V [2:0] read-write BUCK_EN Master enable for buck converter. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. [30:30] read-write BUCK_OUT1_EN Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. [31:31] read-write PWR_BUCK_CTL2 Buck Control Register 2 0x1014 32 read-write 0x0 0xC0000007 BUCK_OUT2_SEL Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V [2:0] read-write BUCK_OUT2_HW_SEL Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. [30:30] read-write BUCK_OUT2_EN Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. [31:31] read-write PWR_SSV_CTL Supply Supervision Control Register 0x1018 32 read-write 0x8080808 0x9D909D9 BODVDDD_VSEL Selects the voltage threshold for BOD on vddd. The BOD does not reliably monitor the supply during the transition. 0: vddd<2.7V 1: vddd<3.0V [0:0] read-write BODVDDD_ENABLE Enable for BOD on vddd. This cannot be disabled during normal operation. [3:3] read-write BODVDDA_VSEL Selects the voltage threshold for BOD on vdda. Ensure BODVDDA_ENABLE==0 before changing this setting to prevent false triggers. 0: vdda<2.7V 1: vdda<3.0V [4:4] read-write BODVDDA_ACTION Action taken when the BOD on vdda triggers. [7:6] read-write NOTHING No action 0 FAULT Generate a fault 1 RESET Reset the chip 2 BODVDDA_ENABLE Enable for BOD on vdda. BODVDDA_ACTION will be triggered when the BOD is disabled. If no action is desired when disabling, firmware must first write BODVDDA_ACTION=NOTHING in a separate write cycle. [8:8] read-write BODVCCD_ENABLE Enable for BOD on vccd. This cannot be disabled during normal operation. [11:11] read-write OVDVDDD_VSEL Selects the voltage threshold for OVD on vddd. The OVD does not reliably monitor the supply during the transition. 0: vddd>5.5V 1: vddd>5.0V [16:16] read-write OVDVDDD_ENABLE Enable for OVD on vddd. This cannot be disabled during normal operation. [19:19] read-write OVDVDDA_VSEL Selects the voltage threshold for OVD on vdda. Ensure OVDVDDA_ENABLE==0 before changing this setting to prevent false triggers 0: vddd>5.5V 1: vddd>5.0V [20:20] read-write OVDVDDA_ACTION Action taken when the OVD on vdda triggers. [23:22] read-write NOTHING No action 0 FAULT Generate a fault 1 RESET Reset the chip 2 OVDVDDA_ENABLE Enable for OVD on vdda. [24:24] read-write OVDVCCD_ENABLE Enable for OVD on vccd. This cannot be disabled during normal operation. [27:27] read-write PWR_SSV_STATUS Supply Supervision Status Register 0x101C 32 read-only 0x30505 0x30707 BODVDDD_OK BOD indicates vddd is ok. This will always read 1, because a detected brownout will reset the chip. [0:0] read-only BODVDDA_OK BOD indicates vdda is ok. [1:1] read-only BODVCCD_OK BOD indicates vccd is ok. This will always read 1, because a detected brownout will reset the chip. [2:2] read-only OVDVDDD_OK OVD indicates vddd is ok. This will always read 1, because a detected over-voltage condition will reset the chip. [8:8] read-only OVDVDDA_OK OVD indicates vdda is ok. [9:9] read-only OVDVCCD_OK OVD indicates vccd is ok. This will always read 1, because a detected over-over-voltage condition will reset the chip. [10:10] read-only OCD_ACT_LINREG_OK OCD indicates the current drawn from the linear Active Regulator is ok. This will always read 1, because a detected over-current condition will reset the chip. [16:16] read-only OCD_DPSLP_REG_OK OCD indicates the current drawn from the linear DeepSleep Regulator is ok. This will always read 1, because a detected over-current condition will reset the chip. [17:17] read-only PWR_LVD_CTL High Voltage / Low Voltage Detector (HVLVD) Configuration Register 0x1020 32 read-write 0x0 0x7DFFF HVLVD1_TRIPSEL Threshold selection for HVLVD1. Disable the detector (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom) [3:0] read-write HVLVD1_SRCSEL Source selection for HVLVD1 [6:4] read-write VDDD Select VDDD 0 AMUXBUSA Select AMUXBUSA (VDDD branch) 1 RSVD N/A 2 VDDIO N/A 3 AMUXBUSB Select AMUXBUSB (VDDD branch) 4 HVLVD1_EN Enable HVLVD1 voltage monitor. HVLVD1 does not function during DEEPSLEEP, but it automatically returns to its configured setting after DEEPSLEEP wakeup. Do not change other HVLVD1 settings when enabled. [7:7] read-write HVLVD1_TRIPSEL_HT N/A [12:8] read-write HVLVD1_DPSLP_EN_HT Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1. [14:14] read-write HVLVD1_EN_HT Enable HVLVD1 voltage monitor. This detector monitors vddd only. Do not change other HVLVD1 settings when enabled. [15:15] read-write HVLVD1_EDGE_SEL Sets which edge(s) will trigger an action when the threshold is crossed. [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 HVLVD1_ACTION Action taken when the threshold is crossed in the programmed directions(s) [18:18] read-write INTERRUPT Generate an interrupt 0 FAULT Generate a fault 1 PWR_LVD_CTL2 High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2 0x1024 32 read-write 0x0 0x7DF00 HVLVD2_TRIPSEL_HT N/A [12:8] read-write HVLVD2_DPSLP_EN_HT Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1. [14:14] read-write HVLVD2_EN_HT Enable HVLVD2 voltage monitor. This detector monitors vddd only. Do not change other HVLVD2 settings when enabled. [15:15] read-write HVLVD2_EDGE_SEL Sets which edge(s) will trigger an action when the threshold is crossed. [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 HVLVD2_ACTION Action taken when the threshold is crossed in the programmed directions(s) [18:18] read-write INTERRUPT Generate an interrupt 0 FAULT Generate a fault 1 PWR_REGHC_CTL REGHC Control Register 0x1028 32 read-write 0x40000104 0xFFFF7DFD REGHC_MODE REGHC control mode: 0: external transistor connected, 1: external PMIC connected [0:0] read-write REGHC_PMIC_DRV_VOUT Setting for DRV_VOUT pin for PMIC mode. See REGHC_VADJ for calculation of vadj. 2'b00: DRV_VOUT=vccd*0.9/vadj; 2'b01: DRV_VOUT=vccd*0.8/vadj; 2'b10: DRV_VOUT=vccd*0.6/vadj; 2'b11: DRV_VOUT=vccd [3:2] read-write REGHC_VADJ Regulator output trim according to the formula vadj=(1.020V + REGHC_VADJ*0.005V) plus an offset described below. For example, 0x1A=>1.15V (nominal). For transistor mode, REGHC will dynamically adjust DRV_VOUT so the supply targets the vadj voltage. Adjust for die to die variation by adding the signed offset value in SFLASH SRSS_PWR_OFFSET.REGHC_TRANS_VADJ_OFFSET. Note: SRSS_PWR_OFFSET.REGHC_TRANS_VADJ_OFFSET value is calculated using the default value of the REGHC_VADJ: 0x10 (1.1V) and applies to the full range of REGHC target voltages. For PMIC mode, adjust for die to die variation by adding the signed offset value in SFLASH SRSS_PWR_OFFSET.PMIC_VADJ_OFFSET to the nominal calculated code. For PMIC mode, also see REGHC_PMIC_DRV_VOUT. [8:4] read-write REGHC_PMIC_USE_LINREG For REGHC external PMIC mode, controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature, if the PMIC fails to keep vccd above the internal regulator target, then the internal regulator will attempt to recover vccd. If the regulator current is too high, the regulator triggers an over-current detector (OCD) reset. 0: Internal Active Linear Regulator disabled after PMIC enabled. OCD is disabled.; 1: Internal Active Linear Regulator kept enabled. See datasheet for minimum PMIC vccd input to prevent OCD. [10:10] read-write REGHC_PMIC_USE_RADJ Controls whether hardware sequencer enables reset voltage adjustment circuit when enabling a PMIC. [11:11] read-write REGHC_PMIC_RADJ Reset voltage adjustment for PMIC as a factor (Vfbk/Vref) where Vfbk is the feedback voltage and Vref is the PMIC internal reference. The reset voltage adjustment circuit is enabled by the hardware sequencer if REGHC_PMIC_USE_RADJ=1. PMIC have Vref of 0.8V or 0.9V, and the resulting reset voltage (Vreset) are precalculated in the table below: 3'b000: Vfbk/Vref=1.0000, Vreset=.800V@(Vref=0.8V), .900V@(Vref=0.9V); 3'b001: Vfbk/Vref=1.0556, Vreset=.844V@(Vref=0.8V), .950V@(Vref=0.9V); 3'b010: Vfbk/Vref=1.1111, Vreset=.889V@(Vref=0.8V), 1.000V@(Vref=0.9V); 3'b011: Vfbk/Vref=1.1250, Vreset=.900V@(Vref=0.8V), 1.013V@(Vref=0.9V); 3'b100: Vfbk/Vref=1.1667, Vreset=.933V@(Vref=0.8V), 1.050V@(Vref=0.9V); 3'b101: Vfbk/Vref=1.1875, Vreset=.950V@(Vref=0.8V), 1.069V@(Vref=0.9V); 3'b110: Vfbk/Vref=1.2500, Vreset=1.000V@(Vref=0.8V), 1.125V@(Vref=0.9V); 3'b111: Vfbk/Vref=1.3125, Vreset=1.050V@(Vref=0.8V), 1.181V@(Vref=0.9V); [14:12] read-write REGHC_PMIC_CTL_OUTEN Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin. [16:16] read-write REGHC_PMIC_CTL_POLARITY Polarity used to enable the PMIC. The sequencer uses REGHC_PMIC_CTL_POLARITY to enable the PMIC, and it uses the complement to disable the PMIC. [17:17] read-write REGHC_PMIC_STATUS_INEN Input buffer enable for PMIC status input. Set this bit high to enable the input receiver. [18:18] read-write REGHC_PMIC_STATUS_POLARITY The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value. [19:19] read-write REGHC_PMIC_STATUS_WAIT Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us. [29:20] read-write REGHC_TRANS_USE_OCD N/A [30:30] read-write REGHC_CONFIGURED Indicates the REGHC has been configured. This is used to know if REGHC should be enabled in response to a debug power up request. It is recommended to not change REGHC settings after REGHC_CONFIGURED is set high, because it can cause failure if REGHC is enabled or transitioning. [31:31] read-write PWR_REGHC_STATUS REGHC Status Register 0x102C 32 read-only 0x0 0x80001307 REGHC_ENABLED Indicates the state of the REGHC enable/disable sequencer. This bit is only valid when REGHC_SEQ_BUSY==0. 0: REGHC sequencer indicates REGHC is disabled. 1: REGHC sequencer indicates REGHC is enabled. [0:0] read-only REGHC_OCD_OK Indicates the over-current detector is operating and the current drawn from REGHC is within limits. OCD is only a choice for transistor mode, and it is disabled for PMIC mode. 0: Current measurement exceeds limit or detector is OFF, 1: Current measurement within limit [1:1] read-only REGHC_CKT_OK Indicates the REGHC circuit is enabled and operating. It does not indicate that the voltage and current are within required limits for robust operation. 0: REGHC circuit is not ready. This can occur if the REGHC circuit is disabled or if it was recently enabled. 1: REGHC circuit is enabled and operating. [2:2] read-only REGHC_UV_OUT N/A [8:8] read-only REGHC_OV_OUT N/A [9:9] read-only REGHC_PMIC_STATUS_OK Indicates the PMIC status is ok. This includes polarity adjustment according to REGHC_PMIC_STATUS_POLARITY. 0: PMIC status is not ok or PMIC input buffer is disabled (REGHC_PMIC_STATUS_INEN==0); 1: PMIC status input buffer is enabled and indicates ok [12:12] read-only REGHC_SEQ_BUSY Indicates the REGHC enable/disable sequencer is busy transitioning to/from REGHC. 0: Sequencer is not busy; 1: Sequencer is busy either enabling or disabling REGHC. [31:31] read-only PWR_REGHC_CTL2 REGHC Control Register 2 0x1030 32 read-write 0x0 0x800000FF REGHC_PMIC_STATUS_TIMEOUT Timeout while waiting for REGHC_PMIC_STATUS_OK==1 when switching to PMIC. 0: disables timeout. >0: enables timeout of REGHC_PMIC_STATUS_TIMEOUT*128us (nominal, clocked by IMO). Timeout expiration generates a 'reset' condition that is only recorded in RES_CAUSE but does not trigger a reset for the SOC, however a WDT will reset the system with REGHC RES_CAUSE. [7:0] read-write REGHC_EN Enable REGHC. This bit will not set if REGHC_CONFIGURED==0. Use PWR_REGHC_STATUS.ENABLED to know the actual status of REGHC. It will differ from this bit in the following cases: A) Do not enter DEEPSLEEP while the sequencer is busy (see PWR_REGHC_STATUS.REGHC_SEQ_BUSY). The hardware sequencer disables REGHC during DEEPSLEEP entry and enables it upon wakeup. B) The debugger requests the chip remain powered up. Hardware prevents REGHC from disabling when this bit is cleared. Hardware does not automatically enable REGHC in response to debugger power up request. If this bit is low when the debugger deasserts the power up request, the hardware sequencer will disable REGHC. [31:31] read-write PWR_REGHC_CTL4 REGHC Control Register 4 0x1038 32 read-write 0x0 0xC0000000 REGHC_PMIC_VADJ_DIS When operating in PMIC mode, disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device. 0: Device generates VADJ when PMIC is enabled. This allows the feedback loop to compensate for voltage drops in the PCB and package. 1: Device does not generate VADJ, and it must not be part of the PMIC feedback loop. This reduces current by turning off the internal resistor divider that generates VADJ. This setting is ineffective when REGHC_PMIC_RADJ_EN==1, and VADJ is generated in that case when PMIC is enabled. [30:30] read-write REGHC_PMIC_DPSLP When operating in PMIC mode, configures PMIC behavior during DEEPSLEEP. 0: Device operates from internal regulators during DEEPSLEEP. If PMIC is enabled at the beginning of the DEEPSLEEP transition, hardware changes to the internal regulators and disables the PMIC. 1: DEEPSLEEP transition does not change PMIC enable. [31:31] read-write 16 4 PWR_HIB_DATA[%s] HIBERNATE Data Register 0x1040 32 read-write 0x0 0xFFFFFFFF HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. [31:0] read-write PWR_PMIC_CTL PMIC Control Register 0x10C0 32 read-write 0x104 0xBFFF85FC PMIC_VREF PMIC reference voltage setting. This selects the scaling factor used to generate the output voltage (vout) given the feedback voltage (vfb) for the chosen PMIC. For a PMIC that compares vfb to an internal reference voltage (vref) according to the formula vout=vref/vfb, select that vref below. For a PMIC that contains an internal resistor divider and expects an unscaled feedback voltage, use the 'No scaling' choice. 2'b00: Scale for vref=0.9V, use PMIC_VADJ to set the vccd target; 2'b01: Scale for vref=0.8V, use PMIC_VADJ to set the vccd target; 2'b10: Scale for vref=0.6V, use PMIC_VADJ to set the vccd target; 2'b11: No scaling, PMIC_VADJ has no effect [3:2] read-write PMIC_VADJ Voltage adjustment output setting. The lookup table in this field requires the proper setting in PMIC_VREF for the chosen PMIC. This field has no effect when PMIC_VREF selects no scaling. The feedback tap point is at a vccd pad inside the chip, so the voltage may be a little higher at the PMIC output. Adjust for die to die variation by adding the signed offset value in SFLASH SRSS_PWR_OFFSET.PMIC_VADJ_OFFSET to desired code in this lookup table: 0x03: 1.040V, 0x04: 1.049V, 0x05: 1.057V, 0x06: 1.066V, 0x07: 1.074V, 0x08: 1.083V, 0x09: 1.091V, 0x0A: 1.099V, 0x0B: 1.108V, 0x0C: 1.116V, 0x0D: 1.125V, 0x0E: 1.133V, 0x0F: 1.142V, 0x10: 1.150V, 0x11: 1.158V, 0x12: 1.167V, 0x13: 1.175V, 0x14: 1.184V, 0x15: 1.192V, 0x16: 1.201V, 0x17: 1.209V, 0x18: 1.218V, 0x19: 1.226V, 0x1A: 1.234V, 0x1B: 1.243V, 0x1C: 1.251V, others: Illegal. Behavior is undefined. [8:4] read-write PMIC_USE_LINREG Controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature, if the PMIC fails to keep vccd above the internal regulator target, then the internal regulator will attempt to recover vccd. If the regulator current is too high, the regulator triggers an over-current detector (OCD) reset. 0: Internal Active Linear Regulator disabled after PMIC enabled. OCD is disabled.; 1: Internal Active Linear Regulator kept enabled. See datasheet for minimum PMIC vccd input to prevent OCD. [10:10] read-write PMIC_VADJ_BUF_EN Analog buffer enable on voltage adjust output. Write this bit depending on the type of PMIC connected: 0: Bypass buffer. This connects the resistor divider directly to the output pin. Use this setting for a PMIC with a high-impedance feedback input, such as those that support a resistor divider on the PCB. This setting can also be used with a low-impedance PMIC with PMIC_VREF=2'b11 (no scaling). 1: Use analog buffer. This enables an analog buffer between the resistor divider output and the pin. The buffer can drive a resistor divider on the PCB that feeds into the PMIC feedback input. This allows targeting a different PMIC reference voltage from PMIC_VREF choices, while still supporting voltage adjustment using the internal divider. [15:15] read-write PMIC_CTL_OUTEN Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin. [16:16] read-write PMIC_CTL_POLARITY Polarity used to enable the PMIC. The sequencer uses PMIC_CTL_POLARITY to enable the PMIC, and it uses the complement to disable the PMIC. [17:17] read-write PMIC_STATUS_INEN Input buffer enable for PMIC status input. Set this bit high to enable the input receiver. [18:18] read-write PMIC_STATUS_POLARITY The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value. [19:19] read-write PMIC_STATUS_WAIT Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us. [29:20] read-write PMIC_CONFIGURED Indicates the PMIC has been configured. This is used to know if PMIC should be enabled in response to a debug power up request. Do not change PMIC settings after this bit is set high. [31:31] read-write PWR_PMIC_STATUS PMIC Status Register 0x10C4 32 read-only 0x0 0x80001001 PMIC_ENABLED Indicates the state of the PMIC enable/disable sequencer. This bit is only valid when PMIC_SEQ_BUSY==0. 0: PMIC sequencer indicates PMIC is disabled. 1: PMIC sequencer indicates PMIC is enabled. [0:0] read-only PMIC_STATUS_OK Indicates the PMIC status is ok. This includes polarity adjustment according to PMIC_STATUS_POLARITY. 0: PMIC status is not ok or PMIC input buffer is disabled (PMIC_STATUS_INEN==0); 1: PMIC status input buffer is enabled and indicates ok [12:12] read-only PMIC_SEQ_BUSY Indicates the PMIC enable/disable sequencer is busy transitioning to/from PMIC. 0: Sequencer is not busy; 1: Sequencer is busy either enabling or disabling PMIC. [31:31] read-only PWR_PMIC_CTL2 PMIC Control Register 2 0x10C8 32 read-write 0x0 0x800000FF PMIC_STATUS_TIMEOUT Timeout while waiting for PMIC_STATUS_OK==1 when switching to PMIC. 0: disables timeout. Do not change this register after setting PWR_PMIC_CTL.PMIC_CONFIGURED. >0: enables timeout of PMIC_STATUS_TIMEOUT*128us (nominal, clocked by IMO). Timeout expiration generates a 'reset' condition that is only recorded in RES_CAUSE but does not trigger a reset for the SOC, however a WDT will reset the system with PMIC RES_CAUSE. [7:0] read-write PMIC_EN Enable PMIC. This bit will not set if PMIC_CONFIGURED==0. Use PWR_PMIC_STATUS.ENABLED to know the actual status of PMIC. It will differ from this bit in the following cases: A) Do not enter DEEPSLEEP while the sequencer is busy (see PWR_PMIC_STATUS.PMIC_SEQ_BUSY). The hardware sequencer disables PMIC during DEEPSLEEP entry and enables it upon wakeup. B) The debugger requests the chip remain powered up. Hardware prevents PMIC from disabling when this bit is cleared. Hardware does not automatically enable PMIC in response to debugger power up request. If this bit is low when the debugger deasserts the power up request, the hardware sequencer will disable PMIC. [31:31] read-write PWR_PMIC_CTL4 PMIC Control Register 4 0x10D0 32 read-write 0x0 0xC0000000 PMIC_VADJ_DIS Disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device. 0: Device generates VADJ when PMIC is enabled. This allows the feedback loop to compensate for voltage drops in the PCB and package. 1: Device does not generate VADJ, and it must not be part of the PMIC feedback loop. This reduces current by turning off the internal resistor divider that generates VADJ. [30:30] read-write PMIC_DPSLP Configures PMIC behavior during DEEPSLEEP. 0: Device operates from internal regulators during DEEPSLEEP. If PMIC is enabled at the beginning of the DEEPSLEEP transition, hardware changes to the internal regulators and disables the PMIC. 1: DEEPSLEEP transition does not change PMIC enable. [31:31] read-write PWR_HIB_WAKE_CTL Hibernate Wakeup Mask Register 0x10E0 32 read-write 0x0 0xE0FFFFFF HIB_WAKE_SRC When set, HIBERNATE will wakeup for the assigned source The number and assignment of wakeup sources are product-specific. [23:0] read-write HIB_WAKE_CSV_BAK When set, HIBERNATE will wakeup for CSV_BAK detection. [29:29] read-write HIB_WAKE_RTC When set, HIBERNATE will wakeup for a pending RTC interrupt. [30:30] read-write HIB_WAKE_WDT When set, HIBERNATE will wakeup for a pending WDT interrupt. [31:31] read-write PWR_HIB_WAKE_CTL2 Hibernate Wakeup Polarity Register 0x10E4 32 read-write 0x0 0xFFFFFF HIB_WAKE_SRC Each bit selects the polarity for the corresponding HIBERNATE wakeup source. The number and assignment of wakeup sources are product-specific. 0: Wakes when unmasked input is 0. 1: Wakes when unmasked input is 1. [23:0] read-write PWR_HIB_WAKE_CAUSE Hibernate Wakeup Cause Register 0x10EC 32 read-write 0x0 0xE0FFFFFF HIB_WAKE_SRC Each bit indicates a HIBERNATE wakeup cause. The number and assigment of wakeup sources are product-specific. For each bit, writing a 1 clears the cause flag. [23:0] read-write HIB_WAKE_CSV_BAK Indicates CSV_BAK wakeup cause. The related fault must be handled before this bit can be cleared. [29:29] read-write HIB_WAKE_RTC Indicates RTC wakeup cause. The RTC interrupt must be cleared before this bit can be cleared. [30:30] read-write HIB_WAKE_WDT Indicates WDT wakeup cause. The WDT interrupt must be cleared before this bit can be cleared. [31:31] read-write 16 4 CLK_PATH_SELECT[%s] Clock Path Select Register 0x1200 32 read-write 0x0 0x7 PATH_MUX Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [2:0] read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 LPECO LPECO - Low-Power External-Crystal Oscillator 5 16 4 CLK_ROOT_SELECT[%s] Clock Root Select Register 0x1240 32 read-write 0x0 0x8000013F ROOT_MUX Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [3:0] read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 ROOT_DIV Selects predivider value for this clock root and DSI input. This divider is after DIRECT_MUX. For products with DSI, the output of this mux is routed to DSI for use as a signal. For products with clock supervision, the output of this mux is the monitored clock for CSV_HF<k>. [5:4] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 DIRECT_MUX Direct selection mux that allows IMO to bypass most of the clock mux structure. For products with multiple regulators, this mux can be used to reduce current without requiring significant reconfiguration of the clocking network. The default value of HFCLK<0>==ROOT_MUX, and the default value for other clock trees is product-specific. [8:8] read-write IMO Select IMO 0 ROOT_MUX Select ROOT_MUX selection 1 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. [31:31] read-write CSV_HF Clock Supervisor (CSV) registers for Root clocks CSV_HF 0x00001400 14 16 CSV[%s] Active domain Clock Supervisor (CSV) registers CSV_HF_CSV 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0xC000FFFF STARTUP Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [15:0] read-write CSV_ACTION Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system). [30:30] read-write FAULT Do a Fault report. 0 RESET Cause a power reset. This should only be used for clk_hf0. 1 CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. A CSV error detection is reported to the Fault structure, or instead it can generate a power reset. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFFFFFFFF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [15:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [31:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFFFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [15:0] read-write CLK_SELECT Clock selection register 0x1500 32 read-write 0x0 0xFF07 LFCLK_SEL Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [2:0] read-write ILO0 ILO0 - Internal Low-speed Oscillator #0. 0 WCO WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). 1 ALTLF ALTLF - Alternate Low-Frequency Clock. Capability is product-specific 2 PILO PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. 3 ILO1 ILO1 - Internal Low-speed Oscillator #1, if present. 4 ECO_PRESCALER ECO_PRESCALER - External-Crystal Oscillator after prescaling, if present. Does not work in DEEPSLEEP or HIBERNATE modes. Intended for applications that operate in ACTIVE/SLEEP modes only. This option is only valid when ECO is present in the product. 5 LPECO_PRESCALER LPECO_PRESCALER - Low-Power External-Crystal Oscillator after prescaling, if present. This choice works in ACTIVE/SLEEP/DEEPSLEEP modes. This option is only valid when LPECO is present in the product. 6 PUMP_SEL N/A [11:8] read-write PUMP_DIV N/A [14:12] read-write NO_DIV N/A 0 DIV_BY_2 N/A 1 DIV_BY_4 N/A 2 DIV_BY_8 N/A 3 DIV_BY_16 N/A 4 PUMP_ENABLE N/A [15:15] read-write CLK_ILO0_CONFIG ILO0 Configuration 0x1508 32 read-write 0x80000000 0xC0000001 ILO0_BACKUP This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes. If backup voltage domain is implemented on the product, this bit also indicates if ILO0 should stay enabled through power-related resets on other supplies, e.g.. BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. This register is reset when the backup logic resets. 0: ILO0 turns off during XRES, HIBERNATE, and power-related resets. ILO0 configuration and trims are reset by these events. 1: ILO0 stays enabled, as described above. ILO0 configuration and trims are not reset by these events. [0:0] read-write ILO0_MON_ENABLE N/A [30:30] read-write ENABLE Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. HT-variant: This register will not clear unless PWR_CTL2.BGREF_LPMODE==0. After enabling, the first ILO0 cycle occurs within 12us and is +/-10 percent accuracy. Thereafter, ILO0 is +/-5 percent accurate. [31:31] read-write CLK_ILO1_CONFIG ILO1 Configuration 0x150C 32 read-write 0x0 0xC0000000 ILO1_MON_ENABLE N/A [30:30] read-write ENABLE Master enable for ILO1. HT-variant: After enabling, the first ILO1 cycle occurs within 12us and is +/-10 percent accuracy. Thereafter, ILO1 is +/-5 percent accurate. [31:31] read-write CLK_IMO_CONFIG IMO Configuration 0x1518 32 read-write 0x80000000 0x80000000 ENABLE Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP, HIBERNATE, and XRES. [31:31] read-write CLK_ECO_CONFIG ECO Configuration Register 0x151C 32 read-write 0x2 0x98000002 AGC_EN Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by CLK_ECO_CONFIG2.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. [1:1] read-write ECO_DIV_DISABLE ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE). SW sets this field to '1' and HW sets this field to '0'. HW sets ECO_DIV_DISABLE field to '0' immediately and HW sets CLK_ECO_PRESCALE.ECO_DIV_EN field to '0' immediately. [27:27] read-write ECO_DIV_ENABLE ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE). ECO Prescaler only works in ACTIVE and SLEEP modes. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled, its integer and fractional counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the ECO_DIV_DISABLE field. 1: Configure CLK_ECO_PRESCALE registers. 2: Enable the divider using the ECO_DIV_ENABLE field. HW sets the ECO_DIV_ENABLE field to '0' when the enabling is performed and HW set CLK_ECO_PRESCALER.ENABLED to '1' when the enabling is performed. [28:28] read-write ECO_EN Master enable for ECO oscillator. Configure the settings in CLK_ECO_CONFIG2 to work with the selected crystal, before enabling ECO. [31:31] read-write CLK_ECO_PRESCALE ECO Prescaler Configuration Register 0x1520 32 read-write 0x0 0x3FFFF01 ECO_DIV_ENABLED ECO prescaler enabled. HW sets this field to '1' as a result of an CLK_ECO_CONFIG.ECO_DIV_ENABLE command. HW sets this field to '0' as a result on a CLK_ECO_CONFIG.ECO_DIV_DISABLE command. [0:0] read-only ECO_FRAC_DIV 8-bit fractional value, sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when ECO Prescaler is enabled. [15:8] read-write ECO_INT_DIV 10-bit integer value allows for ECO frequencies up to 33.55MHz. Subtract one from the desired divide value when writing this field. For example, to divide by 1, write ECO_INT_DIV=0. Do not change this setting when ECO Prescaler is enabled. [25:16] read-write CLK_ECO_STATUS ECO Status Register 0x1524 32 read-only 0x0 0x3 ECO_OK Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. [0:0] read-only ECO_READY Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. [1:1] read-only CLK_PILO_CONFIG Precision ILO Configuration Register 0x1528 32 read-write 0x80 0xE00003FF PILO_FFREQ Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. [9:0] read-write PILO_CLK_EN Enable the PILO clock output. See PILO_EN field for required sequencing. [29:29] read-write PILO_RESET_N Reset the PILO. See PILO_EN field for required sequencing. [30:30] read-write PILO_EN Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. [31:31] read-write CLK_FLL_CONFIG FLL Configuration Register 0x1530 32 read-write 0x1000000 0x8103FFFF FLL_MULT Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) [17:0] read-write FLL_OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2 [24:24] read-write FLL_ENABLE Master enable for FLL. The FLL requires firmware sequencing when enabling and disabling. Hardware handles sequencing automatically when entering/exiting DEEPSLEEP. To enable the FLL, use the following sequence: 1) Configure FLL and CCO settings. Do not modify CLK_FLL_CONFIG3.BYPASS_SEL (must be AUTO) or CLK_FLL_CONFIG.FLL_ENABLE (must be 0). 2) Enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 3) Wait until CLK_FLL_STATUS.CCO_READY==1. 4) Ensure the reference clock has stabilized. 5) Write FLL_ENABLE=1. 6) Optionally wait until CLK_FLL_STATUS.LOCKED==1. The hardware automatically changes to the FLL output when LOCKED==1. To disable the FLL, use the following sequence: 1) Write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. 2) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional). 3) Wait at least ten cycles of either FLL reference clock or FLL output clock, whichever is slower. It is recommended to use a HW counter (e.g. clock calibration counter, event generator) running on the slower clock. 4) Disable FLL with FLL_ENABLE=0. 5) Disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. 6) Write CLK_FLL_CONFIG3.BYPASS_SEL=AUTO. 7) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional). 8) Wait three cycles of FLL reference clock. It is recommended to use a HW counter (e.g. clock calibration counter, event generator) running on the reference clock. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_CONFIG2 FLL Configuration Register 2 0x1534 32 read-write 0x20001 0xFFFF1FFF FLL_REF_DIV Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191 [12:0] read-write LOCK_TOL Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or allow less accuracy. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 255: tolerate error of 256 count values [23:16] read-write UPDATE_TOL Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings. The update tolerance is the allowed difference between the count value for the ideal formula and the measured value. UPDATE_TOL should be less than LOCK_TOL. [31:24] read-write CLK_FLL_CONFIG3 FLL Configuration Register 3 0x1538 32 read-write 0x2800 0x301FFFFF FLL_LF_IGAIN FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [3:0] read-write FLL_LF_PGAIN FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [7:4] read-write SETTLING_COUNT Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles [20:8] read-write BYPASS_SEL Bypass mux located just after FLL output. This register can be written while the FLL is enabled. When changing BYPASS_SEL, do not turn off the reference clock or CCO clock for five cycles (whichever is slower). In case of disabling FLL(FLL_ENABLE=0), additional five cycles are required. Refer to FLL disable sequence for more details in CLK_FLL_CONFIG->FLL_ENABLE. Whenever BYPASS_SEL is changed, it is required to read CLK_FLL_CONFIG3 to ensure the change takes effect. [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects FLL reference input (bypass mode). When locked, automatically selects FLL output. This can allow some processing to occur while the FLL is locking, such as after DEEPSLEEP wakeup. It is incompatible with clock supervision, because the frequency changes based on the lock signal. 0 LOCKED_OR_NOTHING Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. 1 FLL_REF Select FLL reference input (bypass mode). Ignores lock indicator 2 FLL_OUT Select FLL output. Ignores lock indicator. 3 CLK_FLL_CONFIG4 FLL Configuration Register 4 0x153C 32 read-write 0xFF 0xC1FF07FF CCO_LIMIT Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) [7:0] read-write CCO_RANGE Frequency range of CCO [10:8] read-write RANGE0 Target frequency is in range [48, 64) MHz 0 RANGE1 Target frequency is in range [64, 85) MHz 1 RANGE2 Target frequency is in range [85, 113) MHz 2 RANGE3 Target frequency is in range [113, 150) MHz 3 RANGE4 Target frequency is in range [150, 200] MHz 4 CCO_FREQ CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. [24:16] read-write CCO_HW_UPDATE_DIS Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. [30:30] read-write CCO_ENABLE Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_STATUS FLL Status Register 0x1540 32 read-write 0x0 0x7 LOCKED FLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the FLL is enabled and goes out of lock. This bit stays set until cleared by firmware. [1:1] read-write CCO_READY This indicates that the CCO is internally settled and ready to use. [2:2] read-only CLK_ECO_CONFIG2 ECO Configuration Register 2 0x1544 32 read-write 0x3 0x7FF7 WDTRIM Watch Dog Trim. Sets the minimum oscillation amplitude (Vp) for the crystal drive level. The minimum amplitude detector output is readable in CLK_ECO_STATUS.ECO_OK. 0x0: Vp > 0.05V 0x1: Vp > 0.10V 0x2: Vp > 0.15V 0x3: Vp > 0.20V 0x4: Vp > 0.25V 0x5: Vp > 0.30V 0x6: Vp > 0.35V 0x7: Vp > 0.40V [2:0] read-write ATRIM Amplitude trim. Sets maximum oscillation amplitude (Vp) to set the crystal drive level when ECO_CONFIG.AGC_EN=1. When AGC_EN=0, most values of this register are unused, except as noted. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0: Vp < 0.35V 0x1: Vp < 0.40V 0x2: Vp < 0.45V 0x3: Vp < 0.50V 0x4: Vp < 0.55V 0x5: Vp < 0.60V 0x6: Vp < 0.65V 0x7: Vp < 0.70V 0x8: Vp < 0.75V 0x9: Vp < 0.80V 0xA: Vp < 0.85V 0xB: Vp < 0.90V 0xC: Vp < 0.95V 0xD: Vp < 1.00V 0xE: Vp < 1.05V 0xF: Vp < 1.10V when AGC_EN=1. When AGC_EN=0, this setting enables maximum swing between vddd and vssd. [7:4] read-write FTRIM Filter Trim - 3rd harmonic oscillation [9:8] read-write RTRIM Feedback resistor Trim [11:10] read-write GTRIM Gain Trim - Startup time. [14:12] read-write 15 4 CLK_PLL_CONFIG[%s] PLL Configuration Register 0x1600 32 read-write 0x20116 0xBE1F1F7F FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) [6:0] read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) [12:8] read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) [20:16] read-write LOCK_DELAY N/A [26:25] read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) [27:27] read-write BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower). [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. If ENABLE=0, automatically selects PLL reference input. 0 LOCKED_OR_NOTHING Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. If ENABLE=0, no clock is output. 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. If ENABLE=0, no clock is output. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled. When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit. 1: Block is enabled [31:31] read-write 15 4 CLK_PLL_STATUS[%s] PLL Status Register 0x1640 32 read-write 0x0 0x3 LOCKED PLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. [1:1] read-write CSV_REF_SEL Select CSV Reference clock for Active domain 0x1700 32 read-write 0x0 0x7 REF_MUX Selects a source for clock clk_ref_hf. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [2:0] read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 CSV_REF CSV registers for the CSV Reference clock CSV_REF 0x00001710 CSV Active domain Clock Supervisor (CSV) registers for CSV Reference clock CSV_REF_CSV 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0xC000FFFF STARTUP Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [15:0] read-write CSV_ACTION Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system). [30:30] read-write FAULT Do a Fault report. 0 RESET Cause a power reset. This should only be used for clk_hf0. 1 CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. A CSV error detection is reported to the Fault structure, or instead it can generate a power reset. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFFFFFFFF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [15:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [31:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFFFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [15:0] read-write CSV_LF CSV registers for LF clock CSV_LF 0x00001720 CSV LF clock Clock Supervisor registers CSV_LF_CSV 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0x800001FF STARTUP Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [8:0] read-write CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot. A CSV error detection is reported to the Fault structure. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFF00FF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [7:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [23:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [7:0] read-write CSV_ILO CSV registers for HVILO clock CSV_ILO 0x00001730 CSV ILO0 clock DeepSleep domain Clock Supervisor registers CSV_ILO_CSV 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0x800001FF STARTUP Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [8:0] read-write CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot. A CSV error detection is reported to the Fault structure. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFF00FF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [7:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [23:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [7:0] read-write RES_CAUSE Reset Cause Observation Register 0x1800 32 read-write 0x40000000 0x77FF01FF RESET_WDT A basic WatchDog Timer (WDT) reset has occurred since last power cycle. ULP products: This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). For products that support high-voltage cause detection, this bit blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. [0:0] read-write RESET_ACT_FAULT Fault logging system requested a reset from its Active logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [1:1] read-write RESET_DPSLP_FAULT Fault logging system requested a reset from its DeepSleep logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [2:2] read-write RESET_TC_DBGRESET Test controller or debugger asserted reset. Only resets debug domain. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [3:3] read-write RESET_SOFT A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [4:4] read-write RESET_MCWDT0 Multi-Counter Watchdog timer reset #0. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [5:5] read-write RESET_MCWDT1 Multi-Counter Watchdog timer reset #1. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [6:6] read-write RESET_MCWDT2 Multi-Counter Watchdog timer reset #2. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [7:7] read-write RESET_MCWDT3 Multi-Counter Watchdog timer reset #3. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [8:8] read-write RESET_XRES External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. [16:16] read-write RESET_BODVDDD External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain information in the device. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [17:17] read-write RESET_BODVDDA External VDDA supply crossed the brown-out limit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [18:18] read-write RESET_BODVCCD Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions. Functional and timing supervision (CSV, WDT) is provided to create fully failsafe internal crash detection. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [19:19] read-write RESET_OVDVDDD Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [20:20] read-write RESET_OVDVDDA Overvoltage detection on the external VDDA supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [21:21] read-write RESET_OVDVCCD Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [22:22] read-write RESET_OCD_ACT_LINREG Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [23:23] read-write RESET_OCD_DPSLP_LINREG Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [24:24] read-write RESET_OCD_REGHC Overcurrent detection from REGHC (if present). REGHC_STATUS_TIMEOUT expiration will set this bit without issuing reset, which will be observed by a subsequent WDT reset. If REGHC is not present, hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [25:25] read-write RESET_PMIC PMIC status triggered a reset. PMIC_STATUS_TIMEOUT expiration will set this bit without issuing reset, which will be observed by a subsequent WDT reset. If PMIC control is not present, hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [26:26] read-write RESET_PXRES PXRES triggered. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. [28:28] read-write RESET_STRUCT_XRES Structural reset was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. [29:29] read-write RESET_PORVDDD Indicator that a POR occurred. This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes. [30:30] read-write RES_CAUSE2 Reset Cause Observation Register 2 0x1804 32 read-write 0x0 0x1FFFF RESET_CSV_HF Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. [15:0] read-write RESET_CSV_REF Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources. [16:16] read-write 5 16 CLK_PLL400M[%s] 400MHz PLL Configuration Register CLK_PLL400M 0x00001900 CONFIG 400MHz PLL Configuration Register 0x0 32 read-write 0x20116 0xB61F1FFF FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-15: illegal (undefined behavior) 16: divide by 16 ... 200: divide by 200 >200: illegal (undefined behavior) When using fractional mode, the jitter specs are met over the restricted range of 27 to 47, inclusive. [7:0] read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 16: divide by 16 others: illegal (undefined behavior) When using fractional mode, the jitter specs are met over the restricted range of 1 to 4, inclusive. [12:8] read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) [20:16] read-write LOCK_DELAY N/A [26:25] read-write BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower). [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. If ENABLE=0, automatically selects PLL reference input. 0 LOCKED_OR_NOTHING Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. If ENABLE=0, no clock is output. 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. If ENABLE=0, no clock is output. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. fOUT = (FEEDBACK_DIV + FRAC_EN*FRAC_DIV/2^24) * (fREF / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled. When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit. 1: Block is enabled [31:31] read-write CONFIG2 400MHz PLL Configuration Register 2 0x4 32 read-write 0x0 0xF0FFFFFF FRAC_DIV Control bits for fractional divider. This value is interpreted as a fraction of the PFD frequency, i.e. fPFD * (FRAC_DIV/2^24). This field can be dynamically updated within the 1000ppm control limit. It takes up to 115 AHB cycles to transfer the setting to the PLL, and writes that occur faster may be silently ignored and require the application to write again after the previous update has finished. Reading the register returns the accepted value. The PLL will start targeting the new value, but it may take significant time (milliseconds) to stabilize at the new average value. Do not change the FRAC_DIV setting while the PLL is initially locking. [23:0] read-write FRAC_DITHER_EN N/A [30:28] read-write FRAC_EN Enables fractional division mode. When using fractional division mode, see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement. [31:31] read-write CONFIG3 400MHz PLL Configuration Register 3 0x8 32 read-write 0x0 0x910703FF SSCG_DEPTH N/A [9:0] read-write SSCG_RATE N/A [18:16] read-write SSCG_DITHER_EN N/A [24:24] read-write SSCG_MODE N/A [28:28] read-write SSCG_EN Enables spreading mode. When using spreading, see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement. [31:31] read-write STATUS 400MHz PLL Status Register 0xC 32 read-write 0x0 0x3 LOCKED PLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. [1:1] read-write 15 32 CLK_DPLL400M[%s] 400MHz Digital PLL Configuration Register CLK_DPLL400M 0x00001A00 CONFIG 400MHz Digital PLL Configuration Register 0x0 32 read-write 0x20116 0xB61F1FFF FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-15: illegal (undefined behavior) 16: divide by 16 ... 200: divide by 200 >200: illegal (undefined behavior) When using fractional mode, the jitter specs are met over the restricted range of 27 to 47, inclusive. [7:0] read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 18: divide by 18 others: illegal (undefined behavior) When using fractional mode, the jitter specs are met over the restricted range of 1 to 4, inclusive. [12:8] read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) [20:16] read-write LOCK_DELAY N/A [26:25] read-write BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower). [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. If ENABLE=0, automatically selects PLL reference input. 0 LOCKED_OR_NOTHING Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. If ENABLE=0, no clock is output. 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. If ENABLE=0, no clock is output. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. fOUT = (FEEDBACK_DIV + FRAC_EN*FRAC_DIV/2^24) * (fREF / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled. When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit. 1: Block is enabled [31:31] read-write CONFIG2 400MHz Digital PLL Configuration Register 2 0x4 32 read-write 0x0 0xF0FFFFFF FRAC_DIV Control bits for fractional divider. This value is interpreted as a fraction of the PFD frequency, i.e. fPFD * (FRAC_DIV/2^24). This field can be dynamically updated within the 1000ppm control limit. It takes up to 115 AHB cycles to transfer the setting to the PLL, and writes that occur faster may be silently ignored and require the application to write again after the previous update has finished. Reading the register returns the accepted value. The PLL will start targeting the new value, but it may take significant time (milliseconds) to stabilize at the new average value. Do not change the FRAC_DIV setting while the PLL is initially locking. [23:0] read-write FRAC_DITHER_EN N/A [30:28] read-write FRAC_EN Enables fractional division mode. When using fractional division mode, see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement. [31:31] read-write CONFIG3 400MHz Digital PLL Configuration Register 3 0x8 32 read-write 0x0 0x910703FF SSCG_DEPTH N/A [9:0] read-write SSCG_RATE N/A [18:16] read-write SSCG_DITHER_EN N/A [24:24] read-write SSCG_MODE N/A [28:28] read-write SSCG_EN Enables spreading mode. When using spreading, see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement. [31:31] read-write STATUS 400MHz Digital PLL Status Register 0x10 32 read-write 0x0 0x3 LOCKED PLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. [1:1] read-write CLK_TRIM_ILO0_CTL ILO0 Trim Register 0x3014 32 read-write 0x52C 0xF3F ILO0_FTRIM ILO0 frequency trims. LSB step size is 1.5 percent (typical) of the frequency. [5:0] read-write ILO0_MONTRIM ILO0 internal monitor trim. [11:8] read-write PWR_TRIM_PWRSYS_CTL Power System Trim Register 0x3108 32 read-write 0x17 0x1F ACT_REG_TRIM Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: 5'h07: 900mV (nominal) 5'h17: 1100mV (nominal) [4:0] read-write ACT_REG_BOOST Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default); 100mA chip: 2'b00 (default); 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. [31:30] read-write CLK_TRIM_PILO_CTL PILO Trim Register 0x3114 32 read-write 0x108500F 0x7DFF703F PILO_CFREQ Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. [5:0] read-write PILO_OSC_TRIM Trim for current in oscillator block. [14:12] read-write PILO_COMP_TRIM Trim for comparator bias current. [17:16] read-write PILO_NBIAS_TRIM Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier [19:18] read-write PILO_RES_TRIM Trim for beta-multiplier branch current [24:20] read-write PILO_ISLOPE_TRIM Trim for beta-multiplier current slope [27:26] read-write PILO_VTDIFF_TRIM Trim for VT-DIFF output (internal power supply) [30:28] read-write CLK_TRIM_PILO_CTL2 PILO Trim Register 2 0x3118 32 read-write 0xDA10E0 0xFF1FFF PILO_VREF_TRIM Trim for voltage reference [7:0] read-write PILO_IREFBM_TRIM Trim for beta-multiplier current reference [12:8] read-write PILO_IREF_TRIM Trim for current reference [23:16] read-write CLK_TRIM_PILO_CTL3 PILO Trim Register 3 0x311C 32 read-write 0x4800 0xFFFF PILO_ENGOPT Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. [15:0] read-write CLK_TRIM_ILO1_CTL ILO1 Trim Register 0x3220 32 read-write 0x52C 0xF3F ILO1_FTRIM ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency. [5:0] read-write ILO1_MONTRIM ILO1 internal monitor trim. [11:8] read-write 3 256 MCWDT[%s] Multi-Counter Watchdog Timer MCWDT 0x00008000 2 32 CTR[%s] MCWDT Configuration for Subcounter 0 and 1 MCWDT_CTR 0x00000000 CTL MCWDT Subcounter Control Register 0x0 32 read-write 0x0 0x80000001 ENABLED Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles. [0:0] read-only ENABLE Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [31:31] read-write LOWER_LIMIT MCWDT Subcounter Lower Limit Register 0x4 32 read-write 0x0 0xFFFF LOWER_LIMIT Lower limit for this MCWDT subcounter. See LOWER_ACTION. [15:0] read-write UPPER_LIMIT MCWDT Subcounter Upper Limit Register 0x8 32 read-write 0x0 0xFFFF UPPER_LIMIT Upper limit for this MCWDT subcounter. See UPPER_ACTION. [15:0] read-write WARN_LIMIT MCWDT Subcounter Warn Limit Register 0xC 32 read-write 0x0 0xFFFF WARN_LIMIT Warn limit for this MCWDT subcounter. See WARN_ACTION. [15:0] read-write CONFIG MCWDT Subcounter Configuration Register 0x10 32 read-write 0x0 0xD0001133 LOWER_ACTION Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the corresponding processor is in SLEEPDEEP. [1:0] read-write NOTHING Do nothing 0 FAULT Trigger a fault. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager. For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. For LOWER_LIMIT == 0: No action is triggered. 1 FAULT_THEN_RESET Trigger a fault. Further, trigger a system-wide reset if the fault is not serviced and the watchdog is not cleared within 6 clk_lf cycles. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager, which gives at least 3 clk_lf cycles for software to respond. For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. For LOWER_LIMIT == 0: No action is triggered. 2 UPPER_ACTION Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached, regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected. [5:4] read-write NOTHING Do nothing 0 FAULT Trigger a fault. For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For UPPER_LIMIT < 2: The action may take up to one extra clk_lf cycle to trigger. 1 FAULT_THEN_RESET Trigger a fault. Further, trigger a system-wide reset if the fault is not serviced and the watchdog is not cleared within 6 clk_lf cycles. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager, which gives at least 3 clk_lf cycles for software to respond. For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For UPPER_LIMIT < 2: The action may take up to one extra clk_lf cycle to trigger. 2 WARN_ACTION Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically. For WARN_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For WARN_LIMIT == [0,1] : The action may take up to one extra clk_lf cycle to trigger. [8:8] read-write NOTHING Do nothing 0 INT Trigger an interrupt. 1 AUTO_SERVICE Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING. [12:12] read-write DEBUG_TRIGGER_EN Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT, and then set this bit. It takes up to two clk_lf cycles for the trigger signal to be processed. Triggers that are less than two clk_lf cycles may be missed. Synchronization errors can accumulate each time it is halted. 0: Pauses the counter whenever a debug probe is connected. 1: Pauses the counter whenever a debug probe is connected and the trigger input is high. [28:28] read-write SLEEPDEEP_PAUSE Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause, due to internal synchronization. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. 0: Counter runs normally regardless of processor mode. 1: Counter pauses when corresponding processor is in SLEEPDEEP. [30:30] read-write DEBUG_RUN Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause, due to internal synchronization. When (DEBUG_RUN==1 or DEBUG_TRIGGER_EN==0) and the debugger is connected for at least two clk_lf cycles, the LOWER_ACTION is ignored until after the first service after the debugger is disconnected. After the debugger is disconnected, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. If the debugger is disconnected before two clk_lf cycles, the LOWER_ACTION may or may not be ignored. 0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. 1: When debugger connected, counter increments normally, but reset generation is blocked. To block LOWER_ACTION fault generation, write DEBUG_TRIGGER_EN==0. [31:31] read-write CNT MCWDT Subcounter Count Register 0x14 32 read-write 0x0 0xFFFF CNT Current value of subcounter for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled.This register retains information during DeepSleep mode if SLEEPDEEP_PAUSE == 1. [15:0] read-write CPU_SELECT MCWDT CPU selection register 0x40 32 read-write 0x0 0x3 CPU_SEL Assigns this MCWDT to a CPU. This selects which CPU SLEEPDEEP signal is used for SLEEPDEEP_PAUSE. [1:0] read-write CTR2_CTL MCWDT Subcounter 2 Control register 0x80 32 read-write 0x0 0x80000001 ENABLED Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles. [0:0] read-only ENABLE Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [31:31] read-write CTR2_CONFIG MCWDT Subcounter 2 Configuration register 0x84 32 read-write 0x0 0xD01F0001 ACTION Action taken when the specified BIT toggles. Action will be triggered on the same edge where BITS to observe toggle. [0:0] read-write NOTHING Do nothing 0 INT Trigger an interrupt 1 BITS Bit to observe for a toggle: 0: Do ACTION after CNT[0] toggles (i.e. every tick) . 31: Do ACTION after CNT[31] toggles (i.e. every 2^31 ticks) [20:16] read-write DEBUG_TRIGGER_EN Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT, and then set this bit. It takes up to two clk_lf cycles for the trigger signal to be processed. Triggers that are less than two clk_lf cycles may be missed. Synchronization errors can accumulate each time it is halted. 0: Pauses the counter whenever a debug probe is connected. 1: Pauses the counter whenever a debug probe is connected and the trigger input is high. [28:28] read-write SLEEPDEEP_PAUSE Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause, due to internal synchronization. 0: Counter runs normally regardless of processor mode. 1: Counter pauses when corresponding processor is in SLEEPDEEP. [30:30] read-write DEBUG_RUN Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause and another two cycles to unpause, due to internal synchronization. 0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. 1: When debugger connected, counter increments normally, but reset generation is blocked. [31:31] read-write CTR2_CNT MCWDT Subcounter 2 Count Register 0x88 32 read-write 0x0 0xFFFFFFFF CNT2 Current value of subcounter 2 for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep mode if SLEEPDEEP_PAUSE == 1. [31:0] read-write LOCK MCWDT Lock Register 0x90 32 read-write 0x0 0x3 MCWDT_LOCK Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. [1:0] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 SERVICE MCWDT Service Register 0x94 32 read-write 0x0 0x3 CTR0_SERVICE Services subcounter 0. This resets the count value for subcounter 0 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending CTR0_SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write CTR0_SERVICE=1. If subcounter 0 is disabled, CTR0_SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. [0:0] read-write CTR1_SERVICE Services subcounter 1. This resets the count value for subcounter 1 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending CTR1_SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write CTR1_SERVICE=1. If subcounter 1 is disabled, CTR1_SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. [1:1] read-write INTR MCWDT Interrupt Register 0xA0 32 read-write 0x0 0x7 CTR0_INT MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. [0:0] read-write CTR1_INT MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. [1:1] read-write CTR2_INT MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. [2:2] read-write INTR_SET MCWDT Interrupt Set Register 0xA4 32 read-write 0x0 0x7 CTR0_INT Set interrupt for MCWDT_INT0 [0:0] read-write CTR1_INT Set interrupt for MCWDT_INT1 [1:1] read-write CTR2_INT Set interrupt for MCWDT_INT2 [2:2] read-write INTR_MASK MCWDT Interrupt Mask Register 0xA8 32 read-write 0x0 0x7 CTR0_INT Mask for sub-counter 0 for warning interrupt [0:0] read-write CTR1_INT Mask for sub-counter 1 for warning interrupt [1:1] read-write CTR2_INT Mask for sub-counter 2 [2:2] read-write INTR_MASKED MCWDT Interrupt Masked Register 0xAC 32 read-only 0x0 0x7 CTR0_INT Logical and of corresponding request and mask bits. [0:0] read-only CTR1_INT Logical and of corresponding request and mask bits. [1:1] read-only CTR2_INT Logical and of corresponding request and mask bits. [2:2] read-only WDT Watchdog Timer WDT 0x0000C000 CTL WDT Control Register 0x0 32 read-write 0x80000001 0x80000001 ENABLED Indicates actual state of watchdog. May lag ENABLE by up to three clk_ilo0 cycles. [0:0] read-only ENABLE Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE<>ENABLED. This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed. 0: Counter is disabled (not clocked). 1: Counter is enabled (counting up) [31:31] read-write LOWER_LIMIT WDT Lower Limit Register 0x4 32 read-write 0x0 0xFFFFFFFF LOWER_LIMIT Lower limit for watchdog. See LOWER_ACTION. [31:0] read-write UPPER_LIMIT WDT Upper Limit Register 0x8 32 read-write 0x8000 0xFFFFFFFF UPPER_LIMIT Upper limit for watchdog. See UPPER_ACTION. [31:0] read-write WARN_LIMIT WDT Warn Limit Register 0xC 32 read-write 0x0 0xFFFFFFFF WARN_LIMIT Warn limit for watchdog. See WARN_ACTION. [31:0] read-write CONFIG WDT Configuration Register 0x10 32 read-write 0x10 0xF0001111 LOWER_ACTION Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the chip is in DEEPSLEEP/HIBERNATE modes. For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. For LOWER_LIMIT == 0: No action is triggered. [0:0] read-write NOTHING Do nothing 0 RESET Trigger a reset. 1 UPPER_ACTION Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached, regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected. For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For UPPER_LIMIT < 2: The action may take up to one extra clk_ilo0 cycle to trigger. [4:4] read-write NOTHING Do nothing 0 RESET Trigger a reset. 1 WARN_ACTION Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically. For WARN_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For WARN_LIMIT < 2 : The action may take up to one extra clk_ilo0 cycle to trigger. [8:8] read-write NOTHING Do nothing 0 INT Trigger an interrupt. 1 AUTO_SERVICE Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING. [12:12] read-write DEBUG_TRIGGER_EN Enables the trigger input for WDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this WDT, and then set this bit. It takes up to two clk_ilo0 cycles for the trigger signal to be processed. Triggers that are less than two clk_ilo0 cycles may be missed. Synchronization error can accumulate each time it is halted. 0: Pauses the counter whenever a debug probe is connected. 1: Pauses the counter whenever a debug probe is connected and the trigger input is high. [28:28] read-write DPSLP_PAUSE Pauses/runs this counter when the system is in DEEPSLEEP. Note it may take up to two clk_ilo0 cycles for the counter to pause, due to internal synchronization. During DEEPSLEEP wakeup, the pause request is removed when clk_hf0 starts clocking, and then it may take up to two clk_ilo0 cycles for the counter to start. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. 0: Counter behaves normally during DEEPSLEEP. 1: Counter pauses during DEEPSLEEP. [29:29] read-write HIB_PAUSE Pauses/runs this counter when the system is in HIBERNATE. Note it may take up to two clk_ilo0 cycles for the counter to pause, due to internal synchronization. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. 0: Counter behaves normally during HIBERNATE. 1: Counter pauses during HIBERNATE. [30:30] read-write DEBUG_RUN Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_ilo0 cycles for the counter to pause and another two cycles to unpause, due to internal synchronization. If the debugger is connected for at least two clk_ilo0 cycles, the LOWER_ACTION is ignored until after the first service after the debugger is disconnected. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. If the debugger is disconnected before two clk_ilo0 cycles, the LOWER_ACTION may or may not be ignored. 0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. 1: When debugger connected, counter increments normally, but reset generation is blocked. [31:31] read-write CNT WDT Count Register 0x14 32 read-write 0x0 0xFFFFFFFF CNT Current value of subcounter for this WDT. This field may lag the actual count value by up to one clk_ilo0 cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep or Hiberbate mode if DPSLP_PAUSE == 1 or HIB_PAUSE == 1. [31:0] read-write LOCK WDT Lock register 0x40 32 read-write 0x3 0x3 WDT_LOCK Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. This register also locks the clk_ilo0 settings. [1:0] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 SERVICE WDT Service register 0x44 32 read-write 0x0 0x1 SERVICE Services the watchdog. This resets the count value to zero. This may take up to three clk_ilo0 cycle to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write SERVICE=1. If WDT is disabled, SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. [0:0] read-write INTR WDT Interrupt Register 0x50 32 read-write 0x0 0x1 WDT WDT Interrupt Request. This bit is set as configured by WDT action and limits. Due to internal synchronization, it takes up to 8 SYSCLK cycles to update after a W1C or reading this register and during this time AHB bus is stalled. [0:0] read-write INTR_SET WDT Interrupt Set Register 0x54 32 read-write 0x0 0x1 WDT Set interrupt. Due to internal synchronization, it takes up to 8 SYSCLK cycles to update after a W1S or reading from this register and during this time AHB bus is stalled. [0:0] read-write INTR_MASK WDT Interrupt Mask Register 0x58 32 read-write 0x0 0x1 WDT Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. [0:0] read-write INTR_MASKED WDT Interrupt Masked Register 0x5C 32 read-only 0x0 0x1 WDT Logical and of corresponding request and mask bits. Due to internal synchronization, it takes up to 8 SYSCLK cycles to read from this register. During this time AHB bus is stalled. [0:0] read-only BACKUP SRSS Backup Domain (ver3p3) 0x40270000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0xFF0F3308 WCO_EN Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. [3:3] read-write CLK_SEL Clock select for RTC clock [9:8] read-write WCO Watch-crystal oscillator input, available in Active, DeepSleep, Hibernate, and XRES. 0 ALTBAK This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is only available in Active and DeepSleep power modes. Note that LFCLK clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO or ILO is intended as the clock source then choose it directly instead of routing through LFCLK. 1 ILO Internal Low frequency Oscillator, available in Active, DeepSleep, Hibernate, and XRES. For Hibernate operation CLK_ILO_CONFIG. ILO_BACKUP must be set. If there are multiple ILO, this is ILO0. 2 LPECO_PRESCALER Low-power external crystal oscillator prescaler output, available in Active, DeepSleep, Hibernate, and XRES. 3 PRESCALER N/A [13:12] read-write WCO_BYPASS Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. [16:16] read-write VDDBAK_CTL Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. [18:17] read-write VBACKUP_MEAS Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. [19:19] read-write EN_CHARGE_KEY When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. [31:24] read-write RTC_RW RTC Read Write register 0x8 32 read-write 0x0 0x3 READ Read bit When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. [0:0] read-write WRITE Write bit Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. Only user RTC registers that were written to will get copied, others will not be affected. When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. [1:1] read-write CAL_CTL Oscillator calibration for absolute frequency 0xC 32 read-write 0x0 0xB003007F CALIB_VAL Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)) when CAL_COMP_PER_MIN is set at default value. Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) when CAL_COMP_PER_MIN is set at default value . Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments when CAL_COMP_PER_MIN is set at default value . [5:0] read-write CALIB_SIGN Calibration sign: 0= Negative sign: remove pulses (it takes more clock ticks to count one second) 1= Positive sign: add pulses (it takes less clock ticks to count one second) [6:6] read-write CAL_COMP_PER_MIN Select how many time calibration is performed per minute per step of 64 , each time a 64 step is added or substracted one unit 2/4/8/16*CALIB_VAL is substracted. [17:16] read-write 2 Calibration of 64 each is performed twice per minute for 2*CALIB_VAL per hour 0 4 Calibration of 64 each is performed four times per minute for 4*CALIB_VAL per hour 1 8 Calibration of 64 each is performed eight times per minute for 8*CALIB_VAL per hour 2 16 Ca6libration of 64 each is performed sixteen times per minute for 16*CALIB_VAL per hour 3 CAL_SEL Select calibration wave output signal [29:28] read-write CAL512 512Hz wave, not affected by calibration setting (not supported for 50/60Hz input clock: CTL.PRESCALER!=0) 0 RSVD N/A 1 CAL2 2Hz wave, includes the effect of the calibration setting, (not supported for 50/60Hz input clock: CTL.PRESCALER!=0) 2 CAL1 1Hz wave, includes the effect of the calibration setting (supported for all input clocks) 3 CAL_OUT Output enable for wave signal for calibration and allow CALIB_VAL to be written. [31:31] read-write STATUS Status 0x10 32 read-only 0x0 0x5 RTC_BUSY Pending RTC write [0:0] read-only WCO_OK Indicates that output has transitioned. [2:2] read-only RTC_TIME Calendar Seconds, Minutes, Hours, Day of Week 0x14 32 read-write 0x1000000 0x75F3F3F RTC_SEC Calendar seconds, 0-59 [5:0] read-write RTC_MIN Calendar minutes, 0-59 [13:8] read-write RTC_HOUR Calendar hours, value depending on 12/24HR mode 0=24HR: [20:16]=0-23 1=12HR: [20]:0=AM, 1=PM, [19:16]=1-12 [20:16] read-write CTRL_12HR Select 12/24HR mode: 1=12HR, 0=24HR [22:22] read-write RTC_DAY Calendar Day of the week, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write RTC_DATE Calendar Day of Month, Month, Year 0x18 32 read-write 0x101 0x7F0F1F RTC_DATE Calendar Day of the Month, 1-31 Automatic Leap Year Correction [4:0] read-write RTC_MON Calendar Month, 1-12 [11:8] read-write RTC_YEAR Calendar year, 0-99 [22:16] read-write ALM1_TIME Alarm 1 Seconds, Minute, Hours, Day of Week 0x1C 32 read-write 0x1000000 0x879FBFBF ALM_SEC Alarm seconds, 0-59 [5:0] read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match [7:7] read-write ALM_MIN Alarm minutes, 0-59 [13:8] read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match [15:15] read-write ALM_HOUR Alarm hours, value depending on 12/24HR mode 24HR: [4:0]=0-23 12HR: [4]:0=AM, 1=PM, [3:0]=1-12 [20:16] read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match [23:23] read-write ALM_DAY Alarm Day of the week, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match [31:31] read-write ALM1_DATE Alarm 1 Day of Month, Month 0x20 32 read-write 0x101 0x80008F9F ALM_DATE Alarm Day of the Month, 1-31 Leap Year corrected [4:0] read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match [7:7] read-write ALM_MON Alarm Month, 1-12 [11:8] read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match [15:15] read-write ALM_EN Master enable for alarm 1. 0: Alarm 1 is disabled. Fields for date and time are ignored. 1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. [31:31] read-write ALM2_TIME Alarm 2 Seconds, Minute, Hours, Day of Week 0x24 32 read-write 0x1000000 0x879FBFBF ALM_SEC Alarm seconds, 0-59 [5:0] read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match [7:7] read-write ALM_MIN Alarm minutes, 0-59 [13:8] read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match [15:15] read-write ALM_HOUR Alarm hours, value depending on 12/24HR mode 24HR: [4:0]=0-23 12HR: [4]:0=AM, 1=PM, [3:0]=1-12 [20:16] read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match [23:23] read-write ALM_DAY Alarm Day of the week, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match [31:31] read-write ALM2_DATE Alarm 2 Day of Month, Month 0x28 32 read-write 0x101 0x80008F9F ALM_DATE Alarm Day of the Month, 1-31 Leap Year corrected [4:0] read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match [7:7] read-write ALM_MON Alarm Month, 1-12 [11:8] read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match [15:15] read-write ALM_EN Master enable for alarm 2. 0: Alarm 2 is disabled. Fields for date and time are ignored. 1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. [31:31] read-write INTR Interrupt request register 0x2C 32 read-write 0x0 0x7 ALARM1 Alarm 1 Interrupt [0:0] read-write ALARM2 Alarm 2 Interrupt [1:1] read-write CENTURY Century overflow interrupt [2:2] read-write INTR_SET Interrupt set request register 0x30 32 read-write 0x0 0x7 ALARM1 Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write ALARM2 Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write CENTURY Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write INTR_MASK Interrupt mask register 0x34 32 read-write 0x0 0x7 ALARM1 Mask bit for corresponding bit in interrupt request register. [0:0] read-write ALARM2 Mask bit for corresponding bit in interrupt request register. [1:1] read-write CENTURY Mask bit for corresponding bit in interrupt request register. [2:2] read-write INTR_MASKED Interrupt masked request register 0x38 32 read-only 0x0 0x7 ALARM1 Logical and of corresponding request and mask bits. [0:0] read-only ALARM2 Logical and of corresponding request and mask bits. [1:1] read-only CENTURY Logical and of corresponding request and mask bits. [2:2] read-only PMIC_CTL PMIC control register 0x44 32 read-write 0xA0000000 0xE001FF00 UNLOCK This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. [15:8] read-write POLARITY N/A [16:16] read-write PMIC_EN_OUTEN Output enable for the output driver in the PMIC_EN pad. 0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present 1: Output pad is enabled for PMIC_EN pin. [29:29] read-write PMIC_ALWAYSEN Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. 0: Normal operation, PMIC_EN and PMIC_OUTEN work as described 1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. Note: This bit is a write-once bit until the next backup reset. [30:30] read-write PMIC_EN Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. [31:31] read-write RESET Backup reset register 0x48 32 read-write 0x0 0x80000000 RESET Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. [31:31] read-write LPECO_CTL Low-power external crystal oscillator control 0x80 32 read-write 0x40000000 0xD0001130 LPECO_CRANGE Specifies the load capacitance of the chosen crystal. 2'b00: load is in range [5pF, 10pF], 2'b01: load is in range (10pF, 15pF], 2'b10: load is in range (15pF, 20pF], 2'b11: load is in range (20pF, 25pF] [5:4] read-write LPECO_FRANGE Specifies the crystal frequency range. 0: Crystal frequency is in range [4, 6) MHz 1: Crystal frequency is in range [6, 8] MHz. Use this setting for 6 MHz. [8:8] read-write LPECO_AMP_SEL Selects the oscillation amplitude. WARNING: the crystal can be permanently damaged by selecting an amplitude that exceeds the crystal limits. 0: maximum amplitude is 1.35V. This is the lowest power setting. 1: maximum amplitude is 1.8V. This is the lowest jitter setting. [12:12] read-write LPECO_DIV_ENABLE LPECO prescaler enable. Do not set this to '1' when LPECO_EN==0. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled, its integer and fractional counters are initialized to '0'. HW sets the LPECO_DIV_ENABLE field to '0' when the enabling is performed and HW set CLK_LPECO_PRESCALER.ENABLED to '1' when the enabling is performed. [28:28] read-write LPECO_AMPDET_EN Minimum amplitude detector enable/disable. Ignored when LPECO_EN==0. 0: Initially enabled, and then automatically disabled when amplitude detector detects sufficient amplitude. 1: Keep minimum amplitude detector enabled as long as LPECO is enabled. [30:30] read-write LPECO_EN Master enable for LPECO oscillator. This also disables the LPECO prescaler. [31:31] read-write LPECO_PRESCALE Low-power external crystal oscillator prescaler 0x84 32 read-write 0x0 0x3FFFF01 LPECO_DIV_ENABLED LPECO prescaler enabled. HW sets this field to '1' as a result of an BACKUP_LPECO_CTL.LPECO_DIV_ENABLE. HW sets this field to '0' as a result of writing CLK_LPECO_CONFIG.LPECO_EN==0. This field does not update unless LPECO clock is toggling. [0:0] read-only LPECO_FRAC_DIV Fractional value, sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when LPECO Prescaler is enabled. [15:8] read-write LPECO_INT_DIV Integer divide value allows for LPECO frequencies up to 8MHz to generate 32768 Hz. Subtract one from the desired divide value when writing this field. For example, to divide by 1, write LPECO_INT_DIV=0. Do not change this setting when LPECO Prescaler is enabled. [25:16] read-write LPECO_STATUS Low-power external crystal oscillator status 0x88 32 read-only 0x0 0x3 LPECO_AMPDET_OK Indicates sufficient oscillation amplitude reported by LPECO amplitude detector. This field will read as zero when the amplitude detector is off (see LPECO_CTL.LPECO_AMPDET_EN). [0:0] read-only LPECO_READY Indicates the LPECO has had enough time to start. This field is driven by a stabilization counter clocked by IMO. [1:1] read-only CSV_BAK CSV registers for clk_bak clock 0x00000100 CSV clk_bak Backup domain Clock Supervisor registers 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0x800001FF STARTUP Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [8:0] read-write CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot. A CSV error detection is reported to the Fault structure. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFF00FF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [7:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [23:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [7:0] read-write 64 4 BREG[%s] Backup register region 0x1000 32 read-write 0x0 0xFFFFFFFF BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. [31:0] read-write DW0 Datawire Controller DW 0x40280000 0 65536 registers CTL Control 0x0 32 read-write 0x1 0x80000003 ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [0:0] read-write ECC_INJ_EN Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. [1:1] read-write ENABLED IP enable: '0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). '1': Enabled. [31:31] read-write STATUS Status 0x4 32 read-only 0x0 0xF0000000 P Active channel, user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS Active channel, secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only B Active channel, non-bufferable/bufferable access control: '0': non-bufferable '1': bufferable. [2:2] read-only PC Active channel protection context. [7:4] read-only PRIO Active channel priority. [9:8] read-only PREEMPTABLE Active channel preemptable. [11:11] read-only CH_IDX Active channel index. [24:16] read-only STATE State of the DW controller. '0': Default/inactive state. '1': Loading descriptor. '2': Loading data element from source location. '3': Storing data element to destination location. '4': CRC functionality (only used for CRC transfer descriptor type). '5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. '6': Error. [30:28] read-only ACTIVE Active channel present: '0': No. '1': Yes. [31:31] read-only ACT_DESCR_CTL Active descriptor control 0x20 32 read-only 0x0 0x0 DATA N/A [31:0] read-only ACT_DESCR_SRC Active descriptor source 0x24 32 read-only 0x0 0x0 DATA Copy of DESCR_SRC of the currently active descriptor. Base address of source location. [31:0] read-only ACT_DESCR_DST Active descriptor destination 0x28 32 read-only 0x0 0x0 DATA Copy of DESCR_DST of the currently active descriptor. Base address of destination location. Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes. [31:0] read-only ACT_DESCR_X_CTL Active descriptor X loop control 0x30 32 read-only 0x0 0x0 DATA Copy of DESCR_X_CTL of the currently active descriptor. [11:0] SRC_X_INCR Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. [23:12] DST_X_INCR Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. Note: this field is not used for CRC transfer descriptors and must be set to '0'. [31:24] X_COUNT Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. For a single transfer descriptor type, descriptor will not have X_CTL. [31:0] read-only ACT_DESCR_Y_CTL Active descriptor Y loop control 0x34 32 read-only 0x0 0x0 DATA Copy of DESCR_Y_CTL of the currently active descriptor. [11:0] SRC_Y_INCR Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. [23:12] DST_Y_INCR Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. [31:24] Y_COUNT Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL. [31:0] read-only ACT_DESCR_NEXT_PTR Active descriptor next pointer 0x38 32 read-only 0x0 0x0 ADDR Copy of DESCR_NEXT_PTR of the currently active descriptor. [31:2] ADDR Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. [31:2] read-only ACT_SRC Active source 0x40 32 read-only 0x0 0x0 SRC_ADDR Current address of source location. [31:0] read-only ACT_DST Active destination 0x44 32 read-only 0x0 0x0 DST_ADDR Current address of destination location. [31:0] read-only ECC_CTL ECC control 0x80 32 read-write 0x0 0xFE0003FF WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [9:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write CRC_CTL CRC control 0x100 32 read-write 0x0 0x101 DATA_REVERSE Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): '0': Most significant bit (bit 1) first. '1': Least significant bit (bit 0) first. [0:0] read-write REM_REVERSE Specifies whether the remainder is bit reversed (reversal is performed after XORing): '0': No. '1': Yes. [8:8] read-write CRC_DATA_CTL CRC data control 0x110 32 read-write 0x0 0xFF DATA_XOR Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. [7:0] read-write CRC_POL_CTL CRC polynomial control 0x120 32 read-write 0x0 0xFFFFFFFF POLYNOMIAL CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). [31:0] read-write CRC_LFSR_CTL CRC LFSR control 0x130 32 read-write 0x0 0xFFFFFFFF LFSR32 State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). [31:0] read-write CRC_REM_CTL CRC remainder control 0x140 32 read-write 0x0 0xFFFFFFFF REM_XOR Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. [31:0] read-write CRC_REM_RESULT CRC remainder result 0x148 32 read-only 0x0 0xFFFFFFFF REM Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: '0': the more significant bits (bit 31 and down) contain the remainder. '1': the less significant bits (bit 0 and up) contain the remainder. Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. [31:0] read-only 84 64 CH_STRUCT[%s] DW channel structure 0x00008000 CH_CTL Channel control 0x0 32 read-write 0x0 0x80000300 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). [9:8] read-write PREEMPTABLE Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. [11:11] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). [31:31] read-write CH_STATUS Channel status 0x4 32 read-only 0x0 0x80000000 INTR_CAUSE Specifies the source of the interrupt cause: '0': No interrupt generated '1': Interrupt based on transfer complettion configuration based on INTR_TYPE '2': Source transfer bus error '3': Destination transfer bus error '4': Source address misalignment '5': Destination address misalignment '6': Current descriptor pointer is null '7': Active channel is disabled '8': Descriptor bus error '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). [3:0] read-only PENDING Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). [31:31] read-only CH_IDX Channel current indices 0x8 32 read-write 0x0 0x0 X_IDX Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [7:0] read-write Y_IDX Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [15:8] read-write CH_CURR_PTR Channel current descriptor pointer 0xC 32 read-write 0x0 0x0 ADDR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. [31:2] read-write INTR Interrupt 0x10 32 read-write 0x0 0x1 CH Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. [0:0] read-write INTR_SET Interrupt set 0x14 32 read-write 0x0 0x1 CH Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt mask 0x18 32 read-write 0x0 0x1 CH Mask for corresponding field in INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0x1C 32 read-only 0x0 0x1 CH Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only SRAM_DATA0 SRAM data 0 0x20 32 read-write 0x0 0x0 DATA N/A [31:0] read-write SRAM_DATA1 SRAM data 1 0x24 32 read-write 0x0 0x0 DATA N/A [31:0] read-write TR_CMD Channel software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DW1 0x40290000 DMAC DMAC 0x402A0000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 ACTIVE Active channels 0x8 32 read-only 0x0 0xFF ACTIVE Specifies active channels; i.e. enabled channels whose trigger got activated. [7:0] read-only 8 256 CH[%s] DMA controller channel 0x00001000 CTL Channel control 0x0 32 read-write 0x2 0x800003F7 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. [9:8] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' when an error interrupt cause is activated. [31:31] read-write IDX Channel current indices 0x10 32 read-only 0x0 0x0 X Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor. [15:0] read-only Y Specifies the Y loop index, with Y_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor.. [31:16] read-only SRC Channel current source address 0x14 32 read-only 0x0 0x0 ADDR Current address of source location. [31:0] read-only DST Channel current destination address 0x18 32 read-only 0x0 0x0 ADDR Current address of destination location. [31:0] read-only CURR Channel current descriptor pointer 0x20 32 read-write 0x0 0x0 PTR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. [31:2] read-write TR_CMD Channle software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DESCR_STATUS Channel descriptor status 0x40 32 read-only 0x0 0x80000000 VALID Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. [31:31] read-only DESCR_CTL Channel descriptor control 0x60 32 read-only 0x0 0x0 WAIT_FOR_DEACT Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance. '0': Do not wait for trigger de-activation (for pulse sensitive triggers). '1': Wait for up to 4 cycles. '2': Wait for up to 16 cycles. '3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated. [1:0] read-only INTR_TYPE Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): '0': An interrupt is generated after a single transfer. '1': An interrupt is generated after a single 1D transfer or a memory copy transfer - If the descriptor type is 'single', the interrupt is generated after a single transfer. - If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer. - If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer. - If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer. '2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor). '3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. [3:2] read-only TR_OUT_TYPE Specifies when an output trigger is generated: '0': An output trigger is generated after a single transfer. '1': An output trigger is generated after a single 1D transfer or a memory copy transfer. - If the descriptor type is 'single', the output trigger is generated after a single transfer. - If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer. - If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer. - If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer. '2': An output trigger is generated after the execution of the current descriptor. '3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. [5:4] read-only TR_IN_TYPE Specifies the input trigger type (not to be confused with the descriptor type): '0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D. '1': A trigger results in the execution of a single 1D transfer. - If the descriptor type is 'single', the trigger results in the execution of a single transfer. - If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer. - If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer. - If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer. '2': A trigger results in the execution of the current descriptor. '3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information. [7:6] read-only DATA_PREFETCH Source data prefetch: '0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. '1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer. Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects. [8:8] read-only DATA_SIZE Specifies the data element size: '0': Byte (8 bits). '1': Halfword (16 bits). '2': Word (32 bits). DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: - DATA is 8 bit, SRC is 8 bit, DST is 8 bit. - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit. - DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0'). - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0'). - DATA is 16 bit, SRC is 16 bit, DST is 16 bit. - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit. - DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0'). - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0'). - DATA is 32 bit, SRC is 32 bit, DST is 32 bit. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type. [17:16] read-only CH_DISABLE Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): '0': Channel is not disabled. '1': Channel is disabled. [24:24] read-only SRC_TRANSFER_SIZE Specifies the bus transfer size to the source location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. [26:26] read-only DST_TRANSFER_SIZE Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. [27:27] read-only DESCR_TYPE Specifies the descriptor type (not to be confused with the trigger type): '0': Single transfer. The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c. '1': 1D transfer. The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14. '2': 2D transfer. The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c. '3': Memory copy. The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10. '4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. '5'-'7': Undefined. After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'. [30:28] read-only DESCR_SRC Channel descriptor source 0x64 32 read-only 0x0 0x0 ADDR Base address of source location. [31:0] read-only DESCR_DST Channel descriptor destination 0x68 32 read-only 0x0 0x0 ADDR Base address of destination location. [31:0] read-only DESCR_X_SIZE Channel descriptor X size 0x6C 32 read-only 0x0 0x0 X_COUNT Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed. [15:0] read-only DESCR_X_INCR Channel descriptor X increment 0x70 32 read-only 0x0 0x0 SRC_X Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. [15:0] read-only DST_X Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. [31:16] read-only DESCR_Y_SIZE Channel descriptor Y size 0x74 32 read-only 0x0 0x0 Y_COUNT Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. [15:0] read-only DESCR_Y_INCR Channel descriptor Y increment 0x78 32 read-only 0x0 0x0 SRC_Y Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. [15:0] read-only DST_Y Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. [31:16] read-only DESCR_NEXT Channel descriptor next pointer 0x7C 32 read-only 0x0 0x0 PTR Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. [31:2] read-only INTR Interrupt 0x80 32 read-write 0x0 0xFF COMPLETION Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. [0:0] read-write SRC_BUS_ERROR Activated (set to '1') on a bus error for a load from the source. [1:1] read-write DST_BUS_ERROR Activated (set to '1') on a bus error for a store to the destination. [2:2] read-write SRC_MISAL Activated (set to '1') on a misalignment of the source address. [3:3] read-write DST_MISAL Activated (set to '1') on a misalignment of the destination address. [4:4] read-write CURR_PTR_NULL Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. [5:5] read-write ACTIVE_CH_DISABLED Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. [6:6] read-write DESCR_BUS_ERROR Activated (set to '1') on a bus error for a load of the descriptor. [7:7] read-write INTR_SET Interrupt set 0x84 32 read-write 0x0 0xFF COMPLETION Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect). [0:0] read-write SRC_BUS_ERROR Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect). [1:1] read-write DST_BUS_ERROR Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect). [2:2] read-write SRC_MISAL Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect). [3:3] read-write DST_MISAL Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect). [4:4] read-write CURR_PTR_NULL Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect). [5:5] read-write ACTIVE_CH_DISABLED Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect). [6:6] read-write DESCR_BUS_ERROR Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect). [7:7] read-write INTR_MASK Interrupt mask 0x88 32 read-write 0x0 0xFF COMPLETION Mask for INTR.COMPLETION interrupt. [0:0] read-write SRC_BUS_ERROR Mask for INTR.SRC_BUS_ERROR interrupt. [1:1] read-write DST_BUS_ERROR Mask for INTR.DST_BUS_ERROR interrupt. [2:2] read-write SRC_MISAL Mask for INTR.SRC_MISAL interrupt. [3:3] read-write DST_MISAL Mask for INTR.DST_MISAL interrupt. [4:4] read-write CURR_PTR_NULL Mask for INTR.CURR_PTR_NULL interrupt. [5:5] read-write ACTIVE_CH_DISABLED Mask for INTR.ACTIVE_CH_DISABLED interrupt. [6:6] read-write DESCR_BUS_ERROR Mask for INTR.DESCR_BUS_ERROR interrupt. [7:7] read-write INTR_MASKED Interrupt masked 0x8C 32 read-only 0x0 0xFF COMPLETION Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields. [0:0] read-only SRC_BUS_ERROR Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields. [1:1] read-only DST_BUS_ERROR Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields. [2:2] read-only SRC_MISAL Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields. [3:3] read-only DST_MISAL Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields. [4:4] read-only CURR_PTR_NULL Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields. [5:5] read-only ACTIVE_CH_DISABLED Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields. [6:6] read-only DESCR_BUS_ERROR Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields. [7:7] read-only AXI_DMAC AXI DMAC 0x402B0000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. Clearing this field to '0' by software shuts down all channels by clearing their CH_CTL.ENABLED fields, unless all CH_STATUS.ENABLED fields are '0'. After all channels have completed their AXI transactions, all non-retention registers (command and status registers) are reset to their default value, and all retention registers retain their value. '1': Enabled. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 STATUS Enabled channels 0x4 32 read-only 0x0 0xFF CH_EN Specifies channels whose CH_STATUS.ENABLED = '1', i.e. channels that are either enabled, or are still completing their AXI transactions after being disabled. [7:0] read-only ACTIVE_SEC Active secure channels 0x8 32 read-only 0x0 0xFF ACTIVE Specifies active secure channels; i.e. enabled secure channels whose trigger got activated. The bits corresponding to non-secure channels are '0'. [7:0] read-only ACTIVE_NONSEC Active non-secure channels 0xC 32 read-only 0x0 0xFF ACTIVE Specifies active non-secure channels; i.e. enabled non-secure channels whose trigger got activated. The bits corresponding to secure channels are '0'. [7:0] read-only 4 256 CH[%s] AXI DMA controller channel 0x00001000 CTL Channel control 0x0 32 read-write 0x2 0x800003F7 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction ('hprot[1]') and not specified by the transaction write data. All transactions for this channel use the P field for the user/privileged access control ('aprot[0]). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction ('hprot[4]') and not specified by the transaction write data. All transactions for this channel use the NS field for the secure/non-secure access control ('aprot[1]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('acache[0]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). [9:8] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made active. If an active channel is disabled, the channel is de-activated: This field is set to '0' immediately, and CH_STATUS.ENABLED is set to '0' by HW after AXI bus transactions are completed. '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' in the following cases: - when an error interrupt cause is activated - when a descriptor has completed, if CH_DESCR_CTL.CH_DISABLE is '1' - when CTL.ENABLED is cleared to '0' by SW while the CH_STATUS.ENABLED field of at least one channel is '1' [31:31] read-write STATUS Channel status 0x4 32 read-only 0x0 0x80000000 ENABLED Indicates the enable status of the channel. '0': Disabled. '1': Enabled. When CH_CTL.ENABLED is set to '0' by SW or by the activation of an error interrupt cause or by disabling the entire DMAC, HW sets this field to '0' after the channel has completed AXI transactions. When SW sets CH_CTL.ENABLED to '1' and this field is '0', it changes from '0' to '1' immediately (if the entire DMAC is still disabled by CTL.ENABLED, it changes from '0' to '1' after the DMAC gets enabled). If this field is '1' at the time CH_CTL_ENABLED is changed from '0' to '1', then this field is first set to '0' by HW after the channel has completed AXI transactions, and it is set to '1' after one clock cycle if CH_CTL.ENABLED is still '1'. This ensures that the channel is properly initialized (except the retained registers). [31:31] read-only IDX Channel current X and Y indices 0x10 32 read-only 0x0 0x0 X Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor. [15:0] read-only Y Specifies the Y loop index. In the range of [0, Y_COUNT], with Y_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor.. [31:16] read-only SRC Channel current source address 0x14 32 read-only 0x0 0x0 ADDR Current address of source location. [31:0] read-only DST Channel current destination address 0x18 32 read-only 0x0 0x0 ADDR Current address of destination location. [31:0] read-only M_IDX Channel current M index 0x1C 32 read-only 0x0 0x0 M Specifies the M loop index. In the range of [0, M_COUNT], with M_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor. [23:0] read-only CURR Channel current descriptor pointer 0x20 32 read-write 0x0 0x0 PTR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: When this field is '0', and the DMAC and the channel are enabled, and the channel is triggered, then this will raise the CURR_PTR_NULL interrupt, and initiate the disabling of the channel. If this field is changed to a value different from '0' afterwards, then the channel may start to fetch the descriptor before finally being disabled, and the ISR will find this field not being '0' although the CURR_PTR_NULL interrupt has been raised. [31:3] read-write TR_CMD Channel software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DESCR_STATUS Channel descriptor status 0x40 32 read-only 0x0 0x80000000 VALID Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_M_SIZE, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. [31:31] read-only DESCR_CTL Channel descriptor control 0x50 32 read-only 0x0 0x0 WAIT_FOR_DEACT N/A [1:0] read-only INTR_TYPE N/A [3:2] read-only TR_OUT_TYPE N/A [5:4] read-only TR_IN_TYPE N/A [7:6] read-only DATA_PREFETCH N/A [8:8] read-only CH_DISABLE N/A [24:24] read-only DESCR_TYPE N/A [29:28] read-only DESCR_SRC Channel descriptor source 0x54 32 read-only 0x0 0x0 ADDR N/A [31:0] read-only DESCR_DST Channel descriptor destination 0x58 32 read-only 0x0 0x0 ADDR N/A [31:0] read-only DESCR_M_SIZE Channel descriptor M size 0x5C 32 read-only 0x0 0x0 M_COUNT N/A [23:0] read-only DESCR_X_SIZE Channel descriptor X size 0x60 32 read-only 0x0 0x0 X_COUNT N/A [15:0] read-only DESCR_X_INCR Channel descriptor X increment 0x64 32 read-only 0x0 0x0 SRC_X N/A [15:0] read-only DST_X N/A [31:16] read-only DESCR_Y_SIZE Channel descriptor Y size 0x68 32 read-only 0x0 0x0 Y_COUNT N/A [15:0] read-only DESCR_Y_INCR Channel descriptor Y increment 0x6C 32 read-only 0x0 0x0 SRC_Y N/A [15:0] read-only DST_Y N/A [31:16] read-only DESCR_NEXT Channel descriptor next pointer 0x70 32 read-only 0x0 0x0 PTR N/A [31:3] read-only INTR Interrupt 0x80 32 read-write 0x0 0xEF COMPLETION Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. [0:0] read-write SRC_BUS_ERROR Activated (set to '1') on a bus error for a load from the source. [1:1] read-write DST_BUS_ERROR Activated (set to '1') on a bus error for a store to the destination. Also activated when an AXI write response is received although there is no outstanding write transaction. [2:2] read-write INVALID_DESCR_TYPE Activated (set to '1') when the descriptor type is invalid. [3:3] read-write CURR_PTR_NULL Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1'), CH_CURR_PTR is '0', and the channel is triggered. [5:5] read-write ACTIVE_CH_DISABLED Activated (set to '1') when the channel is disabled and the data transfer engine is busy, i.e there is a pending trigger. This flag is also set if an input trigger is received at the same time another error occurs (in this case, ACT_CH_DISABLED is set in addition to another error interrupt flag). [6:6] read-write DESCR_BUS_ERROR Activated (set to '1') on a bus error for a load of the descriptor. [7:7] read-write INTR_SET Interrupt set 0x84 32 read-write 0x0 0xEF COMPLETION Write this field with '1' to set corresponding INTR field to '1' (a write of '0' has no effect). [0:0] read-write SRC_BUS_ERROR N/A [1:1] read-write DST_BUS_ERROR N/A [2:2] read-write INVALID_DESCR_TYPE N/A [3:3] read-write CURR_PTR_NULL N/A [5:5] read-write ACTIVE_CH_DISABLED N/A [6:6] read-write DESCR_BUS_ERROR N/A [7:7] read-write INTR_MASK Interrupt mask 0x88 32 read-write 0x0 0xEF COMPLETION Mask for corresponding field in INTR register. [0:0] read-write SRC_BUS_ERROR N/A [1:1] read-write DST_BUS_ERROR N/A [2:2] read-write INVALID_DESCR_TYPE N/A [3:3] read-write CURR_PTR_NULL N/A [5:5] read-write ACTIVE_CH_DISABLED N/A [6:6] read-write DESCR_BUS_ERROR N/A [7:7] read-write INTR_MASKED Interrupt masked 0x8C 32 read-only 0x0 0xEF COMPLETION Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only SRC_BUS_ERROR N/A [1:1] read-only DST_BUS_ERROR N/A [2:2] read-only INVALID_DESCR_TYPE N/A [3:3] read-only CURR_PTR_NULL N/A [5:5] read-only ACTIVE_CH_DISABLED N/A [6:6] read-only DESCR_BUS_ERROR N/A [7:7] read-only EFUSE EFUSE MXS40 registers 0x402C0000 0 512 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write TEST Test 0x4 32 read-write 0x1 0x3 MARG_READ Margin Read [1:0] read-write LOWR Low Resistance: -50 percent from nominal 0 DEFAULTR Nominal resistance (Default read condition) 1 HIGHR High Resistance: +50 percent from nominal 2 HIGHERR Higher Resistance: +100 percent from nominal 3 CMD Command 0x10 32 read-write 0x1 0x800F1F71 BIT_DATA Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. [0:0] read-write BIT_ADDR Bit address. This field specifies a bit within a Byte. [6:4] read-write BYTE_ADDR Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). [12:8] read-write MACRO_ADDR Macro address. This field specifies an eFUSE macro. [19:16] read-write START FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. [31:31] read-write SEQ_DEFAULT Sequencer Default value 0x20 32 read-write 0x1D0000 0x7F0000 STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write SEQ_READ_CTL_0 Sequencer read control 0 0x40 32 read-write 0x80560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_1 Sequencer read control 1 0x44 32 read-write 0x540004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_2 Sequencer read control 2 0x48 32 read-write 0x560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_3 Sequencer read control 3 0x4C 32 read-write 0x540003 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_4 Sequencer read control 4 0x50 32 read-write 0x80150001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_5 Sequencer read control 5 0x54 32 read-write 0x310004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_0 Sequencer program control 0 0x60 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_1 Sequencer program control 1 0x64 32 read-write 0x220020 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_2 Sequencer program control 2 0x68 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_3 Sequencer program control 3 0x6C 32 read-write 0x310005 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_4 Sequencer program control 4 0x70 32 read-write 0x80350006 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_5 Sequencer program control 5 0x74 32 read-write 0x803D0019 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write HSIOM High Speed IO Matrix (HSIOM) 0x40300000 0 16384 registers 31 16 PRT[%s] HSIOM port registers 0x00000000 PORT_SEL0 Port selection 0 0x0 32 read-write 0x0 0x1F1F1F1F IO0_SEL Selects connection for IO pin 0 route. [4:0] read-write GPIO GPIO controls 'out' 0 GPIO_DSI GPIO controls 'out', DSI controls 'output enable' 1 DSI_DSI DSI controls 'out' and 'output enable' 2 DSI_GPIO DSI controls 'out', GPIO controls 'output enable' 3 AMUXA Analog mux bus A 4 AMUXB Analog mux bus B 5 AMUXA_DSI Analog mux bus A, DSI control 6 AMUXB_DSI Analog mux bus B, DSI control 7 ACT_0 Active functionality 0 8 ACT_1 Active functionality 1 9 ACT_2 Active functionality 2 10 ACT_3 Active functionality 3 11 DS_0 DeepSleep functionality 0 12 DS_1 DeepSleep functionality 1 13 DS_2 DeepSleep functionality 2 14 DS_3 DeepSleep functionality 3 15 ACT_4 Active functionality 4 16 ACT_5 Active functionality 5 17 ACT_6 Active functionality 6 18 ACT_7 Active functionality 7 19 ACT_8 Active functionality 8 20 ACT_9 Active functionality 9 21 ACT_10 Active functionality 10 22 ACT_11 Active functionality 11 23 ACT_12 Active functionality 12 24 ACT_13 Active functionality 13 25 ACT_14 Active functionality 14 26 ACT_15 Active functionality 15 27 DS_4 DeepSleep functionality 4 28 DS_5 DeepSleep functionality 5 29 DS_6 DeepSleep functionality 6 30 DS_7 DeepSleep functionality 7 31 IO1_SEL Selects connection for IO pin 1 route. [12:8] read-write IO2_SEL Selects connection for IO pin 2 route. [20:16] read-write IO3_SEL Selects connection for IO pin 3 route. [28:24] read-write PORT_SEL1 Port selection 1 0x4 32 read-write 0x0 0x1F1F1F1F IO4_SEL Selects connection for IO pin 4 route. See PORT_SEL0 for connection details. [4:0] read-write IO5_SEL Selects connection for IO pin 5 route. [12:8] read-write IO6_SEL Selects connection for IO pin 6 route. [20:16] read-write IO7_SEL Selects connection for IO pin 7 route. [28:24] read-write 64 4 AMUX_SPLIT_CTL[%s] AMUX splitter cell control 0x2000 32 read-write 0x0 0x77 SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. [0:0] read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. [1:1] read-write SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. [2:2] read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. [4:4] read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. [5:5] read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. [6:6] read-write MONITOR_CTL_0 Power/Ground Monitor cell control 0 0x2200 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_1 Power/Ground Monitor cell control 1 0x2204 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_2 Power/Ground Monitor cell control 2 0x2208 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_3 Power/Ground Monitor cell control 3 0x220C 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write ALT_JTAG_EN Alternate JTAG IF selection register 0x2240 32 read-write 0x0 0x80000000 ENABLE Provides the selection for alternate JTAG IF connectivity. 0: Primary JTAG interface is selected 1: Secondary (alternate) JTAG interface is selected. This connectivity works ONLY in ACTIVE mode. [31:31] read-write GPIO GPIO port control/configuration 0x40310000 0 65536 registers 31 128 PRT[%s] GPIO port registers 0x00000000 OUT Port output data register 0x0 32 read-write 0x0 0xFF OUT0 IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' [0:0] read-write OUT1 IO output data for pin 1 [1:1] read-write OUT2 IO output data for pin 2 [2:2] read-write OUT3 IO output data for pin 3 [3:3] read-write OUT4 IO output data for pin 4 [4:4] read-write OUT5 IO output data for pin 5 [5:5] read-write OUT6 IO output data for pin 6 [6:6] read-write OUT7 IO output data for pin 7 [7:7] read-write OUT_CLR Port output data clear register 0x4 32 read-write 0x0 0xFF OUT0 IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'. [0:0] read-write OUT1 IO clear output for pin 1 [1:1] read-write OUT2 IO clear output for pin 2 [2:2] read-write OUT3 IO clear output for pin 3 [3:3] read-write OUT4 IO clear output for pin 4 [4:4] read-write OUT5 IO clear output for pin 5 [5:5] read-write OUT6 IO clear output for pin 6 [6:6] read-write OUT7 IO clear output for pin 7 [7:7] read-write OUT_SET Port output data set register 0x8 32 read-write 0x0 0xFF OUT0 IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'. [0:0] read-write OUT1 IO set output for pin 1 [1:1] read-write OUT2 IO set output for pin 2 [2:2] read-write OUT3 IO set output for pin 3 [3:3] read-write OUT4 IO set output for pin 4 [4:4] read-write OUT5 IO set output for pin 5 [5:5] read-write OUT6 IO set output for pin 6 [6:6] read-write OUT7 IO set output for pin 7 [7:7] read-write OUT_INV Port output data invert register 0xC 32 read-write 0x0 0xFF OUT0 IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0'). [0:0] read-write OUT1 IO invert output for pin 1 [1:1] read-write OUT2 IO invert output for pin 2 [2:2] read-write OUT3 IO invert output for pin 3 [3:3] read-write OUT4 IO invert output for pin 4 [4:4] read-write OUT5 IO invert output for pin 5 [5:5] read-write OUT6 IO invert output for pin 6 [6:6] read-write OUT7 IO invert output for pin 7 [7:7] read-write IN Port input state register 0x10 32 read-only 0x0 0x1FF IN0 IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. [0:0] read-only IN1 IO pin state for pin 1 [1:1] read-only IN2 IO pin state for pin 2 [2:2] read-only IN3 IO pin state for pin 3 [3:3] read-only IN4 IO pin state for pin 4 [4:4] read-only IN5 IO pin state for pin 5 [5:5] read-only IN6 IO pin state for pin 6 [6:6] read-only IN7 IO pin state for pin 7 [7:7] read-only FLT_IN Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. [8:8] read-only INTR Port interrupt status register 0x14 32 read-write 0x0 0x1FF01FF EDGE0 Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. [0:0] read-write EDGE1 Edge detect for IO pin 1 [1:1] read-write EDGE2 Edge detect for IO pin 2 [2:2] read-write EDGE3 Edge detect for IO pin 3 [3:3] read-write EDGE4 Edge detect for IO pin 4 [4:4] read-write EDGE5 Edge detect for IO pin 5 [5:5] read-write EDGE6 Edge detect for IO pin 6 [6:6] read-write EDGE7 Edge detect for IO pin 7 [7:7] read-write FLT_EDGE Edge detected on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write IN_IN0 IO pin state for pin 0 [16:16] read-only IN_IN1 IO pin state for pin 1 [17:17] read-only IN_IN2 IO pin state for pin 2 [18:18] read-only IN_IN3 IO pin state for pin 3 [19:19] read-only IN_IN4 IO pin state for pin 4 [20:20] read-only IN_IN5 IO pin state for pin 5 [21:21] read-only IN_IN6 IO pin state for pin 6 [22:22] read-only IN_IN7 IO pin state for pin 7 [23:23] read-only FLT_IN_IN Filtered pin state for pin selected by INTR_CFG.FLT_SEL [24:24] read-only INTR_MASK Port interrupt mask register 0x18 32 read-write 0x0 0x1FF EDGE0 Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled [0:0] read-write EDGE1 Masks edge interrupt on IO pin 1 [1:1] read-write EDGE2 Masks edge interrupt on IO pin 2 [2:2] read-write EDGE3 Masks edge interrupt on IO pin 3 [3:3] read-write EDGE4 Masks edge interrupt on IO pin 4 [4:4] read-write EDGE5 Masks edge interrupt on IO pin 5 [5:5] read-write EDGE6 Masks edge interrupt on IO pin 6 [6:6] read-write EDGE7 Masks edge interrupt on IO pin 7 [7:7] read-write FLT_EDGE Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_MASKED Port interrupt masked status register 0x1C 32 read-only 0x0 0x1FF EDGE0 Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [0:0] read-only EDGE1 Edge detected and masked on IO pin 1 [1:1] read-only EDGE2 Edge detected and masked on IO pin 2 [2:2] read-only EDGE3 Edge detected and masked on IO pin 3 [3:3] read-only EDGE4 Edge detected and masked on IO pin 4 [4:4] read-only EDGE5 Edge detected and masked on IO pin 5 [5:5] read-only EDGE6 Edge detected and masked on IO pin 6 [6:6] read-only EDGE7 Edge detected and masked on IO pin 7 [7:7] read-only FLT_EDGE Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-only INTR_SET Port interrupt set register 0x20 32 read-write 0x0 0x1FF EDGE0 Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set [0:0] read-write EDGE1 Sets edge detect interrupt for IO pin 1 [1:1] read-write EDGE2 Sets edge detect interrupt for IO pin 2 [2:2] read-write EDGE3 Sets edge detect interrupt for IO pin 3 [3:3] read-write EDGE4 Sets edge detect interrupt for IO pin 4 [4:4] read-write EDGE5 Sets edge detect interrupt for IO pin 5 [5:5] read-write EDGE6 Sets edge detect interrupt for IO pin 6 [6:6] read-write EDGE7 Sets edge detect interrupt for IO pin 7 [7:7] read-write FLT_EDGE Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_CFG Port interrupt configuration register 0x40 32 read-write 0x0 0x1FFFFF EDGE0_SEL Sets which edge will trigger an IRQ for IO pin 0 [1:0] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 EDGE1_SEL Sets which edge will trigger an IRQ for IO pin 1 [3:2] read-write EDGE2_SEL Sets which edge will trigger an IRQ for IO pin 2 [5:4] read-write EDGE3_SEL Sets which edge will trigger an IRQ for IO pin 3 [7:6] read-write EDGE4_SEL Sets which edge will trigger an IRQ for IO pin 4 [9:8] read-write EDGE5_SEL Sets which edge will trigger an IRQ for IO pin 5 [11:10] read-write EDGE6_SEL Sets which edge will trigger an IRQ for IO pin 6 [13:12] read-write EDGE7_SEL Sets which edge will trigger an IRQ for IO pin 7 [15:14] read-write FLT_EDGE_SEL Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 FLT_SEL Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. [20:18] read-write CFG Port configuration register 0x44 32 read-write 0x0 0xFFFFFFFF DRIVE_MODE0 The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. [2:0] read-write HIGHZ Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance 0 RSVD N/A 1 PULLUP Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up 2 PULLDOWN Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down 3 OD_DRIVESLOW Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 4 OD_DRIVESHIGH Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 5 STRONG Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 6 PULLUP_DOWN Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up 7 IN_EN0 Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled [3:3] read-write DRIVE_MODE1 The GPIO drive mode for IO pin 1 [6:4] read-write IN_EN1 Enables the input buffer for IO pin 1 [7:7] read-write DRIVE_MODE2 The GPIO drive mode for IO pin 2 [10:8] read-write IN_EN2 Enables the input buffer for IO pin 2 [11:11] read-write DRIVE_MODE3 The GPIO drive mode for IO pin 3 [14:12] read-write IN_EN3 Enables the input buffer for IO pin 3 [15:15] read-write DRIVE_MODE4 The GPIO drive mode for IO pin4 [18:16] read-write IN_EN4 Enables the input buffer for IO pin 4 [19:19] read-write DRIVE_MODE5 The GPIO drive mode for IO pin 5 [22:20] read-write IN_EN5 Enables the input buffer for IO pin 5 [23:23] read-write DRIVE_MODE6 The GPIO drive mode for IO pin 6 [26:24] read-write IN_EN6 Enables the input buffer for IO pin 6 [27:27] read-write DRIVE_MODE7 The GPIO drive mode for IO pin 7 [30:28] read-write IN_EN7 Enables the input buffer for IO pin 7 [31:31] read-write CFG_IN Port input buffer configuration register 0x48 32 read-write 0x0 0xFF VTRIP_SEL0_0 Configures the pin 0 input buffer mode (trip points and hysteresis) [0:0] read-write CMOS S40S: Input buffer compatible with CMOS and I2C interfaces 0 TTL S40S: Input buffer compatible with TTL and MediaLB interfaces 1 VTRIP_SEL1_0 Configures the pin 1 input buffer mode (trip points and hysteresis) [1:1] read-write VTRIP_SEL2_0 Configures the pin 2 input buffer mode (trip points and hysteresis) [2:2] read-write VTRIP_SEL3_0 Configures the pin 3 input buffer mode (trip points and hysteresis) [3:3] read-write VTRIP_SEL4_0 Configures the pin 4 input buffer mode (trip points and hysteresis) [4:4] read-write VTRIP_SEL5_0 Configures the pin 5 input buffer mode (trip points and hysteresis) [5:5] read-write VTRIP_SEL6_0 Configures the pin 6 input buffer mode (trip points and hysteresis) [6:6] read-write VTRIP_SEL7_0 Configures the pin 7 input buffer mode (trip points and hysteresis) [7:7] read-write CFG_OUT Port output buffer configuration register 0x4C 32 read-write 0x0 0xFFFF00FF SLOW0 Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate [0:0] read-write SLOW1 Enables slow slew rate for IO pin 1 [1:1] read-write SLOW2 Enables slow slew rate for IO pin 2 [2:2] read-write SLOW3 Enables slow slew rate for IO pin 3 [3:3] read-write SLOW4 Enables slow slew rate for IO pin 4 [4:4] read-write SLOW5 Enables slow slew rate for IO pin 5 [5:5] read-write SLOW6 Enables slow slew rate for IO pin 6 [6:6] read-write SLOW7 Enables slow slew rate for IO pin 7 [7:7] read-write DRIVE_SEL0 Sets the GPIO drive strength for IO pin 0 [17:16] read-write DRIVE_SEL_ZERO Please refer to architecture TRM section I/O System 0 DRIVE_SEL_ONE Please refer to architecture TRM section I/O System 1 DRIVE_SEL_TWO Please refer to architecture TRM section I/O System 2 DRIVE_SEL_THREE Please refer to architecture TRM section I/O System 3 DRIVE_SEL1 Sets the GPIO drive strength for IO pin 1 [19:18] read-write DRIVE_SEL2 Sets the GPIO drive strength for IO pin 2 [21:20] read-write DRIVE_SEL3 Sets the GPIO drive strength for IO pin 3 [23:22] read-write DRIVE_SEL4 Sets the GPIO drive strength for IO pin 4 [25:24] read-write DRIVE_SEL5 Sets the GPIO drive strength for IO pin 5 [27:26] read-write DRIVE_SEL6 Sets the GPIO drive strength for IO pin 6 [29:28] read-write DRIVE_SEL7 Sets the GPIO drive strength for IO pin 7 [31:30] read-write CFG_SIO Port SIO configuration register 0x50 32 read-write 0x0 0xFFFFFFFF VREG_EN01 Selects the output buffer mode: '0': Unregulated output buffer '1': Regulated output buffer The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. [0:0] read-write IBUF_SEL01 Selects the input buffer mode: 0: Singled ended input buffer 1: Differential input buffer [1:1] read-write VTRIP_SEL01 Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): '0': Input buffer functions as a CMOS input buffer. '1': Input buffer functions as a TTL input buffer. In differential input buffer mode (IBUF_SEL = '1') '0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) '1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) [2:2] read-write VREF_SEL01 Selects reference voltage (Vref) trip-point of the input buffer: '0': Trip-point reference from pin_ref '1': Trip-point reference of SRSS internal reference Vref (1.2 V) '2': Trip-point reference of AMUXBUS_A '3': Trip-point reference of AMUXBUS_B [4:3] read-write VOH_SEL01 Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). '0': Voh = 1*reference; e.g. reference at 1.2V -> Voh = 1.2V '1': Voh = 1.25*reference; e.g. reference at 1.2V -> Voh = 1.5V '2': Voh = 1.49*reference; e.g. reference at 1.2V -> Voh = ~1.8V '3': Voh = 1.67*reference; e.g. reference at 1.2V -> Voh = 2V '4': Voh = 2.08*reference; e.g. reference at 1.2V -> Voh = 2.5V '5': Voh = 2.5*reference; e.g. reference at 1.2V -> Voh = 3V '6': Voh = 2.78*reference; e.g. reference at 1.2V -> Voh = ~3.3V '7': Voh = 4.16*reference; e.g. reference at 1.2V -> Voh = 5.0V Note: The upper value on Voh is limited to Vddio - 400mV [7:5] read-write VREG_EN23 See corresponding definition for IO pins 0 and 1 [8:8] read-write IBUF_SEL23 See corresponding definition for IO pins 0 and 1 [9:9] read-write VTRIP_SEL23 See corresponding definition for IO pins 0 and 1 [10:10] read-write VREF_SEL23 See corresponding definition for IO pins 0 and 1 [12:11] read-write VOH_SEL23 See corresponding definition for IO pins 0 and 1 [15:13] read-write VREG_EN45 See corresponding definition for IO pins 0 and 1 [16:16] read-write IBUF_SEL45 See corresponding definition for IO pins 0 and 1 [17:17] read-write VTRIP_SEL45 See corresponding definition for IO pins 0 and 1 [18:18] read-write VREF_SEL45 See corresponding definition for IO pins 0 and 1 [20:19] read-write VOH_SEL45 See corresponding definition for IO pins 0 and 1 [23:21] read-write VREG_EN67 See corresponding definition for IO pins 0 and 1 [24:24] read-write IBUF_SEL67 See corresponding definition for IO pins 0 and 1 [25:25] read-write VTRIP_SEL67 See corresponding definition for IO pins 0 and 1 [26:26] read-write VREF_SEL67 See corresponding definition for IO pins 0 and 1 [28:27] read-write VOH_SEL67 See corresponding definition for IO pins 0 and 1 [31:29] read-write CFG_IN_AUTOLVL Port input buffer AUTOLVL configuration register 0x58 32 read-write 0x0 0xFF VTRIP_SEL0_1 Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: {CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: 0,0: CMOS 0,1: TTL 1,0: input buffer is compatible with automotive. 1,1: input buffer is compatible with automotive. [0:0] read-write CMOS_OR_TTL Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. 0 AUTO Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. 1 VTRIP_SEL1_1 Input buffer compatible with automotive (elevated Vil) interfaces. [1:1] read-write VTRIP_SEL2_1 Input buffer compatible with automotive (elevated Vil) interfaces. [2:2] read-write VTRIP_SEL3_1 Input buffer compatible with automotive (elevated Vil) interfaces. [3:3] read-write VTRIP_SEL4_1 Input buffer compatible with automotive (elevated Vil) interfaces. [4:4] read-write VTRIP_SEL5_1 Input buffer compatible with automotive (elevated Vil) interfaces. [5:5] read-write VTRIP_SEL6_1 Input buffer compatible with automotive (elevated Vil) interfaces. [6:6] read-write VTRIP_SEL7_1 Input buffer compatible with automotive (elevated Vil) interfaces. [7:7] read-write CFG_OUT2 Port output buffer configuration register 2 0x60 32 read-write 0x0 0xFFFFFF DS_TRIM0 Sets the Drive Select Trim for IO pin 0 0 - Default (50ohms) 1 - 120ohms 2 - 90ohms 3 - 60ohms 4 - 50ohms 5 - 30ohms 6 - 20ohms 7 - 15ohms [2:0] read-write DEFAULT N/A 0 DS_120OHM N/A 1 DS_90OHM N/A 2 DS_60OHM N/A 3 DS_50OHM N/A 4 DS_30OHM N/A 5 DS_20OHM N/A 6 DS_15OHM N/A 7 DS_TRIM1 Sets the Drive Select Trim for IO pin 1 [5:3] read-write DS_TRIM2 Sets the Drive Select Trim for IO pin 2 [8:6] read-write DS_TRIM3 Sets the Drive Select Trim for IO pin 3 [11:9] read-write DS_TRIM4 Sets the Drive Select Trim for IO pin 4 [14:12] read-write DS_TRIM5 Sets the Drive Select Trim for IO pin 5 [17:15] read-write DS_TRIM6 Sets the Drive Select Trim for IO pin 6 [20:18] read-write DS_TRIM7 Sets the Drive Select Trim for IO pin 7 [23:21] read-write CFG_SLEW_EXT Port output buffer slew extension configuration register 0x64 32 read-write 0x0 0x77777777 SLEW0 Enables slow slew rate for IO pin 0 HSIO_STDLN: slew_ctl[SLEW_WIDTH] = All 0s: Fastest slew rate slew_ctl[SLEW_WIDTH] = All 1s: Slowest slew rate HSIO_ENH: slew_sel[SLEW_WIDTH] = All 0s: Fastest slew rate slew_sel[SLEW_WIDTH] = All 1s: Slowest slew rate [2:0] read-write SLEW1 Slew rate for IO pin 1 [6:4] read-write SLEW2 Slew rate for IO pin 2 [10:8] read-write SLEW3 Slew rate for IO pin 3 [14:12] read-write SLEW4 Slew rate for IO pin 4 [18:16] read-write SLEW5 Slew rate for IO pin 5 [22:20] read-write SLEW6 Slew rate for IO pin 6 [26:24] read-write SLEW7 Slew rate for IO pin 7 [30:28] read-write CFG_DRIVE_EXT0 Port output buffer drive sel extension configuration register 0x68 32 read-write 0x0 0x1F1F1F1F DRIVE_SEL_EXT0 Sets the GPIO drive strength for IO pin 0 [4:0] read-write DRIVE_SEL_EXT1 Sets the GPIO drive strength for IO pin 1 [12:8] read-write DRIVE_SEL_EXT2 Sets the GPIO drive strength for IO pin 2 [20:16] read-write DRIVE_SEL_EXT3 Sets the GPIO drive strength for IO pin 3 [28:24] read-write CFG_DRIVE_EXT1 Port output buffer drive sel extension configuration register 0x6C 32 read-write 0x0 0x1F1F1F1F DRIVE_SEL_EXT4 Sets the GPIO drive strength for IO pin 4 [4:0] read-write DRIVE_SEL_EXT5 Sets the GPIO drive strength for IO pin 5 [12:8] read-write DRIVE_SEL_EXT6 Sets the GPIO drive strength for IO pin 6 [20:16] read-write DRIVE_SEL_EXT7 Sets the GPIO drive strength for IO pin 7 [28:24] read-write INTR_CAUSE0 Interrupt port cause register 0 0x4000 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE1 Interrupt port cause register 1 0x4004 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE2 Interrupt port cause register 2 0x4008 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE3 Interrupt port cause register 3 0x400C 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only VDD_ACTIVE Extern power supply detection register 0x4010 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. '0': Supply is not present '1': Supply is present When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: 0: vbackup, 1: vddio_0, 2: vddio_1, 3: vddio_a, 4: vddio_r, 5: vddusb' [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) [31:31] read-only VDD_INTR Supply detection interrupt register 0x4014 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Supply state change detected. '0': No change to supply detected '1': Change to supply detected [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. [31:31] read-write VDD_INTR_MASK Supply detection interrupt mask register 0x4018 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Masks supply interrupt on VDDIO. '0': VDDIO interrupt forwarding disabled '1': VDDIO interrupt forwarding enabled [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write VDD_INTR_MASKED Supply detection interrupt masked register 0x401C 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Supply transition detected AND masked '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-only VDD_INTR_SET Supply detection interrupt set register 0x4020 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Sets supply interrupt. '0': Interrupt state not affected '1': Interrupt set [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write VDD_LVL External power supply level register 0x4024 32 read-only 0x0 0xFFFF VDDIO_LVL The VDD_LVL circuit detects the VDDIO supply level and writes the detected value in this register. '0' indicates the VDDIO supply is at 1.2V and '1' indicates VDDIO supply is at 1.8V. [15:0] read-only SMARTIO Programmable IO configuration 0x40320000 0 65536 registers 8 256 PRT[%s] Programmable IO port registers 0x00000000 CTL Control register 0x0 32 read-write 0x2001400 0x82001F00 BYPASS Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. '0': No bypass (programmable SMARTIO fabric is exposed). '1': Bypass (programmable SMARTIOIO fabric is hidden). [7:0] read-write CLOCK_SRC Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: '0': io_data_in[0]/'1'. ... '7': io_data_in[7]/'1'. '8': chip_data[0]/'1'. ... '15': chip_data[7]/'1'. '16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. '19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. '20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. '31': asynchronous mode/'1'. Select this when clockless operation is configured. NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. [12:8] read-write HLD_OVR IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: '0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). '1': The SMARTIO controls the IO cel hold override functionality: - In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. - In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). [24:24] read-write PIPELINE_EN Enable for pipeline register: '0': Disabled (register is bypassed). '1': Enabled. [25:25] read-write ENABLED Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: '0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. If the IP is disabled: - The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. - The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. '1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. [31:31] read-write SYNC_CTL Synchronization control register 0x10 32 read-write 0x0 0x0 IO_SYNC_EN Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. '0': No synchronization. '1': Synchronization. [7:0] read-write CHIP_SYNC_EN Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. '0': No synchronization. '1': Synchronization. [15:8] read-write 8 4 LUT_SEL[%s] LUT component input selection 0x20 32 read-write 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). [3:0] read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). [11:8] read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. [19:16] read-write 8 4 LUT_CTL[%s] LUT component control register 0x40 32 read-write 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). [7:0] read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable & (tr1_in ^ LUT[2]) & LUT[3]. clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' [9:8] read-write DU_SEL Data unit component input selection 0xC0 32 read-write 0x0 0x0 DU_TR0_SEL Data unit input signal 'tr0_in' source selection: '0': Constant '0'. '1': Constant '1'. '2': Data unit output. '10-3': LUT 7 - 0 outputs. Otherwise: Undefined. [3:0] read-write DU_TR1_SEL Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. [11:8] read-write DU_TR2_SEL Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. [19:16] read-write DU_DATA0_SEL Data unit input data 'data0_in' source selection: '0': Constant '0'. '1': chip_data[7:0]. '2': io_data_in[7:0]. '3': DATA.DATA MMIO register field. [25:24] read-write DU_DATA1_SEL Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. [29:28] read-write DU_CTL Data unit component control register 0xC4 32 read-write 0x0 0x0 DU_SIZE Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. [2:0] read-write DU_OPC Data unit opcode specifies the data unit operation: '1': INCR '2': DECR '3': INCR_WRAP '4': DECR_WRAP '5': INCR_DECR '6': INCR_DECR_WRAP '7': ROR '8': SHR '9': AND_OR '10': SHR_MAJ3 '11': SHR_EQL. Otherwise: Undefined. [11:8] read-write DATA Data register 0xF0 32 read-write 0x0 0x0 DATA Data unit input data source. [7:0] read-write TCPWM0 Timer/Counter/PWM TCPWM 0x40380000 0 131072 registers 3 32768 GRP[%s] Group of counters 0x00000000 38 128 CNT[%s] Timer/Counter/PWM Counter Module 0x00000000 CTRL Counter control register 0x0 32 read-write 0xF0 0xC73737FF AUTO_RELOAD_CC0 Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. Timer, QUAD, SR modes: '0': never switch. '1': switch on a compare match 0 event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. [0:0] read-write AUTO_RELOAD_CC1 Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. Timer, QUAD, SR modes: '0': never switch. '1': switch on a compare match 1 event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. [1:1] read-write AUTO_RELOAD_PERIOD Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event. In QUAD mode, QUAD_RANGE0_CMP range mode this field is used to select the index / wrap-around capture function. '0': Captures on index (reload) event. The counter value is copied to the PERIOD register on an index (reload) event. '1': Captures when COUNTER equals 0 or 0xffff. The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff. [2:2] read-write AUTO_RELOAD_LINE_SEL Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event. [3:3] read-write CC0_MATCH_UP_EN Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. '0': compare match 0 event generation disabled when counting up '1': compare match 0 event generation enabled when counting up This field has a function in PWM and PWM_DT modes only. [4:4] read-write CC0_MATCH_DOWN_EN Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. '0': compare match 0 event generation disabled when counting down '1': compare match 0 event generation enabled when counting down This field has a function in PWM and PWM_DT modes only. [5:5] read-write CC1_MATCH_UP_EN Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. '0': compare match 1 event generation disabled when counting up '1': compare match 1 event generation enabled when counting up This field has a function in PWM and PWM_DT modes only. [6:6] read-write CC1_MATCH_DOWN_EN Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. '0': compare match 1 event generation disabled when counting down '1': compare match 1 event generation enabled when counting down This field has a function in PWM and PWM_DT modes only. [7:7] read-write PWM_IMM_KILL Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter'). '0': synchronous kill activation. Deactivates the 'dt_line_out' and 'dt_line_compl_out' signals with the next module clock ('active count' pre-scaled 'clk_counter'). '1': immediate kill activation. Immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals. This field has a function in PWM, PWM_DT and PWM_PR modes only. [8:8] read-write PWM_STOP_ON_KILL Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only. [9:9] read-write PWM_SYNC_KILL Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. [10:10] read-write PWM_DISABLE_MODE Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped. Note: The output signal of this selection can be further modified by the immediate kill logic and line_out polarity settings (CTRL.QUAD_ENCODING_MODE). [13:12] read-write Z The behavior is the same is in previous mxtcpwm (version 1). When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are NOT driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the TCPWM output 'line_out_en' to 0. When the counter is stopped upon a stop event the PWM outputs are deactivated (to the polarity defined by CTL.QUAD_ENCODING_MODE). 0 RETAIN When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM outputs are retained (keep their previous levels). While the counter is disabled or stopped the PWM outputs can be changed via LINE_SEL (when parameter GRP_SMC_PRESENT = 1). 1 L When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '0' and the PWM output 'line_compl_out' is driven as a fixed '1'. 2 H When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '1' and the PWM output 'line_compl_out' is driven as a fixed '0'. 3 UP_DOWN_MODE Determines counter direction. In QUAD mode this field acts as QUAD_RANGE_MODE field selecting between different counter range, reload value and compare / capture behavior. [17:16] read-write COUNT_UP Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. 0 COUNT_DOWN Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 1 COUNT_UPDN1 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 2 COUNT_UPDN2 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). 3 ONE_SHOT When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. [18:18] read-write QUAD_ENCODING_MODE In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode. In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUAD_ENCODING_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUAD_ENCODING_MODE[1]. [21:20] read-write X1 X1 encoding (QUAD mode) This encoding is identical with an up / down counting functionality of the following way: Rising edges of input phiA increment or decrement the counter depending on the state of input phiB (direction input). 0 X2 X2 encoding (QUAD mode) 1 X4 X4 encoding (QUAD mode) 2 UP_DOWN Up / Down rotary counting mode. Input phiA increments the counter, input phiB decrements the counter. The trigger edge detection settings apply. 3 MODE Counter mode. [26:24] read-write TIMER Timer mode 0 RSVD1 N/A 1 CAPTURE Capture mode 2 QUAD Quadrature mode Different encoding modes can be selected by QUAD_ENCODING_MODE including up/down count functionality. Different counter range, reload value and capture behavior can be selected by QUAD_RANGE_MODE (overloaded field UP_DOWN_MODE). 3 PWM Pulse width modulation (PWM) mode 4 PWM_DT PWM with deadtime insertion mode 5 PWM_PR Pseudo random pulse width modulation 6 SR Shift register mode. 7 DBG_FREEZE_EN Specifies the counter behavior in debug mode. '0': The counter operation continues in debug mode. '1': The counter operation freezes in debug mode. [30:30] read-write ENABLED Counter enable. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_IN_SEL, TR_IN_EDGE_SEL, TR_PWM_CTRL and TR_OUT_SEL register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ('tr_out0' and tr_out1'). - the counter's line outputs ('line_out' and 'line_compl_out'). [31:31] read-write STATUS Counter status register 0x4 32 read-only 0x20 0xFFFF8FF1 DOWN When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. [0:0] read-only TR_CAPTURE0 Indicates the actual level of the selected capture 0 trigger. [4:4] read-only TR_COUNT Indicates the actual level of the selected count trigger. [5:5] read-only TR_RELOAD Indicates the actual level of the selected reload trigger. [6:6] read-only TR_STOP Indicates the actual level of the selected stop trigger. [7:7] read-only TR_START Indicates the actual level of the selected start trigger. [8:8] read-only TR_CAPTURE1 Indicates the actual level of the selected capture 1 trigger. [9:9] read-only LINE_OUT Indicates the actual level of the PWM line output signal. [10:10] read-only LINE_COMPL_OUT Indicates the actual level of the complementary PWM line output signal. [11:11] read-only RUNNING When '0', the counter is NOT running. When '1', the counter is running. This field is used to indicate that the counter is running after a start/reload event and that the counter is stopped after a stop event. When a running counter operation is paused in debug state (see CTRL.DBG_PAUSE) then the RUNNING bit is still '1'. [15:15] read-only DT_CNT_L Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter). In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. [23:16] read-only DT_CNT_H High byte of 16-bit dead time counter. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8bit wide and the only the field DT_CNT_L is used as dead time counter. [31:24] read-only COUNTER Counter count register 0x8 32 read-write 0x0 0xFFFFFFFF COUNTER 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. [31:0] read-write CC0 Counter compare/capture 0 register 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. [31:0] read-write CC0_BUFF Counter buffered compare/capture 0 register 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC Additional buffer for counter CC register. [31:0] read-write CC1 Counter compare/capture 1 register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. [31:0] read-write CC1_BUFF Counter buffered compare/capture 1 register 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC Additional buffer for counter CC1 register. [31:0] read-write PERIOD Counter period register 0x20 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. [31:0] read-write PERIOD_BUFF Counter buffered period register 0x24 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Additional buffer for counter PERIOD register. In PWM_PR mode PEROD_BUFF defines the LFSR polynomial. Each bit represents a tap of the shift register which can be feed back to the MSB via an XOR tree. Examples for GRP_CNT_WIDTH = 16: - Maximum length 16bit LFSR - polynomial x^16 + x^14 + x^13 + x^11 + 1 - taps 0,2,3,5 -> PERIOD = 0x002d - period is 2^16-1 = 65535 cycles - Maximum length 8bit LFSR: - polynomial x^8 + x^6 + x^5 + x^4 + 1 - taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR) - period is 2^8-1 = 255 cycles In SR mode PERIOD_BUFF defines which tap of the shift register generates the PWM output signals. For a delay of n cycles (from capture event to PWM output) the bit CNT_WIDTH-n should be set to '1'. For a shift register function only one tap should be use, i.e. a one-hot value must be written to PERIOD_BUFF. If multiple bits in PERIOD_BUFF are set then the taps are XOR combined. [31:0] read-write LINE_SEL Counter line selection register 0x28 32 read-write 0x32 0x77 OUT_SEL Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control. This field has a function in PWM and PWM_PR modes only. Note: The output signal of this selection can be further modified by the stop / kill logic and line_out polarity setting (CTRL.QUAD_ENCODING_MODE[0]). [2:0] read-write L fixed '0' 0 H fixed '1' 1 PWM PWM signal 'line' 2 PWM_INV inverted PWM signal 'line' 3 Z The output 'line_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the output 'line_out_en' to 0. 4 RSVD5 N/A 5 RSVD6 N/A 6 RSVD7 N/A 7 COMPL_OUT_SEL Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control. This field has a function in PWM and PWM_PR modes only. Note: The output signal of this selection can be further modified by the stop / kill logic and line_compl_out polarity setting (CTRL.QUAD_ENCODING_MODE[1]). [6:4] read-write L fixed '0' 0 H fixed '1' 1 PWM PWM signal 'line' 2 PWM_INV inverted PWM signal 'line' 3 Z The output 'line_compl_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the output 'line_compl_out_en' to 0. 4 RSVD5 N/A 5 RSVD6 N/A 6 RSVD7 N/A 7 LINE_SEL_BUFF Counter buffered line selection register 0x2C 32 read-write 0x32 0x77 OUT_SEL Buffer for LINE_SEL.OUT_SEL. Can be exchanged with LINE_SEL.LINE_OUT_SEL on a terminal count event with an actively pending switch event. This field has a function in PWM and PWM_PR modes only. [2:0] read-write COMPL_OUT_SEL Buffer for LINE_SEL.COMPL.OUT_SEL. Can be exchanged with LINE_SEL.LINE_COMPL_OUT_SEL on a terminal count event with an actively pending switch event. This field has a function in PWM and PWM_PR modes only. [6:4] read-write DT Counter PWM dead time register 0x30 32 read-write 0x0 0xFFFFFFFF DT_LINE_OUT_L In PWM_DT mode, this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. Note: This field determines the low byte of the 16-bit dead time before activating 'line_out' when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating 'line_out' and 'line_compl_out'. [7:0] read-write DT_LINE_OUT_H In PWM_DT mode, this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. [15:8] read-write DT_LINE_COMPL_OUT In PWM_DT mode, this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. [31:16] read-write TR_CMD Counter trigger command register 0x40 32 read-write 0x0 0x3D CAPTURE0 SW capture 0 trigger. When written with '1', a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.ENABLED, the field is immediately set to '0'. [0:0] read-write RELOAD SW reload trigger. For HW behavior, see COUNTER_CAPTURE0 field. [2:2] read-write STOP SW stop trigger. For HW behavior, see COUNTER_CAPTURE0 field. [3:3] read-write START SW start trigger. For HW behavior, see COUNTER_CAPTURE0 field. [4:4] read-write CAPTURE1 SW capture 1 trigger. For HW behavior, see COUNTER_CAPTURE0 field. [5:5] read-write TR_IN_SEL0 Counter input trigger selection register 0 0x44 32 read-write 0x100 0xFFFFFFFF CAPTURE0_SEL Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing, the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by setting 2 and above. The settings above are used for the general purpose trigger inputs 'tr_all_cnt_in' connected to all counters selected. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. [7:0] read-write COUNT_SEL Selects one of the 256 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. Note: In the modes: TIMER, CAPTURE, PWM, PWM_DT, and SR, If the counter is externally triggered ( COUNT_SEL > 1), an external trigger will be required for each TR_CMD to execute. For example, a write to TR_CMD.START will not start the counter until the trigger selected by COUNT_SEL asserts. The next trigger will increment the counter since the counter is now running. This goes for all TR_CMD fields. [15:8] read-write RELOAD_SEL Selects one of the 256 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In these modes, it will update the counter with 0x8000 (counter midpoint) or 0x0000 depending on the QUAD_RANGE_MODE. [23:16] read-write STOP_SEL Selects one of the 256 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. [31:24] read-write TR_IN_SEL1 Counter input trigger selection register 1 0x48 32 read-write 0x0 0xFFFF START_SEL Selects one of the 256 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). [7:0] read-write CAPTURE1_SEL Selects one of the 256 input triggers as a capture 1 trigger. [15:8] read-write TR_IN_EDGE_SEL Counter input trigger edge selection register 0x4C 32 read-write 0xFFF 0xFFF CAPTURE0_EDGE A capture 0 event will copy the counter value into the CC0 register. [1:0] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 COUNT_EDGE A counter event will increase or decrease the counter by '1'. [3:2] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 RELOAD_EDGE A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. [5:4] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 STOP_EDGE A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. [7:6] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 START_EDGE A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. [9:8] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 CAPTURE1_EDGE A capture 1 event will copy the counter value into the CC1 register. [11:10] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 TR_PWM_CTRL Counter trigger PWM control register 0x50 32 read-write 0xFF 0xFF CC0_MATCH_MODE Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC0 register should be set to '0'. For a 100 percent duty cycle, the counter CC0 register should be set to larger than the counter PERIOD register. [1:0] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 OVERFLOW_MODE Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. [3:2] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 UNDERFLOW_MODE Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. [5:4] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 CC1_MATCH_MODE Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals. [7:6] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 TR_OUT_SEL Counter output trigger selection register 0x54 32 read-write 0x32 0x77 OUT0 Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event. [2:0] read-write OVERFLOW Overflow event 0 UNDERFLOW Underflow event 1 TC Terminal count event (default selection) 2 CC0_MATCH Compare match 0 event 3 CC1_MATCH Compare match 1 event 4 LINE_OUT PWM output signal 'line_out' 5 RSVD6 N/A 6 Disabled Output trigger disabled. 7 OUT1 Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event. [6:4] read-write OVERFLOW Overflow event 0 UNDERFLOW Underflow event 1 TC Terminal count event 2 CC0_MATCH Compare match 0 event (default selection) 3 CC1_MATCH Compare match 1 event 4 LINE_OUT PWM output signal 'line_out' 5 RSVD6 N/A 6 Disabled Output trigger disabled. 7 INTR Interrupt request register 0x70 32 read-write 0x0 0x7 TC Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. [0:0] read-write CC0_MATCH Counter matches CC0 register event. Set to '1', when event is detected. Write with '1' to clear bit. [1:1] read-write CC1_MATCH Counter matches CC1 register event. Set to '1', when event is detected. Write with '1' to clear bit. [2:2] read-write INTR_SET Interrupt set request register 0x74 32 read-write 0x0 0x7 TC Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write CC0_MATCH Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write CC1_MATCH Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write INTR_MASK Interrupt mask register 0x78 32 read-write 0x0 0x7 TC Mask bit for corresponding bit in interrupt request register. [0:0] read-write CC0_MATCH Mask bit for corresponding bit in interrupt request register. [1:1] read-write CC1_MATCH Mask bit for corresponding bit in interrupt request register. [2:2] read-write INTR_MASKED Interrupt masked request register 0x7C 32 read-only 0x0 0x7 TC Logical and of corresponding request and mask bits. [0:0] read-only CC0_MATCH Logical and of corresponding request and mask bits. [1:1] read-only CC1_MATCH Logical and of corresponding request and mask bits. [2:2] read-only EVTGEN0 Event generator EVTGEN 0x403F0000 0 4096 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 COMP0_STATUS Comparator structures comparator 0 status 0x4 32 read-only 0x0 0xFFFF COMP0_OUT Active comparator 'comp0_out[]' outputs. [15:0] read-only COMP1_STATUS Comparator structures comparator 1 status 0x8 32 read-only 0x0 0xFFFF COMP1_OUT DeepSleep comparator 'comp1_out_lf[]' outputs (synchronized from clk_lf to the IP clock). [15:0] read-only COUNTER_STATUS Counter status 0x10 32 read-only 0x0 0x80000000 VALID Active counter validity: '0': Invalid. '1': Valid. The COUNTER register field INT32 is only valid when VALID is '1'. The COUNTER_STATUS and COUNTER registers are non-retention registers; i.e. the COUNTER_STATUS and COUNTER registers are reset during DeepSleep power mode. After entering the Active power mode, the Active counter is initialized with the DeepSleep counter. This initialization may take up to 1 clk_lf cycle. [31:31] read-only COUNTER Counter 0x14 32 read-only 0x0 0x0 INT32 Active counter 'counter_int[31:0]' on clk_ref_div. [31:0] read-only RATIO_CTL Ratio control 0x20 32 read-write 0x0 0xC0070000 DYNAMIC_MODE Weighted average calculation (only used when DYNAMIC is '1'): '0': new RATIO value = (RATIO + measurement + 1) / 2. '1': new RATIO value = (3*RATIO + measurement + 2) / 4. '2': new RATIO value = (7*RATIO + measurement + 4) / 8. '3': new RATIO value = (15*RATIO + measurement + 8) / 16. '4': new RATIO value = (31*RATIO + measurement + 16) / 32. '5': new RATIO value = (63*RATIO + measurement + 32) / 64. '6': new RATIO value = (127*RATIO + measurement + 64) / 128. '7': new RATIO value = (255*RATIO + measurement + 128) / 256. Note: 'measurement' (integer component only) is defined as: 256 * 'number of measured clk_ref_div cycles per clk_lf cycle'. The RATIO value (integer and fractional component) is defined as: 256*RATIO.INT16 + RATIO.FRAC8 (RATIO.INT16 = RATIO >> 8 and RATIO.FRAC8 = RATIO percent 256). [18:16] read-write DYNAMIC Specifies if RATIO_CTL.VALID and RATIO are under SW or HW control: '0': SW control. '1: HW control. Auto calibration is used to derive the RATIO value. HW measures the number of clk_ref_div cycles per clk_lf cycle. This measurement is combined with the current ratio value to calculate a new ratio value. [30:30] read-write VALID Ratio value valid: '0': Invalid. '1': Valid. The RATIO register fields INT16 and FRAC8 are only valid when VALID is '1'. [31:31] read-write RATIO Ratio 0x24 32 read-write 0x0 0x0 FRAC8 Fractional component of ratio value. [15:8] read-write INT16 Integer component of ratio value. [31:16] read-write REF_CLOCK_CTL Reference clock control 0x30 32 read-write 0x0 0xFF INT_DIV Divider control for clk_ref_div: '0': Divide by 1. ... '255': Divide by '256'. Fclk_ref_div = Fclk_ref / (INT_DIV + 1) [7:0] read-write INTR Interrupt 0x700 32 read-write 0x0 0xFFFF COMP0 This interrupt cause field is activated (HW sets the field to '1') when a comparator 0 event is generated (Active counter 'counter_int[31:0]' becomes greater or equal to COMP0.INT[31:0]). [15:0] read-write INTR_SET Interrupt set 0x704 32 read-write 0x0 0xFFFF COMP0 SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write INTR_MASK Interrupt mask 0x708 32 read-write 0x0 0xFFFF COMP0 Mask bit for corresponding field in the INTR register. [15:0] read-write INTR_MASKED Interrupt masked 0x70C 32 read-only 0x0 0xFFFF COMP0 Logical and of corresponding INTR and INTR_MASK fields. [15:0] read-only INTR_DPSLP DeepSleep interrupt 0x710 32 read-write 0x0 0xFFFF COMP1 This interrupt cause field is activated (HW sets the field to '1') when a comparator 1 event is generated (DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1.INT[31:0]). [15:0] read-write INTR_DPSLP_SET DeepSleep interrupt set 0x714 32 read-write 0x0 0xFFFF COMP1 SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write INTR_DPSLP_MASK DeepSleep interrupt mask 0x718 32 read-write 0x0 0xFFFF COMP1 Mask bit for corresponding field in the INTR register. [15:0] read-write INTR_DPSLP_MASKED DeepSleep interrupt masked 0x71C 32 read-only 0x0 0xFFFF COMP1 Logical and of corresponding INTR and INTR_MASK fields. [15:0] read-only 16 32 COMP_STRUCT[%s] Comparator structure 0x00000800 COMP_CTL Comparator control 0x0 32 read-write 0x0 0x80010003 COMP0_EN Active comparator (COMP0) enable: '0': Disabled. The comparator output 'comp0_out' is '0'. '1': Enabled. [0:0] read-write COMP1_EN DeepSleep comparator (COMP1) enable: '0': Disabled. The comparator output 'comp1_out_lf' is '0'. '1': Enabled. [1:1] read-write TR_OUT_EDGE Specifies the 'tr_out' output trigger: '0': The trigger is a level sensitive trigger. The Active comparator output ('comp0_out') is reflected on 'tr_out'. '1': The trigger is an edge sensitive trigger. Activation of the Active comparator output (rising edge on 'comp0_out') results in a two cycle '1'/high pulse on 'tr_out'. [16:16] read-write ENABLED Comparator structure enable: '0': Disabled. '1': Enabled. [31:31] read-write COMP0 Comparator 0 (Active functionality) 0x4 32 read-write 0x0 0x0 INT32 This value is a 32-bit unsigned integer in the range [0, 2^32-1]. The comparator 'comp0_out' output is activated when the Active counter 'counter_int[31:0]' becomes greater or equal to COMP0. Note: SW must ensure that COMP_CTL.COMP_EN[0] is '0' when COMP0 is written. [31:0] read-write COMP1 Comparator 1 (DeepSleep functionality) 0x8 32 read-write 0x0 0x0 INT32 This value is a 32-bit unsigned integer in the range [0, 2^32-1]. The comparator 'comp1_out_lf' output is activated when the DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1. Note: SW must ensure that COMP_CTL.COMP_EN[1] is '0' when COMP1 is written. [31:0] read-write SMIF0 SMIF subsystem (bridge + 2 core SMIFs, OR no bridge and 1 core SMIF) SMIF 0x40400000 0 262144 registers SMIF_BRIDGE AXI/AHB interleaving and FOTA bridge 0x00000000 CTL Global control registers for the bridge 0x0 32 read-write 0x80000303 0x80000303 ARB_PRI_AHB_SMIF0 If two AHB masters are both trying to access the physical SMIF0 space from the separate SMIF0 and SMIF1 XIP spaces as allowed through remap regions, the winner is determined by this bit: 0: the master accessing through the SMIF0 XIP space 1: the master accessing through the SMIF1 XIP space [0:0] read-write ARB_PRI_AHB_SMIF1 Same as ARB_PRI_AHB_SMIF0 except for accessing the physical SMIF1 space. [1:1] read-write ARB_PRI_AXI_SMIF0 Same as ARB_PRI_AHB_SMIF0 except for two AXI masters accessing the physical SMIF0 space. [8:8] read-write ARB_PRI_AXI_SMIF1 Same as ARB_PRI_AHB_SMIF0 except for two AXI masters accessing the physical SMIF1 space. [9:9] read-write ENABLED Determines whether the bridge is enabled or not: 0: Remapping bridge is disabled and bypassed. In that case the SMIF0 XIP region connects directly to the SMIF0 physical space, and the SMIF1 XIP region maps directly to the SMIF1 physical space. As such no extra latency or arbitration cycles are incurred. All remap region registers are ignored as are the ARB_PRI_* registers. 1: Remapping bridge is invoked which allows for the remap regions to be employed. However, an extra bus cycle of latency is incurred on all AHB and AXI address channel accesses to allow for remap calculations. Also there can be arbitration latency in the case where 2 masters are trying to access a single physical SMIF. This bit should not be changed if there is any ongoing or pending XIP activity. When this bit is 1, it is forbidden to change any bridge configuration registers (i.e., the rest of the bits in this CTL register and any bits in the REMAP_REGION registers). [31:31] read-write 8 256 SMIF_REMAP_REGION[%s] 'Remap regions' which define how XIP accesses can be remapped into SMIF physical spaces 0x00001000 CTL Control bits for remap region 0x0 32 read-write 0x30000 0x80070003 USE_SMIF Determines whether the remap region is active or not, and if active whether it is a simple remap or interleaving remap: 0: remap region is inactive (all other registers associated with this remap region are ignored) 1: remap accesses to SMIF0 2: remap accesses to SMIF1 3: remap accesses to SMIF0 and SMIF1 on an interleaving basis This and all other remap region registers are relevant only if the bridge's CTL.ENABLED=1. [1:0] read-write INTLV_STEP_SIZE Interleaving step size (only relevant when USE_SMIF=3): 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes [18:16] read-write SMIF_SPACE Determines which SMIF XIP space the ADDR register applies to: 0: SMIF0 1: SMIF1 [31:31] read-write ADDR Base address of remap region 0x10 32 read-write 0x0 0x1FF00000 ADDR Determines the base address within a SMIF XIP space of a remap region. CTL.SMIF_SPACE determines which SMIF XIP space this address exists in. The associated MASK register determines the size of the remap region. The base address must be situated on a boundary that equals the size of the remap region. If remap regions overlap then the lower numbered remap region will be used where there is overlap. [28:20] read-write MASK Mask value to be paired with ADDR 0x14 32 read-write 0x0 0x1FF00000 MASK Determines the size of the remap region in the XIP space. Pairs with ADDR. To program, determine the size of the region (range is 1MB to 512MB) then set the bits 'above' that value to 1 and the lower bits to 0. Some examples: 1MB: 0x1FF 2MB: 0x1FE 4MB: 0x1FC ... 256MB: 0x100 512MB: 0x000 If USE_SMIF=11 (interleaving) then MASK=0x1FF is illegal. [28:20] read-write SMIF0_REMAP Base address for remaps into SMIF0 physical memory space 0x18 32 read-write 0x0 0x1FF00000 SMIF0_REMAP Determines the base address within the SMIF0 physical space where remaps to SMIF0 are to be located. The size of the remap region is equal to MASK, unless interleaving is true (CTL.USE_SMIF=3) then it is equal to half the size of MASK. SMIF0_REMAP must be situated on a boundardy that equals that resulting granularity. [28:20] read-write SMIF1_REMAP Base address for remaps into SMIF1 physical memory space 0x1C 32 read-write 0x0 0x1FF00000 SMIF1_REMAP Same as described in SMIF0_REMAP except for SMIF1. [28:20] read-write 2 65536 CORE[%s] Serial Memory Interface 0x00020000 CTL Control 0x0 32 read-write 0x500000 0x83F70001 XIP_MODE Mode of operation. Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. [0:0] read-write MMIO_MODE '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. 0 ARB_MODE ''1': Arbitration mode. Arbitrates XIP vs. MMIO accesses such that any ongoing, pending, or 'merged' transactions on XIP always take priority over any MMIO accesses to the device. However, if an MMIO access is in process it cannot be interrupted until it completes (as defined by sending the 'last command' via TX_CMD_MMIO_FIFO_WR). If MMIO accesses are not happening at all, though, then the XIP accesses endure no extra arbitration latency. 1 DESELECT_DELAY Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: '0': 1 memory interface clock cycle. '1': 2 memory interface clock cycles. '2': 3 memory interface clock cycles. '3': 4 memory interface clock cycles. '4': 5 memory interface clock cycles. '5': 6 memory interface clock cycles. '6': 7 memory interface clock cycles. '7': 8 memory interface clock cycles. During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. [18:16] read-write SELECT_SETUP_DELAY Specifies the duration between 'spi_select_out[]' activating (going low) to the first 'spi_clk_out' rising edge before considering any MDL delay due to CTL2.MDL_TAP_SEL. Subtract that delay from the below values, plus allow some margin for combinatorial variances between spi_select_out[] and spi_clk_out. i.e., if after subtracting the MDL delay the timing would barely meet the memory datasheet requirement then it is recommended to go to the next higher setting. These values apply for DDR mode, or SDR mode with CTL2.TX_SDR_EXTRA_SETUP=0. For SDR mode with CTL2.TX_SDR_EXTRA_SETUP=1 add 1 PLL clock cycle to these values. DDR or SDR mode is determined by the mode of the first phase of the transaction. '0': 2 PLL clock cycles '1': 2 PLL clock cycles + 1 memory interface clock cycles '2': 2 PLL clock cycles + 2 memory interface clock cycles '3': 2 PLL clock cycles + 3 memory interface clock cycles [21:20] read-write SELECT_HOLD_DELAY Specifies the duration between the last 'spi_clk_out' falling edge and 'spi_select_out[]' deactivating (going high) before considering any MDL delay due to CTL2.MDL_TAP_SEL. Add that delay to the below values, plus allow some margin for combinatorial variances between spi_select_out[] and spi_clk_out. i.e., if after adding the MDL delay the timing would barely meet the memory datasheet requirement then it is recommended to go to the next higher setting. These values apply for DDR mode, or SDR mode with CTL2.TX_SDR_EXTRA_SETUP=0. For SDR mode with CTL2.TX_SDR_EXTRA_SETUP=1 subtract 1 PLL clock cycle from these values. DDR or SDR mode is determined by the mode of the last phase of the transaction. '0': 1 memory interface clock cycle + CTL2.CLKOUT_DIV adjustment '1': 2 memory interface clock cycles + CTL2.CLKOUT_DIV adjustment '2': 3 memory interface clock cycles + CTL2.CLKOUT_DIV adjustment '3': 4 memory interface clock cycles + CTL2.CLKOUT_DIV adjustment For the following settings of CTL2.CLKOUT_DIV apply these adjustments to the above: 0 (DIV2): subtract 1 PLL clock cycle 1 (DIV4): no adjustment needed 2 (DIV8): add 2 PLL clock cycles 3 (DIV16): add 6 PLL clock cycles [23:22] read-write BLOCK Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. This field is not used for test controller accesses. [24:24] read-write BUS_ERROR 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). 0 WAIT_STATES 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). This can be particularly true if ARB_MODE=1 and an MMIO access must wait a potentially long time behind a XIP access. 1 CLOCK_IF_SEL Specifies the clock source for 'clk_if'. Must be 0 (clk_pll_normal) before entering DeepSleep; can be returned to 1 (clk_pll_direct) afterwards. '0': clk_pll_normal is used to create clk_if '1': clk_pll_direct is used to create clk_if - 'don't use' [25:25] read-write ENABLED SMIF core enable: '0': Disabled. All non-retention registers are reset to their default value when this SMIF core is disabled. When this SMIF core is disabled, the XIP accesses produce AHB-Lite bus errors and AXI error responses. '1': Enabled. Notes: - Before disabling or resetting this SMIF core, SW should ensure that this SMIF core is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. - After CTL.ENABLED is set to 1 it takes up to 20 clk_if cycles until the memory interface registers are realeased from reset. - The DLL is powered up when CTL.ENABLED is set to 1. It takes 8us for the DLL to stabilize and lock to the freerunning PLL clock at which point STATUS.DLL_LOCKED and INTR.DLL_LOCK will be set. Wait another 4us beyond that before executing any transactions on the memory interface; the MDL and SDLs require that extra time after the lock indication to reach their final stable delay values. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 STATUS Status 0x4 32 read-only 0x0 0x0 DLL_LOCKED 0: DLL is not locked 1: DLL is locked Once the reference clock to the DLL is stable and the DLL is powered (CTL.ENABLED=1), the DLL should lock within 8us. The lock time will also be incurred when transitioning from DeepSleep to Active. Wait another 4us beyond the lock indication before executing any transactions on the memory interface; the MDL and SDLs require that extra time after the lock indication to reach their final stable delay values. If the DLL suddenly becomes unlocked then the TX interface will be held in reset to prevent any further transactions to the memory. The block should be disabled (CTL.ENABLED=0) to reset all other non-retention registers. Any data in the internal FIFOs will be lost. The DLL suddenly unlocking is considered an unusual event that would only occur if the reference clock to the DLL had a sudden change in frequency, which should only happen at the direction of SW. When transitioning to DeepSleep the DLL will naturally unlock. However, upon returning to Active all non-retention registers are reset and thus disabling the block to enact that reset is not necessary. [0:0] read-only BUSY AHB Cache, AXI interface, cryptography, XIP, device interface, MPC (if present) initialization, or any other key logic busy in the IP: '0': not busy '1': busy When BUSY is '0', the IP can be safely disabled without: - the potential loss of transient write data. - the potential risk of aborting an inflight SPI device interface transfer. - disrupting MPC (if present) initialization When BUSY is '0', the mode of operation (ARB_MODE or MMIO_MODE) can be safely changed. [31:31] read-only CTL2 Control 2 0x8 32 read-write 0x800000 0x80F00F33 DLL_SPEED_MODE Set according to the PLL clock frequency that feeds the DLL: 0: 160 to 180 MHz 1: >180 to 266 MHz 2: >266 to 333 MHz 3: >333 to 400 MHz [1:0] read-write CLKOUT_DIV The clock out to the memory is a divided version of the MDL clock out: 0: divide by 2 1: divide by 4 2: divide by 8 3: divide by 16 [5:4] read-write MDL_TAP_SEL Determines the relative amount of delay through the MDL for the reference clock in terms of the number of tap delays. There are 16 MDL taps that evenly divide the reference clock period into 16 delay steps. Setting 0 constitutes 1 tap delay, setting 1 constitutes 2 tap delays, etc., setting 15 constitutes 16 tap delays (which is effectively a full MDL reference clock period, which can be thought of as 'zero delay' since it aligns the posedges of the output to the input reference). When CLKOUT_DIV does not equal zero (not divide by 2), MDL tap selections must be between 2 and 12 in order to meet internal timing. Tap selections of 0,1,13,14, and 15 are illegal. There is an exception in DDR mode, it can support between 2 and 13, while 0,1,14, and 15 are illegal. When CLKOUT_DIV=0 internal timing can be met for all MDL tap selections. [11:8] read-write RX_CAPTURE_MODE N/A [21:20] read-write RX_CHASE_MARGIN Determines how long the design should wait after sending the last clock out to the memory interface before 'chase' clocks should be created internally to push remainder data in the interface pipeline into the RX FIFO. Lesser numbers allow for shorter deselect cycles between packets, but if the time is too short then the chase clocks will interfere with the normal capture clock from the last clock cycle from the memory interface (whether it is feedback or RWDS). So a proper balance must be struck. The default value is expected to work for all situations. Other values are there as a backup plan in case something more aggressive can be achieved or whether something even more conservative should be used. [23:22] read-write TX_SDR_EXTRA_SETUP This field is only applicable in SDR transmit mode. 0: transmit data is launched nominally 1 PLL clock period ahead of the rising edge of the clock out to the memory 1: transmit data is launched nominally 2 PLL clock periods ahead of the rising edge of the clock out to the memory [31:31] read-write DLP_DELAY_TAP_SEL0 DLP Delay Tap Select Register 0 0x10 32 read-only 0x0 0x0 DATA_BIT0_TAP_SEL DLP tap selection for the IP's spi_data[0] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL). In SDR mode: The upper 4 bits of this field are zero, while the lower 4 bits represent the winning tap selection for all received bits on this data line. In DDR mode: The upper 4 bits of this field represent the winning tap selection for the bits received in the MSB data of the DDR pair, while the lower 4 bits represent the winning tap selection for the bits received in the LSB data of the DDR pair on this data line. A 'winning tap selection' in either case is mapped as {tap15 of neg SDL, tap13 of neg SDL,..., tap1 of neg SDL, tap15 of pos SDL, tap13 of pos SDL,..., tap1 of pos SDL} for values 15 to 0, respectively. [7:0] read-only DATA_BIT1_TAP_SEL Delay line tap selection for the IP's spi_data[1] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL). See DATA_BIT0_TAP_SEL. [15:8] read-only DATA_BIT2_TAP_SEL Delay line tap selection for the IP's spi_data[2] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL). See DATA_BIT0_TAP_SEL. [23:16] read-only DATA_BIT3_TAP_SEL Delay line tap selection for the IP's spi_data[3] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL). See DATA_BIT0_TAP_SEL. [31:24] read-only DLP_DELAY_TAP_SEL1 DLP Delay Tap Select Register 1 0x14 32 read-only 0x0 0x0 DATA_BIT4_TAP_SEL Delay line tap selection for the IP's spi_data[4] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL). See DATA_BIT0_TAP_SEL. [7:0] read-only DATA_BIT5_TAP_SEL Delay line tap selection for the IP's spi_data[5] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL). See DATA_BIT0_TAP_SEL. [15:8] read-only DATA_BIT6_TAP_SEL Delay line tap selection for the IP's spi_data[6] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL). See DATA_BIT0_TAP_SEL. [23:16] read-only DATA_BIT7_TAP_SEL Delay line tap selection for the IP's spi_data[7] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL). See DATA_BIT0_TAP_SEL. [31:24] read-only DLP_CTL DLP Control Register 0x18 32 read-write 0x3070000 0xF0FFFFF DLP Data Learning Pattern [15:0] read-write DLP_SIZE Size of data learning pattern as such: '0': 1 bit ... '15': 16 bit. If CTL2.RX_CAPTURE_MODE=1 then the DLP_SIZE+1 LSBs of the expected data learning pattern (DLP[DLP_SIZE:0]) are compared with the data learning pattern generated by the memory device and captured during the last latency / dummy cycles of a memory read transfer. Note: For DDR read data transfers the size of the DLP must be an even number, i.e. DLP_SIZE must be an odd number. [19:16] read-write DLP_WARNING_LEVEL Determines when the DLP_WARNING interrupt cause field is set: - DLP_WARNING is set when the number of delay line taps resulting to a correctly captured DLP is less than DLP_WARNING_LEVEL for at least one input data line Note: To provide a margin in both directions relatively to the selected middle tap at least 3 delay line taps have to result into a correctly captured DLP, i.e. the DLP_WARNING_LEVEL has to be set to greater or equal 3. [27:24] read-write DLP_STATUS0 DLP Status Register 0 0x20 32 read-only 0x0 0x0 DATA_BIT0 In SDR mode: Number of delay line taps for the IP's spi_data[0] (note the mapping of spi_data to IO in DEVICE.CTL.DATA_SEL) with correctly captured DLP in last read transaction. Legal values: 0 to 16. In DDR mode: Similar to SDR except the MSB and LSB data of the DDR pair are evaluated separately and this field reflects the least number of successful taps between those two evaluations. [4:0] read-only DATA_BIT1 Same as the DATA_BIT0 description except for spi_data[1] [12:8] read-only DATA_BIT2 Same as the DATA_BIT0 description except for spi_data[2] [20:16] read-only DATA_BIT3 Same as the DATA_BIT0 description except for spi_data[3] [28:24] read-only DLP_STATUS1 DLP Status Register 1 0x24 32 read-only 0x0 0x0 DATA_BIT4 Same as the DATA_BIT0 description except for spi_data[4] [4:0] read-only DATA_BIT5 Same as the DATA_BIT0 description except for spi_data[5] [12:8] read-only DATA_BIT6 Same as the DATA_BIT0 description except for spi_data[6] [20:16] read-only DATA_BIT7 Same as the DATA_BIT0 description except for spi_data[7] [28:24] read-only TX_CMD_FIFO_STATUS Transmitter command FIFO status 0x44 32 read-only 0x0 0xF USED4 Number of entries that are used in the TX command FIFO. Legal range: [0, 8]. [3:0] read-only TX_CMD_MMIO_FIFO_STATUS Transmitter command MMIO FIFO status 0x48 32 read-only 0x0 0xF USED4 Number of entries that are used in the TX command MMIO FIFO. Legal range: [0, 8]. [3:0] read-only TX_CMD_MMIO_FIFO_WR Transmitter command MMIO FIFO write 0x50 32 write-only 0x0 0x7FFFFFF DATA27 N/A [26:0] write-only TX_DATA_MMIO_FIFO_CTL Transmitter data MMIO FIFO control 0x80 32 read-write 0x0 0x7 TX_TRIGGER_LEVEL Determines when the TX data MMIO FIFO 'tr_tx_req' trigger is activated: - Trigger is active when TX_DATA_MMIO FIFO_STATUS.USED <= TRIGGER_LEVEL. [2:0] read-write TX_DATA_FIFO_STATUS Transmitter data FIFO status 0x84 32 read-only 0x0 0xF USED4 Number of entries that are used in the TX data FIFO. Legal range: [0, 8]. [3:0] read-only TX_DATA_MMIO_FIFO_STATUS Transmitter data MMIO FIFO status 0x88 32 read-only 0x0 0xF USED4 Number of entries that are used in the TX data MMIO FIFO. Legal range: [0, 8]. [3:0] read-only TX_DATA_MMIO_FIFO_WR1 Transmitter data MMIO FIFO write 0x90 32 write-only 0x0 0xFF DATA0 TX data (written to TX data MMIO FIFO). [7:0] write-only TX_DATA_MMIO_FIFO_WR2 Transmitter data MMIO FIFO write 0x94 32 write-only 0x0 0xFFFF DATA0 TX data (written to TX data MMIO FIFO, first byte). [7:0] write-only DATA1 TX data (written to TX data MMIO FIFO, second byte). [15:8] write-only TX_DATA_MMIO_FIFO_WR4 Transmitter data MMIO FIFO write 0x98 32 write-only 0x0 0xFFFFFFFF DATA0 TX data (written to TX data MMIO FIFO, first byte). [7:0] write-only DATA1 TX data (written to TX data MMIO FIFO, second byte). [15:8] write-only DATA2 TX data (written to TX data MMIO FIFO, third byte). [23:16] write-only DATA3 TX data (written to TX data MMIO FIFO, fourth byte). [31:24] write-only TX_DATA_MMIO_FIFO_WR1ODD Transmitter data MMIO FIFO write 0x9C 32 write-only 0x0 0xFF DATA0 TX data (written to TX data MMIO FIFO). [7:0] write-only RX_DATA_MMIO_FIFO_CTL Receiver data MMIO FIFO control 0xC0 32 read-write 0x0 0x7 RX_TRIGGER_LEVEL Determines when RX data FIFO 'tr_rx_req' trigger is activated: - Trigger is active when RX_DATA_MMIO_FIFO_STATUS.USED > TRIGGER_LEVEL. [2:0] read-write RX_DATA_MMIO_FIFO_STATUS Receiver data MMIO FIFO status 0xC4 32 read-only 0x0 0xF USED4 Number of entries that are used in the RX data MMIO FIFO. Legal range: [0, 8]. [3:0] read-only RX_DATA_FIFO_STATUS Receiver data FIFO status 0xC8 32 read-only 0x0 0x10F USED4 Number of entries that are used in the RX data FIFO. Legal range: [0, 8]. [3:0] read-only RX_SR_USED Data available in RX Shift Register, i.e. completely read from RX data FIFO. [8:8] read-only RX_DATA_MMIO_FIFO_RD1 Receiver data MMIO FIFO read 0xD0 32 read-only 0x0 0xFF DATA0 RX data (read from RX data FIFO). [7:0] read-only RX_DATA_MMIO_FIFO_RD2 Receiver data MMIO FIFO read 0xD4 32 read-only 0x0 0xFFFF DATA0 RX data (read from RX data FIFO, first byte). [7:0] read-only DATA1 RX data (read from RX data FIFO, second byte). [15:8] read-only RX_DATA_MMIO_FIFO_RD4 Receiver data MMIO FIFO read 0xD8 32 read-only 0x0 0xFFFFFFFF DATA0 RX data (read from RX data FIFO, first byte). [7:0] read-only DATA1 RX data (read from RX data FIFO, second byte). [15:8] read-only DATA2 RX data (read from RX data FIFO, third byte). [23:16] read-only DATA3 RX data (read from RX data FIFO, fourth byte). [31:24] read-only RX_DATA_MMIO_FIFO_RD1_SILENT Receiver data MMIO FIFO silent read 0xE0 32 read-only 0x0 0xFF DATA0 RX data (read from RX data FIFO). [7:0] read-only SLOW_CA_CTL Slow cache control 0x100 32 read-write 0xC0000000 0xC3030000 WAY Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2. [17:16] read-write SET_ADDR Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2. [25:24] read-write PREF_EN Prefetch enable: '0': Disabled. '1': Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. [30:30] read-write ENABLED Cache enable: '0': Disabled. '1': Enabled. [31:31] read-write SLOW_CA_CMD Slow cache command 0x108 32 read-write 0x0 0x1 INV Cache and prefetch buffer invalidation. SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. Note, A write access will invalidate the prefetch buffer automatically in hardware. A write access should invalidate both fast and slow caches, by firmware. Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. [0:0] read-write FAST_CA_CTL Fast cache control 0x180 32 read-write 0xC0000000 0xC3030000 WAY See SLOW_CA_CTL.WAY. [17:16] read-write SET_ADDR See SLOW_CA_CTL.SET_ADDR. [25:24] read-write PREF_EN See SLOW_CA_CTL.PREF_EN. [30:30] read-write ENABLED See SLOW_CA_CTL.ENABLED. [31:31] read-write FAST_CA_CMD Fast cache command 0x188 32 read-write 0x0 0x1 INV See SLOW_CA_CMD.INV. [0:0] read-write 4 128 SMIF_CRYPTO[%s] Cryptography registers (one set for each key) 0x00000200 CRYPTO_CMD Cryptography command 0x0 32 read-write 0x0 0x1 START SW sets this field to '1' to start an AES-128 forward block cipher operation (on CRYPTO_INPUT0-3). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_OUTPUT0, ..., CRYPTO_OUTPUT3. The operation takes roughly 13 clk_mem clock cycles. This register is only applicable for MMIO accesses and only in MMIO_MODE. XIP accesses are encrypted on-the-fly in ARB_MODE and thus do not use this register. Because XIP has exclusive access to the crypto engine in ARB_MODE, MMIO encryption is not available in that mode. As such if encryption is needed for MMIO accesses in ARB_MODE that encryption must be done by other means (i.e., chip level crypto). [0:0] read-write CRYPTO_ADDR Cryptography base address 0x4 32 read-write 0x0 0xFFFFFF00 ADDR Only applies to XIP accesses. Specifies the base address of the memory region that will have cryptography applied on XIP accesses with a unique key. If this region overlaps with another key's region, the lower numbered key is used (i.e., crypto key 0 has the highest priority). If the region is 2^m Bytes, ADDR MUST be a multiple of 2^m. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. Note that in order for cryptogrpahy to be applied the DEVICE.CTL.CRYPTO_EN must be set to 1 as well for any devices that share this region. [31:8] read-write CRYPTO_MASK Cryptography mask 0x8 32 read-write 0x0 0xFFFFFF00 MASK Only applies to XIP accesses. Specifies the size of the memory region whose base address is determined by CRYPTO_ADDR. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in CRYPTO_ADDR.ADDR: Address A is in the cryptography region when (A[31:8] & MASK[31:8]) == CRYPTO_ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. [31:8] read-write CRYPTO_SUBREGION Cryptography subregion disable 0xC 32 read-write 0x0 0xFF SUBREGION_DISABLE Only applies to XIP accesses. The cryptography region for this key as determined by CRYPTO_ADDR and CRYPTO_MASK is further divided into 8 equal subregions. e.g., if a 1 MB region is specified then the 8 subregions will be 128 KB. If SUBREGION_DISABLE=0 then cryptography will be performed on that subregion (assuming any associated DEVICE.CTL.CRYPTO_EN=1). Otherwise if SUBREGION_DISABLE=1 then cryptography is not applied. Note that setting all SUBREGION_DISABLE bits to 1 will effectively disable this key. The encryption decision and the associated key are locked in at the beginning of a memory access and will apply until the end of such atomic accesses. Therefore, it is the user's responsibility to ensure memory accesses do not span across (sub)regions that have different keys and/or cypto enabled/disabled differently across such (sub)regions. [7:0] read-write CRYPTO_INPUT0 Cryptography input 0 0x20 32 read-write 0x0 0x0 INPUT_LSB Plaintext PT[3:0] = CRYPTO_INPUT0.INPUT_LSB. [3:0] read-write INPUT_MSB Plaintext PT[31:4] = CRYPTO_INPUT0.INPUT_MSB. [31:4] read-write CRYPTO_INPUT1 Cryptography input 1 0x24 32 read-write 0x0 0x0 INPUT Plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT2 Cryptography input 2 0x28 32 read-write 0x0 0x0 INPUT Plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT3 Cryptography input 3 0x2C 32 read-write 0x0 0x0 INPUT Plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. [31:0] read-write CRYPTO_KEY0 Cryptography key 0 0x40 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. [31:0] write-only CRYPTO_KEY1 Cryptography key 1 0x44 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. [31:0] write-only CRYPTO_KEY2 Cryptography key 2 0x48 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. [31:0] write-only CRYPTO_KEY3 Cryptography key 3 0x4C 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. [31:0] write-only CRYPTO_OUTPUT0 Cryptography output 0 0x60 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT1 Cryptography output 1 0x64 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT2 Cryptography output 2 0x68 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT3 Cryptography output 3 0x6C 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. [31:0] read-write CRC_CMD CRC Command 0x600 32 read-write 0x0 0x3 START SW sets this field to '1' to start a CRC calculation over the 64 CRC input bits provided in CRC_INPUT0 and CRC_INPUT1, using 0xFF as CRC feedback. HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRC_OUTPUT. A CRC calculation over 64 bits is done by writing the 64 input bits to CRC_INPUT0/1, performing a START command and reading the CRC result from CRC_OUTPUT. This register is only applicable for MMIO accesses. [0:0] read-write CONTINUE SW sets this field to '1' to continue a CRC calculation over the 64 CRC input bits provided in CRC_INPUT0 and CRC_INPUT1, using the current CRC output in CRC_OUTPUT as CRC feedback. HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRC_OUTPUT. This command is used to perform a CRC calculation over more than 64 intput bits. For example a CRC calculation over 128 bits is done by writing the first 64 input bits to CRC_INPUT0/1, performing a START command, writing the second 64 input bits to CRC_INPUT0/1, performing a CONTINUE command and reading the CRC result from CRC_OUTPUT. For a CRC calculation of even more input bits the CONTINUE command has to be used multiple times. This register is only applicable for MMIO accesses. [1:1] read-write CRC_INPUT0 CRC input 0 0x620 32 read-write 0x0 0x0 INPUT Lower 32 input bits to the CRC engine. [31:0] read-write CRC_INPUT1 CRC input 1 0x624 32 read-write 0x0 0x0 INPUT Higher 32 input bits to the CRC engine. [31:0] read-write CRC_OUTPUT CRC output 0x640 32 read-only 0xFF 0xFF CRC_OUTPUT CRC engine output. [7:0] read-only INTR Interrupt register 0x7C0 32 read-write 0x0 0x3713F TR_TX_REQ Activated when a TX data MMIO FIFO trigger 'tr_tx_req' is activated. [0:0] read-write TR_RX_REQ Activated when a RX data MMIO FIFO trigger 'tr_rx_req' is activated. [1:1] read-write XIP_ALIGNMENT_ERROR Activated on a XIP access, when: - a write transfer is requested and - Dual-Quad SPI mode (selected device's ADDR_CTL.DIV2 is '1') is selected or - Octal SPI DDR mode (selected device's DATA_CTL.DDR_MODE = '1' and DATA_CTL.WIDTH = '3') or Hyperbus mode (selected device's ADDR_CTL.SIZE3 = '7') is selected without memory write byte masking (selected device's WR_DUMMY_CTL.RWDS_EN = '0') and - the AHB-Lite / AXI bus transfer address is not a multiple of '2' or - the requested AHB-Lite / AXI bus transfer size is NOT a multiple of '2'. Additionally, it is activated on a XIP access when the selected memory device does not support write byte masking (WR_DUMMY_CTL.RWDS_EN=0) and an AXI transfer occurs with not all of the AXI write strobes ('wstrb') enabled according to the transfer size ('assize'). Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. Write accesses are only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. Octal SPI DDR mode or Hyperbus mode are 16-bit word based protocols, writing single bytes is only possible when write byte masking is supported (via RWDS). Read accesses are always possible by extending the transfer size and / or aligning the address as needed and discarding the non-relevant byte(s). [2:2] read-write TX_CMD_FIFO_OVERFLOW Activated on an AHB-Lite write transfer to the TX command MMIO FIFO (TX_CMD_MMIO_FIFO_WR) with not enough free entries available. [3:3] read-write TX_DATA_FIFO_OVERFLOW Activated on an AHB-Lite write transfer to the TX data MMIO FIFO (TX_DATA_MMIO_FIFO_WR1, TX_DATA_MMIO_FIFO_WR2, TX_DATA_MMIO_FIFO_WR4, TX_DATA_MMIO_FIFO_WR1ODD) with not enough free entries available. [4:4] read-write RX_DATA_MMIO_FIFO_UNDERFLOW Activated on an AHB-Lite read transfer from the RX data MMIO FIFO (RX_DATA_MMIO_FIFO_RD1, RX_DATA_MMIO_FIFO_RD2, RX_DATA_MMIO_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. [5:5] read-write DLP_FAIL Data Learning Failed (no DLP match found on at least one of the input data lines when CTL2.RX_CAPTURE_MODE=1). [8:8] read-write DLP_WARNING Data Learning Warning (for at least one input data line less then DLP.DLP_WARNING_LEVEL delay line taps resulted in a correct DLP capturing when CTL2.RX_CAPTURE_MODE=1). This interrupt will be suppressed, though, if DLP_FAIL also occurs during the same DLP evaluation cycle. [12:12] read-write DLL_LOCK DLL lock (edge detected) [13:13] read-write DLL_UNLOCK DLL unlock (edge detected) [14:14] read-write CRC_ERROR CRC Error. A read transfer data CRC check failed. [16:16] read-write FS_STATUS_ERROR Functional Safety Status Error. A read transfer Functional Safety Status check failed (see definition in DEVICE_ver2.RD_CRC_CTL.STATUS_CHECK_MASK and DEVICE_ver2.RD_CRC_CTL.STATUS_CHECK_MASK_POL). [17:17] read-write INTR_SET Interrupt set register 0x7C4 32 read-write 0x0 0x3713F TR_TX_REQ Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write TR_RX_REQ Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write XIP_ALIGNMENT_ERROR Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write TX_CMD_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write TX_DATA_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write RX_DATA_MMIO_FIFO_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write DLP_FAIL Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write DLP_WARNING Write with '1' to set corresponding bit in interrupt request register. [12:12] read-write DLL_LOCK Write with '1' to set corresponding bit in interrupt request register. [13:13] read-write DLL_UNLOCK Write with '1' to set corresponding bit in interrupt request register. [14:14] read-write CRC_ERROR Write with '1' to set corresponding bit in interrupt request register. [16:16] read-write FS_STATUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [17:17] read-write INTR_MASK Interrupt mask register 0x7C8 32 read-write 0x0 0x3713F TR_TX_REQ Mask bit for corresponding bit in interrupt request register. [0:0] read-write TR_RX_REQ Mask bit for corresponding bit in interrupt request register. [1:1] read-write XIP_ALIGNMENT_ERROR Mask bit for corresponding bit in interrupt request register. [2:2] read-write TX_CMD_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [3:3] read-write TX_DATA_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [4:4] read-write RX_DATA_MMIO_FIFO_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write DLP_FAIL Mask bit for corresponding bit in interrupt request register. [8:8] read-write DLP_WARNING Mask bit for corresponding bit in interrupt request register. [12:12] read-write DLL_LOCK Mask bit for corresponding bit in interrupt request register. [13:13] read-write DLL_UNLOCK Mask bit for corresponding bit in interrupt request register. [14:14] read-write CRC_ERROR Mask bit for corresponding bit in interrupt request register. [16:16] read-write FS_STATUS_ERROR Mask bit for corresponding bit in interrupt request register. [17:17] read-write INTR_MASKED Interrupt masked register 0x7CC 32 read-only 0x0 0x3713F TR_TX_REQ Logical and of corresponding request and mask bits. [0:0] read-only TR_RX_REQ Logical and of corresponding request and mask bits. [1:1] read-only XIP_ALIGNMENT_ERROR Logical and of corresponding request and mask bits. [2:2] read-only TX_CMD_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [3:3] read-only TX_DATA_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [4:4] read-only RX_DATA_MMIO_FIFO_UNDERFLOW Logical and of corresponding request and mask bits. [5:5] read-only DLP_FAIL Logical and of corresponding request and mask bits. [8:8] read-only DLP_WARNING Logical and of corresponding request and mask bits. [12:12] read-only DLL_LOCK Logical and of corresponding request and mask bits. [13:13] read-only DLL_UNLOCK Logical and of corresponding request and mask bits. [14:14] read-only CRC_ERROR Logical and of corresponding request and mask bits. [16:16] read-only FS_STATUS_ERROR Logical and of corresponding request and mask bits. [17:17] read-only 2 128 DEVICE[%s] Device (only used for XIP acceses) 0x00000800 CTL Control 0x0 32 read-write 0x0 0xFFFFF311 WR_EN Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device. [0:0] read-write CRYPTO_EN Cryptography on read/write accesses: '0': disabled. '1': enabled. [4:4] read-write DATA_SEL Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): '0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. '1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. '2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. '3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. [9:8] read-write MERGE_TIMEOUT Continuous transfer merge timeout in clk_mem cycles. This limits the standby time of the memory interface, i.e. the time the memory device is selected but no data is transferred. The counting of the merge timeout period is done in the XIP block using clk_mem cycles. It starts when the last TX or RX byte is transferred to or from the data FIFOs. After this period the memory device is deselected. A later transfer, even from a continuous address, starts with the overhead phases (command, address, mode, dummy cycles). [14:12] read-write _1_cycle Timeout after 1 clk_mem cycle. That means transfers will only be merged if the continuous transfer request is already available when the previous transfer is finished. 0 _16_cycles Timeout after 2^4 = 16 clk_mem cycles. At a clk_mem frequency of 200MHz this means 80ns. 1 _256_cycles Timeout after 2^8 = 256 clk_mem cycles. At a clk_mem frequency of 200MHz this means ~1.3us. 2 _4096_cycles Timeout after 2^12 = 4096 clk_mem cycles. At a clk_mem frequency of 200MHz this means ~20us. 3 _65536_cycles Timeout after 2^16 = 65536 clk_mem cycles. At a clk_mem frequency of 200MHz this means ~330us. 4 RSVD5 N/A 5 RSVD6 N/A 6 RSVD7 N/A 7 MERGE_EN Continous transfer merge enable: '0': Disabled. No merging of transfers is done. Longest possible memory transfer is 16 Byte. '1': Enabled. Merging of continous transfers is done. This skips the overhead (command, address, mode, dummy cycles) for a continuous (linear sequential) transfer. [15:15] read-write TOTAL_TIMEOUT Total transfer timeout in clk_mem cycles. The counting of the total timout period is done in the XIP block using clk_mem cycles. It starts when the first command of a new (not merged) transaction is transferred to the TX command FIFO causing the interface logic to select the memory. After this period the memory device is deselected. This feature is needed for RAM devices requiring refresh cycles. The value needs to be derived from the RAMs maximum transaction length time (tCMS) minus the time of transferring 2x16byte data block (data granularity of the XIP ports is 16byte, 1 16byte block transfer outstanding, another available for merging). If the result in negative, MERGE_EN must be set to '0'. Example: RAM device tCMS = 4us, interface clock frequency = 100MHz: total transfer timeout is 4us - 2x16x10ns = 3680ns. With clk_mem frequency of 200MHz the TOTAL_TIMEOUT value is 3680/5 = 736. Note: In the unlikely case that the total transfer timeout is used (usually for RAM devices) while the page boundary crossing latency generation is enabled via RD_BOUND_CTL.PRESENT (usually for FLASH devices) the additional time needs to taken into account. [29:16] read-write TOTAL_TIMEOUT_EN Total transfer timeout enable. '0': Disabled. There is no limit for the total transfer time. The continuous transfer merge timeout for limiting the idle time of the memory interface still applies. '1': Enabled. The maximum total transfer time is limited by field TOTAL_TIMEOUT. [30:30] read-write ENABLED Device enable: '0': Disabled. '1': Enabled. [31:31] read-write ADDR Device region base address 0x8 32 read-write 0x0 0x0 ADDR Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. [31:8] read-write MASK Device region mask 0xC 32 read-write 0x0 0x0 MASK Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error. [31:8] read-write ADDR_CTL Address control 0x20 32 read-write 0x0 0x107 SIZE3 N/A [2:0] read-write DIV2 Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If DIV2 is set to '1', the memory does not support write masking (WR_DUMMY_CTL.RWDS_EN = '0'), and in this configuration a write transfer is requested and the write transfer request address is NOT a multiple of 2 or the requested number of Bytes to be written is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. [8:8] read-write RX_CAPTURE_CONFIG RX capture configuration 0x28 32 read-write 0x0 0x30300FF NEG_SDL_TAP_SEL Determines the amount of delay through the 'neg' SDL for the receive clock coming from the pins in terms of the number of tap delays. There are 16 SDL taps and the delay resolution of each tap is controlled by and thus closely mimics the delay resolution of the MDL. i.e., each tap has a resolution roughly equal to 1/16th of the DLL reference clock period. Setting 0 constitutes 1 tap delay, setting 1 constitutes 2 tap delays, etc., setting 15 constitutes 16 tap delays (effectively a full DLL reference clock period). [3:0] read-write POS_SDL_TAP_SEL Same as NEG_SDL_TAP_SEL except for the 'pos' SDL. [7:4] read-write SDR_PIPELINE_NEG_DAT 0: Does not pipeline SDR receive data captured relative to the negedge of the receive clock 1: Does pipeline [16:16] read-write SDR_SWAP_BYTES 0: Does not swap SDR receive data captured relative to the negedge of the receive clock with the data captured relative to the posedge of the receive clock 1: Does swap [17:17] read-write DDR_PIPELINE_POS_DAT 0: Does not pipeline DDR receive data captured relative to the posedge of the receive clock 1: Does pipeline DDR_PIPELINE_POS_DAT must be set to '1' if CORE.CTL2.RX_CAPTURE_MODE=2 [24:24] read-write DDR_SWAP_BYTES 0: Does not swap DDR receive data captured relative to the negedge of the receive clock with the data captured relative to the posedge of the receive clock 1: Does swap The setting DDR_SWAP_BYTES is ignored and operates as if set to 1 (even if set to 0) when CORE.CTL2.RX_CAPTURE_MODE=2 [25:25] read-write RD_STATUS Read status 0x30 32 read-only 0x0 0xFF FS_STATUS Provides the Functional Safety Status Register of the memory received with the last read transfer. [7:0] read-only RD_CMD_CTL Read command control 0x40 32 read-write 0x0 0xC007FFFF CODE Command byte code. [7:0] read-write CODEH Command high byte code. This field specifies the most significant command byte, sent before the least significant command byte (CODE). It is only used when PRESENT2 = '2'. [15:8] read-write WIDTH Width of data transfer: '0': 1 bit/cycle (single data transfer). '1': 2 bits/cycle (dual data transfer). '2': 4 bits/cycle (quad data transfer). '3': 8 bits/cycle (octal data transfer). [17:16] read-write DDR_MODE Mode of transfer rate: '0': SDR mode '1': DDR mode [18:18] read-write PRESENT2 Presence of command field: '0': not present '1': present (1 Byte) '2': present (2 Byte for OPI) Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') either the HB protocol needs to be selected (by ADDR_CTL.SIZE3='7') or this field needs to be set to PRESENT2='2'. [31:30] read-write RD_ADDR_CTL Read address control 0x44 32 read-write 0x0 0x70000 WIDTH Width of transfer. [17:16] read-write DDR_MODE Mode of transfer rate. [18:18] read-write RD_MODE_CTL Read mode control 0x48 32 read-write 0x0 0xC007FFFF CODE Mode byte code. Note: If a mode field is present (PRESENT='1') for octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') the CODE is sent twice. [7:0] read-write CODEH Mode high byte code. This field specifies the most significant mode byte, sent before the least significant mode byte (CODE). It is only used when PRESENT2 = '2'. [15:8] read-write WIDTH Width of transfer. [17:16] read-write DDR_MODE Mode of transfer rate. [18:18] read-write PRESENT2 Presence of mode field: '0': not present '1': present (1 Byte) '2': present (2 Byte for OPI) Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') this field needs to be set to PRESENT2='2' to generate a mode field (or to PRESENT2='0'). [31:30] read-write RD_DUMMY_CTL Read dummy control 0x4C 32 read-write 0x0 0xC000001F SIZE5 Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes! [4:0] read-write PRESENT2 Presence of dummy cycles: '0': not present '1': present '2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode) Notes: - If transmitting command, address and mode fields in SDR mode (driving data between falling edges of spihb_clk_out) and the memory is driving read data in DDR mode (based on memory type and transmitted command), then there must be at least 1 latency / dummy cycle specified (RD_DUMMY_CTL.PRESENT2 > 0') to prevent controller and memory driving data signals at the same time. The same is true for the theoretical (practically irrelevant case) of transmitting at least one of the command, address and mode fields in DDR mode but receiving data from the memory in SDR mode. - When using the RWDS / DQS based capturing scheme (CTL.CLK_IF_RX_SEL=[6,7]), then there is a minimum number of latency / dummy cycles required (RD_DUMMY_CTL.PRESENT2 > 0). For the Hyperbus protocol (DDR_CTL.SIZE3=7) at least 1 latency / dummy cycle has to be specified, for SPI with DQS capturing at least 2 latency / dummy cycles need to be selected (RD_DUMMY_CTL.SIZE5 > 0, exception see following note). - In case of falling edge RWDS / DQS capturing (CTL.CLOCK_IF_RX_SEL = '6') and SDR mode, SW should reduce the number of dummy cycles by 1 compared to the latency cycles required by the memory device. -DDR read commands need at least one dummy cycle -For Hyperbus, set RD DUMMY_CTL.SIZE5=initial latency cycles-2 [31:30] read-write RD_DATA_CTL Read data control 0x50 32 read-write 0x0 0x70000 WIDTH Width of transfer. [17:16] read-write DDR_MODE Mode of transfer rate. [18:18] read-write RD_CRC_CTL Read Bus CRC control 0x54 32 read-write 0xFF00 0xDFFFFFFF STATUS_CHECK_MASK Specifies which of the Functional Safety Status field bits are checked. There is 1 mask bit for each Functional Safety Status bit. '0': The associated Functional Safety Status bit is not checked. '1': The associated Functional Safety Status bit is checked. If the received Funciontal Safety Status bit = Functional Safety Status Error Polarity (STATUS_ERROR_POLARITY), then a Functional Safety Status error interrupt and a XIP bus error response is generated. [7:0] read-write STATUS_ERROR_POL Specifies the polarity of the Functional Safety Status field bits. There is 1 polarity bit for each Functional Safety Status bit. '0': The associated Functional Safety Status bit is active-low. '1': The associated Functional Safety Status bit is active-high. [15:8] read-write DATA_CRC_INPUT_SIZE Number of input data bytes for CRC generation (minus 1), i.e. number of data bytes over which the data CRC field is generated (minus 1): '0': 1 byte ... '255': 256 bytes. Note: For octal data transfer with DDR mode (RD_DATA_CTL.WIDTH='3' and RD_DATA_CTL.DDR_MODE='1') the number of bytes for CRC generation must be even (i.e. DATA_CRC_INPUT_SIZE must be odd). [23:16] read-write CMD_ADDR_CRC_WIDTH Width of command / address CRC field. [25:24] read-write CMD_ADDR_CRC_DDR_MODE Mode of transfer rate of command / address CRC field. [26:26] read-write CMD_ADDR_CRC_INPUT Specifies which fields are included in the command / address CRC generation. '0': The command / address CRC field is generated over the address and (if present) mode fields only. '1': The command / address CRC field is generated over the command, address and (if present) mode fields. [27:27] read-write DATA_CRC_CHECK N/A [28:28] read-write CMD_ADDR_CRC_PRESENT Presence of command / address CRC field: '0': not present '1': present Note: For octal data transfer with DDR mode (RD_CRC_CTL.WIDTH='3' and RD_CRC_CTL.DDR_MODE='1') the command / address CRC byte is sent twice, otherwise the command / address CRC byte is only sent once. [30:30] read-write DATA_CRC_PRESENT Presence of data CRC field: '0': not present '1': present Note: Width and data transfer mode (SDR or DDR) of read data CRC fields are the same as for the associated read data fields, i.e. are specified by RD_DATA_CTL.WIDTH and RD_DATA_CTL.DDR_MODE. [31:31] read-write RD_BOUND_CTL Read boundary control 0x58 32 read-write 0x100000 0x9033001F SIZE5 Number of base latency cycles (minus 1) used for calculating the number of fist page boundary crossing latency cycles: '0': base_latency = 1 cycles ... '31': base_latency = 32 cycles. The actual latency cycles when crossing the first page boundary depend on the start address of the transaction and is calculated as follows: if ((page_size - base_latency) < Start_Addr & (sub_page_size - 1)) { ((Start_Addr & (sub_page_size - 1)) - page_size + base_latency) } else { 0 } [4:0] read-write SUB_PAGE_SIZE Specifies the size of a memory sub page 'sub_page_size'. '0': sub_page_size = 8 words = 16 bytes (default). '1': sub_page_size = 16 words = 32 bytes. '2': sub_page_size = 32 words = 64 bytes. '3': sub_page_size = 64 words = 128 bytes. [17:16] read-write SUB_PAGE_NR Specifies the number of sub pages per page. '0': 1 sub pages per page, i.e. page_size = sub_page_size '1': 2 sub pages per page, i.e. page_size = 2 x sub_page_size '2': 4 sub pages per page, i.e. page_size = 4 x sub_page_size '3': 8 sub pages per page, i.e. page_size = 8 x sub_page_size [21:20] read-write SUBSEQ_BOUND_EN Enable subsequent page boundary latency cycles. '0': Disabled. The page crossing latency cycles are only generated when crossing the first page boundary (i.e. the first time when the SUB_PAGE_NRth sub page boundary is crossed, e.g. with 2 sub pages per page when the 2nd sub page boundary is crossed). '1': Enabled. The page crossing latency cycles are generated when crossing the first and subsequent page boundaries (i.e. every time when a SUB_PAGE_NRth sub page boundary is crossed, e.g. with 2 sub pages per page when the 2nd, 4th, 6th, ... sub page boundary is crossed). Note: This only applies when the number of base latency cycles (SIZE5+1) is greater than the size of a page (base_latency > page_size). Must be set to 0 otherwise. [28:28] read-write PRESENT Presence of first page boundary latency cycles: '0': not present '1': present [31:31] read-write WR_CMD_CTL Write command control 0x60 32 read-write 0x0 0xC007FFFF CODE Command byte code. [7:0] read-write CODEH Command high byte code. This field specifies the most significant command byte, sent before the least significant command byte (CODE). It is only used when PRESENT2 = '2'. [15:8] read-write WIDTH Width of transfer. [17:16] read-write DDR_MODE Mode of transfer rate. [18:18] read-write PRESENT2 Presence of command field: '0': not present '1': present (1 Byte) '2': present (2 Byte for OPI) Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') either the HB protocol needs to be selected (by ADDR_CTL.SIZE3='7') or this field needs to be set to PRESENT2='2'. [31:30] read-write WR_ADDR_CTL Write address control 0x64 32 read-write 0x0 0x70000 WIDTH Width of transfer. [17:16] read-write DDR_MODE Mode of transfer rate. [18:18] read-write WR_MODE_CTL Write mode control 0x68 32 read-write 0x0 0xC007FFFF CODE Mode byte code. [7:0] read-write CODEH Mode high byte code. This field specifies the most significant mode byte, sent before the least significant mode byte (CODE). It is only used when PRESENT2 = '2'. [15:8] read-write WIDTH Width of transfer. [17:16] read-write DDR_MODE Mode of transfer rate. [18:18] read-write PRESENT2 Presence of mode field: '0': not present '1': present (1 Byte) '2': present (2 Byte for OPI) Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') this field needs to be set to PRESENT2='2' to generate a mode field (or to PRESENT2='0'). [31:30] read-write WR_DUMMY_CTL Write dummy control 0x6C 32 read-write 0x0 0xC002001F SIZE5 Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. [4:0] read-write RWDS_EN Read-Write-Data-Strobe Enable. Specifies whether the RWDS output signal should be driven starting in the last dummy cycle until DESELECT. This is needed for write transactions with byte masking via RWDS (e.g. Hyperbus). '0': do not drive RWDS output '1': drive RWDS output starting in last dummy cycle until DESELECT Note: this field is located in the WR_DUMMY_CTL register (and not in the WR_DATA_CTL register) since the RWDS signal needs to be driven already in the last dummy cycle. Note:The setting RWDS_EN=1 which enables byte masking limits the maximum frequency. Please refer to device specific datasheet, xSPI specifications (JEDEC with slave DS). [17:17] read-write PRESENT2 Presence of dummy cycles: '0': not present '1': present '2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode) [31:30] read-write WR_DATA_CTL Write data control 0x70 32 read-write 0x0 0x70000 WIDTH Width of transfer. [17:16] read-write DDR_MODE Mode of transfer rate. [18:18] read-write WR_CRC_CTL Write Bus CRC control 0x74 32 read-write 0x0 0xCFFF0000 DATA_CRC_INPUT_SIZE Number of input data bytes for CRC generation (minus 1), i.e. number of data bytes over which the data CRC field is generated (minus 1): '0': 1 byte ... '255': 256 bytes. Note: For octal data transfer with DDR mode (WR_DATA_CTL.WIDTH='3' and WR_DATA_CTL.DDR_MODE='1') the number of bytes for CRC generation must be even (i.e. DATA_CRC_INPUT_SIZE must be odd). [23:16] read-write CMD_ADDR_CRC_WIDTH Width of command / address CRC field. [25:24] read-write CMD_ADDR_CRC_DDR_MODE Mode of transfer rate of command / address CRC field. [26:26] read-write CMD_ADDR_CRC_INPUT Specifies which fields are included in the command / address CRC generation. '0': The command / address CRC field is generated over the address and (if present) mode fields only. '1': The command / address CRC field is generated over the command, address and (if present) mode fields. [27:27] read-write CMD_ADDR_CRC_PRESENT Presence of command / address CRC field: '0': not present '1': present Note: For octal data transfer with DDR mode (RD_CRC_CTL.WIDTH='3' and RD_CRC_CTL.DDR_MODE='1') the command / address CRC byte is sent twice, otherwise the command / address CRC byte is only sent once. [30:30] read-write DATA_CRC_PRESENT Presence of data CRC field: '0': not present '1': present Note: Width and data transfer mode (SDR or DDR) of read data CRC fields are the same as for the associated read data fields, i.e. are specified by RD_DATA_CTL.WIDTH and RD_DATA_CTL.DDR_MODE. Note: For octal data transfer with DDR mode (RD_DATA_CTL.WIDTH='3' and RD_DATA_CTL.DDR_MODE='1') the data CRC byte is sent twice, otherwise the data CRC byte is only sent once. [31:31] read-write ETH0 Ethernet Interface ETH 0x40480000 0 65536 registers CTL MXETH Control Register 0x0 32 read-write 0x0 0x8000FF07 ETH_MODE Set ethernet mode. The speed of 10M/100M/1G is selected by programming network_config after IP is enabled. The field also specifies the clock source of internal tx_clk and rx_clk domain. [1:0] read-write MII MII mode (10/100MHz speed is determined by network_config[0]). 0 GMII GMII mode (network_config[10] must be set to enable 1G operation). 1 RGMII RGMII mode (10M/100M/1G speed is determined by network_config[10] and network_config[0]). 2 RMII RMII mode (10M/100M speed is determined by network_config[0]). 3 REFCLK_SRC_SEL Select the source for ref_clk. 0: Ref_clk comes from REF_CLK_IN input port (HSIO). 1: Ref_clk comes from REF_CLK_INT_IN input port (PLL). [2:2] read-write REFCLK_DIV Specify the ref_clk divider. Integer division by (1+REFCLK_DIV). Allows for integer divisions in the range [1, 256]. [15:8] read-write ENABLED MXETH enable: '0': Disabled. '1': Enabled. [31:31] read-write STATUS MXETH Status Register 0x4 32 read-only 0x0 0xFF01 PFC_NEGOTIATE Identifies that PFC priority based pause flow control has been negotiated. 0 - No PFC priority based pause frames have yet been received, flow control is being handled using classic 802.3 pause frames. 1 - At least one PFC priority based pause frames has been received. All subsequent 802.3 pause frames will be dropped. [0:0] read-only RX_PFC_PAUSED Each bit corresponds to a priority indicated within the PFC priority based pause frame. Each bit is set when a PFC priority based pause frame has been received, and the associated priority pause time quantum is non-zero. Each bit is cleared when the associated pause time identified by the received pause time quantum has elapsed. [15:8] read-only NETWORK_CONTROL The network control register contains general MAC control functions for both receiver and transmitter. 0x1000 32 read-write 0x0 0xFFFFFFFF LOOPBACK Loopback - controls the loopback output pin. [0:0] read-write LOOPBACK_LOCAL Loopback local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loopback. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loopback. Local loopback functionality is optional and may not be supported by some instantiations of the GEM. [1:1] read-write ENABLE_RECEIVE Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected. [2:2] read-write ENABLE_TRANSMIT Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list. [3:3] read-write MAN_PORT_EN Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low. [4:4] read-write CLEAR_ALL_STATS_REGS Clear statistics registers - this bit is write only. Writing a one clears the statistics registers. Self clearing register. [5:5] write-only INC_ALL_STATS_REGS Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes. Self clearing register. [6:6] write-only STATS_WRITE_EN Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes. [7:7] read-write BACK_PRESSURE Back pressure if set in 10M or 100M half duplex mode will force collisions on all received frames. Ignored in gigabit half duplex mode. [8:8] read-write TX_START_PCLK Start transmission - writing one to this bit starts transmission. [9:9] write-only TX_HALT_PCLK Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends. [10:10] write-only TX_PAUSE_FRAME_REQ Transmit pause frame - writing one to this bit causes a pause frame to be transmitted. Self clearing register. [11:11] write-only TX_PAUSE_FRAME_ZERO Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted. [12:12] write-only REMOVED_13 Write ignore, read 0 [13:13] read-only REMOVED_14 Write ignore, read 0 [14:14] read-only STORE_RX_TS Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point. Set to zero for normal operation. [15:15] read-write PFC_ENABLE Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames. [16:16] read-write TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME Write a one to transmit PFC priority based pause frame. Takes the values stored in the Transmit PFC Pause Register. Self clearing register. [17:17] write-only FLUSH_RX_PKT_PCLK Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. Self clearing register. [18:18] write-only TX_LPI_EN Enable LPI transmission when set LPI (low power idle) is immediately transmitted. LPI is transmitted even if bit 3 transmit enable is disabled. Setting this bit also sends a pause signal to the transmit datapath. [19:19] read-write PTP_UNICAST_ENA Enable detection of unicast PTP unicast frames. [20:20] read-write ALT_SGMII_MODE Alternative sgmii mode. If asserted with sgmii_mode in the network control register the ACK bit is driven before ability detect during transfer of status information from the PHY to the MAC. [21:21] read-write STORE_UDP_OFFSET N/A [22:22] read-write EXT_TSU_PORT_ENABLE Write ignore, read 0 [23:23] read-only ONE_STEP_SYNC_MODE 1588 One Step Sync Mode. Write 1 to enable. Replace timestamp field in the 1588 header for TX Sync Frames with current TSU timer value. [24:24] read-write PFC_CTRL 'Enable multiple PFC pause quantums, one per pause priority' [25:25] read-write EXT_RXQ_SEL_EN Enable external selection of receive queue. When this bit is high the ext_match1, ext_match2, ext_match3 and ext_match4 inputs will determine which receive queue a frame is routed to. This will be the case regardless of the state of the external address match enable bit 9 of the network config register. Note that receive frames will be dropped unless they are matched by the internal frame filtering functionality. If the external address match enable bit 9 in the network config register is set frames may be matched by an external address match filter as long as one of the ext_match1, ext_match2, ext_match3 and ext_match4 inputs is asserted early enough. When set ext_rxq_sel_en takes precedence over the existing screener functionality. This bit is only relevant if priority queuing is configured. [26:26] read-write OSS_CORRECTION_FIELD 1588 One Step Correction Field Update. Set this bit high to enable updating the correction field of PTP 1588 version 2 sync frames by adding current TSU timer value. [27:27] read-write SEL_MII_ON_RGMII If the RGMII interface being used set this bit high to configure the interface for MII operation. [28:28] read-write TWO_PT_FIVE_GIG 2.5G operation selected - setting this bit high drives the speed_mode[3] top level output pin high and also adjusts the link timer in the PCS auto-negotiation block to ensure it delivers 10ms for 2500BASE-X and 1.6ms in SGMII mode, and also ensures int_moderation counts 800ns periods with the speeded up MAC clocks. [29:29] read-write IFG_EATS_QAV_CREDIT Setting this bit high modifies the CBS algorithm so the IFG/IPG associated with a transmit frame counts towards its 802.1Qav credit. [30:30] read-write EXT_RXQ_RSVD_31 N/A [31:31] read-only NETWORK_CONFIG The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC. 0x1004 32 read-write 0x2C0000 0xFFFFFFFF SPEED Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. [0:0] read-write FULL_DUPLEX Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin. [1:1] read-write DISCARD_NON_VLAN_FRAMES Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic. [2:2] read-write JUMBO_FRAMES Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes. [3:3] read-write COPY_ALL_FRAMES Copy all frames - when set to logic one, all valid frames will be accepted. [4:4] read-write NO_BROADCAST No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted. [5:5] read-write MULTICAST_HASH_ENABLE Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. [6:6] read-write UNICAST_HASH_ENABLE Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. [7:7] read-write RECEIVE_1536_BYTE_FRAMES Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes. [8:8] read-write EXTERNAL_ADDRESS_MATCH_ENABLE External address match enable - when set the external address match interface can be used to copy frames to memory. [9:9] read-write GIGABIT_MODE_ENABLE Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation. 0: 10/100 operation using MII interface 1: Gigabit operation using GMI interface [10:10] read-write PCS_SELECT PCS select - selects between MII/GMII and TBI [11:11] read-write RETRY_TEST Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle. [12:12] read-write PAUSE_ENABLE Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated. [13:13] read-write RECEIVE_BUFFER_OFFSET Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer. [15:14] read-write LENGTH_FIELD_ERROR_FRAME_DISCARD Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600. [16:16] read-write FCS_REMOVE FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode. [17:17] read-write MDC_CLOCK_DIVISION MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v 000: divide pclk by 8 (pclk up to 20 MHz) 001: divide pclk by 16 (pclk up to 40 MHz) 010: divide pclk by 32 (pclk up to 80 MHz) 011: divide pclk by 48 (pclk up to 120MHz) 100: divide pclk by 64 (pclk up to 160 MHz) 101: divide pclk by 96 (pclk up to 240 MHz) 110: divide pclk by 128 (pclk up to 320 MHz) 111: divide pclk by 224 (pclk up to 540 MHz). Note. The reset value of this field is equal to the gem_mdc_clock_div define, which is user configurable. [20:18] read-write DATA_BUS_WIDTH Data bus width - set according to AMBA (AXI/AHB) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. 00: 32 bit data bus width 01: 64 bit AMBA (AXI/AHB) data bus width 10: 128 bit AMBA (AXI/AHB) data bus width 11: 128 bit AMBA (AXI/AHB) data bus width. Note. The reset value of this field is equal to the gem_dma_bus_width_def define, which is user configurable. Note: For AXI_MASTER_PRESENT=1, MXETH only supports 64b DMA data bus width, so must set it 1. For AXI_MASTER_PRESENT=0, MXETH only supports 32b DMA data bus width, so must set it 0. [22:21] read-write DISABLE_COPY_OF_PAUSE_FRAMES Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set, neither control frames with type id 8808, nor pause frames with destination address 010000c28001 are copied to memory, this functionality was enhanced in release 1p09 (mxeth uses 1p09). Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required. [23:23] read-write RECEIVE_CHECKSUM_OFFLOAD_ENABLE Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded. [24:24] read-write EN_HALF_DUPLEX_RX Enable frames to be received in half-duplex mode while transmitting. Must set '0', MXETH only supports full-duplex mode. [25:25] read-write IGNORE_RX_FCS Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero. [26:26] read-write SGMII_MODE_ENABLE SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms. [27:27] read-write IPG_STRETCH_ENABLE IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register. [28:28] read-write NSP_CHANGE Receive bad preamble. When set frames with non-standard preamble are not rejected. [29:29] read-write IGNORE_IPG_RX_ER Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode. [30:30] read-write RSVD_31 N/A [31:31] read-write NETWORK_STATUS The network status register returns status information with respect to the PHY management interface. 0x1008 32 read-only 0x6 0xFF PCS_LINK_STATE Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronisation status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved. [0:0] read-only MDIO_IN Returns status of the mdio_in pin. [1:1] read-only MAN_DONE The PHY management logic is idle (i.e. has completed). [2:2] read-only MAC_FULL_DUPLEX PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one. [3:3] read-only REMOVED_5_4 N/A [5:4] read-only PFC_NEGOTIATE_PCLK Set when PFC Priority Based Pause has been negotiated. [6:6] read-only LPI_INDICATE_PCLK LPI Indication - Low power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit changes. [7:7] read-only USER_IO_REGISTER Not presents. Access to the register will return AHB error. 0x100C 32 read-only 0x0 0xFFFFFFFF RSVD_31_0 Write ignore, read 0 [31:0] read-only DMA_CONFIG DMA Configuration Register 0x1010 32 read-write 0x180704 0x77FF3FFF AMBA_BURST_LENGTH Selects the burst length to use on the AMBA (AHB/AXI) when transferring frame data. Not used for DMA management operations and only used where space and data size allow and respecting AXI/AHB burst boundary rules. One-hot priority encoding enforced automatically on register writes as follows, where x represents don't care: 1xxxx: Attempt to use bursts of up to 16. 01xxx: Attempt to use bursts of up to 8. 001xx: Attempt to use bursts of up to 4. 0001x: Always use SINGLE bursts. 00001: Always use SINGLE bursts. 00000: Attempt to use bursts of up to 256. Note: MXETH only supports burst length up to 16. [4:0] read-write HDR_DATA_SPLITTING_EN Enable header data Splitting. When set, receive frames will be forwarded to main memory using a minimum of two DMA data buffers. The first X data buffers will contain the frame header, consisting of the Ethernet,VLAN,(IPv4 or IPv6),(TCP or UDP). X= (frame header size divided by rx_buf_size as defined in bits 23:16 of this register). The last Y data buffers will contain the frame payload. Y= (frame payload size divided by rx_buf_size). Note that for non VLAN/IP/TCP/UDP frames, the header will always be 14 bytes. When this feature is disabled, the frame is forwarded to main memory in blocks of rx_buf_size. Note: For AXI_MASTER_PRESENT=0 i.e. AHB master support, this feature cannot be set. [5:5] read-write ENDIAN_SWAP_MANAGEMENT endian swap mode enable for management descriptor accesses. When set, selects swapped endianism for AMBA (AXI/AHB) transfers. When clear, selects little endian mode. Note, the default value of this bit equals to `gem_endian_swap_def, which is design time configuration. [6:6] read-write ENDIAN_SWAP_PACKET endian swap mode enable for packet data accesses. When set, selects swapped endianism for AMBA (AXI/AHB) transfers. When clear, selects little endian mode. Note, the default value of this bit equals to `gem_endian_swap_def, which is design time configuration. [7:7] read-write RX_PBUF_SIZE N/A [9:8] read-write TX_PBUF_SIZE N/A [10:10] read-write TX_PBUF_TCP_EN N/A [11:11] read-write INFINITE_LAST_DBUF_SIZE_EN Forces the DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of infinite size. [12:12] read-write CRC_ERROR_REPORT When the bit is set, bit 16 of the receive buffer descriptor will represent FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the network config register). When this bit is clear, bit 16 of the receive buffer descriptor will represent the Canonical format indicator (CFI) bit as extracted from the receive frame (if the receive buffer descriptor is pointing to the last data buffer of the receive frame and the received frame was VLAN tagged). [13:13] read-write RX_BUF_SIZE DMA receive buffer size in external AMBA (AXI/AHB) system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes. 0x01 corresponds to buffers of 64 bytes 0x02 corresponds to 128 bytes etc. For example: 0x02: 128 byte. 0x18: 1536 byte (1*max length frame/buffer) 0xA0: 10240 byte (1*10K jumbo frame/buffer) Note that this value should never be written as zero. Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. [23:16] read-write FORCE_DISCARD_ON_ERR Auto Discard RX pkts during lack of resource. When set, the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AMBA (AXI/AHB) resource is available. When low, then received packets will remain to be stored in the SRAM based packet buffer until AMBA (AXI/AHB) buffer resource next becomes available. A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode. [24:24] read-write FORCE_MAX_AMBA_BURST_RX Force max length bursts on RX. Force the RX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer)transfers, even if there is less than max burst real packet data required to write. Any extra bytes of pad data is set to 0x00. Does not apply on bursts that break 1k boundary rule. [25:25] read-write FORCE_MAX_AMBA_BURST_TX Force max length bursts on TX. Force the TX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer) transfers as defined by bits 4:0 of this register, even when there is less that max burst data bytes to read. Residual data read is ignored. Does not apply on bursts that break 1k boundary rule. [26:26] read-write RX_BD_EXTENDED_MODE_EN Enable RX extended BD mode. See RX BD control register definition for description of feature. [28:28] read-write TX_BD_EXTENDED_MODE_EN Enable TX extended BD mode. See TX BD control register definition for description of feature. [29:29] read-write DMA_ADDR_BUS_WIDTH_1 DMA address bus width. 0 = 32b, 1 = 64b. MXETH only supports 32b DMA address bus width, so must set it 0. [30:30] read-write TRANSMIT_STATUS This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. 0x1014 32 read-write 0x0 0x1FF USED_BIT_READ Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. [0:0] read-write COLLISION_OCCURRED Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision. [1:1] read-write RETRY_LIMIT_EXCEEDED Retry limit exceeded - cleared by writing a one to this bit. [2:2] read-write TRANSMIT_GO Transmit go - if high transmit is active. When using the exposed FIFO interface, this bit represents bit 3 of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description. [3:3] read-only AMBA_ERROR123 Transmit frame corruption due to AMBA (AXI/AHB) errors. Set if an error occurs whilst midway through reading transmit frame from external memory including RRESP or BRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared by writing a one to this bit. [4:4] read-write TRANSMIT_COMPLETE123 Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit. [5:5] read-write TRANSMIT_UNDER_RUN123 Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for packet buffer mode, this bit will never be set. Cleared by writing a 1. [6:6] read-write LATE_COLLISION_OCCURRED Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit. [7:7] read-write RESP_NOT_OK123 bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. [8:8] read-write RECEIVE_Q_PTR This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AXI) operation, the receive descriptors are read from memory using a single 32bit AXI access. When the datapath is configured at 64bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AXI access. 0x1018 32 read-write 0x0 0xFFFFFFFD DMA_RX_DIS_Q Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. [0:0] read-write DMA_RX_Q_PTR Receive buffer queue base address - written with the address of the start of the receive queue. [31:2] read-write TRANSMIT_Q_PTR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. 0x101C 32 read-write 0x0 0xFFFFFFFD DMA_TX_DIS_Q Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. [0:0] read-write DMA_TX_Q_PTR Transmit buffer queue base address - written with the address of the start of the transmit queue. [31:2] read-write RECEIVE_STATUS This register, when read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. 0x1020 32 read-write 0x0 0xF BUFFER_NOT_AVAILABLE Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Cleared by writing a one to this bit. [0:0] read-write FRAME_RECEIVED Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit. [1:1] read-write RECEIVE_OVERRUN123 Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it. [2:2] read-write RESP_NOT_OK1234 bresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. [3:3] read-write INT_STATUS If not configured for priority queueing, the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. The default configuration is shown below whereby all bits are reset to zero on read. Changing the validity of the `gem_irq_read_clear define will instead require a one to be written to the appropriate bit in order to clear it. In this mode reading has no affect on the status of the bit. 0x1024 32 read-write 0x0 0x3FFFFEFF MANAGEMENT_FRAME_SENT Management frame sent - the PHY maintenance register has completed its operation. Cleared on read. [0:0] read-write RECEIVE_COMPLETE Receive complete - a frame has been stored in memory. Cleared on read. [1:1] read-write RX_USED_BIT_READ RX used bit read - set when a receive buffer descriptor is read with its used bit set. Cleared on read. [2:2] read-write TX_USED_BIT_READ TX used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared on read. [3:3] read-write TRANSMIT_UNDER_RUN Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. If an under run occurs, the transmitter will force bad crc and tx_er high. This interrupt is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB/AXI error response was returned by the connected slave, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this interrupt is also set when the tx_r_underflow input was asserted during a frame transfer. Cleared on read. [4:4] read-write RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted). Cleared on read. [5:5] read-write AMBA_ERROR Transmit frame corruption due to AMBA (AXI/AHB) error. Set if an error occurs whilst midway through reading transmit frame from external system memory, including HRESP (AHB), RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared on a read. [6:6] read-write TRANSMIT_COMPLETE Transmit complete - set when a frame has been transmitted. Cleared on read. [7:7] write-only REMOVED_9 Write ignore, read 0 [9:9] read-only RECEIVE_OVERRUN Receive overrun - set when the receive overrun status bit gets set. Cleared on read. [10:10] write-only RESP_NOT_OK bresp not OK - set when the DMA block sees bresp not OK. Cleared on read. [11:11] write-only PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field. Cleared on read. [12:12] write-only PAUSE_TIME_ELAPSED Pause Time elapsed. set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. Cleared on read. [13:13] write-only PAUSE_FRAME_TRANSMITTED Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin. Cleared on read. [14:14] write-only REMOVED_15 Write ignore, read 0 [15:15] read-only REMOVED_16 Write ignore, read 0 [16:16] read-only REMOVED_17 Write ignore, read 0 [17:17] read-only PTP_DELAY_REQ_FRAME_RECEIVED PTP delay_req frame received indicates a PTP delay_req frame has been received. Cleared on read. [18:18] write-only PTP_SYNC_FRAME_RECEIVED PTP sync frame received indicates a PTP sync frame has been received. Cleared on read. [19:19] write-only PTP_DELAY_REQ_FRAME_TRANSMITTED PTP delay_req frame transmitted indicates a PTP delay_req frame has been transmitted. Cleared on read. [20:20] write-only PTP_SYNC_FRAME_TRANSMITTED PTP sync frame transmitted indicates a PTP sync frame has been transmitted. Cleared on read. [21:21] write-only PTP_PDELAY_REQ_FRAME_RECEIVED PTP pdelay_req frame received indicates a PTP pdelay_req frame has been received. Cleared on read. [22:22] write-only PTP_PDELAY_RESP_FRAME_RECEIVED PTP pdelay_resp frame received indicates a PTP pdelay_resp frame has been received. Cleared on read. [23:23] write-only PTP_PDELAY_REQ_FRAME_TRANSMITTED PTP pdelay_req frame transmitted indicates a PTP pdelay_req frame has been transmitted. Cleared on read. [24:24] write-only PTP_PDELAY_RESP_FRAME_TRANSMITTED PTP pdelay_resp frame transmitted indicates a PTP pdelay_resp frame has been transmitted. Cleared on read. [25:25] write-only TSU_SECONDS_REGISTER_INCREMENT TSU seconds register increment indicates the register has incremented. Cleared on read. [26:26] write-only RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE Receive LPI indication status bit change [27:27] write-only REMOVED_28 Write ignore, read 0 [28:28] read-only TSU_TIMER_COMPARISON_INTERRUPT TSU timer comparison interrupt. Indicates when TSU timer count value is equal to programmed value. [29:29] write-only INT_ENABLE At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero. 0x1028 32 write-only 0x0 0x3FFFFFFF ENABLE_MANAGEMENT_DONE_INTERRUPT Enable management done interrupt [0:0] write-only ENABLE_RECEIVE_COMPLETE_INTERRUPT Enable receive complete interrupt [1:1] write-only ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT Enable receive used bit read interrupt [2:2] write-only ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT Enable transmit used bit read interrupt [3:3] write-only ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT Enable transmit buffer under run interrupt [4:4] write-only ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT Enable retry limit exceeded or late collision interrupt [5:5] write-only ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT Enable transmit frame corruption due to AMBA (AXI/AHB) error interrupt [6:6] write-only ENABLE_TRANSMIT_COMPLETE_INTERRUPT Enable transmit complete interrupt [7:7] write-only UNUSED_8 Not used [8:8] write-only UNUSED_9 Not used [9:9] write-only ENABLE_RECEIVE_OVERRUN_INTERRUPT Enable receive overrun interrupt [10:10] write-only ENABLE_RESP_NOT_OK_INTERRUPT Enable bresp not OK interrupt [11:11] write-only ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT Enable pause frame with non-zero pause quantum interrupt [12:12] write-only ENABLE_PAUSE_TIME_ZERO_INTERRUPT Enable pause time zero interrupt [13:13] write-only ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT Enable pause frame transmitted interrupt [14:14] write-only UNUSED_15 Not used [15:15] write-only UNUSED_16 Not used [16:16] write-only UNUSED_17 Not used [17:17] write-only ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED Enable PTP delay_req frame received [18:18] write-only ENABLE_PTP_SYNC_FRAME_RECEIVED Enable PTP sync frame received [19:19] write-only ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED Enable PTP delay_req frame transmitted [20:20] write-only ENABLE_PTP_SYNC_FRAME_TRANSMITTED Enable PTP sync frame transmitted [21:21] write-only ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED Enable PTP pdelay_req frame received [22:22] write-only ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED Enable PTP pdelay_resp frame received [23:23] write-only ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED Enable PTP pdelay_req frame transmitted [24:24] write-only ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED Enable PTP pdelay_resp frame transmitted [25:25] write-only ENABLE_TSU_SECONDS_REGISTER_INCREMENT Enable TSU seconds register increment [26:26] write-only ENABLE_RX_LPI_INDICATION_INTERRUPT Enable RX LPI indication interrupt [27:27] write-only UNUSED_28 Not used [28:28] write-only ENABLE_TSU_TIMER_COMPARISON_INTERRUPT Enable TSU timer comparison interrupt. [29:29] write-only INT_DISABLE Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero. 0x102C 32 read-write 0x0 0xFFFFFFFF DISABLE_MANAGEMENT_DONE_INTERRUPT 'Disable management done interrupt' [0:0] write-only DISABLE_RECEIVE_COMPLETE_INTERRUPT 'Disable receive complete interrupt' [1:1] write-only DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT 'Disable receive used bit read interrupt' [2:2] write-only DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT 'Disable transmit used bit read interrupt' [3:3] write-only DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT 'Disable transmit buffer under run interrupt' [4:4] write-only DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT 'Disable retry limit exceeded or late collision interrupt' [5:5] write-only DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT 'Disable transmit frame corruption due to AMBA (AHB/AXI) error interrupt' [6:6] write-only DISABLE_TRANSMIT_COMPLETE_INTERRUPT 'Disable transmit complete interrupt' [7:7] write-only UNUSED_8 Not used [8:8] write-only UNUSED_9 Not used [9:9] write-only DISABLE_RECEIVE_OVERRUN_INTERRUPT 'Disable receive overrun interrupt' [10:10] write-only DISABLE_RESP_NOT_OK_INTERRUPT 'Disable bresp/hresp not OK interrupt' [11:11] write-only DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT 'Disable pause frame with non-zero pause quantum interrupt' [12:12] write-only DISABLE_PAUSE_TIME_ZERO_INTERRUPT 'Disable pause time zero interrupt' [13:13] write-only DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT 'Disable pause frame transmitted interrupt' [14:14] write-only UNUSED_15 Not used [15:15] write-only UNUSED_16 Not used [16:16] write-only UNUSED_17 Not used [17:17] write-only DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED 'Disable PTP delay_req frame received' [18:18] write-only DISABLE_PTP_SYNC_FRAME_RECEIVED 'Disable PTP sync frame received' [19:19] write-only DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED 'Disable PTP delay_req frame transmitted ' [20:20] write-only DISABLE_PTP_SYNC_FRAME_TRANSMITTED 'Disable PTP sync frame transmitted ' [21:21] write-only DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED 'Disable PTP pdelay_req frame received' [22:22] write-only DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED 'Disable PTP pdelay_resp frame received' [23:23] write-only DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED 'Disable PTP pdelay_req frame transmitted' [24:24] write-only DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED 'Disable PTP pdelay_resp frame transmitted' [25:25] write-only DISABLE_TSU_SECONDS_REGISTER_INCREMENT 'Disable TSU seconds register increment' [26:26] write-only DISABLE_RX_LPI_INDICATION_INTERRUPT 'Disable RX LPI indication interrupt' [27:27] write-only UNUSED_28 Not used [28:28] write-only DISABLE_TSU_TIMER_COMPARISON_INTERRUPT 'Disable TSU timer comparison interrupt.' [29:29] write-only RSVD_30_30 N/A [30:30] read-only RSVD_31_31 N/A [31:31] read-only INT_MASK The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register. 0x1030 32 read-only 0x3FFFFFFF 0x3FFFFFFF MANAGEMENT_DONE_INTERRUPT_MASK management done interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [0:0] read-only RECEIVE_COMPLETE_INTERRUPT_MASK receive complete interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [1:1] read-only RECEIVE_USED_BIT_READ_INTERRUPT_MASK receive used bit read interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [2:2] read-only TRANSMIT_USED_BIT_READ_INTERRUPT_MASK transmit used bit read interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [3:3] read-only TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK transmit buffer under run interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [4:4] read-only RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only) interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [5:5] read-only AMBA_ERROR_INTERRUPT_MASK transmit frame corruption due to AMBA (AXI) error interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [6:6] read-only TRANSMIT_COMPLETE_INTERRUPT_MASK transmit complete interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [7:7] read-only UNUSED_8 Not used [8:8] read-only UNUSED_9 Not used [9:9] read-only RECEIVE_OVERRUN_INTERRUPT_MASK receive overrun interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [10:10] read-only RESP_NOT_OK_INTERRUPT_MASK bresp not OK interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [11:11] read-only PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK pause frame with non-zero pause quantum interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [12:12] read-only PAUSE_TIME_ZERO_INTERRUPT_MASK pause time zero interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [13:13] read-only PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK pause frame transmitted interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [14:14] read-only UNUSED_15 Not used [15:15] read-only UNUSED_16 Not used [16:16] read-only UNUSED_17 Not used [17:17] read-only PTP_DELAY_REQ_FRAME_RECEIVED_MASK A read of this register returns the value of the PTP delay_req frame received mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [18:18] read-only PTP_SYNC_FRAME_RECEIVED_MASK A read of this register returns the value of the PTP sync frame received mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [19:19] read-only PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK A read of this register returns the value of the PTP delay_req frame transmitted mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [20:20] read-only PTP_SYNC_FRAME_TRANSMITTED_MASK A read of this register returns the value of the PTP sync frame transmitted mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [21:21] read-only PTP_PDELAY_REQ_FRAME_RECEIVED_MASK A read of this register returns the value of the PTP pdelay_req frame received mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [22:22] read-only PTP_PDELAY_RESP_FRAME_RECEIVED_MASK A read of this register returns the value of the PTP pdelay_resp frame received mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [23:23] read-only PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK A read of this register returns the value of the PTP pdelay_req frame transmitted mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [24:24] read-only PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK A read of this register returns the value of the PTP pdelay_resp frame transmitted mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [25:25] read-only TSU_SECONDS_REGISTER_INCREMENT_MASK A read of this register returns the value of the TSU seconds register increment mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [26:26] read-only RX_LPI_INDICATION_MASK A read of this register returns the value of the RX LPI indication mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written [27:27] read-only UNUSED_28 unused [28:28] read-only TSU_TIMER_COMPARISON_MASK Enable TSU timer comparison interrupt mask. [29:29] read-only PHY_MANAGEMENT The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register. 0x1034 32 read-write 0x0 0xFFFFFFFF PHY_WRITE_READ_DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. [15:0] read-write WRITE10 Must be written with 10. [17:16] read-write REGISTER_ADDRESS Register address - specifies the register in the PHY to access. [22:18] read-write PHY_ADDRESS PHY address. [27:23] read-write OPERATION Operation. For a Clause 45 frame: 00 is an addr, 01 is a write, 10 is a post read increment, 11 is a read frame. For a Clause 22 frame: 10 is a read, 01 is a write. [29:28] read-write WRITE1 Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame. [30:30] read-write WRITE0 Must be written with 0. [31:31] read-write PAUSE_TIME Received Pause Quantum Register 0x1038 32 read-only 0x0 0xFFFF QUANTUM Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times. [15:0] read-only TX_PAUSE_QUANTUM Transmit Pause Quantum Register 0x103C 32 read-write 0xFFFFFFFF 0xFFFFFFFF QUANTUM Transmit pause quantum - written with the pause quantum value for pause frame transmission. [15:0] read-write QUANTUM_P1 Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1. [31:16] read-write PBUF_TXCUTTHRU Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. TX Partial Store and Forward 0x1040 32 read-write 0x1FF 0x800001FF DMA_TX_CUTTHRU_THRESHOLD Watermark value. This value must be >= 0x9. The reset value depends on the value of the configuration option `gem_tx_pbuf_addr, which is defined in the verilog defs configuration file. The value chosen for the generation of the userguide was `gem_tx_pbuf_addr = 9 [8:0] read-write DMA_TX_CUTTHRU Enable TX partial store and forward operation [31:31] read-write PBUF_RXCUTTHRU RX Partial Store and Forward 0x1044 32 read-write 0xFF 0x800000FF DMA_RX_CUTTHRU_THRESHOLD Watermark value. The reset value depends on the value of the configuration option `gem_rx_pbuf_addr, which is defined in the verilog defs configuration file. The value chosen for the generation of the userguide was `gem_rx_pbuf_addr = 8. [7:0] read-write DMA_RX_CUTTHRU Enable RX partial store and forward operation [31:31] read-write JUMBO_MAX_LENGTH Maximum Jumbo Frame Size. 0x1048 32 read-write 0x600 0x3FFF JUMBO_MAX_LENGTH Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value. [13:0] read-write EXTERNAL_FIFO_INTERFACE Not presents. 0x104C 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only AXI_MAX_PIPELINE Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v) 0x1054 32 read-write 0x101 0x1FFFF AR2R_MAX_PIPELINE Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel. [7:0] read-write AW2W_MAX_PIPELINE Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel. [15:8] read-write USE_AW2B_FILL For the write issuing capability as defined in bits 15:8 of this register, select whether the max number of transactions operates between the AW to W AXI channel or the AW to B channel. Set to 0 to operate between the AW and W channels. Set to 1 to operate between the AW and B channels. [16:16] read-write RSC_CONTROL Not presents. Access to the register will return AHB error. 0x1058 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_MODERATION Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or transmit event occurs a timer is started and the interrupt is asserted after it times out. This limits the frequency with which the CPU receives interrupts. When interrupt moderation is enabled interrupt status bit one is always used for receive and bit 7 is always used for transmit even when priority queuing is enabled. With interrupt moderation 800ns periods are counted. GEM determines what constitutes an 800ns period by looking at the tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the network configuration register and counting tx_clk cycles. Bit 0 needs to be set to 1 for 100M operation. 0x105C 32 read-write 0x0 0xFF00FF RX_INT_MODERATION Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received. A non-zero value indicates receive interrupt moderation will be performed. [7:0] read-write TX_INT_MODERATION Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted. A non-zero value indicates transmit interrupt moderation will be performed. [23:16] read-write SYS_WAKE_TIME Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 64ns in gigabit mode, 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time. 0x1060 32 read-write 0x0 0xFFFF SYS_WAKE_TIME Count of 64ns, 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en (each interval is equivalent to eight tx_clk periods and so varies with data rate). [15:0] read-write HASH_BOTTOM The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom (31 to 0 bits) 0x1080 32 read-write 0x0 0xFFFFFFFF ADDRESS_HASH_B The first 32 bits of the hash address register. [31:0] read-write HASH_TOP Hash Register Top (63 to 32 bits) 0x1084 32 read-write 0x0 0xFFFFFFFF ADDRESS_HASH_T The remaining 32 bits of the hash address register. [31:0] read-write SPEC_ADD1_BOTTOM The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. 0x1088 32 read-write 0x0 0xFFFFFFFF ADDRESS_ADD1_B 'Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.' [31:0] read-write SPEC_ADD1_TOP Specific Address Top 0x108C 32 read-write 0x0 0x1FFFF ADDRESS_TOP Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. [15:0] read-write FILTER_TYPE This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32. [16:16] read-write SPEC_ADD2_BOTTOM The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. 0x1090 32 read-write 0x0 0xFFFFFFFF ADDRESS_BOTTOM Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. [31:0] read-write SPEC_ADD2_TOP Specific Address Top 0x1094 32 read-write 0x0 0x3F01FFFF ADDRESS_TOP Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. [15:0] read-write FILTER_TYPE This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32. [16:16] read-write FILTER_BYTE_MASK When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. [29:24] read-write SPEC_ADD3_BOTTOM The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. 0x1098 32 read-write 0x0 0xFFFFFFFF ADDRESS_BOTTOM Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. [31:0] read-write SPEC_ADD3_TOP Specific Address Top 0x109C 32 read-write 0x0 0x3F01FFFF ADDRESS_TOP Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. [15:0] read-write FILTER_TYPE This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32. [16:16] read-write FILTER_BYTE_MASK When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. [29:24] read-write SPEC_ADD4_BOTTOM The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. 0x10A0 32 read-write 0x0 0xFFFFFFFF ADDRESS_BOTTOM Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. [31:0] read-write SPEC_ADD4_TOP Specific Address Top 0x10A4 32 read-write 0x0 0x3F01FFFF ADDRESS_TOP Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. [15:0] read-write FILTER_TYPE This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32. [16:16] read-write FILTER_BYTE_MASK When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. [29:24] read-write SPEC_TYPE1 Type ID Match 1 0x10A8 32 read-write 0x0 0x8000FFFF MATCH Type ID match 1. For use in comparisons with received frames type ID/length field. [15:0] read-write ENABLE_COPY Enable copying of type ID match 1 matched frames. [31:31] read-write SPEC_TYPE2 Type ID Match 2 0x10AC 32 read-write 0x0 0x8000FFFF MATCH Type ID match 2. For use in comparisons with received frames type ID/length field. [15:0] read-write ENABLE_COPY Enable copying of type ID match 2 matched frames. [31:31] read-write SPEC_TYPE3 Type ID Match 3 0x10B0 32 read-write 0x0 0x8000FFFF MATCH Type ID match 3. For use in comparisons with received frames type ID/length field. [15:0] read-write ENABLE_COPY Enable copying of type ID match 3 matched frames. [31:31] read-write SPEC_TYPE4 Type ID Match 4 0x10B4 32 read-write 0x0 0x8000FFFF MATCH Type ID match 4. For use in comparisons with received frames type ID/length field. [15:0] read-write ENABLE_COPY Enable copying of type ID match 4 matched frames. [31:31] read-write WOL_REGISTER Wake on LAN Register. Presents in design, but feature is not supported. 0x10B8 32 read-write 0x0 0xFFFFF ADDR Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame. [15:0] read-write WOL_MASK_0 Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted. [16:16] read-write WOL_MASK_1 Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted. [17:17] read-write WOL_MASK_2 Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted. [18:18] read-write WOL_MASK_3 Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted. [19:19] read-write STRETCH_RATIO IPG stretch register 0x10BC 32 read-write 0x0 0xFFFF IPG_STRETCH IPG Stretch. Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero. [15:0] read-write STACKED_VLAN Stacked VLAN Register 0x10C0 32 read-write 0x0 0x8000FFFF MATCH User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100. [15:0] read-write ENABLE_PROCESSING Enable stacked VLAN processing mode [31:31] read-write TX_PFC_PAUSE Transmit PFC Pause Register 0x10C4 32 read-write 0x0 0xFFFF VECTOR_ENABLE Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]. [7:0] read-write VECTOR Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero. [15:8] read-write MASK_ADD1_BOTTOM Specific Address Mask 1 Bottom (31 to 0 bits) 0x10C8 32 read-write 0x0 0xFFFFFFFF ADDRESS_MASK_BOTTOM Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register (31 to 0 bits) [31:0] read-write MASK_ADD1_TOP Specific Address Mask 1 Top (47 to 32 bits) 0x10CC 32 read-write 0x0 0xFFFF ADDRESS_MASK_TOP Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register (47 to 32 bits). [15:0] read-write DMA_ADDR_OR_MASK Receive DMA Data Buffer Address Mask 0x10D0 32 read-write 0x0 0xF000000F MASK_ENABLE Data Buffer Address Mask Enable. These bits are associated directly with bits[31:28].When bit 0 is set, the AXI/AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1 is set, the AXI/AHB address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register. When bit 2 is set, the AXI/AHB address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AXI/AHB address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register. When these bits are clear, the associated value stored in bits 31:28 have no effect on the AXI/AHB address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory. [3:0] read-write MASK_VALUE_DA Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register [3:0] are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory. [31:28] read-write RX_PTP_UNICAST PTP RX unicast IP destination address 0x10D4 32 read-write 0x0 0xFFFFFFFF ADDRESS_UNICAST Unicast IP destination address. Used for detection of PTP frames on receive path. [31:0] read-write TX_PTP_UNICAST PTP TX unicast IP destination address 0x10D8 32 read-write 0x0 0xFFFFFFFF ADDRESS_UNICAST Unicast IP destination address. Used for detection of PTP frames on transmit path. [31:0] read-write TSU_NSEC_CMP TSU timer comparison value nanoseconds 0x10DC 32 read-write 0x0 0x3FFFFF COMPARISON_NSEC TSU timer comparison value (ns). Value is compared to the bits[45:24] of the TSU timer count value (upper 22 bits of nanosecond value). [21:0] read-write TSU_SEC_CMP TSU timer comparison value seconds (31 to 0 bits) 0x10E0 32 read-write 0x0 0xFFFFFFFF COMPARISON_SEC TSU timer comparison value (s). Value is compared to seconds value bits [31:0] of the TSU timer count value. [31:0] read-write TSU_MSB_SEC_CMP TSU timer comparison value seconds (47 to 32 bits) 0x10E4 32 read-write 0x0 0xFFFF COMPARISON_MSB_SEC TSU timer comparison value (s). Value is compared to the top 16 bits (most significant 16-bits {47:32] of seconds value) of the TSU timer count value. [15:0] read-write TSU_PTP_TX_MSB_SEC PTP Event Frame Transmitted Seconds Register (47 to 32 bits) 0x10E8 32 read-only 0x0 0xFFFF TIMER_SECONDS PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. [15:0] read-only TSU_PTP_RX_MSB_SEC PTP Event Frame Received Seconds Register (47 to 32 bits) 0x10EC 32 read-only 0x0 0xFFFF TIMER_SECONDS PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. [15:0] read-only TSU_PEER_TX_MSB_SEC PTP Peer Event Frame Transmitted Seconds Register (47 to 32 bits) 0x10F0 32 read-only 0x0 0xFFFF TIMER_SECONDS PTP Peer Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. [15:0] read-only TSU_PEER_RX_MSB_SEC PTP Peer Event Frame Received Seconds Register (47 to 32 bits) 0x10F4 32 read-only 0x0 0xFFFF TIMER_SECONDS PTP Peer Event Frame RX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. [15:0] read-only DPRAM_FILL_DBG The fill levels for the TX & RX packet buffers can be read using this register, including the fill level for each queue in the TX direction. 0x10F8 32 read-write 0x0 0xFFFF00F1 DMA_TX_RX_FILL_LEVEL_SELECT TX/RX Fill Level select - report the fill level for the TX or RX packet buffer. [0:0] read-write DMA_TX_Q_FILL_LEVEL_SELECT TX queue fill level select - select what TX queue to report fill levels for. [7:4] read-write DMA_TX_RX_FILL_LEVEL Fill Level - TX or RX packet buffer fill level, selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers. Read this register to determine the fill level. [31:16] read-only REVISION_REG This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value 0x10FC 32 read-only 0x70109 0xFFFFFFFF MODULE_REVISION Module revision - fixed value specific to the revision of the design which is incremented for each non-fix release of the IP. [15:0] read-only MODULE_IDENTIFICATION_NUMBER Module identification number - for the GEM, this value is fixed. [27:16] read-only FIX_NUMBER Fix number - incremented for fix releases. [31:28] read-only OCTETS_TXED_BOTTOM Octets Transmitted lower bits (31 to 0 bits) 0x1100 32 read-only 0x0 0xFFFFFFFF COUNT_BOTTOM Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. [31:0] read-only OCTETS_TXED_TOP Octets Transmitted higher bits (47 to 32 bits) 0x1104 32 read-only 0x0 0xFFFF COUNT_TOP Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. [15:0] read-only FRAMES_TXED_OK Frames Transmitted 0x1108 32 read-only 0x0 0xFFFFFFFF COUNT_OK Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted, i.e. no under run and not too many retries. Excludes pause frames. [31:0] read-only BROADCAST_TXED Broadcast Frames Transmitted 0x110C 32 read-only 0x0 0xFFFFFFFF COUNT_BROADCAST Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. [31:0] read-only MULTICAST_TXED Multicast Frames Transmitted 0x1110 32 read-only 0x0 0xFFFFFFFF COUNT_MULTICAST Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. [31:0] read-only PAUSE_FRAMES_TXED Pause Frames Transmitted 0x1114 32 read-only 0x0 0xFFFF COUNT_PAUSE Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through the external FIFO interface are counted in the frames transmitted counter. [15:0] read-only FRAMES_TXED_64 64 Byte Frames Transmitted 0x1118 32 read-only 0x0 0xFFFFFFFF COUNT_64 64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. [31:0] read-only FRAMES_TXED_65 65 to 127 Byte Frames Transmitted 0x111C 32 read-only 0x0 0xFFFFFFFF COUNT_65 65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to127 byte frames successfully transmitted without error, i.e. no under run and not too many retries. [31:0] read-only FRAMES_TXED_128 128 to 255 Byte Frames Transmitted 0x1120 32 read-only 0x0 0xFFFFFFFF COUNT_128 128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error, i.e. no under run and not too many retries. [31:0] read-only FRAMES_TXED_256 256 to 511 Byte Frames Transmitted 0x1124 32 read-only 0x0 0xFFFFFFFF COUNT_256 256 to 511 byte frames transmitted without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error, i.e. no under run and not too many retries. [31:0] read-only FRAMES_TXED_512 512 to 1023 Byte Frames Transmitted 0x1128 32 read-only 0x0 0xFFFFFFFF COUNT_512 512 to 1023 byte frames transmitted without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully transmitted without error, i.e. no under run and not too many retries. [31:0] read-only FRAMES_TXED_1024 1024 to 1518 Byte Frames Transmitted 0x112C 32 read-only 0x0 0xFFFFFFFF COUNT_1024 1024 to 1518 byte frames transmitted without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error, i.e. no under run and not too many retries. [31:0] read-only FRAMES_TXED_1519 Greater Than 1518 Byte Frames Transmitted 0x1130 32 read-only 0x0 0xFFFFFFFF COUNT_1519 Greater than 1518 byte frames transmitted without error. A 32 bit register counting the number of 1518 or above byte frames successfully transmitted without error, i.e. no under run and not too many retries. [31:0] read-only TX_UNDERRUNS Transmit Under Runs 0x1134 32 read-only 0x0 0x3FF COUNT_UN Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented. [9:0] read-only SINGLE_COLLISIONS Single Collision Frames. Presents in design but not support. 0x1138 32 read-only 0x0 0x3FFFF COUNT14 Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no under run. [17:0] read-only MULTIPLE_COLLISIONS Multiple Collision Frames. Presents in design but not support. 0x113C 32 read-only 0x0 0x3FFFF COUNT15 Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries. [17:0] read-only EXCESSIVE_COLLISIONS Excessive Collisions. Presents in design but not support. 0x1140 32 read-only 0x0 0x3FF COUNT16 Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions. [9:0] read-only LATE_COLLISIONS Late Collisions. Presents in design but not support. 0x1144 32 read-only 0x0 0x3FF COUNT17 Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e. both as a collision and a late collision. In gigabit mode, a late collision causes the transmission to be aborted, thus the single and multi collision registers are not updated. [9:0] read-only DEFERRED_FRAMES Deferred Transmission Frames. Presents in design but not support. 0x1148 32 read-only 0x0 0x3FFFF COUNT18 Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit under run. [17:0] read-only CRS_ERRORS Carrier Sense Errors. Presents in design but not support. 0x114C 32 read-only 0x0 0x3FF COUNT19 Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under run). Only incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behaviour of the other statistics registers is unaffected by the detection of a carrier sense error. [9:0] read-only OCTETS_RXED_BOTTOM Octets Received (31 to 0 bits) 0x1150 32 read-only 0x0 0xFFFFFFFF COUNT_BOTTOM Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only OCTETS_RXED_TOP Octets Received (47 to 32 bits) 0x1154 32 read-only 0x0 0xFFFF COUNT_TOP Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered. [15:0] read-only FRAMES_RXED_OK Frames Received 0x1158 32 read-only 0x0 0xFFFFFFFF COUNT_OK Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only BROADCAST_RXED Broadcast Frames Received 0x115C 32 read-only 0x0 0xFFFFFFFF COUNT_BROADCAST Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only MULTICAST_RXED Multicast Frames Received 0x1160 32 read-only 0x0 0xFFFFFFFF COUNT_MULTICAST Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only PAUSE_FRAMES_RXED Pause Frames Received 0x1164 32 read-only 0x0 0xFFFF COUNT_PAUSE Received pause frames - a 16 bit register counting the number of pause frames received without error. [15:0] read-only FRAMES_RXED_64 64 Byte Frames Received 0x1168 32 read-only 0x0 0xFFFFFFFF COUNT_64 64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only FRAMES_RXED_65 65 to 127 Byte Frames Received 0x116C 32 read-only 0x0 0xFFFFFFFF COUNT_65 65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only FRAMES_RXED_128 128 to 255 Byte Frames Received 0x1170 32 read-only 0x0 0xFFFFFFFF COUNT_128 128 to 255 byte frames received without error. A 32 bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only FRAMES_RXED_256 256 to 511 Byte Frames Received 0x1174 32 read-only 0x0 0xFFFFFFFF COUNT_256 256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only FRAMES_RXED_512 512 to 1023 Byte Frames Received 0x1178 32 read-only 0x0 0xFFFFFFFF COUNT_512 512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only FRAMES_RXED_1024 1024 to 1518 Byte Frames Received 0x117C 32 read-only 0x0 0xFFFFFFFF COUNT_1024 1024 to 1518 byte frames received without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only FRAMES_RXED_1519 1519 to maximum Byte Frames Received 0x1180 32 read-only 0x0 0xFFFFFFFF COUNT_1519 1519 to maximum byte frames received without error. A 32 bit register counting the number of 1519 byte or above frames successfully received without error. Maximum frame size is determined by the network configuration register bit 8 (1536 maximum frame size) or bit 3 (jumbo frame size). Excludes pause frames, and is only incremented if the frame is successfully filtered. [31:0] read-only UNDERSIZE_FRAMES Undersized Frames Received 0x1184 32 read-only 0x0 0x3FF COUNT_UNDERSIZE Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full duplex) that do not have either a CRC error or an alignment error. In gigabit mode, half duplex, this register counts either frames not conforming to the minimum slot time of 512 bytes or frames not conforming to the minimum frame size once bursting is active. [9:0] read-only EXCESSIVE_RX_LENGTH Oversize Frames Received 0x1188 32 read-only 0x0 0x3FF COUNT_OVERSIZE Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error. [9:0] read-only RX_JABBERS Jabbers Received 0x118C 32 read-only 0x0 0x3FF COUNT_JABBERS Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. [9:0] read-only FCS_ERRORS Frame Check Sequence Errors 0x1190 32 read-only 0x0 0x3FF COUNT_FCS_ERR Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being enabled in bit 26 of the network configuration register. [9:0] read-only RX_LENGTH_ERRORS Length Field Frame Errors 0x1194 32 read-only 0x0 0x3FF COUNT_LENGTH_ERR Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled through bit 16 of the network configuration register. [9:0] read-only RX_SYMBOL_ERRORS Receive Symbol Errors 0x1198 32 read-only 0x0 0x3FF COUNT_SYMBOL_ERR Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements in order to count a symbol error. Additionally, in gigabit half duplex mode, carrier extension errors are also recorded. Receive symbol errors will also be counted as an FCS or alignment error if the frame is between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register, 10240 bytes if bit 3 is set in the network configuration register). If the frame is larger it will be recorded as a jabber error. [9:0] read-only ALIGNMENT_ERRORS Alignment Errors 0x119C 32 read-only 0x0 0x3FF COUNT_ALIGNMENT_ERROR Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. [9:0] read-only RX_RESOURCE_ERRORS Receive Resource Errors 0x11A0 32 read-only 0x0 0x3FFFF COUNT_RESOURCE_ERR Receive resource errors - an 18 bit register counting the number of frames that were successfully received by the MAC (correct address matched frame and adequate slot time) but could not be copied to memory because no receive buffer was available. This occurs when the GEM reads a buffer descriptor with its ownership (or used) bit set. [17:0] read-only RX_OVERRUNS Receive Overruns 0x11A4 32 read-only 0x0 0x3FF COUNT_OVERRUN Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun. [9:0] read-only RX_IP_CK_ERRORS IP Header Checksum Errors 0x11A8 32 read-only 0x0 0xFF COUNT_IPCK_ERR IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. [7:0] read-only RX_TCP_CK_ERRORS TCP Checksum Errors 0x11AC 32 read-only 0x0 0xFF COUNT_TCPCK_ERR TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. [7:0] read-only RX_UDP_CK_ERRORS UDP Checksum Errors 0x11B0 32 read-only 0x0 0xFF COUNT_UDPCK_ERR UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. [7:0] read-only AUTO_FLUSHED_PKTS Receive DMA Flushed Packets 0x11B4 32 read-only 0x0 0xFFFF COUNT_FLUSHED Flushed RX packets counter. A 16 bit register counting the number of frames that have been flushed from the receive SRAM based packet buffer due to one of the following reasons .1. When partial store and forward mode is enabled or bit 24 of the DMA configuration register is enabled, a packet is received while there is no AMBA (AXI/AHB) resource. 2. When partial store and forward mode is enabled and an AMBA (AXI/AHB) error is encountered while writing the packet data to external memory. When bit 18 of the network control register(software action to flush a packet from the head of the PBUF queue) is pulsed and the GEM DMA is not currently busy. [15:0] read-only TSU_TIMER_INCR_SUB_NSEC 1588 Timer Increment Register sub nsec 0x11BC 32 read-write 0x0 0xFF00FFFF SUB_NS_INCR These are the most significant bits [23:8] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds). [15:0] read-write SUB_NS_INCR_LSB These are the least significant bits [7:0] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. [31:24] read-write TSU_TIMER_MSB_SEC 1588 Timer Seconds Register (47 to 32 bits) 0x11C0 32 read-write 0x0 0xFFFF TIMER_MSB_SEC TSU timer value (s). Most significant 16 bits of seconds timer count. The register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). Note: The value of this register is used only when the lower 32 bit register is written to. This is to ensure a single update of the 48 bit seconds value [15:0] read-write TSU_STROBE_MSB_SEC 1588 Timer Sync Strobe Seconds Register (47 to 32 bits) 0x11C4 32 read-only 0x0 0xFFFF STROBE_MSB_SEC 1588 Timer Sync Strobe Seconds. The most significant 16-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. [15:0] read-only TSU_STROBE_SEC 1588 Timer Sync Strobe Seconds Register (31 to 0 bits) 0x11C8 32 read-only 0x0 0xFFFFFFFF STROBE_SEC 1588 Timer Sync Strobe Seconds. The lowest significant 32-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. [31:0] read-only TSU_STROBE_NSEC 1588 Timer Sync Strobe Nanoseconds Register 0x11CC 32 read-only 0x0 0x3FFFFFFF STROBE_NSEC 1588 Timer Sync Strobe Nanoseconds. The value of the Timer Nanoseconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. [29:0] read-only TSU_TIMER_SEC 1588 Timer Seconds Register (31 to 0 bits) 0x11D0 32 read-write 0x0 0xFFFFFFFF TIMER_SEC 1588 Timer Seconds Register. TSU timer value (s). Least significant 32 bits of seconds timer count. This register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). [31:0] read-write TSU_TIMER_NSEC 1588 Timer Nanoseconds Register 0x11D4 32 read-write 0x0 0x3FFFFFFF TIMER_NSEC Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register. It increments by the value of the 1588 timer increment register each clock cycle (if this register is close to zero and a write to the timer adjust register causes a decrement the seconds register will be decremented if necessary and the nanoseconds register will roll back to 9999999xx(decimal)). [29:0] read-write TSU_TIMER_ADJUST This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read. 0x11D8 32 write-only 0x0 0xBFFFFFFF INCREMENT_VALUE Timer increment value. The number of nanoseconds to increment or decrement the 1588 timer nanoseconds register. If necessary the 1588 seconds register will be incremented or decremented. [29:0] write-only ADD_SUBTRACT Write as one to subtract from the 1588 timer. Write as zero to add to it. [31:31] write-only TSU_TIMER_INCR 1588 Timer Increment Register 0x11DC 32 read-write 0x0 0xFFFFFF NS_INCREMENT A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. These are the most significant 8 bits of the 32 bit timer_increment counter. The tsu_timer_incr_sub_nsec register holds the least significant 24 bits of the increment. [7:0] read-write ALT_NS_INCR Alternative nanoseconds count. Alternative count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. [15:8] read-write NUM_INCS Number of incs before alt inc. The number of increments after which the alternative increment is used. [23:16] read-write TSU_PTP_TX_SEC PTP Event Frame Transmitted Seconds Register (31 to 0 bits) 0x11E0 32 read-only 0x0 0xFFFFFFFF TIMER_PTP_SEC PTP Event Frame Transmitted Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. [31:0] read-only TSU_PTP_TX_NSEC PTP Event Frame Transmitted Nanoseconds Register 0x11E4 32 read-only 0x0 0x3FFFFFFF TIMER_PTP_NSEC PTP Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. [29:0] read-only TSU_PTP_RX_SEC PTP Event Frame Received Seconds Register (31 to 0 bits) 0x11E8 32 read-only 0x0 0xFFFFFFFF TIMER_PTP_SEC PTP Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. [31:0] read-only TSU_PTP_RX_NSEC PTP Event Frame Received Nanoseconds Register 0x11EC 32 read-only 0x0 0x3FFFFFFF TIMER_PTP_NSEC PTP Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. [29:0] read-only TSU_PEER_TX_SEC PTP Peer Event Frame Transmitted Seconds Register (31 to 0 bits) 0x11F0 32 read-only 0x0 0xFFFFFFFF TIMER_PEER_SEC PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. [31:0] read-only TSU_PEER_TX_NSEC PTP Peer Event Frame Transmitted Nanoseconds Register 0x11F4 32 read-only 0x0 0x3FFFFFFF TIMER_PEER_NSEC PTP Peer Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. [29:0] read-only TSU_PEER_RX_SEC PTP Peer Event Frame Received Seconds Register (31 to 0 bits) 0x11F8 32 read-only 0x0 0xFFFFFFFF TIMER_PEER_SEC PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. [31:0] read-only TSU_PEER_RX_NSEC PTP Peer Event Frame Received Nanoseconds Register 0x11FC 32 read-only 0x0 0x3FFFFFFF TIMER_PEER_NSEC PTP Peer Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. [29:0] read-only PCS_CONTROL Not presents. Access to the register returns AHB error. 0x1200 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only PCS_STATUS Not presents. Access to the register returns AHB error. 0x1204 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only PCS_AN_ADV Not presents. Access to the register returns AHB error. 0x1210 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only PCS_AN_LP_BASE Not presents. Access to the register returns AHB error. 0x1214 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only PCS_AN_EXP Not presents. Access to the register returns AHB error. 0x1218 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only PCS_AN_NP_TX Not presents. Access to the register returns AHB error. 0x121C 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only PCS_AN_LP_NP Not presents. Access to the register returns AHB error. 0x1220 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only PCS_AN_EXT_STATUS Not presents. Access to the register returns AHB error. 0x123C 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only TX_PAUSE_QUANTUM1 Transmit Pause Quantum Register 1 0x1260 32 read-write 0xFFFFFFFF 0xFFFFFFFF QUANTUM_P2 Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2. [15:0] read-write QUANTUM_P3 Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3. [31:16] read-write TX_PAUSE_QUANTUM2 Transmit Pause Quantum Register 2 0x1264 32 read-write 0xFFFFFFFF 0xFFFFFFFF QUANTUM_P4 Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4. [15:0] read-write QUANTUM_P5 Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5. [31:16] read-write TX_PAUSE_QUANTUM3 Transmit Pause Quantum Register 3 0x1268 32 read-write 0xFFFFFFFF 0xFFFFFFFF QUANTUM_P6 Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6. [15:0] read-write QUANTUM_P7 Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7. [31:16] read-write RX_LPI Received LPI transitions 0x1270 32 read-only 0x0 0xFFFF COUNT_LPI Count of RX LPI transitions. A count of the number of times there is a transition from receiving normal idle to receiving low power idle. Cleared on read. [15:0] read-only RX_LPI_TIME Received LPI time 0x1274 32 read-only 0x0 0xFFFFFF LPI_TIME Time in LPI. This register increments once every 16 pclk cycles when the LPI indication bit 20 is set in the receive configuration register. Cleared on read. [23:0] read-only TX_LPI Transmit LPI transitions 0x1278 32 read-only 0x0 0xFFFF COUNT_LPI Count of LPI transmissions. A count of the number of times the enable LPI transmission bit 20 goes from low to high in the transmit control register. [15:0] read-only TX_LPI_TIME Transmit LPI time 0x127C 32 read-only 0x0 0xFFFFFF LPI_TIME Time in LPI. This register increments once every 16 pclk cycles when the enable LPI transmission bit 20 is set in the transmit control register. Cleared on read. [23:0] read-only DESIGNCFG_DEBUG1 The GEM_GXL(3PIP) has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called mxeth_defs.v. 0x1280 32 read-only 0x508503 0xFFFFFFFF NO_PCS Takes the value of the `gem_no_pcs DEFINE [0:0] read-only EXCLUDE_QBV Takes the value of the `gem_exclude_qbv DEFINE [1:1] read-only RSVD_2 N/A [3:2] read-only INT_LOOPBACK Takes the value of the `gem_int_loopback DEFINE [4:4] read-only RSVD_5 N/A [5:5] read-only EXT_FIFO_INTERFACE Takes the value of the `gem_ext_fifo_interface DEFINE [6:6] read-only RSVD_7 N/A [7:7] read-only RSVD_8 N/A [8:8] read-only USER_IO Takes the value of the `gem_user_io DEFINE [9:9] read-only USER_OUT_WIDTH Takes the value of the `gem_user_out_width DEFINE if `gem_user_io is set. If 'gem_user_io is not set, the value is 0x01 [14:10] read-only USER_IN_WIDTH Takes the value of the `gem_user_in_width DEFINE `gem_user_io. If 'gem_user_io is not set, the value is 0x01 [19:15] read-only RSVD_20 N/A [20:20] read-only NO_STATS Takes the value of the `gem_no_stats DEFINE [21:21] read-only NO_SNAPSHOT Takes the value of the `gem_no_snapshot DEFINE [22:22] read-only IRQ_READ_CLEAR Takes the value of the `gem_irq_read_clear DEFINE [23:23] read-only EXCLUDE_CBS Takes the value of the `gem_exclude_cbs DEFINE [24:24] read-only DMA_BUS_WIDTH Takes the value of bits 7:5 of the `gem_dma_bus_width DEFINE. So if the define is set to decimal 64 this will return binary 010. [27:25] read-only AXI_CACHE_VALUE Takes the value of the `gem_axi_cache_value DEFINE [31:28] read-only DESIGNCFG_DEBUG2 Design Configuration Register 2 0x1284 32 read-only 0xA6310600 0xFFFF3FFF JUMBO_MAX_LENGTH Takes the value of the `gem_jumbo_max_length DEFINE [13:0] read-only HPROT_VALUE Takes the value of the `gem_hprot_value DEFINE [19:16] read-only RX_PKT_BUFFER Takes the value of the `gem_rx_pkt_buffer DEFINE [20:20] read-only TX_PKT_BUFFER Takes the value of the `gem_tx_pkt_buffer DEFINE [21:21] read-only RX_PBUF_ADDR Takes the value of the `gem_rx_pbuf_addr DEFINE [25:22] read-only TX_PBUF_ADDR Takes the value of the `gem_tx_pbuf_addr DEFINE [29:26] read-only AXI Takes the value of the `gem_axi DEFINE [30:30] read-only SPRAM Takes the value of the `gem_spram DEFINE [31:31] read-only DESIGNCFG_DEBUG3 Design Configuration Register 3 0x1288 32 read-only 0x4000000 0x3F000000 NUM_SPEC_ADD_FILTERS Takes the value of the `num_spec_add_filters DEFINE [29:24] read-only DESIGNCFG_DEBUG4 Design Configuration Register 4 0x128C 32 read-only 0x0 0xFFFFFFFF RSVD_31_0 N/A [31:0] read-only DESIGNCFG_DEBUG5 Design Configuration Register 5 0x1290 32 read-only 0x518E3744 0xFFFFFFFF RX_FIFO_CNT_WIDTH Takes the value of the `gem_rx_fifo_cnt_width DEFINE [3:0] read-only TX_FIFO_CNT_WIDTH Takes the value of the `gem_tx_fifo_cnt_width DEFINE [7:4] read-only TSU Takes the value of the `gem_tsu DEFINE [8:8] read-only PHY_IDENT Takes the value of the `gem_phy_ident DEFINE [9:9] read-only DMA_BUS_WIDTH_DEF Takes the value of the `gem_dma_bus_width_def DEFINE [11:10] read-only MDC_CLOCK_DIV Takes the value of the `gem_mdc_clock_div DEFINE [14:12] read-only ENDIAN_SWAP_DEF Takes the value of the `gem_endian_swap_def DEFINE [16:15] read-only RX_PBUF_SIZE_DEF Takes the value of the `gem_rx_pbuf_size_def DEFINE [18:17] read-only TX_PBUF_SIZE_DEF Takes the value of the `gem_tx_pbuf_size_def DEFINE [19:19] read-only RX_BUFFER_LENGTH_DEF Takes the value of the `gem_rx_buffer_length_def DEFINE [27:20] read-only TSU_CLK Takes the value of the `gem_tsu_clk DEFINE [28:28] read-only AXI_PROT_VALUE Takes the value of the `gem_axi_prot_value DEFINE [31:29] read-only DESIGNCFG_DEBUG6 Design Configuration Register 6 0x1294 32 read-only 0x3020006 0xFFFFFFE DMA_PRIORITY_QUEUE1 Takes the value of the `dma_priority_queue1 DEFINE [1:1] read-only DMA_PRIORITY_QUEUE2 Takes the value of the `dma_priority_queue2 DEFINE [2:2] read-only DMA_PRIORITY_QUEUE3 Takes the value of the `dma_priority_queue3 DEFINE [3:3] read-only DMA_PRIORITY_QUEUE4 Takes the value of the `dma_priority_queue4 DEFINE [4:4] read-only DMA_PRIORITY_QUEUE5 Takes the value of the `dma_priority_queue5 DEFINE [5:5] read-only DMA_PRIORITY_QUEUE6 Takes the value of the `dma_priority_queue6 DEFINE [6:6] read-only DMA_PRIORITY_QUEUE7 Takes the value of the `dma_priority_queue7 DEFINE [7:7] read-only DMA_PRIORITY_QUEUE8 Takes the value of the `dma_priority_queue8 DEFINE [8:8] read-only DMA_PRIORITY_QUEUE9 Takes the value of the `dma_priority_queue9 DEFINE [9:9] read-only DMA_PRIORITY_QUEUE10 Takes the value of the `dma_priority_queue10 DEFINE [10:10] read-only DMA_PRIORITY_QUEUE11 Takes the value of the `dma_priority_queue11 DEFINE [11:11] read-only DMA_PRIORITY_QUEUE12 Takes the value of the `dma_priority_queue12 DEFINE [12:12] read-only DMA_PRIORITY_QUEUE13 Takes the value of the `dma_priority_queue13 DEFINE [13:13] read-only DMA_PRIORITY_QUEUE14 Takes the value of the `dma_priority_queue14 DEFINE [14:14] read-only DMA_PRIORITY_QUEUE15 Takes the value of the `dma_priority_queue15 DEFINE [15:15] read-only TX_PBUF_QUEUE_SEGMENT_SIZE Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE [19:16] read-only EXT_TSU_TIMER Takes the value of the `gem_ext_tsu_timer DEFINE [20:20] read-only TX_ADD_FIFO_IF Takes the value of the `gem_tx_add_fifo_if DEFINE [21:21] read-only HOST_IF_SOFT_SELECT Takes the value of the `gem_host_if_soft_select DEFINE [22:22] read-only DMA_ADDR_WIDTH_IS_64B Takes the value of the `gem_dma_addr_width_is_64b DEFINE [23:23] read-only PFC_MULTI_QUANTUM Takes the value of the `gem_pfc_multi_quantum DEFINE [24:24] read-only PBUF_CUTTHRU Takes the value of the `gem_pbuf_cutthru DEFINE [25:25] read-only PBUF_RSC Takes the value of the `gem_pbuf_rsc DEFINE [26:26] read-only PBUF_LSO Takes the value of the `gem_pbuf_lso DEFINE [27:27] read-only DESIGNCFG_DEBUG7 Design Configuration Register 7 0x1298 32 read-only 0x1 0xFFFFFFFF X_PBUF_NUM_SEGMENTS_Q0 Takes the value of the `gem_tx_pbuf_num_segments_q0 DEFINE [3:0] read-only X_PBUF_NUM_SEGMENTS_Q1 Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE [7:4] read-only X_PBUF_NUM_SEGMENTS_Q2 Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE [11:8] read-only X_PBUF_NUM_SEGMENTS_Q3 Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE [15:12] read-only X_PBUF_NUM_SEGMENTS_Q4 Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE [19:16] read-only X_PBUF_NUM_SEGMENTS_Q5 Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE [23:20] read-only X_PBUF_NUM_SEGMENTS_Q6 Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE [27:24] read-only X_PBUF_NUM_SEGMENTS_Q7 Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE [31:28] read-only DESIGNCFG_DEBUG8 Design Configuration Register 8 0x129C 32 read-only 0x10100820 0xFFFFFFFF NUM_SCR2_COMPARE_REGS Takes the value of the `num_scr2_compare_regs DEFINE [7:0] read-only NUM_SCR2_ETHTYPE_REGS Takes the value of the `num_scr2_ethtype_regs DEFINE [15:8] read-only NUM_TYPE2_SCREENERS Takes the value of the `num_type2_screeners DEFINE [23:16] read-only NUM_TYPE1_SCREENERS Takes the value of the `num_type1_screeners DEFINE [31:24] read-only DESIGNCFG_DEBUG9 Design Configuration Register 9 0x12A0 32 read-only 0x0 0xFFFFFFFF TX_PBUF_NUM_SEGMENTS_Q8 Takes the value of the `gem_tx_pbuf_num_segments_q8 DEFINE [3:0] read-only TX_PBUF_NUM_SEGMENTS_Q9 Takes the value of the `gem_tx_pbuf_num_segments_q9 DEFINE [7:4] read-only TX_PBUF_NUM_SEGMENTS_Q10 Takes the value of the `gem_tx_pbuf_num_segments_q10 DEFINE [11:8] read-only TX_PBUF_NUM_SEGMENTS_Q11 Takes the value of the `gem_tx_pbuf_num_segments_q11 DEFINE [15:12] read-only TX_PBUF_NUM_SEGMENTS_Q12 Takes the value of the `gem_tx_pbuf_num_segments_q12 DEFINE [19:16] read-only TX_PBUF_NUM_SEGMENTS_Q13 Takes the value of the `gem_tx_pbuf_num_segments_q13 DEFINE [23:20] read-only TX_PBUF_NUM_SEGMENTS_Q14 Takes the value of the `gem_tx_pbuf_num_segments_q14 DEFINE [27:24] read-only TX_PBUF_NUM_SEGMENTS_Q15 Takes the value of the `gem_tx_pbuf_num_segments_q15 DEFINE [31:28] read-only DESIGNCFG_DEBUG10 Design Configuration Register 10 0x12A4 32 read-only 0x4411111 0xFFFFFFFF AXI_RX_DESCR_WR_BUFF_BITS Takes the value of the `gem_axi_rx_descr_wr_buff_bits DEFINE [3:0] read-only AXI_TX_DESCR_WR_BUFF_BITS Takes the value of the `gem_axi_tx_descr_wr_buff_bits DEFINE [7:4] read-only AXI_RX_DESCR_RD_BUFF_BITS Takes the value of the `gem_axi_rx_descr_rd_buff_bits DEFINE [11:8] read-only AXI_TX_DESCR_RD_BUFF_BITS Takes the value of the `gem_axi_tx_descr_rd_buff_bits DEFINE [15:12] read-only AXI_ACCESS_PIPELINE_BITS Takes the value of the `gem_axi_access_pipeline_bits DEFINE [19:16] read-only RX_PBUF_DATA Takes the value of the `gem_rx_pbuf_data DEFINE. 1 - The RX DPRAM has a datawidth of 32bits. 2 - The RX DPRAM has a datawidth of 64bits. 4 - RX The DPRAM has a datawidth of 128bits [23:20] read-only TX_PBUF_DATA Takes the value of the `gem_tx_pbuf_data DEFINE. 1 - The TX DPRAM has a datawidth of 32bits. 2 - The TX DPRAM has a datawidth of 64bits. 4 - The TX DPRAM has a datawidth of 128bits [27:24] read-only EMAC_BUS_WIDTH Takes the value of the `gem_emac_bus_width DEFINE. 1 - The MAC has a datawidth of 32bits. 2 - The MAC has a datawidth of 64bits. 4 - The MAC has a datawidth of 128bits [31:28] read-only SPEC_ADD5_BOTTOM Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error. 0x1300 32 read-only 0x0 0xFFFFFFFF RSVD_31_0 Write ignore, read 0 [31:0] read-only SPEC_ADD5_TOP Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error. 0x1304 32 read-only 0x0 0xFFFFFFFF RSVD_31_0 Write ignore, read 0 [31:0] read-only SPEC_ADD36_BOTTOM Not presents. 0x13F8 32 read-only 0x0 0xFFFFFFFF RSVD_31_0 Write ignore, read 0 [31:0] read-only SPEC_ADD36_TOP Not presents. 0x13FC 32 read-only 0x0 0xFFFFFFFF RSVD_31_0 Write ignore, read 0 [31:0] read-only INT_Q1_STATUS Priority queue Interrupt Status Register 0x1400 32 read-only 0x0 0x8E6 RECEIVE_COMPLETE Receive complete [1:1] read-only RX_USED_BIT_READ RX used bit read [2:2] read-only RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION Retry limit exceeded or late collision [5:5] read-only AMBA_ERROR Transmit frame corruption due to AMBA (AXI/AHB) error set if an error occurs whilst midway through reading transmit frame from the external memory, including HRESP (AHB), RRESP and BRESP errors (AXI) and buffers exhausted mid frame [6:6] read-only TRANSMIT_COMPLETE Transmit complete [7:7] read-only RESP_NOT_OK bresp not OK [11:11] read-only INT_Q2_STATUS Priority queue Interrupt Status Register 0x1404 32 read-only 0x0 0x8E6 RECEIVE_COMPLETE Receive complete [1:1] read-only RX_USED_BIT_READ RX used bit read [2:2] read-only RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION Retry limit exceeded or late collision [5:5] read-only AMBA_ERROR Transmit frame corruption due to AMBA (AXI/AHB) error set if an error occurs whilst midway through reading transmit frame from the external memory, including HRESP(AHB), RRESP and BRESP errors (AXI) and buffers exhausted mid frame [6:6] read-only TRANSMIT_COMPLETE Transmit complete [7:7] read-only RESP_NOT_OK bresp not OK [11:11] read-only INT_Q3_STATUS int_q3_status to int_q15_status doesn't present. Access to the register returns AHB error. 0x1408 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q15_STATUS Not presents. 0x1438 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only TRANSMIT_Q1_PTR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. 0x1440 32 read-write 0x0 0xFFFFFFFD DMA_TX_DIS_Q Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. [0:0] read-write DMA_TX_Q_PTR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses. [31:2] read-write TRANSMIT_Q2_PTR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. 0x1444 32 read-write 0x0 0xFFFFFFFD DMA_TX_DIS_Q Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. [0:0] read-write DMA_TX_Q_PTR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses [31:2] read-write TRANSMIT_Q3_PTR transmit_q3_ptr to transmit_q15_ptr doesn't present. Access to the register returns AHB error. 0x1448 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. [31:0] read-only TRANSMIT_Q15_PTR Not presents. 0x1478 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only RECEIVE_Q1_PTR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. 0x1480 32 read-write 0x0 0xFFFFFFFD DMA_RX_DIS_Q Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. [0:0] read-write DMA_RX_Q_PTR Receive buffer queue base address - written with the address of the start of the receive queue. [31:2] read-write RECEIVE_Q2_PTR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. 0x1484 32 read-write 0x0 0xFFFFFFFD DMA_RX_DIS_Q Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. [0:0] read-write DMA_RX_Q_PTR Receive buffer queue base address - written with the address of the start of the receive queue. [31:2] read-write RECEIVE_Q3_PTR Not presents. Start address register doesn't present for queue3 ~ queue7. 0x1488 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only RECEIVE_Q7_PTR Not presents. 0x1498 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only DMA_RXBUF_SIZE_Q1 Receive Buffer queue 1 Size 0x14A0 32 read-write 0x18 0xFF DMA_RX_Q_BUF_SIZE DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes. 0x01 corresponds to buffers of 64 bytes. 0x02 corresponds to 128 bytes etc. For example: 0x02: 128 byte 0x18: 1536 byte (1*max length frame/buffer) 0xA0: 10240 byte (1*10K jumbo frame/buffer) Note that this value should never be written as zero. Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. [7:0] read-write DMA_RXBUF_SIZE_Q2 Receive Buffer queue 2 Size 0x14A4 32 read-write 0x18 0xFF DMA_RX_Q_BUF_SIZE DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes. 0x01 corresponds to buffers of 64 bytes. 0x02 corresponds to 128 bytes etc. For example: 0x02: 128 byte 0x18: 1536 byte (1*max length frame/buffer) 0xA0: 10240 byte (1*10K jumbo frame/buffer) Note that this value should never be written as zero. Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. [7:0] read-write DMA_RXBUF_SIZE_Q3 dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present. 0x14A8 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes. 0x01 corresponds to buffers of 64 bytes. 0x02 corresponds to 128 bytes etc. For example: 0x02: 128 byte 0x18: 1536 byte (1*max length frame/buffer) 0xA0: 10240 byte (1*10K jumbo frame/buffer) Note that this value should never be written as zero. Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. [31:0] read-only DMA_RXBUF_SIZE_Q7 Not presents. 0x14B8 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only CBS_CONTROL The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTranmsitRate. 1Gb/s = 32'h07735940 (125 Mbytes/s), 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 32'h002625A0 (2.5 Mnibbles/s). If 50 percent of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32'h07735940/2. Note that Credit-Based Shaping should be disabled prior to updating the IdleSlope values. As another example, for a 1722 audio packet with a payload of 6 samples per channel, the packet size would be 7 (preamble) + 1 (SFD) + 50 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a rate of 8000 packets per second, the desired rate would 110 x 8000 bytes per second, so the programmed idleSlope value would be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In practice, the actual transmission rate will be vary slightly from that calculated. In this case, the idleSlope value should be recalibrated based on the variance between the measured and expected rate, and in this case very accurate transmission rates can be achieved. 0x14BC 32 read-write 0x0 0x3 CBS_ENABLE_QUEUE_A Enable Credit-Based Shaping on the highest priority queue (queue A). Write 1 to enable [0:0] read-write CBS_ENABLE_QUEUE_B Enable Credit-Based shaping on the 2nd highest priority queue (queue B). Write 1 to enable [1:1] read-write CBS_IDLESLOPE_Q_A queue A is the highest priority queue. This would be queue 8 in an 8 queue configuration. 0x14C0 32 read-write 0x0 0xFFFFFFFF IDLESLOPE_A IdleSlope value for queue A in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation [31:0] read-write CBS_IDLESLOPE_Q_B queue B is the 2nd highest priority queue. This would be queue 7 in an 8 queue configuration. 0x14C4 32 read-write 0x0 0xFFFFFFFF IDLESLOPE_B IdleSlope value for queue B in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation [31:0] read-write UPPER_TX_Q_BASE_ADDR Upper 32 bits of transmit buffer descriptor queue base address. 0x14C8 32 read-write 0x0 0xFFFFFFFF UPPER_TX_Q_BASE_ADDR Upper 32 bits of transmit buffer descriptor queue base address. Used when 64 bit addressing is enabled. (In releases earlier to 1p06f2 this register also affected the receive descriptor queue.) [31:0] read-write TX_BD_CONTROL TX BD control register 0x14CC 32 read-write 0x0 0x30 TX_BD_TS_MODE TX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames [5:4] read-write RX_BD_CONTROL RX BD control register 0x14D0 32 read-write 0x0 0x30 RX_BD_TS_MODE RX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames [5:4] read-write UPPER_RX_Q_BASE_ADDR Upper 32 bits of receive buffer descriptor queue base address. 0x14D4 32 read-write 0x0 0xFFFFFFFF UPPER_RX_Q_BASE_ADDR Upper 32 bits of receive buffer descriptor queue base address. Used when 64 bit addressing is enabled. [31:0] read-write HIDDEN_REG0 Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_10m 12'h4e0 // 10M Port TX Rate *** HIDDEN Register ***'. Default value of cbs related hidden registers (0x14E0~0x14E8) are depicted in cbs_control register. 0x14E0 32 read-write 0x2625A0 0xFFFFFFFF HIDDEN0_FIELD default value is defined per description of register cbs_control. [31:0] read-write HIDDEN_REG1 Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_100m 12'h4e4 // 100M Port TX Rate *** HIDDEN Register ***' 0x14E4 32 read-write 0x17D7840 0xFFFFFFFF HIDDEN1_FIELD default value is defined per description of register cbs_control. [31:0] read-write HIDDEN_REG2 Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_1g 12'h4e8 // 1G Port TX Rate *** HIDDEN Register ***' 0x14E8 32 read-write 0x7735940 0xFFFFFFFF HIDDEN2_FIELD default value is defined per description of register cbs_control. [31:0] read-write HIDDEN_REG3 Hidden registers defined in edma_defs.v '`define gem_wd_counter 12'h4ec // *** HIDDEN Register ***'. 0x14EC 32 read-write 0x7 0xF HIDDEN3_FIELD default value is defined per description of register cbs_control. [3:0] read-write HIDDEN_REG4 Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold0 12'h4f8 // AXI full threshold setting *** HIDDEN Register ***'. Note. When using AXI mode with a single port ram ( gem_spram == 1) mode and a 32b dma bus width ( gem_dma_bus_width == 32 or bits 22 to 21 of the network_config register are set to 0) the AXI hidden registers (0x14F8 and 0x14FC) need to be updated (these registers are used for fine tuning AXI dma bursts and normally should not be touched). 0x14F8 32 read-write 0x60008 0x1FF01FF HIDDEN4_FIELD_L The valid bits is defined by `gem_tx_pbuf_addr. [8:0] read-write HIDDEN4_FIELD_H The valid bits is defined by `gem_tx_pbuf_addr. [24:16] read-write HIDDEN_REG5 Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold1 12'h4fc // AXI full threshold setting *** HIDDEN Register ***'. 0x14FC 32 read-write 0x0 0x1FF01FF HIDDEN5_FIELD_L The valid bits is defined by `gem_tx_pbuf_addr. [8:0] read-write HIDDEN5_FIELD_H The valid bits is defined by `gem_tx_pbuf_addr. [24:16] read-write SCREENING_TYPE_1_REGISTER_0 Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11 to 4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27 to 12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 2 to 0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. 0x1500 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_1 screening type 1 register 1, same as screening_type_1_register_0 0x1504 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_2 screening type 1 register 2, same as screening_type_1_register_0 0x1508 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_3 screening type 1 register 3, same as screening_type_1_register_0 0x150C 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_4 screening type 1 register 4, same as screening_type_1_register_0 0x1510 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_5 screening type 1 register 5, same as screening_type_1_register_0 0x1514 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_6 screening type 1 register 6, same as screening_type_1_register_0 0x1518 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_7 screening type 1 register 7, same as screening_type_1_register_0 0x151C 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_8 screening type 1 register 8, same as screening_type_1_register_0 0x1520 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_9 screening type 1 register 9, same as screening_type_1_register_0 0x1524 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_10 screening type 1 register 10, same as screening_type_1_register_0 0x1528 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_11 screening type 1 register 11, same as screening_type_1_register_0 0x152C 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_12 screening type 1 register 12, same as screening_type_1_register_0 0x1530 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_13 screening type 1 register 13, same as screening_type_1_register_0 0x1534 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_14 screening type 1 register 14, same as screening_type_1_register_0 0x1538 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_1_REGISTER_15 screening type 1 register 15, same as screening_type_1_register_0 0x153C 32 read-write 0x0 0x3FFFFFFF QUEUE_NUMBER Queue Number (0 to 15) [3:0] read-write DSTC_MATCH DS/TC Match [11:4] read-write UDP_PORT_MATCH UDP Port Match [27:12] read-write DSTC_ENABLE DS/TC Enable [28:28] read-write UDP_PORT_MATCH_ENABLE UDP port match enable [29:29] read-write SCREENING_TYPE_2_REGISTER_0 Screener Type 2 match registers operate independently of screener type 1 registers and offer additional match capabilities, extending the capabilities into vendor specific protocols. 0x1540 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_1 screening type 2 register 1, same as screening_type_2_register_0 0x1544 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_2 screening type 2 register 2, same as screening_type_2_register_0 0x1548 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_3 screening type 2 register 3, same as screening_type_2_register_0 0x154C 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_4 screening type 2 register 4, same as screening_type_2_register_0 0x1550 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_5 screening type 2 register 5, same as screening_type_2_register_0 0x1554 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_6 screening type 2 register 6, same as screening_type_2_register_0 0x1558 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_7 screening type 2 register 7, same as screening_type_2_register_0 0x155C 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_8 screening type 2 register 8, same as screening_type_2_register_0 0x1560 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_9 screening type 2 register 9, same as screening_type_2_register_0 0x1564 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_10 screening type 2 register 10, same as screening_type_2_register_0 0x1568 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_11 screening type 2 register 11, same as screening_type_2_register_0 0x156C 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_12 screening type 2 register 12, same as screening_type_2_register_0 0x1570 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_13 screening type 2 register 13, same as screening_type_2_register_0 0x1574 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_14 screening type 2 register 14, same as screening_type_2_register_0 0x1578 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only SCREENING_TYPE_2_REGISTER_15 screening type 2 register 15, same as screening_type_2_register_0 0x157C 32 read-write 0x0 0xFFFFFFFF QUEUE_NUMBER 'Queue Number (0 to 15)' [3:0] read-write VLAN_PRIORITY 'VLAN Priority' [6:4] read-write RSVD_7 N/A [7:7] read-write VLAN_ENABLE 'VLAN Enable' [8:8] read-write INDEX 'Index to screener type 2 EtherType register' [11:9] read-write ETHERTYPE_ENABLE 'EtherType Enable' [12:12] read-write COMPARE_A 'Compare A - Index to screener type 2 Compare register ' [17:13] read-write COMPARE_A_ENABLE 'Compare A Enable' [18:18] read-write COMPARE_B 'Compare B - Index to screener type 2 Compare register' [23:19] read-write COMPARE_B_ENABLE 'Compare B Enable' [24:24] read-write COMPARE_C 'Compare C - Index to screener type 2 Compare register' [29:25] read-write COMPARE_C_ENABLE 'Compare C Enable' [30:30] read-write RSVD_31 N/A [31:31] read-only TX_SCHED_CTRL This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority, with the top indexed queue having overall priority 0x1580 32 read-write 0x0 0xFFFFFFFF TX_SCHED_Q0 'Queue 0 selection. 00 : Fixed Priority 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected. 10 : DWRR Enabled 11 : ETS Enabled' [1:0] read-write TX_SCHED_Q1 'Queue 1 selection. 00 : Fixed Priority 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected. 10 : DWRR Enabled 11 : ETS Enabled' [3:2] read-write TX_SCHED_Q2 'Queue 2 selection. 00 : Fixed Priority 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected. 10 : DWRR Enabled 11 : ETS Enabled [5:4] read-write TX_SCHED_Q3 Write ignore, read 0 [7:6] read-only REMOVED_31_8 Write ignore, read 0 [31:8] read-only BW_RATE_LIMIT_Q0TO3 This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3. 0x1590 32 read-write 0x0 0xFFFFFFFF DWRR_ETS_WEIGHT_Q0 'DWRR Weighting / ETS Bandwidth Allocation for queue 0' [7:0] read-write DWRR_ETS_WEIGHT_Q1 'DWRR Weighting / ETS Bandwidth Allocation for queue 1' [15:8] read-write DWRR_ETS_WEIGHT_Q2 'DWRR Weighting / ETS Bandwidth Allocation for queue 2' [23:16] read-write DWRR_ETS_WEIGHT_Q3 Write ignore, read 0 [31:24] read-only BW_RATE_LIMIT_Q4TO7 Not presents. MXETH has only 3 queues. Access to the register returns AHB error. 0x1594 32 read-write 0x0 0xFFFFFFFF REMOVED_31_0 'DWRR Weighting / ETS Bandwidth Allocation for queue 0' [31:0] read-write BW_RATE_LIMIT_Q8TO11 Not presents. MXETH has only 3 queues. Access to the register returns AHB error. 0x1598 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only BW_RATE_LIMIT_Q12TO15 Not presents. MXETH has only 3 queues. Access to the register returns AHB error. 0x159C 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only TX_Q_SEG_ALLOC_Q0TO7 This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues, for queues 0 to 7. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog configuration defs file - for the configuration used to generate this register description, the total number of segments was set to '16'). Those segments can then be freely distributed across the active queues, in powers of 2. I.e. a value of 0 would mean 1 segment has been allocated to the queue. A value of 1 would mean 2 segments, a value of 2 means 4 segments and so on. The reset values of these registers are defined in the configuration defs file. 0x15A0 32 read-write 0x1 0xFFFFFFFF SEGMENT_ALLOC_Q0 Number of segments allocated to q0. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted. The default value is determined by `gem_tx_pbuf_num_segments_q0 [2:0] read-write RSVD_3_3 N/A [3:3] read-only SEGMENT_ALLOC_Q1 Number of segments allocated to q1. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted [6:4] read-write RSVD_7_7 N/A [7:7] read-only SEGMENT_ALLOC_Q2 Number of segments allocated to q2. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted [10:8] read-write RSVD_11_11 Write ignore, read 0 [11:11] read-only REMOVED_14_12 Write ignore, read 0 [14:12] read-only RSVD_15_15 Write ignore, read 0 [15:15] read-only REMOVED_18_16 Write ignore, read 0 [18:16] read-only RSVD_19_19 Write ignore, read 0 [19:19] read-only REMOVED_22_20 Write ignore, read 0 [22:20] read-only RSVD_23 Write ignore, read 0 [23:23] read-only REMOVED_26_24 Write ignore, read 0 [26:24] read-only RSVD_27_27 Write ignore, read 0 [27:27] read-only REMOVED_30_28 Write ignore, read 0 [30:28] read-only RSVD_31_31 Write ignore, read 0 [31:31] read-only TX_Q_SEG_ALLOC_Q8TO15 Not presents. Access to the register returns AHB error. 0x15A4 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only RECEIVE_Q8_PTR receive_q8_ptr to receive_q15_ptr doesn't present. Access to the register returns AHB error. 0x15C0 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only RECEIVE_Q15_PTR Not presents. 0x15DC 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only DMA_RXBUF_SIZE_Q8 dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present. Access to the register returns AHB error. 0x15E0 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only DMA_RXBUF_SIZE_Q15 Not presents. 0x15FC 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q1_ENABLE At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero. 0x1600 32 write-only 0x0 0x8E6 ENABLE_RECEIVE_COMPLETE_INTERRUPT Enable Receive complete interrupt [1:1] write-only ENABLE_RX_USED_BIT_READ_INTERRUPT Enable RX used bit read interrupt [2:2] write-only ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT Enable Retry limit exceeded or late collision interrupt [5:5] write-only ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt [6:6] write-only ENABLE_TRANSMIT_COMPLETE_INTERRUPT Enable Transmit complete interrupt [7:7] write-only ENABLE_RESP_NOT_OK_INTERRUPT Enable bresp not OK interrupt [11:11] write-only INT_Q2_ENABLE At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero. 0x1604 32 write-only 0x0 0x8E6 ENABLE_RECEIVE_COMPLETE_INTERRUPT Enable Receive complete interrupt [1:1] write-only ENABLE_RX_USED_BIT_READ_INTERRUPT Enable RX used bit read interrupt [2:2] write-only ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT Enable Retry limit exceeded or late collision interrupt [5:5] write-only ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt [6:6] write-only ENABLE_TRANSMIT_COMPLETE_INTERRUPT Enable Transmit complete interrupt [7:7] write-only ENABLE_RESP_NOT_OK_INTERRUPT Enable bresp not OK interrupt [11:11] write-only INT_Q3_ENABLE int_q3_enable to int_q7_enable doesn't present. Access to the register returns AHB error. 0x1608 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q7_ENABLE Not presents. 0x1618 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q1_DISABLE Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero. 0x1620 32 write-only 0x0 0x8E6 DISABLE_RECEIVE_COMPLETE_INTERRUPT Disable Receive complete interrupt [1:1] write-only DISABLE_RX_USED_BIT_READ_INTERRUPT Disable RX used bit read interrupt [2:2] write-only DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT Disable Retry limit exceeded or late collision interrupt [5:5] write-only DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT Disable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt [6:6] write-only DISABLE_TRANSMIT_COMPLETE_INTERRUPT Disable Transmit complete interrupt [7:7] write-only DISABLE_RESP_NOT_OK_INTERRUPT Disable bresp not OK interrupt [11:11] write-only INT_Q2_DISABLE Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero. 0x1624 32 write-only 0x0 0x8E6 DISABLE_RECEIVE_COMPLETE_INTERRUPT Disable Receive complete interrupt [1:1] write-only DISABLE_RX_USED_BIT_READ_INTERRUPT Disable RX used bit read interrupt [2:2] write-only DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT Disable Retry limit exceeded or late collision interrupt [5:5] write-only DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT Disable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt [6:6] write-only DISABLE_TRANSMIT_COMPLETE_INTERRUPT Disable Transmit complete interrupt [7:7] write-only DISABLE_RESP_NOT_OK_INTERRUPT Disable bresp not OK interrupt [11:11] write-only INT_Q3_DISABLE int_q3_disable to int_q7_disable doesn't present. Access to the register returns AHB error. 0x1628 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q7_DISABLE Not presents. 0x1638 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q1_MASK The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register. 0x1640 32 read-only 0x8E6 0x8E6 RECEIVE_COMPLETE_INTERRUPT_MASK receive complete interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [1:1] read-only RX_USED_INTERRUPT_MASK A read of this register returns the value of the RX Used interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [2:2] read-only RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK retry limit exceeded or late collision interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [5:5] read-only AMBA_ERROR_INTERRUPT_MASK A read of this register returns the value of the AMBA (AXI/AHB) error interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [6:6] read-only TRANSMIT_COMPLETE_INTERRUPT_MASK transmit complete interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [7:7] read-only RESP_NOT_OK_INTERRUPT_MASK bresp not OK interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [11:11] read-only INT_Q2_MASK The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register. 0x1644 32 read-only 0x8E6 0x8E6 RECEIVE_COMPLETE_INTERRUPT_MASK receive complete interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [1:1] read-only RX_USED_INTERRUPT_MASK A read of this register returns the value of the RX Used interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [2:2] read-only RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK retry limit exceeded or late collision interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [5:5] read-only AMBA_ERROR_INTERRUPT_MASK A read of this register returns the value of the AMBA (AXI/AHB) error interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [6:6] read-only TRANSMIT_COMPLETE_INTERRUPT_MASK transmit complete interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [7:7] read-only RESP_NOT_OK_INTERRUPT_MASK bresp not OK interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. [11:11] read-only INT_Q3_MASK int_q3_mask to int_q7_mask doesn't present. Access to the register returns AHB error. 0x1648 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q7_MASK Not presents. 0x1658 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q8_ENABLE int_q8_enable to int_q15_enable doesn't present. Access to the register returns AHB error. 0x1660 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q15_ENABLE Not presents. 0x167C 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q8_DISABLE int_q8_disable to int_q15_disable doesn't present. Access to the register returns AHB error. 0x1680 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q15_DISABLE Not presents. 0x169C 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q8_MASK int_q8_mask to int_q15_mask doesn't present. Access to the register returns AHB error. 0x16A0 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only INT_Q15_MASK Not presents. 0x16BC 32 read-only 0x0 0xFFFFFFFF REMOVED_31_0 Write ignore, read 0 [31:0] read-only SCREENING_TYPE_2_ETHERTYPE_REG_0 Ethertype Register 0x16E0 32 read-write 0x0 0xFFFFFFFF COMPARE_VALUE 'EtherType compare value' [15:0] read-write RSVD_31_16 N/A [31:16] read-only SCREENING_TYPE_2_ETHERTYPE_REG_1 Ethertype Register 0x16E4 32 read-write 0x0 0xFFFFFFFF COMPARE_VALUE 'EtherType compare value' [15:0] read-write RSVD_31_16 N/A [31:16] read-only SCREENING_TYPE_2_ETHERTYPE_REG_2 Ethertype Register 0x16E8 32 read-write 0x0 0xFFFFFFFF COMPARE_VALUE 'EtherType compare value' [15:0] read-write RSVD_31_16 N/A [31:16] read-only SCREENING_TYPE_2_ETHERTYPE_REG_3 Ethertype Register 0x16EC 32 read-write 0x0 0xFFFFFFFF COMPARE_VALUE 'EtherType compare value' [15:0] read-write RSVD_31_16 N/A [31:16] read-only SCREENING_TYPE_2_ETHERTYPE_REG_4 Ethertype Register 0x16F0 32 read-write 0x0 0xFFFFFFFF COMPARE_VALUE 'EtherType compare value' [15:0] read-write RSVD_31_16 N/A [31:16] read-only SCREENING_TYPE_2_ETHERTYPE_REG_5 Ethertype Register 0x16F4 32 read-write 0x0 0xFFFFFFFF COMPARE_VALUE 'EtherType compare value' [15:0] read-write RSVD_31_16 N/A [31:16] read-only SCREENING_TYPE_2_ETHERTYPE_REG_6 Ethertype Register 0x16F8 32 read-write 0x0 0xFFFFFFFF COMPARE_VALUE 'EtherType compare value' [15:0] read-write RSVD_31_16 N/A [31:16] read-only SCREENING_TYPE_2_ETHERTYPE_REG_7 Ethertype Register 0x16FC 32 read-write 0x0 0xFFFFFFFF COMPARE_VALUE 'EtherType compare value' [15:0] read-write RSVD_31_16 N/A [31:16] read-only TYPE2_COMPARE_0_WORD_0 'Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7 to 0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15 to 8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. ' 0x1700 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_0_WORD_1 'Type2 Compare Word 1' 0x1704 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_1_WORD_0 same as type2_compare_0_word_0 0x1708 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_1_WORD_1 same as type2_compare_0_word_1 0x170C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_2_WORD_0 same as type2_compare_0_word_0 0x1710 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_2_WORD_1 same as type2_compare_0_word_1 0x1714 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_3_WORD_0 same as type2_compare_0_word_0 0x1718 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_3_WORD_1 same as type2_compare_0_word_1 0x171C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_4_WORD_0 same as type2_compare_0_word_0 0x1720 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_4_WORD_1 same as type2_compare_0_word_1 0x1724 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_5_WORD_0 same as type2_compare_0_word_0 0x1728 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_5_WORD_1 same as type2_compare_0_word_1 0x172C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_6_WORD_0 same as type2_compare_0_word_0 0x1730 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_6_WORD_1 same as type2_compare_0_word_1 0x1734 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_7_WORD_0 same as type2_compare_0_word_0 0x1738 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_7_WORD_1 same as type2_compare_0_word_1 0x173C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_8_WORD_0 same as type2_compare_0_word_0 0x1740 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_8_WORD_1 same as type2_compare_0_word_1 0x1744 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_9_WORD_0 same as type2_compare_0_word_0 0x1748 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_9_WORD_1 same as type2_compare_0_word_1 0x174C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_10_WORD_0 same as type2_compare_0_word_0 0x1750 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_10_WORD_1 same as type2_compare_0_word_1 0x1754 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_11_WORD_0 same as type2_compare_0_word_0 0x1758 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_11_WORD_1 same as type2_compare_0_word_1 0x175C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_12_WORD_0 same as type2_compare_0_word_0 0x1760 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_12_WORD_1 same as type2_compare_0_word_1 0x1764 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_13_WORD_0 same as type2_compare_0_word_0 0x1768 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_13_WORD_1 same as type2_compare_0_word_1 0x176C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_14_WORD_0 same as type2_compare_0_word_0 0x1770 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_14_WORD_1 same as type2_compare_0_word_1 0x1774 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_15_WORD_0 same as type2_compare_0_word_0 0x1778 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_15_WORD_1 same as type2_compare_0_word_1 0x177C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_16_WORD_0 same as type2_compare_0_word_0 0x1780 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_16_WORD_1 same as type2_compare_0_word_1 0x1784 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_17_WORD_0 same as type2_compare_0_word_0 0x1788 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_17_WORD_1 same as type2_compare_0_word_1 0x178C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_18_WORD_0 same as type2_compare_0_word_0 0x1790 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_18_WORD_1 same as type2_compare_0_word_1 0x1794 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_19_WORD_0 same as type2_compare_0_word_0 0x1798 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_19_WORD_1 same as type2_compare_0_word_1 0x179C 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_20_WORD_0 same as type2_compare_0_word_0 0x17A0 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_20_WORD_1 same as type2_compare_0_word_1 0x17A4 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_21_WORD_0 same as type2_compare_0_word_0 0x17A8 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_21_WORD_1 same as type2_compare_0_word_1 0x17AC 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_22_WORD_0 same as type2_compare_0_word_0 0x17B0 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_22_WORD_1 same as type2_compare_0_word_1 0x17B4 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_23_WORD_0 same as type2_compare_0_word_0 0x17B8 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_23_WORD_1 same as type2_compare_0_word_1 0x17BC 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_24_WORD_0 same as type2_compare_0_word_0 0x17C0 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_24_WORD_1 same as type2_compare_0_word_1 0x17C4 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_25_WORD_0 same as type2_compare_0_word_0 0x17C8 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_25_WORD_1 same as type2_compare_0_word_1 0x17CC 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_26_WORD_0 same as type2_compare_0_word_0 0x17D0 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_26_WORD_1 same as type2_compare_0_word_1 0x17D4 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_27_WORD_0 same as type2_compare_0_word_0 0x17D8 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_27_WORD_1 same as type2_compare_0_word_1 0x17DC 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_28_WORD_0 same as type2_compare_0_word_0 0x17E0 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_28_WORD_1 same as type2_compare_0_word_1 0x17E4 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_29_WORD_0 same as type2_compare_0_word_0 0x17E8 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_29_WORD_1 same as type2_compare_0_word_1 0x17EC 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_30_WORD_0 same as type2_compare_0_word_0 0x17F0 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_30_WORD_1 same as type2_compare_0_word_1 0x17F4 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only TYPE2_COMPARE_31_WORD_0 same as type2_compare_0_word_0 0x17F8 32 read-write 0x0 0xFFFFFFFF MASK_VALUE These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. [15:0] read-write COMPARE_VALUE_TYPE2 2 byte Compare Value. If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [31:16] read-write TYPE2_COMPARE_31_WORD_1 same as type2_compare_0_word_1 0x17FC 32 read-write 0x0 0xFFFFFFFF OFFSET_VALUE 'Offset value in bytes' [6:0] read-write COMPARE_OFFSET 'Compare byte offset. 00 : Offset from beginning of the frame. 01 : Offset from byte after Ether Type. 10 : Offset from byte following end of IP header. 11 : Offset from byte following end of TCP/UDP header' If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. [8:7] read-write DISABLE_MASK 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. 1 - 4-byte compare value 0 - 2-byte compare, 2-byte mask ' [9:9] read-write RSVD_31_10 N/A [31:10] read-only LIN0 LIN LIN 0x40500000 0 65536 registers ERROR_CTL Error control 0x0 32 read-write 0x0 0x80EF001F CH_IDX Specifies the channel index of the channel to which HW injected channel transmitter errors applies. [4:0] read-write TX_SYNC_ERROR The synchronization field is changed from 0x55 to 0x00. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation. [16:16] read-write TX_SYNC_STOP_ERROR The synchronization field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation. [17:17] read-write TX_PARITY_ERROR In LIN mode, the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]). At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. In UART mode, a data field's parity bit is inverted. [18:18] read-write TX_PID_STOP_ERROR The PID field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation. [19:19] read-write TX_DATA_STOP_ERROR The data field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. Note: Used in UART mode. [21:21] read-write TX_CHECKSUM_ERROR The checksum field is inverted. At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation. [22:22] read-write TX_CHECKSUM_STOP_ERROR The checksum field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. [23:23] read-write ENABLED Error injection enable: '0': Disabled. '1': Enabled. [31:31] read-write TEST_CTL Test control 0x4 32 read-write 0x0 0x8001001F CH_IDX Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0, CH_NR-2], as channel index CH_NR-1 is always involved in test and cannot be connected to itself. The test mode allows BOTH of the two connected channels to be tested. Note: this testing functionality simplifies SW development, but may also be used in the field to verify correct channel functionality. [4:0] read-write MODE Test mode: '0': Partial disconnect from IOSS. This mode's isolation allows for device test without relying on an external LIN transceiver. The IOSS 'tx' IO cell can be used to observe messages outside of the device. - tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. - tx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX]. - rx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. - rx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX]. - lin_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. - lin_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. '1': Full disconnect from IOSS (the IOSS/HSIOM should disconnect 'tx_out' from the 'tx' IO cell). This mode's isolation allows for device test without effecting an operational LIN cluster. - tx_in[CH_IDX] = lin_tx_out[CH_IDX]. - tx_in[CH_NR-1] = lin_tx_out[CH_IDX]. - rx_in[CH_IDX] = lin_tx_out[CH_IDX]. - rx_in[CH_NR-1] = lin_tx_out[CH_IDX]. - lin_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. - lin_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. [16:16] read-write ENABLED Test enable: '0': Disabled. Functional mode. - tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. - tx_in[CH_NR-1] = IOSS lin_tx_in[CH_NR-1]. - rx_in[CH_IDX] = IOSS lin_rx_in[CH_IDX]. - rx_in[CH_NR-1] = IOSS lin_rx_in[CH_NR-1]. - lin_tx_out[CH_IDX] = tx_out[CH_IDX]. - lin_tx_out[CH_NR-1] = tx_out[CH_NR-1]. '1': Enabled. Test mode, specific test mode is specified by MODE. [31:31] read-write 2 256 CH[%s] LIN channel structure 0x00008000 CTL0 Control 0 0x0 32 read-write 0x400C0101 0xF91F0313 STOP_BITS STOP bit periods: '0': 1/2 bit period. '1': 1 bit period. '2': 1 1/2 bit period. '3': 2 bit periods. In LIN mode, this field should be set to '1' (the default value) . In UART mode, this field can be programmed as desired. Note: receiver STOP bit frame errors can only be detected if the number of STOP bit periods is 1 or more bit period. [1:0] read-write AUTO_EN LIN transceiver auto enable: '0': Disabled. '1': Enabled. The TX_RX_STATUS.EN_OUT field is controlled by HW. [4:4] read-write BREAK_DELIMITER_LENGTH In LIN mode, this field specifies the break delimiter length: (used in header transmission, not used in header reception). '0': 1 bit period. '1': 2 bit periods (default value). '2': 3 bit periods. '3': 4 bit periods. In UART mode, this field specifies the data field size: '0': 5 bit data field. '1': 6 bit data field. '2': 7 bit data field. '3': 8 bit data field. When the data field size is less than 8 bits, the most significant (unused) bits of the DATAx.DATAy[7:0] fields should be set to '0' for the transmitter. [9:8] read-write BREAK_WAKEUP_LENGTH Break/wakeup length (minus 1) in bit periods: '0': 1 bit period. ... '10': 11 bit periods (break length for slave nodes) ... '12': 13 bit periods (break length for master nodes) ... '30': 31 bit periods. '31': Illegal (should NOT be used!!!) This field is used for transmission/reception of BOTH break and wakeup signals. Note that these functions are mutually exclusive: - When CMD.TX_HEADER is '1', the field specifies the transmitted break field. - When CMD.TX_WAKEUP is '1', the field specifies the transmitted wakeup field. - When CMD.RX_HEADER is '1', the field specifies the to be received break field. - Otherwise, the field specifies the to be received wakeup field. Per the standard, the master wakeup duration is between 250 us and 5 ms. To support uncalibrated slaves, a slave has a detection threshold of 150 us (3 bit periods at 20 kbps). After transmission of a break or wakeup signal, the INTR.TX_BREAK_WAKEUP_DONE interrupt cause is activated. After reception of a wakeup signal, the INTR.RX_BREAK_WAKEUP_DONE interrupt cause is activated. To specify longer wakeup signals in terms of absolute time (us/ms rather than bit periods), the associated PERI clock divider value can be (temporarily) increased to make the LIN bit period longer. Note: entering bus sleep mode is achieved with the 'go-to-sleep' command. [20:16] read-write MODE Mode of operation: '0': LIN mode. '1': UART mode. [24:24] read-write LIN LIN mode. 0 UART UART mode. 1 BIT_ERROR_IGNORE Specifies behavior on a detected bit error during header or response transmission: '0': Message transfer is aborted. '1': Message transfer is NOT aborted. Note: this field does NOT effect the reporting of the bit error through INTR/STATUS.TX_HEADER/RESPONSE_BIT_ERROR; i.e. bit errors are always reported. [27:27] read-write PARITY Parity mode: '0': Even parity: even number of '1' bits (including parity). '1': Odd parity. Note: Used in UART mode only. [28:28] read-write PARITY_EN Parity generation enable: '0': Disabled. No parity bit is transferred. '1': Enabled. The parity bit is transferred after the last (most significant) data field bit. Note: Used in UART mode only. [29:29] read-write FILTER_EN RX filter (for 'lin_rx_in'): '0': No filter. '1': Median 3 (default value) operates on the last three 'lin_rx_in' values. The sequences '000', '001', '010' and '100' result in a filtered value '0'. The sequences '111', '110', '101' and '011' result in a filtered value '1'. [30:30] read-write ENABLED Channel enable: '0': Disabled. If a channel is disabled, all non-retained MMIO registers (e.g. the TX_RX_STATUS, and INTR registers) have their fields reset to their default value. '1': Enabled. [31:31] read-write CTL1 Control 1 0x4 32 read-write 0x0 0x3000000 DATA_NR Number of data fields (minus 1) in the response (not including the checksum): '0': 1 data field. '1': 2 data fields. ... '7': 8 data fields. Note: master and slave nodes need to agree upon the number of data fields before message transfer. In RX_RESPONSE case, When PID (header) is received, firmware has the time of one response data byte, to modify CTL1.DATA_NR. [2:0] read-write CHECKSUM_ENHANCED Checksum mode: '0': Classic mode. PID field is NOT included in the checksum calculation. '1': Enhanced mode. PID field is included in the checksum calculation. This mode requires special attention when the master node transmits the header and a (different) slave node transmits the response: the slave node will use the calculated partial checksum over the received PID field as a starting point for the calculation over the to be transmitted data fields. Note: If the frame identifier ID[5:0] is 0x3c or 0x3d, the classic mode will ALWAYS be used for transmission and assumed for reception, independent of the CHECKSUM_ENHANCED value. [8:8] read-write FRAME_TIMEOUT Specifies the maximum allowed length (timeout value) for a frame, frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and Tresponse_max = 1.4 x Tresponse_nom). The nominal header length Theader_nom is 34 bit periods and the nominal response length Tresponse_nom is 10 * (data_nr + 1) bit periods (data_nr is the number of data fields) Note: the LIN specification specifies the following: 'Tools and tests shall check the Tframe_max (= Theader_max + Tresponse_max). Nodes shall not check this time. The receiving node of the frame shall accept the frame up to the next frame slot (i.e. next break field), even if it is longer then Tframe_max).' [23:16] read-write FRAME_TIMEOUT_SEL Specifies the frame timeout mode: '0': No timeout functionality (default value). '1': Frame mode: detects timeout from the start of break field to checksum field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34+20 bit periods (header and a response with 1 data field). '2': Frame header mode: detects timeout from the start of break field to PID field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34 bit periods (header). '3': Frame response mode: detects timeout from the PID field STOP bits (exclusive) to checksum field STOP bits (the response space is included in the frame response). The minimum FRAME_TIMEOUT value is 20 bit periods (response with 1 data field). [25:24] read-write STATUS Status 0x8 32 read-only 0x0 0x1F03333F DATA_IDX Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0, DATA1, PID_CHECKSUM)) : '0': No data fields transferred. '1': Data field 1 transferred. ... '7': Data fields 1, 2, 3, ... and 7 transferred. '8': Data fields 1, 2, 3, ... and 8 transferred. '9': Data fields 1, 2, 3, ..., 8 and checksum field transferred. '10'-'15': Unused. Set to '0' on the start of a TX_HEADER or RX_HEADER command. [3:0] read-only HEADER_RESPONSE Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'): '0': Frame header being transferred. '1': Frame response being transferred. [4:4] read-only RX_DATA0_FRAME_ERROR Frame response, first data field frame error. HW sets this field to '1' when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command), and this data byte is 0x00. HW clears this field to '0' at the falling edge of SYNC start bit (after INTR.RX_HEADER_BREAK_WAKEUP_DONE). This field is used together with INTR.RX_RESPONSE_FRAME_ERROR to distinguish 'no response', 'error response' and 'correct response' scenarios. Note: The ongoing message transfer is NOT aborted. [5:5] read-only TX_BUSY Transmitter busy. - Set to '1' on the start of the following commands: TX_HEADER, TX_RESPONSE, TX_WAKEUP. - Set to '0' on successful completion of previous commands or when an error is detected. In 'TX_HEADER, RX_RESPONSE' case, set to '0' at the start bit falling edge in the first response data byte, after header transmission [8:8] read-only RX_BUSY Receiver busy. - Set to '1' on the start of the following commands: RX_HEADER, RX_RESPONSE. in RX_HEADER case, set at Break filed rising edge. in RX_RESPONSE case, set at the start bit falling edge in the first response data byte. - Set to '0' on successful completion of previous commands or when an error is detected. [9:9] read-only TX_DONE Transmitter done: - Set to '0' on the start of a new command. - Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble): - TX_HEADER. - TX_HEADER, TX_RESPONSE. - RX_HEADER, TX_RESPONSE. - TX_WAKEUP. [12:12] read-only RX_DONE Receiver done: - Set to '0' on the start of a new command. - Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble): - RX_HEADER, RX_RESPONSE. - TX_HEADER, RX_RESPONSE. [13:13] read-only TX_HEADER_BIT_ERROR Copy of INTR.TX_HEADER_BIT_ERROR. [16:16] read-only TX_RESPONSE_BIT_ERROR Copy of INTR.TX_RESPONSE_BIT_ERROR. [17:17] read-only RX_HEADER_FRAME_ERROR Copy of INTR.RX_HEADER_FRAME_ERROR. [24:24] read-only RX_HEADER_SYNC_ERROR Copy of INTR.RX_HEADER_SYNC_ERROR. [25:25] read-only RX_HEADER_PARITY_ERROR Copy of INTR.RX_HEADER_PARITY_ERROR. [26:26] read-only RX_RESPONSE_FRAME_ERROR Copy of INTR.RX_RESPONSE_FRAME_ERROR. [27:27] read-only RX_RESPONSE_CHECKSUM_ERROR Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR. [28:28] read-only CMD Command 0x10 32 read-write 0x0 0x307 TX_HEADER SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected): - TX_HEADER - TX_HEADER, TX_RESPONSE. - TX_HEADER, RX_RESPONSE. - RX_HEADER, TX_RESPONSE. - RX_HEADER, RX_RESPONSE. - TX_WAKEUP. The header is transmitted when the PID field STOP bits are transmitted (INTR.TX_HEADER_DONE). HW sets this field to '1', when the 'tr_cmd_tx_header' input trigger is activated. This allows for time triggered LIN message transfer. HW driven time triggered transfer eliminates the jitter that is typically associated with SW driven transfer. In UART mode, a single data field (DATA0.DATA1) is transmitted. [0:0] read-write TX_RESPONSE SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected). The response is transmitted when the checksum field STOP bits are transmitted (INTR.TX_RESPONSE_DONE). [1:1] read-write TX_WAKEUP SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected). The command generates CTL.BREAK_WAKEUP_LENGTH bit periods in the dominant state (low/'0') and transitions to the recessive state (high/'1') (INTR.TX_WAKEUP_DONE). [2:2] read-write RX_HEADER SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode). The header is received when the PID field STOP bits are received (INTR.RX_HEADER_DONE). Typically, a slave node SW sets both RX_HEADER and RX_RESPONSE to '1', anticipating a transfer of a response from the master node to this slave node. After receipt of the header PID field (INTR.RX_HEADER_PID_DONE is activated), the slave node may decide to set TX_RESPONSE to '1' (which has a higher priority than RX_RESPONSE) to transmit a response. the Break detection is performed regardless of CMD.RX_HEADER. INTR.RX_BREAK_WAKEUP_DONE will trigger at LIN_RX rising edge, when the low pulse meet CTL0.BREAK_WAKEUP_LENGTH. when Break is detected, HW check CMD.RX_HEADER before entering SYNC byte processing state. when RX_HEADER is cleared, SW has at least 11 bit times to set RX_HEADER again, before next Break is detected (RX_BREAK_WAKEUP_DONE). in this case, there is no gap, Break will never be missed. In UART mode, a single data field in received (in DATA0.DATA1). HW set this field to '0' when the data field is received, or when an error is detected. [8:8] read-write RX_RESPONSE SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected). The response is received when the checksum field STOP bits are received (INTR.RX_RESPONSE_DONE). [9:9] read-write TX_RX_STATUS TX/RX status 0x60 32 read-write 0x5000000 0x5000000 SYNC_COUNTER Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field, this fields reflects the duration of the synchronization field. Ideally, SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of eight bit period of 16 LIN channel clock periods each). - If SYNC_COUNTER is less than 128, the LIN channel clock is too slow and the PERI/PCLK divider value should be decreased. - If SYNC_COUNTER is greater than 128, the LIN channel clock is too fast and the PERI/PCLK divider value should be increased. The biggest master-slave clock discrepancy occurs when the master is slow and the slave is fast or vice versa. At a 0.5 percent master inaccuracy and a 14 percent slave inaccuracy, this results in the extreme synchronization values of (.86 * 128) / 1.005 = 109.5 and (1.14 *128) / 0.995 = 146.6. We add a little margin for a valid range of [106, 152]. Note: Only slave nodes with imprecise clocks require clock resynchronization. Master and slave nodes with precise clocks do NOT require clock resynchronization. [7:0] read-only TX_IN LIN transmitter input ('tx_in', 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality. [16:16] read-only RX_IN LIN receiver input ('rx_in', 'lin_rx_in' in functional mode). [17:17] read-only TX_OUT LIN transmitter output ('tx_out', 'lin_tx_out'). [24:24] read-only EN_OUT LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: '0': Disabled. '1': Enabled. If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver: - Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble. - After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble. Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers. [26:26] read-write PID_CHECKSUM PID and checksum 0x80 32 read-write 0x0 0x0 PID Header protected identifier (PID). - Bits 5 down to 0: frame identifier ID[5:0]. Frame identifier 0x3c is for a 'master request' frame, 0x3d is for a 'slave response' frame, 0x3e and 0x3f are for future LIN enhancements. Frame identifier ID[5:4] is optionally used for length control; i.e. specifies the number of response data fields. - Bits 1 down to 0: parity bits P[1] and P[0]. - P[1] = ! (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) - P[0] = (ID[4] ^ ID[2] ^ ID[1] ^ ID[0]) Transmission: To be transmitted PID field. SW needs to calculate the PID field parity bits P[1] and P[0]. Reception: Received PID field. Slave node SW uses the PID field to determine how to handle the response for a received frame header: TX_RESPONSE or RX_RESPONSE. [7:0] read-write CHECKSUM Checksum. Transmission: HW calculated checksum (SW does not need to calculate the checksum) over the transmitted PID field (optional per CTL.CHECKSUM_ENHANCED) and data fields. Reception: Received checksum. Note that in case of a RX_CHECKSUM_ERROR, SW can use the received PID field and the received data fields to calculate the correct checksum value. [15:8] read-only DATA0 Response data 0 0x84 32 read-write 0x0 0x0 DATA1 Data field 1. Transmission: To be transmitted data field. SW provides data field. Reception: Received data field. SW uses the data field. [7:0] read-write DATA2 Data field 2. [15:8] read-write DATA3 Data field 3. [23:16] read-write DATA4 Data field 4. [31:24] read-write DATA1 Response data 1 0x88 32 read-write 0x0 0x0 DATA5 Data field 5. [7:0] read-write DATA6 Data field 6. [15:8] read-write DATA7 Data field 7. [23:16] read-write DATA8 Data field 8. [31:24] read-write INTR Interrupt 0xC0 32 read-write 0x0 0x1F036F07 TX_HEADER_DONE HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically: - When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer. - When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. Note: used in UART mode. [0:0] read-write TX_RESPONSE_DONE HW sets this field to '1', when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. [1:1] read-write TX_WAKEUP_DONE HW sets this field to '1', when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal. [2:2] read-write RX_HEADER_DONE HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically: - When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer. - When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. Note: used in UART mode. [8:8] read-write RX_RESPONSE_DONE HW sets this field to '1', when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. Note: activation implies that RX_RESPONSE_FRAME_ERROR and RX_RESPONSE_CHECKSUM_ERROR are not activated during response reception [9:9] read-write RX_BREAK_WAKEUP_DONE HW sets this field to '1', when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal. The break or wakeup detection is always enabled, regardless of CMD register setting. [10:10] read-write RX_HEADER_SYNC_DONE HW sets this field to '1', when a synchronization field is received (including trailing STOP bits). [11:11] read-write RX_NOISE_DETECT HW sets this field to '1', when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line. Note: The ongoing frame transfer is NOT aborted. Note: Used in UART mode. [13:13] read-write TIMEOUT HW sets this field to '1', when a frame, frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL). Note: The ongoing frame transfer is NOT aborted. [14:14] read-write TX_HEADER_BIT_ERROR HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an indication of bus collisions on the LIN line. The match is performed for the Wakeup, Break, SYNC and the PID fields (for the START bit, data Byte and STOP bit). Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. Note: Used in UART mode. [16:16] read-write TX_RESPONSE_BIT_ERROR HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission). The match is performed for the data fields and the checksum field (for the START bit, data Byte and STOP bit). Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. [17:17] read-write RX_HEADER_FRAME_ERROR HW sets this field to '1', when the received START or STOP bits have an unexpected value (during header reception). Note: The ongoing message transfer is aborted (INTR.RX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. Note: Used in UART mode. [24:24] read-write RX_HEADER_SYNC_ERROR HW sets this field to '1', when the received synchronization field is not received within the synchronization counter range [106, 152] (see TX_RX_STATUS.SYNC_COUNTER). Note: The ongoing message transfer is aborted (INTR.RX_HEADER_SYNC_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. [25:25] read-write RX_HEADER_PARITY_ERROR HW sets this field to '1', when the received PID field has a parity error. Note: The ongoing message transfer is aborted (INTR.RX_PID_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. +G119 HW sets this field to '1', when the received data field has a parity error (when CTL0.PARITY_EN is '1'). [26:26] read-write RX_RESPONSE_FRAME_ERROR HW sets this field to '1', when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command, if the received data byte is 0x00. (STATUS.RX_DATA0_FRAME_ERROR is used instead). Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. [27:27] read-write RX_RESPONSE_CHECKSUM_ERROR HW sets this field to '1', when the calculated checksum over the received PID and data fields is not the same as the received checksum. Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. [28:28] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x1F036F07 TX_HEADER_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write TX_RESPONSE_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [1:1] read-write TX_WAKEUP_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [2:2] read-write RX_HEADER_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [8:8] read-write RX_RESPONSE_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [9:9] read-write RX_BREAK_WAKEUP_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [10:10] read-write RX_HEADER_SYNC_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [11:11] read-write RX_NOISE_DETECT Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [13:13] read-write TIMEOUT Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [14:14] read-write TX_HEADER_BIT_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [16:16] read-write TX_RESPONSE_BIT_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [17:17] read-write RX_HEADER_FRAME_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [24:24] read-write RX_HEADER_SYNC_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [25:25] read-write RX_HEADER_PARITY_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [26:26] read-write RX_RESPONSE_FRAME_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [27:27] read-write RX_RESPONSE_CHECKSUM_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [28:28] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x1F036F07 TX_HEADER_DONE Mask for corresponding field in INTR register. [0:0] read-write TX_RESPONSE_DONE Mask for corresponding field in INTR register. [1:1] read-write TX_WAKEUP_DONE Mask for corresponding field in INTR register. [2:2] read-write RX_HEADER_DONE Mask for corresponding field in INTR register. [8:8] read-write RX_RESPONSE_DONE Mask for corresponding field in INTR register. [9:9] read-write RX_BREAK_WAKEUP_DONE Mask for corresponding field in INTR register. [10:10] read-write RX_HEADER_SYNC_DONE Mask for corresponding field in INTR register. [11:11] read-write RX_NOISE_DETECT Mask for corresponding field in INTR register. [13:13] read-write TIMEOUT Mask for corresponding field in INTR register. [14:14] read-write TX_HEADER_BIT_ERROR Mask for corresponding field in INTR register. [16:16] read-write TX_RESPONSE_BIT_ERROR Mask for corresponding field in INTR register. [17:17] read-write RX_HEADER_FRAME_ERROR Mask for corresponding field in INTR register. [24:24] read-write RX_HEADER_SYNC_ERROR Mask for corresponding field in INTR register. [25:25] read-write RX_HEADER_PARITY_ERROR Mask for corresponding field in INTR register. [26:26] read-write RX_RESPONSE_FRAME_ERROR Mask for corresponding field in INTR register. [27:27] read-write RX_RESPONSE_CHECKSUM_ERROR Mask for corresponding field in INTR register. [28:28] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x1F036F07 TX_HEADER_DONE Logical AND of corresponding INTR and INTR_MASK fields. [0:0] read-only TX_RESPONSE_DONE Logical AND of corresponding INTR and INTR_MASK fields. [1:1] read-only TX_WAKEUP_DONE Logical AND of corresponding INTR and INTR_MASK fields. [2:2] read-only RX_HEADER_DONE Logical AND of corresponding INTR and INTR_MASK fields. [8:8] read-only RX_RESPONSE_DONE Logical AND of corresponding INTR and INTR_MASK fields. [9:9] read-only RX_BREAK_WAKEUP_DONE Logical AND of corresponding INTR and INTR_MASK fields. [10:10] read-only RX_HEADER_SYNC_DONE Logical AND of corresponding INTR and INTR_MASK fields. [11:11] read-only RX_NOISE_DETECT Logical AND of corresponding INTR and INTR_MASK fields. [13:13] read-only TIMEOUT Logical AND of corresponding INTR and INTR_MASK fields. [14:14] read-only TX_HEADER_BIT_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [16:16] read-only TX_RESPONSE_BIT_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [17:17] read-only RX_HEADER_FRAME_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [24:24] read-only RX_HEADER_SYNC_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [25:25] read-only RX_HEADER_PARITY_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [26:26] read-only RX_RESPONSE_FRAME_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [27:27] read-only RX_RESPONSE_CHECKSUM_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [28:28] read-only CXPI0 CXPI CXPI 0x40510000 0 65536 registers ERROR_CTL Error control 0x0 32 read-write 0x0 0x821C001F CH_IDX Specifies the channel index of the channel to which HW injected channel transmitter errors applies. [4:0] read-write TX_CRC_ERROR The crc field is inverted. At the receiver, this should result in INTR.RX_CRC_ERROR activation. [18:18] read-write TX_PID_PARITY_ERROR In cxpi mode, the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]). At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. [19:19] read-write TX_DATA_LENGTH_ERROR The transmitter continues to send logical '0' (during IFS) after CRC field is transmitted. At the receiver, this should result in INTR.RX_DATA_LENGTH_ERROR activation. At the transmitter, this should result in INTR.TX_DATA_LENGTH_ERROR activation. [20:20] read-write TX_DATA_STOP_ERROR The data field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_FRAME_ERROR activation. At the transmitter, this should result in INTR.TX_FRAME_ERROR activation. [25:25] read-write ENABLED Error injection enable: '0': Disabled. '1': Enabled. [31:31] read-write TEST_CTL Test control 0x4 32 read-write 0x0 0x8001001F CH_IDX Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0, CH_NR-2], as channel index CH_NR-1 is always involved in test and cannot be connected to itself. The test mode allows BOTH of the two connected channels to be tested. Note: this testing functionality simplifies SW development, but may also be used in the field to verify correct channel functionality. [4:0] read-write MODE Test mode: '0': Partial disconnect from IOSS. This mode's isolation allows for device test without relying on an external cxpi transceiver. The IOSS 'tx' IO cell can be used to observe messages outside of the device. - tx_in[CH_IDX] = IOSS cxpi_tx_in[CH_IDX]. - tx_in[CH_NR-1] = IOSS cxpi_tx_in[CH_IDX]. - rx_in[CH_IDX] = IOSS cxpi_tx_in[CH_IDX]. - rx_in[CH_NR-1] = IOSS cxpi_tx_in[CH_IDX]. - cxpi_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. - cxpi_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. '1': Full disconnect from IOSS (the IOSS/HSIOM should disconnect 'tx_out' from the 'tx' IO cell). This mode's isolation allows for device test without effecting an operational cxpi cluster. - tx_in[CH_IDX] = cxpi_tx_out[CH_IDX]. - tx_in[CH_NR-1] = cxpi_tx_out[CH_IDX]. - rx_in[CH_IDX] = cxpi_tx_out[CH_IDX]. - rx_in[CH_NR-1] = cxpi_tx_out[CH_IDX]. - cxpi_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. - cxpi_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. [16:16] read-write PARTIAL_DISCONNECT Partial disconnect 0 FULL_DISCONNECT Full disconnect 1 ENABLED Test enable: '0': Disabled. Functional mode. - tx_in[CH_IDX] = IOSS cxpi_tx_in[CH_IDX]. - tx_in[CH_NR-1] = IOSS cxpi_tx_in[CH_NR-1]. - rx_in[CH_IDX] = IOSS cxpi_rx_in[CH_IDX]. - rx_in[CH_NR-1] = IOSS cxpi_rx_in[CH_NR-1]. - cxpi_tx_out[CH_IDX] = tx_out[CH_IDX]. - cxpi_tx_out[CH_NR-1] = tx_out[CH_NR-1]. '1': Enabled. Test mode, specific test mode is specified by MODE. [31:31] read-write FUNCTIONAL_MODE Functional mode 0 TEST_MODE Test mode 1 2 256 CH[%s] CXPI channel structure 0x00008000 CTL0 Control 0 0x0 32 read-write 0x10 0xC9FF0191 MODE Mode of operation: '0': NRZ mode. '1': PWM mode. [0:0] read-write NRZ NRZ mode 0 PWM PWM mode 1 AUTO_EN CXPI transceiver auto enable: '0': Disabled. '1': Enabled. The TX_RX_STATUS.EN_OUT field is controlled by HW. [4:4] read-write RXPIDZERO_CHECK_EN Receive PID Zero Check Enable. 0 - No action if received PID[6:0] = 0 and PID[7]=1'b1. 1 - If received PID[6:0] = 0 and PID[7]=1'b1, HW (slave) does not clear CMD.RX_HEADER and will anticipate receiving header again (CMD.TX_HEADER=0). If CMD.TX_HEADER=1 in the same scenario, then HW (slave) clears CMD.RX_HEADER upon receiving the header follow by transmit PID. This mode is useful for case where polling method is used and CXPI controller is configured as slave. This would reduce dependency on SW to react to the header received within IBS=1. [7:7] read-write FILTER_EN RX filter enable (for 'cxpi_rx_in') '0': No filter '1': Median 3 (default value) operates on the last three 'cxpi_rx_in' values. The sequences '000', '001', '010', and '100' result in a filtered value '0'. The sequences '111', '110', '101', and '011' result in a filtered value '1'. [8:8] read-write IFS Inter Frame Space in bit periods: '0'' Invalid. ... '10': 10 bit periods ... '31': 31 bit periods Values of <10 are not allowed. This field is used for transmission/reception for adding waiting inter frame space. Note that after a valid transaction (after CRC), HW waits for 10 bits as EOF. Hence, by setting CTL0.IFS=0xA means that HW will wait for 10bits before transmitting a new transaction (not including the EOF). Note: 0 is not allowed when IFS_WAIT=1. SW needs to ensure it has program valid values before it can set IFS_WAIT=1. If IFS_WAIT=1 after timeout occurs, the value of CTL0.IFS would need to consider the timeout count i.e. (IFS needed - CTL2.TIMEOUT_LENGTH-1) to get the total idle time. For example if TIMEOUT_LENGTH=9 and IFS needed is 20, then CTL0.IFS is set to 10. [20:16] read-write IBS Inter Byte Space in bit periods: '0' No offset. '1' 1 IBS is inserted per every byte frame. ... '9' 9 IBS are inserted per every byte frame. Values >9 are invalid per spec. This field is used to control number of IBS after every byte frame when transmitting message frame. Note that this field is the minimum IBS inserted for every byte frame as the SW may require some time to prepare the response when it receives the PID. When receiving, this field is ignored with the exception of receiving header and transmitting response. For receiving header and transmitting response, SW can enable IBS insertion by setting TIMEOUT_SEL=1/2 prior to setting CMD.RX_HEADER=1 and CMD.RX_RESPONSE=1. If the received header corresponds to transmit response, SW clears CMD.RX_RESPONSE =0 and sets TX FIFO and CMD.TX_RESPONSE=1. HW waits for minimum IBS before transmit response (if timeout has not occurred yet). It is prohibit to program IBS>TIMEOUT_LENGTH. This field should not be changed during inflight transaction including EOF. [24:21] read-write BIT_ERROR_IGNORE Specifies behavior on a detected bit error during header or response transmission: '0': Message transfer is aborted. '1': Message transfer is NOT aborted. Note: This field does NOT effect the reporting of the bit error through INTR/STATUS.TX_BIT_ERROR; i.e. bit errors are always reported. Note: This field must not be set to '1' when it is NRZ mode. This is due to delay in transceiver will cause the transmitter behavior undefined when error occurs. [27:27] read-write ABORT_TX_MSG Message transfer is aborted 0 CONT_TX_MSG Message transfer is NOT aborted 1 MASTER CXPI master mode. '0': Indicates CXPI as slave node. '1': Indicates CXPI as master node. This bit is only valid if ENABLED=1. SW needs to set only 1 node as master within the same CXPI cluster. SW needs to set this bit either at the same time as ENABLED or before ENABLED is set. If SW needs to change the controller to different mode, it needs to make sure that HW is quiescent before doing so. [30:30] read-write SLAVE_MODE Slave mode 0 MASTER_MODE Master mode 1 ENABLED Channel enable: '0': Disabled. If a channel is disabled, CMD, STATUS, INTR MMIO registers will have their fields reset to their default value. '1': Enabled. [31:31] read-write DISABLED Disabled 0 ENABLED Enabled 1 CTL1 Control 1 0x4 32 read-write 0x0 0x7FDFF1FF T_LOW1 Low count for logic 1. This is valid only for PWM mode. The count value here indicates the number of clocks per clk_cxpi_ch to drive a '0' at CXPI bus before releasing it to indicate a logical '1'. 0: means 1 clock. 1: means 2 clocks .. 15: means 16 clocks. .. 399: means 400 clocks. Any value above 399 is invalid. Note that for NRZ mode, this field is ignored. Note that this field is used for TX. [8:0] read-write T_LOW0 Low count for logic 0. This is valid only for PWM mode. The count value here indicates the number of clocks per clk_cxpi_ch to drive a '0' at CXPI bus before releasing it to indicate a logical '0'. 0: means 1 clock. 1: means 2 clocks .. 15: means 16 clocks .. 399: means 400 clocks Any value above 399 is invalid. Note that for NRZ mode, this field is ignored. Note that this field is used for TX. [20:12] read-write T_OFFSET The value of offset that is used for sampling the 'rx'. The value of this counter is used in HW as below. - 0 : means 1 clock after detecting falling edge of 'rx' - 1 : means 2 clocks after detecting falling edge of 'rx' .. - 7 : means 8 clocks after detecting falling edge of 'rx' .. - 15 : means 16 clocks after detecting falling edge of 'rx' .. - 399 : means 400 clocks after detecting falling edge of 'rx' Any value above 399 is invalid. [30:22] read-write CTL2 Control 2 0x8 32 read-write 0x0 0xC00F3F03 RETRY Number of retries after arbitration lost. '0': No retries. .. '3': 3 retries. HW will immediately retry after arbitration lost i.e. after the message frame that won the arbitration is complete and fulfilled IFS. If SW wants to manage the retransmission then SW can program RETRY =0. In this case, HW will not retry after arbitration lost and will set TX_HEADER_ARB_LOST bit. SW needs to trigger HW to resend by programming the CMD fields again. [1:0] read-write T_WAKEUP_LENGTH Specifies the wake up pulse low period in Tbits that is transmitted during Standby mode. '0': 1 bit period '1': 2 bit period .. '49': 50 bit period Any value above 49 is invalid. This field is only valid if TX_WAKE_PULSE is set to 1. [13:8] read-write TIMEOUT_LENGTH Timeout Length (in Tbits). Specifies the number of Tbits to exceed timeout between frame bytes within a message frame. CXPI spec states that the maximum allowed inter byte space (IBS) is 9Tbits. This field is valid only when TIMEOUT_SEL=1/2. '0' - 1Tbit '1' - 2Tbits .. '9' - 10Tbits Values >9 is invalid per CXPI spec. Note for NRZ mode, although there are propagation delay from transceiver to CXPI controller, the delay is cancelled out as the timeout is compared on the RX (for transmit case, HW waits for the feedback on RX). [19:16] read-write TIMEOUT_SEL Timeout Select. '0' - Timeout check is disabled. HW clears timeout counter. '1' - Timeout check is enabled and HW will refer to TIMEOUT_LENGTH as number of Tbits allowed between header and response. '2' - Timeout check is enabled to check header-header, header-response, and header-header-response within a message frame to be space within TIMEOUT_LENGTH bit time. '3' - invalid For '1', HW will restart/start timeout counter after transmitting/receiving header. HW will hold the counter if timeout until the next header is transmitted or received. Timeout will cause HW to stop transmission of the current message frame together with interrupt to SW. For receive, HW abort reception of the frame if timeout occurs while waiting for receiving response and notify SW with interrupt. For '2', HW will re-start/start timeout counter after receiving any frame bytes within a message frame. HW will hold the counter if timeout until the IFS. Timeout will cause HW to stop transmission of the current message frame and notify SW with interrupt. For receive, HW will abort reception of the message frame if timeout occurs while waiting for receiving response and notify SW with interrupt. For all cases, HW stops counting when it is out of a message frame such as IFS or CXPI bus IDLE. If the timeout counter > TIMEOUT_LENGTH, then it will set the INTR.TIMEOUT=1. Note that, TIMEOUT_SEL=1/2 also enables the count for IBS between receive header and transmit response on top of timeout check. [31:30] read-write TIMEOUT_DISABLED Timeout check is disabled. 0 TIMEOUT_CHECK_BTW_HDR_RSP Timeout check is enabled and HW will refer to TIMEOUT_LENGHT as number of Tbits allowed between header and response. 1 TIMEOUT_CHECK_BTW_HDR_HDR_RSP Timeout check is enabled to check header-header, header-response, and header-header-response within a message frame to be space within TIMEOUT_LENGTH bit time. 2 STATUS Status 0xC 32 read-only 0x0 0x7FFC3313 RETRIES_COUNT Retries count. The value reflects the number of retries that HW tries to transmit a header/response. HW will reset counter (either case below): 1. after successfully transmit the retry attempt 2. SW clears the CMD.TX_HEADER='0' 3. HW clearing CMD.TX_HEADER=0 due to errors (TX_BIT_ERROR, TX_HEADER_ARB_LOST, TX_OVERFLOW_ERROR, TX_UNDERFLOW_ERROR, TX_DATA_LENGTH_ERROR, and TX_FRAME_ERROR) [1:0] read-only HEADER_RESPONSE Frame header/response identifier (only valid when TX_BUSY or RX_BUSY is '1') '0' - Frame header being transferred. '1' - Frame response being transferred. [4:4] read-only TX_BUSY Transmitter busy. - Set to '1' on the start of the following commands: TX_HEADER, TX_RESPONSE. - Set to '0' on successful completion of previous commands or when an error is detected. [8:8] read-only RX_BUSY Receiver busy. - Set to '1' on the start of the following commands: RX_HEADER, RX_RESPONSE. - Set to '0' on successful completion of previous commands or when an error is detected. [9:9] read-only TX_DONE Transmitter done: - Set to '0' on the start of a new command. - Set to '1' on successful completion of the following command sequences: - TX_HEADER. - TX_HEADER, TX_RESPONSE. - RX_HEADER, TX_RESPONSE. [12:12] read-only RX_DONE Receiver done: - Set to '0' on the start of a new command. - Set to '1' on successful completion of the following commmand sequences: - RX_HEADER, RX_RESPONSE. - TX_HEADER, RX_RESPONSE. [13:13] read-only TIMEOUT Copy of INTR.TIMEOUT [18:18] read-only TX_HEADER_ARB_LOST Copy of INTR.TX_HEADER_ARB_LOST [19:19] read-only TX_BIT_ERROR Copy of INTR.TX_BIT_ERROR. [20:20] read-only RX_CRC_ERROR Copy of INTR.RX_CRC_ERROR. [21:21] read-only RX_HEADER_PARITY_ERROR Copy of INTR.RX_HEADER_PARITY_ERROR. [22:22] read-only RX_DATA_LENGTH_ERROR Copy of INTR.RX_DATA_LENGTH_ERROR. [23:23] read-only TX_DATA_LENGTH_ERROR Copy of INTR.TX_DATA_LENGTH_ERROR. [24:24] read-only RX_OVERFLOW_ERROR Copy of INTR.RX_OVERFLOW_ERROR. [25:25] read-only TX_OVERFLOW_ERROR Copy of INTR.TX_OVERFLOW_ERROR. [26:26] read-only RX_UNDERFLOW_ERROR Copy of INTR.RX_UNDERFLOW_ERROR. [27:27] read-only TX_UNDERFLOW_ERROR Copy of INTR.TX_UNDERFLOW_ERROR. [28:28] read-only RX_FRAME_ERROR Copy of INTR.RX_FRAME_ERROR. [29:29] read-only TX_FRAME_ERROR Copy of INTR.TX_FRAME_ERROR. [30:30] read-only CMD Command 0x10 32 read-write 0x0 0x33F TX_HEADER SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error (such as bit error if bit_ignore=0, arbitration loss, tx data length error. For timeout please refer to SAS) is detected): - TX_HEADER - TX_HEADER, TX_RESPONSE. - TX_HEADER, RX_RESPONSE. The above is for transmission of PID without prior transmission of PTYPE. The header is transmitted when the PID field STOP bits are transmitted (INTR.TX_HEADER_DONE). HW sets this field to '1', when the 'tr_cmd_tx_header' input trigger is activated. This allows for time triggered CXPI message transfer. HW driven time triggered transfer eliminates the jitter that is typically associated with SW driven transfer. SW clears this field to '0', when it wants to cancel a pending request. Note that if SW clears this field to '0' while HW is already in the middle of the request, then the cancel will be ignored. The cancel request can happen when HW is pending a retry when it is still servicing the current transaction. Or the cancel request can occur when HW is checking IFS/bus idle-ness. Note that if PTYPE (TX_HEADER) is transmitted follow by receive response (RX_RESPONSE) or no response, HW clears TX_HEADER right after transmitting PTYPE. [0:0] read-write TX_RESPONSE SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected). - TX_HEADER, TX_RESPONSE. - RX_HEADER, TX_RESPONSE. SW can also clear this field to '0' if SW wants to cancel the TX_RESPONSE. The response is transmitted when the CRC are transmitted (INTR.TX_RESPONSE_DONE). [1:1] read-write SLEEP SW sets this field to '1' to direct HW to sleep mode. HW transits from Normal to Sleep upon SLEEP=1 and both TX and RX is idle. HW sets this field to '0' when it is in Sleep mode. Note that, SW needs to manage the entry to sleep mode by checking the conditions are met before initiating sleep mode e.g. all slave nodes supports sleep and on transmitting sleep frames to indicate sleep to all slave nodes.SW shall not program SLEEP=1 when HW is executing TX_WAKEUP_PULSE command. If SW programs SLEEP=1 during HW executing TX_WAKEUP_PULSE command, it will cause HW to abruptly stop transmitting wakeup pulse as below: 1. HW not clearing TX_WAKEUP_PULSE 2. HW not setting TX_WAKEUP_DONE 3. HW outputting TX_OUT=0. [2:2] read-write WAKE_TO_STANDBY SW sets this field to '1' to direct HW to wake up from Sleep mode to Standby mode. SW clears this field to '0' from '1' when it wants to direct HW from Standby to Normal mode. HW clears this field to '0' when it is in Normal mode or back to Sleep mode from Standby mode. For the case of CXPI master mode, HW will move its power mode from Sleep->Standby when this field is set to '1'. When SW clears this field is from '1' to '0' in Standby mode, HW will move to Normal mode while HW starts transmitting clock. To transmit wake pulse, SW need to program TX_WAKE_PULSE accordingly in Standby mode before entering Normal. For the case of CXPI slave mode and PWM mode, HW will move power mode from Sleep->Standby when this field is set to '1'. HW will wait for detection of clock before moving from Standby->Normal. SW clearing this field to '0' will have no effect. For the case of CXPI slave mode and NRZ mode, HW will move power mode from Sleep->Standby when this field is set to '1'. HW needs to be directed by SW by clearing this field to '0' to move from Standby->Normal after SW has detected clock through another IP (e.g. MXTCPWM). [3:3] read-write TX_WAKE_PULSE SW sets this field to '1' to direct HW to send wake up pulse. HW will transmit wake up pulse in Standby state only. HW will ignore this field when it's not in Standby state. '1' - HW will drive CXPI bus to low for period dictated by T_WAKEUP_LENGTH. '0:'- No wake up pulse HW clears this field to '0' after it transmit the pulse per T_WAKEUP_LENGTH. For the case where more than 1 wake pulses are required, SW is expected to set this field to '1' again (after this field is cleared to '0') per the number of times the wake pulse is required. [4:4] read-write IFS_WAIT SW sets this field to '1' to wait for IFS. HW clears this field to '0' after it detects logical '1' based on IFS. HW will keep this field to '1' if it detects logical '0' before fulfilling the number of logical '1' required. The intention of this bit is to provide capability for SW to direct HW to check bus idle-ness before transmitting. Without setting this bit before directing HW to send header, HW will not check bus idle before transmitting. Besides that, this bit will also provide SW an option to configure HW to wait for IFS before sending again PTYPE or PID to fulfill IFS if there is no response from other nodes. Note: SW needs to configure valid IFS values before setting IFS_WAIT=1. [5:5] read-write RX_HEADER SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences. (Not set to '0' when an error is detected). -RX_HEADER -RX_HEADER, TX_RESPONSE -RX_HEADER, RX_RESPONSE The above applies for cases of receiving PID without prior receiving PTYPE. The header is received when the PID field STOP bits are received (INTR.RX_HEADER_PID_DONE and INTR.RX_HEADER_DONE). Typically, a slave node SW sets both RX_HEADER and RX_RESPONSE to '1', anticipating a transfer of a response from the master node to this slave node. After receipt of the header PID/PTYPE field (INTR.RX_HEADER_PID_DONE is activated), the slave node may decide to set TX_RESPONSE to '1' (which has lower priority than RX_RESPONSE hence RX_RESPONSE need to be clear to '0' by SW) to transmit a response. Note that, for cases with RXPIDZERO_CHECK_EN=1 for slave in polling mode, RX_HEADER is cleared upon receiving PTYPE if the next course of action is to transmit PID. If the next course of action is to receive PID, then the RX_HEADER is cleared upon completion of response. [8:8] read-write RX_RESPONSE SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected). -TX_HEADER, RX_RESPONSE -RX_HEADER, RX_RESPONSE SW can set this field to '1' to be conservative on receiving response i.e. IBS=0 whenever it is receiving PID. If the PID corresponds to transmit response, the SW can then clear this field to '0' and set TX_RESPONSE=1 to direct HW to send response. The response is received after CRC are received (INTR.RX_RESPONSE_DONE). [9:9] read-write TX_RX_STATUS TX/RX status 0x40 32 read-write 0x5000000 0x5000000 TX_IN CXPI transmitter input ('tx_in', 'cxpi_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality. [16:16] read-only RX_IN CXPI receiver input ('rx_in', 'cxpi_rx_in' in functional mode). [17:17] read-only TX_OUT CXPI transmitter output ('tx_out', 'cxpi_tx_out'). [24:24] read-only EN_OUT CXPI transceiver enable ('en_out', 'cxpi_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: '0': Disabled. '1': Enabled. If CTL0.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL0.AUTO_EN is '1', HW controls this field to enable the external transceiver: - HW sets this field to '1' when it is out of Sleep state. If it moves to Sleep state, HW will clear this field to '0'. [26:26] read-write TXPID_FI TXPID and Frame Information 0x50 32 read-write 0x0 0x0 PID Header protected identifier (PID). - Bits 6 downto 0: frame identifier ID[6:0]. - Bits 7: is odd parity bit. - PID[7] = ! (ID[6] ^ ID[5] ^ ID[4] ^ ID[3] ^ ID[2] ^ ID[1] ^ ID[0]) Software does not need to program the parity bit i.e. bit[7]. HW will calculate the odd parity bit and ignore the bit[7] if SW occupies this bit. Transmission: To be transmitted PID field. HW will ignore bit[7] and compute the parity bit based on bits[6:0] Note that, this field can be use by SW to send PType byte as the HW handles both PID and PType the same way. The frame type would occupy bit[6:0] and the odd parity will be calculated by the HW. [7:0] read-write FI Frame Information. This is the byte that will be transmitted as Frame Information. Per CXPI spec, FI[7:4] denotes the data length count (DLC). FI[3:2] denotes Network Management. Bit[3] - wakeup.ind Bit[2] - sleep.ind FI[1:0] denotes CT. Please program to 2'b11 if no support of counter. [15:8] read-write DLCEXT Data Length Count Extension. This field is intended for payload of more than 12B. This field is only valid if DLC=4'b1111 (FI[7:4]). The value specified in this field will be the new payload size. Valid values are 0-255. [23:16] read-write RXPID_FI RXPID and Frame Information 0x54 32 read-only 0x0 0x0 PID Header protected identifier (PID). - Bits 6 downto 0: frame identifier ID[6:0]. - Bits 7: is odd parity bit. - PID[7] = ! (ID[6] ^ ID[5] ^ ID[4] ^ ID[3] ^ ID[2] ^ ID[1] ^ ID[0]) Reception: Received PID field. SW uses the PID field to determine how to handle the response for a received frame header: TX_RESPONSE or RX_RESPONSE. Note that, this field can be use by SW to check PType byte as the HW handles both PID and PType the same way. The frame type would occupy bit[6:0] and bit[7] is the parity bit of the frame type. This parity bit is send by the transmitting node. [7:0] read-only FI Frame Information. This is the byte that is received as Frame Information. Per CXPI spec, FI[7:4] denotes the data length count (DLC). FI[3:2] denotes Network Management. Bit[3] - wakeup.ind Bit[2] - sleep.ind FI[1:0] denotes CT. [15:8] read-only DLCEXT Data Length Count Extension. This field is intended for payload of more than 12B. This field is only valid if DLC=4'b1111 (FI[15:12]). The value specified in this field will be the new payload size. Valid values are 0-255. [23:16] read-only CRC CRC 0x58 32 read-only 0x0 0x0 RXCRC1 CRC first byte for both CRC8 and CRC16. This is valid for both Normal frame and Long frame. HW will load this field with first byte of CRC upon receiving it. [7:0] read-only RXCRC2 CRC second byte of CRC16. This is valid only for Long frames. HW will load this field with second byte of CRC upon receiving it. [15:8] read-only TXCRC1 CRC first byte for both CRC8 and CRC16. This is valid for both Normal frame and Long frame. HW will load this field with first byte of CRC for transmit. [23:16] read-only TXCRC2 CRC second byte of CRC16. This is valid only for Long frames. HW will load this field with second byte of CRC for transmit. [31:24] read-only TX_FIFO_CTL TX FIFO control 0x80 32 read-write 0x0 0x3001F TRIGGER_LEVEL Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated: -INTR.TX_FIFO_TRIGGER = (#FIFO entries < TRIGGER_LEVEL) [4:0] read-write CLEAR This is a synchronous clear signal to the TX FIFO. When '1', the TX FIFO content are cleared. If a quick clear is required, the field should be set to '1' and followed by '0'. If a clear is required for an extended time, the field should be set to 1 during the complete time. [16:16] read-write FREEZE Freeze functionality: '0': HW uses TX FIFO data and pops the data from the TX FIFO for every HW read. '1': HW read from TX FIFO does not pop the data from the TX FIFO. Note: Freeze functionality is for debug purpose only. [17:17] read-write TX_FIFO_STATUS TX FIFO status 0x84 32 read-only 0x0 0x1F USED Number of used/occupied entries in the TX FIFO. The field value is in the range [0, 16]. When '0', the TX FIFO is empty. When '16', the TX FIFO is full. [4:0] read-only AVAIL TX FIFO Avail 0-No available slot in TX FIFO 1-1 available slot in TX FIFO. 2-2 available slot in TX FIFO. .. 16-16 available slot in TX FIFO. Note that the Fifo Width is 1Byte and each slot in this context is 1 depth of the Fifo. The number of bytes are determine through the number of data bytes in a message frame. (TXPID_FI.FI/TXPID_FI.DLCEXT) [20:16] read-only TX_FIFO_WR TX FIFO write 0x88 32 write-only 0x0 0xFF DATA Transmit Data field. Transmission: To be transmitted data field. SW provides data field. HW shadows over the write data to TX FIFO after SW performs a write to this field. HW shadows the whole 8 bits to the TX FIFO and relies on the TXPID_FI.FI/TXPID_FI.DCLEXT to determine the number of bytes. SW needs to ensure that TX FIFO is not overwritten before the content is consumed by HW by checking TX_FIFO_STATUS.AVAIL. Otherwise, the previous content would be overwritten and resulting in TX FIFO's overflow error (INTR.TX_OVERFLOW_ERROR). [7:0] write-only RX_FIFO_CTL RX FIFO control 0xA0 32 read-write 0x0 0x3001F TRIGGER_LEVEL Trigger level. When RX FIFO has more entries than the number of this field, a receiver trigger event is generated. - INTR_RX.FIFO_TRIGGER = (#FIFO entries > TRIGGER_LEVEL) [4:0] read-write CLEAR When '1', the RX FIFO content are popped. If a quick clear is required, the field should be set to '1' and followed by '0'. If a clear is required for an extended time, the field should be set to 1 during the complete time. [16:16] read-write FREEZE Freeze functionality: '0': HW writes to RX FIFO and push the data to RX FIFO. '1': HW write to RX FIFO does not push the data to the RX FIFO. Note: Freeze functionality is for debug purpose only. [17:17] read-write RX_FIFO_STATUS RX FIFO status 0xA4 32 read-only 0x0 0x1F USED Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 16]. When '0', the RX FIFO is empty. When '16', the RX FIFO is full. [4:0] read-only AVAIL RX FIFO avail 0-No content in RX FIFO 1-1 available content in RX FIFO. 2-2 available content in RX FIFO. .. 16-16 available content in RX FIFO. Note that the Fifo Width is 1Byte and each content in this context means 1 fifo slot. The number of bytes in each slot are determine through the number of data bytes in a message frame. (RXPID_FI.FI/RXPID_FI.DLCEXT) [20:16] read-only RX_FIFO_RD RX FIFO read 0xA8 32 read-only 0x0 0x0 DATA Received Data field. Software uses this data field. HW shadows the first content of the RX FIFO to this field. Software reading this field will remove the content from the RX FIFO and the next content of the RX FIFO will be shadowed over to this field. This field is 8bits and reflects the width of the RX FIFO. Software needs to rely on the RXPID_FI.FI/RXPID_FI.DLCEXT fields to determine number of bytes. Note that, during debug, a read from test controller would not remove/destory the content. Software needs to ensure it does not read from this field if there is no available content (from RX_FIFO_STATUS.USED). Otherwise, the content is undefined and it would result in RX FIFO underflow error. (INTR.RX_UNDERFLOW_ERROR). [7:0] read-only RX_FIFO_RD_SILENT RX FIFO silent read 0xAC 32 read-only 0x0 0x0 DATA Data read from the RX FIFO. Reading data from this field would not pop the data from RX FIFO. This register is for debug purpose. [7:0] read-only INTR Interrupt 0xC0 32 read-write 0x0 0x7FFC3F1B TX_HEADER_DONE HW sets this field to '1', when a frame header (PID field or PType field) is transmitted (the CMD.TX_HEADER is completed). Specifically: - For PID transmission only and without prior transmission of PTYPE, when followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the message frame transfer. - For PID transmission only and without prior transmission of PTYPE, when not followed by a response command, this field is set to '1' after completion of the header transfer. -Note for the case of PTYPE is transmitted follow by CMD.RX_RESPONSE or no following response, HW sets this field to '1' after transmitting PTYPE. [0:0] read-write TX_RESPONSE_DONE HW sets this field to '1', when a frame response (frame information fields, data fields, and crc field) is transmitted (the CMD.TX_RESPONSE is completed). [1:1] read-write TX_WAKEUP_DONE HW sets this field to '1', when a wakeup signal is transmitted (per CTL2.T_WAKEUP_LENGTH). This interrupt cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal. [3:3] read-write TX_FIFO_TRIGGER HW sets this field to '1', when TX trigger is generated (#used TX FIFO < TRIGGER_LEVEL). [4:4] read-write RX_HEADER_DONE HW sets this field to '1', when a frame header (PID field or PType field) is received (the CMD.RX_HEADER is completed). Specifically: - When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the message frame transfer. - When not followed by a response command, this field is set to '1' after completion of the header transfer if RXPIDZERO_CHECK_EN=1 and header received is PID. If RXPIDZERO_CHECK_EN=0 and response commands are not set, HW will set this field to '1' after receiving PID or PTYPE. [8:8] read-write RX_RESPONSE_DONE HW sets this field to '1', when a frame response (frame information fields, data fields, and crc field) is received (the CMD.RX_RESPONSE is completed). [9:9] read-write RX_WAKEUP_DETECT HW sets this field to '1', when RX fall is detected in Sleep mode. [10:10] read-write RX_FIFO_TRIGGER HW sets this field to '1', when RX trigger is generated (#used RX FIFO > TRIGGER_LEVEL). [11:11] read-write RX_HEADER_PID_DONE HW sets this field to '1', when RX header (PID/PTYPE field) is received. [12:12] read-write TXRX_COMPLETE HW sets this field to '1', when message frame ends after EOF is completed and TX/RX_DATA_LENGTH_ERROR=0. [13:13] read-write TIMEOUT HW sets this field to '1', when the transmitted/received bytes space within a message frame is > TIMEOUT_LENGTH. SW needs to set TIMEOUT_SEL=0 before clearing TIMEOUT=0 to ensure HW does not immediately sets back the interrupt. [18:18] read-write TX_HEADER_ARB_LOST HW sets this field to '1', when it detects arbitration lost after the number of retries has exceed the maximum allowed retries. Note: The ongoing message transfer is aborted (INTR.TX_HEADER_DONE and INTR.TX_RESPONSE_DONE is NOT activated and the TX_HEADER and TX_RESPONSE command is cleared to 0). [19:19] read-write TX_BIT_ERROR HW sets this field to '1', when a transmitted 'cxpi_tx_out' value does NOT match a received 'cxpi_rx_in' value. The match is performed for the PID fields or PType (for the START bit and STOP bit only) and for the rest of the response i.e. frame information fields, data fields and the crc field (for the START bit, DATA bits, and STOP bits). Note: When CTL0.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE and INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER and TX_RESPONSE commands are set to '0'. When CTL0.BIT_ERROR_IGNORE is '1', the ongoing message transfer would be transferred. [20:20] read-write RX_CRC_ERROR HW sets this field to '1', when received CRC is not matching with the compute CRC from header and response. Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated). [21:21] read-write RX_HEADER_PARITY_ERROR HW sets this field to '1', when the received PID field or PType field has a parity error. Note: The ongoing message transfer is aborted (INTR.RX_HEADER_PID_DONE is NOT activated). [22:22] read-write RX_DATA_LENGTH_ERROR HW sets this field to '1, when the received message frame's data fields are more than the value specified in DLC (for normal frame) or DLCEXT (for long frame) i.e. after receiving CRC byte(s), HW is receiving logical '0' during EOF. For the case of receiving data length less than DLC/DLCEXT, HW will also set this field to '1'. This is the case where IBS>9 before the number of data reaches data length, then HW will report as data length error. HW starts checking after frame information byte. Note: SW needs to handle the message transfer i.e. discard or flush out. HW will still set the RX_RESPONSE_DONE. [23:23] read-write TX_DATA_LENGTH_ERROR HW sets this field to '1, when the transmit message frame's data fields are more than the value specified in DLC (for normal frame) or DLCEXT (for long frame) i.e. after transmitting CRC(s) byte, HW is receiving logical '0' during EOF. Note: HW will still set TX_RESPONSE_DONE and the TX_HEADER and TX_RESPONSE commands are set to '0'. [24:24] read-write RX_OVERFLOW_ERROR HW sets this field to '1', when the RX data is overwritten by HW before the SW reads from it. In CXPI spec, this error is denoted as overrun error. Note: Upon this error, SW should discard the RX data in RX FIFO. [25:25] read-write TX_OVERFLOW_ERROR HW sets this field to '1', when the TX data is overwritten by SW before the HW reads from it to transmit to CXPI bus. Note: The ongoing message transfer will continue when this error happens however, data transferred at CXPI bus will be bogus and HW will invert the CRC to invalidate the message at the receiving node. TX_HEADER and TX_RESPONSE commands are set to '0'. [26:26] read-write RX_UNDERFLOW_ERROR HW sets this field to '1', when RX FIFO is empty and SW reads from it. Note: Upon this error, SW should discard the RX data in RX FIFO. [27:27] read-write TX_UNDERFLOW_ERROR HW sets this field to '1', when TX FIFO is empty and HW reads from it. Note: The ongoing message transfer will continue when this error happens however, data transferred at CXPI will be bogus and HW will invert the CRC to invalidate the message at the receiving node. TX_HEADER and TX_RESPONSE commands are set to '0'. [28:28] read-write RX_FRAME_ERROR HW sets this field to '1', when the stop bit of a byte frame is incorrect. Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated and the INTR.RX_HEADER_DONE/TX_HEADER_DONE is NOT activated if the frame error occurs during header byte or if frame error occurs during response byte (if the HEADER and RESPONSE commands are set together)). [29:29] read-write TX_FRAME_ERROR HW sets this field to '1', when the stop bit of a byte frame is incorrect. This error would be a subset of TX_BIT_ERROR and also subjected to BIT_ERROR_IGNORE field. Note: The ongoing message transfer is aborted (INTR.TX_HEADER_DONE/RX_HEADER_DONE and INTR.TX_RESPONSE_DONE are NOT activated) and the TX_HEADER and TX_RESPONSE commands are set to '0'. Note: When CTL0.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE and INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER and TX_RESPONSE commands are set to '0'. When CTL0.BIT_ERROR_IGNORE is '1', the ongoing message transfer would be transferred. [30:30] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x7FFC3F1B TX_HEADER_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write TX_RESPONSE_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [1:1] read-write TX_WAKEUP_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [3:3] read-write TX_FIFO_TRIGGER Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [4:4] read-write RX_HEADER_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [8:8] read-write RX_RESPONSE_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [9:9] read-write RX_WAKEUP_DETECT Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [10:10] read-write RX_FIFO_TRIGGER Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [11:11] read-write RX_HEADER_PID_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [12:12] read-write TXRX_COMPLETE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [13:13] read-write TIMEOUT Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [18:18] read-write TX_HEADER_ARB_LOST Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [19:19] read-write TX_BIT_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [20:20] read-write RX_CRC_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [21:21] read-write RX_HEADER_PARITY_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [22:22] read-write RX_DATA_LENGTH_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [23:23] read-write TX_DATA_LENGTH_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [24:24] read-write RX_OVERFLOW_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [25:25] read-write TX_OVERFLOW_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [26:26] read-write RX_UNDERFLOW_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [27:27] read-write TX_UNDERFLOW_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [28:28] read-write RX_FRAME_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [29:29] read-write TX_FRAME_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [30:30] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x7FFC3F1B TX_HEADER_DONE Mask for corresponding field in INTR register. [0:0] read-write TX_RESPONSE_DONE Mask for corresponding field in INTR register. [1:1] read-write TX_WAKEUP_DONE Mask for corresponding field in INTR register. [3:3] read-write TX_FIFO_TRIGGER Mask for corresponding field in INTR register. [4:4] read-write RX_HEADER_DONE Mask for corresponding field in INTR register. [8:8] read-write RX_RESPONSE_DONE Mask for corresponding field in INTR register. [9:9] read-write RX_WAKEUP_DETECT Mask for corresponding field in INTR register. [10:10] read-write RX_FIFO_TRIGGER Mask for corresponding field in INTR register. [11:11] read-write RX_HEADER_PID_DONE Mask for corresponding field in INTR register. [12:12] read-write TXRX_COMPLETE Mask for corresponding field in INTR register. [13:13] read-write TIMEOUT Mask for corresponding field in INTR register. [18:18] read-write TX_HEADER_ARB_LOST Mask for corresponding field in INTR register. [19:19] read-write TX_BIT_ERROR Mask for corresponding field in INTR register. [20:20] read-write RX_CRC_ERROR Mask for corresponding field in INTR register. [21:21] read-write RX_HEADER_PARITY_ERROR Mask for corresponding field in INTR register. [22:22] read-write RX_DATA_LENGTH_ERROR Mask for corresponding field in INTR register. [23:23] read-write TX_DATA_LENGTH_ERROR Mask for corresponding field in INTR register. [24:24] read-write RX_OVERFLOW_ERROR Mask for corresponding field in INTR register. [25:25] read-write TX_OVERFLOW_ERROR Mask for corresponding field in INTR register. [26:26] read-write RX_UNDERFLOW_ERROR Mask for corresponding field in INTR register. [27:27] read-write TX_UNDERFLOW_ERROR Mask for corresponding field in INTR register. [28:28] read-write RX_FRAME_ERROR Mask for corresponding field in INTR register. [29:29] read-write TX_FRAME_ERROR Mask for corresponding field in INTR register. [30:30] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x7FFC3F1B TX_HEADER_DONE Logical AND of corresponding INTR and INTR_MASK fields. [0:0] read-only TX_RESPONSE_DONE Logical AND of corresponding INTR and INTR_MASK fields. [1:1] read-only TX_WAKEUP_DONE Logical AND of corresponding INTR and INTR_MASK fields. [3:3] read-only TX_FIFO_TRIGGER Logical AND of corresponding INTR and INTR_MASK fields. [4:4] read-only RX_HEADER_DONE Logical AND of corresponding INTR and INTR_MASK fields. [8:8] read-only RX_RESPONSE_DONE Logical AND of corresponding INTR and INTR_MASK fields. [9:9] read-only RX_WAKEUP_DETECT Logical AND of corresponding INTR and INTR_MASK fields. [10:10] read-only RX_FIFO_TRIGGER Logical AND of corresponding INTR and INTR_MASK fields. [11:11] read-only RX_HEADER_PID_DONE Logical AND of corresponding INTR and INTR_MASK fields. [12:12] read-only TXRX_COMPLETE Logical AND of corresponding INTR and INTR_MASK fields. [13:13] read-only TIMEOUT Logical AND of corresponding INTR and INTR_MASK fields. [18:18] read-only TX_HEADER_ARB_LOST Logical AND of corresponding INTR and INTR_MASK fields. [19:19] read-only TX_BIT_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [20:20] read-only RX_CRC_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [21:21] read-only RX_HEADER_PARITY_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [22:22] read-only RX_DATA_LENGTH_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [23:23] read-only TX_DATA_LENGTH_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [24:24] read-only RX_OVERFLOW_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [25:25] read-only TX_OVERFLOW_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [26:26] read-only RX_UNDERFLOW_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [27:27] read-only TX_UNDERFLOW_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [28:28] read-only RX_FRAME_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [29:29] read-only TX_FRAME_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [30:30] read-only CANFD0 CAN Controller CANFD 0x40520000 0 131072 registers 2 512 CH[%s] FIFO wrapper around M_TTCAN 3PIP, to enable DMA 0x00000000 M_TTCAN TTCAN 3PIP, includes FD 0x00000000 CREL Core Release Register 0x0 32 read-only 0x32380609 0xFFFFFFFF DAY Time Stamp Day Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [7:0] read-only MON Time Stamp Month Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [15:8] read-only YEAR Time Stamp Year One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [19:16] read-only SUBSTEP Sub-step of Core Release One digit, BCD-coded. [23:20] read-only STEP Step of Core Release One digit, BCD-coded. [27:24] read-only REL Core Release One digit, BCD-coded. [31:28] read-only ENDN Endian Register 0x4 32 read-only 0x87654321 0xFFFFFFFF ETV Endianness Test Value The endianness test value is 0x87654321. [31:0] read-only DBTP Data Bit Timing & Prescaler Register 0xC 32 read-write 0xA33 0x9F1FFF DSJW Data (Re)Synchronization Jump Width 0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [3:0] read-write DTSEG2 Data time segment after sample point 0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [7:4] read-write DTSEG1 Data time segment before sample point 0x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [12:8] read-write DBRP Data Bit Rate Prescaler 0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [20:16] read-write TDC Transmitter Delay Compensation 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled [23:23] read-write TEST Test Register 0x10 32 read-write 0x0 0x7F TAM ASC is not supported by M_TTCAN Test ASC Multiplexer Control Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE 0= Level at pin m_ttcan_ascm controlled by FSE 1= Level at pin m_ttcan_ascm = '1' [0:0] read-write TAT ASC is not supported by M_TTCAN Test ASC Transmit Control Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE 0= Level at pin m_ttcan_asct controlled by FSE 1= Level at pin m_ttcan_asct = '1' [1:1] read-write CAM ASC is not supported by M_TTCAN Check ASC Multiplexer Control Monitors level at output pin m_ttcan_ascm. 0= Output pin m_ttcan_ascm = '0' 1= Output pin m_ttcan_ascm = '1' [2:2] read-write CAT ASC is not supported by M_TTCAN Check ASC Transmit Control Monitors level at output pin m_ttcan_asct. 0= Output pin m_ttcan_asct = '0' [3:3] read-write LBCK Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled (see Section 3.1.9, Test Modes) [4:4] read-write TX Control of Transmit Pin 00 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_ttcan_tx 10 Dominant ('0') level at pin m_ttcan_tx 11 Recessive ('1') at pin m_ttcan_tx [6:5] read-write RX Receive Pin Monitors the actual value of pin m_ttcan_rx 0= The CAN bus is dominant (m_ttcan_rx = '0') 1= The CAN bus is recessive (m_ttcan_rx = '1') [7:7] read-only RWD RAM Watchdog 0x14 32 read-write 0x0 0xFFFF WDC Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled. [7:0] read-write WDV Watchdog Value Actual Message RAM Watchdog Counter Value. [15:8] read-only CCCR CC Control Register 0x18 32 read-write 0x1 0xF3FF INIT Initialization 0= Normal Operation 1= Initialization is started [0:0] read-write CCE Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') [1:1] read-write ASM Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active [2:2] read-write CSA Clock Stop Acknowledge 0= No clock stop acknowledged 1= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk [3:3] read-write CSR Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead. 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. [4:4] read-write MON_ Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled [5:5] read-write DAR Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled [6:6] read-write TEST Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled [7:7] read-write FDOE FD Operation Enable 0= FD operation disabled 1= FD operation enabled [8:8] read-write BRSE Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled [9:9] read-write PXHD Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled [12:12] read-write EFBI Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization [13:13] read-write TXP Transmit Pause If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled [14:14] read-write NISO Non ISO Operation If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD [15:15] read-write NBTP Nominal Bit Timing & Prescaler Register 0x1C 32 read-write 0x6000A03 0xFFFFFF7F NTSEG2 Nominal Time segment after sample point 0x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [6:0] read-write NTSEG1 Nominal Time segment before sample point 0x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [15:8] read-write NBRP Nominal Bit Rate Prescaler 0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [24:16] read-write NSJW Nominal (Re)Synchronization Jump Width 0x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [31:25] read-write TSCC Timestamp Counter Configuration 0x20 32 read-write 0x0 0xF0003 TSS Timestamp Select, should always be set to external timestamp counter 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as '00' [1:0] read-write TCP Timestamp Counter Prescaler (still used for TOCC) 0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1...16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [19:16] read-write TSCV Timestamp Counter Value 0x24 32 read-write 0x0 0xFFFF TSC Timestamp Counter, not used for M_TTCAN The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external Timestamp Counter value. A write access has no impact. [15:0] read-write TOCC Timeout Counter Configuration 0x28 32 read-write 0xFFFF0000 0xFFFF0007 ETOC Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled [0:0] read-write TOS Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1 [2:1] read-write TOP Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period. [31:16] read-write TOCV Timeout Counter Value 0x2C 32 read-write 0xFFFF 0xFFFF TOC Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. [15:0] read-write ECR Error Counter Register 0x40 32 read-only 0x0 0xFFFFFF TEC Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255 [7:0] read-only REC Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127 [14:8] read-only RP Receive Error Passive 0= The Receive Error Counter is below the error passive level of 128 1= The Receive Error Counter has reached the error passive level of 128 [15:15] read-only CEL CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. [23:16] read-only PSR Protocol Status Register 0x44 32 read-only 0x707 0x7F7FFF LEC Last Error Code, Set on Read0 The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2= Form Error: A fixed format part of a received frame has the wrong format. 3= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node. 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. [2:0] read-only ACT Activity Monitors the module's CAN communication state. 00= Synchronizing - node is synchronizing on CAN communication 01= Idle - node is neither receiver nor transmitter 10= Receiver - node is operating as receiver 11= Transmitter - node is operating as transmitter [4:3] read-only EP Error Passive 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1= The M_CAN is in the Error_Passive state [5:5] read-only EW Warning Status 0= Both error counters are below the Error_Warning limit of 96 1= At least one of error counter has reached the Error_Warning limit of 96 [6:6] read-only BO Bus_Off Status 0= The M_CAN is not Bus_Off 1= The M_CAN is in Bus_Off state [7:7] read-only DLEC Data Phase Last Error Code , Set on Read Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. [10:8] read-only RESI ESI flag of last received CAN FD Message , Reset on Read This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its ESI flag set 1= Last received CAN FD message had its ESI flag set [11:11] read-only RBRS BRS flag of last received CAN FD Message , Reset on Read This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its BRS flag set 1= Last received CAN FD message had its BRS flag set [12:12] read-only RFDF Received a CAN FD Message , Reset on Read This bit is set independent of acceptance filtering. 0= Since this bit was reset by the CPU, no CAN FD message has been received 1= Message in CAN FD format with FDF flag set has been received [13:13] read-only PXE Protocol Exception Event , Reset on Read 0= No protocol exception event occurred since last read access 1= Protocol exception event occurred [14:14] read-only TDCV Transmitter Delay Compensation Value 0x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. [22:16] read-only TDCR Transmitter Delay Compensation Register 0x48 32 read-write 0x0 0x7F7F TDCF Transmitter Delay Compensation Filter Window Length 0x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq [6:0] read-write TDCO Transmitter Delay Compensation Offset 0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq. [14:8] read-write IR Interrupt Register 0x50 32 read-write 0x0 0x3FFFFFFF RF0N Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0 [0:0] read-write RF0W Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark [1:1] read-write RF0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full [2:2] read-write RF0L_ Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero [3:3] read-write RF1N Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1 [4:4] read-write RF1W Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark [5:5] read-write RF1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full [6:6] read-write RF1L_ Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero [7:7] read-write HPM High Priority Message 0= No high priority message received 1= High priority message received [8:8] read-write TC Transmission Completed 0= No transmission completed 1= Transmission completed [9:9] read-write TCF Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished [10:10] read-write TFE Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty [11:11] read-write TEFN Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element [12:12] read-write TEFW Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark [13:13] read-write TEFF Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full [14:14] read-write TEFL_ Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero [15:15] read-write TSW Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around [16:16] read-write MRAF Message RAM Access Failure The flag is set, when the Rx Handler - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. - was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred [17:17] read-write TOO Timeout Occurred 0= No timeout 1= Timeout reached [18:18] read-write DRX Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into a Rx Buffer [19:19] read-write BEC M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0. Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC) [20:20] read-write BEU Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic) [21:21] read-write ELO Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred [22:22] read-write EP_ Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed [23:23] read-write EW_ Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed [24:24] read-write BO_ Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed [25:25] read-write WDI Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY [26:26] read-write PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC != 0,7) [27:27] read-write PED Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC != 0,7) [28:28] read-write ARA N/A [29:29] read-write IE Interrupt Enable 0x54 32 read-write 0x0 0x3FFFFFFF RF0NE Rx FIFO 0 New Message Interrupt Enable [0:0] read-write RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable [1:1] read-write RF0FE Rx FIFO 0 Full Interrupt Enable [2:2] read-write RF0LE Rx FIFO 0 Message Lost Interrupt Enable [3:3] read-write RF1NE Rx FIFO 1 New Message Interrupt Enable [4:4] read-write RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable [5:5] read-write RF1FE Rx FIFO 1 Full Interrupt Enable [6:6] read-write RF1LE Rx FIFO 1 Message Lost Interrupt Enable [7:7] read-write HPME High Priority Message Interrupt Enable [8:8] read-write TCE Transmission Completed Interrupt Enable [9:9] read-write TCFE Transmission Cancellation Finished Interrupt Enable [10:10] read-write TFEE Tx FIFO Empty Interrupt Enable [11:11] read-write TEFNE Tx Event FIDO New Entry Interrupt Enable [12:12] read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable [13:13] read-write TEFFE Tx Event FIFO Full Interrupt Enable [14:14] read-write TEFLE Tx Event FIFO Event Lost Interrupt Enable [15:15] read-write TSWE Timestamp Wraparound Interrupt Enable [16:16] read-write MRAFE Message RAM Access Failure Interrupt Enable [17:17] read-write TOOE Timeout Occurred Interrupt Enable [18:18] read-write DRXE Message stored to Dedicated Rx Buffer Interrupt Enable [19:19] read-write BECE Bit Error Corrected Interrupt Enable (not used in M_TTCAN) [20:20] read-write BEUE Bit Error Uncorrected Interrupt Enable [21:21] read-write ELOE Error Logging Overflow Interrupt Enable [22:22] read-write EPE Error Passive Interrupt Enable [23:23] read-write EWE Warning Status Interrupt Enable [24:24] read-write BOE Bus_Off Status Interrupt Enable [25:25] read-write WDIE Watchdog Interrupt Enable [26:26] read-write PEAE Protocol Error in Arbitration Phase Enable [27:27] read-write PEDE Protocol Error in Data Phase Enable [28:28] read-write ARAE N/A [29:29] read-write ILS Interrupt Line Select 0x58 32 read-write 0x0 0x3FFFFFFF RF0NL Rx FIFO 0 New Message Interrupt Line [0:0] read-write RF0WL Rx FIFO 0 Watermark Reached Interrupt Line [1:1] read-write RF0FL Rx FIFO 0 Full Interrupt Line [2:2] read-write RF0LL Rx FIFO 0 Message Lost Interrupt Line [3:3] read-write RF1NL Rx FIFO 1 New Message Interrupt Line [4:4] read-write RF1WL Rx FIFO 1 Watermark Reached Interrupt Line [5:5] read-write RF1FL Rx FIFO 1 Full Interrupt Line [6:6] read-write RF1LL Rx FIFO 1 Message Lost Interrupt Line [7:7] read-write HPML High Priority Message Interrupt Line [8:8] read-write TCL Transmission Completed Interrupt Line [9:9] read-write TCFL Transmission Cancellation Finished Interrupt Line [10:10] read-write TFEL Tx FIFO Empty Interrupt Line [11:11] read-write TEFNL Tx Event FIFO New Entry Interrupt Line [12:12] read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line [13:13] read-write TEFFL Tx Event FIFO Full Interrupt Line [14:14] read-write TEFLL Tx Event FIFO Event Lost Interrupt Line [15:15] read-write TSWL Timestamp Wraparound Interrupt Line [16:16] read-write MRAFL Message RAM Access Failure Interrupt Line [17:17] read-write TOOL Timeout Occurred Interrupt Line [18:18] read-write DRXL Message stored to Dedicated Rx Buffer Interrupt Line [19:19] read-write BECL Bit Error Corrected Interrupt Line (not used in M_TTCAN) [20:20] read-write BEUL Bit Error Uncorrected Interrupt Line [21:21] read-write ELOL Error Logging Overflow Interrupt Line [22:22] read-write EPL Error Passive Interrupt Line [23:23] read-write EWL Warning Status Interrupt Line [24:24] read-write BOL Bus_Off Status Interrupt Line [25:25] read-write WDIL Watchdog Interrupt Line [26:26] read-write PEAL Protocol Error in Arbitration Phase Line [27:27] read-write PEDL Protocol Error in Data Phase Line [28:28] read-write ARAL N/A [29:29] read-write ILE Interrupt Line Enable 0x5C 32 read-write 0x0 0x3 EINT0 Enable Interrupt Line 0 0= Interrupt line m_ttcan_int0 disabled 1= Interrupt line m_ttcan_int0 enabled [0:0] read-write EINT1 Enable Interrupt Line 1 0= Interrupt line m_ttcan_int1 disabled 1= Interrupt line m_ttcan_int1 enabled [1:1] read-write GFC Global Filter Configuration 0x80 32 read-write 0x0 0x3F RRFE Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs [0:0] read-write RRFS Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs [1:1] read-write ANFE Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject [3:2] read-write ANFS Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject [5:4] read-write SIDFC Standard ID Filter Configuration 0x84 32 read-write 0x0 0xFFFFFC FLSSA Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see Figure 2). [15:2] read-write LSS List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements 128= Values greater than 128 are interpreted as 128 [23:16] read-write XIDFC Extended ID Filter Configuration 0x88 32 read-write 0x0 0x7FFFFC FLESA Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address, see Figure 2). [15:2] read-write LSE List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements 64= Values greater than 64 are interpreted as 64 [22:16] read-write XIDAM Extended ID AND Mask 0x90 32 read-write 0x1FFFFFFF 0x1FFFFFFF EIDM Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. [28:0] read-write HPMS High Priority Message Status 0x94 32 read-only 0x0 0xFFFF BIDX Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'. [5:0] read-only MSI Message Storage Indicator 00= No FIFO selected 01= FIFO message lost 10= Message stored in FIFO 0 11= Message stored in FIFO 1 [7:6] read-only FIDX Filter Index Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. [14:8] read-only FLST Filter List Indicates the filter list of the matching filter element. 0= Standard Filter List 1= Extended Filter List [15:15] read-only NDAT1 New Data 1 0x98 32 read-write 0x0 0xFFFFFFFF ND New Data The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message [31:0] read-write NDAT2 New Data 2 0x9C 32 read-write 0x0 0xFFFFFFFF ND New Data The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message [31:0] read-write RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write 0x0 0xFF7FFFFC F0SA Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2). [15:2] read-write F0S Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements 64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1 [22:16] read-write F0WM Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) 64= Watermark interrupt disabled [30:24] read-write F0OM FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode [31:31] read-write RXF0S Rx FIFO 0 Status 0xA4 32 read-only 0x0 0x33F3F7F F0FL Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64. When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected. [6:0] read-only F0GI Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63. This field is updated by the software writing to RXF0A.F0AI. When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected. [13:8] read-only F0PI Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63. [21:16] read-only F0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full [24:24] read-only RF0L Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero [25:25] read-only RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write 0x0 0x3F F0AI Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. [5:0] read-write RXBC Rx Buffer Configuration 0xAC 32 read-write 0x0 0xFFFC RBSA Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). Also used to reference debug messages A,B,C. [15:2] read-write RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write 0x0 0xFF7FFFFC F1SA Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2). [15:2] read-write F1S Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements 64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1 [22:16] read-write F1WM Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) 64= Watermark interrupt disabled [30:24] read-write F1OM FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode [31:31] read-write RXF1S Rx FIFO 1 Status 0xB4 32 read-only 0x0 0xC33F3F7F F1FL Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64. When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected. [6:0] read-only F1GI Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63. This field is updated by the software writing to RXF1A.F1AI. When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected. [13:8] read-only F1PI Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63. [21:16] read-only F1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full [24:24] read-only RF1L Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero [25:25] read-only DMS Debug Message Status 00= Idle state, wait for reception of debug messages, DMA request is cleared 01= Debug message A received 10= Debug messages A, B received 11= Debug messages A, B, C received, DMA request is set [31:30] read-only RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write 0x0 0x3F F1AI Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. [5:0] read-write RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write 0x0 0x777 F0DS Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [2:0] read-write F1DS Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [6:4] read-write RBDS Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [10:8] read-write TXBC Tx Buffer Configuration 0xC0 32 read-write 0x0 0x7F3FFFFC TBSA Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). [15:2] read-write NDTB Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers 32= Values greater than 32 are interpreted as 32 [21:16] read-write TFQS Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue 32= Values greater than 32 are interpreted as 32 [29:24] read-write TFQM Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation [30:30] read-write TXFQS Tx FIFO/Queue Status 0xC4 32 read-only 0x0 0x3F1F3F TFFL Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1') [5:0] read-only TFGI Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured TXBC.TFQM = '1'). [12:8] read-only TFQPI Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31. [20:16] read-only TFQF Tx FIFO/Queue Full 0= Tx FIFO/Queue not full 1= Tx FIFO/Queue full [21:21] read-only TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write 0x0 0x7 TBDS Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [2:0] read-write TXBRP Tx Buffer Request Pending 0xCC 32 read-only 0x0 0xFFFFFFFF TRP Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0= No transmission request pending 1= Transmission request pending [31:0] read-only TXBAR Tx Buffer Add Request 0xD0 32 read-write 0x0 0xFFFFFFFF AR Add Request Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added [31:0] read-write TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write 0x0 0xFFFFFFFF CR Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending [31:0] read-write TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only 0x0 0xFFFFFFFF TO Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0= No transmission occurred 1= Transmission occurred [31:0] read-only TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only 0x0 0xFFFFFFFF CF Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0= No transmit buffer cancellation 1= Transmit buffer cancellation finished [31:0] read-only TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write 0x0 0xFFFFFFFF TIE Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable [31:0] read-write TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write 0x0 0xFFFFFFFF CFIE Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled [31:0] read-write TXEFC Tx Event FIFO Configuration 0xF0 32 read-write 0x0 0x3F3FFFFC EFSA Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2). [15:2] read-write EFS Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements 32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1 [21:16] read-write EFWM Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) 32= Watermark interrupt disabled [29:24] read-write TXEFS Tx Event FIFO Status 0xF4 32 read-only 0x0 0x31F1F3F EFFL Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32. When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected. [5:0] read-only EFGI Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31. This field is updated by the software writing to TXEFA.EFAI. When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected. [12:8] read-only EFPI Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31. [20:16] read-only EFF Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full [24:24] read-only TEFL Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. [25:25] read-only TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write 0x0 0x1F EFAI Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. [4:0] read-write TTTMC TT Trigger Memory Configuration 0x100 32 read-write 0x0 0x7FFFFC TMSA Trigger Memory Start Address Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2). [15:2] read-write TME Trigger Memory Elements 0= No Trigger Memory 1-64= Number of Trigger Memory elements 64= Values greater than 64 are interpreted as 64 [22:16] read-write TTRMC TT Reference Message Configuration 0x104 32 read-write 0x0 0xDFFFFFFF RID Reference Identifier Identifier transmitted with reference message and used for reference message filtering. Standard or extended reference identifier depending on bit XTD. A standard identifier has to be written to ID[28:18]. [28:0] read-write XTD Extended Identifier 0= 11-bit standard identifier 1= 29-bit extended identifier [30:30] read-write RMPS Reference Message Payload Select Ignored in case of time slaves. 0= Reference message has no additional payload 1= The following elements are taken from Tx Buffer 0: Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB Level 1: bytes 2-8, Level 0,2: bytes 5-8) [31:31] read-write TTOCF TT Operation Configuration 0x108 32 read-write 0x10000 0x7FFFFFB OM Operation Mode 00= Event-driven CAN communication, default 01= TTCAN level 1 10= TTCAN level 2 11= TTCAN level 0 [1:0] read-write GEN Gap Enable 0= Strictly time-triggered operation 1= External event-synchronized time-triggered operation [3:3] read-write TM Time Master 0= Time Master function disabled 1= Potential Time Master [4:4] read-write LDSDL LD of Synchronization Deviation Limit The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = 2(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration. 0x0-7 LD of Synchronization Deviation Limit (SDL <= 32...4096) [7:5] read-write IRTO Initial Reference Trigger Offset 0x00-7F Positive offset, range from 0 to 127 [14:8] read-write EECS Enable External Clock Synchronization If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation. 0= External clock synchronization in TTCAN Level 0,2 disabled 1= External clock synchronization in TTCAN Level 0,2 enabled [15:15] read-write AWL Application Watchdog Limit The application watchdog can be disabled by programming AWL to 0x00. 0x00-FF Maximum time after which the application has to serve the application watchdog. The application watchdog is incremented once each 256 NTUs. [23:16] read-write EGTF Enable Global Time Filtering 0= Global time filtering in TTCAN Level 0,2 is disabled 1= Global time filtering in TTCAN Level 0,2 is enabled [24:24] read-write ECC Enable Clock Calibration 0= Automatic clock calibration in TTCAN Level 0,2 is disabled 1= Automatic clock calibration in TTCAN Level 0,2 is enabled [25:25] read-write EVTP Event Trigger Polarity 0= Rising edge trigger 1= Falling edge trigger [26:26] read-write TTMLM TT Matrix Limits 0x10C 32 read-write 0x0 0xFFF0FFF CCM N/A [5:0] read-write CSS N/A [7:6] read-write TXEW Tx Enable Window 0x0-F Length of Tx enable window, 1-16 NTU cycles [11:8] read-write ENTT Expected Number of Tx Triggers 0x000-FFF Expected number of Tx Triggers in one Matrix Cycle [27:16] read-write TURCF TUR Configuration 0x110 32 read-write 0x10000000 0xBFFFFFFF NCL Numerator Configuration Low Write access to the TUR Numerator Configuration Low is only possible during configuration with TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new value for NCL is written outside TT Configuration Mode, the new value takes effect when TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'. 0x0000-FFFF Numerator Configuration Low [15:0] read-write DC Denominator Configuration 0x0000 Illegal value 0x0001-3FFF Denominator Configuration [29:16] read-write ELT Enable Local Time 0= Local time is stopped, default 1= Local time is enabled [31:31] read-write TTOCN TT Operation Control 0x114 32 read-write 0x0 0xBFFF SGT Set Global time Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one Host clock period. The global time preset takes effect when the node transmits the next reference message with the Master_Ref_Mark modified by the preset value written to TTGTP. [0:0] read-write ECS External Clock Synchronization Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one Host clock period. The external clock synchronization takes effect at the start of the next basic cycle. [1:1] read-write SWP Stop Watch Polarity 0= Rising edge trigger 1= Falling edge trigger [2:2] read-write SWS Stop Watch Source 00= Stop Watch disabled 01= Actual value of cycle time is copied to TTCPT.SWV 10= Actual value of local time is copied to TTCPT.SWV 11= Actual value of global time is copied to TTCPT.SWV [4:3] read-write RTIE Register Time Mark Interrupt Pulse Enable Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent of the synchronization state. 0= Register Time Mark Interrupt output m_ttcan_rtp disabled 1= Register Time Mark Interrupt output m_ttcan_rtp enabled [5:5] read-write TMC Register Time Mark Compare 00= No Register Time Mark Interrupt generated 01= Register Time Mark Interrupt if Time Mark = cycle time 10= Register Time Mark Interrupt if Time Mark = local time 11= Register Time Mark Interrupt if Time Mark = global time [7:6] read-write TTIE Trigger Time Mark Interrupt Pulse Enable External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A trigger time mark interrupt pulse is generated when the trigger memory element becomes active, and the M_TTCAN is in synchronization state In_Schedule or In_Gap. 0= Trigger Time Mark Interrupt output m_ttcan_tmp disabled 1= Trigger Time Mark Interrupt output m_ttcan_tmp enabled [8:8] read-write GCS Gap Control Select 0= Gap control independent from m_ttcan_evt 1= Gap control by input pin m_ttcan_evt [9:9] read-write FGP Finish Gap Set by the CPU, reset by each reference message 0= No reference message requested 1= Application requested start of reference message [10:10] read-write TMG Time Mark Gap 0= Reset by each reference message 1= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated [11:11] read-write NIG Next is Gap This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for external event-synchronized time-triggered operation (TTOCF.GEN = '1') 0= No action, reset by reception of any reference message 1= Transmit next reference message with Next_is_Gap = '1' [12:12] read-write ESCN External Synchronization Control If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising edge at pin m_ttcan_evt (see Section 4.11). 0= External synchronization disabled 1= External synchronization enabled [13:13] read-write LCKC TT Operation Control Register Locked Set by a write access to register TTOCN. Reset when the updated configuration has been synchronized into the CAN clock domain. 0= Write access to TTOCN enabled 1= Write access to TTOCN locked [15:15] read-only TTGTP TT Global Time Preset 0x118 32 read-write 0x0 0xFFFFFFFF TP N/A [15:0] read-write CTP Cycle Time Target Phase CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11). 0x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected [31:16] read-write TTTMK TT Time Mark 0x11C 32 read-write 0x0 0x807FFFFF TM_ Time Mark 0x0000-FFFF Time Mark [15:0] read-write TICC Time Mark Cycle Code Cycle count for which the time mark is valid. 0b000000x valid for all cycles 0b000001c valid every second cycle at cycle count mod2 = c 0b00001cc valid every fourth cycle at cycle count mod4 = cc 0b0001ccc valid every eighth cycle at cycle count mod8 = ccc 0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc 0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc 0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc [22:16] read-write LCKM TT Time Mark Register Locked Always set by a write access to registers TTOCN. Set by write access to register TTTMK when TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain. 0= Write access to TTTMK enabled 1= Write access to TTTMK locked [31:31] read-only TTIR TT Interrupt Register 0x120 32 read-write 0x0 0x7FFFF SBC Start of Basic Cycle 0= No Basic Cycle started since bit has been reset 1= Basic Cycle started [0:0] read-write SMC Start of Matrix Cycle 0= No Matrix Cycle started since bit has been reset 1= Matrix Cycle started [1:1] read-write CSM_ Change of Synchronization Mode 0= No change in master to slave relation or schedule synchronization 1= Master to slave relation or schedule synchronization changed, also set when TTOST.SPL is reset [2:2] read-write SOG Start of Gap 0= No reference message seen with Next_is_Gap bit set 1= Reference message with Next_is_Gap bit set becomes valid [3:3] read-write RTMI Register Time Mark Interrupt Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent of the synchronization state. 0= Time mark not reached 1= Time mark reached [4:4] read-write TTMI Trigger Time Mark Event Internal Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set when the trigger memory element becomes active, and the M_TTCAN is in synchronization state In_Gap or In_Schedule. 0= Time mark not reached 1= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200) [5:5] read-write SWE Stop Watch Event 0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected 1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected [6:6] read-write GTW Global Time Wrap 0= No global time wrap occurred 1= Global time wrap from 0xFFFF to 0x0000 occurred [7:7] read-write GTD Global Time Discontinuity 0= No discontinuity of global time 1= Discontinuity of global time [8:8] read-write GTE Global Time Error Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only. 0= Synchronization deviation within limit 1= Synchronization deviation exceeded limit [9:9] read-write TXU Tx Count Underflow 0= Number of Tx Trigger as expected 1= Less Tx trigger than expected in one matrix cycle [10:10] read-write TXO Tx Count Overflow 0= Number of Tx Trigger as expected 1= More Tx trigger than expected in one matrix cycle [11:11] read-write SE1 Scheduling Error 1 0= No scheduling error 1 1= Scheduling error 1 occurred [12:12] read-write SE2 Scheduling Error 2 0= No scheduling error 2 1= Scheduling error 2 occurred [13:13] read-write ELC Error Level Changed Not set when error level changed during initialization. 0= No change in error level 1= Error level changed [14:14] read-write IWT Initialization Watch Trigger The initialization is restarted by resetting IWT. 0= No missing reference message during system startup 1= No system startup due to missing reference message [15:15] read-write WT Watch Trigger 0= No missing reference message 1= Missing reference message (Level 0: cycle time 0xFF00) [16:16] read-write AW Application Watchdog 0= Application watchdog served in time 1= Application watchdog not served in time [17:17] read-write CER Configuration Error Trigger out of order. 0= No error found in trigger list 1= Error found in trigger list [18:18] read-write TTIE TT Interrupt Enable 0x124 32 read-write 0x0 0x7FFFF SBCE Start of Basic Cycle Interrupt Enable [0:0] read-write SMCE Start of Matrix Cycle Interrupt Enable [1:1] read-write CSME Change of Synchronization Mode Interrupt Enable [2:2] read-write SOGE Start of Gap Interrupt Enable [3:3] read-write RTMIE Register Time Mark Interrupt Enable [4:4] read-write TTMIE Trigger Time Mark Event Internal Enable [5:5] read-write SWEE Stop Watch Event Interrupt Enable [6:6] read-write GTWE Global Time Wrap Interrupt Enable [7:7] read-write GTDE Global Time Discontinuity Interrupt Enable [8:8] read-write GTEE Global Time Error Interrupt Enable [9:9] read-write TXUE Tx Count Underflow Interrupt Enable [10:10] read-write TXOE Tx Count Overflow Interrupt Enable [11:11] read-write SE1E Scheduling Error 1 Interrupt Enable [12:12] read-write SE2E Scheduling Error 2 Interrupt Enable [13:13] read-write ELCE Change Error Level Interrupt Enable [14:14] read-write IWTE Initialization Watch Trigger Interrupt Enable [15:15] read-write WTE Watch Trigger Interrupt Enable [16:16] read-write AWE_ Application Watchdog Interrupt Enable [17:17] read-write CERE Configuration Error Interrupt Enable [18:18] read-write TTILS TT Interrupt Line Select 0x128 32 read-write 0x0 0x7FFFF SBCL Start of Basic Cycle Interrupt Line [0:0] read-write SMCL Start of Matrix Cycle Interrupt Line [1:1] read-write CSML Change of Synchronization Mode Interrupt Line [2:2] read-write SOGL Start of Gap Interrupt Line [3:3] read-write RTMIL Register Time Mark Interrupt Line [4:4] read-write TTMIL Trigger Time Mark Event Internal Line [5:5] read-write SWEL Stop Watch Event Interrupt Line [6:6] read-write GTWL Global Time Wrap Interrupt Line [7:7] read-write GTDL Global Time Discontinuity Interrupt Line [8:8] read-write GTEL Global Time Error Interrupt Line [9:9] read-write TXUL Tx Count Underflow Interrupt Line [10:10] read-write TXOL Tx Count Overflow Interrupt Line [11:11] read-write SE1L Scheduling Error 1 Interrupt Line [12:12] read-write SE2L Scheduling Error 2 Interrupt Line [13:13] read-write ELCL Change Error Level Interrupt Line [14:14] read-write IWTL Initialization Watch Trigger Interrupt Line [15:15] read-write WTL Watch Trigger Interrupt Line [16:16] read-write AWL_ Application Watchdog Interrupt Line [17:17] read-write CERL Configuration Error Interrupt Line [18:18] read-write TTOST TT Operation Status 0x12C 32 read-only 0x80 0xFFC0FFFF EL Error Level 00= Severity 0 - No Error 01= Severity 1 - Warning 10= Severity 2 - Error 11= Severity 3 - Severe Error [1:0] read-only MS Master State 00= Master_Off, no master properties relevant 01= Operating as Time Slave 10= Operating as Backup Time Master 11= Operating as current Time Master [3:2] read-only SYS Synchronization State 00= Out of Synchronization 01= Synchronizing to TTCAN communication 10= Schedule suspended by Gap (In_Gap) 11= Synchronized to schedule (In_Schedule) [5:4] read-only QGTP Quality of Global Time Phase Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'. 0= Global time not valid 1= Global time in phase with Time Master [6:6] read-only QCS Quality of Clock Speed Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'. 0= Local clock speed not synchronized to Time Master clock speed 1= Synchronization Deviation <= SDL [7:7] read-only RTO Reference Trigger Offset The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read. 0x00-FF Actual Reference Trigger offset value [15:8] read-only WGTD Wait for Global Time Discontinuity 0= No global time preset pending 1= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = '1' or after it received a reference message. [22:22] read-only GFI Gap Finished Indicator Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another node sending a reference message. 0= Reset at the end of each reference message 1= Gap finished by M_TTCAN [23:23] read-only TMP Time Master Priority 0x0-7 Priority of actual Time Master [26:24] read-only GSI Gap Started Indicator 0= No Gap in schedule, reset by each reference message and for all time slaves 1= Gap time after Basic Cycle has started [27:27] read-only WFE Wait for Event 0= No Gap announced, reset by a reference message with Next_is_Gap = '0' 1= Reference message with Next_is_Gap = '1' received [28:28] read-only AWE Application Watchdog Event The application watchdog is served by reading TTOST. When the watchdog is not served in time, bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring Mode. 0= Application Watchdog served in time 1= Failed to serve Application Watchdog in time [29:29] read-only WECS Wait for External Clock Synchronization 0= No external clock synchronization pending 1= Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle. [30:30] read-only SPL Schedule Phase Lock The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11). 0= Phase outside range 1= Phase inside range [31:31] read-only TURNA TUR Numerator Actual 0x130 32 read-only 0x10000 0x3FFFF NAV N/A [17:0] read-only TTLGT TT Local & Global Time 0x134 32 read-only 0x0 0xFFFFFFFF LT Local Time Non-fractional part of local time, incremented once each local NTU (see Section 4.5). 0x0000-FFFF Local time value of TTCAN node [15:0] read-only GT Global Time Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5). 0x0000-FFFF Global time value of TTCAN network [31:16] read-only TTCTC TT Cycle Time & Count 0x138 32 read-only 0x3F0000 0x3FFFFF CT Cycle Time Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5). 0x0000-FFFF Cycle time value of TTCAN Basic Cycle [15:0] read-only CC Cycle Count 0x00-3F Number of actual Basic Cycle in the System Matrix [21:16] read-only TTCPT TT Capture Time 0x13C 32 read-only 0x0 0xFFFF003F CCV Cycle Count Value Cycle count value captured together with SWV. 0x00-3F Captured cycle count value [5:0] read-only SWV Stop Watch Value On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE. 0x0000-FFFF Captured Stop Watch value [31:16] read-only TTCSM TT Cycle Sync Mark 0x140 32 read-only 0x0 0xFFFF CSM Cycle Sync Mark The Cycle Sync Mark is measured [15:0] read-only RXFTOP_CTL Receive FIFO Top control 0x180 32 read-write 0x0 0x3 F0TPE FIFO 0 Top Pointer Enable. This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter. This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1). When this logic is disabled a Read from RXFTOP0_DATA is undefined. [0:0] read-write F1TPE FIFO 1 Top Pointer Enable. [1:1] read-write RXFTOP0_STAT Receive FIFO 0 Top Status 0x1A0 32 read-only 0x0 0xFFFF F0TA Current FIFO 0 Top Address. This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC) FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC [15:0] read-only RXFTOP0_DATA Receive FIFO 0 Top Data 0x1A8 32 read-only 0x0 0x0 F0TD When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met: - M_TTCAN not being reconfigured (CCCR.CCE=0) - FIFO Top Pointer logic is enabled (FnTPE=1) - FIFO is not empty (FnFL!=0) The read side effect is as follows: - if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI - FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message) - the FIFO top address FnTA is incremented (with FIFO wrap around) When this logic is disabled (F0TPE=0) a Read from this register returns undefined data. [31:0] read-only RXFTOP1_STAT Receive FIFO 1 Top Status 0x1B0 32 read-only 0x0 0xFFFF F1TA See F0TA description [15:0] read-only RXFTOP1_DATA Receive FIFO 1 Top Data 0x1B8 32 read-only 0x0 0x0 F1TD See F0TD description [31:0] read-only CTL Global CAN control register 0x1000 32 read-write 0x0 0x800000FF STOP_REQ Clock Stop Request for each TTCAN IP . The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits. [7:0] read-write MRAM_OFF MRAM off 0= Default MRAM on (with MRAM retained in DeepSleep). 1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode. [31:31] read-write STATUS Global CAN status register 0x1004 32 read-only 0x0 0xFF STOP_ACK Clock Stop Acknowledge for each TTCAN IP. These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP. When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write [7:0] read-only INTR0_CAUSE Consolidated interrupt0 cause register 0x1010 32 read-only 0x0 0xFF INT0 Show pending m_ttcan_int0 of each channel [7:0] read-only INTR1_CAUSE Consolidated interrupt1 cause register 0x1014 32 read-only 0x0 0xFF INT1 Show pending m_ttcan_int1 of each channel [7:0] read-only TS_CTL Time Stamp control register 0x1020 32 read-write 0x0 0x8000FFFF PRESCALE Time Stamp counter prescale value. When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks. [15:0] read-write ENABLED Counter enable bit 0 = Count disabled. Stop counting up and keep the counter value 1 = Count enabled. Start counting up from the current value [31:31] read-write TS_CNT Time Stamp counter value 0x1024 32 read-write 0x0 0xFFFF VALUE The counter value of the Time Stamp Counter. When enabled this counter will count Time Stamp clock ticks from the pre-scaler. When written this counter and the pre-scaler will reset to 0 (write data is ignored). [15:0] read-write ECC_CTL ECC control 0x1080 32 read-write 0x0 0x10000 ECC_EN Enable ECC for CANFD SRAM When disabled also all error injection functionality is disabled. [16:16] read-write ECC_ERR_INJ ECC error injection 0x1084 32 read-write 0xFFFC 0x7F10FFFC ERR_ADDR Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed. When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address. When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown. Note that error reporting to the fault structure cannot be suppressed. [15:2] read-write ERR_EN Enable error injection (ECC_EN must be 1). When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address. When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set). When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or AHB bus. [20:20] read-write ERR_PAR ECC Parity bits to use for ECC error injection at address ERR_ADDR. [30:24] read-write CANFD1 0x40540000 SCB0 Serial Communications Block (SPI/UART/I2C) SCB 0x40600000 0 65536 registers CTRL Generic control 0x0 32 read-write 0x300400F 0x9303D70F OVS N/A [3:0] read-write EC_AM_MODE Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. In UART mode this field should be '0'. [8:8] read-write EC_OP_MODE Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). In UART mode this field should be '0'. [9:9] read-write EZ_MODE Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. In UART mode this field should be '0'. [10:10] read-write CMD_RESP_MODE Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled. '1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). [12:12] read-write MEM_WIDTH Determines the number of bits per FIFO data element. [15:14] read-write BYTE 8-bit FIFO data elements. This mode provides the biggest amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. 0 HALFWORD 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 15]. 1 WORD 32-bit FIFO data elements. This mode provides the smallest amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH can be in a range of [0, 31]. 2 RSVD N/A 3 ADDR_ACCEPT Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers. In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. [16:16] read-write BLOCK Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX. [17:17] read-write MODE N/A [25:24] read-write I2C Inter-Integrated Circuits (I2C) mode. 0 SPI Serial Peripheral Interface (SPI) mode. 1 UART Universal Asynchronous Receiver/Transmitter (UART) mode. 2 EC_ACCESS used to enable I2CS_EC or SPIS_EC access to internal SRAM memory. 0: enable clock_scb_en, has no effect on ec_busy_pp 1: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access) Before going to deepsleep this field should be set to 1. when waking up from DeepSleep power mode, and PLL is locked (clk_scb is at expected frequency), this filed should be set to 0. [28:28] read-write ENABLED IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: - Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. - Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. - Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. - Program CTRL to enable IP, select the specific operation mode and oversampling factor. Generally hen the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). Specific to SPI master case, when SCB is idle, below registers can be changed without disabling SCB block, TX_CTRL TX_FIFO_CTRL RX_CTRL RX_FIFO_CTRL SPI_CTRL.SSEL, [31:31] read-write STATUS Generic status 0x4 32 read-only 0x0 0x0 EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. [0:0] read-only CMD_RESP_CTRL Command/response control 0x8 32 read-write 0x0 0x1FF01FF BASE_RD_ADDR I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. [8:0] read-write BASE_WR_ADDR I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. [24:16] read-write CMD_RESP_STATUS Command/response status 0xC 32 read-only 0x0 0x0 CURR_RD_ADDR I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. [8:0] read-only CURR_WR_ADDR I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. [24:16] read-only CMD_RESP_EC_BUS_BUSY Indicates whether there is an ongoing bus transfer to the IP. '0': no ongoing bus transfer. '1': ongoing bus transfer. For SPI, the field is '1' when the slave is selected. For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. [30:30] read-only CMD_RESP_EC_BUSY Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note: - When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable). - When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW. - When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW. Note that this update lasts one I2C clock cycle, or two SPI clock cycles. [31:31] read-only SPI_CTRL SPI control 0x20 32 read-write 0x3000010 0x8F017F3F SSEL_CONTINUOUS Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: data frames are always separated by slave deselection. [0:0] read-write SELECT_PRECEDE Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. [1:1] read-write CPHA Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: - Motorola mode 0. CPOL is '0', CPHA is '0': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. - Motorola mode 1. CPOL is '0', CPHA is '1': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 2. CPOL is '1', CPHA is '0': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 3. CPOL is '1', CPHA is '1': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. In SPI Motorola submode, all four CPOL/CPHA modes are valid. in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. [2:2] read-write CPOL Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: - CPOL is '0': SCLK is '0' when not transmitting data. - CPOL is '1': SCLK is '1' when not transmitting data. [3:3] read-write LATE_MISO_SAMPLE Changes the SCLK edge on which MISO is captured. Only used in master mode. When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. [4:4] read-write SCLK_CONTINUOUS Only applicable in master mode. '0': SCLK is generated, when the SPI master is enabled and data is transmitted. '1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality. [5:5] read-write SSEL_POLARITY0 Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes: '0': slave select is low/'0' active. '1': slave select is high/'1' active. For Texas Instruments submode: '0': high/'1' active precede/coincide pulse. '1': low/'0' active precede/coincide pulse. [8:8] read-write SSEL_POLARITY1 Slave select polarity. [9:9] read-write SSEL_POLARITY2 Slave select polarity. [10:10] read-write SSEL_POLARITY3 Slave select polarity. [11:11] read-write SSEL_SETUP_DEL Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit). '0': 0.75 SPI clock cycles '1': 1.75 SPI clock cycles Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0, CTRL.OVS>=3. above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle. [12:12] read-write SSEL_HOLD_DEL Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit, and SELECT deactivation). '0': 0.75 SPI clock cycles '1': 1.75 SPI clock cycles Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0, CTRL.OVS>=3. above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle. [13:13] read-write SSEL_INTER_FRAME_DEL Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation). '0': 1.5 SPI clock cycles '1': 2.5 SPI clock cycles Only applies in SPI MOTOROLA submode and when SPI_CTRL.SSEL_CONTINUOUS=0, CTRL.OVS>=3. above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle. [14:14] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. '0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin. '1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. [16:16] read-write MODE N/A [25:24] read-write SPI_MOTOROLA SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. 0 SPI_TI SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. 1 SPI_NS SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. 2 SSEL Selects one of the four incoming/outgoing SPI slave select signals: - 0: Slave 0, SSEL[0]. - 1: Slave 1, SSEL[1]. - 2: Slave 2, SSEL[2]. - 3: Slave 3, SSEL[3]. The IP should be disabled when changes are made to this field. [27:26] read-write MASTER_MODE Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. [31:31] read-write SPI_STATUS SPI status 0x24 32 read-only 0x0 0x0 BUS_BUSY SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. [0:0] read-only SPI_EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. [1:1] read-only CURR_EZ_ADDR SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only SPI_TX_CTRL SPI transmitter control 0x28 32 read-write 0x0 0x30 PARITY Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. [4:4] read-write PARITY_ENABLED Parity generation enabled ('1') or not ('0'). [5:5] read-write SPI_RX_CTRL SPI receiver control 0x2C 32 read-write 0x0 0x130 PARITY Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. [4:4] read-write PARITY_ENABLED Parity checking enabled ('1') or not ('0'). [5:5] read-write DROP_ON_PARITY_ERROR Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. [8:8] read-write UART_CTRL UART control 0x40 32 read-write 0x3000000 0x3010000 LOOPBACK Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'. This allows a SCB UART transmitter to communicate with its receiver counterpart. [16:16] read-write MODE N/A [25:24] read-write UART_STD Standard UART submode. 0 UART_SMARTCARD SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. 1 UART_IRDA Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. 2 UART_TX_CTRL UART transmitter control 0x44 32 read-write 0x2 0x137 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. [2:0] read-write PARITY Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware [5:5] read-write RETRY_ON_NACK When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. [8:8] read-write UART_RX_CTRL UART receiver control 0x48 32 read-write 0xA0002 0x10F3777 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value. [2:0] read-write PARITY Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. [5:5] read-write POLARITY Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. [6:6] read-write DROP_ON_PARITY_ERROR Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). [8:8] read-write DROP_ON_FRAME_ERROR Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. [9:9] read-write MP_MODE Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped. [10:10] read-write LIN_MODE Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. [12:12] read-write SKIP_START Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. [13:13] read-write BREAK_WIDTH Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. [19:16] read-write BREAK_LEVEL 0: low level pulse detection, like Break field in LIN protocol 1: high level pulse detection, like IFS field in CXPI protocol, or idle line state in UART [24:24] read-write UART_RX_STATUS UART receiver status 0x4C 32 read-only 0x0 0x0 BR_COUNTER Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. [11:0] read-only UART_FLOW_CTRL UART flow control 0x50 32 read-write 0x0 0x30100FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes). [7:0] read-write RTS_POLARITY Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive. '1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive. During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity. [16:16] read-write CTS_POLARITY Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive. '1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive. [24:24] read-write CTS_ENABLED Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). [25:25] read-write I2C_CTRL I2C control 0x60 32 read-write 0xFB88 0xC001FBFF HIGH_PHASE_OVS Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles. [3:0] read-write LOW_PHASE_OVS Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. The field is mainly used in master mode. In slave mode, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be >= 8 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles. in slave mode, this field is used to define number of clk_scb cycles for tSU-DAT timing (from ACK/NACK/data ready, to SCL rising edge (released from I2C slave clock stretching)) [7:4] read-write M_READY_DATA_ACK When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. [8:8] read-write M_NOT_READY_DATA_NACK When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). [9:9] read-write S_GENERAL_IGNORE When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. [11:11] read-write S_READY_ADDR_ACK When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. [12:12] read-write S_READY_DATA_ACK When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. [13:13] read-write S_NOT_READY_ADDR_NACK For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when: - EC_AM is '0', EC_OP is '0' and non EZ mode. Functionality is as follows: - 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): - EC_AM is '1' and EC_OP is '0'. - EC_AM is '1' and general call address match. - EC_AM is '1' and non EZ mode. Functionality is as follows: - 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). - 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled. [14:14] read-write S_NOT_READY_DATA_NACK For internally clocked logic only. Only used when: - non EZ mode. Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). [15:15] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. [16:16] read-write SLAVE_MODE Slave mode enabled ('1') or not ('0'). [30:30] read-write MASTER_MODE Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. [31:31] read-write I2C_STATUS I2C status 0x64 32 read-only 0x0 0x35 BUS_BUSY I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). [0:0] read-only I2C_EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. [1:1] read-only I2CS_IC_BUSY Indicates whether the internally clocked slave logic is being accessed by external I2C master. --set at ADDR_MATCH --clear at START/RESET, STOP detection, or BUS_ERROR This bit can be used by SW to determine whether I2CS_IC is busy before entering DeepSleep. [2:2] read-only S_READ I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. [4:4] read-only M_READ I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. [5:5] read-only CURR_EZ_ADDR I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only I2C_M_CMD I2C master command 0x68 32 read-write 0x0 0x1F M_START When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. [0:0] read-write M_START_ON_IDLE When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. [1:1] read-write M_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. [2:2] read-write M_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. [3:3] read-write M_STOP When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. [4:4] read-write I2C_S_CMD I2C slave command 0x6C 32 read-write 0x0 0x3 S_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). [0:0] read-write S_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. [1:1] read-write I2C_CFG I2C configuration 0x70 32 read-write 0x2A1013 0x303F1313 SDA_IN_FILT_TRIM Trim bits for 'i2c_sda_in' 50 ns filter. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [1:0] read-write SDA_IN_FILT_SEL Selection of 'i2c_sda_in' filter delay: '0': 0 ns. '1: 50 ns (filter enabled). [4:4] read-write SCL_IN_FILT_TRIM Trim bits for 'i2c_scl_in' 50 ns filter. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [9:8] read-write SCL_IN_FILT_SEL Selection of 'i2c_scl_in' filter delay: '0': 0 ns. '1: 50 ns (filter enabled). [12:12] read-write SDA_OUT_FILT0_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 0. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [17:16] read-write SDA_OUT_FILT1_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 1. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [19:18] read-write SDA_OUT_FILT2_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 2. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [21:20] read-write SDA_OUT_FILT_SEL Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns. '1': 50 ns (filter 0 enabled). '2': 100 ns (filters 0 and 1 enabled). '3': 150 ns (filters 0, 1 and 2 enabled). [29:28] read-write TX_CTRL Transmitter control 0x200 32 read-write 0x107 0x1011F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 31]. For I2C the only valid value is 7. [4:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write OPEN_DRAIN Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. '0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. '1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). The open drain mode is supported for: - UART mode, 'uart_tx' IO cell. - SPI mode, 'spi_miso' IO cell. not applicable to I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. (I2C SCL/SDA always work in open-drain mode) [16:16] read-write TX_FIFO_CTRL Transmitter FIFO control 0x204 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. [7:0] read-write CLEAR When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. [17:17] read-write TX_FIFO_STATUS Transmitter FIFO status 0x208 32 read-only 0x0 0xFFFF81FF USED Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). [8:0] read-only SR_VALID Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read by the hardware. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written. [31:24] read-only TX_FIFO_WR Transmitter FIFO write 0x240 32 write-only 0x0 0xFFFFFFFF DATA Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used. A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. [31:0] write-only RX_CTRL Receiver control 0x300 32 read-write 0x107 0x31F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 31]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. [4:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write MEDIAN Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. [9:9] read-write RX_FIFO_CTRL Receiver FIFO control 0x304 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. [7:0] read-write CLEAR When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. [17:17] read-write RX_FIFO_STATUS Receiver FIFO status 0x308 32 read-only 0x0 0xFFFF81FF USED Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). [8:0] read-only SR_VALID Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written by the hardware. [31:24] read-only RX_MATCH Slave address and mask 0x310 32 read-write 0x0 0xFF00FF ADDR Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). [7:0] read-write MASK Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK)). [23:16] read-write RX_FIFO_RD Receiver FIFO read 0x340 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used. This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [31:0] read-only RX_FIFO_RD_SILENT Receiver FIFO read silent 0x344 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [31:0] read-only INTR_CAUSE Active clocked interrupt signal 0xE00 32 read-only 0x0 0x3F M Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. [0:0] read-only S Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. [1:1] read-only TX Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. [2:2] read-only RX Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. [3:3] read-only I2C_EC Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. [4:4] read-only SPI_EC Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. [5:5] read-only INTR_I2C_EC Externally clocked I2C interrupt request 0xE80 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request (with address match). Only used when EC_AM is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (I2C STOP). Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [3:3] read-write INTR_I2C_EC_MASK Externally clocked I2C interrupt mask 0xE88 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_I2C_EC_MASKED Externally clocked I2C interrupt masked 0xE8C 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_SPI_EC Externally clocked SPI interrupt request 0xEC0 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request when externally clocked selection is '1'. Only used when EC_AM is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (SPI deselection). Only available in EZ and CMD_RESP mode and when EC_OP is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only used in EZ and CMD_RESP modes and when EC_OP is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. Only used in EZ and CMD_RESP modes and when EC_OP is '1'. [3:3] read-write INTR_SPI_EC_MASK Externally clocked SPI interrupt mask 0xEC8 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_SPI_EC_MASKED Externally clocked SPI interrupt masked 0xECC 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_M Master interrupt request 0xF00 32 read-write 0x0 0x317 I2C_ARB_LOST I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. [0:0] read-write I2C_NACK I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). [1:1] read-write I2C_ACK I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). [2:2] read-write I2C_STOP I2C master STOP. Set to '1', when the master has transmitted a STOP. [4:4] read-write I2C_BUS_ERROR I2C master bus error (unexpected detection of START or STOP condition). [8:8] read-write SPI_DONE SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. [9:9] read-write INTR_M_SET Master interrupt set request 0xF04 32 read-write 0x0 0x317 I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASK Master interrupt mask 0xF08 32 read-write 0x0 0x317 I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASKED Master interrupt masked request 0xF0C 32 read-only 0x0 0x317 I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_DONE Logical and of corresponding request and mask bits. [9:9] read-only INTR_S Slave interrupt request 0xF40 32 read-write 0x0 0xFFF I2C_ARB_LOST I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [0:0] read-write I2C_NACK I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). [1:1] read-write I2C_ACK I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). [2:2] read-write I2C_WRITE_STOP I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected). [3:3] read-write I2C_STOP I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. [4:4] read-write I2C_START I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. [5:5] read-write I2C_ADDR_MATCH I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. [6:6] read-write I2C_GENERAL I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. [7:7] read-write I2C_BUS_ERROR I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [8:8] read-write SPI_EZ_WRITE_STOP SPI slave deselected after a write EZ SPI transfer occurred. [9:9] read-write SPI_EZ_STOP SPI slave deselected after any EZ SPI transfer occurred. [10:10] read-write SPI_BUS_ERROR SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [11:11] read-write INTR_S_SET Slave interrupt set request 0xF44 32 read-write 0x0 0xFFF I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_START Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASK Slave interrupt mask 0xF48 32 read-write 0x0 0xFFF I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_START Mask bit for corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Mask bit for corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Mask bit for corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Mask bit for corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASKED Slave interrupt masked request 0xF4C 32 read-only 0x0 0xFFF I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_WRITE_STOP Logical and of corresponding request and mask bits. [3:3] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_START Logical and of corresponding request and mask bits. [5:5] read-only I2C_ADDR_MATCH Logical and of corresponding request and mask bits. [6:6] read-only I2C_GENERAL Logical and of corresponding request and mask bits. [7:7] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_EZ_WRITE_STOP Logical and of corresponding request and mask bits. [9:9] read-only SPI_EZ_STOP Logical and of corresponding request and mask bits. [10:10] read-only SPI_BUS_ERROR Logical and of corresponding request and mask bits. [11:11] read-only INTR_TX Transmitter interrupt request 0xF80 32 read-write 0x0 0x7F3 TRIGGER Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL. Only used in FIFO mode. [0:0] read-write NOT_FULL TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2) MEM_WIDTH is '0': # entries != FF_DATA_NR. MEM_WIDTH is '1': # entries != FF_DATA_NR/2. MEM_WIDTH is '2': # entries != FF_DATA_NR/4. Only used in FIFO mode. [1:1] read-write EMPTY TX FIFO is empty; i.e. it has 0 entries. Only used in FIFO mode. [4:4] read-write OVERFLOW Attempt to write to a full TX FIFO. Only used in FIFO mode. [5:5] read-write UNDERFLOW Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. Only used in FIFO mode. [6:6] read-write BLOCKED AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write UART_NACK UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. [8:8] read-write UART_DONE UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit. [9:9] read-write UART_ARB_LOST UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit. [10:10] read-write INTR_TX_SET Transmitter interrupt set request 0xF84 32 read-write 0x0 0x7F3 TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write EMPTY Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write UART_NACK Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write UART_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASK Transmitter interrupt mask 0xF88 32 read-write 0x0 0x7F3 TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Mask bit for corresponding bit in interrupt request register. [1:1] read-write EMPTY Mask bit for corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write UART_NACK Mask bit for corresponding bit in interrupt request register. [8:8] read-write UART_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Mask bit for corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASKED Transmitter interrupt masked request 0xF8C 32 read-only 0x0 0x7F3 TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_FULL Logical and of corresponding request and mask bits. [1:1] read-only EMPTY Logical and of corresponding request and mask bits. [4:4] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only UART_NACK Logical and of corresponding request and mask bits. [8:8] read-only UART_DONE Logical and of corresponding request and mask bits. [9:9] read-only UART_ARB_LOST Logical and of corresponding request and mask bits. [10:10] read-only INTR_RX Receiver interrupt request 0xFC0 32 read-write 0x0 0xFED TRIGGER More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL. Only used in FIFO mode. [0:0] read-write NOT_EMPTY RX FIFO is not empty. Only used in FIFO mode. [2:2] read-write FULL RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2) MEM_WIDTH is '0': # entries == FF_DATA_NR. MEM_WIDTH is '1': # entries == FF_DATA_NR/2. MEM_WIDTH is '2': # entries == FF_DATA_NR/4. Only used in FIFO mode. [3:3] read-write OVERFLOW Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. Only used in FIFO mode. [5:5] read-write UNDERFLOW Attempt to read from an empty RX FIFO. Only used in FIFO mode. [6:6] read-write BLOCKED AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write FRAME_ERROR Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error: Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. [8:8] read-write PARITY_ERROR Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. [9:9] read-write BAUD_DETECT LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit. [10:10] read-write BREAK_DETECT Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. [11:11] read-write INTR_RX_SET Receiver interrupt set request 0xFC4 32 read-write 0x0 0xFED TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Write with '1' to set corresponding bit in interrupt status register. [2:2] read-write FULL Write with '1' to set corresponding bit in interrupt status register. [3:3] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt status register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt status register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt status register. [7:7] read-write FRAME_ERROR Write with '1' to set corresponding bit in interrupt status register. [8:8] read-write PARITY_ERROR Write with '1' to set corresponding bit in interrupt status register. [9:9] read-write BAUD_DETECT Write with '1' to set corresponding bit in interrupt status register. [10:10] read-write BREAK_DETECT Write with '1' to set corresponding bit in interrupt status register. [11:11] read-write INTR_RX_MASK Receiver interrupt mask 0xFC8 32 read-write 0x0 0xFED TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Mask bit for corresponding bit in interrupt request register. [2:2] read-write FULL Mask bit for corresponding bit in interrupt request register. [3:3] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write FRAME_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write PARITY_ERROR Mask bit for corresponding bit in interrupt request register. [9:9] read-write BAUD_DETECT Mask bit for corresponding bit in interrupt request register. [10:10] read-write BREAK_DETECT Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_RX_MASKED Receiver interrupt masked request 0xFCC 32 read-only 0x0 0xFED TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_EMPTY Logical and of corresponding request and mask bits. [2:2] read-only FULL Logical and of corresponding request and mask bits. [3:3] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only FRAME_ERROR Logical and of corresponding request and mask bits. [8:8] read-only PARITY_ERROR Logical and of corresponding request and mask bits. [9:9] read-only BAUD_DETECT Logical and of corresponding request and mask bits. [10:10] read-only BREAK_DETECT Logical and of corresponding request and mask bits. [11:11] read-only SCB1 0x40610000 SCB2 0x40620000 SCB3 0x40630000 SCB4 0x40640000 SCB5 0x40650000 SCB6 0x40660000 SCB7 0x40670000 SCB8 0x40680000 SCB9 0x40690000 SCB10 0x406A0000 SCB11 0x406B0000 TDM0 TDM TDM 0x40810000 0 65536 registers 4 512 TDM_STRUCT[%s] TDM structure 0x00008000 TDM_TX_STRUCT TDM TX structure 0x00000000 TX_CTL TX control 0x0 32 read-write 0x10000 0x8001300F WORD_SIZE PCM word size: '0': 8 bit. '1': 10 bit. '2': 12 bit. '3': 14 bit. '4': 16 bit. '5': 18 bit. '6': 20 bit. '7': 24 bit. '8': 32 bit. '9'-'15': Undefined. [3:0] read-write SIZE_8 N/A 0 SIZE_10 N/A 1 SIZE_12 N/A 2 SIZE_14 N/A 3 SIZE_16 N/A 4 SIZE_18 N/A 5 SIZE_20 N/A 6 SIZE_24 N/A 7 SIZE_32 N/A 8 FORMAT Format: '0': Left-aligned delayed. '1': Left-aligned. '2': Right-aligned delayed. '3': Right-aligned. [13:12] read-write LEFT_DELAYED N/A 0 LEFT N/A 1 RIGHT_DELAYED N/A 2 RIGHT N/A 3 MS Master/slave setting: '0': Slave. - External transmitter 'tdm_tx_sck_in' and transmitter 'tdm_tx_fsync_in'. '1': Master. - Interface clock 'clk_if' is used to generate transmitter 'tdm_tx_sck_out' and transmitter 'tdm_tx_fsync_out'. [16:16] read-write SLAVE N/A 0 MASTER N/A 1 ENABLED Transmitter (TX) enable: '0': Disabled. All non-retained MMIO registers (e.g. the TX_FIFO_STATUS and INTR_TX registers) have their fields reset to their default value. '1': Enabled. Note: when all transmitters and receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). [31:31] read-write TX_IF_CTL TX interface control 0x10 32 read-write 0x1F018707 0x9F1FB7FF CLOCK_DIV Interface clock divider (legal range [1, 255]). The TDM interface 'tdm_tx_sck_out' output signal is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle clock. Note: Used in master configuration only. [7:0] read-write CLOCK_SEL Interface clock 'clk_if' selection: '0': SRSS clock clk_if_srss[0]. '1': SRSS clock clk_if_srss[1]. '2': SRSS clock clk_if_srss[2]. '3': SRSS clock clk_if_srss[3]. '4': Master interface clock 'tdm_tx_mck_in'. '5'-'7': undefined. Note: the application is always required to program this field to a value different from the default. [10:8] read-write SEL_SRSS_CLOCK0 N/A 0 SEL_SRSS_CLOCK1 N/A 1 SEL_SRSS_CLOCK2 N/A 2 SEL_SRSS_CLOCK3 N/A 3 SEL_TDM_TX_MCK_IN N/A 4 SCK_POLARITY Clock polarity: '0': Clock signal is used 'as is'. '1': Clock signal is inverted. Note: Used in BOTH master and slave configurations. [12:12] read-write FSYNC_POLARITY Channel synchronization polarity: '0': Channel synchronization signal is used 'as is'. '1': Channel synchronization signal is inverted. Note: Used in BOTH master and slave configurations. [13:13] read-write FSYNC_FORMAT Channel synchronization pulse format: '0': Duration of a single bit period. '1': Duration of the first channel. [15:15] read-write BIT_PERIOD N/A 0 CH_PERIOD N/A 1 CH_NR Number of channels in the frame: '0': Undefined/illegal. '1': 2 channels. '2': 3 channels. ... '31': 32 channels. Note: the field value chould be less than CH_NR (the number of support channels). Note: the TX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels. [20:16] read-write CH_SIZE Channel size: '0'-'2': Undefined/illegal. '3': 4 bits. ... '31': 32 bits. Note: if TX_CTL.WORD_SIZE is greater than CH_SIZE, the more significant bits of the word are transmitted and the lesser significant bits of the word are dropped. [28:24] read-write SIZE_1 N/A 0 SIZE_2 N/A 1 SIZE_32 N/A 31 I2S_MODE I2S mode setting: '0': TDM mode. '1': I2S mode. [31:31] read-write TDM N/A 0 I2S N/A 1 TX_CH_CTL TX channel control 0x14 32 read-write 0x0 0xFFFFFFFF CH_EN Channel enables: channel i is controlled by CH_EN[i]. '0': Disabled. The TX FIFO does not produce channel i words and the transmitted channel i words on the interface are not driven (the output enable of the 'tdm_tx_sd_out' output signal is not driven). '1': Enabled. Note: Only bit 0 through TX_IF_CTL.CH_NR may be set to '1'; i.e. only channels that are present in the frame can be enabled. [31:0] read-write TX_TEST_CTL TX test control 0x20 32 read-write 0x0 0x80000000 ENABLED Test mode enable. '0': Disabled. Functional mode. - Transmitter tx_sck_in = IOSS tdm_tx_sck_in. - Transmitter tx_fsync_in = IOSS tdm_tx_fsync_in. - Receiver rx_sd_in = IOSS tdm_rx_sd_in. '1': Enabled. Test mode (intended to be used with (slave transmitter, master receiver) configuration). - Transmitter tx_sck_in = Receiver tdm_rx_sck_out. - Transmitter tx_fsync_in = Receiver tdm_rx_fsync_out. - Receiver rx_sd_in = Transmitter tdm_tx_sd_out. Note: TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1' simultaneously. [31:31] read-write FUNCTIONAL N/A 0 TEST N/A 1 TX_ROUTE_CTL TX route control 0x24 32 read-write 0x0 0x3 MODE Controls routing to the TX slave signalling inputs (FSYNC/SCK): '0': TX slave signaling indipendent from RX signaling: - Transmitter tx_sck_in = IOSS tdm_tx_sck_in - Transmitter tx_fsync_in = IOSS tdm_tx_fsync_in '1': TX slave signalling inputs driven by RX Slave: - Transmitter tx_sck_in = IOSS tdm_rx_sck_in - Transmitter tx_fsync_in = IOSS tdm_rx_fsync_in '2': TX slave signalling inputs driven by RX Master: - Transmitter tx_sck_in = receiver tdm_rx_sck_out - Transmitter tx_fsync_in = receiver tdm_rx_fsync_out Note: MODE=0 is the default behaviour. MODE=1 or 2 is intended to allow the TX slave to share the same signaling used by the RX. This feature can be used to reduce the number of IO pins necessary to connect to an external codec supporting common TX/RX signaling. Note: when MODE=1 or 2, TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1'. [1:0] read-write TX_IN_DRIVEN_BY_IOSS_TX_IN N/A 0 TX_IN_DRIVEN_BY_IOSS_RX_IN N/A 1 TX_IN_DRIVEN_BY_RX_OUT N/A 2 TX_FIFO_CTL TX FIFO control 0x80 32 read-write 0x0 0xF007F TRIGGER_LEVEL Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated: - INTR_TX.FIFO_TRIGGER = (# FIFO entries < TRIGGER_LEVEL) [6:0] read-write MUTE Mute functionality: '0': HW uses TX FIFO data. '1': HW uses a constant PCM data value of '0'. Mute does advance the FIFO read pointer. Note: HW ensures that mute functionality synchronizes on the first channel of a frame to ensure that either all or none of the frame's channels are muted. [16:16] read-write FREEZE Freeze functionality: '0': HW uses TX FIFO data and advances the FIFO read pointer. '1': HW uses a constant PCM data value of '0' or the previous channel PCM data is replayed. Freeze does not advance the FIFO read pointer (the FIFO data is not used). Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time. Note: This functionality is intended for debugging purposes. [17:17] read-write ACTIVE Activate functionality: '0': Transmitter off. The FIFO_UNDERFLOW interrupt cause will not be activated. '1': Transmitter on. The FIFO_UNDERFLOW interrupt may be activated (when an underflow event occurs). Note: This functionality is intended for startup purposes. [18:18] read-write REPLAY Replay functionality (used when FREEZE is '1' or in case of a FIFO underflow event): '0': HW uses a constant PCM data value of '0'. '1': HW uses the previous PCM data value. [19:19] read-write TX_FIFO_STATUS TX FIFO status 0x84 32 read-only 0x0 0x7F7F00FF USED Number of used/occupied entries in the TX FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full. [7:0] read-only RD_PTR TX FIFO read pointer: FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [22:16] read-only WR_PTR TX FIFO write pointer: FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [30:24] read-only TX_FIFO_WR TX FIFO write 0x88 32 write-only 0x0 0xFFFFFFFF DATA Data (PCM sample) written to the TX FIFO. Writing adds the data to the TX FIFO; i.e. behavior is similar to that of a PUSH operation (TX_FIFO_STATUS.WR_PTR is incremented and TX_FIFO_STATUS.USED is incremented). The write data (DATA) should be right aligned when it is written to the FIFO entry (data[31:0]): - 8 bit, data[31:0] = DATA[7:0] << 24. - 10 bit, data[31:0] = DATA[9:0] << 22. - 12 bit, data[31:0] = DATA[11:0] << 20. - 14 bit, data[31:0] = DATA[13:0] << 18. - 16 bit, data[31:0] = DATA[15:0] << 16. - 18 bit, data[31:0] = DATA[17:0] << 14. - 20 bit, data[31:0] = DATA[19:0] << 12. - 24 bit, data[31:0] = DATA[23:0] << 8. - 32 bit, data[31:0] = DATA[31:0]. Note: Writing to a full TX FIFO activates INTR.TX_FIFO_OVERFLOW. [31:0] write-only INTR_TX Interrupt 0xC0 32 read-write 0x0 0x107 FIFO_TRIGGER HW sets this field to '1', when a TX trigger is generated. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a full TX FIFO (TX_FIFO_STATUS.USED is '128'). [1:1] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an (almost) empty TX FIFO (TX_FIFO_STATUS.USED < 'number of enabled channels per frame'). This is referred to as an underflow event. Note: HW ensures that either all or none of the frame's channels are transmitted. In a TX FIFO underflow situation, HW replays previous PCM data or uses a constant PCM data value of '0'. [2:2] read-write IF_UNDERFLOW HW sets this field to '1', when PCM samples are not generated in time for the interface logic (interface underflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface underflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_TX.IF_UNDERFLOW does not resolve the interface underflow). Note: This functionality is intended for debug purposes. [8:8] read-write INTR_TX_SET Interrupt set 0xC4 32 read-write 0x0 0x107 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [1:1] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [2:2] read-write IF_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [8:8] read-write INTR_TX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x107 FIFO_TRIGGER Mask for corresponding field in INTR_TX register. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR_TX register. [1:1] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR_TX register. [2:2] read-write IF_UNDERFLOW Mask for corresponding field in INTR_TX register. [8:8] read-write INTR_TX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x107 FIFO_TRIGGER Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [1:1] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [2:2] read-only IF_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [8:8] read-only TDM_RX_STRUCT TDM RX structure 0x00000100 RX_CTL RX control 0x0 32 read-write 0x100 0x8001310F WORD_SIZE PCM word size: '0': 8 bit. '1': 10 bit. '2': 12 bit. '3': 14 bit. '4': 16 bit. '5': 18 bit. '6': 20 bit. '7': 24 bit. '8': 32 bit. '9'-'15': Undefined. [3:0] read-write SIZE_8 N/A 0 SIZE_10 N/A 1 SIZE_12 N/A 2 SIZE_14 N/A 3 SIZE_16 N/A 4 SIZE_18 N/A 5 SIZE_20 N/A 6 SIZE_24 N/A 7 SIZE_32 N/A 8 WORD_SIGN_EXTEND Word extension: '0': zero extension. '1': sign extension. [8:8] read-write ZERO_EXTEND N/A 0 SIGN_EXTEND N/A 1 FORMAT Format: '0': Left-aligned delayed. '1': Left-aligned. '2': Right-aligned delayed. '3': Right-aligned. [13:12] read-write LEFT_DELAYED N/A 0 LEFT N/A 1 RIGHT_DELAYED N/A 2 RIGHT N/A 3 MS Master/slave setting: '0': Slave. - External receiver 'tdm_rx_sck_in' and receiver 'tdm_rx_fsync_in'. '1': Master. - Interface clock 'clk_if' is used to generate receiver 'tdm_rx_sck_out' and receiver 'tdm_rx_fsync_out'. [16:16] read-write SLAVE N/A 0 MASTER N/A 1 ENABLED Receiver (RX) enable: '0': Disabled. All non-retained MMIO registers (e.g. the RX_FIFO_STATUS and INTR_RX registers) have their fields reset to their default value. '1': Enabled. Note: when all transmitters and receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). [31:31] read-write RX_IF_CTL RX interface control 0x10 32 read-write 0x1F018707 0xFF1FF7FF CLOCK_DIV Interface clock divider (legal range [1, 255]). The TDM interface 'tdm_rx_sck_out' output signals is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle clock. Note: Used in master configuration only. Note: Due to delays in the IO SubSystem (specifically the IO cells), the maximum TDM interface clock 'tdm_rx_sck_out' may be restricted. As a result, the maximum bitrate is less than the theoretical maximum (32 channels, 32 bits per channel and a high Fs of e.g. 48 kHz). This restriction is most applicable to the master, receiver configuration. [7:0] read-write CLOCK_SEL Interface clock 'clk_if' selection: '0': SRSS clock clk_if_srss[0]. '1': SRSS clock clk_if_srss[1]. '2': SRSS clock clk_if_srss[2]. '3': SRSS clock clk_if_srss[3]. '4': Master interface clock 'tdm_rx_mck_in'. '5'-'7': undefined. Note: the application is always required to program this field to a value different from the default. [10:8] read-write SEL_SRSS_CLOCK0 N/A 0 SEL_SRSS_CLOCK1 N/A 1 SEL_SRSS_CLOCK2 N/A 2 SEL_SRSS_CLOCK3 N/A 3 SEL_TDM_RX_MCK_IN N/A 4 SCK_POLARITY Clock polarity: '0': Clock signal is used 'as is'. '1': Clock signal is inverted. Note: Used in BOTH master and slave configurations. [12:12] read-write FSYNC_POLARITY Channel synchronization polarity: '0': Channel synchronization signal is used 'as is'. '1': Channel synchronization signal is inverted. Note: Used in BOTH master and slave configurations. [13:13] read-write LATE_SAMPLE Interface late sample sample delay: Slave configuration (RX_CTL.MS is '0'). '0': Sample PCM bit value on rising edge (SCK_POLARITY is '0') or falling edge (SCK_POLARITY is '1') of receiver 'rx_sck_in'. '1': Sample PCM bit value on falling edge (SCK_POLARITY is '0') or rising edge (SCK_POLARITY is '1') of receiver 'rx_sck_in' (half a cycle delay). Master configuration (RX_CTL.MS is '1'). '0': Sample PCM bit value on rising edge (SCK_POLARITY is '0') or falling edge (SCK_POLARITY is '1') of receiver 'rx_sck_out'. '1': Sample PCM bit value on falling edge (SCK_POLARITY is '0') or rising edge (SCK_POLARITY is '1') of receiver 'rx_sck_out' (half a cycle delay). Note: This field can be set to '1' when the roundtrip delay is large (typically) in a master receiver configuration. [14:14] read-write RISING N/A 0 FALLING N/A 1 FSYNC_FORMAT Channel synchronization pulse format: '0': Duration of a single bit period. '1': Duration of the first channel. [15:15] read-write BIT_PERIOD N/A 0 CH_PERIOD N/A 1 CH_NR Number of channels in the frame: '0': Undefined/illegal. '1': 2 channels. '2': 3 channels. ... '31': 32 channels. Note: the field value chould be less than CH_NR (the number of support channels). Note: the RX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels. [20:16] read-write CH_SIZE Channel size: '0'-'2': Undefined/illegal. '3': 4 bits. ... '31': 32 bits. Note: if RX_CTL.WORD_SIZE is greater than CH_SIZE, the lesser significant bits of the word are filled with '0's. [28:24] read-write SIZE_1 N/A 0 SIZE_2 N/A 1 SIZE_32 N/A 31 LATE_CAPTURE Extra delay (in 'rx_sck_out' cycles) for capturing 'tdm_rx_sd_in': '0': no extra delay '1': 1 cycle extra delay '2': 2 cycles extra delay '3': 3 cycles extra delay Note: the value of this field pushes further out the capturing edges used by the receiver to sample 'tdm_rx_sd_in'. This function is intended to support very large round-trip delays in a master receiver configuration, where the delay at the receiver between 'tdm_rx_fsync_out' and the arrival of the first bit on 'tdm_rx_sd_in' is multiple clock cycles. [30:29] read-write EXTRA_DELAY_0 N/A 0 EXTRA_DELAY_1 N/A 1 EXTRA_DELAY_2 N/A 2 EXTRA_DELAY_3 N/A 3 I2S_MODE I2S mode setting: '0': TDM mode. '1': I2S mode. [31:31] read-write TDM N/A 0 I2S N/A 1 RX_CH_CTL RX channel control 0x14 32 read-write 0x0 0xFFFFFFFF CH_EN Channel enables: channel i is controlled by CH_EN[i]. '0': Disabled. The RX FIFO does not consume channel i words and the received channel i words on the interface are discarded. '1': Enabled.. Note: Only bit 0 through RX_IF_CTL.CH_NR may be set to '1'; i.e. only channels that are present in the frame can be enabled. [31:0] read-write RX_TEST_CTL RX test control 0x20 32 read-write 0x0 0x80000000 ENABLED Test mode enable. '0': Disabled. Functional mode. - Receiver rx_sck_in = IOSS tdm_rx_sck_in. - Receiver rx_fsync_in = IOSS tdm_rx_fsync_in. - Receiver rx_sd_in = IOSS tdm_rx_sd_in. '1': Enabled. Test mode (intended to be used with (master transmitter, slave receiver) configuration). - Receiver rx_sck_in = Transmitter tdm_tx_sck_out. - Receiver rx_fsync_in = Transmitter tdm_tx_fsync_out. - Receiver rx_sd_in = Transmitter tdm_tx_sd_out. Note: TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1' simultaneously. [31:31] read-write FUNCTIONAL N/A 0 TEST N/A 1 RX_ROUTE_CTL RX route control 0x24 32 read-write 0x0 0x3 MODE Controls routing to the RX slave signalling inputs (FSYNC/SCK): '0': RX slave signaling indipendent from TX signaling: - Receiver rx_sck_in = IOSS tdm_rx_sck_in - Receiver rx_fsync_in = IOSS tdm_rx_fsync_in '1': RX slave signalling inputs driven by TX Slave: - Receiver rx_sck_in = IOSS tdm_tx_sck_in - Receiver rx_fsync_in = IOSS tdm_tx_fsync_in '2': RX slave signalling inputs driven by TX Master: - Receiver rx_sck_in = transmitter tdm_tx_sck_out - Receiver rx_fsync_in = transmitter tdm_tx_fsync_out Note: MODE=0 is the default behaviour. MODE=1 or 2 is intended to allow the RX slave to share the same signaling used by the TX. This feature can be used to reduce the number of IO pins necessary to connect to an external codec supporting common TX/RX signaling. Note: when MODE=1 or 2, TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1'. [1:0] read-write RX_IN_DRIVEN_BY_IOSS_RX_IN N/A 0 RX_IN_DRIVEN_BY_IOSS_TX_IN N/A 1 RX_IN_DRIVEN_BY_TX_OUT N/A 2 RX_FIFO_CTL RX FIFO control 0x80 32 read-write 0x0 0x6007F TRIGGER_LEVEL Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated: - INTR_RX.FIFO_TRIGGER = (# FIFO entries > TRIGGER_LEVEL) [6:0] read-write FREEZE Freeze functionality: '0': HW writes to the RX FIFO and advances the FIFO write pointer. '1': HW writes from the RX FIFO have no effect: freeze will not advance the FIFO write pointer. Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time. Note: This functionality is intended for debugging purposes. [17:17] read-write ACTIVE Activate functionality: '0': Receiver off. The FIFO_OVERFLOW interrupt cause will not be activated. '1': Receiver on. The FIFO_OVERFLOW interrupt may be activated (when an overflow event occurs). Note: This functionality is intended for stopping purposes. [18:18] read-write RX_FIFO_STATUS RX FIFO status 0x84 32 read-only 0x0 0x7F7F00FF USED Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full. [7:0] read-only RD_PTR RX FIFO read pointer: FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [22:16] read-only WR_PTR RX FIFO write pointer: FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [30:24] read-only RX_FIFO_RD RX FIFO read 0x88 32 read-only 0x0 0xFFFFFFFF DATA Data (PCM sample) read from the RX FIFO. Reading removes the data from the RX FIFO; i.e. behavior is similar to that of a POP operation (RX_FIFO_STATUS.RD_PTR is incremented and RX_FIFO_STATUS.USED is decremented). The read data (DATA) is right aligned (unused bit positions follow the specified sign extension per RX_CTL.WORD_SIGN_EXTEND) when it is read from the FIFO entry (data[31:0]): - 8 bit, DATA[7:0] = data[31:24]. - 10 bit, DATA[9:0] = data[31:22]. - 12 bit, DATA[11:0] = data[31:20]. - 14 bit, DATA[13:0] = data[31:18]. - 16 bit, DATA[15:0] = data[31:16]. - 18 bit, DATA[17:0] = data[31:14]. - 20 bit, DATA[19:0] = data[31:12]. - 24 bit, DATA[23:0] = data[31:8]. - 32 bit, DATA[31:0] = data[31:0]. Note: Reading from an empty RX FIFO activates INTR_RX.FIFO_UNDERFLOW. [31:0] read-only RX_FIFO_RD_SILENT RX FIFO silent read 0x8C 32 read-only 0x0 0xFFFFFFFF DATA N/A [31:0] read-only INTR_RX Interrupt 0xC0 32 read-write 0x0 0x107 FIFO_TRIGGER HW sets this field to '1', when a RX trigger is generated. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a (almost) full RX FIFO (128 -RX_FIFO_STATUS.USED < 'number of enabled channels per frame'). This is referred to as an overflow event. Note: HW ensures that either all or none of the frame's channels are received. In a RX FIFO overflow situation, HW discards received PCM data values. [1:1] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an empty RX FIFO (RX_FIFO_STATUS.USED is '0'). [2:2] read-write IF_OVERFLOW HW sets this field to '1', when PCM samples are generated too fast by the interface logic (interface overflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface overflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_RX.IF_OVERFLOW does not resolve the interface underflow). Note: This functionality is intended for debug purposes. [8:8] read-write INTR_RX_SET Interrupt set 0xC4 32 read-write 0x0 0x107 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [1:1] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [2:2] read-write IF_OVERFLOW Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect). [8:8] read-write INTR_RX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x107 FIFO_TRIGGER Mask for corresponding field in INTR_RX register. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR_RX register. [1:1] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR_RX register. [2:2] read-write IF_OVERFLOW Mask for corresponding field in INTR_RX register. [8:8] read-write INTR_RX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x107 FIFO_TRIGGER Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [1:1] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [2:2] read-only IF_OVERFLOW Logical AND of corresponding INTR_RX and INTR_RX_MASK fields. [8:8] read-only SG0 SG SG 0x40820000 0 65536 registers 5 256 SG_STRUCT[%s] Sound generator structure 0x00008000 CTL Source control 0x0 32 read-write 0x0 0x80040001 FORMAT Output format: '0': Separate. The 'sg_ampl_out' (amplitude signal) and 'sg_tone_out' (tone signal) output signals are driven seperately. '1': Combined. The 'sg_tone_out' output signal is the logical AND of the amplitude signal and tone signal. [0:0] read-write SEPARATE N/A 0 COMBINED N/A 1 ACTIVE Activate functionality: '0': Transmitter off. The UNDERFLOW interrupt cause will not be activated (provided SW never set this bit). '1': Transmitter on. The UNDERFLOW interrupt may be activated (when an underflow event occurs). Note: This functionality is intended for startup purposes. Typically, SW sets ACTIVE to '1' after the segment structure and the buffered segment structure are written with valid information. Note: SW clearing ACTIVE to '0' (after setting ACTIVE to '1') is not intended usage model and it has no effect on HW functionality. [18:18] read-write ENABLED Source enable: '0': Disabled. All non-retained MMIO registers (e.g. TIME_CTL, ..., INTR_TX register) have their fields reset to their default value. '1': Enabled. [31:31] read-write IF_CTL Interface control 0x10 32 read-write 0x707 0x7FF CLOCK_DIV Interface clock divider (legal range [0, 255]). The PWM interface clock clk_pwm is defined as clk_if / (CLOCK_DIV + 1). '0': clk_pwm frequency is clk_if frequency (1 clk_pwm cycle consists of 1 clk_if cycles). '1': clk_pwm frequency is 1/2 clk_if frequency (1 clk_pwm cycle consists of 2 clk_if cycles). '2': clk_pwm frequency is 1/3 clk_if frequency. ... '255': clk_pwm frequency is 1/256 clk_if frequency. [7:0] read-write CLOCK_SEL Interface clock clk_if selection: '0': SRSS clock clk_if_srss[0]. '1': SRSS clock clk_if_srss[1]. '2': SRSS clock clk_if_srss[2]. '3': SRSS clock clk_if_srss[3]. '4': Master interface clock 'sg_mck_in'. '5'-'7': undefined. Note: the application is always required to program this field to a value different from the default. [10:8] read-write SEL_SRSS_CLOCK0 N/A 0 SEL_SRSS_CLOCK1 N/A 1 SEL_SRSS_CLOCK2 N/A 2 SEL_SRSS_CLOCK3 N/A 3 SEL_SG_MCK_IN N/A 4 TIME_CTL Time control 0x20 32 read-write 0x0 0xFF00FF PERIOD8 Time period in tone periods: a single time period is (PERIOD + 1) tone periods. A tone period is considered a time cycle. HW updates the AMPL_CTL.HIGH value after completion of a time period. [7:0] read-write NR Segment in time periods: a single segment is (NR+1) timer periods. HW activates the 'completion' event on completion of a segment descriptor (in registers STEP_CTL, AMPL_CTL, TONE_CTL and TIME_CTL). [23:16] read-write TONE_CTL Tone control 0x24 32 read-write 0x0 0xFF00FF PERIOD8 Tone period in amplitude periods: a single tone period is 2 * (PERIOD + 1) amplitude periods. A ampolitude period is considered a tone cycle. [7:0] read-write HIGH8 Specifies the high/'1' time of the generated (right-aligned) tone PWM signal: the 'sg_tone_out' signal is '1' for HIGH+1 PWM periods. Clipping is applied if HIGH exceeds its legal range of [0, PERIOD] (the high/'1' time of the period is up to 50 percent) Note: To generate a 50/50 percent duty cycle, HIGH should equal PERIOD. [23:16] read-write AMPL_CTL Amplitude control 0x28 32 read-write 0x0 0xFFFFFFFF PERIOD16 Amplitude period in interface clock 'clk_pwm' cycles: a single amplitude period is PERIOD+1 'clk_pwm' cycles. [15:0] read-write HIGH16 Specifies the high/'1' of the generated (left-aligned) amplitude PWM waveform: the 'sg_ampl_out' output signal is '1' for HIGH+1 interface clock 'clk_pwm' cycles. The legal range is [0, PERIOD]. [31:16] read-write STEP_CTL Step control 0x2C 32 read-write 0x0 0x8000FFFF STEP Specifies the amplitude step size of the generated PWM waveform. The value is a two-complements signed number with a legal range of [-32768, 32767]. The value is added to HIGH after completion of a time period. Clipping is applied if HIGH exceeds its legal range of [0, AMPL_CTL.PERIOD]. [15:0] read-write VALID Specifies validity/availability of the segment structure (TIME_CTL, NOTE_CTL, AMPL_CTL and STEP_CTL): '0': Invalid. '1': Valid. [31:31] read-write TIME_CTL_BUFF Buffered time control 0x30 32 read-write 0x0 0xFF00FF PERIOD8 See TIME_CTL. [7:0] read-write NR See TIME_CTL. [23:16] read-write TONE_CTL_BUFF Buffered tone control 0x34 32 read-write 0x0 0xFF00FF PERIOD8 See TONE_CTL. [7:0] read-write HIGH8 See TONE_CTL. [23:16] read-write AMPL_CTL_BUFF Buffered amplitude control 0x38 32 read-write 0x0 0xFFFFFFFF PERIOD16 See AMPL_CTL. [15:0] read-write HIGH16 See AMPL_CTL. [31:16] read-write STEP_CTL_BUFF Buffered step control 0x3C 32 read-write 0x0 0x8000FFFF STEP See STEP_CTL. [15:0] read-write VALID Specifies validity of the buffered segment structure: '0': Invalid. '1': Valid. HW clears this field to '0' on a completion event. Typically, SW sets this field to '1' when a new buffered segment structure is written. An underflow event is generated when STEP_CTL_BUFF.VALID is '0' on a completion event. [31:31] read-write INTR_TX Interrupt 0xC0 32 read-write 0x0 0x105 COMPLETE HW sets this field to '1', on a completion event (completion of a segment descriptor). [0:0] read-write UNDERFLOW HW sets this field to '1', on a completion event when STEP_CTL_BUFF.VALID is '0'; i.e. a new segment structure is NOT valid/available. [2:2] read-write IF_UNDERFLOW HW sets this field to '1', when (amplitude, tone) sample pairs are not generated in time for the interface logic (interface underflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface underflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_TX.IF_UNDERFLOW does not resolve the interface underflow). The interface drives the 'sg_ampl_out' and 'sg_tone_out' output signals to '0'. Note: This functionality is intended for debug purposes. [8:8] read-write INTR_TX_SET Interrupt set 0xC4 32 read-write 0x0 0x105 COMPLETE Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [0:0] read-write UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [2:2] read-write IF_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [8:8] read-write INTR_TX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x105 COMPLETE Mask for corresponding field in INTR_TX register. [0:0] read-write UNDERFLOW Mask for corresponding field in INTR_TX register. [2:2] read-write IF_UNDERFLOW Mask for corresponding field in INTR_TX register. [8:8] read-write INTR_TX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x105 COMPLETE Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [0:0] read-only UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [2:2] read-only IF_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [8:8] read-only PWM0 PWM PWM 0x40830000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0xFF ACTIVE Activate functionality (1 bit for each channel): '0': Transmitter off. The FIFO_UNDERFLOW interrupt cause will not be activated. '1': Transmitter on. The FIFO_UNDERFLOW interrupt may be activated (when an underflow event occurs). Note: Setting this bit is intended for startup purposes. Note: Clearing this bit is intended to return the data lines at '0' prior to disabling the interface. [7:0] read-write CTL_CLR Control clear 0x4 32 read-write 0x0 0xFF ACTIVE Activate functionality: '0': No effect. '1': Bit is cleared to '0'. [7:0] read-write CTL_SET Control set 0x8 32 read-write 0x0 0xFF ACTIVE Activate functionality: '0': No effect. '1': Bit is set to '1'. [7:0] read-write 2 256 TX[%s] PWM structure 0x00008000 CTL Control 0x0 32 read-write 0x0 0x8000000F WORD_SIZE PCM word size: '0': 8 bit. '1': 10 bit. '2': 12 bit. '3': 14 bit. '4': 16 bit. '5': 18 bit. '6': 20 bit. '7': 24 bit. '8': 32 bit. '9'-'15': Undefined. [3:0] read-write SIZE_8 N/A 0 SIZE_10 N/A 1 SIZE_12 N/A 2 SIZE_14 N/A 3 SIZE_16 N/A 4 SIZE_18 N/A 5 SIZE_20 N/A 6 SIZE_24 N/A 7 SIZE_32 N/A 8 ENABLED Transmitter enable: '0': Disabled. All non-retained MMIO registers (e.g. the TX_FIFO_STATUS and INTR_TX registers) have their fields reset to their default value. The line output signals have a default value of '0' (before applying LINE_POLARITY). '1': Enabled. Note: when all transmitters are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). Note: To return the data lines at '0' prior to disable the interface software can clear the ACTIVE bit prior to clearing the ENABLED field. [31:31] read-write IF_CTL Interface control 0x10 32 read-write 0x707 0xF7FF CLOCK_DIV Interface clock divider (legal range [0, 255]). The PWM interface clock clk_pwm is defined as clk_if / (CLOCK_DIV + 1). '0': clk_pwm frequency is clk_if frequency (1 clk_pwm cycle consists of 1 clk_if cycles). '1': clk_pwm frequency is 1/2 clk_if frequency (1 clk_pwm cycle consists of 2 clk_if cycles). '2': clk_pwm frequency is 1/3 clk_if frequency. ... '255': clk_pwm frequency is 1/256 clk_if frequency. [7:0] read-write CLOCK_SEL Interface clock clk_if selection: '0': SRSS clock clk_if_srss[0]. '1': SRSS clock clk_if_srss[1]. '2': SRSS clock clk_if_srss[2]. '3': SRSS clock clk_if_srss[3]. '4': Master interface clock 'pwm_mck_in'. '5'-'7': undefined. Note: the application is always required to program this field to a value different from the default. [10:8] read-write SEL_SRSS_CLOCK0 N/A 0 SEL_SRSS_CLOCK1 N/A 1 SEL_SRSS_CLOCK2 N/A 2 SEL_SRSS_CLOCK3 N/A 3 SEL_PWM_MCK_IN N/A 4 LINE_POLARITY Line polarity (one bit for each PWM output signal): '0': Line output signal is used 'as is'. '1': Line output signal inverted. LINE_POLARITY[0]: 'line1_p_out' output signal. LINE_POLARITY[1]: 'line1_n_out' output signal. LINE_POLARITY[2]: 'line2_p_out' output signal. LINE_POLARITY[3]: 'line2_n_out' output signal. Note: the 'line2_p_out'/'line2_n_out' output signals are not used in 'E bridge' format. [15:12] read-write DOUBLE_CTL Double control 0x14 32 read-write 0x0 0x80000001 MODE Doubler mode (only applicable when ENABLED is '1'): '0': Repetition. An additional sample is created by repeating each TX FIFO data sample. '1': Averaging. An additional sample is calculated by averaging two consecutive TX FIFO data samples. [0:0] read-write REPETITION N/A 0 AVERAGING N/A 1 ENABLED Doubler enable: '0': Disabled. doubler_pcm[23:0] = pcm_data[23:0]. '1': Enabled. An 'intermediate' sample is generated through either repetition or averaging (as specified by MODE). This effectively doubles the sample frequency Fs and effectively halves the dynamic PWM sample range (at the same PWM interface clock frequency). [31:31] read-write GAIN_CTL Gain control 0x18 32 read-write 0x73 0x7F CODE Gain code in the range [0, 127]. Each gain code increment represents 1 dB. Gain code value '0' represents digital mute. Gain code '127' represents a maximum amplification of 12 dB. The gain code is used to derive a multipler value (in the range [0, 8191]) and shift value (in the range [11, 26]). '0': digital mute. Multiplier value is '0' and 'shift' is '26'. '1': -114 dB. Multiplier value is '134' and 'shift' is '26'. '2': -113 dB. Multiplier value is '150' and 'shift' is '26'. '3': -112 dB. Multiplier value is '169' and 'shift' is '26'. ... '115': 0 dB. Multiplier value is '4096' and 'shift' is '12'. ... '121': 6 dB. Multiplier value is '8173' and 'shift' is '12'. ... '127': 12 dB. Multiplier value is '8153' and 'shift' is '11'. gc_pcm[15:0] = CLIP16 ((multiplier[12:0]*doubler_pcm[23:0] + (1 << (SCALE - 1)) >> SCALE, with: SCALE = shift + PWM_CTL0.SCALE[3:0]. Note that gain control includes scaling as specified by PWM_CTL0.SCALE[3:0]. [6:0] read-write PWM_CTL0 PWM control 0 0x20 32 read-write 0x80000 0xF0003 FORMAT PWM format: '0': 'E-bridge' format. pcm[16:0] = gc_pcm[15:0] + PWM_CTL2.OFFSET. Output signals 'line1_p_out'/'line1_n_out' are used. '1': 'H-bridge' format. pcm[16:0] = Abs (gc_pcm[15:0]) and sign = gc_pcm[15] (PWM_CTL2.OFFSET is not used). Output signals 'line1_p_out'/'line1_n_out' (when sign is positive/'0') and 'line2_p_out'/'line2_n_out' (when sign is negative/'1') are used. '2': Undefined. '3': Undefined. [1:0] read-write E_BRIDGE N/A 0 H_BRIDGE N/A 1 SCALE Scaling of gain corrected PCM sample. See GAIN_CTL.CODE (scaling is performed as part of gain correction). [19:16] read-write SCALE_0 N/A 0 SCALE_1 N/A 1 SCALE_15 N/A 15 PWM_CTL1 PWM control 1 0x24 32 read-write 0xFFFF0000 0xFFFFFFFF MIN Minimum PWM clip value in the range [0, 65535]. Note: This field is typically not used for the H-bridge format (field value should be set to '0'). [15:0] read-write MAX Maximum PWM clip value in the range [0, 65535]. pwm[15:0] = (pcm[16:0] > MAX) ? MAX : (pcm[16:0] < MIN) ? MIN : pcm[15:0] Note: The MIN and MAX values are typically in the range [0, PWM_CTL2.PERIOD]. [31:16] read-write PWM_CTL2 PWM control 2 0x28 32 read-write 0x8000FFFF 0xFFFFFFFF PERIOD Period in PWM interface clock cycles (minus 1). [15:0] read-write OFFSET Offset in the range [0, 0xffff]. Note: This field is only used in 'E-bridge' format. Typically, the offset is half of the PWM period: OFFSET = (PERIOD +1) >> 1. [31:16] read-write PWM_CTL3 PWM control 3 0x2C 32 read-write 0x0 0xFFFF DT Dead time in PWM interface clock cycles. Dead time is implemented by 'delaying' the rising edge of all PWM output signals (before applying LINE_POLARITY). Dead time is used to prevent 'shoot through' (direct connection between power supply and ground). [15:0] read-write TX_FIFO_CTL TX FIFO control 0x80 32 read-write 0x0 0x3003F TRIGGER_LEVEL Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated: - INTR_TX.FIFO_TRIGGER = (# FIFO entries < TRIGGER_LEVEL) [5:0] read-write EMPTY N/A 0 USED_1 N/A 1 USED_63 N/A 63 MUTE Mute functionality: '0': HW uses TX FIFO data. '1': HW uses a constant PCM data value of '0'. Mute does advance the FIFO read pointer. [16:16] read-write FREEZE Freeze functionality: '0': HW reads from the TX FIFO and advances the FIFO read pointer. '1': HW repeats the previous TX FIFO sample. Freeze does NOT advance the FIFO read pointer. Note: This functionality is intended for debugging purposes. Note: This functionality can also be controlled by the 'tr_dbg_freeze' input signal. [17:17] read-write TX_FIFO_STATUS TX FIFO status 0x84 32 read-only 0x0 0x3F3F007F USED Number of used/occupied entries in the TX FIFO. The field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full. [6:0] read-only RD_PTR TX FIFO read pointer: FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [21:16] read-only WR_PTR TX FIFO write pointer: FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [29:24] read-only TX_FIFO_WR TX FIFO write 0x88 32 write-only 0x0 0xFFFFFFFF DATA Data (PCM sample) written to the TX FIFO. Writing adds the data to the TX FIFO; i.e. behavior is similar to that of a PUSH operation (TX_FIFO_STATUS.WR_PTR is incremented and TX_FIFO_STATUS.USED is incremented). The write data (DATA) should be right aligned when it is written to the FIFO entry (data[23:0]): - 8 bit, pcm_data[23:0] = DATA[7:0] << 16. - 10 bit, pcm_data[23:0] = DATA[9:0] << 14. - 12 bit, pcm_data[23:0] = DATA[11:0] << 12. - 14 bit, pcm_data[23:0] = DATA[13:0] << 10. - 16 bit, pcm_data[23:0] = DATA[15:0] << 8. - 18 bit, pcm_data[23:0] = DATA[17:0] << 6. - 20 bit, pcm_data[23:0] = DATA[19:0] << 4. - 24 bit, pcm_data[23:0] = DATA[23:0]. - 32 bit, pcm_data[23:0] = DATA[31:8]. Note: Writing to a full TX FIFO activates INTR.TX_FIFO_OVERFLOW. [31:0] write-only INTR_TX Interrupt 0xC0 32 read-write 0x0 0x107 FIFO_TRIGGER HW sets this field to '1', when a TX trigger is generated. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a full TX FIFO (TX_FIFO_STATUS.USED is '64'). This is referred to as an underflow event. [1:1] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an empty TX FIFO (TX_FIFO_STATUS.USED is '0'). Note: in case of a TX FIFO underflow event, the logic 'replays' the previous PCM value. [2:2] read-write IF_UNDERFLOW HW sets this field to '1', when PWM samples are not generated in time for the interface logic (interface underflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface underflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_TX.IF_UNDERFLOW does not resolve the interface underflow). The interface drives the 'line1_p' and 'line2_p' output signals to '0' and drives the 'line1_n' and 'line2_n' output signals to '0' also. Note: This functionality is intended for debug purposes. [8:8] read-write INTR_TX_SET Interrupt set 0xC4 32 read-write 0x0 0x107 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [1:1] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [2:2] read-write IF_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [8:8] read-write INTR_TX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x107 FIFO_TRIGGER Mask for corresponding field in INTR_TX register. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR_TX register. [1:1] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR_TX register. [2:2] read-write IF_UNDERFLOW Mask for corresponding field in INTR_TX register. [8:8] read-write INTR_TX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x107 FIFO_TRIGGER Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [1:1] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [2:2] read-only IF_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [8:8] read-only DAC0 DAC DAC 0x40840000 0 256 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED DAC IP enable: '0': Disabled. If DAC is disabled, all non-retained MMIO registers (e.g. the TX_FIFO_STATUS and INTR_TX registers) have their fields reset to their default value. SRAM content is not retained. Analog DAC output is disabled and powered down irrespective of DAC_EN. '1': Enabled. [31:31] read-write IF_CTL Interface Control 0x4 32 read-write 0x4020007 0xCF0307FF CLOCK_DIV Interface clock divider (legal range [0, 255]). The DAC system clock clk_dac is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ([1,3,5,...255]) or 0 (divide by 1), to ensure a 50/50 percent duty cycle clock output. '0': clk_dac frequency is clk_if frequency (1 clk_dac cycle consists of 1 clk_if cycles). '1': clk_dac frequency is 1/2 clk_if frequency (1 clk_dac cycle consists of 2 clk_if cycles). '2': clk_dac frequency is 1/3 clk_if frequency. Note: results in a non 50/50 percent duty cycle. ... '255': clk_dac frequency is 1/256 clk_if frequency. Note: This field can only be changed when CLOCK_SEL= clk_if off. [7:0] read-write CLOCK_SEL Interface clock clk_if selection: '0': SRSS clock clk_if_srss. '1'-'3': Clock 'clk_if' is off. '4': Master interface clock 'dac_mck'. '5'-'7': Clock 'clk_if' is off. [10:8] read-write SEL_SRSS_CLOCK N/A 0 SEL_CLK_IF_OFF N/A 1 SEL_DAC_MCK N/A 4 FS_SEL N/A [17:16] read-write RSVD N/A 0 256FS_128OSR N/A 1 256FS_256OSR N/A 2 512FS_512OSR N/A 3 LDATA_POLARITY Left Data polarity. '0' - No change in Left data. '1' - Invert (2's complement) Left data. The name of this field corresponds to the default setting. The function of this field always inverts bits 31:16 before the data is written into the FIFO. LDATA_SEL does not affect which bits are inverted. [24:24] read-write RDATA_POLARITY Right Data polarity. '0' - No change in Right data. '1' - Invert (2's complement) Right data. The name of this field corresponds to the default setting. The function of this field always inverts bits 15:0 before the data is written into the FIFO. RDATA_SEL does not affect which bits are inverted. [25:25] read-write LDATA_SEL Left Data Selection. Specifies selection of the channel's 16-bit PCM data from the source FIFO data[31:0]: '0': data[15:0]. '1': data[31:16] (default setting). Note: LDATA_SEL and RDATA_SEL are used to specify mono and stereo audio formats. [26:26] read-write DATA_LOW N/A 0 DATA_HIGH N/A 1 RDATA_SEL Right Data Selection. Specifies selection of the channel's 16-bit PCM data from the source FIFO data[31:0]: '0': data[15:0] (default setting). '1': data[31:16]. [27:27] read-write DATA_LOW N/A 0 DATA_HIGH N/A 1 SW_OVERRIDE_FAST_RAMP_EN SW Override Fast Ramp enable. '0' - No SW override for fast ramp enable. HW controls the fast ramp enable. '1' - SW override for fast ramp enable. HW control is disabled. SW set the Fast Ramp enable before DAC_EN is set to 1. When SW override is used, 1. SW needs to disable the fast ramp enable by clearing this bit after the fast ramp up circuit is complete i.e. 10ms after setting DAC_EN. 2. After that, SW needs to ensure the DAC's stabilization time is met (i.e. 60ms after disabling the fast ramp circuit) before starting transactions to DAC. [30:30] read-write DAC_EN DAC Analog Enable. '0' - DAC Opamp and DAC COM analog bias generator is disabled. '1' - DAC Opamp and DAC COM analog bias generator is enabled. Note that after enabling the DAC Analog circuit, it requires 70ms to be stable. The same ramp up time applies when waking up from DeepSleep. DACEN is only valid when ENABLED=1. Note: This bit does not 'silent' the AudioDAC. CTL.ENABLED=0 is required to 'slient' the AudioDAC [31:31] read-write COUNT Count 0x8 32 read-write 0x3C0A1F40 0xFFFFFFFF COUNT_1MS Count for 1ms with clk_timer. Specifies the number of counts to achieve 1ms based on clk_timer (1 count represent 1 clk_timer period). This field needs to be programmed before IF_CTL.DAC_EN=1. [15:0] read-write FAST_RAMP_COUNT_IN_MS Fast Ramp count in ms. Specifies the number of counts in ms for the fast ramp circuit. HW will enable the fast ramp circuit when counting is in progress. HW will disable the fast ramp circuit when counting is complete. E.g. FAST_RAMP_COUNT_IN_MS=10 means that HW enables the fast ramp circuit when it starts counting and disable the fast ramp circuit after 10ms. HW sets STATUS.FAST_RAMP_DONE=1 after counting is complete. [23:16] read-write COMP_RAMP_COUNT_IN_MS Complete Ramp count in ms. Specifies the number of counts in ms for the complete ramp circuit. The count takes place after the fast ramp count is complete. E.g. COMP_RAMP_COUNT_IN_MS=60 means that HW starts counting after disabling fast ramp circuit and stops counting after 60ms. HW sets STATUS.COMP_RAMP_DONE=1 after counting is complete. [31:24] read-write STATUS Status 0x10 32 read-only 0x0 0x30001 DAC_BUSY DAC Busy. '0' - DAC is idle. '1' - Indicates that FS_SEL is in the middle of synchronizing to clk_if domain. SW must not change FS_SEL until DAC_BUSY=0. [0:0] read-only FAST_RAMP_DONE Fast Ramp Done. '0' - Fast ramping is not complete. '1' - Fast ramp circuit is complete. The fast ramp circuit is deemed complete based on time specified in FAST_RAMP_COUNT_IN_MS. Timer starts counting if FAST_RAMP_DONE=0 and IF_CTL.DAC_EN=1. [16:16] read-only COMP_RAMP_DONE Complete Ramp Done. '0' - Complete Ramp is not complete. '1' - Complete Ramp is complete. The ramping of the circuit is deemed complete based on time specified in COMP_RAMP_COUNT_IN_MS. Timer starts counting if FAST_RAMP_DONE=1 and COMP_RAMP_DONE=0 and IF_CTL.DAC_EN=1 This bit transition from '0'->'1' will cause HW to set TX_INTR.RAMP_COMPLETE=1. SW clearing TX_INTR.RAMP_COMPLETE=0 will not have effect of this status bit. [17:17] read-only TX_FIFO_CTL TX FIFO control 0x80 32 read-write 0x0 0x7003F TRIGGER_LEVEL Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated: - INTR_TX.FIFO_TRIGGER = (# FIFO entries < TRIGGER_LEVEL) Note: Setting TRIGGER_LEVEL=0 means trigger will not be set. [5:0] read-write MUTE Mute functionality: '0': HW uses TX FIFO data. '1'- HW uses a constant PCM data value of '0'. Mute does advance the FIFO read pointer. [16:16] read-write FREEZE Freeze functionality: '0': HW uses TX FIFO data and advances the FIFO read pointer. '1': HW uses a constant PCM data value of '0' (the FIFO data is not used). HW reads from the TX FIFO have no effect: freeze will not advance the FIFO read pointer. Note: This functionality is intended for debugging purposes. [17:17] read-write ACTIVE Activate functionality: '0': The FIFO_UNDERFLOW interrupt cause will not be activated. HW uses a constant PCM data value of '0' if ACTIVE=0 prior to FIFO content is available. Otherwise, PCM data is transmitted from the TX FIFO when finishing an audio packet stream. '1': The FIFO_UNDERFLOW interrupt may be activated (when an underflow event occurs). PCM data is transmitted from the TX FIFO. Note: This functionality is intended for startup for an audio packet stream when ACTIVE=0->1. PCM data is transmitted from the TX FIFO throughout ACTIVE=1. An audio packet stream ends when FIFO is empty and ACTIVE=0. HW uses a constant PCM data value of '0' if TX FIFO is empty regardless of ACTIVE=0/1. [18:18] read-write TX_FIFO_STATUS TX FIFO status 0x84 32 read-only 0x0 0x3F3F007F USED Number of used/occupied entries in the TX FIFO. The field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full. [6:0] read-only RD_PTR TX FIFO read pointer: FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [21:16] read-only WR_PTR TX FIFO write pointer: FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [29:24] read-only TX_FIFO_WR TX FIFO write 0x88 32 write-only 0x0 0xFFFFFFFF DATA Data written to the TX FIFO. Writing adds the data to the TX FIFO; i.e. behavior is similar to that of a PUSH operation (TX_FIFO_STATUS.WR_PTR is incremented and TX_FIFO_STATUS.USED is incremented). -16-bit left PCM data = DATA[31:16] -16-bit right PCM data = DATA[15:0] Note: Writing to a full TX FIFO activates INTR.TX_FIFO_OVERFLOW. [31:0] write-only INTR_TX Interrupt 0xC0 32 read-write 0x0 0x30007 FIFO_TRIGGER HW sets this field to '1', when a TX trigger is generated. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a full TX FIFO (TX_FIFO_STATUS.USED is '64'). [1:1] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an empty TX FIFO. HW tracks underflow after TX FIFO is being written to and TX_FIFO_CTL.ACTIVE==1. [2:2] read-write FAST_RAMP_COMPLETE HW sets this field to '1', when fast ramping of the DAC circuit is complete. [16:16] read-write RAMP_COMPLETE HW sets this field to '1', when ramping of the DAC circuit is complete. [17:17] read-write INTR_TX_SET Interrupt set 0xC4 32 read-write 0x0 0x30007 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [1:1] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [2:2] read-write FAST_RAMP_COMPLETE Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [16:16] read-write RAMP_COMPLETE Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [17:17] read-write INTR_TX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x30007 FIFO_TRIGGER Mask for corresponding field in INTR_TX register. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR_TX register. [1:1] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR_TX register. [2:2] read-write FAST_RAMP_COMPLETE Mask for corresponding field in INTR_TX register. [16:16] read-write RAMP_COMPLETE Mask for corresponding field in INTR_TX register. [17:17] read-write INTR_TX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x30007 FIFO_TRIGGER Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [1:1] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [2:2] read-only FAST_RAMP_COMPLETE Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [16:16] read-only RAMP_COMPLETE Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [17:17] read-only MIXER0 MIXER MIXER 0x40880000 0 65536 registers 5 256 MIXER_SRC_STRUCT[%s] Mixer source structure 0x00008000 SRC_CTL Source control 0x0 32 read-write 0x41000 0x800F7000 FS_RATIO Sample frequency upscale ratio: '0': 0.5 (downsampling by 2x). '1': 1 (no resampling). '2': 2 (upsampling by 2x). '3': 3. '4': 4. '5': 6. '6': 8. '7': 12 (upsampling by 12x). [14:12] read-write DOWN_2 N/A 0 SAME N/A 1 UP_2 N/A 2 UP_3 N/A 3 UP_4 N/A 4 UP_6 N/A 5 UP_8 N/A 6 UP_12 N/A 7 CH0_SEL Channel selection. Specifies selection of the channel's 16-bit PCM data from the source FIFO data[31:0]: '0': data[15:0] (default setting). '1': data[31:16]. '2': Constant PCM data value of '0'; i.e. source FIFO data is not used. '3': undefined. Note: CH0_SEL and CH1_SEL are used to specify mono and stereo audio formats. [17:16] read-write DATA_LOW N/A 0 DATA_HIGH N/A 1 CONSTANT_0 N/A 2 CH1_SEL Channel selection. Specifies selection of the channel's 16-bit PCM data from the source FIFO data[31:0]: '0': data[15:0]. '1': data[31:16] (default setting). '2': Constant PCM data value of '0'; i.e. source FIFO data is not used. '3': undefined. [19:18] read-write DATA_LOW N/A 0 DATA_HIGH N/A 1 CONSTANT_0 N/A 2 ENABLED Source enable: '0': Disabled. All non-retained MMIO registers (e.g. the SRC_STATUS, SRC_FIFO_STATUS and INTR_SRC registers) have their fields reset to their default value. '1': Enabled. Note: when all sources, destination and transmitter are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). [31:31] read-write SRC_STATUS Source status 0x4 32 read-only 0x0 0xF PHASE Current FIR phase value. A upscale ratio of 'n' uses a n polyphase FIR filter. The phases are numbered [0, n-1]. [3:0] read-only PHASE_0 N/A 0 PHASE_1 N/A 1 PHASE_11 N/A 11 SRC_FADE_CTL Source fade control 0x14 32 read-write 0x73 0x7F CODE Gain code in the range [0, 115]. See SRC_GAIN_CTL.CODE[]. Note: HW modifies this field during 'fade in' and 'fade out'. For 'fade in' HW will gradually increment the value until it reaches '115'. For 'fade out' HW will gradually decrement the value until it reaches '0'. Note: SW is typically required to reprogram the CODE field in between successive 'fade in' operations or in between successive 'fade out' operations. [6:0] read-write SRC_FADE_STATUS Source fade status 0x18 32 read-only 0x0 0x0 PACE Current fading pace counter value. SRC_FADE_CTL.PACE value of 'n' reuses a specific fade value 'n+1' times. The reuses are numbered [0, n]. [25:16] read-only SRC_FADE_CMD Source fade command 0x1C 32 read-write 0x1FF0000 0x3FF0103 FADE_IN 'Fade in' functionality: '0': Disabled. '1': Enabled: Increments CODE gradually to '115'. Typically, SW sets this field to '1' to start 'fade in' functionality. HW clears this field to '0' to indicate that 'fade in' has completed; i.e. 0 dB amplification is achieved. [0:0] read-write FADE_OUT 'Fade out' functionality: '0': Disabled. '1': Enabled: Changes CODE gradually to '0' (digital mute). Typically, SW sets this field to '1' to start 'fade out' functionality. HW clears this field to '0' to indicate that 'fade out' has completed; i.e. 'muting' is achieved. Note: FADE_IN and FADE_OUT should be used mutually exclusively. However, if 'fade in' is desired while 'fading out', SW can set FADE_IN to '1' and clear FADE_OUT to '0'. 'Fade in' will commence from the current CODE value. Similarly, if 'fade out' is desired while 'fading in', SW can set FADE_OUT to '1' and clear FADE_IN to '0'. 'Fade out' will commence from the current CODE value. [1:1] read-write AUTO_DEACTIVATE Specifies behavior when 'fade out' has completed: '0': Source does NOT get deactivated. '1': Source gets deactivated; i.e. HW clears SRC_FIFO_CTL.ACTIVE to '0'. [8:8] read-write PACE Specifies the pace/speed of 'fade in' and 'fade out': '0': The same CODE value is used (0+1) times. '1': The same CODE value is used (1+1) times. ... '1023': The same CODE value is used (1023+1) times. A fade in from 'mute' to 0 dB takes 1024*116 = 118,784 PCM samples. At a PCM sample frequency Fs of 48 kHz, this translates into 118,784/48,000 = 2.474 seconds. [25:16] read-write SRC_GAIN_CTL Source gain control 0x20 32 read-write 0x73 0x7F CODE Gain code in the range [0, 127]. Each gain code increment represents 1 dB. Gain code value '0' represents digital mute. Gain code '127' represents a maximum amplification of 12 dB. The gain code is used to derive a multipler value (in the range [0, 8191]) and shift value (in the range [11, 26]). '0': digital mute. Multiplier value is '0' and 'shift' is '26'. '1': -114 dB. Multiplier value is '134' and 'shift' is '26'. '2': -113 dB. Multiplier value is '150' and 'shift' is '26'. '3': -112 dB. Multiplier value is '169' and 'shift' is '26'. ... '115': 0 dB. Multiplier value is '4096' and 'shift' is '12'. Note that (4096 * x) >> 12 = x; i.e. the PCM value is unaffected. ... '121': 6 dB. Multiplier value is '8173' and 'shift' is '12'. ... '127': 12 dB. Multiplier value is '8153' and 'shift' is '11'. gc_pcm[15:0] = CLIP16 ((multiplier[12:0]*fir_scaled_pcm[15:0]) >> shift) [6:0] read-write SRC_FIFO_CTL Source FIFO control 0x80 32 read-write 0x0 0x5007F TRIGGER_LEVEL Trigger level. When the source FIFO has less entries than the number of this field, a transmitter trigger event is generated: - INTR_SRC.FIFO_TRIGGER = (# FIFO entries < TRIGGER_LEVEL) [6:0] read-write MUTE Mute functionality: '0': Mixer source unmuted; i.e. source FIFO data. '1': Mixer source muted; i.e. use PCM data value of '0'. Mute does advance the FIFO read pointer. Note: HW ensures that mute functionality synchronizes on the first channel of a frame to ensure that either all or none of the frame's channels are muted. [16:16] read-write ACTIVE Activate functionality: '0': Mixer source inactive; i.e. use PCM data value of '0'. '1': Mixer source active; i.e. use FIFO PCM data, when PCM data are not available: wait. HW clears this field to '0' when fading out has completed and SRC_FADE_CMD.AUTO_DEACTIVATE is '1'. Note: This functionality is intended for startup purposes. To start the mixer, SW should first activate the sources(s) and second activate the destination. To stop the mixer, SW should first deactivate the destination and second deactivate the source(s). [18:18] read-write SRC_FIFO_STATUS Source FIFO status 0x84 32 read-only 0x0 0x7F7F00FF USED Number of used/occupied entries in the source FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full. Note: A source FIFO has double the capacity of the destination FIFO. This is because the sample frequency conversion requires 63 PCM input samples to produce a PCM output sample (63-taps FIR filter). [7:0] read-only RD_PTR Source FIFO read pointer: Source FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [22:16] read-only WR_PTR Source FIFO write pointer: Source FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [30:24] read-only SRC_FIFO_WR Source FIFO write 0x88 32 write-only 0x0 0xFFFFFFFF DATA Data (PCM sample pair of two 16-bit samples) written to the top source FIFO entry (data[31:0] = DATA[31:0]). Typically, DATA[15:0] is used for channel 0 and DATA[31:16] is used for channel 1. Writing adds the data to the source FIFO; i.e. behavior is similar to that of a PUSH operation (SRC_FIFO_STATUS.WR_PTR is incremented and SRC_FIFO_STATUS.USED is incremented). Note: Writing to a full source FIFO activates INTR_SRC.FIFO_OVERFLOW. [31:0] write-only INTR_SRC Interrupt 0xC0 32 read-write 0x0 0x103 FIFO_TRIGGER HW sets this field to '1', when a source trigger is generated. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a full source FIFO (SRC_FIFO_STATUS.USED is '128'). [1:1] read-write FADED_OUT HW sets this field to '1', when fade out has completed (HW changes SRC_FADE_CMD.FADE_OUT from '0' to '1'). [8:8] read-write INTR_SRC_SET Interrupt set 0xC4 32 read-write 0x0 0x103 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_SRC field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR_SRC field (a write of '0' has no effect). [1:1] read-write FADED_OUT Write this field with '1' to set corresponding INTR_SRC field (a write of '0' has no effect). [8:8] read-write INTR_SRC_MASK Interrupt mask 0xC8 32 read-write 0x0 0x103 FIFO_TRIGGER Mask for corresponding field in INTR_SRC register. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR_SRC register. [1:1] read-write FADED_OUT Mask for corresponding field in INTR_SRC register. [8:8] read-write INTR_SRC_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x103 FIFO_TRIGGER Logical AND of corresponding INTR_SRC and INTR_SRC_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR_SRC and INTR_SRC_MASK fields. [1:1] read-only FADED_OUT Logical AND of corresponding INTR_SRC and INTR_SRC_MASK fields. [8:8] read-only MIXER_DST_STRUCT Mixer destination structure 0x0000C000 DST_CTL Destination control 0x0 32 read-write 0x0 0x80000000 ENABLED Destination enable: '0': Disabled. All non-retained MMIO registers (e.g. the DST_FADE_STATUS, DST_FIFO_STATUS and INTR_DST registers) have their fields reset to their default value. '1': Enabled. Note: when all sources, destination and transmitter are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). [31:31] read-write DST_FADE_CTL Destination fade control 0x14 32 read-write 0x73 0x7F CODE Gain code in the range [0, 115]. See DST_GAIN_CTL.CODE[]. Note: HW modifies this field during 'fade in' and 'fade out'. For 'fade in' HW will gradually increment the value until it reaches '115'. For 'fade out' HW will gradually decrement the value until it reaches '0'. Note: SW is typically required to reprogram the CODE field in between successive 'fade in' operations or in between successive 'fade out' operations. [6:0] read-write DST_FADE_STATUS Destination fade status 0x18 32 read-only 0x0 0x0 PACE Current fading pace counter value. DST_FADE_CTL.PACE value of 'n' reuses a specific fade value 'n+1' times. The reuses are numbered [0, n]. [25:16] read-only DST_FADE_CMD Destination fade command 0x1C 32 read-write 0x1FF0000 0x3FF0103 FADE_IN 'Fade in' functionality: '0': Disabled. '1': Enabled: Increments CODE gradually to '115'. Typically, SW sets this field to '1' to start 'fade in' functionality. HW clears this field to '0' to indicate that 'fade in' has completed; i.e. 0 dB amplification is achieved. [0:0] read-write FADE_OUT 'Fade out' functionality: '0': Disabled. '1': Enabled: Changes CODE gradually to '0' (digital mute). Typically, SW sets this field to '1' to start 'fade out' functionality. HW clears this field to '0' to indicate that 'fade out' has completed; i.e. 'muting' is achieved. Note: FADE_IN and FADE_OUT should be used mutually exclusively. However, if 'fade in' is desired while 'fading out', SW can set FADE_IN to '1' and clear FADE_OUT to '0'. 'Fade in' will commence from the current CODE value. Similarly, if 'fade out' is desired while 'fading in', SW can set FADE_OUT to '1' and clear FADE_IN to '0'. 'Fade out' will commence from the current CODE value. [1:1] read-write AUTO_DEACTIVATE Specifies behavior when 'fade out' has completed: '0': Destination does NOT get deactivated. '1': Destination gets deactivated; i.e. HW clears DST_FIFO_CTL.ACTIVE to '0'. [8:8] read-write PACE Specifies the pace/speed of 'fade in' and 'fade out': '0': The same CODE value is used (0+1) times. '1': The same CODE value is used (1+1) times. ... '1023': The same CODE value is used (1023+1) times. A fade in from 'mute' to 0 dB takes 1024*116 = 118,784 PCM samples. At a PCM sample frequency Fs of 48 kHz, this translates into 118,784/48,000 = 2.474 seconds. [25:16] read-write DST_GAIN_CTL Destination gain control 0x20 32 read-write 0x73 0x7F CODE Gain code in the range [0, 127]. Each gain code increment represents 1 dB. Gain code value '0' represents digital mute. Gain code '127' represents a maximum amplification of 12 dB. The gain code is used to derive a multipler value (in the range [0, 8191]) and shift value (in the range [11, 26]). '0': digital mute. Multiplier value is '0' and 'shift' is '26'. '1': -114 dB. Multiplier value is '134' and 'shift' is '26'. '2': -113 dB. Multiplier value is '150' and 'shift' is '26'. '3': -112 dB. Multiplier value is '169' and 'shift' is '26'. ... '115': 0 dB. Multiplier value is '4096' and 'shift' is '12'. Note that (4096 * x) >> 12 = x; i.e. the PCM value is unaffected. ... '121': 6 dB. Multiplier value is '8173' and 'shift' is '12'. ... '127': 12 dB. Multiplier value is '8153' and 'shift' is '11'. gc_pcm[15:0] = CLIP16 ((multiplier[12:0]*fir_scaled_pcm[15:0]) >> shift) [6:0] read-write DST_FIFO_CTL Destination FIFO control 0x80 32 read-write 0x0 0x5003F TRIGGER_LEVEL Trigger level. When the destination FIFO has more entries than the number of this field, a receiver trigger event is generated: - INTR_DST.FIFO_TRIGGER = (# FIFO entries > TRIGGER_LEVEL) [5:0] read-write EMPTY N/A 0 USED_1 N/A 1 USED_63 N/A 63 MUTE Mute functionality: '0': Mixer destination unmuted; i.e. use mixed PCM data. '1': Mixer destination muted; i.e. use PCM data value of '0'. Mute does advance the FIFO write pointer. Note: HW ensures that mute functionality synchronizes on the first channel of a frame to ensure that either all or none of the frame's channels are muted. [16:16] read-write ACTIVE Activate functionality: '0': Mixer destination off; i.e. no PCM data produced. '1': Mixer destination on; i.e. PCM data produced. Note: This functionality is intended for stopping purposes. To start the mixer, SW should first activate the sources(s) and second activate the destination. To stop the mixer, SW should first deactivate the destination and second deactivate the source(s). [18:18] read-write DST_FIFO_STATUS Destination FIFO status 0x84 32 read-only 0x0 0x3F3F007F USED Number of used/occupied entries in the destination FIFO. The field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full. [6:0] read-only RD_PTR Destination FIFO read pointer: Destination FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. [21:16] read-only WR_PTR Destination FIFO write pointer: Destination FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. [29:24] read-only DST_FIFO_RD Destination FIFO read 0x88 32 read-only 0x0 0xFFFFFFFF DATA Data (PCM sample pair) read from the top destination FIFO entry (DATA[31:0] = {ch1_data[15:0], ch0_data[15:0]). Reading removes the data from the destination FIFO; i.e. behavior is similar to that of a POP operation (DST_FIFO_STATUS.RD_PTR is incremented and DST_FIFO_STATUS.USED is decremented). Note: Reading from an empty destination FIFO activates INTR_DST.FIFO_UNDERFLOW (if DST_CTL.ENABLED is '1' and TX_CTL.ENABLED is ''0'). [31:0] read-only DST_FIFO_RD_SILENT Destination FIFO silent read 0x8C 32 read-only 0x0 0xFFFFFFFF DATA N/A [31:0] read-only INTR_DST Interrupt 0xC0 32 read-write 0x0 0x105 FIFO_TRIGGER HW sets this field to '1', when a destination trigger is generated. [0:0] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an empty destination FIFO (DST_FIFO_STATUS.USED is '0'). [2:2] read-write FADED_OUT HW sets this field to '1', when fading out has completed (HW changes DST_FADE_CMD.FADE_OUT from '0' to '1'). [8:8] read-write INTR_DST_SET Interrupt set 0xC4 32 read-write 0x0 0x105 FIFO_TRIGGER Write this field with '1' to set corresponding INTR_DST field (a write of '0' has no effect). [0:0] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_DST field (a write of '0' has no effect). [2:2] read-write FADED_OUT Write this field with '1' to set corresponding INTR_DST field (a write of '0' has no effect). [8:8] read-write INTR_DST_MASK Interrupt mask 0xC8 32 read-write 0x0 0x105 FIFO_TRIGGER Mask for corresponding field in INTR_DST register. [0:0] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR_DST register. [2:2] read-write FADED_OUT Mask for corresponding field in INTR_DST register. [8:8] read-write INTR_DST_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x105 FIFO_TRIGGER Logical AND of corresponding INTR_DST and INTR_DST_MASK fields. [0:0] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR_DST and INTR_DST_MASK fields. [2:2] read-only FADED_OUT Logical AND of corresponding INTR_DST and INTR_DST_MASK fields. [8:8] read-only MIXER_TX_STRUCT Mixer TX structure 0x0000D000 TX_CTL TX control 0x0 32 read-write 0x10004 0x8001300F WORD_SIZE PCM word size: '0'-'3': Undefined. '4': 16 bit. The IP always uses 16-bit PCM words. '9'-'15': Undefined. [3:0] read-only SIZE_16 N/A 4 FORMAT Format: '0': Left-aligned delayed (I2S). '1': Left-aligned. '2': Right-aligned delayed. '3': Right-aligned. [13:12] read-write LEFT_DELAYED N/A 0 LEFT N/A 1 RIGHT_DELAYED N/A 2 RIGHT N/A 3 MS Master/slave setting: '0': Slave. - External transmitter 'mixer_tx_sck_in' and transmitter 'mixer_tx_ws_in'. '1': Master. - Interface clock 'clk_if' is used to generate transmitter 'mixer_tx_sck_out' and transmitter 'mixer_tx_ws_out'. [16:16] read-write SLAVE N/A 0 MASTER N/A 1 ENABLED Transmitter (TX) enable: '0': Disabled. All non-retained MMIO registers (e.g. the TX_FIFO_STATUS and INTR_TX registers) have their fields reset to their default value. '1': Enabled. Note: when all sources, destination and transmitter are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40). [31:31] read-write TX_IF_CTL TX interface control 0x10 32 read-write 0x1F000707 0x1F0337FF CLOCK_DIV Interface clock divider (legal range [1, 255]). The I2S interface 'i2s_tx_sck_out' output signal is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle clock. Note: Used in master configuration only. [7:0] read-write CLOCK_SEL Interface clock 'clk_if' selection: '0': SRSS clock clk_if_srss. '1'-'3': undefined. '4': Master interface clock 'mixer_tx_mck_in'. '5'-'7': undefined. Note: the application is always required to program this field to a value different from the default. [10:8] read-write SEL_SRSS_CLOCK N/A 0 SEL_MIXER_TX_MCK_IN N/A 4 SCK_POLARITY Clock polarity: '0': Clock signal is used 'as is'. '1': Clock signal is inverted. Note: Used in BOTH master and slave configurations. [12:12] read-write WS_POLARITY Word select polarity: '0': Word select signal is used 'as is'. '1': Word select signal is inverted. Note: Used in BOTH master and slave configurations. [13:13] read-write CH0_EN Channel 0 enable: '0': Disabled. The TX FIFO does not produce channel 0 words and 'mixer_tx_sd_out' is not driven. '1': Enabled. [16:16] read-write CH1_EN Channel 1 enable: '0': Disabled. The TX FIFO does not produce channel 1 words and 'mixer_tx_sd_out' is not driven. '1': Enabled. [17:17] read-write CH_SIZE Channel size: '0': 1 bit. '1': 2 bits. ... '31': 32 bits. Note: channel size must be greater or equal to the word size. [28:24] read-write SIZE_1 N/A 0 SIZE_2 N/A 1 SIZE_32 N/A 31 TX_FIFO_CTL TX FIFO control 0x80 32 read-write 0x0 0xF0000 MUTE Mute functionality: '0': HW uses destination (TX) FIFO data. '1': HW uses a constant PCM data value of '0'. Mute does advance the FIFO read pointer. Note: HW ensures that mute functionality synchronizes on the first channel of a frame to ensure that either all or none of the frame's channels are muted. [16:16] read-write FREEZE Freeze functionality: '0': HW uses destination (TX) FIFO data and advances the FIFO read pointer. '1': HW uses a constant PCM data value of '0' or the previous channel PCM data is replayed. Freeze does not advance the FIFO read pointer (the FIFO data is not used). Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time. Note: This functionality is intended for debugging purposes. [17:17] read-write ACTIVE Activate functionality: '0': Transmitter off. The FIFO_UNDERFLOW interrupt cause will not be activated. '1': Transmitter on. The FIFO_UNDERFLOW interrupt may be activated (when an underflow event occurs). Note: This functionality is intended for startup purposes. [18:18] read-write REPLAY Replay functionality (used when FREEZE is '1' or in case of a FIFO underflow event): '0': HW uses a constant PCM data value of '0'. '1': HW uses the previous PCM data value. [19:19] read-write INTR_TX Interrupt 0xC0 32 read-write 0x0 0x104 FIFO_UNDERFLOW HW sets this field to '1', when reading from an empty destination (TX) FIFO (DST_FIFO_STATUS.USED == 0). This is referred to as an underflow event. Note: HW ensures that either all or none of the frame's channels are transmitted. In a FIFO underflow situation, HW replays previous PCM data or uses a constant PCM data value of '0'. [2:2] read-write IF_UNDERFLOW HW sets this field to '1', when PCM samples are not generated in time for the interface logic (interface underflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface underflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_TX.IF_UNDERFLOW does not resolve the interface underflow). Note: This functionality is intended for debug purposes. [8:8] read-write INTR_TX_SET Interrupt set 0xC4 32 read-write 0x0 0x104 FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [2:2] read-write IF_UNDERFLOW Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect). [8:8] read-write INTR_TX_MASK Interrupt mask 0xC8 32 read-write 0x0 0x104 FIFO_UNDERFLOW Mask for corresponding field in INTR_TX register. [2:2] read-write IF_UNDERFLOW Mask for corresponding field in INTR_TX register. [8:8] read-write INTR_TX_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x104 FIFO_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [2:2] read-only IF_UNDERFLOW Logical AND of corresponding INTR_TX and INTR_TX_MASK fields. [8:8] read-only MIXER1 0x40890000 PASS0 Programmable Analog Subsystem for S40E PASS 0x40900000 0 1048576 registers 2 4096 SAR[%s] SAR ADC with Sequencer for S40E 0x00000000 CTL Analog control register. 0x0 32 read-write 0x0 0xE00007FF PWRUP_TIME Number cycles to wait to power up after IDLE_PWRDWN. Check the STATUS.PWRUP_BUSY flag to see if the delay is still in progress. The power up delay is 1 us. [7:0] read-write IDLE_PWRDWN When idle automatically power down the analog. After an automatic power down a new trigger will power up the analog, however it will take PWRUP_TIME cycles before the first acquisition can be started. Note that re-arbitration happens at that time, i.e. the trigger that caused the power up may not get handled first. [8:8] read-write MSB_STRETCH When set use 2 cycles for the Most Significant Bit (MSB) - 0: Use 1 clock cycle for MSB - 1: Use 2 clock cycles for MSB [9:9] read-write HALF_LSB When set take an extra cycle to convert the half LSB and add it to 12-bit result for Missing Code Recovery This bit should always be set to '1' - 0: disable half LSB conversion (not recommended) - 1: enable half LSB conversion [10:10] read-write SARMUX_EN Enable the SARMUX (only valid if ENABLED=1) - 0: SARMUX disabled (put analog in power down) - 1: SARMUX enabled. [29:29] read-write ADC_EN Enable the SAR ADC and SAR sequencer (only valid if ENABLED=1) - 0: SARADC and SARSEQ are disabled (put SARADC analog in power down and stop clocks), also clears all pending triggers. - 1: SAR ADC and SARSEQ are enabled. To enable ADC0 to borrow SARMUX1-3 the corresponding ADC_EN must be set to 0. [30:30] read-write ENABLED - 0: SAR IP disabled (put analog in power down and stop clocks), also clears all pending triggers. - 1: SAR IP enabled. [31:31] read-write DIAG_CTL Diagnostic Reference control register. 0x4 32 read-write 0x0 0x8000000F DIAG_SEL Select Diagnostic Reference function [3:0] read-write VREFL DiagOut = VrefL 0 VREFH_1DIV8 DiagOut = VrefH * 1/8 1 VREFH_2DIV8 DiagOut = VrefH * 2/8 2 VREFH_3DIV8 DiagOut = VrefH * 3/8 3 VREFH_4DIV8 DiagOut = VrefH * 4/8 4 VREFH_5DIV8 DiagOut = VrefH * 5/8 5 VREFH_6DIV8 DiagOut = VrefH * 6/8 6 VREFH_7DIV8 DiagOut = VrefH * 7/8 7 VREFH DiagOut = VrefH 8 VREFX DiagOut = VrefX = VrefH * 199/200 9 VBG DiagOut = Vbg from SRSS 10 VIN1 DiagOut = Vin1 11 VIN2 DiagOut = Vin2 12 VIN3 DiagOut = Vin3 13 I_SOURCE DiagOut = Isource (10uA) 14 I_SINK DiagOut = Isink (10uA) 15 DIAG_EN Diagnostic Reference enable (only valid if ENABLED=1) - 0: Diagnostic Reference disabled (powered down resistor ladder and current mirrors, DiagOut = Vssa). - 1: Diagnostic Reference enabled, output signal select according to DIAG_SEL (note also EPASS_MMIO.PASS_CTL.REFBUF_EN must be set). [31:31] read-write PRECOND_CTL Preconditioning control register. 0x10 32 read-write 0x0 0xF PRECOND_TIME Number ADC clock cycles that Preconditioning is done before the sample window starts. If OVERLAP_EN=0 there will be 1 additional break before make cycle between preconditioning and sampling. Note that the minimum value is 1 (0 gives the same result as 1). [3:0] read-write ANA_CAL Current analog calibration values 0x80 32 read-write 0x0 0x1F00FF AOFFSET Analog offset correction [7:0] read-write AGAIN Analog gain correction [20:16] read-write DIG_CAL Current digital calibration values 0x84 32 read-write 0x0 0x3F0FFF DOFFSET Digital offset correction Subtract DOFFSET from ADC output. [11:0] read-write DGAIN Digital gain correction. Signed value to correct +/- 30 codes for the maximum input voltage. Corrected = (D - DOFFSET) + ( (D - DOFFSET) * DGAIN + 0x800) / 0x1000 [21:16] read-write ANA_CAL_ALT Alternate analog calibration values 0x90 32 read-write 0x0 0x1F00FF AOFFSET See corresponding ANA_CAL field [7:0] read-write AGAIN See corresponding ANA_CAL field [20:16] read-write DIG_CAL_ALT Alternate digital calibration values 0x94 32 read-write 0x0 0x3F0FFF DOFFSET See corresponding DIG_CAL field [11:0] read-write DGAIN See corresponding DIG_CAL field [21:16] read-write CAL_UPD_CMD Calibration update command 0x98 32 read-write 0x0 0x1 UPDATE Calibration update command: coherently copy values from alternate calibration regs to current calibration regs. Software sets this bit when the alternate calibration values have been set with the new values. Hardware will do the calibration update as soon as the ADC is idle or a 'continuous' triggered group completes. This ensures that all acquisitions within a group scan (even if preempted) are done with the same calibration values. This bit is cleared at the same time the calibration update is done. By clearing this bit software can cancel a requested update. Note: if the ADC is always busy with acquisitions for non continuously triggered groups/channels then the calibration update will remain pending forever. In such a case the software can either do a non coherent update by writing directly to the current calibration registers, or software can force the ADC to idle by disabling some or all channels. Software can check/poll this bit to see if the calibration update has taken effect. [0:0] read-write TR_PEND Trigger pending status 0x100 32 read-only 0x0 0xFFFFFFFF TR_PEND Trigger Pending. Hardware will set this bit if a hardware trigger is received. [31:0] read-only WORK_VALID Channel working data register 'valid' bits 0x180 32 read-only 0x0 0xFFFFFFFF WORK_VALID If set the corresponding WORK register is valid, i.e. was already acquired during the current group scan. If this bit is low then either the channel is not enabled, not yet acquired or it is used as a pulse detect channel. [31:0] read-only WORK_RANGE Range detected 0x184 32 read-only 0x0 0xFFFFFFFF RANGE N/A [31:0] read-only WORK_RANGE_HI Range detect above Hi flag 0x188 32 read-only 0x0 0xFFFFFFFF ABOVE_HI Out of range was detected and the value was above the Hi threshold [31:0] read-only WORK_PULSE Pulse detected 0x18C 32 read-only 0x0 0xFFFFFFFF PULSE N/A [31:0] read-only RESULT_VALID Channel result data register 'valid' bits 0x1A0 32 read-only 0x0 0xFFFFFFFF RESULT_VALID If set the corresponding RESULT register is valid, i.e. was acquired during the preceding group scan. If this bit is low, after a group scan completed, then either the channel is not enabled or is used as a pulse detect channel. [31:0] read-only RESULT_RANGE_HI Channel Range above Hi flags 0x1A4 32 read-only 0x0 0xFFFFFFFF ABOVE_HI Out of range was detected and the value was above the Hi threshold [31:0] read-only STATUS Current status of internal SAR registers (mostly for debug) 0x200 32 read-only 0x0 0xE000371F CUR_CHAN current channel being acquired, only valid if BUSY. [4:0] read-only CUR_PRIO priority of current group/channel, only valid if BUSY. [10:8] read-only CUR_PREEMPT_TYPE Preempting type of current group/channel, only valid if BUSY. [13:12] read-only DBG_FREEZE If high then the SAR is prevented from starting a new acquisition, see DBG_FREEZE_EN. [29:29] read-only PWRUP_BUSY If high then the SAR is waiting for PWRUP_TIME due to IDLE_PWRDWN [30:30] read-only BUSY If high then the SAR is busy with a conversion. [31:31] read-only AVG_STAT Current averaging status (for debug) 0x204 32 read-only 0x0 0xFF0FFFFF CUR_AVG_ACCU the current value of the averaging accumulator [19:0] read-only CUR_AVG_CNT the current value of the averaging counter. Note that the value shown is updated after the sample window and therefore runs ahead of the accumulator update. [31:24] read-only 32 64 CH[%s] Channel structure 0x00000800 TR_CTL Trigger control. 0x0 32 read-write 0x800 0x80000B77 SEL Trigger select [2:0] read-write OFF Use for channels in group, except the first channel 0 TCPWM Trigger from corresponding TCPWM channel 1 GENERIC0 Generic trigger input 0 2 GENERIC1 N/A 3 GENERIC2 N/A 4 GENERIC3 N/A 5 GENERIC4 N/A 6 CONTINUOUS Always triggered (also called idle), can only be used for at most 1 channel 7 PRIO Channel priority: '0': highest priority. '1' ... '6' '7': lowest priority. Channels with the same priority constitute a priority level. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority level with pending channels is identified. Second, within this priority level, round robin arbitration is applied. Round robin arbitration (within a priority level) gives the highest priority to the lower channel indices (within the priority level). [6:4] read-write PREEMPT_TYPE Preemption type allow for this group [9:8] read-write ABORT_CANCEL Abort ongoing acquisition, do not return Clear pending trigger for aborted group and set Cancelled interrupt. Also 'Abort' whenever this group (do not pend the trigger) is not immediately scheduled for acquisition after a new trigger arrives. For this preemption type only, only a positive edge on the trigger can trigger the channel, i.e. CONTINUOUS or level high operation is not supported (to avoid continuous Cancelled interrupts). In case CTL.IDLE_PWRDWN is used and the analog is powered down, the group cannot be immediately scheduled for acquisition and therefore a trigger for a group with this preemption type will power up the analog, but the group will ABORT and set the Cancelled interrupt 0 ABORT_RESTART Abort ongoing acquisition, up on return Restart group from first channel. 1 ABORT_RESUME Abort ongoing acquisition, up on return Resume group from aborted channel If averaging, discard averaging results so far and restart averaging. 2 FINISH_RESUME Complete ongoing acquisition (including averaging), up on return Resume group from next channel 3 GROUP_END 0: continue group with next channel 1: last channel of a group. Note that for the channel with the highest index (SAR_CH_NR) this always needs to be set [11:11] read-write DONE_LEVEL select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO [31:31] read-write PULSE tr_ch_done generates a 2 cycle pulse (clk_sys), no need to read the result to clear (also no ch_overflow detection) 0 LEVEL tr_ch_done is a level output until the result register is read (typical for DW usage, this also enables ch_overflow detection when DW is too slow) 1 SAMPLE_CTL Sample control. 0x4 32 read-write 0x0 0x0 PIN_ADDR N/A [5:0] read-write PORT_ADDR Select the physical port. This field is only valid for ADC0. ADC0 can control and connect to the SARMUX of the neighboring ADC1-3. This requires the corresponding ADC to be off while the SARMUX is left on. When ADC0 controls another SARMUX it uses the PIN_ADDR, EXT_MUX_EN/SEL of this channel to control the other SARMUX. [7:6] read-write SARMUX0 ADC uses it's own SARMUX 0 SARMUX1 ADC0 uses SARMUX1 (only valid for ADC0, undefined result if used for ADC1-3) 1 SARMUX2 ADC0 uses SARMUX2 (only valid for ADC0, undefined result if used for ADC1-3) 2 SARMUX3 ADC0 uses SARMUX3 (only valid for ADC0, undefined result if used for ADC1-3) 3 EXT_MUX_SEL External analog mux select. This bit setting is related to EXT_MUX[x]_y on pin assignment. 0x0: Select EXT_MUX[x]_0 pin 0x1: Select EXT_MUX[x]_1 pin [10:8] read-write EXT_MUX_EN External analog mux enable. This enable can be used as enable (chip select) for the external analog mux (this enable is not used as enable for the GPIO output driver). This enable also prevents unnecessary toggle activity on the select signals of the external analog mux. When this enable is low EXT_MUX_SEL value will be ignored and the previous value will be maintained. Note that an external analog mux can only be used in combination with a pin input, i.e. PIN_ADDR<32 or Vmotor. If an internal signal is selected this enable should be 0. [11:11] read-write PRECOND_MODE Select preconditioning mode. Preconditioning (dis)charges the SAR sample capacitor to the selected reference voltage for PRECOND_TIME (global) cycles, a break before make cycle will be inserted before sampling starts (SAMPLE_TIME). [13:12] read-write OFF No preconditioning 0 VREFL Discharge to VREFL 1 VREFH Charge to VREFH 2 DIAG Connect the Diagnostic reference output during preconditioning. The Diagnostic reference should be configured to output a reference voltage. Note: this selection is mutual exclusive with using the Diagnostic reference to supply an ibias current for OVERLAP. 3 OVERLAP_DIAG Select Overlap mode or SARMUX Diagnostics, in both cases the Diagnostic reference is used. With Overlap the Diagnostic reference typically sources or sinks a small current which is connected at the same time as the analog signal being sampled. For SARMUX Diagnostics the Diagnostic reference should provide a reference voltage which is selected at the SARMUX input instead of the normal analog signal being sampled. [15:14] read-write OFF No overlap or SARMUX Diagnostics 0 HALF Sample the selected analog input for 2 SAMPLE_TIME periods. During the first period use overlap sampling, i.e. connect both the analog input and Diagnostic reference. During second period only connect the analog input. 1 FULL Like normal sample the selected analog input for a single SAMPLE_TIME period but use overlap sampling, i.e. connect both the analog input and Diagnostic reference. 2 MUX_DIAG Select Diagnostic reference instead of analog signal at the input of the SARMUX. This enables a functional safety check of the SARMUX analog connections. 3 SAMPLE_TIME Sample time (aperture) in ADC clock cycles. Minimum is 1 (0 gives the same result as 1), minimum time needed for proper settling is at least 412ns, i.e.11 clock cycles at the max frequency of 26.7MHz. [27:16] read-write ALT_CAL Use alternate calibration values instead of the current calibration values. This allows the firmware to allocate one or more channels to quietly re-calibrate the ADC in the background of regular processing. 0 = use regular calibration values (ANA/DIG_CAL) 1 = use alternate calibration values (ANA/DIG_CAL_ALT) Note: typically calibration measurements select VrefL (PIN_ADDR=62) or VrefH (PIN_ADDR=63) [31:31] read-write POST_CTL Post processing control 0x8 32 read-write 0x0 0x0 POST_PROC Post processing [2:0] read-write NONE No postprocessing 0 AVG Averaging 1 AVG_RANGE Averaging followed by Range detect 2 RANGE Range detect 3 RANGE_PULSE Range detect followed by pulse detect 4 RSVD0 N/A 5 RSVD1 N/A 6 RSVD2 N/A 7 LEFT_ALIGN Left or right align data in result[15:0]. 0: the data is right aligned in result[11:0], with sign extension to 16 bits if enabled 1: the data is left aligned in result[15:4] with the lower nibble 0. Caveat if the result was more than 12 bits (e.g. after averaging) then the bits above 12 will be discarded. [6:6] read-write SIGN_EXT Output data is sign extended [7:7] read-write UNSIGNED Default: result data is unsigned (zero extended if needed) 0 SIGNED Result data is signed (sign extended if needed) 1 AVG_CNT Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled. A channel will be sampled (AVG_CNT+1) = [1..256] times. The signal will be acquired back to back (1st order accumulate and dump filter), the average result is calculated and stored and then the next enabled channel is sampled. If more than 16 sample are taken (AVG_CNT>=16) then AVG_SHIFT must be set so that the result after shifting fits in 16 bits Pulse detect positive reload value PULSE_POS_RL[7:0] [15:8] read-write SHIFT_R Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here. Software has to make sure that the result fits in less than 16 bits. Any value >12 will be treated as 12, bit [4] is always ignored. This can also be used to fit the 12-bit result in 8 bits. Pulse detect negative reload value PULSE_NEG_RL[4:0] [20:16] read-write RANGE_MODE Range detect mode [23:22] read-write BELOW_LO Below Low threshold (result < Lo) 0 INSIDE_RANGE Inside range (Lo <= result < Hi) 1 ABOVE_HI Above high threshold (Hi <= result) 2 OUTSIDE_RANGE Outside range (result < Lo || Hi <= result) 3 TR_DONE_GRP_VIO Select tr_sar_ch_done mode for last channel of a group, ignored for all other channels Also see TR_CTL.DONE_LEVEL [25:25] read-write DONE Default: tr_sar_ch_done is set when the group is done 0 GRP_RANGE_VIO tr_sar_ch_done is only set if any of the channels in the group has a Range Violation. This mode is ignored if this is not the last channel in the group. Note that if none of the channels in the group have Range detection enabled then the trigger will never get set. 1 RANGE_CTL Range thresholds 0xC 32 read-write 0x0 0x0 RANGE_LO Range detect low threshold (Lo) [15:0] read-write RANGE_HI Range detect high threshold (Hi) [31:16] read-write INTR Interrupt request register. 0x10 32 read-write 0x0 0x707 GRP_DONE Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done. Write with '1' to clear bit. [0:0] read-write GRP_CANCELLED Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED. Note that it is possible that also the GRP_DONE interrupt is set. If that is the case one or more new triggers were detected while the group was already busy, i.e. triggers are too fast. Write with '1' to clear bit. [1:1] read-write GRP_OVERFLOW Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending. Write with '1' to clear bit. [2:2] read-write CH_RANGE Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. This interrupt is mutual exclusive with Pulse detect interrupt. Write with '1' to clear bit. [8:8] read-write CH_PULSE Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero. This interrupt is mutual exclusive with Range detect interrupt. Write with '1' to clear bit. [9:9] read-write CH_OVERFLOW Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup. Write with '1' to clear bit. [10:10] read-write INTR_SET Interrupt set request register 0x14 32 read-write 0x0 0x707 GRP_DONE_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write GRP_CANCELLED_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write GRP_OVERFLOW_SET Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write CH_RANGE_SET Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write CH_PULSE_SET Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write CH_OVERFLOW_SET Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write INTR_MASK Interrupt mask register. 0x18 32 read-write 0x0 0x707 GRP_DONE_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write GRP_CANCELLED_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write GRP_OVERFLOW_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write CH_RANGE_MASK Mask bit for corresponding bit in interrupt request register. [8:8] read-write CH_PULSE_MASK Mask bit for corresponding bit in interrupt request register. [9:9] read-write CH_OVERFLOW_MASK Mask bit for corresponding bit in interrupt request register. [10:10] read-write INTR_MASKED Interrupt masked request register 0x1C 32 read-only 0x0 0x707 GRP_DONE_MASKED Logical and of corresponding request and mask bits. [0:0] read-only GRP_CANCELLED_MASKED Logical and of corresponding request and mask bits. [1:1] read-only GRP_OVERFLOW_MASKED Logical and of corresponding request and mask bits. [2:2] read-only CH_RANGE_MASKED Logical and of corresponding request and mask bits. [8:8] read-only CH_PULSE_MASKED Logical and of corresponding request and mask bits. [9:9] read-only CH_OVERFLOW_MASKED Logical and of corresponding request and mask bits. [10:10] read-only WORK Working data register 0x20 32 read-only 0x0 0xF0000000 WORK SAR conversion working data of the channel. The data is written here right after sampling this channel. [15:0] read-only ABOVE_HI_MIR mirror bit of the corresponding ABOVE_HI bit [28:28] read-only RANGE_MIR mirror bit of corresponding bit in WORK_RANGE register [29:29] read-only PULSE_MIR mirror bit of corresponding bit in WORK_PULSE register [30:30] read-only VALID_MIR mirror bit of corresponding bit in WORK_VALID register [31:31] read-only RESULT Result data register 0x24 32 read-only 0x0 0xF0000000 RESULT SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. [15:0] read-only ABOVE_HI_MIR mirror bit of the corresponding ABOVE_HI bit [28:28] read-only RANGE_INTR_MIR mirror bit of INTR.CH_RANGE bit [29:29] read-only PULSE_INTR_MIR mirror bit of INTR.CH_PULSE bit [30:30] read-only VALID_MIR mirror bit of the corresponding bit in RESULT_VALID register [31:31] read-only GRP_STAT Group status register 0x28 32 read-only 0x0 0x10707 GRP_COMPLETE Group acquisition complete. This is a copy of the INTR.GRP_DONE bit. [0:0] read-only GRP_CANCELLED Group Cancelled. This is a copy of the INTR.GRP_CANCELLED bit. [1:1] read-only GRP_OVERFLOW Group Overflow. This is a copy of the INTR.GRP_OVERFLOW bit. [2:2] read-only CH_RANGE_COMPLETE Channel Range complete. This is a copy of the INTR.CH_RANGE bit. [8:8] read-only CH_PULSE_COMPLETE Channel Pulse complete. This is a copy of the INTR.CH_PULSE bit. [9:9] read-only CH_OVERFLOW Channel Overflow. This is a copy of the INTR.CH_OVERFLOW bit. [10:10] read-only GRP_BUSY Group acquisition busy. This is a copy of the TR_PENDING bit of the first channel of the group. [16:16] read-only ENABLE Enable register 0x38 32 read-write 0x0 0x1 CHAN_EN Channel enable. - 0: the corresponding channel is disabled. Corresponding trigger will be reset immediately. - 1: the corresponding channel is enabled. Note: To disable a group either stop the trigger first or begin with disabling the lowest channel first. To enable a group either start with enabling the last channel first and the first channel last, or start the trigger after all channels are enabled. If these rules are not followed the result is undefined. [0:0] read-write TR_CMD Software triggers 0x3C 32 read-write 0x0 0x1 START Software start trigger. When written with '1', a start trigger is generated which sets the corresponding TR_PEND bit (only if the channel is enabled). A read always returns a 0. [0:0] read-write EPASS_MMIO PASS top-level MMIO (Generic Triggers) 0x000F0000 PASS_CTL PASS control register 0x0 32 read-write 0x0 0xF0600033 SUPPLY_MON_EN_A Supply monitor enable for AMUXBUS_A (amuxbus_a_mon) [0:0] read-write SUPPLY_MON_LVL_A Supply monitor level select for AMUXBUS_A [1:1] read-write VRL amuxbus_a_mon = VRL 0 VRH amuxbus_a_mon = VRH 1 SUPPLY_MON_EN_B Supply monitor enable for AMUXBUS_B (amuxbus_b_mon) [4:4] read-write SUPPLY_MON_LVL_B Supply monitor level select for AMUXBUS_B [5:5] read-write VRL amuxbus_b_mon = VRL 0 VRH amuxbus_b_mon = VRH 1 REFBUF_MODE Reference mode. The reference needs to be present when using TEMP sensor or diagnostic reference (in addition to SAR.DIAG_CTL.DIAG_EN). Note that setting this mode is not required for the ADC operation itself. [22:21] read-write OFF No reference 0 ON Reference = buffered Vbg from SRSS 1 RSVD undefined 2 BYPASS Reference = unbuffered Vbg from SRSS 3 DBG_FREEZE_EN Debug pause enable, 1 per ADC. When set a high tr_debug_freeze trigger will prevent the scheduler from starting acquisitions on a new channel. Note that averaging for an already started channel will be completed. [31:28] read-write 4 4 SAR_TR_IN_SEL[%s] per SAR generic input trigger select 0x20 32 read-write 0x43210 0xFFFFF IN0_SEL Select generic trigger for SAR generic trigger input 0 [3:0] read-write IN1_SEL Select generic trigger for SAR generic trigger input 1 [7:4] read-write IN2_SEL Select generic trigger for SAR generic trigger input 2 [11:8] read-write IN3_SEL Select generic trigger for SAR generic trigger input 3 [15:12] read-write IN4_SEL Select generic trigger for SAR generic trigger input 4 [19:16] read-write 4 4 SAR_TR_OUT_SEL[%s] per SAR generic output trigger select 0x40 32 read-write 0x100 0x3F3F OUT0_SEL Select SAR output trigger for generic trigger output 0 0-31: selects a tr_sar_ch_done trigger 32-63: selects a tr_sar_ch_rangvio trigger [5:0] read-write OUT1_SEL Select SAR output trigger for generic trigger output 1 [13:8] read-write TEST_CTL Test control bits 0x80 32 read-write 0x0 0x137D TS_CAL_CUR_IN External current input switch control, for Temperature Sensor Calibration [0:0] read-write TS_CAL_VB_OUT Voltage Base switch control, for Temperature Sensor Calibration [2:2] read-write TS_CAL_VE_OUT Voltage Emitter switch control, for Temperature Sensor Calibration [3:3] read-write TS_CAL_DIODE_EN Diode Enable, disconnect or connect the base and collector terminal of the BJT [4:4] read-write TS_CAL_DIODE_PNP_EN Enable signal for PNP transistor. This transistor will be used only during calibration for accurate estimation of chip temp. 0 = Turn PNP off 1 = Configure PNP as a diode (short base and collector) [5:5] read-write TS_CAL_VI_SEL Select current or voltage output on 'v_temp' pin, for Temperature Sensor Calibration [6:6] read-write CURRENT Current is selected 0 VOLTAGE Voltage is selected 1 TS_CAL_CUR_SEL Select the current going into the BJT, for Temperature Sensor Calibration [9:8] read-write I_1U Select 1 uA 0 I_2U Select 2 uA 1 I_5U Select 5 uA 2 I_10U Select 10 uA 3 TS_CAL_SPARE Spare [12:12] read-write VIDEOSS0 Video and Graphics Subsystem IP VIDEOSS 0x40A00000 0 1048576 registers SUBSS Sub Interface 0x00000000 VIDEOSSCFG Subsystem Control. 0x00000000 CTL IP Control Register 0x0 32 read-write 0x0 0x80000000 ENABLED VIDEOSS enable/disable bit. [31:31] read-write DIS Disable the entire VIDEOSS. System will be held in reset until re-enabled (with the exception of the AHB interface and this register) 0 EN Enable VIDEOSS 1 GFX2D_CTL IP Control Register for Graphics 2D Core 0x4 32 read-write 0x80000000 0x80000000 GFX2D_ENABLED If disabled, the Graphics 2D Core is put on reset and its clock input gated. [31:31] read-write IPIDENTIFIER IP and Design Release Identification 0x8 32 read-only 0x0 0x0 IPPLATFORM Name of SOC Platform [0:0] read-only MXS40_S40E MXS40 High Temperature Variant 0 IPNAME Name of IP [5:4] read-only VIDEOSS Video and Graphics Subsystem with internal SRAM 0 VIDEOSSDDR Video and Graphics Subsystem for external DDR-SDRAM 1 VIDEOSSLITE Display Composition Subsystem 2 IPVERSION IP Vault Version [9:8] read-only IPPHASE IP Vault Phase [13:12] read-only IPMATURITY CIC Chip Integration Cycle [17:16] read-only NONE Pre Review 0 CPR CIC Physical Readiness Review 1 CMR CIC Mock Review 2 CFR CIC Final Handoff Review 3 IPRELEASE Design Release ID [27:20] read-only IPCONFIGURATION IP Design Configuration 0xC 32 read-only 0x0 0x0 GFX2D Graphics 2D Core available (0 = no, 1 = yes) [0:0] read-only MIPICSI MIPI CSI-2 Video Input Interface available (0 = no, 1 = yes) [1:1] read-only FPDLINK0 1st FPDLink Video Output Interface available (0 = no, 1 = yes) [2:2] read-only FPDLINK1 2nd FPDLink Video Output Interface available (0 = no, 1 = yes) [3:3] read-only LCDBUSIF LCD Bus Output Interface available (0 = no, 1 = yes) [4:4] read-only DISPLAY1 2nd Display Engine available (0 = no, 1 = yes) [5:5] read-only CAPTURE0 Capture Engine available (0 = no, 1 = yes) [6:6] read-only WARPING Warping Layer available in Composition Engine (0 = no, 1 = yes) [7:7] read-only TCON Timing Controller available in Display Engine (0 = no, 1 = yes) [8:8] read-only VRAM Embedded Video RAM available (0 = no, 1 = yes) [9:9] read-only VRAMSIZE Size of embedded Video RAM if available (in MB). [19:16] read-only CLKDSP0CFG Display 0 Clock Configuration Register 0x10 32 read-write 0x10 0x13 DIVVAL0 Clock Divider Setting (KDIV) [1:0] read-write DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 TTLCLKINV0 Enable bit for pixel clock inversion on TTL display output interface 0. If enabled, pixel data changes with falling instead of rising clock edge (180 deg phase shift). [4:4] read-write CLKDSP1CFG Display 1 Clock Configuration Register 0x14 32 read-write 0x10 0x13 DIVVAL1 Clock Divider Setting (KDIV) [1:0] read-write DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 TTLCLKINV1 Enable bit for pixel clock inversion on TTL display output interface 1. If enabled, pixel data changes with falling instead of rising clock edge (180 deg phase shift). [4:4] read-write CAP0CFG Capture 0 Configuration 0x18 32 read-write 0x0 0x3 CAP0SRC Capture Source Selection [1:0] read-write TTL TTL0 interface selected 0 CSI CSI-2 (DPHY) Interface Selected 1 DSP0 N/A 2 DSP1 N/A 3 FPDLINKCFG FPDLink Configuration 0x1C 32 read-write 0x0 0x1 FPDLINKSEL Selects the channel mode for the two FPDlink interfaces. [0:0] read-write SINGLE FPDlink 0 and 1 are operating independently, driven by the two Display Engine 0 and 1. 0 DUAL FPDlink 0 and 1 are operating synchronously, both driven by Display Engine 0. 1 DSP0_CTL Enable for Display Engine 0 0x20 32 read-write 0x0 0x80000000 DSP0_ENABLED This field, along with CTL.ENABLED above which enables the whole videoss IP, controls the clock and reset release of the DSP0 clock domain. [31:31] read-write DSP1_CTL Enable for Display Engine 1 0x24 32 read-write 0x0 0x80000000 DSP1_ENABLED This field, along with CTL.ENABLED above which enables the whole videoss IP, controls the clock and reset release of the DSP1 clock domain. [31:31] read-write VRAM Video RAM. 0x00000400 ARBITER_PRIORITY N/A 0x0 32 read-write 0x0 0x333330F PRIORITY_WR0 Priority for write slave interfaces 0. [1:0] read-write PRIORITY_WR1 Priority for write slave interfaces 1. [3:2] read-write PRIORITY_RD0 Priority for read slave interface 0. [9:8] read-write PRIORITY_RD1 Priority for read slave interface 1. [13:12] read-write PRIORITY_RD2 Priority for read slave interface 2. [17:16] read-write PRIORITY_RD3 Priority for read slave interface 3. [21:20] read-write PRIORITY_RD4 Priority for read slave interface 4. [25:24] read-write GFX2D Graphics 2D Core 0x00040000 GFX2DCFG Graphics 2D Core config 0x00000000 INTR_GFX2D Interrupt cause register 0x20 32 read-write 0x0 0xFFFFFF INTR_GFX2D Interrupt status vector. A bit is set when the related event occurs or the corresponding bit of INTR_GFX2D_SET is written. By writing 1 the corresponding bit is cleared. [23:0] read-write INTR_GFX2D_SET Interrupt set register 0x24 32 write-only 0x0 0x0 INTR_GFX2D_SET Interrupt set vector. Writing a 1 to this field sets the corresponding bit of INTR_GFX2D. [23:0] write-only INTR_GFX2D_MASK Interrupt mask register 0x28 32 read-write 0x0 0xFFFFFF INTR_GFX2D_MASK Interrupt mask vector. Please note that this enable vector does not affect the INTR0 register field. It only affects INTR_GFX2D_MASKED. [23:0] read-write INTR_GFX2D_MASKED Interrupt masked register 0x2C 32 read-only 0x0 0x0 INTR_GFX2D_MASKED Status vector that generates the interrupt to the CPU if at least one bit of this field is set. This field corresponds to the bit-wise AND between INTR_GFX2D and INTR_GFX2D_MASK fields. [23:0] read-only INTR_CMDSEQ Interrupt cause register for CmdSeq 0x30 32 read-write 0x0 0x3FFFFF INTR_CMDSEQ Interrupt status vector. A bit is set when the related event occurs or the corresponding bit of INTR_CMDSEQ_SET is written. By writing 1 the corresponding bit is cleared. [21:0] read-write INTR_CMDSEQ_SET Interrupt set register 0x34 32 write-only 0x0 0x0 INTR_CMDSEQ_SET Interrupt set vector. Writing a 1 to this field sets the corresponding bit of INTR_CMDSEQ. [21:0] write-only 16 4 GENERALPURPOSE[%s] General purpose config memory 0x40 32 read-write 0x0 0x0 GENERALPURPOSE General purpose config memory entry, does not have any function. [31:0] read-write CMDSEQ Command Sequencer 0x00010000 TASKBUFFERADDRESS0 Task buffer 0 address register 0x0 32 read-write 0x0 0xFFFFFFF8 ADDRESSTB0 Task buffer 0 base address in multiple of 64-bit words. [31:3] read-write TASKBUFFERSIZE0 Task buffer 0 size register 0x4 32 read-write 0x0 0xFFFF SIZETB0 Task buffer 0 size in multiple of 32-bit words. The maximal size of task buffer equals to 4 * (2^16 - 1) bytes. The minimal size required to start execution is 2, because the minimal value of the stop offset is 1 and it has to be smaller then the task buffer size. [15:0] read-write TASKBUFFERSTOPOFFSET0 Task buffer 0 stop offset register 0x8 32 read-write 0x0 0xFFFF STOPOFFSETTB0 Task buffer 0 stop offset in multiple of 32-bit words to determine the last valid scheduling instruction. Only scheduling instructions up to this offset are executed or with other words instruction at the StopOffset-1 is the last instruction which is executed. [15:0] read-write TASKBUFFERADDRESS1 Task buffer 1 address register 0xC 32 read-write 0x0 0xFFFFFFF8 ADDRESSTB1 Task buffer 1 base address in multiple of 64-bit words. [31:3] read-write TASKBUFFERSIZE1 Task buffer 1 size register 0x10 32 read-write 0x0 0xFFFF SIZETB1 Task buffer 1 size in multiple of 32-bit words. The maximal size of task buffer equals to 4 * (2^16 - 1) bytes. The minimal size required to start execution is 2, because the minimal value of the stop offset is 1 and it has to be smaller then the task buffer size. [15:0] read-write TASKBUFFERSTOPOFFSET1 Task buffer 1 stop offset register 0x14 32 read-write 0x0 0xFFFF STOPOFFSETTB1 Task buffer 1 stop offset in multiple of 32-bit words to determine the last valid scheduling instruction. Only scheduling instructions up to this offset are executed or with other words instruction at the StopOffset-1 is the last instruction which is executed. [15:0] read-write TASKBUFFERADDRESS2 Task buffer 2 address register 0x18 32 read-write 0x0 0xFFFFFFF8 ADDRESSTB2 Task buffer 2 base address in multiple of 64-bit words. [31:3] read-write TASKBUFFERSIZE2 Task buffer 2 size register 0x1C 32 read-write 0x0 0xFFFF SIZETB2 Task buffer 2 size in multiple of 32-bit words. The maximal size of task buffer equals to 4 * (2^16 - 1) bytes. The minimal size required to start execution is 2, because the minimal value of the stop offset is 1 and it has to be smaller then the task buffer size. [15:0] read-write TASKBUFFERSTOPOFFSET2 Task buffer 2 stop offset register 0x20 32 read-write 0x0 0xFFFF STOPOFFSETTB2 Task buffer 2 stop offset in multiple of 32-bit words to determine the last valid scheduling instruction. Only scheduling instructions up to this offset are executed or with other words instruction at the StopOffset-1 is the last instruction which is executed. [15:0] read-write TASKBUFFERADDRESS3 Task buffer 3 address register 0x24 32 read-write 0x0 0xFFFFFFF8 ADDRESSTB3 Task buffer 3 base address in multiple of 64-bit words. [31:3] read-write TASKBUFFERSIZE3 Task buffer 3 size register 0x28 32 read-write 0x0 0xFFFF SIZETB3 Task buffer 3 size in multiple of 32-bit words. The maximal size of task buffer equals to 4 * (2^16 - 1) bytes. The minimal size required to start execution is 2, because the minimal value of the stop offset is 1 and it has to be smaller then the task buffer size. [15:0] read-write TASKBUFFERSTOPOFFSET3 Task buffer 3 stop offset register 0x2C 32 read-write 0x0 0xFFFF STOPOFFSETTB3 Task buffer 3 stop offset in multiple of 32-bit words to determine the last valid scheduling instruction. Only scheduling instructions up to this offset are executed or with other words instruction at the StopOffset-1 is the last instruction which is executed. [15:0] read-write TASKBUFFERADDRESS4 Task buffer 4 address register 0x30 32 read-write 0x0 0xFFFFFFF8 ADDRESSTB4 Task buffer 4 base address in multiple of 64-bit words. [31:3] read-write TASKBUFFERSIZE4 Task buffer 4 size register 0x34 32 read-write 0x0 0xFFFF SIZETB4 Task buffer 4 size in multiple of 32-bit words. The maximal size of task buffer equals to 4 * (2^16 - 1) bytes. The minimal size required to start execution is 2, because the minimal value of the stop offset is 1 and it has to be smaller then the task buffer size. [15:0] read-write TASKBUFFERSTOPOFFSET4 Task buffer 4 stop offset register 0x38 32 read-write 0x0 0xFFFF STOPOFFSETTB4 Task buffer 4 stop offset in multiple of 32-bit words to determine the last valid scheduling instruction. Only scheduling instructions up to this offset are executed or with other words instruction at the StopOffset-1 is the last instruction which is executed. [15:0] read-write TASKBUFFERADDRESS5 Task buffer 5 address register 0x3C 32 read-write 0x0 0xFFFFFFF8 ADDRESSTB5 Task buffer 5 base address in multiple of 64-bit words. [31:3] read-write TASKBUFFERSIZE5 Task buffer 5 size register 0x40 32 read-write 0x0 0xFFFF SIZETB5 Task buffer 5 size in multiple of 32-bit words. The maximal size of task buffer equals to 4 * (2^16 - 1) bytes. The minimal size required to start execution is 2, because the minimal value of the stop offset is 1 and it has to be smaller then the task buffer size. [15:0] read-write TASKBUFFERSTOPOFFSET5 Task buffer 5 stop offset register 0x44 32 read-write 0x0 0xFFFF STOPOFFSETTB5 Task buffer 5 stop offset in multiple of 32-bit words to determine the last valid scheduling instruction. Only scheduling instructions up to this offset are executed or with other words instruction at the StopOffset-1 is the last instruction which is executed. [15:0] read-write TASKBUFFERADDRESS6 Task buffer 6 address register 0x48 32 read-write 0x0 0xFFFFFFF8 ADDRESSTB6 Task buffer 6 base address in multiple of 64-bit words. [31:3] read-write TASKBUFFERSIZE6 Task buffer 6 size register 0x4C 32 read-write 0x0 0xFFFF SIZETB6 Task buffer 6 size in multiple of 32-bit words. The maximal size of task buffer equals to 4 * (2^16 - 1) bytes. The minimal size required to start execution is 2, because the minimal value of the stop offset is 1 and it has to be smaller then the task buffer size. [15:0] read-write TASKBUFFERSTOPOFFSET6 Task buffer 6 stop offset register 0x50 32 read-write 0x0 0xFFFF STOPOFFSETTB6 Task buffer 6 stop offset in multiple of 32-bit words to determine the last valid scheduling instruction. Only scheduling instructions up to this offset are executed or with other words instruction at the StopOffset-1 is the last instruction which is executed. [15:0] read-write TASKBUFFERADDRESS7 Task buffer 7 address register 0x54 32 read-write 0x0 0xFFFFFFF8 ADDRESSTB7 Task buffer 7 base address in multiple of 64-bit words. [31:3] read-write TASKBUFFERSIZE7 Task buffer 7 size register 0x58 32 read-write 0x0 0xFFFF SIZETB7 Task buffer 7 size in multiple of 32-bit words. The maximal size of task buffer equals to 4 * (2^16 - 1) bytes. The minimal size required to start execution is 2, because the minimal value of the stop offset is 1 and it has to be smaller then the task buffer size. [15:0] read-write TASKBUFFERSTOPOFFSET7 Task buffer 7 stop offset register 0x5C 32 read-write 0x0 0xFFFF STOPOFFSETTB7 Task buffer 7 stop offset in multiple of 32-bit words to determine the last valid scheduling instruction. Only scheduling instructions up to this offset are executed or with other words instruction at the StopOffset-1 is the last instruction which is executed. [15:0] read-write TASKBUFFEREXECOFFSET0 Task buffer 0 execute offset register 0x60 32 read-only 0x0 0x0 EXECOFFSETTB0 Task buffer 0 execution offset in multiple of 32-bit words. Offset of the scheduling instruction that is to be executed next. Instruction at address = AddressTB0 has offset zero. [15:0] read-only TASKBUFFEREXECOFFSET1 Task buffer 1 execute offset register 0x64 32 read-only 0x0 0x0 EXECOFFSETTB1 Task buffer 1 execution offset in multiple of 32-bit words. Offset of the scheduling instruction that is to be executed next. Instruction at address = AddressTB1 has offset zero. [15:0] read-only TASKBUFFEREXECOFFSET2 Task buffer 2 execute offset register 0x68 32 read-only 0x0 0x0 EXECOFFSETTB2 Task buffer 2 execution offset in multiple of 32-bit words. Offset of the scheduling instruction that is to be executed next. Instruction at address = AddressTB2 has offset zero. [15:0] read-only TASKBUFFEREXECOFFSET3 Task buffer 3 execute offset register 0x6C 32 read-only 0x0 0x0 EXECOFFSETTB3 Task buffer 3 execution offset in multiple of 32-bit words. Offset of the scheduling instruction that is to be executed next. Instruction at address = AddressTB3 has offset zero. [15:0] read-only TASKBUFFEREXECOFFSET4 Task buffer 4 execute offset register 0x70 32 read-only 0x0 0x0 EXECOFFSETTB4 Task buffer 4 execution offset in multiple of 32-bit words. Offset of the scheduling instruction that is to be executed next. Instruction at address = AddressTB4 has offset zero. [15:0] read-only TASKBUFFEREXECOFFSET5 Task buffer 5 execute offset register 0x74 32 read-only 0x0 0x0 EXECOFFSETTB5 Task buffer 5 execution offset in multiple of 32-bit words. Offset of the scheduling instruction that is to be executed next. Instruction at address = AddressTB5 has offset zero. [15:0] read-only TASKBUFFEREXECOFFSET6 Task buffer 6 execute offset register 0x78 32 read-only 0x0 0x0 EXECOFFSETTB6 Task buffer 6 execution offset in multiple of 32-bit words. Offset of the scheduling instruction that is to be executed next. Instruction at address = AddressTB6 has offset zero. [15:0] read-only TASKBUFFEREXECOFFSET7 Task buffer 7 execute offset register 0x7C 32 read-only 0x0 0x0 EXECOFFSETTB7 Task buffer 7 execution offset in multiple of 32-bit words. Offset of the scheduling instruction that is to be executed next. Instruction at address = AddressTB7 has offset zero. [15:0] read-only STATUS Status register 0x80 32 read-only 0x0 0x0 TASKBUFFERDONE Each bit corresponds to one task buffer. '1' means that the ExecOffset equals to the StopOffset [7:0] read-only TASKBUFFERSYNC Each bit corresponds to one task buffer. '1' means that the scheduling of corresponding TB is blocked until some SW or HW state is reached. [15:8] read-only SCHEDULERACTIVETB Task buffer being executed in scheduler. If scheduler is in idle state, the value of this field is not valid. [18:16] read-only SCHEDULERIDLE Scheduler is not processing any instructions and there are no outstanding AXI transactions. [19:19] read-only FETCHEDACTIVETB Task buffer being fetch last in programmer. If programmer is in idle state, the value of this field is not valid. [22:20] read-only REQUESTEDAXITRANSACTIONS There are some outstanding axi transactions that have been requested but are not received yet. [23:23] read-only PROGRAMMERSTATE Execution state of programmer [25:24] read-only IDLE When all fetched instructions have been executed and there are no functions scheduled for the execution 0 SYNC During execution of the SYNC instruction 1 ACTIVE Execution of instructions 2 AXI_WAIT There is function scheduled for the execution, but the internal instruction buffer is empty. 3 CMDSEQIDLE CmdSeq is not processing any instructions and there are no outstanding AXI transactions. [26:26] read-only ERRORCODE Error code register, each field of this register is one bit wide and corresponds to an error event. If the value of this register is zero, than there are no errors. 0x84 32 read-only 0x0 0x0 ERRORSCHEDULEROPCODE Opcode error in scheduler [0:0] read-only ERRORPROGRAMMEROPCODE Opcode error in programmer [1:1] read-only ERROREXECUTIONOFFSET Execution offset is outside of the task buffer [2:2] read-only ERRORSTOPOFFSETWITHININSTRUCTION Stop offset is within instruction in scheduler [3:3] read-only ERRORAXISLV AXI slave error has been occurred. SchedulerAddress and ProgrammerAddress have to be evaluated [4:4] read-only ERRORAXIDEC AXI decoder error has been occurred. SchedulerAddress and ProgrammerAddress have to be evaluated [5:5] read-only ERRORREGID Error accessing an register via id that is not bound to any GPR or SPR register [6:6] read-only ERRORDELAYEDSYNC SYNC is following delayed SYNC in Scheduler [7:7] read-only ERRORSTOPOFFSETOUTSIDETB Stop offset value is bigger than or equals to task buffer size. If however both are zero, no error should be raised. [8:8] read-only ERRORFUNCTIONOFFSET Function offset provided by the EXEC instruction is outside of task buffer [9:9] read-only DESIGNCONFIGURATION Provides HW specific information. 0x88 32 read-only 0x0 0x0 BUFFERDEPTH The size of the buffer between the Scheduler and the Programmer. [3:0] read-only BUFFERDEPTHSCHEDULER The buffer (axi decouple fifo) size inside of the scheduler. [15:8] read-only BUFFERDEPTHPROGRAMMER The buffer (axi decouple fifo) size inside of the programmer. [23:16] read-only SCHEDULERADDRESS Last fetched address of scheduler. 0x8C 32 read-only 0x0 0x0 SCHEDULERADDRESS Last fetched address of scheduler [31:0] read-only PROGRAMMERADDRESS Last fetched address of programmer. 0x90 32 read-only 0x0 0x0 PROGRAMMERADDRESS Last fetched address of programmer [31:0] read-only GPR0 General purpose Register. (Internal register with id = 0) 0x94 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER0 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR1 General purpose Register. (Internal register with id = 1) 0x98 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER1 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR2 General purpose Register. (Internal register with id = 2) 0x9C 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER2 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR3 General purpose Register. (Internal register with id = 3) 0xA0 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER3 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR4 General purpose Register. (Internal register with id = 4) 0xA4 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER4 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR5 General purpose Register. (Internal register with id = 5) 0xA8 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER5 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR6 General purpose Register. (Internal register with id = 6) 0xAC 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER6 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR7 General purpose Register. (Internal register with id = 7) 0xB0 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER7 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR8 General purpose Register. (Internal register with id = 8) 0xB4 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER8 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR9 General purpose Register. (Internal register with id = 9) 0xB8 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER9 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR10 General purpose Register. (Internal register with id = 10) 0xBC 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER10 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR11 General purpose Register. (Internal register with id = 11) 0xC0 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER11 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR12 General purpose Register. (Internal register with id = 12) 0xC4 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER12 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR13 General purpose Register. (Internal register with id = 13) 0xC8 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER13 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR14 General purpose Register. (Internal register with id = 14) 0xCC 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER14 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only GPR15 General purpose Register. (Internal register with id = 15) 0xD0 32 read-only 0x0 0x0 GENERALPURPOSEREGISTER15 General Purpose Register used internally for CmdSeq and for synchronization with SW. [31:0] read-only SPR0 Special Purpose Register. (Internal register with id = 16) 0xD4 32 read-only 0x0 0x0 LINECOUNTERTB0 Holds the scheduled line of the frame that is being executed in TB0. The value of this register is routed outside CmdSeq. [15:0] read-only SPR1 Special Purpose Register (internal register with id = 17) 0xD8 32 read-only 0x0 0x0 LINECOUNTERTB1 Holds the scheduled line of the frame that is being executed in TB1. The value of this register is routed outside CmdSeq. [15:0] read-only SPR2 Special Purpose Register (internal register with id = 18) 0xDC 32 read-only 0x0 0x0 LINECOUNTERTB2 Holds the scheduled line of the frame that is being executed in TB2. The value of this register is routed outside CmdSeq. [15:0] read-only SPR3 Special Purpose Register (internal register with id = 19) 0xE0 32 read-only 0x0 0x0 LINECOUNTERTB3 Holds the scheduled line of the frame that is being executed in TB3. The value of this register is routed outside CmdSeq. [15:0] read-only SPR4 Special Purpose Register (internal register with id = 20) 0xE4 32 read-only 0x0 0x0 LINECOUNTERTB4 Holds the scheduled line of the frame that is being executed in TB4. The value of this register is routed outside CmdSeq. [15:0] read-only SPR5 Special Purpose Register (internal register with id = 21) 0xE8 32 read-only 0x0 0x0 LINECOUNTERTB5 Holds the scheduled line of the frame that is being executed in TB5. The value of this register is routed outside CmdSeq. [15:0] read-only SPR6 Special Purpose Register (internal register with id = 22) 0xEC 32 read-only 0x0 0x0 LINECOUNTERTB6 Holds the scheduled line of the frame that is being executed in TB6. The value of this register is routed outside CmdSeq. [15:0] read-only SPR7 Special Purpose Register (internal register with id = 23) 0xF0 32 read-only 0x0 0x0 LINECOUNTERTB7 Holds the scheduled line of the frame that is being executed in TB7. The value of this register is routed outside CmdSeq. [15:0] read-only BLITENG Blit Engine 0x00020000 BLITENGCFG Top-Level 0x00000000 STATICCONTROL Static control register. 0x0 32 read-write 0x0 0x1F31 SHDEN Enable shadowing of all RWS type registers (0=write_through, 1=shadowed). For LBO this ShdEn and ShdEn fields of all modules inside Bliteng have to be 1. [0:0] read-write LRSTATUSSELECT Select pipeline from which to access status register information in line-rendering mode. [5:4] read-write BLITENGUTILIZATIONMEASUREMENTEN Enable utilization measurement of LBO render mode. Corresponding registers are IBOCounter and LBOCounter. [8:8] read-write LBOUTILIZATIONMEASUREMENTEN Enable utilization measurement of LBO render mode. Corresponding registers are LBOAllFetchesActiveCounter and LBOWaitBlitEngRessourcesCounter. [9:9] read-write TBUTILIZATIONMEASUREMENTEN Enable utilization measurement of CmdSeq task buffers (active time for each TB). Corresponding registers are TB[x]UtilizationCounter. [10:10] read-write LBOSOURCEPIXELMEASUREMENTEN Enable source pixel counting for LBO. Corresponding registers are LBOSourcePixelRGBACounter and LBOSourcePixelAlphaCounter. [11:11] read-write DESTINATIONPIXELMEASUREMENTEN Enable destination pixel counting for LBO and LBO. Corresponding registers are LBODestinationPixelCounter and IBODestinationPixelCounter. [12:12] read-write TASKSETUP Task configuration register. 0x4 32 read-write 0x0 0x717 TASKSELECT Select task bank for operation status registers (ypos, ...). [2:0] read-write RENDERMODE Blit engine operation mode. [4:4] read-write FRAMERENDERING Frame rendering mode (framebuffer). 0 LINERENDERING Line rendering mode (linebuffer). 1 PROXYSELECT Proxy to use for the next operation [10:8] read-write OFF Proxy disabled. 0 FETCHLBH0 Proxy connected to FETCHLBH0. 1 FETCHLBH1 Proxy connected to FETCHLBH1. 2 FETCHLBH2 Proxy connected to FETCHLBH2. 3 FETCHLBH3 Proxy connected to FETCHLBH3. 4 FETCHLBH4 Proxy connected to FETCHLBH4. 5 LRFRAMEDIMENSION Dimension of final frame in memory. 0x8 32 read-write 0xF00140 0x3FFF3FFF TOTALWIDTH Frame width (programmed with -1). [13:0] read-write TOTALHEIGHT Frame height (programmed with -1). [29:16] read-write OPERATIONSETUP Setup for rendering operation. 0xC 32 read-write 0x0 0xFFFF33 DESTINATIONSELECT Select operation for destination buffer. In IBO the buffer is provided via the FETCHDST in LBO the buffer is provided via internal RGBA slice buffer. [1:0] read-write OFF Destination buffer is not read, used for FILL or COPY operations. 0 ROP Destination is connected to raster operation block (tertary). Only possible in IBO mode. 1 BLEND Destination is connected to blend operation block. 2 FETCHMASK Destination fetch is connected to the external input of the fetch MASK, for planar YUV. Only possible in IBO mode. 3 MASKSELECT Select operation for mask buffer. In IBO the buffer is provided via the FETCHMASK; in LBO the buffer is provided via internal ALPHA slice buffer. If the value of both fields this and DestinationSelect is BLEND, OFF is used for this field. [5:4] read-write OFF Mask buffer is not read. 0 ROP Mask is connected to raster operation block (secondary). Only possible in IBO mode. 1 BLEND Mask is connected to blend operation block. Only possible in LBO mode. 2 FETCHSRC Mask is connected to the fetch SRC. 3 BUFFERSELECT Line buffer to render into. This field is ignored for IBO render mode. [8:8] read-write RGBA RGBA buffer. 0 MASK MASK buffer. 1 ENABLEROP Set 1 to enable ROP module. This field is ignored for LBO render mode. [9:9] read-write ENABLECLUT Set 1 to enable CLUT. This field is ignored for LBO render mode. [10:10] read-write ENABLEMATRIX Set 1 to enable matrix. [11:11] read-write ENABLEGPSCALER Set 1 enable GPScaler. This field is ignored for LBO render mode. [12:12] read-write ENABLEBLITBLEND Set 1 enable the BlitBlend module. If this field is set [13:13] read-write CONSTANTCOLORFILL If this field is set, the selected destination (BufferSelect) will be filled with constant color (ConstantColorRed, ConstantColorGreen, ConstantColorBlue, ConstantAlpha) not using any fetch pipeline. Only possible in LBO mode. [14:14] read-write USECOPS Cops are used for the next fetch operation. If the value is zero, CopsAddress is not evaluated. Only possible in LBO mode. [15:15] read-write COPSADDRESS Address to use in Current Object Processing State (COPS) memory (required for decode operations). Only possible in LBO mode. [23:16] read-write LROBJECTDIMENSION Dimension of object. Only possible in LBO mode 0x10 32 read-write 0xF00140 0x3FFF3FFF OBJECTWIDTH Object width (programmed with -1). [13:0] read-write OBJECTHEIGHT Object height (programmed with -1). [29:16] read-write LROBJECTPOSITION Position of current object in frame coordinate system. Only possible in LBO mode 0x14 32 read-write 0x0 0x3FFF3FFF OBJECTOFFSETX Object position in x direction (start at 0). [13:0] read-write OBJECTOFFSETY Object position in y direction (start at 0). [29:16] read-write LRCONSTALPHA Constant alpha used to fill buffer w/o fetch unit. Has affect only if ConstantColorFill is set. Only possible in LBO mode. 0x18 32 read-write 0x0 0xFF CONSTANTALPHA Alpha to be filled to RGBA or Alpha buffer. [7:0] read-write LRCONSTRGB Constant color used to fill buffer w/o fetch unit. Has affect only if ConstantColorFill is set and BufferSelect==RGBA. Only possible in LBO mode 0x1C 32 read-write 0x0 0x3FFFFFFF CONSTANTCOLORRED Constant red color to be filled into RGBA buffer. [9:0] read-write CONSTANTCOLORGREEN Constant green color to be filled into RGBA buffer. [19:10] read-write CONSTANTCOLORBLUE Constant blue color to be filled into RGBA buffer. [29:20] read-write SYNCIDREQUEST0 Sync ID request register. 0x20 32 read-write 0x0 0xFFFFFFFF SYNCIDREQUEST0 Sync ID requested by SW. Will be loaded into SyncIdStatus0 if SyncIdTrigger[0] is set and if/once store operation is done. [31:0] read-write SYNCIDREQUEST1 Sync ID request register. 0x24 32 read-write 0x0 0xFFFFFFFF SYNCIDREQUEST1 Sync ID requested by SW. Will be loaded into SyncIdStatus1 if SyncIdTrigger[1] is set and if/once store operation is done. [31:0] read-write SYNCIDREQUEST2 Sync ID request register. 0x28 32 read-write 0x0 0xFFFFFFFF SYNCIDREQUEST2 Sync ID requested by SW. Will be loaded into SyncIdStatus2 if SyncIdTrigger[2] is set and if/once store operation is done. [31:0] read-write SYNCIDREQUEST3 Sync ID request register. 0x2C 32 read-write 0x0 0xFFFFFFFF SYNCIDREQUEST3 Sync ID requested by SW. Will be loaded into SyncIdStatus3 if SyncIdTrigger[3] is set and if/once store operation is done. [31:0] read-write SYNCIDREQUEST4 Sync ID request register. 0x30 32 read-write 0x0 0xFFFFFFFF SYNCIDREQUEST4 Sync ID requested by SW. Will be loaded into SyncIdStatus4 if SyncIdTrigger[4] is set and if/once store operation is done. [31:0] read-write SYNCIDREQUEST5 Sync ID request register. 0x34 32 read-write 0x0 0xFFFFFFFF SYNCIDREQUEST5 Sync ID requested by SW. Will be loaded into SyncIdStatus5 if SyncIdTrigger[5] is set and if/once store operation is done. [31:0] read-write SYNCIDREQUEST6 Sync ID request register. 0x38 32 read-write 0x0 0xFFFFFFFF SYNCIDREQUEST6 Sync ID requested by SW. Will be loaded into SyncIdStatus6 if SyncIdTrigger[6] is set and if/once store operation is done. [31:0] read-write SYNCIDREQUEST7 Sync ID request register. 0x3C 32 read-write 0x0 0xFFFFFFFF SYNCIDREQUEST7 Sync ID requested by SW. Will be loaded into SyncIdStatus7 if SyncIdTrigger[7] is set and if/once store operation is done. [31:0] read-write SYNCCONTROL Triggers interrupts for sequence complete of specific TB of global sequence complete interrupt. 0x40 32 write-only 0x0 0x0 SYNCIDTRIGGER Trigger SyncIdComplete[0:7] and load SyncIdRequest[0:7] into SyncIdStatus[0:7]. Is executed after store operation is completed or no operation is active on the corresponding TB. [7:0] write-only SEQUENCECOMPLETE Trigger SeqComplete interrupt if BlitEng is idle or the last operation has been completed. [8:8] write-only LINERENDERINGCONTROL Line rendering operation control register. 0x44 32 write-only 0x0 0x0 LRSTART Start next source to linebuffer operation. [0:0] write-only CLEARTASK Clear related registers (ypos, perf) of corresponding TB. Each bit corresponds to one TB. [15:8] write-only PERFORMANCEMEASUREMENTCONTROL Control of the performance and utilitzation measurements. 0x48 32 write-only 0x0 0x0 SAVEANDRESETMEASUREMENTS All performance and utilization counters are implemented internally. Writing one to this field provides all measured values to corresponding configurations registers and resets the internal counters. [0:0] write-only SYNCIDSTATUS0 Sync ID Status register for task 0. 0x4C 32 read-only 0x0 0x0 SYNCIDCOMPLETE0 Latest ID completed as requested by SyncIdRequest and SyncIdTrigger with TaskSelect = 0. [31:0] read-only SYNCIDSTATUS1 Sync ID Status register for task 1. 0x50 32 read-only 0x0 0x0 SYNCIDCOMPLETE1 Latest ID completed as requested by SyncIdRequest and SyncIdTrigger with TaskSelect = 1. [31:0] read-only SYNCIDSTATUS2 Sync ID Status register for task 2. 0x54 32 read-only 0x0 0x0 SYNCIDCOMPLETE2 Latest ID completed as requested by SyncIdRequest and SyncIdTrigger with TaskSelect = 2. [31:0] read-only SYNCIDSTATUS3 Sync ID Status register for task 3. 0x58 32 read-only 0x0 0x0 SYNCIDCOMPLETE3 Latest ID completed as requested by SyncIdRequest and SyncIdTrigger with TaskSelect = 3. [31:0] read-only SYNCIDSTATUS4 Sync ID Status register for task 4. 0x5C 32 read-only 0x0 0x0 SYNCIDCOMPLETE4 Latest ID completed as requested by SyncIdRequest and SyncIdTrigger with TaskSelect = 4. [31:0] read-only SYNCIDSTATUS5 Sync ID Status register for task 5. 0x60 32 read-only 0x0 0x0 SYNCIDCOMPLETE5 Latest ID completed as requested by SyncIdRequest and SyncIdTrigger with TaskSelect = 5. [31:0] read-only SYNCIDSTATUS6 Sync ID Status register for task 6. 0x64 32 read-only 0x0 0x0 SYNCIDCOMPLETE6 Latest ID completed as requested by SyncIdRequest and SyncIdTrigger with TaskSelect = 6. [31:0] read-only SYNCIDSTATUS7 Sync ID Status register for task 7. 0x68 32 read-only 0x0 0x0 SYNCIDCOMPLETE7 Latest ID completed as requested by SyncIdRequest and SyncIdTrigger with TaskSelect = 7. [31:0] read-only DESIGNATTRIBUTES0 This register contains attributes of Bliteng. They are not parameters since they cannot be easily changed, however here we still have them to provide some static status on design. 0x6C 32 read-only 0x63F0207 0x3FFF070F SLICEHEIGHT Returns the slice height mode minus one. [3:0] read-only PROCESSINGPIPELINES Returns the maximum number of pixel processing pipelines LBO mode minus one. [10:8] read-only SLICEWIDTH Returns the maximum width that can be rendered in LBO mode minus one. [29:16] read-only DESIGNATTRIBUTES1 This register contains attributes of Bliteng. They are not parameters since they cannot be easily changed, however here we still have them to provide some static status on design. 0x70 32 read-only 0x63F 0x3FFF GPSCALERWIDTH Returns the maximum width that can be rendered in LBO mode minus one. [13:0] read-only CLOCKCOUNTER One of Clock Counter registers. 0x74 32 read-only 0x0 0x0 CLOCKCOUNTER The internal clock counter is incremented with each 16th clock cycle if any of the measurements are activated. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only CLOCKCOUNTEROVERFLOW One of Clock Counter registers. 0x78 32 read-only 0x0 0x0 CLOCKCOUNTEROVERFLOW This bit is set if ClockCounter overflows. [0:0] read-only IBOACTIVECOUNTER One of BlitEng Utilization Measurement registers. 0x7C 32 read-only 0x0 0x0 IBOACTIVECOUNTER The internal LBO counter is incremented with each 16th clock cycle when BlitEng is executing IBO operation and when BlitEngUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only LBOACTIVECOUNTER One of BlitEng Utilization Measurement registers. 0x80 32 read-only 0x0 0x0 LBOACTIVECOUNTER The internal LBO counter is incremented with each 16th clock cycle when BlitEng is executing LBO operation and when BlitEngUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only LBOALLFETCHESACTIVECOUNTER One of the LBO utilization measurement registers. 0x84 32 read-only 0x0 0x0 LBOALLFETCHESACTIVECOUNTER The internal counter is incremented with each 16th clock when all source fetch pipelines are active. Only active in LBO and when LBOUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only LBOWAITBLITENGRESSOURCESCOUNTER One of the LBO utilization measurement registers. 0x88 32 read-only 0x0 0x0 LBOWAITBLITENGRESSOURCESCOUNTER The internal counter is incremented with each 16th clock when the operation has been triggered but is waiting for BlitEng ressources. Only active in LBO and when LBOUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only TB0ACTIVECOUNTER One of the TB utilization measurement registers. Since TB operations may be overlapping the sum of all TB utilization measurement registers may be higher than clock counter 0x8C 32 read-only 0x0 0x0 TB0ACTIVECOUNTER The internal counter is incremented with each 16th clock when there is any ongoing blit operation programmed via TB0. Only active when TBUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only TB1ACTIVECOUNTER One of the TB utilization measurement registers. Since TB operations may be overlapping the sum of all TB utilization measurement registers may be higher than clock counter 0x90 32 read-only 0x0 0x0 TB1ACTIVECOUNTER The internal counter is incremented with each 16th clock when there is any ongoing blit operation programmed via TB1. Only active when TBUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only TB2ACTIVECOUNTER One of the TB utilization measurement registers. Since TB operations may be overlapping the sum of all TB utilization measurement registers may be higher than clock counter 0x94 32 read-only 0x0 0x0 TB2ACTIVECOUNTER The internal counter is incremented with each 16th clock when there is any ongoing blit operation programmed via TB2. Only active when TBUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only TB3ACTIVECOUNTER One of the TB utilization measurement registers. Since TB operations may be overlapping the sum of all TB utilization measurement registers may be higher than clock counter 0x98 32 read-only 0x0 0x0 TB3ACTIVECOUNTER The internal counter is incremented with each 16th clock when there is any ongoing blit operation programmed via TB3. Only active when TBUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only TB4ACTIVECOUNTER One of the TB utilization measurement registers. Since TB operations may be overlapping the sum of all TB utilization measurement registers may be higher than clock counter 0x9C 32 read-only 0x0 0x0 TB4ACTIVECOUNTER The internal counter is incremented with each 16th clock when there is any ongoing blit operation programmed via TB4. Only active when TBUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only TB5ACTIVECOUNTER One of the TB utilization measurement registers. Since TB operations may be overlapping the sum of all TB utilization measurement registers may be higher than clock counter 0xA0 32 read-only 0x0 0x0 TB5ACTIVECOUNTER The internal counter is incremented with each 16th clock when there is any ongoing blit operation programmed via TB5. Only active when TBUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only TB6ACTIVECOUNTER One of the TB utilization measurement registers. Since TB operations may be overlapping the sum of all TB utilization measurement registers may be higher than clock counter 0xA4 32 read-only 0x0 0x0 TB6ACTIVECOUNTER The internal counter is incremented with each 16th clock when there is any ongoing blit operation programmed via TB6. Only active when TBUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only TB7ACTIVECOUNTER One of the TB utilization measurement registers. Since TB operations may be overlapping the sum of all TB utilization measurement registers may be higher than clock counter 0xA8 32 read-only 0x0 0x0 TB7ACTIVECOUNTER The internal counter is incremented with each 16th clock when there is any ongoing blit operation programmed via TB7. Only active when TBUtilizationMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only LBOSOURCEPIXELRGBACOUNTER RGBA source pixel counter for LBO mode 0xAC 32 read-only 0x0 0x0 LBOSOURCEPIXELRGBACOUNTER Provides the number of processed source RGBA pixels which should be multiplied by 256. Only active in LBO and when LBOSourcePixelMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only LBOSOURCEPIXELALPHACOUNTER Alpha source pixel counter for LBO mode 0xB0 32 read-only 0x0 0x0 LBOSOURCEPIXELALPHACOUNTER Provides the number of processed source alpha pixels which should be multiplied by 256. Only active in LBO and when LBOSourcePixelMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only LBODESTINATIONPIXELCOUNTER Destination pixel counter for LBO mode 0xB4 32 read-only 0x0 0x0 LBODESTINATIONPIXELCOUNTER Provides the number of processed destination pixels which should be multiplied by 32. In the case of odd width this counter counts one more pixel per line compared to the actual number of pixels. Only active in LBO and when DestinationPixelMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only IBODESTINATIONPIXELCOUNTER Destination pixel counter for IBO mode 0xB8 32 read-only 0x0 0x0 IBODESTINATIONPIXELCOUNTER Provides the number of processed destination pixels which should be multiplied by 16. Only active in IBO and when DestinationPixelMeasurementEn is set. This field is updated with SaveAndResetMeasurements pulse and internal counter is reset. [31:0] read-only LBHLINK0BUFFERCONFIG0 Line buffer configuration register 0. 0x200 32 read-write 0x0 0xF11 LBHLINK0ENABLE Activates the line-buffer handshake, i.e. will stall the store or the display fetch upon respective condition. [0:0] read-write LBHLINK0SIZEENABLE Activates the ring buffer usage. This signal will be provided to the fetch and the store. [4:4] read-write LBHLINK0BUFLINES The number of lines in the line buffer in power of two. Max supported number of lines in ringbuffer is 16384 (14pow2=16384). Programming 15 results also in 16384 lines. [11:8] read-write LBHLINK0BUFFERCONFIG1 Line buffer configuration register 1. 0x204 32 read-write 0x0 0x3FFF3FFF LBHLINK0FRAMELINES Height of the frame in number of lines. The height must be identical to the related Blit and Composition Engine setups. [13:0] read-write LBHLINK0KEEPLINES Number of lines to keep in the line buffer even if the display fetch is already beyond this line. Required for re-sampling operations that span over several input lines. [29:16] read-write LBHLINK0BUFFERSTATUS0 Buffer status register 0 for the line buffer handshake. Writing to this register has no effect, reading provides the value and simultaneously resets the internal register. The value provided after the first read or if LBH is inactive is not valid. 0x208 32 read-write 0x0 0x7FFF7FFF LBHLINK0MAXFREELINES The maximal number of free lines in the line buffer that can be scheduled by CmdSeq. [14:0] read-write LBHLINK0MAXFREELINESSTORE The maximal number of free lines in the line buffer that can be written by the store. [30:16] read-write LBHLINK0BUFFERSTATUS1 Buffer status register 1 for the line buffer handshake. 0x20C 32 read-only 0x10001 0x17FFF LBHLINK0AVAILABLELINES The number of lines in the line buffer that the store can write. [14:0] read-only LBHLINK0SAMEFRAME This status bit indicates if the fetch and the store are processing the same frame. If this bit is zero the store has already switched to the next frame [16:16] read-only LBHLINK0BUFFERSTATUS3 Buffer status register 3 for the line buffer handshake. 0x214 32 read-only 0x0 0x0 LBHLINK0FETCHLINE This field describes the line currently read by the display fetch. [13:0] read-only LBHLINK0STORELINE This field describes the line currently written by the store. [29:16] read-only LBHLINK0BUFFERSTATUS4 Buffer status register 4 for the line buffer handshake. 0x218 32 read-only 0x0 0x0 LBHLINK0FETCHSTOPLINE This field describes the stopline of the display fetch. [14:0] read-only LBHLINK0STORESTOPLINE This field describes the stopline of the store. [30:16] read-only LBHLINK1BUFFERCONFIG0 Line buffer configuration register 0. 0x240 32 read-write 0x0 0xF11 LBHLINK1ENABLE Activates the line-buffer handshake, i.e. will stall the store or the display fetch upon respective condition. [0:0] read-write LBHLINK1SIZEENABLE Activates the ring buffer usage. This signal will be provided to the fetch and the store. [4:4] read-write LBHLINK1BUFLINES The number of lines in the line buffer in power of two. Max supported number of lines in ringbuffer is 16384 (14pow2=16384). Programming 15 results also in 16384 lines. [11:8] read-write LBHLINK1BUFFERCONFIG1 Line buffer configuration register 1. 0x244 32 read-write 0x0 0x3FFF3FFF LBHLINK1FRAMELINES Height of the frame in number of lines. The height must be identical to the related Blit and Composition Engine setups. [13:0] read-write LBHLINK1KEEPLINES Number of lines to keep in the line buffer even if the display fetch is already beyond this line. Required for re-sampling operations that span over several input lines. [29:16] read-write LBHLINK1BUFFERSTATUS0 Buffer status register 0 for the line buffer handshake. Writing to this register has no effect, reading provides the value and simultaneously resets the internal register. The value provided after the first read or if LBH is inactive is not valid. 0x248 32 read-write 0x0 0x7FFF7FFF LBHLINK1MAXFREELINES The maximal number of free lines in the line buffer that can be scheduled by CmdSeq. [14:0] read-write LBHLINK1MAXFREELINESSTORE The maximal number of free lines in the line buffer that can be written by the store. [30:16] read-write LBHLINK1BUFFERSTATUS1 Buffer status register 1 for the line buffer handshake. 0x24C 32 read-only 0x10001 0x17FFF LBHLINK1AVAILABLELINES The number of lines in the line buffer that the store can write. [14:0] read-only LBHLINK1SAMEFRAME This status bit indicates if the fetch and the store are processing the same frame. If this bit is zero the store has already switched to the next frame [16:16] read-only LBHLINK1BUFFERSTATUS3 Buffer status register 3 for the line buffer handshake. 0x254 32 read-only 0x0 0x0 LBHLINK1FETCHLINE This field describes the line currently read by the display fetch. [13:0] read-only LBHLINK1STORELINE This field describes the line currently written by the store. [29:16] read-only LBHLINK1BUFFERSTATUS4 Buffer status register 4 for the line buffer handshake. 0x258 32 read-only 0x0 0x0 LBHLINK1FETCHSTOPLINE This field describes the stopline of the display fetch. [14:0] read-only LBHLINK1STORESTOPLINE This field describes the stopline of the store. [30:16] read-only LBHLINK2BUFFERCONFIG0 Line buffer configuration register 0. 0x280 32 read-write 0x0 0xF11 LBHLINK2ENABLE Activates the line-buffer handshake, i.e. will stall the store or the display fetch upon respective condition. [0:0] read-write LBHLINK2SIZEENABLE Activates the ring buffer usage. This signal will be provided to the fetch and the store. [4:4] read-write LBHLINK2BUFLINES The number of lines in the line buffer in power of two. Max supported number of lines in ringbuffer is 16384 (14pow2=16384). Programming 15 results also in 16384 lines. [11:8] read-write LBHLINK2BUFFERCONFIG1 Line buffer configuration register 1. 0x284 32 read-write 0x0 0x3FFF3FFF LBHLINK2FRAMELINES Height of the frame in number of lines. The height must be identical to the related Blit and Composition Engine setups. [13:0] read-write LBHLINK2KEEPLINES Number of lines to keep in the line buffer even if the display fetch is already beyond this line. Required for re-sampling operations that span over several input lines. [29:16] read-write LBHLINK2BUFFERSTATUS0 Buffer status register 0 for the line buffer handshake. Writing to this register has no effect, reading provides the value and simultaneously resets the internal register. The value provided after the first read or if LBH is inactive is not valid. 0x288 32 read-write 0x0 0x7FFF7FFF LBHLINK2MAXFREELINES The maximal number of free lines in the line buffer that can be scheduled by CmdSeq. [14:0] read-write LBHLINK2MAXFREELINESSTORE The maximal number of free lines in the line buffer that can be written by the store. [30:16] read-write LBHLINK2BUFFERSTATUS1 Buffer status register 1 for the line buffer handshake. 0x28C 32 read-only 0x10001 0x17FFF LBHLINK2AVAILABLELINES The number of lines in the line buffer that the store can write. [14:0] read-only LBHLINK2SAMEFRAME This status bit indicates if the fetch and the store are processing the same frame. If this bit is zero the store has already switched to the next frame [16:16] read-only LBHLINK2BUFFERSTATUS3 Buffer status register 3 for the line buffer handshake. 0x294 32 read-only 0x0 0x0 LBHLINK2FETCHLINE This field describes the line currently read by the display fetch. [13:0] read-only LBHLINK2STORELINE This field describes the line currently written by the store. [29:16] read-only LBHLINK2BUFFERSTATUS4 Buffer status register 4 for the line buffer handshake. 0x298 32 read-only 0x0 0x0 LBHLINK2FETCHSTOPLINE This field describes the stopline of the display fetch. [14:0] read-only LBHLINK2STORESTOPLINE This field describes the stopline of the store. [30:16] read-only LBHLINK3BUFFERCONFIG0 Line buffer configuration register 0. 0x2C0 32 read-write 0x0 0xF11 LBHLINK3ENABLE Activates the line-buffer handshake, i.e. will stall the store or the display fetch upon respective condition. [0:0] read-write LBHLINK3SIZEENABLE Activates the ring buffer usage. This signal will be provided to the fetch and the store. [4:4] read-write LBHLINK3BUFLINES The number of lines in the line buffer in power of two. Max supported number of lines in ringbuffer is 16384 (14pow2=16384). Programming 15 results also in 16384 lines. [11:8] read-write LBHLINK3BUFFERCONFIG1 Line buffer configuration register 1. 0x2C4 32 read-write 0x0 0x3FFF3FFF LBHLINK3FRAMELINES Height of the frame in number of lines. The height must be identical to the related Blit and Composition Engine setups. [13:0] read-write LBHLINK3KEEPLINES Number of lines to keep in the line buffer even if the display fetch is already beyond this line. Required for re-sampling operations that span over several input lines. [29:16] read-write LBHLINK3BUFFERSTATUS0 Buffer status register 0 for the line buffer handshake. Writing to this register has no effect, reading provides the value and simultaneously resets the internal register. The value provided after the first read or if LBH is inactive is not valid. 0x2C8 32 read-write 0x0 0x7FFF7FFF LBHLINK3MAXFREELINES The maximal number of free lines in the line buffer that can be scheduled by CmdSeq. [14:0] read-write LBHLINK3MAXFREELINESSTORE The maximal number of free lines in the line buffer that can be written by the store. [30:16] read-write LBHLINK3BUFFERSTATUS1 Buffer status register 1 for the line buffer handshake. 0x2CC 32 read-only 0x10001 0x17FFF LBHLINK3AVAILABLELINES The number of lines in the line buffer that the store can write. [14:0] read-only LBHLINK3SAMEFRAME This status bit indicates if the fetch and the store are processing the same frame. If this bit is zero the store has already switched to the next frame [16:16] read-only LBHLINK3BUFFERSTATUS3 Buffer status register 3 for the line buffer handshake. 0x2D4 32 read-only 0x0 0x0 LBHLINK3FETCHLINE This field describes the line currently read by the display fetch. [13:0] read-only LBHLINK3STORELINE This field describes the line currently written by the store. [29:16] read-only LBHLINK3BUFFERSTATUS4 Buffer status register 4 for the line buffer handshake. 0x2D8 32 read-only 0x0 0x0 LBHLINK3FETCHSTOPLINE This field describes the stopline of the display fetch. [14:0] read-only LBHLINK3STORESTOPLINE This field describes the stopline of the store. [30:16] read-only LBHLINK4BUFFERCONFIG0 Line buffer configuration register 0. 0x300 32 read-write 0x0 0xF11 LBHLINK4ENABLE Activates the line-buffer handshake, i.e. will stall the store or the display fetch upon respective condition. [0:0] read-write LBHLINK4SIZEENABLE Activates the ring buffer usage. This signal will be provided to the fetch and the store. [4:4] read-write LBHLINK4BUFLINES The number of lines in the line buffer in power of two. Max supported number of lines in ringbuffer is 16384 (14pow2=16384). Programming 15 results also in 16384 lines. [11:8] read-write LBHLINK4BUFFERCONFIG1 Line buffer configuration register 1. 0x304 32 read-write 0x0 0x3FFF3FFF LBHLINK4FRAMELINES Height of the frame in number of lines. The height must be identical to the related Blit and Composition Engine setups. [13:0] read-write LBHLINK4KEEPLINES Number of lines to keep in the line buffer even if the display fetch is already beyond this line. Required for re-sampling operations that span over several input lines. [29:16] read-write LBHLINK4BUFFERSTATUS0 Buffer status register 0 for the line buffer handshake. Writing to this register has no effect, reading provides the value and simultaneously resets the internal register. The value provided after the first read or if LBH is inactive is not valid. 0x308 32 read-write 0x0 0x7FFF7FFF LBHLINK4MAXFREELINES The maximal number of free lines in the line buffer that can be scheduled by CmdSeq. [14:0] read-write LBHLINK4MAXFREELINESSTORE The maximal number of free lines in the line buffer that can be written by the store. [30:16] read-write LBHLINK4BUFFERSTATUS1 Buffer status register 1 for the line buffer handshake. 0x30C 32 read-only 0x10001 0x17FFF LBHLINK4AVAILABLELINES The number of lines in the line buffer that the store can write. [14:0] read-only LBHLINK4SAMEFRAME This status bit indicates if the fetch and the store are processing the same frame. If this bit is zero the store has already switched to the next frame [16:16] read-only LBHLINK4BUFFERSTATUS3 Buffer status register 3 for the line buffer handshake. 0x314 32 read-only 0x0 0x0 LBHLINK4FETCHLINE This field describes the line currently read by the display fetch. [13:0] read-only LBHLINK4STORELINE This field describes the line currently written by the store. [29:16] read-only LBHLINK4BUFFERSTATUS4 Buffer status register 4 for the line buffer handshake. 0x318 32 read-only 0x0 0x0 LBHLINK4FETCHSTOPLINE This field describes the stopline of the display fetch. [14:0] read-only LBHLINK4STORESTOPLINE This field describes the stopline of the store. [30:16] read-only 2048 4 PALETTE[%s] Shared Palette Memory. 0x2000 32 read-write 0x0 0x0 PALETTEENTRY Shared palette entry with 24-bit. Color format can be defined by Fetch configuration. [23:0] read-write FETCHSRC Fetch SRC 0x00004000 STATICCONTROL Common static control options. 0x0 32 read-write 0x0 0xFF0001 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 BASEADDRESS0 Source buffer base address of layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0xC 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x10 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x14 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x18 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x1C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x20 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x24 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x28 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x2C 32 read-write 0xB8000008 0xFFFF7FFF PALETTEENABLE0 Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower bits of the lookup index are read from memory (PaletteIdWidth0), upper bits are set to index of this layer. Palette output is extended by upper bits of index word read from memory (e.g. to store alpha together with index). Result is mapped to color channels according to ColorComponentBits/Shift settings. [0:0] read-write TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE0 Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [3:3] read-write ALPHACONSTENABLE0 Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [4:4] read-write ALPHAMASKENABLE0 Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. [5:5] read-write ALPHATRANSENABLE0 Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [6:6] read-write RGBALPHASRCENABLE0 Value 1 enables source alpha (stored together with color component in the source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. [7:7] read-write RGBALPHACONSTENABLE0 Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. [8:8] read-write RGBALPHAMASKENABLE0 Value 1 enables mask alpha (read by another Fetch unit from a separate alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be enabled for this field to have effect. [9:9] read-write RGBALPHATRANSENABLE0 Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB0 When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no effect then. [11:11] read-write YUVCONVERSIONMODE0 Enables different kind of YUV to RGB conversions. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE0 Value 1 enables the stage to remove a gamma from RGB components. [14:14] read-write PALETTEOFFSET0 Palette may contain multiple areas. This offset shows to the starting position of the currently used area. [26:16] read-write PALETTEIDWIDTH0 Number minus one of least significant bits of pixel data read from the source buffer that are used as index value for color palette look-up. [29:27] read-write CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x30 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x34 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write WARPCONTROL Warping control options. 0x38 32 read-write 0x20 0x133F WARPBITSPERPIXEL Number of bits per pixel in the coordinate layer, which is read by another Fetch unit. Has to be 1, 2, 4, 8, 16 or 32. [5:0] read-write WARPCOORDINATEMODE Content of pixel data in the coordinate layer. [9:8] read-write PNT x and y (sample points). 0 D_PNT dx and dy (vectors between adjacent sample points). 1 DD_PNT ddx and ddy (deltas between adjacent vectors). 2 WARPSYMMETRICOFFSET Value 1 enables symmetric range for negative and positive coordinate values by adding an offset of +0.03125 internally to all coordinate input values. Recommended for small coordinate formats in DD_PNT mode. [12:12] read-write PERSPSTARTX Start value X for affine/perspective warping. 0x3C 32 read-write 0x0 0xFFFFFFFF PERSPSTARTX Start value for homogenous X coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPSTARTY Start value Y for affine/perspective warping. 0x40 32 read-write 0x0 0xFFFFFFFF PERSPSTARTY Start value for homogenous Y coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXX DeltaXX increment for affine/perspective warping. 0x44 32 read-write 0x3F800000 0xFFFFFFFF PERSPDELTAXX Increment of homogenous X coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYY DeltaYY increment for affine/perspective warping. 0x48 32 read-write 0x3F800000 0xFFFFFFFF PERSPDELTAYY Increment of homogenous Y coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXY DeltaXY increment for affine/perspective warping. 0x4C 32 read-write 0x0 0xFFFFFFFF PERSPDELTAXY Increment of homogenous Y coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYX DeltaYX increment for affine/perspective warping. 0x50 32 read-write 0x0 0xFFFFFFFF PERSPDELTAYX Increment of homogenous X coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPSTARTW Start value W for perspective warping. 0x54 32 read-write 0x3F800000 0xFFFFFFFF PERSPSTARTW Start value for homogenous W coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXW DeltaWX increment for perspective warping. 0x58 32 read-write 0x0 0xFFFFFFFF PERSPDELTAXW Increment of homogenous W coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYW DeltaWY increment for perspective warping. 0x5C 32 read-write 0x0 0xFFFFFFFF PERSPDELTAYW Increment of homogenous W coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write ARBSTARTX Start value X for arbitrary warping. 0x60 32 read-write 0x0 0x1FFFFF ARBSTARTX Start point for sample-point interpolation (X coordinate). (format is signed fix-point 16.5) [20:0] read-write ARBSTARTY Start value Y for arbitrary warping. 0x64 32 read-write 0x0 0x1FFFFF ARBSTARTY Start point for sample-point interpolation (Y coordinate). (format is signed fix-point 16.5) [20:0] read-write ARBDELTA Start values for delta incrementation of arbitrary warping. 0x68 32 read-write 0x0 0xFFFFFFFF ARBDELTAXX X coordinate of vector between first and second sample point. (format is signed fix-point 3.5) [7:0] read-write ARBDELTAXY Y coordinate of vector between first and second sample point. (format is signed fix-point 3.5) [15:8] read-write ARBDELTAYX X coordinate of vector between start and first sample point. (format is signed fix-point 3.5) [23:16] read-write ARBDELTAYY Y coordinate of vector between start and first sample point. (format is signed fix-point 3.5) [31:24] read-write FIRPOSITIONS FIR sequence control register. 0x6C 32 read-write 0xA965 0xFFFF FIR0POSITION Position of first pixel. [3:0] read-write FIR1POSITION Position of second pixel. [7:4] read-write FIR2POSITION Position of third pixel. [11:8] read-write FIR3POSITION Position of fourth pixel. [15:12] read-write FIRCOEFFICIENTS FIR coefficients register. 0x70 32 read-write 0x20 0xFFFFFFFF FIR0COEFFICIENT First coefficient. (format is signed fix-point 3.5) [7:0] read-write FIR1COEFFICIENT Second coefficient. (format is signed fix-point 3.5) [15:8] read-write FIR2COEFFICIENT Third coefficient. (format is signed fix-point 3.5) [23:16] read-write FIR3COEFFICIENT Fourth coefficient. (format is signed fix-point 3.5) [31:24] read-write DECODECONTROL Control options for RLAD decompression. 0x74 32 read-write 0x88880001 0xFFFF0003 COMPRESSIONMODE Algorithm that the encoder used for compression. [1:0] read-write RLAD Run-Length Adaptive Dithering (lossy compression). 0 RLAD_UNIFORM Run-Length Adaptive Dithering (lossy compression; uniform package size). 1 RLA Run-Length Adaptive (lossless compression). 2 RL Standard Run-Length. In contrary to other modes is in big endian format. 3 RLADCOMPBITSRED Maximum for average number of bits per compressed pixel for Red or Y (luma) channel. This must match the corresponding encoder setting. [19:16] read-write RLADCOMPBITSGREEN Maximum for average number of bits per compressed pixel for Green or U (chroma) channel. This must match the corresponding encoder setting. [23:20] read-write RLADCOMPBITSBLUE Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel. This must match the corresponding encoder setting. [27:24] read-write RLADCOMPBITSALPHA Maximum for average number of bits per compressed pixel for Alpha channel. This must match the corresponding encoder setting. [31:28] read-write SOURCEBUFFERLENGTH Source buffer length for compressed data. 0x78 32 read-write 0x0 0x1FFFFFFF RLEWORDS Number of 32-bit words minus one that are required to decode the run length encoded source buffer. [28:0] read-write CONTROL Shared common control settings for all layers. 0x7C 32 read-write 0x30010000 0x307100BF RASTERMODE Selects a method how to generate source buffer sample points. [2:0] read-write NORMAL [IBO only, for LBO use PERSPECTIVE with corresponding Geometry] First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. 0 DECODE [FetchDecode/FetchBlit only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). 1 ARBITRARY [FetchBlit/Warp only] Arbitrary warping (filter is active). Coordinates are read from frame input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. 2 PERSPECTIVE [FetchBlit only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. See also field Geometry to reduce coordinate amount. 3 YUV422 [FetchBlit/Decode only] Source buffer is packed YUV 422. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). All correllated window widths and horizontal offsets must be even. 4 INPUTSELECT Selects function for the frame input port. [4:3] read-write INACTIVE Not used. 0 COMPPACK Used for component packing (e.g. UV or source alpha buffer). 1 ALPHAMASK Used for RGB and alpha pre-multiply stage (mask alpha buffer). 2 COORDINATE Used for arbitrary warping (coordinate buffer). 3 YUV422UPSAMPLINGMODE Selects a method for horizontal up-sampling of YUV 422/420 input data. [5:5] read-write REPLICATE Replicate mode for interspersed samples (UV samples between Y samples). 0 INTERPOLATE Interpolate mode for coaligned samples (UV samples at Y sample positions). 1 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 FILTERMODE Use this to select between nearest and bilinear filtering. Only has an effect if rastermode == ARBITRARY or rastermode == PERSPECTIVE or rastermode == AFFINE. [22:20] read-write NEAREST Chooses pixel closest to sample point 0 BILINEAR Calculates result from 4 pixels closest to sample point 1 FIR2 FIR mode with 2 programmable pixel positions and coefficients 2 FIR4 FIR mode with 4 programmable pixel positions and coefficients 3 HOR_LINEAR Calculates result from 2 pixels closest to the sample point and on the same line 4 GEOMETRY Control the geomety settings (PerspStartX/Y/W and PerspDeltaXX/XY/YX/YY/XW/YW usage) for the raster mode PERSPECTIVE. [29:28] read-write TRANSLATE PerspStartX/Y are used. (PerspDeltaXY/YX/XW/YW are 0. PerspDeltaXX/YY and PerspStartW are 1.) 0 SCALE PerspStartX/Y and PerspDeltaXX/YY are used. (PerspDeltaXY/YX/XW/YW are 0. PerspStartW is 1.) 1 ROTATION PerspStartX/Y and PerspDeltaXX/XY/YX/YY are used. (PerspDeltaXW/YW are 0. PerspStartW is 1.) 2 PERSPECTIVE All values PerspStartX/Y/W and PerspDeltaXX/XY/YX/YY/XW/YW are used 3 CONTROLTRIGGER Shadow load trigger. 0x80 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x84 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x88 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 DECODERSTATUS Status information of the RLAD decoder. 0x8C 32 read-write 0x0 0x3 BUFFERTOOSMALL The buffer size given by RLEWords is too small. No complete output frame could be decoded. [0:0] read-write BUFFERTOOLARGE The buffer size given by RLEWords is too large. A complete output frame could be decoded, but more data was read than necessary. [1:1] read-write BURSTBUFFERPROPERTIES Burst buffer properties. 0x90 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only FETCHDST Fetch DST (only for IBO) 0x00004400 STATICCONTROL Common static control options. 0x0 32 read-write 0x0 0xFF0001 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 BASEADDRESS0 Source buffer base address of layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0xC 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x10 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x14 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x18 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x1C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x20 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x24 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x28 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x2C 32 read-write 0xB8000008 0xFFFF7FFF PALETTEENABLE0 Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower bits of the lookup index are read from memory (PaletteIdWidth0), upper bits are set to index of this layer. Palette output is extended by upper bits of index word read from memory (e.g. to store alpha together with index). Result is mapped to color channels according to ColorComponentBits/Shift settings. [0:0] read-write TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE0 Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [3:3] read-write ALPHACONSTENABLE0 Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [4:4] read-write ALPHAMASKENABLE0 Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. [5:5] read-write ALPHATRANSENABLE0 Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [6:6] read-write RGBALPHASRCENABLE0 Value 1 enables source alpha (stored together with color component in the source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. [7:7] read-write RGBALPHACONSTENABLE0 Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. [8:8] read-write RGBALPHAMASKENABLE0 Value 1 enables mask alpha (read by another Fetch unit from a separate alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be enabled for this field to have effect. [9:9] read-write RGBALPHATRANSENABLE0 Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB0 When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no effect then. [11:11] read-write YUVCONVERSIONMODE0 Enables different kind of YUV to RGB conversions. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE0 Value 1 enables the stage to remove a gamma from RGB components. [14:14] read-write PALETTEOFFSET0 Palette may contain multiple areas. This offset shows to the starting position of the currently used area. [26:16] read-write PALETTEIDWIDTH0 Number minus one of least significant bits of pixel data read from the source buffer that are used as index value for color palette look-up. [29:27] read-write CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x30 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x34 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write WARPCONTROL Warping control options. 0x38 32 read-write 0x20 0x133F WARPBITSPERPIXEL Number of bits per pixel in the coordinate layer, which is read by another Fetch unit. Has to be 1, 2, 4, 8, 16 or 32. [5:0] read-write WARPCOORDINATEMODE Content of pixel data in the coordinate layer. [9:8] read-write PNT x and y (sample points). 0 D_PNT dx and dy (vectors between adjacent sample points). 1 DD_PNT ddx and ddy (deltas between adjacent vectors). 2 WARPSYMMETRICOFFSET Value 1 enables symmetric range for negative and positive coordinate values by adding an offset of +0.03125 internally to all coordinate input values. Recommended for small coordinate formats in DD_PNT mode. [12:12] read-write PERSPSTARTX Start value X for affine/perspective warping. 0x3C 32 read-write 0x0 0xFFFFFFFF PERSPSTARTX Start value for homogenous X coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPSTARTY Start value Y for affine/perspective warping. 0x40 32 read-write 0x0 0xFFFFFFFF PERSPSTARTY Start value for homogenous Y coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXX DeltaXX increment for affine/perspective warping. 0x44 32 read-write 0x3F800000 0xFFFFFFFF PERSPDELTAXX Increment of homogenous X coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYY DeltaYY increment for affine/perspective warping. 0x48 32 read-write 0x3F800000 0xFFFFFFFF PERSPDELTAYY Increment of homogenous Y coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXY DeltaXY increment for affine/perspective warping. 0x4C 32 read-write 0x0 0xFFFFFFFF PERSPDELTAXY Increment of homogenous Y coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYX DeltaYX increment for affine/perspective warping. 0x50 32 read-write 0x0 0xFFFFFFFF PERSPDELTAYX Increment of homogenous X coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPSTARTW Start value W for perspective warping. 0x54 32 read-write 0x3F800000 0xFFFFFFFF PERSPSTARTW Start value for homogenous W coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXW DeltaWX increment for perspective warping. 0x58 32 read-write 0x0 0xFFFFFFFF PERSPDELTAXW Increment of homogenous W coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYW DeltaWY increment for perspective warping. 0x5C 32 read-write 0x0 0xFFFFFFFF PERSPDELTAYW Increment of homogenous W coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write ARBSTARTX Start value X for arbitrary warping. 0x60 32 read-write 0x0 0x1FFFFF ARBSTARTX Start point for sample-point interpolation (X coordinate). (format is signed fix-point 16.5) [20:0] read-write ARBSTARTY Start value Y for arbitrary warping. 0x64 32 read-write 0x0 0x1FFFFF ARBSTARTY Start point for sample-point interpolation (Y coordinate). (format is signed fix-point 16.5) [20:0] read-write ARBDELTA Start values for delta incrementation of arbitrary warping. 0x68 32 read-write 0x0 0xFFFFFFFF ARBDELTAXX X coordinate of vector between first and second sample point. (format is signed fix-point 3.5) [7:0] read-write ARBDELTAXY Y coordinate of vector between first and second sample point. (format is signed fix-point 3.5) [15:8] read-write ARBDELTAYX X coordinate of vector between start and first sample point. (format is signed fix-point 3.5) [23:16] read-write ARBDELTAYY Y coordinate of vector between start and first sample point. (format is signed fix-point 3.5) [31:24] read-write FIRPOSITIONS FIR sequence control register. 0x6C 32 read-write 0xA965 0xFFFF FIR0POSITION Position of first pixel. [3:0] read-write FIR1POSITION Position of second pixel. [7:4] read-write FIR2POSITION Position of third pixel. [11:8] read-write FIR3POSITION Position of fourth pixel. [15:12] read-write FIRCOEFFICIENTS FIR coefficients register. 0x70 32 read-write 0x20 0xFFFFFFFF FIR0COEFFICIENT First coefficient. (format is signed fix-point 3.5) [7:0] read-write FIR1COEFFICIENT Second coefficient. (format is signed fix-point 3.5) [15:8] read-write FIR2COEFFICIENT Third coefficient. (format is signed fix-point 3.5) [23:16] read-write FIR3COEFFICIENT Fourth coefficient. (format is signed fix-point 3.5) [31:24] read-write DECODECONTROL Control options for RLAD decompression. 0x74 32 read-write 0x88880001 0xFFFF0003 COMPRESSIONMODE Algorithm that the encoder used for compression. [1:0] read-write RLAD Run-Length Adaptive Dithering (lossy compression). 0 RLAD_UNIFORM Run-Length Adaptive Dithering (lossy compression; uniform package size). 1 RLA Run-Length Adaptive (lossless compression). 2 RL Standard Run-Length. In contrary to other modes is in big endian format. 3 RLADCOMPBITSRED Maximum for average number of bits per compressed pixel for Red or Y (luma) channel. This must match the corresponding encoder setting. [19:16] read-write RLADCOMPBITSGREEN Maximum for average number of bits per compressed pixel for Green or U (chroma) channel. This must match the corresponding encoder setting. [23:20] read-write RLADCOMPBITSBLUE Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel. This must match the corresponding encoder setting. [27:24] read-write RLADCOMPBITSALPHA Maximum for average number of bits per compressed pixel for Alpha channel. This must match the corresponding encoder setting. [31:28] read-write SOURCEBUFFERLENGTH Source buffer length for compressed data. 0x78 32 read-write 0x0 0x1FFFFFFF RLEWORDS Number of 32-bit words minus one that are required to decode the run length encoded source buffer. [28:0] read-write CONTROL Shared common control settings for all layers. 0x7C 32 read-write 0x30010000 0x307100BF RASTERMODE Selects a method how to generate source buffer sample points. [2:0] read-write NORMAL [IBO only, for LBO use PERSPECTIVE with corresponding Geometry] First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. 0 DECODE [FetchDecode/FetchBlit only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). 1 ARBITRARY [FetchBlit/Warp only] Arbitrary warping (filter is active). Coordinates are read from frame input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. 2 PERSPECTIVE [FetchBlit only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. See also field Geometry to reduce coordinate amount. 3 YUV422 [FetchBlit/Decode only] Source buffer is packed YUV 422. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). All correllated window widths and horizontal offsets must be even. 4 INPUTSELECT Selects function for the frame input port. [4:3] read-write INACTIVE Not used. 0 COMPPACK Used for component packing (e.g. UV or source alpha buffer). 1 ALPHAMASK Used for RGB and alpha pre-multiply stage (mask alpha buffer). 2 COORDINATE Used for arbitrary warping (coordinate buffer). 3 YUV422UPSAMPLINGMODE Selects a method for horizontal up-sampling of YUV 422/420 input data. [5:5] read-write REPLICATE Replicate mode for interspersed samples (UV samples between Y samples). 0 INTERPOLATE Interpolate mode for coaligned samples (UV samples at Y sample positions). 1 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 FILTERMODE Use this to select between nearest and bilinear filtering. Only has an effect if rastermode == ARBITRARY or rastermode == PERSPECTIVE or rastermode == AFFINE. [22:20] read-write NEAREST Chooses pixel closest to sample point 0 BILINEAR Calculates result from 4 pixels closest to sample point 1 FIR2 FIR mode with 2 programmable pixel positions and coefficients 2 FIR4 FIR mode with 4 programmable pixel positions and coefficients 3 HOR_LINEAR Calculates result from 2 pixels closest to the sample point and on the same line 4 GEOMETRY Control the geomety settings (PerspStartX/Y/W and PerspDeltaXX/XY/YX/YY/XW/YW usage) for the raster mode PERSPECTIVE. [29:28] read-write TRANSLATE PerspStartX/Y are used. (PerspDeltaXY/YX/XW/YW are 0. PerspDeltaXX/YY and PerspStartW are 1.) 0 SCALE PerspStartX/Y and PerspDeltaXX/YY are used. (PerspDeltaXY/YX/XW/YW are 0. PerspStartW is 1.) 1 ROTATION PerspStartX/Y and PerspDeltaXX/XY/YX/YY are used. (PerspDeltaXW/YW are 0. PerspStartW is 1.) 2 PERSPECTIVE All values PerspStartX/Y/W and PerspDeltaXX/XY/YX/YY/XW/YW are used 3 CONTROLTRIGGER Shadow load trigger. 0x80 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x84 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x88 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 DECODERSTATUS Status information of the RLAD decoder. 0x8C 32 read-write 0x0 0x3 BUFFERTOOSMALL The buffer size given by RLEWords is too small. No complete output frame could be decoded. [0:0] read-write BUFFERTOOLARGE The buffer size given by RLEWords is too large. A complete output frame could be decoded, but more data was read than necessary. [1:1] read-write BURSTBUFFERPROPERTIES Burst buffer properties. 0x90 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only FETCHMASK Fetch MASK (only for IBO) 0x00004800 STATICCONTROL Common static control options. 0x0 32 read-write 0x0 0xFF0001 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 BASEADDRESS0 Source buffer base address of layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0xC 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x10 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x14 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x18 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x1C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x20 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x24 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x28 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x2C 32 read-write 0xB8000008 0xFFFF7FFF PALETTEENABLE0 Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower bits of the lookup index are read from memory (PaletteIdWidth0), upper bits are set to index of this layer. Palette output is extended by upper bits of index word read from memory (e.g. to store alpha together with index). Result is mapped to color channels according to ColorComponentBits/Shift settings. [0:0] read-write TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE0 Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [3:3] read-write ALPHACONSTENABLE0 Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [4:4] read-write ALPHAMASKENABLE0 Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. [5:5] read-write ALPHATRANSENABLE0 Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [6:6] read-write RGBALPHASRCENABLE0 Value 1 enables source alpha (stored together with color component in the source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. [7:7] read-write RGBALPHACONSTENABLE0 Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. [8:8] read-write RGBALPHAMASKENABLE0 Value 1 enables mask alpha (read by another Fetch unit from a separate alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be enabled for this field to have effect. [9:9] read-write RGBALPHATRANSENABLE0 Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB0 When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no effect then. [11:11] read-write YUVCONVERSIONMODE0 Enables different kind of YUV to RGB conversions. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE0 Value 1 enables the stage to remove a gamma from RGB components. [14:14] read-write PALETTEOFFSET0 Palette may contain multiple areas. This offset shows to the starting position of the currently used area. [26:16] read-write PALETTEIDWIDTH0 Number minus one of least significant bits of pixel data read from the source buffer that are used as index value for color palette look-up. [29:27] read-write CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x30 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x34 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write WARPCONTROL Warping control options. 0x38 32 read-write 0x20 0x133F WARPBITSPERPIXEL Number of bits per pixel in the coordinate layer, which is read by another Fetch unit. Has to be 1, 2, 4, 8, 16 or 32. [5:0] read-write WARPCOORDINATEMODE Content of pixel data in the coordinate layer. [9:8] read-write PNT x and y (sample points). 0 D_PNT dx and dy (vectors between adjacent sample points). 1 DD_PNT ddx and ddy (deltas between adjacent vectors). 2 WARPSYMMETRICOFFSET Value 1 enables symmetric range for negative and positive coordinate values by adding an offset of +0.03125 internally to all coordinate input values. Recommended for small coordinate formats in DD_PNT mode. [12:12] read-write PERSPSTARTX Start value X for affine/perspective warping. 0x3C 32 read-write 0x0 0xFFFFFFFF PERSPSTARTX Start value for homogenous X coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPSTARTY Start value Y for affine/perspective warping. 0x40 32 read-write 0x0 0xFFFFFFFF PERSPSTARTY Start value for homogenous Y coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXX DeltaXX increment for affine/perspective warping. 0x44 32 read-write 0x3F800000 0xFFFFFFFF PERSPDELTAXX Increment of homogenous X coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYY DeltaYY increment for affine/perspective warping. 0x48 32 read-write 0x3F800000 0xFFFFFFFF PERSPDELTAYY Increment of homogenous Y coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXY DeltaXY increment for affine/perspective warping. 0x4C 32 read-write 0x0 0xFFFFFFFF PERSPDELTAXY Increment of homogenous Y coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYX DeltaYX increment for affine/perspective warping. 0x50 32 read-write 0x0 0xFFFFFFFF PERSPDELTAYX Increment of homogenous X coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPSTARTW Start value W for perspective warping. 0x54 32 read-write 0x3F800000 0xFFFFFFFF PERSPSTARTW Start value for homogenous W coordinate relative to origin. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAXW DeltaWX increment for perspective warping. 0x58 32 read-write 0x0 0xFFFFFFFF PERSPDELTAXW Increment of homogenous W coordinate for horizontal step (X) in destination frame. (format is floating-point 1e8m23) [31:0] read-write PERSPDELTAYW DeltaWY increment for perspective warping. 0x5C 32 read-write 0x0 0xFFFFFFFF PERSPDELTAYW Increment of homogenous W coordinate for vertical step (Y) in destination frame. (format is floating-point 1e8m23) [31:0] read-write ARBSTARTX Start value X for arbitrary warping. 0x60 32 read-write 0x0 0x1FFFFF ARBSTARTX Start point for sample-point interpolation (X coordinate). (format is signed fix-point 16.5) [20:0] read-write ARBSTARTY Start value Y for arbitrary warping. 0x64 32 read-write 0x0 0x1FFFFF ARBSTARTY Start point for sample-point interpolation (Y coordinate). (format is signed fix-point 16.5) [20:0] read-write ARBDELTA Start values for delta incrementation of arbitrary warping. 0x68 32 read-write 0x0 0xFFFFFFFF ARBDELTAXX X coordinate of vector between first and second sample point. (format is signed fix-point 3.5) [7:0] read-write ARBDELTAXY Y coordinate of vector between first and second sample point. (format is signed fix-point 3.5) [15:8] read-write ARBDELTAYX X coordinate of vector between start and first sample point. (format is signed fix-point 3.5) [23:16] read-write ARBDELTAYY Y coordinate of vector between start and first sample point. (format is signed fix-point 3.5) [31:24] read-write FIRPOSITIONS FIR sequence control register. 0x6C 32 read-write 0xA965 0xFFFF FIR0POSITION Position of first pixel. [3:0] read-write FIR1POSITION Position of second pixel. [7:4] read-write FIR2POSITION Position of third pixel. [11:8] read-write FIR3POSITION Position of fourth pixel. [15:12] read-write FIRCOEFFICIENTS FIR coefficients register. 0x70 32 read-write 0x20 0xFFFFFFFF FIR0COEFFICIENT First coefficient. (format is signed fix-point 3.5) [7:0] read-write FIR1COEFFICIENT Second coefficient. (format is signed fix-point 3.5) [15:8] read-write FIR2COEFFICIENT Third coefficient. (format is signed fix-point 3.5) [23:16] read-write FIR3COEFFICIENT Fourth coefficient. (format is signed fix-point 3.5) [31:24] read-write DECODECONTROL Control options for RLAD decompression. 0x74 32 read-write 0x88880001 0xFFFF0003 COMPRESSIONMODE Algorithm that the encoder used for compression. [1:0] read-write RLAD Run-Length Adaptive Dithering (lossy compression). 0 RLAD_UNIFORM Run-Length Adaptive Dithering (lossy compression; uniform package size). 1 RLA Run-Length Adaptive (lossless compression). 2 RL Standard Run-Length. In contrary to other modes is in big endian format. 3 RLADCOMPBITSRED Maximum for average number of bits per compressed pixel for Red or Y (luma) channel. This must match the corresponding encoder setting. [19:16] read-write RLADCOMPBITSGREEN Maximum for average number of bits per compressed pixel for Green or U (chroma) channel. This must match the corresponding encoder setting. [23:20] read-write RLADCOMPBITSBLUE Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel. This must match the corresponding encoder setting. [27:24] read-write RLADCOMPBITSALPHA Maximum for average number of bits per compressed pixel for Alpha channel. This must match the corresponding encoder setting. [31:28] read-write SOURCEBUFFERLENGTH Source buffer length for compressed data. 0x78 32 read-write 0x0 0x1FFFFFFF RLEWORDS Number of 32-bit words minus one that are required to decode the run length encoded source buffer. [28:0] read-write CONTROL Shared common control settings for all layers. 0x7C 32 read-write 0x30010000 0x307100BF RASTERMODE Selects a method how to generate source buffer sample points. [2:0] read-write NORMAL [IBO only, for LBO use PERSPECTIVE with corresponding Geometry] First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. 0 DECODE [FetchDecode/FetchBlit only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). 1 ARBITRARY [FetchBlit/Warp only] Arbitrary warping (filter is active). Coordinates are read from frame input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. 2 PERSPECTIVE [FetchBlit only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. See also field Geometry to reduce coordinate amount. 3 YUV422 [FetchBlit/Decode only] Source buffer is packed YUV 422. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). All correllated window widths and horizontal offsets must be even. 4 INPUTSELECT Selects function for the frame input port. [4:3] read-write INACTIVE Not used. 0 COMPPACK Used for component packing (e.g. UV or source alpha buffer). 1 ALPHAMASK Used for RGB and alpha pre-multiply stage (mask alpha buffer). 2 COORDINATE Used for arbitrary warping (coordinate buffer). 3 YUV422UPSAMPLINGMODE Selects a method for horizontal up-sampling of YUV 422/420 input data. [5:5] read-write REPLICATE Replicate mode for interspersed samples (UV samples between Y samples). 0 INTERPOLATE Interpolate mode for coaligned samples (UV samples at Y sample positions). 1 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 FILTERMODE Use this to select between nearest and bilinear filtering. Only has an effect if rastermode == ARBITRARY or rastermode == PERSPECTIVE or rastermode == AFFINE. [22:20] read-write NEAREST Chooses pixel closest to sample point 0 BILINEAR Calculates result from 4 pixels closest to sample point 1 FIR2 FIR mode with 2 programmable pixel positions and coefficients 2 FIR4 FIR mode with 4 programmable pixel positions and coefficients 3 HOR_LINEAR Calculates result from 2 pixels closest to the sample point and on the same line 4 GEOMETRY Control the geomety settings (PerspStartX/Y/W and PerspDeltaXX/XY/YX/YY/XW/YW usage) for the raster mode PERSPECTIVE. [29:28] read-write TRANSLATE PerspStartX/Y are used. (PerspDeltaXY/YX/XW/YW are 0. PerspDeltaXX/YY and PerspStartW are 1.) 0 SCALE PerspStartX/Y and PerspDeltaXX/YY are used. (PerspDeltaXY/YX/XW/YW are 0. PerspStartW is 1.) 1 ROTATION PerspStartX/Y and PerspDeltaXX/XY/YX/YY are used. (PerspDeltaXW/YW are 0. PerspStartW is 1.) 2 PERSPECTIVE All values PerspStartX/Y/W and PerspDeltaXX/XY/YX/YY/XW/YW are used 3 CONTROLTRIGGER Shadow load trigger. 0x80 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x84 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x88 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 DECODERSTATUS Status information of the RLAD decoder. 0x8C 32 read-write 0x0 0x3 BUFFERTOOSMALL The buffer size given by RLEWords is too small. No complete output frame could be decoded. [0:0] read-write BUFFERTOOLARGE The buffer size given by RLEWords is too large. A complete output frame could be decoded, but more data was read than necessary. [1:1] read-write BURSTBUFFERPROPERTIES Burst buffer properties. 0x90 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only ROP ROp 0x00005000 STATICCONTROL Raster Operation static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write CONTROL Raster Operation control register 0x4 32 read-write 0x0 0x7F1 MODE Operation mode for rop [0:0] read-write NEUTRAL Neutral mode 0 OPERATION Normal Operation 1 ALPHAMODE Selects the mode for the alpha component channel, has no effect in NEUTRAL mode [4:4] read-write ROP Normal raster operation mode, using the operation index 0 ADD Add mode, adds this component from all enabled inputs, clamps to 1 1 BLUEMODE Selects the mode for the blue component channel, has no effect in NEUTRAL mode [5:5] read-write ROP Normal raster operation mode, using the operation index 0 ADD Add mode, adds this component from all enabled inputs, clamps to 1 1 GREENMODE Selects the mode for the green component channel, has no effect in NEUTRAL mode [6:6] read-write ROP Normal raster operation mode, using the operation index 0 ADD Add mode, adds this component from all enabled inputs, clamps to 1 1 REDMODE Selects the mode for the red component channel, has no effect in NEUTRAL mode [7:7] read-write ROP Normal raster operation mode, using the operation index 0 ADD Add mode, adds this component from all enabled inputs, clamps to 1 1 PRIMDIV2 Selects whether to divide the primary input color components by two or not for ADD mode. This field has no effect on a color component in ROP mode. [8:8] read-write BYPASS No change to input 0 DIVIDEBY2 Input is divided by two/shift to the right by one 1 SECDIV2 Selects whether to divide the secondary input color components by two or not for ADD mode. This field has no effect on a color component in ROP mode. [9:9] read-write BYPASS No change to input 0 DIVIDEBY2 Input is divided by two/shift to the right by one 1 TERTDIV2 Selects whether to divide the tertiary input color components by two or not for ADD mode. This field has no effect on a color component in ROP mode. [10:10] read-write BYPASS No change to input 0 DIVIDEBY2 Input is divided by two/shift to the right by one 1 RASTEROPERATIONINDICES ROP operation indices 0x8 32 read-write 0x0 0xFFFFFFFF OPINDEXALPHA Alpha operation index [7:0] read-write OPINDEXBLUE Blue operation index [15:8] read-write OPINDEXGREEN Green operation index [23:16] read-write OPINDEXRED Red operation index [31:24] read-write PRIMCONTROLWORD Value of last received primary control word 0xC 32 read-only 0x0 0x0 P_VAL Value of last received control word on the primary input. If a 39 bit pixel channel is connected, the mapping is as follows: p_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only SECCONTROLWORD Value of last received secondary control word 0x10 32 read-only 0x0 0x0 S_VAL Value of last received control word on the secondary input. If a 39 bit pixel channel is connected, the mapping is as follows: s_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only TERTCONTROLWORD Value of last received tertiary control word 0x14 32 read-only 0x0 0x0 T_VAL Value of last received control word on the tertiary input. If a 39 bit pixel channel is connected, the mapping is as follows: t_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only CLUT CLut (only for IBO) 0x00005800 STATICCONTROL CLUT static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write UNSHADOWEDCONTROL CLUT unshadowed control register 0x4 32 read-write 0x0 0x7 B_EN Write enable for writing the blue color LUT entry from the host (allows writing a single color entry without a read-modify-write cycle) [0:0] read-write DISABLE disable 0 ENABLE enable 1 G_EN Write enable for writing the green color LUT entry from the host (allows writing a single color entry without a read-modify-write cycle) [1:1] read-write DISABLE disable 0 ENABLE enable 1 R_EN Write enable for writing the red color LUT entry from the host (allows writing a single color entry without a read-modify-write cycle) [2:2] read-write DISABLE disable 0 ENABLE enable 1 CONTROL CLUT control register 0x8 32 read-write 0x800 0xF73 MODE Operation mode for color lookup table [1:0] read-write NEUTRAL module in neutral mode, input data is bypassed to the output 0 LUT module in color lookup mode (LUT holds a 10bit color value lookup value for each input color) 1 INDEX_10BIT module in 10bit color index table mode (LUT holds a 3x10bit color value, indexed with the red input color) 2 INDEX_RGBA module in RGBA color index table mode (LUT holds a 3x8bit color value and a 6bit alpha value, indexed with the red input color) 3 COL_8BIT Color (red, green, blue) output bitwidth select [4:4] read-write DISABLE color is 10bit output 0 ENABLE color is 8bit output (dithering of internal 10bit value) 1 ALPHAMASK Enables the alpha mask mode. This mode disables lookup for all pixels with an alpha component smaller or greater/equal than 128. They are bypassed unchanged. [5:5] read-write DISABLE Alpha mask mode disabled 0 ENABLE Alpha mask mode enabled 1 ALPHAINVERT Chooses whether to disable lookup for alpha components smaller or greater/equal than 128. For this field to have an effect AlphaMask must be set to ENABLE. [6:6] read-write NORMAL Disable computation for alpha smaller than 128 0 INVERT Disable computation for alpha greater than or equal to 128 1 IDX_BITS Number of msb bits of the red color input used for the LUT index input [11:8] read-write STATUS CLUT status register 0xC 32 read-write 0x0 0x11 WRITE_TIMEOUT Timeout detected when writing to the LUT [0:0] read-write READ_TIMEOUT Timeout detected when reading from the LUT [4:4] read-write LASTCONTROLWORD Value of last received control word, for debugging 0x10 32 read-only 0x0 0x0 L_VAL Value of last received control word. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only 256 4 LUT[%s] Look Up Table 0x400 32 read-write 0x0 0x0 BLUE Blue component [9:0] read-write GREEN Green component [19:10] read-write RED Red component [29:20] read-write MATRIX Matrix 0x00006000 STATICCONTROL Color Matrix static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write CONTROL Color Matrix control register 0x4 32 read-write 0x0 0x33 MODE Operation mode for color matrix [1:0] read-write NEUTRAL Module in neutral mode, input data is bypassed 0 MATRIX Module in matrix mode, input data is multiplied with matrix values 1 PREMUL Module in alpha pre-multiplication mode, input color is multiplied with input alpha 2 RSVD N/A 3 ALPHAMASK Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value smaller than 0.5 are by-passed unchanged. [4:4] read-write ALPHAINVERT Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha value greater or equal 0.5 are by-passed). [5:5] read-write RED0 Matrix values for calculation of the red output value. 0x8 32 read-write 0x400 0x1FFF1FFF A11 Value for red input. (format is signed fix-point 3.10) [12:0] read-write A12 Value for green input. (format is signed fix-point 3.10) [28:16] read-write RED1 Matrix values for calculation of the red output value. 0xC 32 read-write 0x0 0x1FFF1FFF A13 Value for blue input. (format is signed fix-point 3.10) [12:0] read-write A14 Value for alpha input. (format is signed fix-point 3.10) [28:16] read-write GREEN0 Matrix values for calculation of the green output value. 0x10 32 read-write 0x4000000 0x1FFF1FFF A21 Value for red input. (format is signed fix-point 3.10) [12:0] read-write A22 Value for green input. (format is signed fix-point 3.10) [28:16] read-write GREEN1 Matrix values for calculation of the green output value. 0x14 32 read-write 0x0 0x1FFF1FFF A23 Value for blue input. (format is signed fix-point 3.10) [12:0] read-write A24 Value for alpha input. (format is signed fix-point 3.10) [28:16] read-write BLUE0 Matrix values for calculation of the blue output value. 0x18 32 read-write 0x0 0x1FFF1FFF A31 Value for red input. (format is signed fix-point 3.10) [12:0] read-write A32 Value for green input. (format is signed fix-point 3.10) [28:16] read-write BLUE1 Matrix values for calculation of the blue output value. 0x1C 32 read-write 0x400 0x1FFF1FFF A33 Value for blue input. (format is signed fix-point 3.10) [12:0] read-write A34 Value for alpha input. (format is signed fix-point 3.10) [28:16] read-write ALPHA0 Matrix values for calculation of the alpha output value. 0x20 32 read-write 0x0 0x1FFF1FFF A41 Value for red input. (format is signed fix-point 3.10) [12:0] read-write A42 Value for green input. (format is signed fix-point 3.10) [28:16] read-write ALPHA1 Matrix values for calculation of the alpha output value. 0x24 32 read-write 0x4000000 0x1FFF1FFF A43 Value for blue input. (format is signed fix-point 3.10) [12:0] read-write A44 Value for alpha input. (format is signed fix-point 3.10) [28:16] read-write OFFSETVECTOR0 Offset vectors for red and green output. 0x28 32 read-write 0x0 0x1FFF1FFF C1 Red output offset. (format is signed integer) [12:0] read-write C2 Green output offset. (format is signed integer) [28:16] read-write OFFSETVECTOR1 Offset vectors for blue and alpha output. 0x2C 32 read-write 0x0 0x1FFF1FFF C3 Blue output offset. (format is signed integer) [12:0] read-write C4 Alpha output offset. Note that the 8-bit alpha input is up-scaled to 10-bit, before the matrix and this offset is applied, and down-scaled to 8-bit for output afterwards. (format is signed integer) [28:16] read-write GPSCALER GPScaler (only for IBO) 0x00006400 STATICCONTROL Static control settings that must typically be setup once only. 0x0 32 read-write 0x0 0x1 SHDEN If ShdEn==1 shadow registers are loaded when indicated by hardware signal ( a command signal in the data stream at frame start ). If ShdEn==0 shadow registers are loaded each frame start. (format is unsigned integer) [0:0] read-write CONTROL Global operation control. 0x4 32 read-write 0x0 0x10F MODE Controls the sequence of horizontal and vertical operation for all operation modes. (format is unsigned integer) [3:0] read-write NEUTRAL Neutral mode. Pixels are by-passed unchanged, all other settings are ignored. 0 ACTIVE_AUTO Automatic mode. Behaves like ACTIVE_VER_FIRST when operation_mode=SCALE and scale_mode_h=UPSCALE, like ACTIVE_HOR_FIRST otherwise. 14 ACTIVE_HOR_FIRST Horizontal is done before vertical operation. 12 ACTIVE_VER_FIRST Vertical is done before horizontal operation. 13 ACTIVE_HOR_ONLY Only horizontal operation is done. 8 ACTIVE_VER_ONLY Only vertical operation is done. 5 OPERATION_MODE Selects the kind of operation to execute. (format is unsigned integer) [8:8] read-write SCALE Scaler is active with the corresponding settings from scaler registers; filter registers are ignored. 0 FIR FIR-Filter is active with the corresponding settings from filter registers; scaler registers are ignored. 1 OUTPUTDIMENSION Dimensions of the output frame or fame slice. This values are required for both FIR filter and scaler, since their output may have other dimension than input. The dimension of scaler's output is defined by the scale factor. The dimension of FIR filter's output depends on the tiling at the begin and the end of the slice. 0x8 32 read-write 0x0 0x3FFF3FFF OUTPUT_WIDTH Number of output pixel per input line. This number is equal to the width of the output frame minus one. (format is unsigned integer) [13:0] read-write OUTPUT_HEIGHT Number of output lines per input frame or slice. This number is equal to the height of the output frame minus one. (format is unsigned integer) [29:16] read-write SCALERCONTROL Scaler operation control. 0xC 32 read-write 0x20000 0xFF31111 SCALE_MODE_H Scale mode for horizontal scaling. (format is unsigned integer) [0:0] read-write DOWNSCALE Down-scaling (output width is less or equal input width). 0 UPSCALE Up-scaling (output width greater or equal input width) 1 SCALE_MODE_V Scale mode for vertical scaling. (format is unsigned integer) [4:4] read-write DOWNSCALE Down-scaling (output height less or equal input height). 0 UPSCALE Up-scaling (output height greater or equal input height) 1 FILTER_MODE_H Selects sampling algorithm for horizontal scaling. (format is unsigned integer) [8:8] read-write NEAREST Nearest filter (point-sampling) 0 LINEAR Box filter (linear) 1 FILTER_MODE_V Selects sampling algorithm for vertical scaling. (format is unsigned integer) [12:12] read-write NEAREST Nearest filter (point-sampling) 0 LINEAR Box filter (linear) 1 FIELD_MODE Controls generation of output field polarity for vertical scaling. (format is unsigned integer) [17:16] read-write ALWAYS0 Constant 0 indicates frame or top field. 0 ALWAYS1 Constant 1 indicates bottom field. 1 INPUT Output field polarity is taken from input field polarity. 2 TOGGLE Output field polarity toggles, starting with 0 after reset. 3 ALPHA_VALUE When 'mode' field is not 'NEUTRAL', then input alpha values are ignore and output alpha set to this constant value for all pixels. This restriction applies to GPScalerL derivative only. (format is unsigned integer) [27:20] read-write SCALERSETUPH0 Phase interpolator setup. 0x10 32 read-write 0x80000 0xFFFFF SCALE_FACTOR_H Scale factor has to be greater than 0.0 and less than or equal to 1.0. If scale_mode is UPSCALE then the inverse scale factor has to be programmed. (format is unsigned fix-point 1.19) [19:0] read-write SCALERSETUPH1 Phase interpolator setup. 0x14 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_H Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the right, a positive one to the left. (format is signed fix-point 2.19) [20:0] read-write SCALERSETUPV0 Phase interpolator setup. 0x18 32 read-write 0x80000 0xFFFFF SCALE_FACTOR_V Scale factor is greater than 0.0 and less than or equal to 1.0. If scale_mode is UPSCALE then the inverse scale factor have to be programmed. (format is unsigned fix-point 1.19) [19:0] read-write SCALERSETUPV1 Phase interpolator setup, selected if input and output field polarity is 0. 0x1C 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_V Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the bottom, a positive one to the top. (format is signed fix-point 2.19) [20:0] read-write SCALERSETUPV2 Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. 0x20 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_V1 Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the bottom, a positive one to the top. (format is signed fix-point 2.19) [20:0] read-write SCALERSETUPV3 Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. 0x24 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_V2 Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the bottom, a positive one to the top. (format is signed fix-point 2.19) [20:0] read-write SCALERSETUPV4 Phase interpolator setup, selected if input and output field polarity is 1. 0x28 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_V3 Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the bottom, a positive one to the top. (format is signed fix-point 2.19) [20:0] read-write FILTERCONTROL Filter operation control. 0x2C 32 read-write 0x0 0xFF33FF77 TAPS_H Defines the horizontal size of the FIR filter between 1 and 15 with increment of 2. Only odd filter width is supported. To program this field following formula has to be used: (filter width - 1)/2 (format is unsigned integer) [2:0] read-write TAPS_V Defines the vertical size of the FIR filter between 1 and 15 with increment of 2. Only odd filter width is supported. To program this field following formula has to be used: (filter height - 1)/2 (format is unsigned integer) [6:4] read-write BYPASS_MODE_R Bypass configuration for red color components of every pixel. (format is unsigned integer) [8:8] read-write NEUTRAL Red color is filtered. 0 ACTIVE Red color is not filtered, but is written to the line buffer. 1 BYPASS_MODE_G Bypass configuration for green color components of every pixel. (format is unsigned integer) [9:9] read-write NEUTRAL Green color is filtered. 0 ACTIVE Green color is not filtered, but is written to the line buffer. 1 BYPASS_MODE_B Bypass configuration for blue color components of every pixel. (format is unsigned integer) [10:10] read-write NEUTRAL Blue color is filtered. 0 ACTIVE Blue color is not filtered, but is written to the line buffer. 1 BYPASS_MODE_A Bypass configuration for alpha components of every pixel. (format is unsigned integer) [11:11] read-write NEUTRAL Alpha is filtered. 0 ACTIVE Alpha is not filtered, but is written to the line buffer. 1 EXPONENT_FIR FIR product sum is divided by 2**FIR_exponent and rounded. (format is unsigned integer) [15:12] read-write TILE_MODE Selects the tile mode for pixels outside the source frame. In order to enable tiling tiling_at_begin_h or tiling_at_begin_v and the corresponding output frame dimension have to be set. (format is unsigned integer) [17:16] read-write TILE_FILL_ZERO Use zero value. 0 TILE_FILL_CONSTANT Use constant color value from the field tile_color. 1 TILE_PAD Use closest pixel from source frame. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. 3 TILING_AT_BEGIN_H If set to true, this bit enables tiling at the begin of the slice for horizontal direction. Tiling at the end occurs automatically by setting the corresponding output size. (format is unsigned integer) [20:20] read-write TILING_AT_BEGIN_V If set to true, this bit enables tiling at the begin of the slice for vertical direction. Tiling at the end occurs automatically by setting the corresponding output size. (format is unsigned integer) [21:21] read-write TILE_COLOR_ALPHA Sets the alpha value for pixels outside of the slice. (format is unsigned integer) [31:24] read-write TILECOLORRGB Color for outside of the slice. 0x30 32 read-write 0x0 0x3FFFFFFF TILE_COLOR_RED Sets the red color value for pixels outside of the slice. (format is unsigned integer) [9:0] read-write TILE_COLOR_GREEN Sets the green color value for pixels outside of the slice. (format is unsigned integer) [19:10] read-write TILE_COLOR_BLUE Sets the blue color value for pixels outside of the slice. (format is unsigned integer) [29:20] read-write COEFFICIENTSH0 Horizontal coefficients for filter_mode FIR. 0x34 32 read-write 0x0 0xFFFFFFFF COEFF_H3 Horizontal coefficient 3. (format is signed integer) [7:0] read-write COEFF_H2 Horizontal coefficient 2. (format is signed integer) [15:8] read-write COEFF_H1 Horizontal coefficient 1. (format is signed integer) [23:16] read-write COEFF_H0 Horizontal coefficient 0. (format is signed integer) [31:24] read-write COEFFICIENTSH1 Horizontal coefficients for filter_mode FIR. 0x38 32 read-write 0x0 0xFFFFFFFF COEFF_H7 Horizontal coefficient 7. (format is signed integer) [7:0] read-write COEFF_H6 Horizontal coefficient 6. (format is signed integer) [15:8] read-write COEFF_H5 Horizontal coefficient 5. (format is signed integer) [23:16] read-write COEFF_H4 Horizontal coefficient 4. (format is signed integer) [31:24] read-write COEFFICIENTSH2 Horizontal coefficients for filter_mode FIR. 0x3C 32 read-write 0x0 0xFFFFFFFF COEFF_H11 Horizontal coefficient 11. (format is signed integer) [7:0] read-write COEFF_H10 Horizontal coefficient 10. (format is signed integer) [15:8] read-write COEFF_H9 Horizontal coefficient 9. (format is signed integer) [23:16] read-write COEFF_H8 Horizontal coefficient 8. (format is signed integer) [31:24] read-write COEFFICIENTSH3 Horizontal coefficients for filter_mode FIR. 0x40 32 read-write 0x0 0xFFFFFF00 COEFF_H14 Horizontal coefficient 14. The rightmost coefficient regardless of the filter width. In contrast to the coeff_h0 this coefficient has to be always programmed. (format is signed integer) [15:8] read-write COEFF_H13 Horizontal coefficient 13. (format is signed integer) [23:16] read-write COEFF_H12 Horizontal coefficient 12. (format is signed integer) [31:24] read-write COEFFICIENTSV0 Vertical coefficients for filter_mode FIR. 0x44 32 read-write 0x0 0xFFFFFFFF COEFF_V3 Vertical coefficient 3. (format is signed integer) [7:0] read-write COEFF_V2 Vertical coefficient 2. (format is signed integer) [15:8] read-write COEFF_V1 Vertical coefficient 1. (format is signed integer) [23:16] read-write COEFF_V0 Vertical coefficient 0. (format is signed integer) [31:24] read-write COEFFICIENTSV1 Vertical coefficients for filter_mode FIR. 0x48 32 read-write 0x0 0xFFFFFFFF COEFF_V7 Vertical coefficient 7. (format is signed integer) [7:0] read-write COEFF_V6 Vertical coefficient 6. (format is signed integer) [15:8] read-write COEFF_V5 Vertical coefficient 5. (format is signed integer) [23:16] read-write COEFF_V4 Vertical coefficient 4. (format is signed integer) [31:24] read-write COEFFICIENTSV2 Vertical coefficients for filter_mode FIR. 0x4C 32 read-write 0x0 0xFFFFFFFF COEFF_V11 Vertical coefficient 11. (format is signed integer) [7:0] read-write COEFF_V10 Vertical coefficient 10. (format is signed integer) [15:8] read-write COEFF_V9 Vertical coefficient 9. (format is signed integer) [23:16] read-write COEFF_V8 Vertical coefficient 8. (format is signed integer) [31:24] read-write COEFFICIENTSV3 Vertical coefficients for filter_mode FIR. 0x50 32 read-write 0x0 0xFFFFFF00 COEFF_V14 Vertical coefficient 14. The bottommost coefficient regardless of the filter height. In contrast to the coeff_v0 this coefficient has to be always programmed. (format is signed integer) [15:8] read-write COEFF_V13 Vertical coefficient 13. (format is signed integer) [23:16] read-write COEFF_V12 Vertical coefficient 12. (format is signed integer) [31:24] read-write BLITBLEND BlitBlend 0x00006800 STATICCONTROL BlitBlend static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write CONTROL BlitBlend control register 0x4 32 read-write 0x0 0x1 MODE Operation mode for BlitBlend [0:0] read-write NEUTRAL Neutral mode, only route pixels and commands from primary input to output 0 OPERATION Normal Operation 1 NEUTRALBORDER Neutral border setup register 0x8 32 read-write 0x0 0x7701 NEUTRALBORDERMODE Chooses whether to bypass primary or secondary input pixels [0:0] read-write PRIMARY Bypasses primary pixel 0 SECONDARY Bypasses secondary pixel 1 NEUTRALBORDERLEFT Number of neutral left border pixels [10:8] read-write NEUTRALBORDERRIGHT Number of neutral right border pixels [14:12] read-write CONSTANTCOLOR Constant color register 0xC 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA Alpha. [7:0] read-write CONSTANTBLUE Blue and V (chroma). [15:8] read-write CONSTANTGREEN Green and U (chroma). [23:16] read-write CONSTANTRED Red and Y (luma). [31:24] read-write COLORREDBLENDFUNCTION Open GL RGB blending factors 0x10 32 read-write 0x3000300 0xFFFFFFFF BLENDFUNCCOLORREDSRC Red component source blend function [15:0] read-write BLENDFUNCCOLORREDDST Red component destination blend function [31:16] read-write COLORGREENBLENDFUNCTION Open GL RGB blending factors 0x14 32 read-write 0x3000300 0xFFFFFFFF BLENDFUNCCOLORGREENSRC Green component source blend function [15:0] read-write BLENDFUNCCOLORGREENDST Green component destination blend function [31:16] read-write COLORBLUEBLENDFUNCTION Open GL RGB blending factors 0x18 32 read-write 0x3000300 0xFFFFFFFF BLENDFUNCCOLORBLUESRC Blue component source blend function [15:0] read-write BLENDFUNCCOLORBLUEDST Blue component destination blend function [31:16] read-write ALPHABLENDFUNCTION Open GL alpha blending factors 0x1C 32 read-write 0x3000300 0xFFFFFFFF BLENDFUNCALPHASRC Alpha component source blend function [15:0] read-write BLENDFUNCALPHADST Alpha component destination blend function [31:16] read-write BLENDMODE1 Open GL and Open VG blending modes for colors red and green 0x20 32 read-write 0x80068006 0xFFFFFFFF BLENDMODECOLORRED Red component blend mode [15:0] read-write BLENDMODECOLORGREEN Green component blend mode [31:16] read-write BLENDMODE2 Open GL and Open VG blending modes for color blue and alpha 0x24 32 read-write 0x80068006 0xFFFFFFFF BLENDMODECOLORBLUE Blue component blend mode [15:0] read-write BLENDMODEALPHA Alpha component blend mode [31:16] read-write DIRECTSETUP Direct Control of the BlitBlend Datapath multiplexers, do not change 0x28 32 read-write 0x0 0x3FF03FF COLORDEBUG Sets the multiplexers of the color datapath directly, do not change [9:0] read-write ALPHADEBUG Sets the multiplexers of the alpha datapath directly, do not change [25:16] read-write PRIMCONTROLWORD Value of last received primary control word 0x2C 32 read-only 0x0 0x0 P_VAL Value of last received control word on primary input. If a 39 bit pixel channel is connected, the mapping is as follows: p_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only SECCONTROLWORD Value of last received secondary control word 0x30 32 read-only 0x0 0x0 S_VAL Value of last received control word on secondary input. If a 39 bit pixel channel is connected, the mapping is as follows: s_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only STORE Store 0x00006C00 STATICCONTROL Store unit static control register. 0x0 32 read-write 0x0 0x111 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write SINGLEFRAMEOPERATION If this field and ShdEn are enabled, only frames with reload bit in command word are written to AXI, other frames are still consumed. If disabled all frames are writen to AXI [4:4] read-write BASEADDRESSAUTOUPDATE If enabled (value 1) the base address is automatically updated at the start of each frame. This update is then executed independently of the ShdEn setting. When disabled ShdEn controls the update of the base address operation register. [8:8] read-write BURSTBUFFERMANAGEMENT Burst Buffer setup register. 0x4 32 read-write 0x400 0x1F00 SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. Please note that SetBurstLength has to be smaller or equal to MaxBurstLength. Only a power of two may be specified as burst length. Please set this to at least 2 for 64bit pixels, otherwise performance will suffer. [12:8] read-write RINGBUFSTARTADDR Ring buffer setup for destination. 0x8 32 read-write 0x0 0xFFFFFFFF RINGBUFSTARTADDR Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes. [31:0] read-write RINGBUFWRAPADDR Ring buffer setup for destination. 0xC 32 read-write 0x0 0xFFFFFFFF RINGBUFWRAPADDR End address of the ring buffer (last byte of the buffer plus one). [31:0] read-write BASEADDRESS Destination buffer base address. 0x10 32 read-write 0x0 0xFFFFFFFF BASEADDRESS Byte aligned start address of the destination buffer. For 32 bit pixels BaseAddress[1:0] must be set 0 and for 16 bit pixels BaseAddress[0] must be set 0. [31:0] read-write DESTINATIONBUFFERATTRIBUTES Destination buffer attributes. 0x14 32 read-write 0x200004FF 0x7F01FFFF STRIDE Destination buffer stride in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [16:0] read-write BITSPERPIXEL Size of a pixel in the destination buffer in bits. Has to be a power of two, 18 or 24. When 64 bit is selected, input pixels are converted into a 32 bit value that is replicated into low and high word of the 64 bit output. Set SetBurstLength at least to 2 in that case to get best possible performance. [30:24] read-write DESTINATIONBUFFERDIMENSION Destination buffer dimension. 0x18 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH Width of the destination buffer in pixels minus one. [13:0] read-write LINECOUNT Number of lines of the destination buffer in pixels minus one. [29:16] read-write FRAMEOFFSET Offset between destination frame and buffer. 0x1C 32 read-write 0x0 0x7FFF7FFF FRAMEXOFFSET Horizontal offset (X). (format is signed integer) [14:0] read-write FRAMEYOFFSET Vertical offset (Y). (format is signed integer) [30:16] read-write COLORCOMPONENTBITS Color component size of destination buffer 0x20 32 read-write 0x8080808 0xF0F0F0F COMPONENTBITSALPHA Alpha component bits. [3:0] read-write COMPONENTBITSBLUE Blue/V component bits. [11:8] read-write COMPONENTBITSGREEN Green/U component bits. [19:16] read-write COMPONENTBITSRED Red/Y component bits. [27:24] read-write COLORCOMPONENTSHIFT Color component offset of destination buffer. 0x24 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA Alpha component shift. [4:0] read-write COMPONENTSHIFTBLUE Blue/V component shift. [12:8] read-write COMPONENTSHIFTGREEN Green/U component shift. [20:16] read-write COMPONENTSHIFTRED Red/Y component shift. [28:24] read-write CONTROL Store unit dynamic control register 0x28 32 read-write 0x0 0x3F10F3 COLORDITHERENABLE Controls whether spatial dithering (value 1) or LSB truncation (value 0) is used when ComponentBitsRed/Green/Blue is smaller than 10 bits. [0:0] read-write ALPHADITHERENABLE Controls whether spatial dithering (value 1) or LSB truncation (value 0) is used when ComponentBitsAlpha is smaller than 8 bits. [1:1] read-write DITHEROFFSET Dither offset that is additionally applied to the spatial offset, which is internally generated from the pixel position. Can be used by SW to generate image sequences with temporal dithering. [7:4] read-write GAMMAAPPLYENABLE Enable gamma conversion stage to apply gamma function. This gamma function converts the pixel data from linear color space to non-linear color space before writing it to AXI. [12:12] read-write YUVCONVERSIONMODE Enables different kind of RGB to YUV conversions. [17:16] read-write OFF No conversion. Input data must be RGB. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 RASTERMODE Selects a method for destination buffer data from input pixels. [19:18] read-write NORMAL RGBA or YUV 4:4:4 pixel buffer. 0 YUV422 Packed YUV 4:2:2 pixel buffer. Effect is that U samples are written for pixels with even and V samples for odd column index only. So BitsPerPixel must be set to the size that a pair of YU or YV has in memory (most typically 16 bits). All correlated widths and horizontal offsets must be even. 1 ENCODE RLAD compressed bit stream. 2 YUV422DOWNSAMPLINGMODE Selects a method for horizontal down-sampling when RasterMode is YUV422. [21:20] read-write NEAREST Nearest mode. Discards all odd samples, outputs even samples. 0 COALIGNED Linear coaligned mode. 3 nearest UV samples are combined in linear filter to get one output sample. 1 INTERSPERSED Linear interspersed mode. 2 nearest UV samples are combined in linear filter to get one output sample. 2 ENCODECONTROL Control options for RLAD compression. 0x2C 32 read-write 0x88880001 0xFFFF0001 COMPRESSIONMODE Algorithm to use for compression. [0:0] read-write RLAD Run-Length Adaptive Dithering (lossy compression). 0 RLAD_UNIFORM Run-Length Adaptive Dithering (lossy compression; uniform package size). 1 RLADCOMPBITSRED Maximum for average number of bits per compressed pixel for Red or Y (luma) channel. [19:16] read-write RLADCOMPBITSGREEN Maximum for average number of bits per compressed pixel for Green or U (chroma) channel. [23:20] read-write RLADCOMPBITSBLUE Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel. [27:24] read-write RLADCOMPBITSALPHA Maximum for average number of bits per compressed pixel for Alpha channel. [31:28] read-write DESTINATIONBUFFERLENGTH Destination buffer length for compressed data. 0x30 32 read-write 0x0 0x1FFFFFFF RLEWORDSMAX N/A [28:0] read-write START Store unit start register 0x34 32 write-only 0x0 0x0 START Writing a one starts processing of the pixel engine. [0:0] write-only ENCODERSTATUS Status information of the RLAD encoder. 0x38 32 read-write 0x1FFFFFFF 0x9FFFFFFF RLEWORDS Number of 32-bit words minus one that was used for the compressed buffer. [28:0] read-only BUFFERTOOSMALL The buffer size given by RLEWordsMax is too small. Not the complete input frame could be encoded. [31:31] read-write WRITEADDRESS Ring buffer synchronization. 0x3C 32 read-only 0x0 0xFFFFFFFF WRITEADDRESS Last burst address that was written to the destination buffer. [31:0] read-only FRAMEPROPERTIES Ring buffer synchronization. 0x40 32 read-only 0x0 0x1 FIELDID Field identifier for interlaced video streams (0/1 = even/odd line indices of progressive frame). Status is updated with begin of a new field. [0:0] read-only BURSTBUFFERPROPERTIES Burst Buffer Property register 0x44 32 read-only 0x0 0x0 MAXBURSTLENGTH Maximum Burst Length that can be configured. [12:8] read-only LASTCONTROLWORD Shows the last control word received 0x48 32 read-only 0x0 0xFFFFFFFF L_VAL Shows the last control word received from the pixel engine. If a 39 bit pixel channel is connected, the mapping is as follows: l_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only PERFCOUNTER Performance counter result 0x4C 32 read-only 0x0 0xFFFFFFFF PERFRESULT Returns the performance counter value. Please note that a sw reset during a frame can potentially produce invalid results in the first frame afterwards. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only DRAWENG Drawing Engine 0x00030000 STATICCONTROL Drawing Engine static control register 0x0 32 read-write 0x30 0x30 SWRESET Puts the Drawing Engine in software reset. [4:4] read-write OPERATION Normal Operation 0 SW_RESET Software Reset 1 CLOCKDISABLE Deactivates most internal clocks of Drawing Engine. Can only be activated if SWReset field is set to SW_RESET. [5:5] read-write OPERATION Normal Operation 0 POWERDOWN Clocks are off 1 STATICBURSTBUFFERMANAGEMENT Burst Buffer setup register 0x4 32 read-write 0x40004 0x1F001F SETFETCHBURSTLENGTH Set this to the maximum burst length that should be used on the AXI command fetch interface. Please note that SetFetchBurstLength has to be smaller or equal to MaxFetchBurstLength and it has to be one at the least. [4:0] read-write SETSTOREBURSTLENGTH Set this to the burst length that should be used on the AXI alpha store interface. Please note that SetStoreBurstLength has to be smaller or equal to MaxStoreBurstLength. Only a power of two may be specified as burst length. [20:16] read-write STATICCMDBUFFERADDRESS Lowest command buffer address 0x8 32 read-write 0x0 0xFFFFFFFF CMDBUFFERADDRESS Start address of the command buffer. The address is word aligned, keep bits [1:0] zero. Writing this register resets the CmdBufferReadPtr register. [31:0] read-write STATICCMDBUFFERSIZE Command buffer size 0xC 32 read-write 0x1FF 0x3FFFFFFF CMDBUFFERSIZE Command buffer size in number of 32-bit words. Only power-of-two values are allowed. The value programmed into this field must be one less than the actual number of words. [29:0] read-write CMDBUFFERWRITEPTR Buffer end address of command list 0x10 32 read-write 0x0 0x3FFFFFFF CMDBUFFERWRITEPTR Command buffer write pointer in words. This pointer must be set by the software to one word after the last valid command (start of the next operation). [29:0] read-write TRANSFORMATIONMATRIXA11 Component A11 of transformation Matrix A 0x14 32 read-write 0x40 0xFFFFFFFF A11 A11, given in signed fixed-point 26.6 two's complement notation. (format is signed fix-point 26.6) [31:0] read-write TRANSFORMATIONMATRIXA21 Component A21 of transformation Matrix A 0x18 32 read-write 0x0 0xFFFFFFFF A21 A21, given in signed fixed-point 26.6 two's complement notation. (format is signed fix-point 26.6) [31:0] read-write TRANSFORMATIONMATRIXA12 Component A12 of transformation Matrix A 0x1C 32 read-write 0x0 0xFFFFFFFF A12 A12, given in signed fixed-point 26.6 two's complement notation. (format is signed fix-point 26.6) [31:0] read-write TRANSFORMATIONMATRIXA22 Component A22 of transformation Matrix A 0x20 32 read-write 0x40 0xFFFFFFFF A22 A22, given in signed fixed-point 26.6 two's complement notation. (format is signed fix-point 26.6) [31:0] read-write TRANSLATIONVECTORX Horizontal translation of the alpha frame. 0x24 32 read-write 0x0 0x3FFFFF TRANSLATIONX Horizontal translation (X), given in signed 16.6 fixed-point format. Fractional part is used for processing. The integer part modifies the XOffset field of the LayerOffset register for subsequent Blit operation. (format is signed fix-point 16.6) [21:0] read-write TRANSLATIONVECTORY Vertical translation of the alpha frame. 0x28 32 read-write 0x0 0x3FFFFF TRANSLATIONY Vertical translation (Y), given in signed 16.6 fixed-point format. Fractional part is used for processing. The integer part modifies the YOffset field of the LayerOffset register for subsequent Blit operation. (format is signed fix-point 16.6) [21:0] read-write PROCESSINGCONTROL Drawing Engine main processing control register 0x2C 32 read-write 0x200008 0x3F001F SUBPIXELGRID Higher SubPixelGrid (super sampling) results in better anti-aliased output at the cost of processing time. [3:0] read-write TOTALBITS_1 1 bit per pixel, anti-aliased 1 TOTALBITS_2 2 bit per pixel, results in 2 bit anti-aliased intermediate value 2 TOTALBITS_4 4 bit per pixel, results in 4 bit anti-aliased intermediate value 4 TOTALBITS_8 8 bit per pixel, results in 6 bit anti-aliased intermediate value 8 FILLRULE Set the fill rule. [4:4] read-write NONZERO a edge count unequal zero is inside 1 EVENODD an odd edge count is inside, an even edge count is outside 0 TARGETBITSPERPIXEL Number of bits per pixel in the target buffer for the following blit operation. Must be 1, 2, 4, 8, 16, 18, 24 or 32. This field allows to obtain an aligned bounding box width. [21:16] read-write STORECONTROL Store unit dynamic control register 0x30 32 read-write 0x8 0x1FFFF0F STOREBITSPERPIXEL The resulting alpha mask can be saved to memory with the following BitsPerPixel settings. [3:0] read-write TOTALBITS_1 1 bit per pixel 1 TOTALBITS_2 2 bit per pixel 2 TOTALBITS_4 4 bit per pixel 4 TOTALBITS_8 8 bit per pixel 8 STORESTRIDE Destination buffer stride in bytes minus one. Used for address generation. [24:8] read-write DESTINATIONBUFFERDIMENSIONS Maximum dimensions of the destination buffer. The resulting alpha frame is limited to this dimensions. However, the active area can be smaller and is given by ActiveDimensions register. 0x34 32 read-write 0x0 0x3FFF3FFF DSTBUFFERWIDTH Maximum width of the destination buffer in pixels minus one. [13:0] read-write DSTBUFFERHEIGHT Maximum height of the destination buffer in pixels minus one. [29:16] read-write DESTINATIONBUFFER Destination buffer base address 0x38 32 read-write 0x0 0xFFFFFFFF DSTBASEADDRESS Byte aligned start address of the destination buffer. [31:0] read-write START Drawing Engine start register 0x3C 32 write-only 0x0 0x0 START Writing a one starts processing. [0:0] write-only READACK Drawing Engine read acknowledge register 0x40 32 write-only 0x0 0x0 READACK Writing a one acknowledges the read of the status registers ActiveDimensions and Offset. [0:0] write-only READACK_ERROR Writing a one acknowledges the read of the status register Error. [1:1] write-only CMDBUFFERREADPTR Buffer end address of command list 0x44 32 read-only 0x0 0x3FFFFFFF CMDBUFFERREADPTR Command buffer read pointer in words. This pointer is modified by the Drawing Engine hardware and indicates which words are ultimately consumed. [29:0] read-only ACTIVEDIMENSIONS Shows active dimensions of the output alpha frame. This register is aligned to the ClipWindowDimensions register of the fetch. 0x48 32 read-only 0x0 0x3FFF3FFF ACTIVEWIDTH Active width of the resulting alpha frame minus one. [13:0] read-only ACTIVEHEIGHT Active height of the resulting alpha frame minus one. [29:16] read-only LAYEROFFSET Desired position of the alpha frame for the following Blit operation. This register is aligned to the LayerOffset of the fetch and given as signed 16.0 values. 0x4C 32 read-only 0x0 0xFFFFFFFF XOFFSET Horizontal offset (X). (format is signed integer) [15:0] read-only YOFFSET Vertical offset (Y). (format is signed integer) [31:16] read-only ERROR Error status of finished operation. If register is unequal to zero the resulting raster image is most likely corrupted. 0x50 32 read-only 0x0 0xF FETCHERROR Indicates if an bus error occurred while fetching the command list. [0:0] read-only STOREERROR Indicates if storing the alpha bitmap to memory failed. [1:1] read-only INSTRERROR Indicates if the command list contained an illegal or unexpected instruction. [2:2] read-only OVERFLOWERROR Indicates if an overflow occurred when truncating to internal data width. [3:3] read-only BURSTBUFFERPROPERTIES Burst Buffer Property register 0x54 32 read-only 0x0 0x0 MAXFETCHBURSTLENGTH Maximum Burst Length that can be configured for command fetch. [4:0] read-only MAXSTOREBURSTLENGTH Maximum Burst Length that can be configured for alpha store. [20:16] read-only STATUS Status bits. 0x58 32 read-only 0x4 0xF STATUSBUSY Indicates if Drawing Engine is busy with drawing a command list. [0:0] read-only WAITACK Indicates if Drawing Engine is waiting on an read acknowledge. [1:1] read-only STATUSDIRTY Indicates if the linebuffer memory requires a clear prior to the next drawing operation. [2:2] read-only STARTPENDING Indicates if another start trigger is pending. [3:3] read-only PERFCOUNTERFRONT Performance counter result 0x5C 32 read-only 0x0 0xFFFFFFFF PERFRESULTFRONT Returns the performance counter value of the front pipeline. For the total cycle count add PerfResultFront and PerfResultBack. For debug purposes only, read when stable only. [31:0] read-only PERFCOUNTERBACK Performance counter result 0x60 32 read-only 0x0 0xFFFFFFFF PERFRESULTBACK Returns the performance counter value of the back pipeline. For the total cycle count add PerfResultFront and PerfResultBack. For debug purposes only, read when stable only. [31:0] read-only VIDEOIO Video I/O Core 0x00080000 SUBIO Sub Interface 0x00000000 VIDEOIOCFG Video I/O Core Configuration 0x00000000 INTR_VIDEOIO0 Interrupt status register 0 0x0 32 read-write 0x0 0xFFFFFF INTR_VIDEOIO0 Interrupt status vector. A bit is set when the related event occurs or the corresponding bit of INTR_VIDEOIO0_SET is written. By writing 1 the corresponding bit is cleared. [23:0] read-write INTR_VIDEOIO1 Interrupt Status register 1 0x4 32 read-write 0x0 0xFFFFFFF INTR_VIDEOIO1 Interrupt status vector. A bit is set when the related event occurs or the corresponding bit of INTR_VIDEOIO0_SET is written. By writing 1 the corresponding bit is cleared. [27:0] read-write INTR_VIDEOIO0_SET Interrupt set register 0 0x8 32 write-only 0x0 0x0 INTR_VIDEOIO0_SET Interrupt set vector. Writing a 1 to this fields sets status in INTR_VIDEOIO0. [23:0] write-only INTR_VIDEOIO1_SET Interrupt set register 1 0xC 32 write-only 0x0 0x0 INTR_VIDEOIO1_SET Interrupt set vector. Writing a 1 to this fields sets status in INTR_VIDEOIO1. [27:0] write-only INTR_VIDEOIO0_MASK Interrupt mask register 0 0x10 32 read-write 0x0 0xFFFFFF INTR_VIDEOIO0_MASK Interrupt mask vector. When a bit is set in this field, the related INTR_VIDEOIO0 status activates the interrupt signal. [23:0] read-write INTR_VIDEOIO1_MASK Interrupt mask register 1 0x14 32 read-write 0x0 0xFFFFFFF INTR_VIDEOIO1_MASK Interrupt mask vector. When a bit is set in this field, the related INTR_VIDEOIO1 status activates the interrupt signal. [27:0] read-write INTR_VIDEOIO0_MASKED Interrupt masked register 0 0x18 32 read-only 0x0 0x0 INTR_VIDEOIO0_MASKED Status vector INTR_VIDEOIO0 masked with INTR_VIDEOIO0_MASK. [23:0] read-only INTR_VIDEOIO1_MASKED Interrupt masked register 1 0x1C 32 read-only 0x0 0x0 INTR_VIDEOIO1_MASKED Status vector INTR_VIDEOIO1 masked with INTR_VIDEOIO1_MASK. [27:0] read-only INTR_VIDEOIO0_SAFETY Interrupt Status register 0 0x20 32 read-write 0x0 0xFFFFFF INTR_VIDEOIO0_SAFETY Interrupt status vector. A bit is set when the related event occurs or the corresponding bit of INTR_VIDEOIO0_SET is written. By writing 1 the corresponding bit is cleared. [23:0] read-write INTR_VIDEOIO1_SAFETY Interrupt Status register 1 0x24 32 read-write 0x0 0xFFFFFFF INTR_VIDEOIO1_SAFETY Interrupt status vector. A bit is set when the related event occurs or the corresponding bit of INTR_VIDEOIO0_SET is written. By writing 1 the corresponding bit is cleared. [27:0] read-write INTR_VIDEOIO0_SAFETY_SET Interrupt set register 0 0x28 32 write-only 0x0 0x0 INTR_VIDEOIO0_SAFETY_SET Interrupt set vector. Writing a 1 to this fields sets status in INTR_VIDEOIO0_SAFETY. [23:0] write-only INTR_VIDEOIO1_SAFETY_SET Interrupt set register 1 0x2C 32 write-only 0x0 0x0 INTR_VIDEOIO1_SAFETY_SET Interrupt set vector. Writing a 1 to this fields sets status in INTR_VIDEOIO1_SAFETY. [27:0] write-only INTR_VIDEOIO0_SAFETY_MASK Interrupt mask register 0 0x30 32 read-write 0x0 0xFFFFFF INTR_VIDEOIO0_SAFETY_MASK Interrupt mask vector. When a bit is set in this field, the related INTR_VIDEOIO0_SAFETY status activates the interrupt_safety signal. [23:0] read-write INTR_VIDEOIO1_SAFETY_MASK Interrupt mask register 1 0x34 32 read-write 0x0 0xFFFFFFF INTR_VIDEOIO1_SAFETY_MASK Interrupt mask vector. When a bit is set in this field, the related INTR_VIDEOIO1_SAFETY status activates the interrupt_safety signal. [27:0] read-write INTR_VIDEOIO0_SAFETY_MASKED Interrupt masked register 0 0x38 32 read-only 0x0 0x0 INTR_VIDEOIO0_SAFETY_MASKED Status vector INTR_VIDEOIO0_SAFETY masked with INTR_MASK_SAFETY0. [23:0] read-only INTR_VIDEOIO1_SAFETY_MASKED Interrupt masked register 1 0x3C 32 read-only 0x0 0x0 INTR_VIDEOIO1_SAFETY_MASKED Status vector INTR_VIDEOIO1_SAFETY masked with INTR_MASK_SAFETY1. [27:0] read-only FRAMEDUMP Frame Dump Unit 0x00000400 CONTROL Control settings. 0x0 32 read-write 0x0 0x3000001 INPUTSELECT Index of display stream that is dumped. [0:0] read-write SETFIELD The field property of the generated frame is set to this value. If field toggle is used, this is the start value. [24:24] read-write TOGGLEFIELD Enable toggling of the field property from frame to frame. Set to '1' to enable. [25:25] read-write FRAMESIZE Dump window size. 0x4 32 read-write 0xEF013F 0x3FFF3FFF FRAMEWIDTH Width of output frame of framedump, given minus one. Do not change during operation. [13:0] read-write FRAMEHEIGHT Height of output frame of framedump, given minus one. Do not change during operation. [29:16] read-write INPUTSETUP Dump window position. 0x8 32 read-write 0x0 0x3FFF3FFF INPUTCAPTUREXOFFSET X offset of capture area. Note that capture windows must not overlap the last column of the input frame. Do not change during operation. [13:0] read-write INPUTCAPTUREYOFFSET Y offset of capture area. Note that capture windows must not overlap the last row of the input frame. Do not change during operation. [29:16] read-write ENABLE Enable register. 0xC 32 read-write 0x0 0x1 DUMPEN If this is set to 1, the framedump unit will continuously dump all input frames. If set to 0, DumpReq is the other option of triggering the dumping of an input frame. [0:0] read-write TRIGGER Trigger bits. 0x10 32 read-write 0x0 0x1 DUMPREQ Next frame is dumped when this field is set. It is reset by HW once dumping of frame data has started. It cannot be reset by SW. [0:0] read-write STATUS Status register. 0x14 32 read-only 0x1 0x1 DUMPIDLE If read as '1', the framedump unit is currently not dumping any frames. If read as '0' the framedump unit is currently dumping frames. [0:0] read-only CAPENG0 Capture Engine 0x00001000 FRAMECAP Frame Capture Unit 0x00000400 CAPTUREMODE Capture mode configuration. FrameCap input mode configuration. 0x0 32 read-write 0x0 0x3 CAPTUREMODE Selects a capture mode. Do not change during operation of FrameCap unit. [1:0] read-write ENHSVS_32BIT Capture of 32-bit parallel or MIPI_CSI2 pixel input data with dedicated frame synchronization signals 0 ITU656_10BIT Capture of ITU656 10 bit data 1 ITU656_8BIT Capture of ITU656 8 bit data 2 CTR FrameCap control register for starting the unit 0x4 32 read-write 0x0 0x1 CEN CaptureEnable=1, enable bit for FrameCap unit. Capture starts with next frame sync signal. CaptureEnable=0, disable bit for FrameCap unit. Current frame is completed before FrameCap is stopped. [0:0] read-write SPR FrameCap sync signal polarity configuration. 0x8 32 read-write 0x0 0x7 POLEN Change polarity of video signal de. [0:0] read-write HIGHACT Signal is active high (default). 0 LOWACT Signal is active low. 1 POLHS Change polarity of video signal hsync. [1:1] read-write LOWACT Signal is active low (default). 0 HIGHACT Signal is active high. 1 POLVS Change polarity of video signal vsync. [2:2] read-write LOWACT Signal is active low (default). 0 HIGHACT Signal is active high. 1 MDR FrameCap control register for starting the mode detection 0xC 32 read-write 0x0 0xFFFFFFFF MDR_EN Mdr_en=1, enable bit for FrameCap mode detection and pixel frame rate measurement for the captured frame. Make sure that MdSts0.MdrCmrDone is 1 before starting it again. Mdr_en=0, disable bit for FrameCap mode detection. [0:0] read-write FRAMET_OFFSET Frame size tolerance which will not generate a mode detection size mismatch. Set an offset for frame time duration. [31:1] read-write FDR Frame dimension (progressive frame and field 0). 0x10 32 read-write 0xEF013F 0x3FFF3FFF WIDTH Expected frame width of video frame (value is Width - 1). It could be configured after mode detection. [13:0] read-write HEIGHT Expected frame height of video frames and fields with id 0 (value is Height - 1). It could be configured after mode detection. [29:16] read-write FDR1 Frame dimension (field 1). 0x14 32 read-write 0xEF0000 0x3FFF0000 HEIGHT1 Expected frame height of video fields with id 1 (value is Height - 1). It could be configured after mode detection. [29:16] read-write KDR FrameCap kick delay configuration register 0x18 32 read-write 0x0 0xFFFFFFF KICKDEL Delay after receiving last active pixel in frame (in video clock cycles) until the kick pulse is generated. In any case the kick pulse is generated with first active pixel of next frame latest. [27:0] read-write SCR FrameCap Sync frame number configuration register 0x1C 32 read-write 0x2 0xF FUS Number of consecutive frames captured until synchronization state is reached (value of 0 is not allowed). indicated by sts signal and register field Sts.SyncStat. [3:0] read-write CSVR Framecap control register for capture clock supervision 0x20 32 read-write 0x22 0x7FF CSVENABLE CsvEnable=1, start a capture clock supervision. [0:0] read-write CSVTIMEOUT setting a time limitation for waiting the recovery of capture clock. The value should be bigger than 11 or equal to 11, otherwise it reports fake clk_cap loss. [10:1] read-write STSCLR FrameCap status clear register. Clears the status bits of Sts register, Mdr_SizeChange and Csv_lost field. 0x24 32 write-only 0x0 0x0 STATUSCLEAR Clears status bits of Sts register. [0:0] write-only STS FrameCap status register. Current status of the FrameCap module. 0x28 32 read-only 0x0 0x13F FIFOFULL Write Access to the full coupling FIFO (bit locked when 1, cleared by writing StatusClear field). [0:0] read-only VSLATE VSYNC is detected too late. The received frame is too big (bit locked when 1, cleared by writing StatusClear field). [1:1] read-only VSEARLY VSYNC is detected too early. The received frame is too small (bit locked when 1, cleared by writing StatusClear field). [2:2] read-only CSV_LOST Csv_Lost=1, capture clock is not available. Csv_Lost=0, capture clock is resumed.(bit locked when 1, cleared by writing StatusClear field). [3:3] read-only MDR_SIZECHANGE Mdr_SizeChange=1, frame size of the video frame detected is not consistent. (bit locked when 1, clear by writing StatusClear field). If frame size change, the clock measurement fails. [4:4] read-only MDRCMRDONE MdrCmrDone=1 means that the mode detection is completed and pixel clock measurement is done. (bit locked when 1, clear by writing StatusClear field). [5:5] read-only SYNCSTAT Indicates the current state of synchronization (0 = out of sync, 1 = in sync). Note: A loss of the video stream cannot be detected using this field. Use the framegen status fields for this purpose. [8:8] read-only MDSTS0 FrameCap mode detection status register for the active part of the video frames.(bit locked when MdrCmrDone=1). 0x2C 32 read-only 0x0 0x7FFF7FFF ACTIVEWIDTH Frame width of active part of the video frame detected by the mode detection. The status can be read when MdrCmrDone=1. [14:0] read-only ACTIVEHEIGHT Frame height of active part of the video frame detected by the mode detection. The status can be read when MdrCmrDone=1. [30:16] read-only MDSTS1 FrameCap mode detection status register. The current (x,y) position of the capture stream (with respect to the output). 0x30 32 read-only 0x0 0x7FFF7FFF POSITIONX the current X position of the capture stream. [14:0] read-only POSITIONY the current Y position of the capture stream. [30:16] read-only FRCNT FrameCap frame counter register indicating the corresponding clk_axi cycles. 0x34 32 read-only 0x0 0xFFFFFFFF FRCOUNT Shows frame counts of video input. It is updated every vsync (for debugging purposes only). [31:0] read-only FRLINECOUNT FrameCap line counter register. 0x38 32 read-only 0x0 0x3F1F0000 FRLINECOUNT Shows current line number of input timing. Incremented with leading edge of hsync signal, set to 0 with leading edge of vsync signal. [13:0] read-only TOTWIDTHT_MSBS MSBs of CmSts1.TotWidthT. Bit locked when MdrCmrDone=1. [20:16] read-only ACTWIDTHT_MSBS MSBs of CmSts1.ActWidthT. Bit locked when MdrCmrDone=1. [29:24] read-only CMSTS1 clk_axi cycle number of a frame. (bit locked when MdrCmrDone=1). 0x3C 32 read-only 0x0 0x3FFFFFFF TOTAL_TIME clk_axi cycle number of a frame starting from vsync to another vsync. [29:0] read-only CMSTS2 clk_axi cycle number of totwidth and actwidth of a frame. (bit locked when MdrCmrDone=1). 0x40 32 read-only 0x0 0x1FFFFFFF TOTWIDTHT cycle number of the total part of a video frame line for calculating pixel frame rate. LSBs contained in this field, MSBs contained in FRLineCount.TotWidthT_MSBs. [14:0] read-only ACTWIDTHT cycle number of the active part of a video frame line for calculating pixel frame rate. LSBs contained in this field, MSBs contained in FRLineCount.ActWidthT_MSBs. [28:15] read-only ITUSTS ITU error status register. 0x44 32 read-write 0x0 0x3 ITUPROTECTIONONEBITERROR Set if a one bit error in the reference code of the ITU capture input 0 is found and corrected. Clear by writing a 1 to this field. [0:0] read-write ITUPROTECTIONTWOBITERROR Set if a two bit error in the reference code of the ITU capture input 0 is found. Two bit errors can only be detected, not corrected. Clear by writing a 1 to this field. [1:1] read-write COMPENG Composition Engine 0x00010000 COMPENGCFG Top-Level 0x00000000 1024 4 PALETTE[%s] Shared Color Palette Memory. 0x0 32 read-write 0x0 0x0 PALETTEENTRY Shared palette entry with 24-bit. Color format can be defined by Fetch configuration. [23:0] read-write EXTDST0_SAFETYMASK Safety mask for extdst0 0x1000 32 read-write 0x1FFFFF 0x1FFFFF EXTDST0_SAFETYMASK Each bit in this field describes whether the corresponding processing unit is allowed to be configured in a path leading to this endpoint (extdst0). 1 = allowed, 0 = prohibited. [20:0] read-write EXTDST4_SAFETYMASK Safety mask for extdst4 0x1004 32 read-write 0x1FFFFF 0x1FFFFF EXTDST4_SAFETYMASK Each bit in this field describes whether the corresponding processing unit is allowed to be configured in a path leading to this endpoint (extdst4). 1 = allowed, 0 = prohibited. [20:0] read-write EXTDST1_SAFETYMASK Safety mask for extdst1 0x1008 32 read-write 0x1FFFFF 0x1FFFFF EXTDST1_SAFETYMASK Each bit in this field describes whether the corresponding processing unit is allowed to be configured in a path leading to this endpoint (extdst1). 1 = allowed, 0 = prohibited. [20:0] read-write EXTDST5_SAFETYMASK Safety mask for extdst5 0x100C 32 read-write 0x1FFFFF 0x1FFFFF EXTDST5_SAFETYMASK Each bit in this field describes whether the corresponding processing unit is allowed to be configured in a path leading to this endpoint (extdst5). 1 = allowed, 0 = prohibited. [20:0] read-write STORE4_SAFETYMASK Safety mask for store4 0x1010 32 read-write 0x1FFFFF 0x1FFFFF STORE4_SAFETYMASK Each bit in this field describes whether the corresponding processing unit is allowed to be configured in a path leading to this endpoint (store4). 1 = allowed, 0 = prohibited. [20:0] read-write CONSTFRAME0_STATUS Status information for pixel engine configuration of constframe0 0x1020 32 read-only 0x0 0x0 CONSTFRAME0_SEL Status of the connection of the constframe0 module [18:16] read-only EXTDST0 constframe0 module is used from extdst0 processing path 1 EXTDST4 constframe0 module is used from extdst4 processing path 2 EXTDST1 constframe0 module is used from extdst1 processing path 3 EXTDST5 constframe0 module is used from extdst5 processing path 4 STORE4 constframe0 module is used from store4 processing path 5 DISABLE constframe0 module is not used 0 EXTDST0_STATIC Static pixel engine configuration for extdst0 0x1040 32 read-write 0x800010 0xFF0911 EXTDST0_SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for pixelbus configuration of pipeline with endpoint extdst0. [0:0] read-write EXTDST0_POWERDOWN Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst0 endpoint. [4:4] read-write EXTDST0_SYNC_MODE Synchronization mode for extdst0 pipeline endpoint synchronizer [8:8] read-write SINGLE Reconfig pipeline after explicit trigger 0 AUTO Reconfig pipeline after every kick when idle 1 EXTDST0_SW_RESET Software reset for extdst0 synchronizer, for debug purposes only [11:11] read-write OPERATION Normal Operation 0 SWRESET Software Reset 1 EXTDST0_DIV N/A [23:16] read-write EXTDST0_DYNAMIC Dynamic pixel engine configuration for extdst0 0x1044 32 read-write 0x17 0x1F EXTDST0_SRC_SEL Selection of the source for the src input of the extdst0 module [4:0] read-write DISABLE Unit extdst0 input port src is disabled 0 CONSTFRAME0 Unit extdst0 input port src is connected to output of unit constframe0 1 GPSCALER4 Unit extdst0 input port src is connected to output of unit gpscaler4 20 EXTSRC4 Unit extdst0 input port src is connected to output of unit extsrc4 9 LAYERBLEND5 Unit extdst0 input port src is connected to output of unit layerblend5 26 LAYERBLEND4 Unit extdst0 input port src is connected to output of unit layerblend4 25 LAYERBLEND3 Unit extdst0 input port src is connected to output of unit layerblend3 24 LAYERBLEND2 Unit extdst0 input port src is connected to output of unit layerblend2 23 LAYERBLEND1 Unit extdst0 input port src is connected to output of unit layerblend1 22 EXTDST0_REQUEST ShadowLoadRequest register for endpoint extdst0 0x1048 32 read-write 0x0 0x3FFF EXTDST0_SEL_SHDLDREQ Shadow load request flag for destination extdst0. [0:0] read-write EXTDST0_SHDLDREQ Vector of shadow load request flag of all sources for destination extdst0. Setting a bit has no effect if the source is currently in a different pipeline than the one of destination extdst0. [13:1] read-write EXTDST0_TRIGGER Trigger bits for pixel engine configuration of extdst0 0x104C 32 write-only 0x0 0x0 EXTDST0_SYNC_TRIGGER Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst0 [0:0] write-only EXTDST0_TRIGGER_SEQUENCE_COMPLETE By writing a '1' to this register field, you can trigger the extdst0 sequence complete interrupt that will occur as soon as the pipeline with the endpoint extdst0 is empty. This interrupt will also occur if the pipeline is already empty when this field is written. The interrupt will not occur if this field is not written. The interrupt will occur exactly as often as this field is written, assuming that this field is not written again until the interrupt has occured after a previous trigger. [4:4] write-only EXTDST0_STATUS Status information for pixel engine configuration of extdst0 0x1050 32 read-only 0x0 0x103 EXTDST0_PIPELINE_STATUS Status of pipeline with endpoint extdst0 [1:0] read-only EMPTY Pipeline with endpoint extdst0 is empty 0 RUNNING Pipeline with endpoint extdst0 is currently processing one operation 1 RUNNING_RETRIGGERED Pipeline with endpoint extdst0 is currently processing one operation with a second one already kicked to be processed afterwards 2 RSVD N/A 3 EXTDST0_SYNC_BUSY Synchronization busy status of extdst0 endpoint [8:8] read-only IDLE extdst0 synchronizer is idle 0 BUSY extdst0 synchronizer is busy 1 CONSTFRAME4_STATUS Status information for pixel engine configuration of constframe4 0x1080 32 read-only 0x0 0x0 CONSTFRAME4_SEL Status of the connection of the constframe4 module [18:16] read-only EXTDST0 constframe4 module is used from extdst0 processing path 1 EXTDST4 constframe4 module is used from extdst4 processing path 2 EXTDST1 constframe4 module is used from extdst1 processing path 3 EXTDST5 constframe4 module is used from extdst5 processing path 4 STORE4 constframe4 module is used from store4 processing path 5 DISABLE constframe4 module is not used 0 EXTDST4_STATIC Static pixel engine configuration for extdst4 0x10A0 32 read-write 0x800010 0xFF0911 EXTDST4_SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for pixelbus configuration of pipeline with endpoint extdst4. [0:0] read-write EXTDST4_POWERDOWN Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst4 endpoint. [4:4] read-write EXTDST4_SYNC_MODE Synchronization mode for extdst4 pipeline endpoint synchronizer [8:8] read-write SINGLE Reconfig pipeline after explicit trigger 0 AUTO Reconfig pipeline after every kick when idle 1 EXTDST4_SW_RESET Software reset for extdst4 synchronizer, for debug purposes only [11:11] read-write OPERATION Normal Operation 0 SWRESET Software Reset 1 EXTDST4_DIV N/A [23:16] read-write EXTDST4_DYNAMIC Dynamic pixel engine configuration for extdst4 0x10A4 32 read-write 0x0 0x1F EXTDST4_SRC_SEL Selection of the source for the src input of the extdst4 module [4:0] read-write DISABLE Unit extdst4 input port src is disabled 0 CONSTFRAME4 Unit extdst4 input port src is connected to output of unit constframe4 3 GPSCALER4 Unit extdst4 input port src is connected to output of unit gpscaler4 20 EXTSRC4 Unit extdst4 input port src is connected to output of unit extsrc4 9 LAYERBLEND5 Unit extdst4 input port src is connected to output of unit layerblend5 26 LAYERBLEND4 Unit extdst4 input port src is connected to output of unit layerblend4 25 LAYERBLEND3 Unit extdst4 input port src is connected to output of unit layerblend3 24 LAYERBLEND2 Unit extdst4 input port src is connected to output of unit layerblend2 23 LAYERBLEND1 Unit extdst4 input port src is connected to output of unit layerblend1 22 EXTDST4_REQUEST ShadowLoadRequest register for endpoint extdst4 0x10A8 32 read-write 0x0 0x3FFF EXTDST4_SEL_SHDLDREQ Shadow load request flag for destination extdst4. [0:0] read-write EXTDST4_SHDLDREQ Vector of shadow load request flag of all sources for destination extdst4. Setting a bit has no effect if the source is currently in a different pipeline than the one of destination extdst4. [13:1] read-write EXTDST4_TRIGGER Trigger bits for pixel engine configuration of extdst4 0x10AC 32 write-only 0x0 0x0 EXTDST4_SYNC_TRIGGER Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst4 [0:0] write-only EXTDST4_TRIGGER_SEQUENCE_COMPLETE By writing a '1' to this register field, you can trigger the extdst4 sequence complete interrupt that will occur as soon as the pipeline with the endpoint extdst4 is empty. This interrupt will also occur if the pipeline is already empty when this field is written. The interrupt will not occur if this field is not written. The interrupt will occur exactly as often as this field is written, assuming that this field is not written again until the interrupt has occured after a previous trigger. [4:4] write-only EXTDST4_STATUS Status information for pixel engine configuration of extdst4 0x10B0 32 read-only 0x0 0x103 EXTDST4_PIPELINE_STATUS Status of pipeline with endpoint extdst4 [1:0] read-only EMPTY Pipeline with endpoint extdst4 is empty 0 RUNNING Pipeline with endpoint extdst4 is currently processing one operation 1 RUNNING_RETRIGGERED Pipeline with endpoint extdst4 is currently processing one operation with a second one already kicked to be processed afterwards 2 RSVD N/A 3 EXTDST4_SYNC_BUSY Synchronization busy status of extdst4 endpoint [8:8] read-only IDLE extdst4 synchronizer is idle 0 BUSY extdst4 synchronizer is busy 1 CONSTFRAME1_STATUS Status information for pixel engine configuration of constframe1 0x10C0 32 read-only 0x0 0x0 CONSTFRAME1_SEL Status of the connection of the constframe1 module [18:16] read-only EXTDST0 constframe1 module is used from extdst0 processing path 1 EXTDST4 constframe1 module is used from extdst4 processing path 2 EXTDST1 constframe1 module is used from extdst1 processing path 3 EXTDST5 constframe1 module is used from extdst5 processing path 4 STORE4 constframe1 module is used from store4 processing path 5 DISABLE constframe1 module is not used 0 EXTDST1_STATIC Static pixel engine configuration for extdst1 0x10E0 32 read-write 0x800010 0xFF0911 EXTDST1_SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for pixelbus configuration of pipeline with endpoint extdst1. [0:0] read-write EXTDST1_POWERDOWN Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst1 endpoint. [4:4] read-write EXTDST1_SYNC_MODE Synchronization mode for extdst1 pipeline endpoint synchronizer [8:8] read-write SINGLE Reconfig pipeline after explicit trigger 0 AUTO Reconfig pipeline after every kick when idle 1 EXTDST1_SW_RESET Software reset for extdst1 synchronizer, for debug purposes only [11:11] read-write OPERATION Normal Operation 0 SWRESET Software Reset 1 EXTDST1_DIV N/A [23:16] read-write EXTDST1_DYNAMIC Dynamic pixel engine configuration for extdst1 0x10E4 32 read-write 0x18 0x1F EXTDST1_SRC_SEL Selection of the source for the src input of the extdst1 module [4:0] read-write DISABLE Unit extdst1 input port src is disabled 0 CONSTFRAME1 Unit extdst1 input port src is connected to output of unit constframe1 5 GPSCALER4 Unit extdst1 input port src is connected to output of unit gpscaler4 20 EXTSRC4 Unit extdst1 input port src is connected to output of unit extsrc4 9 LAYERBLEND5 Unit extdst1 input port src is connected to output of unit layerblend5 26 LAYERBLEND4 Unit extdst1 input port src is connected to output of unit layerblend4 25 LAYERBLEND3 Unit extdst1 input port src is connected to output of unit layerblend3 24 LAYERBLEND2 Unit extdst1 input port src is connected to output of unit layerblend2 23 LAYERBLEND1 Unit extdst1 input port src is connected to output of unit layerblend1 22 EXTDST1_REQUEST ShadowLoadRequest register for endpoint extdst1 0x10E8 32 read-write 0x0 0x3FFF EXTDST1_SEL_SHDLDREQ Shadow load request flag for destination extdst1. [0:0] read-write EXTDST1_SHDLDREQ Vector of shadow load request flag of all sources for destination extdst1. Setting a bit has no effect if the source is currently in a different pipeline than the one of destination extdst1. [13:1] read-write EXTDST1_TRIGGER Trigger bits for pixel engine configuration of extdst1 0x10EC 32 write-only 0x0 0x0 EXTDST1_SYNC_TRIGGER Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst1 [0:0] write-only EXTDST1_TRIGGER_SEQUENCE_COMPLETE By writing a '1' to this register field, you can trigger the extdst1 sequence complete interrupt that will occur as soon as the pipeline with the endpoint extdst1 is empty. This interrupt will also occur if the pipeline is already empty when this field is written. The interrupt will not occur if this field is not written. The interrupt will occur exactly as often as this field is written, assuming that this field is not written again until the interrupt has occured after a previous trigger. [4:4] write-only EXTDST1_STATUS Status information for pixel engine configuration of extdst1 0x10F0 32 read-only 0x0 0x103 EXTDST1_PIPELINE_STATUS Status of pipeline with endpoint extdst1 [1:0] read-only EMPTY Pipeline with endpoint extdst1 is empty 0 RUNNING Pipeline with endpoint extdst1 is currently processing one operation 1 RUNNING_RETRIGGERED Pipeline with endpoint extdst1 is currently processing one operation with a second one already kicked to be processed afterwards 2 RSVD N/A 3 EXTDST1_SYNC_BUSY Synchronization busy status of extdst1 endpoint [8:8] read-only IDLE extdst1 synchronizer is idle 0 BUSY extdst1 synchronizer is busy 1 CONSTFRAME5_STATUS Status information for pixel engine configuration of constframe5 0x1100 32 read-only 0x0 0x0 CONSTFRAME5_SEL Status of the connection of the constframe5 module [18:16] read-only EXTDST0 constframe5 module is used from extdst0 processing path 1 EXTDST4 constframe5 module is used from extdst4 processing path 2 EXTDST1 constframe5 module is used from extdst1 processing path 3 EXTDST5 constframe5 module is used from extdst5 processing path 4 STORE4 constframe5 module is used from store4 processing path 5 DISABLE constframe5 module is not used 0 EXTDST5_STATIC Static pixel engine configuration for extdst5 0x1120 32 read-write 0x800010 0xFF0911 EXTDST5_SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for pixelbus configuration of pipeline with endpoint extdst5. [0:0] read-write EXTDST5_POWERDOWN Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst5 endpoint. [4:4] read-write EXTDST5_SYNC_MODE Synchronization mode for extdst5 pipeline endpoint synchronizer [8:8] read-write SINGLE Reconfig pipeline after explicit trigger 0 AUTO Reconfig pipeline after every kick when idle 1 EXTDST5_SW_RESET Software reset for extdst5 synchronizer, for debug purposes only [11:11] read-write OPERATION Normal Operation 0 SWRESET Software Reset 1 EXTDST5_DIV N/A [23:16] read-write EXTDST5_DYNAMIC Dynamic pixel engine configuration for extdst5 0x1124 32 read-write 0x0 0x1F EXTDST5_SRC_SEL Selection of the source for the src input of the extdst5 module [4:0] read-write DISABLE Unit extdst5 input port src is disabled 0 CONSTFRAME5 Unit extdst5 input port src is connected to output of unit constframe5 7 GPSCALER4 Unit extdst5 input port src is connected to output of unit gpscaler4 20 EXTSRC4 Unit extdst5 input port src is connected to output of unit extsrc4 9 LAYERBLEND5 Unit extdst5 input port src is connected to output of unit layerblend5 26 LAYERBLEND4 Unit extdst5 input port src is connected to output of unit layerblend4 25 LAYERBLEND3 Unit extdst5 input port src is connected to output of unit layerblend3 24 LAYERBLEND2 Unit extdst5 input port src is connected to output of unit layerblend2 23 LAYERBLEND1 Unit extdst5 input port src is connected to output of unit layerblend1 22 EXTDST5_REQUEST ShadowLoadRequest register for endpoint extdst5 0x1128 32 read-write 0x0 0x3FFF EXTDST5_SEL_SHDLDREQ Shadow load request flag for destination extdst5. [0:0] read-write EXTDST5_SHDLDREQ Vector of shadow load request flag of all sources for destination extdst5. Setting a bit has no effect if the source is currently in a different pipeline than the one of destination extdst5. [13:1] read-write EXTDST5_TRIGGER Trigger bits for pixel engine configuration of extdst5 0x112C 32 write-only 0x0 0x0 EXTDST5_SYNC_TRIGGER Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst5 [0:0] write-only EXTDST5_TRIGGER_SEQUENCE_COMPLETE By writing a '1' to this register field, you can trigger the extdst5 sequence complete interrupt that will occur as soon as the pipeline with the endpoint extdst5 is empty. This interrupt will also occur if the pipeline is already empty when this field is written. The interrupt will not occur if this field is not written. The interrupt will occur exactly as often as this field is written, assuming that this field is not written again until the interrupt has occured after a previous trigger. [4:4] write-only EXTDST5_STATUS Status information for pixel engine configuration of extdst5 0x1130 32 read-only 0x0 0x103 EXTDST5_PIPELINE_STATUS Status of pipeline with endpoint extdst5 [1:0] read-only EMPTY Pipeline with endpoint extdst5 is empty 0 RUNNING Pipeline with endpoint extdst5 is currently processing one operation 1 RUNNING_RETRIGGERED Pipeline with endpoint extdst5 is currently processing one operation with a second one already kicked to be processed afterwards 2 RSVD N/A 3 EXTDST5_SYNC_BUSY Synchronization busy status of extdst5 endpoint [8:8] read-only IDLE extdst5 synchronizer is idle 0 BUSY extdst5 synchronizer is busy 1 EXTSRC4_STATUS Status information for pixel engine configuration of extsrc4 0x1140 32 read-only 0x0 0x0 EXTSRC4_SEL Status of the connection of the extsrc4 module [18:16] read-only EXTDST0 extsrc4 module is used from extdst0 processing path 1 EXTDST4 extsrc4 module is used from extdst4 processing path 2 EXTDST1 extsrc4 module is used from extdst1 processing path 3 EXTDST5 extsrc4 module is used from extdst5 processing path 4 STORE4 extsrc4 module is used from store4 processing path 5 DISABLE extsrc4 module is not used 0 STORE4_STATIC Static pixel engine configuration for store4 0x1160 32 read-write 0x800010 0xFF0911 STORE4_SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for pixelbus configuration of pipeline with endpoint store4. [0:0] read-write STORE4_POWERDOWN Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the store4 endpoint. [4:4] read-write STORE4_SYNC_MODE Synchronization mode for store4 pipeline endpoint synchronizer [8:8] read-write SINGLE Reconfig pipeline after explicit trigger 0 AUTO Reconfig pipeline after every kick when idle 1 STORE4_SW_RESET Software reset for store4 synchronizer, for debug purposes only [11:11] read-write OPERATION Normal Operation 0 SWRESET Software Reset 1 STORE4_DIV N/A [23:16] read-write STORE4_DYNAMIC Dynamic pixel engine configuration for store4 0x1164 32 read-write 0x9 0x1F STORE4_SRC_SEL Selection of the source for the src input of the store4 module Value matrix4 is only supported for IPVersion 1 IPPhase 2 or higher. [4:0] read-write DISABLE Unit store4 input port src is disabled 0 EXTSRC8 Unit store4 input port src is connected to output of unit extsrc8 27 GPSCALER4 Unit store4 input port src is connected to output of unit gpscaler4 20 EXTSRC4 Unit store4 input port src is connected to output of unit extsrc4 9 MATRIX4 Unit store4 input port src is connected to output of unit matrix4 19 STORE4_REQUEST ShadowLoadRequest register for endpoint store4 0x1168 32 read-write 0x0 0x3FFF STORE4_SEL_SHDLDREQ Shadow load request flag for destination store4. [0:0] read-write STORE4_SHDLDREQ Vector of shadow load request flag of all sources for destination store4. Setting a bit has no effect if the source is currently in a different pipeline than the one of destination store4. [13:1] read-write STORE4_TRIGGER Trigger bits for pixel engine configuration of store4 0x116C 32 write-only 0x0 0x0 STORE4_SYNC_TRIGGER Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint store4 [0:0] write-only STORE4_TRIGGER_SEQUENCE_COMPLETE By writing a '1' to this register field, you can trigger the store4 sequence complete interrupt that will occur as soon as the pipeline with the endpoint store4 is empty. This interrupt will also occur if the pipeline is already empty when this field is written. The interrupt will not occur if this field is not written. The interrupt will occur exactly as often as this field is written, assuming that this field is not written again until the interrupt has occured after a previous trigger. [4:4] write-only STORE4_STATUS Status information for pixel engine configuration of store4 0x1170 32 read-only 0x0 0x103 STORE4_PIPELINE_STATUS Status of pipeline with endpoint store4 [1:0] read-only EMPTY Pipeline with endpoint store4 is empty 0 RUNNING Pipeline with endpoint store4 is currently processing one operation 1 RUNNING_RETRIGGERED Pipeline with endpoint store4 is currently processing one operation with a second one already kicked to be processed afterwards 2 RSVD N/A 3 STORE4_SYNC_BUSY Synchronization busy status of store4 endpoint [8:8] read-only IDLE store4 synchronizer is idle 0 BUSY store4 synchronizer is busy 1 FETCHLAYER0_STATUS Status information for pixel engine configuration of fetchlayer0 0x1180 32 read-only 0x0 0x0 FETCHLAYER0_SEL Status of the connection of the fetchlayer0 module [18:16] read-only EXTDST0 fetchlayer0 module is used from extdst0 processing path 1 EXTDST4 fetchlayer0 module is used from extdst4 processing path 2 EXTDST1 fetchlayer0 module is used from extdst1 processing path 3 EXTDST5 fetchlayer0 module is used from extdst5 processing path 4 STORE4 fetchlayer0 module is used from store4 processing path 5 DISABLE fetchlayer0 module is not used 0 FETCHDECODE4_DYNAMIC Dynamic pixel engine configuration for fetchdecode4 0x11A0 32 read-write 0x0 0x1F FETCHDECODE4_SRC_SEL Selection of the source for the src input of the fetchdecode4 module Value gpscaler4 is only supported for IPVersion 1 IPPhase 2 or higher. [4:0] read-write DISABLE Unit fetchdecode4 input port src is disabled 0 FETCHECO4 Unit fetchdecode4 input port src is connected to output of unit fetcheco4 13 GPSCALER4 Unit fetchdecode4 input port src is connected to output of unit gpscaler4 20 FETCHDECODE4_STATUS Status information for pixel engine configuration of fetchdecode4 0x11A4 32 read-only 0x0 0x0 FETCHDECODE4_SEL Status of the connection of the fetchdecode4 module [18:16] read-only EXTDST0 fetchdecode4 module is used from extdst0 processing path 1 EXTDST4 fetchdecode4 module is used from extdst4 processing path 2 EXTDST1 fetchdecode4 module is used from extdst1 processing path 3 EXTDST5 fetchdecode4 module is used from extdst5 processing path 4 STORE4 fetchdecode4 module is used from store4 processing path 5 DISABLE fetchdecode4 module is not used 0 FETCHECO4_STATUS Status information for pixel engine configuration of fetcheco4 0x11C0 32 read-only 0x0 0x0 FETCHECO4_SEL Status of the connection of the fetcheco4 module [18:16] read-only EXTDST0 fetcheco4 module is used from extdst0 processing path 1 EXTDST4 fetcheco4 module is used from extdst4 processing path 2 EXTDST1 fetcheco4 module is used from extdst1 processing path 3 EXTDST5 fetcheco4 module is used from extdst5 processing path 4 STORE4 fetcheco4 module is used from store4 processing path 5 DISABLE fetcheco4 module is not used 0 FETCHWARP1_DYNAMIC Dynamic pixel engine configuration for fetchwarp1 0x1200 32 read-write 0x0 0x1F FETCHWARP1_SRC_SEL Selection of the source for the src input of the fetchwarp1 module [4:0] read-write DISABLE Unit fetchwarp1 input port src is disabled 0 FETCHECO1 Unit fetchwarp1 input port src is connected to output of unit fetcheco1 15 FETCHWARP1_STATUS Status information for pixel engine configuration of fetchwarp1 0x1204 32 read-only 0x0 0x0 FETCHWARP1_SEL Status of the connection of the fetchwarp1 module [18:16] read-only EXTDST0 fetchwarp1 module is used from extdst0 processing path 1 EXTDST4 fetchwarp1 module is used from extdst4 processing path 2 EXTDST1 fetchwarp1 module is used from extdst1 processing path 3 EXTDST5 fetchwarp1 module is used from extdst5 processing path 4 STORE4 fetchwarp1 module is used from store4 processing path 5 DISABLE fetchwarp1 module is not used 0 FETCHECO1_STATUS Status information for pixel engine configuration of fetcheco1 0x1208 32 read-only 0x0 0x0 FETCHECO1_SEL Status of the connection of the fetcheco1 module [18:16] read-only EXTDST0 fetcheco1 module is used from extdst0 processing path 1 EXTDST4 fetcheco1 module is used from extdst4 processing path 2 EXTDST1 fetcheco1 module is used from extdst1 processing path 3 EXTDST5 fetcheco1 module is used from extdst5 processing path 4 STORE4 fetcheco1 module is used from store4 processing path 5 DISABLE fetcheco1 module is not used 0 FETCHLAYER1_STATUS Status information for pixel engine configuration of fetchlayer1 0x1220 32 read-only 0x0 0x0 FETCHLAYER1_SEL Status of the connection of the fetchlayer1 module [18:16] read-only EXTDST0 fetchlayer1 module is used from extdst0 processing path 1 EXTDST4 fetchlayer1 module is used from extdst4 processing path 2 EXTDST1 fetchlayer1 module is used from extdst1 processing path 3 EXTDST5 fetchlayer1 module is used from extdst5 processing path 4 STORE4 fetchlayer1 module is used from store4 processing path 5 DISABLE fetchlayer1 module is not used 0 FETCHDECODE0_DYNAMIC Dynamic pixel engine configuration for fetchdecode0 0x1240 32 read-write 0x0 0x1F FETCHDECODE0_SRC_SEL Selection of the source for the src input of the fetchdecode0 module [4:0] read-write DISABLE Unit fetchdecode0 input port src is disabled 0 FETCHECO1 Unit fetchdecode0 input port src is connected to output of unit fetcheco1 15 FETCHECO4 Unit fetchdecode0 input port src is connected to output of unit fetcheco4 13 FETCHDECODE0_STATUS Status information for pixel engine configuration of fetchdecode0 0x1244 32 read-only 0x0 0x0 FETCHDECODE0_SEL Status of the connection of the fetchdecode0 module [18:16] read-only EXTDST0 fetchdecode0 module is used from extdst0 processing path 1 EXTDST4 fetchdecode0 module is used from extdst4 processing path 2 EXTDST1 fetchdecode0 module is used from extdst1 processing path 3 EXTDST5 fetchdecode0 module is used from extdst5 processing path 4 STORE4 fetchdecode0 module is used from store4 processing path 5 DISABLE fetchdecode0 module is not used 0 GAMMACOR4_DYNAMIC Dynamic pixel engine configuration for gammacor4 0x1260 32 read-write 0x0 0x1F GAMMACOR4_SRC_SEL Selection of the source for the src input of the gammacor4 module [4:0] read-write DISABLE Unit gammacor4 input port src is disabled 0 EXTSRC4 Unit gammacor4 input port src is connected to output of unit extsrc4 9 FETCHDECODE4 Unit gammacor4 input port src is connected to output of unit fetchdecode4 12 GAMMACOR4_STATUS Status information for pixel engine configuration of gammacor4 0x1264 32 read-only 0x0 0x0 GAMMACOR4_SEL Status of the connection of the gammacor4 module [18:16] read-only EXTDST0 gammacor4 module is used from extdst0 processing path 1 EXTDST4 gammacor4 module is used from extdst4 processing path 2 EXTDST1 gammacor4 module is used from extdst1 processing path 3 EXTDST5 gammacor4 module is used from extdst5 processing path 4 STORE4 gammacor4 module is used from store4 processing path 5 DISABLE gammacor4 module is not used 0 MATRIX4_DYNAMIC Dynamic pixel engine configuration for matrix4 0x1270 32 read-write 0x1000000 0x300001F MATRIX4_SRC_SEL Selection of the source for the src input of the matrix4 module [4:0] read-write DISABLE Unit matrix4 input port src is disabled 0 GAMMACOR4 Unit matrix4 input port src is connected to output of unit gammacor4 18 MATRIX4_CLKEN Enable of matrix4 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the register [endpoint_name]_clk must be set to 0x80. [25:24] read-write DISABLE Clock for matrix4 is disabled 0 AUTOMATIC Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) 1 FULL Clock for matrix4 is without gating 3 MATRIX4_STATUS Status information for pixel engine configuration of matrix4 0x1274 32 read-only 0x0 0x0 MATRIX4_SEL Status of the connection of the matrix4 module [18:16] read-only EXTDST0 matrix4 module is used from extdst0 processing path 1 EXTDST4 matrix4 module is used from extdst4 processing path 2 EXTDST1 matrix4 module is used from extdst1 processing path 3 EXTDST5 matrix4 module is used from extdst5 processing path 4 STORE4 matrix4 module is used from store4 processing path 5 DISABLE matrix4 module is not used 0 GPSCALER4_DYNAMIC Dynamic pixel engine configuration for gpscaler4 0x1280 32 read-write 0x1000000 0x300001F GPSCALER4_SRC_SEL Selection of the source for the src input of the gpscaler4 module Value fetcheco4 is only supported for IPVersion 1 IPPhase 2 or higher. [4:0] read-write DISABLE Unit gpscaler4 input port src is disabled 0 MATRIX4 Unit gpscaler4 input port src is connected to output of unit matrix4 19 FETCHECO4 Unit gpscaler4 input port src is connected to output of unit fetcheco4 13 GPSCALER4_CLKEN Enable of gpscaler4 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the register [endpoint_name]_clk must be set to 0x80. [25:24] read-write DISABLE Clock for gpscaler4 is disabled 0 AUTOMATIC Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) 1 FULL Clock for gpscaler4 is without gating 3 GPSCALER4_STATUS Status information for pixel engine configuration of gpscaler4 0x1284 32 read-only 0x0 0x0 GPSCALER4_SEL Status of the connection of the gpscaler4 module [18:16] read-only EXTDST0 gpscaler4 module is used from extdst0 processing path 1 EXTDST4 gpscaler4 module is used from extdst4 processing path 2 EXTDST1 gpscaler4 module is used from extdst1 processing path 3 EXTDST5 gpscaler4 module is used from extdst5 processing path 4 STORE4 gpscaler4 module is used from store4 processing path 5 DISABLE gpscaler4 module is not used 0 HISTOGRAM4_DYNAMIC Dynamic pixel engine configuration for histogram4 0x1290 32 read-write 0x1000000 0x300001F HISTOGRAM4_SRC_SEL Selection of the source for the src input of the histogram4 module [4:0] read-write DISABLE Unit histogram4 input port src is disabled 0 EXTSRC4 Unit histogram4 input port src is connected to output of unit extsrc4 9 FETCHDECODE4 Unit histogram4 input port src is connected to output of unit fetchdecode4 12 GAMMACOR4 Unit histogram4 input port src is connected to output of unit gammacor4 18 MATRIX4 Unit histogram4 input port src is connected to output of unit matrix4 19 HISTOGRAM4_CLKEN Enable of histogram4 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the register [endpoint_name]_clk must be set to 0x80. [25:24] read-write DISABLE Clock for histogram4 is disabled 0 AUTOMATIC Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) 1 FULL Clock for histogram4 is without gating 3 HISTOGRAM4_STATUS Status information for pixel engine configuration of histogram4 0x1294 32 read-only 0x0 0x0 HISTOGRAM4_SEL Status of the connection of the histogram4 module [18:16] read-only EXTDST0 histogram4 module is used from extdst0 processing path 1 EXTDST4 histogram4 module is used from extdst4 processing path 2 EXTDST1 histogram4 module is used from extdst1 processing path 3 EXTDST5 histogram4 module is used from extdst5 processing path 4 STORE4 histogram4 module is used from store4 processing path 5 DISABLE histogram4 module is not used 0 LAYERBLEND1_DYNAMIC Dynamic pixel engine configuration for layerblend1 0x12A0 32 read-write 0x1000000 0x3001F1F LAYERBLEND1_PRIM_SEL Selection of the source for the prim input of the layerblend1 module [4:0] read-write DISABLE Unit layerblend1 input port prim is disabled 0 CONSTFRAME0 Unit layerblend1 input port prim is connected to output of unit constframe0 1 CONSTFRAME1 Unit layerblend1 input port prim is connected to output of unit constframe1 5 CONSTFRAME4 Unit layerblend1 input port prim is connected to output of unit constframe4 3 CONSTFRAME5 Unit layerblend1 input port prim is connected to output of unit constframe5 7 MATRIX4 Unit layerblend1 input port prim is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend1 input port prim is connected to output of unit gpscaler4 20 EXTSRC4 Unit layerblend1 input port prim is connected to output of unit extsrc4 9 LAYERBLEND1_SEC_SEL Selection of the source for the sec input of the layerblend1 module [12:8] read-write DISABLE Unit layerblend1 input port sec is disabled 0 FETCHDECODE4 Unit layerblend1 input port sec is connected to output of unit fetchdecode4 12 FETCHWARP1 Unit layerblend1 input port sec is connected to output of unit fetchwarp1 14 FETCHDECODE0 Unit layerblend1 input port sec is connected to output of unit fetchdecode0 17 MATRIX4 Unit layerblend1 input port sec is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend1 input port sec is connected to output of unit gpscaler4 20 FETCHLAYER0 Unit layerblend1 input port sec is connected to output of unit fetchlayer0 11 FETCHLAYER1 Unit layerblend1 input port sec is connected to output of unit fetchlayer1 16 LAYERBLEND1_CLKEN Enable of layerblend1 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the register [endpoint_name]_clk must be set to 0x80. [25:24] read-write DISABLE Clock for layerblend1 is disabled 0 AUTOMATIC Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) 1 FULL Clock for layerblend1 is without gating 3 LAYERBLEND1_STATUS Status information for pixel engine configuration of layerblend1 0x12A4 32 read-only 0x0 0x0 LAYERBLEND1_SEL Status of the connection of the layerblend1 module [18:16] read-only EXTDST0 layerblend1 module is used from extdst0 processing path 1 EXTDST4 layerblend1 module is used from extdst4 processing path 2 EXTDST1 layerblend1 module is used from extdst1 processing path 3 EXTDST5 layerblend1 module is used from extdst5 processing path 4 STORE4 layerblend1 module is used from store4 processing path 5 DISABLE layerblend1 module is not used 0 LAYERBLEND2_DYNAMIC Dynamic pixel engine configuration for layerblend2 0x12C0 32 read-write 0x1000B01 0x3001F1F LAYERBLEND2_PRIM_SEL Selection of the source for the prim input of the layerblend2 module [4:0] read-write DISABLE Unit layerblend2 input port prim is disabled 0 CONSTFRAME0 Unit layerblend2 input port prim is connected to output of unit constframe0 1 CONSTFRAME1 Unit layerblend2 input port prim is connected to output of unit constframe1 5 CONSTFRAME4 Unit layerblend2 input port prim is connected to output of unit constframe4 3 CONSTFRAME5 Unit layerblend2 input port prim is connected to output of unit constframe5 7 MATRIX4 Unit layerblend2 input port prim is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend2 input port prim is connected to output of unit gpscaler4 20 EXTSRC4 Unit layerblend2 input port prim is connected to output of unit extsrc4 9 LAYERBLEND1 Unit layerblend2 input port prim is connected to output of unit layerblend1 22 LAYERBLEND2_SEC_SEL Selection of the source for the sec input of the layerblend2 module [12:8] read-write DISABLE Unit layerblend2 input port sec is disabled 0 FETCHDECODE4 Unit layerblend2 input port sec is connected to output of unit fetchdecode4 12 FETCHWARP1 Unit layerblend2 input port sec is connected to output of unit fetchwarp1 14 FETCHDECODE0 Unit layerblend2 input port sec is connected to output of unit fetchdecode0 17 MATRIX4 Unit layerblend2 input port sec is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend2 input port sec is connected to output of unit gpscaler4 20 FETCHLAYER0 Unit layerblend2 input port sec is connected to output of unit fetchlayer0 11 FETCHLAYER1 Unit layerblend2 input port sec is connected to output of unit fetchlayer1 16 LAYERBLEND2_CLKEN Enable of layerblend2 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the register [endpoint_name]_clk must be set to 0x80. [25:24] read-write DISABLE Clock for layerblend2 is disabled 0 AUTOMATIC Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) 1 FULL Clock for layerblend2 is without gating 3 LAYERBLEND2_STATUS Status information for pixel engine configuration of layerblend2 0x12C4 32 read-only 0x0 0x0 LAYERBLEND2_SEL Status of the connection of the layerblend2 module [18:16] read-only EXTDST0 layerblend2 module is used from extdst0 processing path 1 EXTDST4 layerblend2 module is used from extdst4 processing path 2 EXTDST1 layerblend2 module is used from extdst1 processing path 3 EXTDST5 layerblend2 module is used from extdst5 processing path 4 STORE4 layerblend2 module is used from store4 processing path 5 DISABLE layerblend2 module is not used 0 LAYERBLEND3_DYNAMIC Dynamic pixel engine configuration for layerblend3 0x12E0 32 read-write 0x1001005 0x3001F1F LAYERBLEND3_PRIM_SEL Selection of the source for the prim input of the layerblend3 module [4:0] read-write DISABLE Unit layerblend3 input port prim is disabled 0 CONSTFRAME0 Unit layerblend3 input port prim is connected to output of unit constframe0 1 CONSTFRAME1 Unit layerblend3 input port prim is connected to output of unit constframe1 5 CONSTFRAME4 Unit layerblend3 input port prim is connected to output of unit constframe4 3 CONSTFRAME5 Unit layerblend3 input port prim is connected to output of unit constframe5 7 MATRIX4 Unit layerblend3 input port prim is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend3 input port prim is connected to output of unit gpscaler4 20 EXTSRC4 Unit layerblend3 input port prim is connected to output of unit extsrc4 9 LAYERBLEND2 Unit layerblend3 input port prim is connected to output of unit layerblend2 23 LAYERBLEND1 Unit layerblend3 input port prim is connected to output of unit layerblend1 22 LAYERBLEND3_SEC_SEL Selection of the source for the sec input of the layerblend3 module [12:8] read-write DISABLE Unit layerblend3 input port sec is disabled 0 FETCHDECODE4 Unit layerblend3 input port sec is connected to output of unit fetchdecode4 12 FETCHWARP1 Unit layerblend3 input port sec is connected to output of unit fetchwarp1 14 FETCHDECODE0 Unit layerblend3 input port sec is connected to output of unit fetchdecode0 17 MATRIX4 Unit layerblend3 input port sec is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend3 input port sec is connected to output of unit gpscaler4 20 FETCHLAYER0 Unit layerblend3 input port sec is connected to output of unit fetchlayer0 11 FETCHLAYER1 Unit layerblend3 input port sec is connected to output of unit fetchlayer1 16 LAYERBLEND3_CLKEN Enable of layerblend3 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the register [endpoint_name]_clk must be set to 0x80. [25:24] read-write DISABLE Clock for layerblend3 is disabled 0 AUTOMATIC Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) 1 FULL Clock for layerblend3 is without gating 3 LAYERBLEND3_STATUS Status information for pixel engine configuration of layerblend3 0x12E4 32 read-only 0x0 0x0 LAYERBLEND3_SEL Status of the connection of the layerblend3 module [18:16] read-only EXTDST0 layerblend3 module is used from extdst0 processing path 1 EXTDST4 layerblend3 module is used from extdst4 processing path 2 EXTDST1 layerblend3 module is used from extdst1 processing path 3 EXTDST5 layerblend3 module is used from extdst5 processing path 4 STORE4 layerblend3 module is used from store4 processing path 5 DISABLE layerblend3 module is not used 0 LAYERBLEND4_DYNAMIC Dynamic pixel engine configuration for layerblend4 0x1300 32 read-write 0x1000000 0x3001F1F LAYERBLEND4_PRIM_SEL Selection of the source for the prim input of the layerblend4 module [4:0] read-write DISABLE Unit layerblend4 input port prim is disabled 0 CONSTFRAME0 Unit layerblend4 input port prim is connected to output of unit constframe0 1 CONSTFRAME1 Unit layerblend4 input port prim is connected to output of unit constframe1 5 CONSTFRAME4 Unit layerblend4 input port prim is connected to output of unit constframe4 3 CONSTFRAME5 Unit layerblend4 input port prim is connected to output of unit constframe5 7 MATRIX4 Unit layerblend4 input port prim is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend4 input port prim is connected to output of unit gpscaler4 20 EXTSRC4 Unit layerblend4 input port prim is connected to output of unit extsrc4 9 LAYERBLEND3 Unit layerblend4 input port prim is connected to output of unit layerblend3 24 LAYERBLEND2 Unit layerblend4 input port prim is connected to output of unit layerblend2 23 LAYERBLEND1 Unit layerblend4 input port prim is connected to output of unit layerblend1 22 LAYERBLEND4_SEC_SEL Selection of the source for the sec input of the layerblend4 module [12:8] read-write DISABLE Unit layerblend4 input port sec is disabled 0 FETCHDECODE4 Unit layerblend4 input port sec is connected to output of unit fetchdecode4 12 FETCHWARP1 Unit layerblend4 input port sec is connected to output of unit fetchwarp1 14 FETCHDECODE0 Unit layerblend4 input port sec is connected to output of unit fetchdecode0 17 MATRIX4 Unit layerblend4 input port sec is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend4 input port sec is connected to output of unit gpscaler4 20 FETCHLAYER0 Unit layerblend4 input port sec is connected to output of unit fetchlayer0 11 FETCHLAYER1 Unit layerblend4 input port sec is connected to output of unit fetchlayer1 16 LAYERBLEND4_CLKEN Enable of layerblend4 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the register [endpoint_name]_clk must be set to 0x80. [25:24] read-write DISABLE Clock for layerblend4 is disabled 0 AUTOMATIC Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) 1 FULL Clock for layerblend4 is without gating 3 LAYERBLEND4_STATUS Status information for pixel engine configuration of layerblend4 0x1304 32 read-only 0x0 0x0 LAYERBLEND4_SEL Status of the connection of the layerblend4 module [18:16] read-only EXTDST0 layerblend4 module is used from extdst0 processing path 1 EXTDST4 layerblend4 module is used from extdst4 processing path 2 EXTDST1 layerblend4 module is used from extdst1 processing path 3 EXTDST5 layerblend4 module is used from extdst5 processing path 4 STORE4 layerblend4 module is used from store4 processing path 5 DISABLE layerblend4 module is not used 0 LAYERBLEND5_DYNAMIC Dynamic pixel engine configuration for layerblend5 0x1320 32 read-write 0x1000000 0x3001F1F LAYERBLEND5_PRIM_SEL Selection of the source for the prim input of the layerblend5 module [4:0] read-write DISABLE Unit layerblend5 input port prim is disabled 0 CONSTFRAME0 Unit layerblend5 input port prim is connected to output of unit constframe0 1 CONSTFRAME1 Unit layerblend5 input port prim is connected to output of unit constframe1 5 CONSTFRAME4 Unit layerblend5 input port prim is connected to output of unit constframe4 3 CONSTFRAME5 Unit layerblend5 input port prim is connected to output of unit constframe5 7 MATRIX4 Unit layerblend5 input port prim is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend5 input port prim is connected to output of unit gpscaler4 20 EXTSRC4 Unit layerblend5 input port prim is connected to output of unit extsrc4 9 LAYERBLEND4 Unit layerblend5 input port prim is connected to output of unit layerblend4 25 LAYERBLEND3 Unit layerblend5 input port prim is connected to output of unit layerblend3 24 LAYERBLEND2 Unit layerblend5 input port prim is connected to output of unit layerblend2 23 LAYERBLEND1 Unit layerblend5 input port prim is connected to output of unit layerblend1 22 LAYERBLEND5_SEC_SEL Selection of the source for the sec input of the layerblend5 module [12:8] read-write DISABLE Unit layerblend5 input port sec is disabled 0 FETCHDECODE4 Unit layerblend5 input port sec is connected to output of unit fetchdecode4 12 FETCHWARP1 Unit layerblend5 input port sec is connected to output of unit fetchwarp1 14 FETCHDECODE0 Unit layerblend5 input port sec is connected to output of unit fetchdecode0 17 MATRIX4 Unit layerblend5 input port sec is connected to output of unit matrix4 19 GPSCALER4 Unit layerblend5 input port sec is connected to output of unit gpscaler4 20 FETCHLAYER0 Unit layerblend5 input port sec is connected to output of unit fetchlayer0 11 FETCHLAYER1 Unit layerblend5 input port sec is connected to output of unit fetchlayer1 16 LAYERBLEND5_CLKEN Enable of layerblend5 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the register [endpoint_name]_clk must be set to 0x80. [25:24] read-write DISABLE Clock for layerblend5 is disabled 0 AUTOMATIC Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) 1 FULL Clock for layerblend5 is without gating 3 LAYERBLEND5_STATUS Status information for pixel engine configuration of layerblend5 0x1324 32 read-only 0x0 0x0 LAYERBLEND5_SEL Status of the connection of the layerblend5 module [18:16] read-only EXTDST0 layerblend5 module is used from extdst0 processing path 1 EXTDST4 layerblend5 module is used from extdst4 processing path 2 EXTDST1 layerblend5 module is used from extdst1 processing path 3 EXTDST5 layerblend5 module is used from extdst5 processing path 4 STORE4 layerblend5 module is used from store4 processing path 5 DISABLE layerblend5 module is not used 0 EXTSRC8_STATUS Status information for pixel engine configuration of extsrc8 0x1340 32 read-only 0x0 0x0 EXTSRC8_SEL Status of the connection of the extsrc8 module [18:16] read-only EXTDST0 extsrc8 module is used from extdst0 processing path 1 EXTDST4 extsrc8 module is used from extdst4 processing path 2 EXTDST1 extsrc8 module is used from extdst1 processing path 3 EXTDST5 extsrc8 module is used from extdst5 processing path 4 STORE4 extsrc8 module is used from store4 processing path 5 DISABLE extsrc8 module is not used 0 CONSTFRAME0 ConstFrame #0 (Content) 0x00002000 STATICCONTROL ConstFrame unit static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write FRAMEDIMENSIONS Output frame dimensions. 0x4 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width in pixels minus one. [13:0] read-write FRAMEHEIGHT Frame height in pixels minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). [31:31] read-write CONSTANTCOLOR Color of output frame. 0x8 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA Alpha component. [7:0] read-write CONSTANTBLUE Blue component. [15:8] read-write CONSTANTGREEN Green component. [23:16] read-write CONSTANTRED Red component. [31:24] read-write CONTROLTRIGGER ConstFrame unit trigger register 0xC 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START ConstFrame unit start register 0x10 32 write-only 0x0 0x0 START Writing a one starts processing, it is recommended to use this for debug purposes only. [0:0] write-only EXTDST0 ExtDst #0 (Content) 0x00002400 STATICCONTROL External Destination static control register 0x0 32 read-write 0x100 0x1101 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write KICK_MODE Operation mode of generated kick signal [8:8] read-write SOFTWARE kick generation by KICK field only 0 EXTERNAL kick signal from external allowed 1 PERFCOUNTMODE Value 1 enables performance counter mode, which does not generate an output frame but processes input data as fast as possible instead. Can be used to determine the maximum possible read-out performance of display buffers. [12:12] read-write CONTROL External Destination shadowed control register 0x4 32 read-write 0x0 0x1 GAMMAAPPLYENABLE Enable gamma conversion stage to apply gamma function. This gamma function converts the pixel data from linear color space to non-linear color space before they are output. [0:0] read-write SOFTWAREKICK External Destination software kick 0x8 32 write-only 0x0 0x0 KICK Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick. [0:0] write-only STATUS External Destination Unit current status 0xC 32 read-write 0x0 0x1 CNT_ERR_STS Pixel count error [0:0] read-write CONTROLWORD Value of last received control word 0x10 32 read-only 0x0 0x0 CW_VAL Value of last received control word [31:0] read-only CURPIXELCNT pixel count of currently running frame 0x14 32 read-only 0x0 0x0 C_XVAL value of horizontal pixel counter, internal counter counting from max-1 to 0 [15:0] read-only C_YVAL value of vertical line counter, internal counter counting from max-1 to 0 [31:16] read-only LASTPIXELCNT pixel count between last two control words 0x18 32 read-only 0x0 0x0 L_XVAL value of horizontal pixel counter [15:0] read-only L_YVAL value of vertical line counter [31:16] read-only PERFCOUNTER Performance counter result 0x1C 32 read-only 0x0 0xFFFFFFFF PERFRESULT Returns the performance counter value. Returns number of cycles of the last frame on the input. To calculate the performance divide the known number of pixels of the frame by this number. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only CONSTFRAME4 ConstFrame #4 (Safety) 0x00002800 STATICCONTROL ConstFrame unit static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write FRAMEDIMENSIONS Output frame dimensions. 0x4 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width in pixels minus one. [13:0] read-write FRAMEHEIGHT Frame height in pixels minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). [31:31] read-write CONSTANTCOLOR Color of output frame. 0x8 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA Alpha component. [7:0] read-write CONSTANTBLUE Blue component. [15:8] read-write CONSTANTGREEN Green component. [23:16] read-write CONSTANTRED Red component. [31:24] read-write CONTROLTRIGGER ConstFrame unit trigger register 0xC 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START ConstFrame unit start register 0x10 32 write-only 0x0 0x0 START Writing a one starts processing, it is recommended to use this for debug purposes only. [0:0] write-only EXTDST4 ExtDst #4 (Safety) 0x00002C00 STATICCONTROL External Destination static control register 0x0 32 read-write 0x100 0x1101 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write KICK_MODE Operation mode of generated kick signal [8:8] read-write SOFTWARE kick generation by KICK field only 0 EXTERNAL kick signal from external allowed 1 PERFCOUNTMODE Value 1 enables performance counter mode, which does not generate an output frame but processes input data as fast as possible instead. Can be used to determine the maximum possible read-out performance of display buffers. [12:12] read-write CONTROL External Destination shadowed control register 0x4 32 read-write 0x0 0x1 GAMMAAPPLYENABLE Enable gamma conversion stage to apply gamma function. This gamma function converts the pixel data from linear color space to non-linear color space before they are output. [0:0] read-write SOFTWAREKICK External Destination software kick 0x8 32 write-only 0x0 0x0 KICK Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick. [0:0] write-only STATUS External Destination Unit current status 0xC 32 read-write 0x0 0x1 CNT_ERR_STS Pixel count error [0:0] read-write CONTROLWORD Value of last received control word 0x10 32 read-only 0x0 0x0 CW_VAL Value of last received control word [31:0] read-only CURPIXELCNT pixel count of currently running frame 0x14 32 read-only 0x0 0x0 C_XVAL value of horizontal pixel counter, internal counter counting from max-1 to 0 [15:0] read-only C_YVAL value of vertical line counter, internal counter counting from max-1 to 0 [31:16] read-only LASTPIXELCNT pixel count between last two control words 0x18 32 read-only 0x0 0x0 L_XVAL value of horizontal pixel counter [15:0] read-only L_YVAL value of vertical line counter [31:16] read-only PERFCOUNTER Performance counter result 0x1C 32 read-only 0x0 0xFFFFFFFF PERFRESULT Returns the performance counter value. Returns number of cycles of the last frame on the input. To calculate the performance divide the known number of pixels of the frame by this number. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only CONSTFRAME1 ConstFrame #1 (Content) 0x00003000 STATICCONTROL ConstFrame unit static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write FRAMEDIMENSIONS Output frame dimensions. 0x4 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width in pixels minus one. [13:0] read-write FRAMEHEIGHT Frame height in pixels minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). [31:31] read-write CONSTANTCOLOR Color of output frame. 0x8 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA Alpha component. [7:0] read-write CONSTANTBLUE Blue component. [15:8] read-write CONSTANTGREEN Green component. [23:16] read-write CONSTANTRED Red component. [31:24] read-write CONTROLTRIGGER ConstFrame unit trigger register 0xC 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START ConstFrame unit start register 0x10 32 write-only 0x0 0x0 START Writing a one starts processing, it is recommended to use this for debug purposes only. [0:0] write-only EXTDST1 ExtDst #1 (Content) 0x00003400 STATICCONTROL External Destination static control register 0x0 32 read-write 0x100 0x1101 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write KICK_MODE Operation mode of generated kick signal [8:8] read-write SOFTWARE kick generation by KICK field only 0 EXTERNAL kick signal from external allowed 1 PERFCOUNTMODE Value 1 enables performance counter mode, which does not generate an output frame but processes input data as fast as possible instead. Can be used to determine the maximum possible read-out performance of display buffers. [12:12] read-write CONTROL External Destination shadowed control register 0x4 32 read-write 0x0 0x1 GAMMAAPPLYENABLE Enable gamma conversion stage to apply gamma function. This gamma function converts the pixel data from linear color space to non-linear color space before they are output. [0:0] read-write SOFTWAREKICK External Destination software kick 0x8 32 write-only 0x0 0x0 KICK Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick. [0:0] write-only STATUS External Destination Unit current status 0xC 32 read-write 0x0 0x1 CNT_ERR_STS Pixel count error [0:0] read-write CONTROLWORD Value of last received control word 0x10 32 read-only 0x0 0x0 CW_VAL Value of last received control word [31:0] read-only CURPIXELCNT pixel count of currently running frame 0x14 32 read-only 0x0 0x0 C_XVAL value of horizontal pixel counter, internal counter counting from max-1 to 0 [15:0] read-only C_YVAL value of vertical line counter, internal counter counting from max-1 to 0 [31:16] read-only LASTPIXELCNT pixel count between last two control words 0x18 32 read-only 0x0 0x0 L_XVAL value of horizontal pixel counter [15:0] read-only L_YVAL value of vertical line counter [31:16] read-only PERFCOUNTER Performance counter result 0x1C 32 read-only 0x0 0xFFFFFFFF PERFRESULT Returns the performance counter value. Returns number of cycles of the last frame on the input. To calculate the performance divide the known number of pixels of the frame by this number. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only CONSTFRAME5 ConstFrame #5 (Safety) 0x00003800 STATICCONTROL ConstFrame unit static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write FRAMEDIMENSIONS Output frame dimensions. 0x4 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width in pixels minus one. [13:0] read-write FRAMEHEIGHT Frame height in pixels minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). [31:31] read-write CONSTANTCOLOR Color of output frame. 0x8 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA Alpha component. [7:0] read-write CONSTANTBLUE Blue component. [15:8] read-write CONSTANTGREEN Green component. [23:16] read-write CONSTANTRED Red component. [31:24] read-write CONTROLTRIGGER ConstFrame unit trigger register 0xC 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START ConstFrame unit start register 0x10 32 write-only 0x0 0x0 START Writing a one starts processing, it is recommended to use this for debug purposes only. [0:0] write-only EXTDST5 ExtDst #5 (Safety) 0x00003C00 STATICCONTROL External Destination static control register 0x0 32 read-write 0x100 0x1101 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write KICK_MODE Operation mode of generated kick signal [8:8] read-write SOFTWARE kick generation by KICK field only 0 EXTERNAL kick signal from external allowed 1 PERFCOUNTMODE Value 1 enables performance counter mode, which does not generate an output frame but processes input data as fast as possible instead. Can be used to determine the maximum possible read-out performance of display buffers. [12:12] read-write CONTROL External Destination shadowed control register 0x4 32 read-write 0x0 0x1 GAMMAAPPLYENABLE Enable gamma conversion stage to apply gamma function. This gamma function converts the pixel data from linear color space to non-linear color space before they are output. [0:0] read-write SOFTWAREKICK External Destination software kick 0x8 32 write-only 0x0 0x0 KICK Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick. [0:0] write-only STATUS External Destination Unit current status 0xC 32 read-write 0x0 0x1 CNT_ERR_STS Pixel count error [0:0] read-write CONTROLWORD Value of last received control word 0x10 32 read-only 0x0 0x0 CW_VAL Value of last received control word [31:0] read-only CURPIXELCNT pixel count of currently running frame 0x14 32 read-only 0x0 0x0 C_XVAL value of horizontal pixel counter, internal counter counting from max-1 to 0 [15:0] read-only C_YVAL value of vertical line counter, internal counter counting from max-1 to 0 [31:16] read-only LASTPIXELCNT pixel count between last two control words 0x18 32 read-only 0x0 0x0 L_XVAL value of horizontal pixel counter [15:0] read-only L_YVAL value of vertical line counter [31:16] read-only PERFCOUNTER Performance counter result 0x1C 32 read-only 0x0 0xFFFFFFFF PERFRESULT Returns the performance counter value. Returns number of cycles of the last frame on the input. To calculate the performance divide the known number of pixels of the frame by this number. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only EXTSRC4 ExtSrc #0 (Capture) 0x00004000 STATICCONTROL ExtSrc static control register 0x0 32 read-write 0x0 0x101 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write STARTSEL Start select selects the mode to start processing operations. [8:8] read-write INPUT Free running mode, use the incoming command word as trigger to start processing. 0 LOCAL Keep to local start configuration, use external kick or SW trigger to start processing. The behavior is similar to fetch units. 1 CLIPWINDOWOFFSET Clip window offset, to generate a clipping of the frame. It has to be within the input frame. 0x4 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWXOFFSET Clip window offset in X direction, relative to the frame origin. [13:0] read-write CLIPWINDOWYOFFSET Clip window offset in Y direction, relative to the frame origin. [29:16] read-write CLIPWINDOWDIMENSION Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame. 0x8 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH Clip window width in pixels minus one. [13:0] read-write CLIPWINDOWHEIGHT Clip window height in pixels minus one. [29:16] read-write COLORCOMPONENTBITS Color component size of raw input data. Please note that the width must be equal or lower than the output width. 0xC 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA Component size of alpha channel [0-8]. [3:0] read-write COMPONENTBITSBLUE Component size of blue channel [0-10]. [11:8] read-write COMPONENTBITSGREEN Component size of green channel [0-10]. [19:16] read-write COMPONENTBITSRED Component size of red channel [0-10]. [27:24] read-write ITUFORMAT When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT Color component offset of raw input data. 0x10 32 read-write 0x10080018 0x3F3F3F3F COMPONENTSHIFTALPHA Offset for alpha component. [5:0] read-write COMPONENTSHIFTBLUE Offset for blue component. [13:8] read-write COMPONENTSHIFTGREEN Offset for green component. [21:16] read-write COMPONENTSHIFTRED Offset for red component. [29:24] read-write CONSTANTCOLOR Constant color register 0x14 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA Alpha. [7:0] read-write CONSTANTBLUE Blue or V (chroma). [15:8] read-write CONSTANTGREEN Green or U (chroma). [23:16] read-write CONSTANTRED Red or Y (luma). [31:24] read-write CONTROL Common control settings. 0x18 32 read-write 0x1000 0x17FF1 CLIPWINDOWENABLE Value 1 enables the clip window feature. [0:0] read-write RASTERMODE Selects a method how generate output samples from input stream. [4:4] read-write NORMAL Input stream is RGB(A) or YUV 4:4:4. 0 YUV422 Input stream is packed YUV 4:2:2. 1 YUV422UPSAMPLINGMODE Selects a method for horizontal up-sampling when RasterMode is YUV422. [5:5] read-write REPLICATE Replicate mode for interspersed samples (UV samples between Y samples). 0 INTERPOLATE Interpolate mode for coaligned samples (UV samples at Y sample positions). 1 YUVCONVERSIONMODE Enables different kind of YUV to RGB conversions. [7:6] read-write OFF No conversion. Input data must be RGB. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 RGBALPHASRCENABLE Value 1 enables source alpha (extracted from input stream) for RGB pre-multiply. When disabled source alpha is set to 1. [8:8] read-write RGBALPHACONSTENABLE Value 1 enables constant alpha (ConstAlpha field) for RGB pre-multiply. When disabled constant alpha is set to 1. [9:9] read-write RGBALPHATRANSENABLE Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/TransEnable have no effect then. [11:11] read-write ALPHASRCENABLE Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [12:12] read-write ALPHACONSTENABLE Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [13:13] read-write ALPHATRANSENABLE Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [14:14] read-write GAMMAREMOVEENABLE Value 1 enables the stage to remove a gamma from RGB components. [16:16] read-write CONTROLTRIGGER ExtSrc unit trigger token generation 0x1C 32 write-only 0x0 0x0 SHDTOKGEN Write a 1 to this field for the extsrc unit to perform a shadow load with the next start of operation and set the rld bit in the start of frame control word (generate shadow load token for subsequent units). [0:0] write-only START ExtSrc unit start register 0x20 32 write-only 0x0 0x0 START Writing a one starts processing, use this only for debug purposes. [0:0] write-only STORE4 Store #0 (Capture) 0x00004400 STATICCONTROL Store unit static control register. 0x0 32 read-write 0x0 0x111 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write SINGLEFRAMEOPERATION If this field and ShdEn are enabled, only frames with reload bit in command word are written to AXI, other frames are still consumed. If disabled all frames are writen to AXI [4:4] read-write BASEADDRESSAUTOUPDATE If enabled (value 1) the base address is automatically updated at the start of each frame. This update is then executed independently of the ShdEn setting. When disabled ShdEn controls the update of the base address operation register. [8:8] read-write BURSTBUFFERMANAGEMENT Burst Buffer setup register. 0x4 32 read-write 0x400 0x1F00 SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. Please note that SetBurstLength has to be smaller or equal to MaxBurstLength. Only a power of two may be specified as burst length. Please set this to at least 2 for 64bit pixels, otherwise performance will suffer. [12:8] read-write RINGBUFSTARTADDR Ring buffer setup for destination. 0x8 32 read-write 0x0 0xFFFFFFFF RINGBUFSTARTADDR Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes. [31:0] read-write RINGBUFWRAPADDR Ring buffer setup for destination. 0xC 32 read-write 0x0 0xFFFFFFFF RINGBUFWRAPADDR End address of the ring buffer (last byte of the buffer plus one). [31:0] read-write BASEADDRESS Destination buffer base address. 0x10 32 read-write 0x0 0xFFFFFFFF BASEADDRESS Byte aligned start address of the destination buffer. For 32 bit pixels BaseAddress[1:0] must be set 0 and for 16 bit pixels BaseAddress[0] must be set 0. [31:0] read-write DESTINATIONBUFFERATTRIBUTES Destination buffer attributes. 0x14 32 read-write 0x200004FF 0x7F01FFFF STRIDE Destination buffer stride in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [16:0] read-write BITSPERPIXEL Size of a pixel in the destination buffer in bits. Has to be a power of two, 18 or 24. When 64 bit is selected, input pixels are converted into a 32 bit value that is replicated into low and high word of the 64 bit output. Set SetBurstLength at least to 2 in that case to get best possible performance. [30:24] read-write DESTINATIONBUFFERDIMENSION Destination buffer dimension. 0x18 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH Width of the destination buffer in pixels minus one. [13:0] read-write LINECOUNT Number of lines of the destination buffer in pixels minus one. [29:16] read-write FRAMEOFFSET Offset between destination frame and buffer. 0x1C 32 read-write 0x0 0x7FFF7FFF FRAMEXOFFSET Horizontal offset (X). (format is signed integer) [14:0] read-write FRAMEYOFFSET Vertical offset (Y). (format is signed integer) [30:16] read-write COLORCOMPONENTBITS Color component size of destination buffer 0x20 32 read-write 0x8080808 0xF0F0F0F COMPONENTBITSALPHA Alpha component bits. [3:0] read-write COMPONENTBITSBLUE Blue/V component bits. [11:8] read-write COMPONENTBITSGREEN Green/U component bits. [19:16] read-write COMPONENTBITSRED Red/Y component bits. [27:24] read-write COLORCOMPONENTSHIFT Color component offset of destination buffer. 0x24 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA Alpha component shift. [4:0] read-write COMPONENTSHIFTBLUE Blue/V component shift. [12:8] read-write COMPONENTSHIFTGREEN Green/U component shift. [20:16] read-write COMPONENTSHIFTRED Red/Y component shift. [28:24] read-write CONTROL Store unit dynamic control register 0x28 32 read-write 0x0 0x3F10F3 COLORDITHERENABLE Controls whether spatial dithering (value 1) or LSB truncation (value 0) is used when ComponentBitsRed/Green/Blue is smaller than 10 bits. [0:0] read-write ALPHADITHERENABLE Controls whether spatial dithering (value 1) or LSB truncation (value 0) is used when ComponentBitsAlpha is smaller than 8 bits. [1:1] read-write DITHEROFFSET Dither offset that is additionally applied to the spatial offset, which is internally generated from the pixel position. Can be used by SW to generate image sequences with temporal dithering. [7:4] read-write GAMMAAPPLYENABLE Enable gamma conversion stage to apply gamma function. This gamma function converts the pixel data from linear color space to non-linear color space before writing it to AXI. [12:12] read-write YUVCONVERSIONMODE Enables different kind of RGB to YUV conversions. [17:16] read-write OFF No conversion. Input data must be RGB. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 RASTERMODE Selects a method for destination buffer data from input pixels. [19:18] read-write NORMAL RGBA or YUV 4:4:4 pixel buffer. 0 YUV422 Packed YUV 4:2:2 pixel buffer. Effect is that U samples are written for pixels with even and V samples for odd column index only. So BitsPerPixel must be set to the size that a pair of YU or YV has in memory (most typically 16 bits). All correlated widths and horizontal offsets must be even. 1 ENCODE RLAD compressed bit stream. 2 YUV422DOWNSAMPLINGMODE Selects a method for horizontal down-sampling when RasterMode is YUV422. [21:20] read-write NEAREST Nearest mode. Discards all odd samples, outputs even samples. 0 COALIGNED Linear coaligned mode. 3 nearest UV samples are combined in linear filter to get one output sample. 1 INTERSPERSED Linear interspersed mode. 2 nearest UV samples are combined in linear filter to get one output sample. 2 ENCODECONTROL Control options for RLAD compression. 0x2C 32 read-write 0x88880001 0xFFFF0001 COMPRESSIONMODE Algorithm to use for compression. [0:0] read-write RLAD Run-Length Adaptive Dithering (lossy compression). 0 RLAD_UNIFORM Run-Length Adaptive Dithering (lossy compression; uniform package size). 1 RLADCOMPBITSRED Maximum for average number of bits per compressed pixel for Red or Y (luma) channel. [19:16] read-write RLADCOMPBITSGREEN Maximum for average number of bits per compressed pixel for Green or U (chroma) channel. [23:20] read-write RLADCOMPBITSBLUE Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel. [27:24] read-write RLADCOMPBITSALPHA Maximum for average number of bits per compressed pixel for Alpha channel. [31:28] read-write DESTINATIONBUFFERLENGTH Destination buffer length for compressed data. 0x30 32 read-write 0x0 0x1FFFFFFF RLEWORDSMAX N/A [28:0] read-write START Store unit start register 0x34 32 write-only 0x0 0x0 START Writing a one starts processing of the pixel engine. [0:0] write-only ENCODERSTATUS Status information of the RLAD encoder. 0x38 32 read-write 0x1FFFFFFF 0x9FFFFFFF RLEWORDS Number of 32-bit words minus one that was used for the compressed buffer. [28:0] read-only BUFFERTOOSMALL The buffer size given by RLEWordsMax is too small. Not the complete input frame could be encoded. [31:31] read-write WRITEADDRESS Ring buffer synchronization. 0x3C 32 read-only 0x0 0xFFFFFFFF WRITEADDRESS Last burst address that was written to the destination buffer. [31:0] read-only FRAMEPROPERTIES Ring buffer synchronization. 0x40 32 read-only 0x0 0x1 FIELDID Field identifier for interlaced video streams (0/1 = even/odd line indices of progressive frame). Status is updated with begin of a new field. [0:0] read-only BURSTBUFFERPROPERTIES Burst Buffer Property register 0x44 32 read-only 0x0 0x0 MAXBURSTLENGTH Maximum Burst Length that can be configured. [12:8] read-only LASTCONTROLWORD Shows the last control word received 0x48 32 read-only 0x0 0xFFFFFFFF L_VAL Shows the last control word received from the pixel engine. If a 39 bit pixel channel is connected, the mapping is as follows: l_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only PERFCOUNTER Performance counter result 0x4C 32 read-only 0x0 0xFFFFFFFF PERFRESULT Returns the performance counter value. Please note that a sw reset during a frame can potentially produce invalid results in the first frame afterwards. For debug purposes only, read when stable only, otherwise read data might be corrupted. [31:0] read-only FETCHLAYER0 FetchLayer #0 (Display) 0x00004800 STATICCONTROL Common static control options. 0x0 32 read-write 0xFF000002 0xFFFF0003 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write LBHSHDEN Enables shadowing of LBH configuration signals. [1:1] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write SHDLDREQSTICKY Shadow load request flags for each layer (always load). See description of register TriggerEnable for further information. [31:24] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 BASEADDRESS0 Source buffer base address of layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0xC 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x10 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x14 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x18 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x1C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x20 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x24 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x28 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x2C 32 read-write 0xB8000008 0xFFFF7DDF PALETTEENABLE0 Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower bits of the lookup index are read from memory (PaletteIdWidth0), upper bits are set to index of this layer. Palette output is extended by upper bits of index word read from memory (e.g. to store alpha together with index). Result is mapped to color channels according to ColorComponentBits/Shift settings. [0:0] read-write TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE0 Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [3:3] read-write ALPHACONSTENABLE0 Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [4:4] read-write ALPHATRANSENABLE0 Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [6:6] read-write RGBALPHASRCENABLE0 Value 1 enables source alpha (stored together with color component in the source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. [7:7] read-write RGBALPHACONSTENABLE0 Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. [8:8] read-write RGBALPHATRANSENABLE0 Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB0 When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no effect then. [11:11] read-write YUVCONVERSIONMODE0 Enables different kind of YUV to RGB conversions. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE0 Value 1 enables the stage to remove a gamma from RGB components. [14:14] read-write PALETTEOFFSET0 Palette may contain multiple areas. This offset shows to the starting position of the currently used area. [26:16] read-write PALETTEIDWIDTH0 Number minus one of least significant bits of pixel data read from the source buffer that are used as index value for color palette look-up. [29:27] read-write CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write BASEADDRESS1 Source buffer base address of layer 1. 0x30 32 read-write 0x0 0xFFFFFFFF BASEADDRESS1 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES1 Source buffer attributes for layer 1. 0x34 32 read-write 0x200003 0x3FFFFF STRIDE1 See Stride0. [15:0] read-write BITSPERPIXEL1 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION1 Source buffer dimensions of layer 1, 0x38 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH1 See LineWidth0. [13:0] read-write LINECOUNT1 See LineCount0. [29:16] read-write COLORCOMPONENTBITS1 Size of color components for RGB, YUV and index formats (layer 1). 0x3C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA1 Alpha. [3:0] read-write COMPONENTBITSBLUE1 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN1 Green and U (chroma). [19:16] read-write COMPONENTBITSRED1 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT1 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT1 Bit position of color components for RGB, YUV and index formats (layer 1). 0x40 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA1 Alpha. [4:0] read-write COMPONENTSHIFTBLUE1 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN1 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED1 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET1 Position of layer 1 within the destination frame. 0x44 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET1 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET1 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET1 Clip window position for layer 1. 0x48 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET1 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET1 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS1 Clip window size for layer 1. 0x4C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH1 Width. [13:0] read-write CLIPWINDOWHEIGHT1 Height. [29:16] read-write CONSTANTCOLOR1 Constant color for layer 1. 0x50 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA1 Alpha. [7:0] read-write CONSTANTBLUE1 Blue and V (chroma). [15:8] read-write CONSTANTGREEN1 Green and U (chroma). [23:16] read-write CONSTANTRED1 Red and Y (luma). [31:24] read-write LAYERPROPERTY1 Common properties of layer 1. 0x54 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE1 See PaletteEnable0. [0:0] read-write TILEMODE1 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE1 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE1 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE1 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE1 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE1 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE1 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB1 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE1 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE1 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET1 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH1 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE1 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE1 See SourceBufferEnable0. [31:31] read-write BASEADDRESS2 Source buffer base address of layer 2. 0x58 32 read-write 0x0 0xFFFFFFFF BASEADDRESS2 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES2 Source buffer attributes for layer 2. 0x5C 32 read-write 0x200003 0x3FFFFF STRIDE2 See Stride0. [15:0] read-write BITSPERPIXEL2 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION2 Source buffer dimension of layer 2. 0x60 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH2 See LineWidth0. [13:0] read-write LINECOUNT2 See LineCount0. [29:16] read-write COLORCOMPONENTBITS2 Size of color components for RGB, YUV and index formats (layer 2). 0x64 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA2 Alpha. [3:0] read-write COMPONENTBITSBLUE2 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN2 Green and U (chroma). [19:16] read-write COMPONENTBITSRED2 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT2 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT2 Bit position of color components for RGB, YUV and index formats (layer 2). 0x68 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA2 Alpha. [4:0] read-write COMPONENTSHIFTBLUE2 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN2 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED2 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET2 Position of layer 2 within the destination frame. 0x6C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET2 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET2 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET2 Clip window position for layer 2. 0x70 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET2 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET2 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS2 Clip window size for layer 2. 0x74 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH2 Width. [13:0] read-write CLIPWINDOWHEIGHT2 Height. [29:16] read-write CONSTANTCOLOR2 Constant color for layer 2. 0x78 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA2 Alpha. [7:0] read-write CONSTANTBLUE2 Blue and V (chroma). [15:8] read-write CONSTANTGREEN2 Green and U (chroma). [23:16] read-write CONSTANTRED2 Red and Y (luma). [31:24] read-write LAYERPROPERTY2 Common properties of layer 2. 0x7C 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE2 See PaletteEnable0. [0:0] read-write TILEMODE2 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE2 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE2 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE2 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE2 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE2 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE2 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB2 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE2 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE2 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET2 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH2 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE2 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE2 See SourceBufferEnable0. [31:31] read-write BASEADDRESS3 Source buffer base address of layer 3. 0x80 32 read-write 0x0 0xFFFFFFFF BASEADDRESS3 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES3 Source buffer attributes for layer 3. 0x84 32 read-write 0x200003 0x3FFFFF STRIDE3 See Stride0. [15:0] read-write BITSPERPIXEL3 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION3 Source buffer dimension of layer 3. 0x88 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH3 See LineWidth0. [13:0] read-write LINECOUNT3 See LineCount0. [29:16] read-write COLORCOMPONENTBITS3 Size of color components for RGB, YUV and index formats (layer 3). 0x8C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA3 Alpha. [3:0] read-write COMPONENTBITSBLUE3 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN3 Green and U (chroma). [19:16] read-write COMPONENTBITSRED3 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT3 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT3 Bit position of color components for RGB, YUV and index formats (layer 3). 0x90 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA3 Alpha. [4:0] read-write COMPONENTSHIFTBLUE3 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN3 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED3 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET3 Position of layer 3 within the destination frame. 0x94 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET3 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET3 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET3 Clip window position for layer 3. 0x98 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET3 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET3 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS3 Clip window size for layer 3. 0x9C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH3 Width. [13:0] read-write CLIPWINDOWHEIGHT3 Height. [29:16] read-write CONSTANTCOLOR3 Constant color for layer 3. 0xA0 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA3 Alpha. [7:0] read-write CONSTANTBLUE3 Blue and V (chroma). [15:8] read-write CONSTANTGREEN3 Green and U (chroma). [23:16] read-write CONSTANTRED3 Red and Y (luma). [31:24] read-write LAYERPROPERTY3 Common properties of layer 3. 0xA4 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE3 See PaletteEnable0. [0:0] read-write TILEMODE3 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE3 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE3 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE3 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE3 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE3 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE3 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB3 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE3 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE3 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET3 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH3 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE3 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE3 See SourceBufferEnable0. [31:31] read-write BASEADDRESS4 Source buffer base address of layer 4. 0xA8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS4 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES4 Source buffer attributes for layer 4. 0xAC 32 read-write 0x200003 0x3FFFFF STRIDE4 See Stride0. [15:0] read-write BITSPERPIXEL4 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION4 Source buffer dimension of layer 4. 0xB0 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH4 See LineWidth0. [13:0] read-write LINECOUNT4 See LineCount0. [29:16] read-write COLORCOMPONENTBITS4 Size of color components for RGB, YUV and index formats (layer 4). 0xB4 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA4 Alpha. [3:0] read-write COMPONENTBITSBLUE4 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN4 Green and U (chroma). [19:16] read-write COMPONENTBITSRED4 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT4 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT4 Bit position of color components for RGB, YUV and index formats (layer 4). 0xB8 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA4 Alpha. [4:0] read-write COMPONENTSHIFTBLUE4 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN4 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED4 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET4 Position of layer 4 within the destination frame. 0xBC 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET4 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET4 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET4 Clip window position for layer 4. 0xC0 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET4 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET4 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS4 Clip window size for layer 4. 0xC4 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH4 Width. [13:0] read-write CLIPWINDOWHEIGHT4 Height. [29:16] read-write CONSTANTCOLOR4 Constant color for layer 4. 0xC8 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA4 Alpha. [7:0] read-write CONSTANTBLUE4 Blue and V (chroma). [15:8] read-write CONSTANTGREEN4 Green and U (chroma). [23:16] read-write CONSTANTRED4 Red and Y (luma). [31:24] read-write LAYERPROPERTY4 Common properties of layer 4. 0xCC 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE4 See PaletteEnable0. [0:0] read-write TILEMODE4 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE4 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE4 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE4 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE4 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE4 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE4 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB4 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE4 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE4 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET4 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH4 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE4 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE4 See SourceBufferEnable0. [31:31] read-write BASEADDRESS5 Source buffer base address of layer 5. 0xD0 32 read-write 0x0 0xFFFFFFFF BASEADDRESS5 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES5 Source buffer attributes for layer 5. 0xD4 32 read-write 0x200003 0x3FFFFF STRIDE5 See Stride0. [15:0] read-write BITSPERPIXEL5 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION5 Source buffer dimension of layer 5. 0xD8 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH5 See LineWidth0. [13:0] read-write LINECOUNT5 See LineCount0. [29:16] read-write COLORCOMPONENTBITS5 Size of color components for RGB, YUV and index formats (layer 5). 0xDC 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA5 Alpha. [3:0] read-write COMPONENTBITSBLUE5 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN5 Green and U (chroma). [19:16] read-write COMPONENTBITSRED5 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT5 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT5 Bit position of color components for RGB, YUV and index formats (layer 5). 0xE0 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA5 Alpha. [4:0] read-write COMPONENTSHIFTBLUE5 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN5 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED5 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET5 Position of layer 5 within the destination frame. 0xE4 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET5 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET5 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET5 Clip window position for layer 5. 0xE8 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET5 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET5 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS5 Clip window size for layer 5. 0xEC 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH5 Width. [13:0] read-write CLIPWINDOWHEIGHT5 Height. [29:16] read-write CONSTANTCOLOR5 Constant color for layer 5. 0xF0 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA5 Alpha. [7:0] read-write CONSTANTBLUE5 Blue and V (chroma). [15:8] read-write CONSTANTGREEN5 Green and U (chroma). [23:16] read-write CONSTANTRED5 Red and Y (luma). [31:24] read-write LAYERPROPERTY5 Common properties of layer 5. 0xF4 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE5 See PaletteEnable0. [0:0] read-write TILEMODE5 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE5 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE5 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE5 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE5 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE5 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE5 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB5 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE5 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE5 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET5 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH5 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE5 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE5 See SourceBufferEnable0. [31:31] read-write BASEADDRESS6 Source buffer base address of layer 6. 0xF8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS6 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES6 Source buffer attributes for layer 6. 0xFC 32 read-write 0x200003 0x3FFFFF STRIDE6 See Stride0. [15:0] read-write BITSPERPIXEL6 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION6 Source buffer dimension of layer 6. 0x100 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH6 See LineWidth0. [13:0] read-write LINECOUNT6 See LineCount0. [29:16] read-write COLORCOMPONENTBITS6 Size of color components for RGB, YUV and index formats (layer 6). 0x104 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA6 Alpha. [3:0] read-write COMPONENTBITSBLUE6 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN6 Green and U (chroma). [19:16] read-write COMPONENTBITSRED6 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT6 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT6 Bit position of color components for RGB, YUV and index formats (layer 6). 0x108 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA6 Alpha. [4:0] read-write COMPONENTSHIFTBLUE6 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN6 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED6 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET6 Position of layer 1 within the destination frame. 0x10C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET6 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET6 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET6 Clip window position for layer 6. 0x110 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET6 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET6 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS6 Clip window size for layer 6. 0x114 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH6 Width. [13:0] read-write CLIPWINDOWHEIGHT6 Height. [29:16] read-write CONSTANTCOLOR6 Constant color for layer 6. 0x118 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA6 Alpha. [7:0] read-write CONSTANTBLUE6 Blue and V (chroma). [15:8] read-write CONSTANTGREEN6 Green and U (chroma). [23:16] read-write CONSTANTRED6 Red and Y (luma). [31:24] read-write LAYERPROPERTY6 Common properties of layer 6. 0x11C 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE6 See PaletteEnable0. [0:0] read-write TILEMODE6 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE6 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE6 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE6 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE6 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE6 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE6 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB6 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE6 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE6 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET6 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH6 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE6 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE6 See SourceBufferEnable0. [31:31] read-write BASEADDRESS7 Source buffer base address of layer 7. 0x120 32 read-write 0x0 0xFFFFFFFF BASEADDRESS7 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES7 Source buffer stride for layer 7. 0x124 32 read-write 0x200003 0x3FFFFF STRIDE7 See Stride0. [15:0] read-write BITSPERPIXEL7 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION7 Source buffer dimension of layer 7. 0x128 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH7 See LineWidth0. [13:0] read-write LINECOUNT7 See LineCount0. [29:16] read-write COLORCOMPONENTBITS7 Size of color components for RGB, YUV and index formats (layer 7). 0x12C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA7 Alpha. [3:0] read-write COMPONENTBITSBLUE7 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN7 Green and U (chroma). [19:16] read-write COMPONENTBITSRED7 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT7 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT7 Bit position of color components for RGB, YUV and index formats (layer 7). 0x130 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA7 Alpha. [4:0] read-write COMPONENTSHIFTBLUE7 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN7 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED7 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET7 Position of layer 7 within the destination frame. 0x134 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET7 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET7 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET7 Clip window position for layer 7. 0x138 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET7 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET7 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS7 Clip window size for layer 7. 0x13C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH7 Width. [13:0] read-write CLIPWINDOWHEIGHT7 Height. [29:16] read-write CONSTANTCOLOR7 Constant color for layer 7. 0x140 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA7 Alpha. [7:0] read-write CONSTANTBLUE7 Blue and V (chroma). [15:8] read-write CONSTANTGREEN7 Green and U (chroma). [23:16] read-write CONSTANTRED7 Red and Y (luma). [31:24] read-write LAYERPROPERTY7 Common properties of layer 7. 0x144 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE7 See PaletteEnable0. [0:0] read-write TILEMODE7 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE7 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE7 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE7 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE7 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE7 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE7 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB7 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE7 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE7 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET7 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH7 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE7 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE7 See SourceBufferEnable0. [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x148 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x14C 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write CONTROL Shared common control settings for all layers. 0x150 32 read-write 0x10000 0x70F0080 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 CLIPLAYER Index of the layer which is used to fill the clipping area of the frame layout when ClipColor is set to LAYER. The selected layer must be enabled (LayerEnable). [19:17] read-write LINEBUFLAYER Index of the layer which used as a memory based linebuffer. Only has an effect if this fetch unit is connected to a store unit for linebuffer handshake and linebuffer handshake is enabled. [26:24] read-write TRIGGERENABLE Shadow load enable flags for all layers. 0x154 32 read-write 0x0 0xFF SHDLDREQ Shadow load request flags for each layer (one time load). [7:0] read-write CONTROLTRIGGER Shadow load trigger. 0x158 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x15C 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x160 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 BURSTBUFFERPROPERTIES Burst buffer properties. 0x164 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only STATUS Status information. 0x168 32 read-write 0x0 0x11 WRITETIMEOUT Timeout detected when writing to the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [0:0] read-write READTIMEOUT Timeout detected when reading from the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [4:4] read-write FETCHDECODE4 FetchDecode #4 (Capture) 0x00004C00 STATICCONTROL Common static control options. 0x0 32 read-write 0x2 0xFF0003 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write LBHSHDEN Enables shadowing of LBH configuration signals. [1:1] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 RINGBUFSTARTADDR0 Ring buffer setup for layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF RINGBUFSTARTADDR0 Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes. [31:0] read-write RINGBUFWRAPADDR0 Ring buffer setup for layer 0. 0xC 32 read-write 0x0 0xFFFFFFFF RINGBUFWRAPADDR0 End address of the ring buffer (last byte of the buffer plus one). [31:0] read-write FRAMEPROPERTIES0 Frame property setup for layer 0. 0x10 32 read-write 0x0 0x1 FIELDID0 Field identifier that is generated for subsequent units (0 = progressive frame or interlaced field with even line indices, 1 = odd field). [0:0] read-write BASEADDRESS0 Source buffer base address of layer 0. 0x14 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0x18 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x1C 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x20 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x24 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x28 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x2C 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x30 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x34 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x38 32 read-write 0xB8000008 0xFFFF7FFF PALETTEENABLE0 Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower bits of the lookup index are read from memory (PaletteIdWidth0), upper bits are set to index of this layer. Palette output is extended by upper bits of index word read from memory (e.g. to store alpha together with index). Result is mapped to color channels according to ColorComponentBits/Shift settings. [0:0] read-write TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE0 Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [3:3] read-write ALPHACONSTENABLE0 Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [4:4] read-write ALPHAMASKENABLE0 Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. [5:5] read-write ALPHATRANSENABLE0 Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [6:6] read-write RGBALPHASRCENABLE0 Value 1 enables source alpha (stored together with color component in the source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. [7:7] read-write RGBALPHACONSTENABLE0 Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. [8:8] read-write RGBALPHAMASKENABLE0 Value 1 enables mask alpha (read by another Fetch unit from a separate alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be enabled for this field to have effect. [9:9] read-write RGBALPHATRANSENABLE0 Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB0 When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no effect then. [11:11] read-write YUVCONVERSIONMODE0 Enables different kind of YUV to RGB conversions. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE0 Value 1 enables the stage to remove a gamma from RGB components. [14:14] read-write PALETTEOFFSET0 Palette may contain multiple areas. This offset shows to the starting position of the currently used area. [26:16] read-write PALETTEIDWIDTH0 Number minus one of least significant bits of pixel data read from the source buffer that are used as index value for color palette look-up. [29:27] read-write CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x3C 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x40 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write DECODECONTROL Control options for RLAD decompression. 0x44 32 read-write 0x88880001 0xFFFF0003 COMPRESSIONMODE Algorithm that the encoder used for compression. [1:0] read-write RLAD Run-Length Adaptive Dithering (lossy compression). 0 RLAD_UNIFORM Run-Length Adaptive Dithering (lossy compression; uniform package size). 1 RLA Run-Length Adaptive (lossless compression). 2 RL Standard Run-Length. In contrary to other modes is in big endian format. 3 RLADCOMPBITSRED Maximum for average number of bits per compressed pixel for Red or Y (luma) channel. This must match the corresponding encoder setting. [19:16] read-write RLADCOMPBITSGREEN Maximum for average number of bits per compressed pixel for Green or U (chroma) channel. This must match the corresponding encoder setting. [23:20] read-write RLADCOMPBITSBLUE Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel. This must match the corresponding encoder setting. [27:24] read-write RLADCOMPBITSALPHA Maximum for average number of bits per compressed pixel for Alpha channel. This must match the corresponding encoder setting. [31:28] read-write SOURCEBUFFERLENGTH Source buffer length for compressed data. 0x48 32 read-write 0x0 0x1FFFFFFF RLEWORDS Number of 32-bit words minus one that are required to decode the run length encoded source buffer. [28:0] read-write CONTROL Shared common control settings for all layers. 0x4C 32 read-write 0x10000 0x100BF RASTERMODE Selects a method how to generate source buffer sample points. [2:0] read-write NORMAL [IBO only, for LBO use PERSPECTIVE with corresponding Geometry] First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. 0 DECODE [FetchDecode/FetchBlit only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). 1 ARBITRARY [FetchBlit/Warp only] Arbitrary warping (filter is active). Coordinates are read from frame input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. 2 PERSPECTIVE [FetchBlit only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. See also field Geometry to reduce coordinate amount. 3 YUV422 [FetchBlit/Decode only] Source buffer is packed YUV 422. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). All correllated window widths and horizontal offsets must be even. 4 INPUTSELECT Selects function for the frame input port. [4:3] read-write INACTIVE Not used. 0 COMPPACK Used for component packing (e.g. UV or source alpha buffer). 1 ALPHAMASK Used for RGB and alpha pre-multiply stage (mask alpha buffer). 2 COORDINATE Used for arbitrary warping (coordinate buffer). 3 YUV422UPSAMPLINGMODE Selects a method for horizontal up-sampling of YUV 422/420 input data. [5:5] read-write REPLICATE Replicate mode for interspersed samples (UV samples between Y samples). 0 INTERPOLATE Interpolate mode for coaligned samples (UV samples at Y sample positions). 1 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 CONTROLTRIGGER Shadow load trigger. 0x50 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x54 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x58 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 DECODERSTATUS Status information of the RLAD decoder. 0x5C 32 read-write 0x0 0x3 BUFFERTOOSMALL The buffer size given by RLEWords is too small. No complete output frame could be decoded. [0:0] read-write BUFFERTOOLARGE The buffer size given by RLEWords is too large. A complete output frame could be decoded, but more data was read than necessary. [1:1] read-write READADDRESS0 Ring buffer synchronization for layer 0. 0x60 32 read-only 0x0 0xFFFFFFFF READADDRESS0 Last burst address that was read from the layer's source buffer. [31:0] read-only BURSTBUFFERPROPERTIES Burst buffer properties. 0x64 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only STATUS Status information. 0x68 32 read-write 0x0 0x11 WRITETIMEOUT Timeout detected when writing to the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [0:0] read-write READTIMEOUT Timeout detected when reading from the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [4:4] read-write FETCHECO4 FetchEco #4 (Capture) 0x00005000 STATICCONTROL Common static control options. 0x0 32 read-write 0x0 0xFF0001 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 BASEADDRESS0 Source buffer base address of layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0xC 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x10 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x14 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x18 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x1C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x20 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x24 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x28 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x2C 32 read-write 0x80000000 0xC0000006 TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x30 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x34 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write CONTROL Shared common control settings for all layers. 0x38 32 read-write 0x10000 0x10080 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 CONTROLTRIGGER Shadow load trigger. 0x3C 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x40 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x44 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 BURSTBUFFERPROPERTIES Burst buffer properties. 0x48 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only FETCHWARP1 FetchWarp #1 (Display) 0x00005800 STATICCONTROL Common static control options. 0x0 32 read-write 0xFF000002 0xFFFF0003 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write LBHSHDEN Enables shadowing of LBH configuration signals. [1:1] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write SHDLDREQSTICKY Shadow load request flags for each layer (always load). See description of register TriggerEnable for further information. [31:24] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 BASEADDRESS0 Source buffer base address of layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0xC 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x10 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x14 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x18 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x1C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x20 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x24 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x28 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x2C 32 read-write 0x80000008 0xC0007FFE TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE0 Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [3:3] read-write ALPHACONSTENABLE0 Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [4:4] read-write ALPHAMASKENABLE0 Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. [5:5] read-write ALPHATRANSENABLE0 Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [6:6] read-write RGBALPHASRCENABLE0 Value 1 enables source alpha (stored together with color component in the source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. [7:7] read-write RGBALPHACONSTENABLE0 Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. [8:8] read-write RGBALPHAMASKENABLE0 Value 1 enables mask alpha (read by another Fetch unit from a separate alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be enabled for this field to have effect. [9:9] read-write RGBALPHATRANSENABLE0 Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB0 When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no effect then. [11:11] read-write YUVCONVERSIONMODE0 Enables different kind of YUV to RGB conversions. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE0 Value 1 enables the stage to remove a gamma from RGB components. [14:14] read-write CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write BASEADDRESS1 Source buffer base address of layer 1. 0x30 32 read-write 0x0 0xFFFFFFFF BASEADDRESS1 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES1 Source buffer attributes for layer 1. 0x34 32 read-write 0x200003 0x3FFFFF STRIDE1 See Stride0. [15:0] read-write BITSPERPIXEL1 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION1 Source buffer dimensions of layer 1, 0x38 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH1 See LineWidth0. [13:0] read-write LINECOUNT1 See LineCount0. [29:16] read-write COLORCOMPONENTBITS1 Size of color components for RGB, YUV and index formats (layer 1). 0x3C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA1 Alpha. [3:0] read-write COMPONENTBITSBLUE1 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN1 Green and U (chroma). [19:16] read-write COMPONENTBITSRED1 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT1 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT1 Bit position of color components for RGB, YUV and index formats (layer 1). 0x40 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA1 Alpha. [4:0] read-write COMPONENTSHIFTBLUE1 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN1 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED1 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET1 Position of layer 1 within the destination frame. 0x44 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET1 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET1 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET1 Clip window position for layer 1. 0x48 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET1 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET1 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS1 Clip window size for layer 1. 0x4C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH1 Width. [13:0] read-write CLIPWINDOWHEIGHT1 Height. [29:16] read-write CONSTANTCOLOR1 Constant color for layer 1. 0x50 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA1 Alpha. [7:0] read-write CONSTANTBLUE1 Blue and V (chroma). [15:8] read-write CONSTANTGREEN1 Green and U (chroma). [23:16] read-write CONSTANTRED1 Red and Y (luma). [31:24] read-write LAYERPROPERTY1 Common properties of layer 1. 0x54 32 read-write 0x8 0xC0007FFE TILEMODE1 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE1 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE1 See AlphaConstSelect0. [4:4] read-write ALPHAMASKENABLE1 See AlphaMaskSelect0. [5:5] read-write ALPHATRANSENABLE1 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE1 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE1 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHAMASKENABLE1 See RGBAlphaMaskSelect0. [9:9] read-write RGBALPHATRANSENABLE1 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB1 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE1 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE1 See GammaRemoveEnable0. [14:14] read-write CLIPWINDOWENABLE1 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE1 See SourceBufferEnable0. [31:31] read-write BASEADDRESS2 Source buffer base address of layer 2. 0x58 32 read-write 0x0 0xFFFFFFFF BASEADDRESS2 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES2 Source buffer attributes for layer 2. 0x5C 32 read-write 0x200003 0x3FFFFF STRIDE2 See Stride0. [15:0] read-write BITSPERPIXEL2 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION2 Source buffer dimension of layer 2. 0x60 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH2 See LineWidth0. [13:0] read-write LINECOUNT2 See LineCount0. [29:16] read-write COLORCOMPONENTBITS2 Size of color components for RGB, YUV and index formats (layer 2). 0x64 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA2 Alpha. [3:0] read-write COMPONENTBITSBLUE2 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN2 Green and U (chroma). [19:16] read-write COMPONENTBITSRED2 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT2 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT2 Bit position of color components for RGB, YUV and index formats (layer 2). 0x68 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA2 Alpha. [4:0] read-write COMPONENTSHIFTBLUE2 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN2 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED2 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET2 Position of layer 2 within the destination frame. 0x6C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET2 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET2 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET2 Clip window position for layer 2. 0x70 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET2 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET2 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS2 Clip window size for layer 2. 0x74 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH2 Width. [13:0] read-write CLIPWINDOWHEIGHT2 Height. [29:16] read-write CONSTANTCOLOR2 Constant color for layer 2. 0x78 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA2 Alpha. [7:0] read-write CONSTANTBLUE2 Blue and V (chroma). [15:8] read-write CONSTANTGREEN2 Green and U (chroma). [23:16] read-write CONSTANTRED2 Red and Y (luma). [31:24] read-write LAYERPROPERTY2 Common properties of layer 2. 0x7C 32 read-write 0x8 0xC0007FFE TILEMODE2 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE2 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE2 See AlphaConstSelect0. [4:4] read-write ALPHAMASKENABLE2 See AlphaMaskSelect0. [5:5] read-write ALPHATRANSENABLE2 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE2 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE2 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHAMASKENABLE2 See RGBAlphaMaskSelect0. [9:9] read-write RGBALPHATRANSENABLE2 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB2 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE2 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE2 See GammaRemoveEnable0. [14:14] read-write CLIPWINDOWENABLE2 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE2 See SourceBufferEnable0. [31:31] read-write BASEADDRESS3 Source buffer base address of layer 3. 0x80 32 read-write 0x0 0xFFFFFFFF BASEADDRESS3 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES3 Source buffer attributes for layer 3. 0x84 32 read-write 0x200003 0x3FFFFF STRIDE3 See Stride0. [15:0] read-write BITSPERPIXEL3 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION3 Source buffer dimension of layer 3. 0x88 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH3 See LineWidth0. [13:0] read-write LINECOUNT3 See LineCount0. [29:16] read-write COLORCOMPONENTBITS3 Size of color components for RGB, YUV and index formats (layer 3). 0x8C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA3 Alpha. [3:0] read-write COMPONENTBITSBLUE3 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN3 Green and U (chroma). [19:16] read-write COMPONENTBITSRED3 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT3 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT3 Bit position of color components for RGB, YUV and index formats (layer 3). 0x90 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA3 Alpha. [4:0] read-write COMPONENTSHIFTBLUE3 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN3 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED3 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET3 Position of layer 3 within the destination frame. 0x94 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET3 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET3 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET3 Clip window position for layer 3. 0x98 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET3 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET3 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS3 Clip window size for layer 3. 0x9C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH3 Width. [13:0] read-write CLIPWINDOWHEIGHT3 Height. [29:16] read-write CONSTANTCOLOR3 Constant color for layer 3. 0xA0 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA3 Alpha. [7:0] read-write CONSTANTBLUE3 Blue and V (chroma). [15:8] read-write CONSTANTGREEN3 Green and U (chroma). [23:16] read-write CONSTANTRED3 Red and Y (luma). [31:24] read-write LAYERPROPERTY3 Common properties of layer 3. 0xA4 32 read-write 0x8 0xC0007FFE TILEMODE3 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE3 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE3 See AlphaConstSelect0. [4:4] read-write ALPHAMASKENABLE3 See AlphaMaskSelect0. [5:5] read-write ALPHATRANSENABLE3 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE3 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE3 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHAMASKENABLE3 See RGBAlphaMaskSelect0. [9:9] read-write RGBALPHATRANSENABLE3 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB3 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE3 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE3 See GammaRemoveEnable0. [14:14] read-write CLIPWINDOWENABLE3 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE3 See SourceBufferEnable0. [31:31] read-write BASEADDRESS4 Source buffer base address of layer 4. 0xA8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS4 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES4 Source buffer attributes for layer 4. 0xAC 32 read-write 0x200003 0x3FFFFF STRIDE4 See Stride0. [15:0] read-write BITSPERPIXEL4 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION4 Source buffer dimension of layer 4. 0xB0 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH4 See LineWidth0. [13:0] read-write LINECOUNT4 See LineCount0. [29:16] read-write COLORCOMPONENTBITS4 Size of color components for RGB, YUV and index formats (layer 4). 0xB4 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA4 Alpha. [3:0] read-write COMPONENTBITSBLUE4 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN4 Green and U (chroma). [19:16] read-write COMPONENTBITSRED4 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT4 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT4 Bit position of color components for RGB, YUV and index formats (layer 4). 0xB8 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA4 Alpha. [4:0] read-write COMPONENTSHIFTBLUE4 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN4 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED4 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET4 Position of layer 4 within the destination frame. 0xBC 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET4 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET4 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET4 Clip window position for layer 4. 0xC0 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET4 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET4 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS4 Clip window size for layer 4. 0xC4 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH4 Width. [13:0] read-write CLIPWINDOWHEIGHT4 Height. [29:16] read-write CONSTANTCOLOR4 Constant color for layer 4. 0xC8 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA4 Alpha. [7:0] read-write CONSTANTBLUE4 Blue and V (chroma). [15:8] read-write CONSTANTGREEN4 Green and U (chroma). [23:16] read-write CONSTANTRED4 Red and Y (luma). [31:24] read-write LAYERPROPERTY4 Common properties of layer 4. 0xCC 32 read-write 0x8 0xC0007FFE TILEMODE4 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE4 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE4 See AlphaConstSelect0. [4:4] read-write ALPHAMASKENABLE4 See AlphaMaskSelect0. [5:5] read-write ALPHATRANSENABLE4 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE4 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE4 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHAMASKENABLE4 See RGBAlphaMaskSelect0. [9:9] read-write RGBALPHATRANSENABLE4 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB4 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE4 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE4 See GammaRemoveEnable0. [14:14] read-write CLIPWINDOWENABLE4 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE4 See SourceBufferEnable0. [31:31] read-write BASEADDRESS5 Source buffer base address of layer 5. 0xD0 32 read-write 0x0 0xFFFFFFFF BASEADDRESS5 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES5 Source buffer attributes for layer 5. 0xD4 32 read-write 0x200003 0x3FFFFF STRIDE5 See Stride0. [15:0] read-write BITSPERPIXEL5 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION5 Source buffer dimension of layer 5. 0xD8 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH5 See LineWidth0. [13:0] read-write LINECOUNT5 See LineCount0. [29:16] read-write COLORCOMPONENTBITS5 Size of color components for RGB, YUV and index formats (layer 5). 0xDC 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA5 Alpha. [3:0] read-write COMPONENTBITSBLUE5 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN5 Green and U (chroma). [19:16] read-write COMPONENTBITSRED5 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT5 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT5 Bit position of color components for RGB, YUV and index formats (layer 5). 0xE0 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA5 Alpha. [4:0] read-write COMPONENTSHIFTBLUE5 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN5 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED5 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET5 Position of layer 5 within the destination frame. 0xE4 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET5 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET5 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET5 Clip window position for layer 5. 0xE8 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET5 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET5 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS5 Clip window size for layer 5. 0xEC 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH5 Width. [13:0] read-write CLIPWINDOWHEIGHT5 Height. [29:16] read-write CONSTANTCOLOR5 Constant color for layer 5. 0xF0 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA5 Alpha. [7:0] read-write CONSTANTBLUE5 Blue and V (chroma). [15:8] read-write CONSTANTGREEN5 Green and U (chroma). [23:16] read-write CONSTANTRED5 Red and Y (luma). [31:24] read-write LAYERPROPERTY5 Common properties of layer 5. 0xF4 32 read-write 0x8 0xC0007FFE TILEMODE5 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE5 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE5 See AlphaConstSelect0. [4:4] read-write ALPHAMASKENABLE5 See AlphaMaskSelect0. [5:5] read-write ALPHATRANSENABLE5 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE5 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE5 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHAMASKENABLE5 See RGBAlphaMaskSelect0. [9:9] read-write RGBALPHATRANSENABLE5 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB5 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE5 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE5 See GammaRemoveEnable0. [14:14] read-write CLIPWINDOWENABLE5 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE5 See SourceBufferEnable0. [31:31] read-write BASEADDRESS6 Source buffer base address of layer 6. 0xF8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS6 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES6 Source buffer attributes for layer 6. 0xFC 32 read-write 0x200003 0x3FFFFF STRIDE6 See Stride0. [15:0] read-write BITSPERPIXEL6 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION6 Source buffer dimension of layer 6. 0x100 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH6 See LineWidth0. [13:0] read-write LINECOUNT6 See LineCount0. [29:16] read-write COLORCOMPONENTBITS6 Size of color components for RGB, YUV and index formats (layer 6). 0x104 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA6 Alpha. [3:0] read-write COMPONENTBITSBLUE6 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN6 Green and U (chroma). [19:16] read-write COMPONENTBITSRED6 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT6 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT6 Bit position of color components for RGB, YUV and index formats (layer 6). 0x108 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA6 Alpha. [4:0] read-write COMPONENTSHIFTBLUE6 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN6 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED6 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET6 Position of layer 1 within the destination frame. 0x10C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET6 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET6 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET6 Clip window position for layer 6. 0x110 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET6 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET6 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS6 Clip window size for layer 6. 0x114 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH6 Width. [13:0] read-write CLIPWINDOWHEIGHT6 Height. [29:16] read-write CONSTANTCOLOR6 Constant color for layer 6. 0x118 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA6 Alpha. [7:0] read-write CONSTANTBLUE6 Blue and V (chroma). [15:8] read-write CONSTANTGREEN6 Green and U (chroma). [23:16] read-write CONSTANTRED6 Red and Y (luma). [31:24] read-write LAYERPROPERTY6 Common properties of layer 6. 0x11C 32 read-write 0x8 0xC0007FFE TILEMODE6 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE6 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE6 See AlphaConstSelect0. [4:4] read-write ALPHAMASKENABLE6 See AlphaMaskSelect0. [5:5] read-write ALPHATRANSENABLE6 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE6 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE6 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHAMASKENABLE6 See RGBAlphaMaskSelect0. [9:9] read-write RGBALPHATRANSENABLE6 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB6 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE6 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE6 See GammaRemoveEnable0. [14:14] read-write CLIPWINDOWENABLE6 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE6 See SourceBufferEnable0. [31:31] read-write BASEADDRESS7 Source buffer base address of layer 7. 0x120 32 read-write 0x0 0xFFFFFFFF BASEADDRESS7 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES7 Source buffer stride for layer 7. 0x124 32 read-write 0x200003 0x3FFFFF STRIDE7 See Stride0. [15:0] read-write BITSPERPIXEL7 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION7 Source buffer dimension of layer 7. 0x128 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH7 See LineWidth0. [13:0] read-write LINECOUNT7 See LineCount0. [29:16] read-write COLORCOMPONENTBITS7 Size of color components for RGB, YUV and index formats (layer 7). 0x12C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA7 Alpha. [3:0] read-write COMPONENTBITSBLUE7 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN7 Green and U (chroma). [19:16] read-write COMPONENTBITSRED7 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT7 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT7 Bit position of color components for RGB, YUV and index formats (layer 7). 0x130 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA7 Alpha. [4:0] read-write COMPONENTSHIFTBLUE7 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN7 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED7 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET7 Position of layer 7 within the destination frame. 0x134 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET7 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET7 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET7 Clip window position for layer 7. 0x138 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET7 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET7 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS7 Clip window size for layer 7. 0x13C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH7 Width. [13:0] read-write CLIPWINDOWHEIGHT7 Height. [29:16] read-write CONSTANTCOLOR7 Constant color for layer 7. 0x140 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA7 Alpha. [7:0] read-write CONSTANTBLUE7 Blue and V (chroma). [15:8] read-write CONSTANTGREEN7 Green and U (chroma). [23:16] read-write CONSTANTRED7 Red and Y (luma). [31:24] read-write LAYERPROPERTY7 Common properties of layer 7. 0x144 32 read-write 0x8 0xC0007FFE TILEMODE7 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE7 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE7 See AlphaConstSelect0. [4:4] read-write ALPHAMASKENABLE7 See AlphaMaskSelect0. [5:5] read-write ALPHATRANSENABLE7 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE7 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE7 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHAMASKENABLE7 See RGBAlphaMaskSelect0. [9:9] read-write RGBALPHATRANSENABLE7 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB7 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE7 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE7 See GammaRemoveEnable0. [14:14] read-write CLIPWINDOWENABLE7 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE7 See SourceBufferEnable0. [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x148 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x14C 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write WARPCONTROL Warping control options. 0x150 32 read-write 0x20 0x133F WARPBITSPERPIXEL Number of bits per pixel in the coordinate layer, which is read by another Fetch unit. Has to be 1, 2, 4, 8, 16 or 32. [5:0] read-write WARPCOORDINATEMODE Content of pixel data in the coordinate layer. [9:8] read-write PNT x and y (sample points). 0 D_PNT dx and dy (vectors between adjacent sample points). 1 DD_PNT ddx and ddy (deltas between adjacent vectors). 2 WARPSYMMETRICOFFSET Value 1 enables symmetric range for negative and positive coordinate values by adding an offset of +0.03125 internally to all coordinate input values. Recommended for small coordinate formats in DD_PNT mode. [12:12] read-write ARBSTARTX Start value X for arbitrary warping. 0x154 32 read-write 0x0 0x1FFFFF ARBSTARTX Start point for sample-point interpolation (X coordinate). (format is signed fix-point 16.5) [20:0] read-write ARBSTARTY Start value Y for arbitrary warping. 0x158 32 read-write 0x0 0x1FFFFF ARBSTARTY Start point for sample-point interpolation (Y coordinate). (format is signed fix-point 16.5) [20:0] read-write ARBDELTA Start values for delta incrementation of arbitrary warping. 0x15C 32 read-write 0x0 0xFFFFFFFF ARBDELTAXX X coordinate of vector between first and second sample point. (format is signed fix-point 3.5) [7:0] read-write ARBDELTAXY Y coordinate of vector between first and second sample point. (format is signed fix-point 3.5) [15:8] read-write ARBDELTAYX X coordinate of vector between start and first sample point. (format is signed fix-point 3.5) [23:16] read-write ARBDELTAYY Y coordinate of vector between start and first sample point. (format is signed fix-point 3.5) [31:24] read-write FIRPOSITIONS FIR sequence control register. 0x160 32 read-write 0xA965 0xFFFF FIR0POSITION Position of first pixel. [3:0] read-write FIR1POSITION Position of second pixel. [7:4] read-write FIR2POSITION Position of third pixel. [11:8] read-write FIR3POSITION Position of fourth pixel. [15:12] read-write FIRCOEFFICIENTS FIR coefficients register. 0x164 32 read-write 0x20 0xFFFFFFFF FIR0COEFFICIENT First coefficient. (format is signed fix-point 3.5) [7:0] read-write FIR1COEFFICIENT Second coefficient. (format is signed fix-point 3.5) [15:8] read-write FIR2COEFFICIENT Third coefficient. (format is signed fix-point 3.5) [23:16] read-write FIR3COEFFICIENT Fourth coefficient. (format is signed fix-point 3.5) [31:24] read-write CONTROL Shared common control settings for all layers. 0x168 32 read-write 0x10000 0x77F009F RASTERMODE Selects a method how to generate source buffer sample points. [2:0] read-write NORMAL [IBO only, for LBO use PERSPECTIVE with corresponding Geometry] First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. 0 DECODE [FetchDecode/FetchBlit only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). 1 ARBITRARY [FetchBlit/Warp only] Arbitrary warping (filter is active). Coordinates are read from frame input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. 2 PERSPECTIVE [FetchBlit only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. See also field Geometry to reduce coordinate amount. 3 YUV422 [FetchBlit/Decode only] Source buffer is packed YUV 422. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). All correllated window widths and horizontal offsets must be even. 4 INPUTSELECT Selects function for the frame input port. [4:3] read-write INACTIVE Not used. 0 COMPPACK Used for component packing (e.g. UV or source alpha buffer). 1 ALPHAMASK Used for RGB and alpha pre-multiply stage (mask alpha buffer). 2 COORDINATE Used for arbitrary warping (coordinate buffer). 3 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 CLIPLAYER Index of the layer which is used to fill the clipping area of the frame layout when ClipColor is set to LAYER. The selected layer must be enabled (LayerEnable). [19:17] read-write FILTERMODE Use this to select between nearest and bilinear filtering. Only has an effect if rastermode == ARBITRARY or rastermode == PERSPECTIVE or rastermode == AFFINE. [22:20] read-write NEAREST Chooses pixel closest to sample point 0 BILINEAR Calculates result from 4 pixels closest to sample point 1 FIR2 FIR mode with 2 programmable pixel positions and coefficients 2 FIR4 FIR mode with 4 programmable pixel positions and coefficients 3 HOR_LINEAR Calculates result from 2 pixels closest to the sample point and on the same line 4 LINEBUFLAYER Index of the layer which used as a memory based linebuffer. Only has an effect if this fetch unit is connected to a store unit for linebuffer handshake and linebuffer handshake is enabled. [26:24] read-write TRIGGERENABLE Shadow load enable flags for all layers. 0x16C 32 read-write 0x0 0xFF SHDLDREQ Shadow load request flags for each layer (one time load). [7:0] read-write CONTROLTRIGGER Shadow load trigger. 0x170 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x174 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x178 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 BURSTBUFFERPROPERTIES Burst buffer properties. 0x17C 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only STATUS Status information. 0x180 32 read-write 0x0 0x11 WRITETIMEOUT Timeout detected when writing to the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [0:0] read-write READTIMEOUT Timeout detected when reading from the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [4:4] read-write FETCHECO1 FetchEco #1 (Display) 0x00005C00 STATICCONTROL Common static control options. 0x0 32 read-write 0x0 0xFF0001 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 BASEADDRESS0 Source buffer base address of layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0xC 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x10 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x14 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x18 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x1C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x20 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x24 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x28 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x2C 32 read-write 0x80000000 0xC0000006 TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x30 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x34 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write CONTROL Shared common control settings for all layers. 0x38 32 read-write 0x10000 0x10080 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 CONTROLTRIGGER Shadow load trigger. 0x3C 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x40 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x44 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 BURSTBUFFERPROPERTIES Burst buffer properties. 0x48 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only FETCHLAYER1 FetchLayer #1 (Display) 0x00006000 STATICCONTROL Common static control options. 0x0 32 read-write 0xFF000002 0xFFFF0003 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write LBHSHDEN Enables shadowing of LBH configuration signals. [1:1] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write SHDLDREQSTICKY Shadow load request flags for each layer (always load). See description of register TriggerEnable for further information. [31:24] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 BASEADDRESS0 Source buffer base address of layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0xC 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x10 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x14 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x18 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x1C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x20 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x24 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x28 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x2C 32 read-write 0xB8000008 0xFFFF7DDF PALETTEENABLE0 Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower bits of the lookup index are read from memory (PaletteIdWidth0), upper bits are set to index of this layer. Palette output is extended by upper bits of index word read from memory (e.g. to store alpha together with index). Result is mapped to color channels according to ColorComponentBits/Shift settings. [0:0] read-write TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE0 Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [3:3] read-write ALPHACONSTENABLE0 Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [4:4] read-write ALPHATRANSENABLE0 Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [6:6] read-write RGBALPHASRCENABLE0 Value 1 enables source alpha (stored together with color component in the source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. [7:7] read-write RGBALPHACONSTENABLE0 Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. [8:8] read-write RGBALPHATRANSENABLE0 Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB0 When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no effect then. [11:11] read-write YUVCONVERSIONMODE0 Enables different kind of YUV to RGB conversions. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE0 Value 1 enables the stage to remove a gamma from RGB components. [14:14] read-write PALETTEOFFSET0 Palette may contain multiple areas. This offset shows to the starting position of the currently used area. [26:16] read-write PALETTEIDWIDTH0 Number minus one of least significant bits of pixel data read from the source buffer that are used as index value for color palette look-up. [29:27] read-write CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write BASEADDRESS1 Source buffer base address of layer 1. 0x30 32 read-write 0x0 0xFFFFFFFF BASEADDRESS1 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES1 Source buffer attributes for layer 1. 0x34 32 read-write 0x200003 0x3FFFFF STRIDE1 See Stride0. [15:0] read-write BITSPERPIXEL1 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION1 Source buffer dimensions of layer 1, 0x38 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH1 See LineWidth0. [13:0] read-write LINECOUNT1 See LineCount0. [29:16] read-write COLORCOMPONENTBITS1 Size of color components for RGB, YUV and index formats (layer 1). 0x3C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA1 Alpha. [3:0] read-write COMPONENTBITSBLUE1 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN1 Green and U (chroma). [19:16] read-write COMPONENTBITSRED1 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT1 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT1 Bit position of color components for RGB, YUV and index formats (layer 1). 0x40 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA1 Alpha. [4:0] read-write COMPONENTSHIFTBLUE1 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN1 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED1 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET1 Position of layer 1 within the destination frame. 0x44 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET1 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET1 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET1 Clip window position for layer 1. 0x48 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET1 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET1 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS1 Clip window size for layer 1. 0x4C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH1 Width. [13:0] read-write CLIPWINDOWHEIGHT1 Height. [29:16] read-write CONSTANTCOLOR1 Constant color for layer 1. 0x50 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA1 Alpha. [7:0] read-write CONSTANTBLUE1 Blue and V (chroma). [15:8] read-write CONSTANTGREEN1 Green and U (chroma). [23:16] read-write CONSTANTRED1 Red and Y (luma). [31:24] read-write LAYERPROPERTY1 Common properties of layer 1. 0x54 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE1 See PaletteEnable0. [0:0] read-write TILEMODE1 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE1 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE1 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE1 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE1 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE1 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE1 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB1 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE1 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE1 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET1 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH1 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE1 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE1 See SourceBufferEnable0. [31:31] read-write BASEADDRESS2 Source buffer base address of layer 2. 0x58 32 read-write 0x0 0xFFFFFFFF BASEADDRESS2 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES2 Source buffer attributes for layer 2. 0x5C 32 read-write 0x200003 0x3FFFFF STRIDE2 See Stride0. [15:0] read-write BITSPERPIXEL2 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION2 Source buffer dimension of layer 2. 0x60 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH2 See LineWidth0. [13:0] read-write LINECOUNT2 See LineCount0. [29:16] read-write COLORCOMPONENTBITS2 Size of color components for RGB, YUV and index formats (layer 2). 0x64 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA2 Alpha. [3:0] read-write COMPONENTBITSBLUE2 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN2 Green and U (chroma). [19:16] read-write COMPONENTBITSRED2 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT2 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT2 Bit position of color components for RGB, YUV and index formats (layer 2). 0x68 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA2 Alpha. [4:0] read-write COMPONENTSHIFTBLUE2 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN2 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED2 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET2 Position of layer 2 within the destination frame. 0x6C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET2 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET2 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET2 Clip window position for layer 2. 0x70 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET2 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET2 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS2 Clip window size for layer 2. 0x74 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH2 Width. [13:0] read-write CLIPWINDOWHEIGHT2 Height. [29:16] read-write CONSTANTCOLOR2 Constant color for layer 2. 0x78 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA2 Alpha. [7:0] read-write CONSTANTBLUE2 Blue and V (chroma). [15:8] read-write CONSTANTGREEN2 Green and U (chroma). [23:16] read-write CONSTANTRED2 Red and Y (luma). [31:24] read-write LAYERPROPERTY2 Common properties of layer 2. 0x7C 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE2 See PaletteEnable0. [0:0] read-write TILEMODE2 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE2 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE2 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE2 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE2 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE2 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE2 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB2 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE2 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE2 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET2 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH2 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE2 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE2 See SourceBufferEnable0. [31:31] read-write BASEADDRESS3 Source buffer base address of layer 3. 0x80 32 read-write 0x0 0xFFFFFFFF BASEADDRESS3 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES3 Source buffer attributes for layer 3. 0x84 32 read-write 0x200003 0x3FFFFF STRIDE3 See Stride0. [15:0] read-write BITSPERPIXEL3 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION3 Source buffer dimension of layer 3. 0x88 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH3 See LineWidth0. [13:0] read-write LINECOUNT3 See LineCount0. [29:16] read-write COLORCOMPONENTBITS3 Size of color components for RGB, YUV and index formats (layer 3). 0x8C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA3 Alpha. [3:0] read-write COMPONENTBITSBLUE3 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN3 Green and U (chroma). [19:16] read-write COMPONENTBITSRED3 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT3 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT3 Bit position of color components for RGB, YUV and index formats (layer 3). 0x90 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA3 Alpha. [4:0] read-write COMPONENTSHIFTBLUE3 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN3 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED3 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET3 Position of layer 3 within the destination frame. 0x94 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET3 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET3 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET3 Clip window position for layer 3. 0x98 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET3 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET3 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS3 Clip window size for layer 3. 0x9C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH3 Width. [13:0] read-write CLIPWINDOWHEIGHT3 Height. [29:16] read-write CONSTANTCOLOR3 Constant color for layer 3. 0xA0 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA3 Alpha. [7:0] read-write CONSTANTBLUE3 Blue and V (chroma). [15:8] read-write CONSTANTGREEN3 Green and U (chroma). [23:16] read-write CONSTANTRED3 Red and Y (luma). [31:24] read-write LAYERPROPERTY3 Common properties of layer 3. 0xA4 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE3 See PaletteEnable0. [0:0] read-write TILEMODE3 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE3 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE3 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE3 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE3 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE3 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE3 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB3 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE3 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE3 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET3 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH3 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE3 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE3 See SourceBufferEnable0. [31:31] read-write BASEADDRESS4 Source buffer base address of layer 4. 0xA8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS4 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES4 Source buffer attributes for layer 4. 0xAC 32 read-write 0x200003 0x3FFFFF STRIDE4 See Stride0. [15:0] read-write BITSPERPIXEL4 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION4 Source buffer dimension of layer 4. 0xB0 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH4 See LineWidth0. [13:0] read-write LINECOUNT4 See LineCount0. [29:16] read-write COLORCOMPONENTBITS4 Size of color components for RGB, YUV and index formats (layer 4). 0xB4 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA4 Alpha. [3:0] read-write COMPONENTBITSBLUE4 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN4 Green and U (chroma). [19:16] read-write COMPONENTBITSRED4 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT4 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT4 Bit position of color components for RGB, YUV and index formats (layer 4). 0xB8 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA4 Alpha. [4:0] read-write COMPONENTSHIFTBLUE4 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN4 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED4 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET4 Position of layer 4 within the destination frame. 0xBC 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET4 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET4 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET4 Clip window position for layer 4. 0xC0 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET4 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET4 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS4 Clip window size for layer 4. 0xC4 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH4 Width. [13:0] read-write CLIPWINDOWHEIGHT4 Height. [29:16] read-write CONSTANTCOLOR4 Constant color for layer 4. 0xC8 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA4 Alpha. [7:0] read-write CONSTANTBLUE4 Blue and V (chroma). [15:8] read-write CONSTANTGREEN4 Green and U (chroma). [23:16] read-write CONSTANTRED4 Red and Y (luma). [31:24] read-write LAYERPROPERTY4 Common properties of layer 4. 0xCC 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE4 See PaletteEnable0. [0:0] read-write TILEMODE4 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE4 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE4 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE4 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE4 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE4 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE4 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB4 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE4 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE4 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET4 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH4 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE4 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE4 See SourceBufferEnable0. [31:31] read-write BASEADDRESS5 Source buffer base address of layer 5. 0xD0 32 read-write 0x0 0xFFFFFFFF BASEADDRESS5 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES5 Source buffer attributes for layer 5. 0xD4 32 read-write 0x200003 0x3FFFFF STRIDE5 See Stride0. [15:0] read-write BITSPERPIXEL5 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION5 Source buffer dimension of layer 5. 0xD8 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH5 See LineWidth0. [13:0] read-write LINECOUNT5 See LineCount0. [29:16] read-write COLORCOMPONENTBITS5 Size of color components for RGB, YUV and index formats (layer 5). 0xDC 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA5 Alpha. [3:0] read-write COMPONENTBITSBLUE5 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN5 Green and U (chroma). [19:16] read-write COMPONENTBITSRED5 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT5 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT5 Bit position of color components for RGB, YUV and index formats (layer 5). 0xE0 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA5 Alpha. [4:0] read-write COMPONENTSHIFTBLUE5 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN5 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED5 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET5 Position of layer 5 within the destination frame. 0xE4 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET5 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET5 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET5 Clip window position for layer 5. 0xE8 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET5 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET5 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS5 Clip window size for layer 5. 0xEC 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH5 Width. [13:0] read-write CLIPWINDOWHEIGHT5 Height. [29:16] read-write CONSTANTCOLOR5 Constant color for layer 5. 0xF0 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA5 Alpha. [7:0] read-write CONSTANTBLUE5 Blue and V (chroma). [15:8] read-write CONSTANTGREEN5 Green and U (chroma). [23:16] read-write CONSTANTRED5 Red and Y (luma). [31:24] read-write LAYERPROPERTY5 Common properties of layer 5. 0xF4 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE5 See PaletteEnable0. [0:0] read-write TILEMODE5 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE5 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE5 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE5 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE5 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE5 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE5 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB5 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE5 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE5 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET5 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH5 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE5 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE5 See SourceBufferEnable0. [31:31] read-write BASEADDRESS6 Source buffer base address of layer 6. 0xF8 32 read-write 0x0 0xFFFFFFFF BASEADDRESS6 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES6 Source buffer attributes for layer 6. 0xFC 32 read-write 0x200003 0x3FFFFF STRIDE6 See Stride0. [15:0] read-write BITSPERPIXEL6 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION6 Source buffer dimension of layer 6. 0x100 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH6 See LineWidth0. [13:0] read-write LINECOUNT6 See LineCount0. [29:16] read-write COLORCOMPONENTBITS6 Size of color components for RGB, YUV and index formats (layer 6). 0x104 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA6 Alpha. [3:0] read-write COMPONENTBITSBLUE6 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN6 Green and U (chroma). [19:16] read-write COMPONENTBITSRED6 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT6 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT6 Bit position of color components for RGB, YUV and index formats (layer 6). 0x108 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA6 Alpha. [4:0] read-write COMPONENTSHIFTBLUE6 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN6 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED6 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET6 Position of layer 1 within the destination frame. 0x10C 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET6 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET6 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET6 Clip window position for layer 6. 0x110 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET6 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET6 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS6 Clip window size for layer 6. 0x114 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH6 Width. [13:0] read-write CLIPWINDOWHEIGHT6 Height. [29:16] read-write CONSTANTCOLOR6 Constant color for layer 6. 0x118 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA6 Alpha. [7:0] read-write CONSTANTBLUE6 Blue and V (chroma). [15:8] read-write CONSTANTGREEN6 Green and U (chroma). [23:16] read-write CONSTANTRED6 Red and Y (luma). [31:24] read-write LAYERPROPERTY6 Common properties of layer 6. 0x11C 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE6 See PaletteEnable0. [0:0] read-write TILEMODE6 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE6 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE6 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE6 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE6 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE6 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE6 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB6 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE6 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE6 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET6 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH6 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE6 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE6 See SourceBufferEnable0. [31:31] read-write BASEADDRESS7 Source buffer base address of layer 7. 0x120 32 read-write 0x0 0xFFFFFFFF BASEADDRESS7 See BaseAddress0. [31:0] read-write SOURCEBUFFERATTRIBUTES7 Source buffer stride for layer 7. 0x124 32 read-write 0x200003 0x3FFFFF STRIDE7 See Stride0. [15:0] read-write BITSPERPIXEL7 See BitsPerPixel0. [21:16] read-write SOURCEBUFFERDIMENSION7 Source buffer dimension of layer 7. 0x128 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH7 See LineWidth0. [13:0] read-write LINECOUNT7 See LineCount0. [29:16] read-write COLORCOMPONENTBITS7 Size of color components for RGB, YUV and index formats (layer 7). 0x12C 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA7 Alpha. [3:0] read-write COMPONENTBITSBLUE7 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN7 Green and U (chroma). [19:16] read-write COMPONENTBITSRED7 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT7 See ITUFormat0. [31:31] read-write COLORCOMPONENTSHIFT7 Bit position of color components for RGB, YUV and index formats (layer 7). 0x130 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA7 Alpha. [4:0] read-write COMPONENTSHIFTBLUE7 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN7 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED7 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET7 Position of layer 7 within the destination frame. 0x134 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET7 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET7 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET7 Clip window position for layer 7. 0x138 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET7 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET7 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS7 Clip window size for layer 7. 0x13C 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH7 Width. [13:0] read-write CLIPWINDOWHEIGHT7 Height. [29:16] read-write CONSTANTCOLOR7 Constant color for layer 7. 0x140 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA7 Alpha. [7:0] read-write CONSTANTBLUE7 Blue and V (chroma). [15:8] read-write CONSTANTGREEN7 Green and U (chroma). [23:16] read-write CONSTANTRED7 Red and Y (luma). [31:24] read-write LAYERPROPERTY7 Common properties of layer 7. 0x144 32 read-write 0x38000008 0xFFFF7DDF PALETTEENABLE7 See PaletteEnable0. [0:0] read-write TILEMODE7 See TileMode0. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE7 See AlphaSrcSelect0. [3:3] read-write ALPHACONSTENABLE7 See AlphaConstSelect0. [4:4] read-write ALPHATRANSENABLE7 See AlphaTransSelect0. [6:6] read-write RGBALPHASRCENABLE7 See RGBAlphaSrcSelect0. [7:7] read-write RGBALPHACONSTENABLE7 See RGBAlphaConstSelect0. [8:8] read-write RGBALPHATRANSENABLE7 See RGBAlphaTransSelect0. [10:10] read-write PREMULCONSTRGB7 See PremulConstRGB0. [11:11] read-write YUVCONVERSIONMODE7 See YUVConversionMode0. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE7 See GammaRemoveEnable0. [14:14] read-write PALETTEOFFSET7 see PaletteOffset0. [26:16] read-write PALETTEIDWIDTH7 see PaletteIdWidth0. [29:27] read-write CLIPWINDOWENABLE7 See ClipWindowEnable0. [30:30] read-write SOURCEBUFFERENABLE7 See SourceBufferEnable0. [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x148 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x14C 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write CONTROL Shared common control settings for all layers. 0x150 32 read-write 0x10000 0x70F0080 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 CLIPLAYER Index of the layer which is used to fill the clipping area of the frame layout when ClipColor is set to LAYER. The selected layer must be enabled (LayerEnable). [19:17] read-write LINEBUFLAYER Index of the layer which used as a memory based linebuffer. Only has an effect if this fetch unit is connected to a store unit for linebuffer handshake and linebuffer handshake is enabled. [26:24] read-write TRIGGERENABLE Shadow load enable flags for all layers. 0x154 32 read-write 0x0 0xFF SHDLDREQ Shadow load request flags for each layer (one time load). [7:0] read-write CONTROLTRIGGER Shadow load trigger. 0x158 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x15C 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x160 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 BURSTBUFFERPROPERTIES Burst buffer properties. 0x164 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only STATUS Status information. 0x168 32 read-write 0x0 0x11 WRITETIMEOUT Timeout detected when writing to the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [0:0] read-write READTIMEOUT Timeout detected when reading from the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [4:4] read-write FETCHDECODE0 FetchDecode #0 (Display) 0x00006400 STATICCONTROL Common static control options. 0x0 32 read-write 0x2 0xFF0003 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write LBHSHDEN Enables shadowing of LBH configuration signals. [1:1] read-write BASEADDRESSAUTOUPDATE Enable flag for continuous shadow load of BaseAddress field for each layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded from shadow at start of each frame. This update is then executed independently from other RWS type fields. ShdEn must be enabled for this mode. When the flag is enabled for layer 0, also the FieldId0 shadow is automatically loaded. [23:16] read-write BURSTBUFFERMANAGEMENT AXI interface buffer management register 0x4 32 read-write 0x204 0x80001FFF SETNUMBUFFERS Set this to the number of bursts that should be buffered. SetNumBuffers has to be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum allowed settings is 4 except for the FetchEco derivate which has a minimum allowed setting of 2. [7:0] read-write SETBURSTLENGTH Set this to the burst length that should be used on the AXI interface. SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length. [12:8] read-write LINEMODE Fetch buffer cache control. [31:31] read-write DISPLAY Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. 0 BLIT Recommended setting for operation in the Blit Engine. 1 RINGBUFSTARTADDR0 Ring buffer setup for layer 0. 0x8 32 read-write 0x0 0xFFFFFFFF RINGBUFSTARTADDR0 Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes. [31:0] read-write RINGBUFWRAPADDR0 Ring buffer setup for layer 0. 0xC 32 read-write 0x0 0xFFFFFFFF RINGBUFWRAPADDR0 End address of the ring buffer (last byte of the buffer plus one). [31:0] read-write FRAMEPROPERTIES0 Frame property setup for layer 0. 0x10 32 read-write 0x0 0x1 FIELDID0 Field identifier that is generated for subsequent units (0 = progressive frame or interlaced field with even line indices, 1 = odd field). [0:0] read-write BASEADDRESS0 Source buffer base address of layer 0. 0x14 32 read-write 0x0 0xFFFFFFFF BASEADDRESS0 Byte aligned start address of the layer source buffer. For a pixel width of 32 bits or DECODE operations BaseAddress bits 1 downto 0 have to be 0 and for a pixel width of 16 bit BaseAddress[0] has to be 0. [31:0] read-write SOURCEBUFFERATTRIBUTES0 Source buffer attributes for layer 0. 0x18 32 read-write 0x2004FF 0x3FFFFF STRIDE0 Source buffer stride of the layer in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one. [15:0] read-write BITSPERPIXEL0 Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or 32. [Exception] FetchEco does not support 18 and 24. [21:16] read-write SOURCEBUFFERDIMENSION0 Source buffer dimension of layer 0. 0x1C 32 read-write 0x3FFF3FFF 0x3FFF3FFF LINEWIDTH0 Width of the source buffer of the layer in pixels minus one. [13:0] read-write LINECOUNT0 Number of lines of the source buffer of the layer minus one. [29:16] read-write COLORCOMPONENTBITS0 Size of color components for RGB, YUV and index formats (layer 0). 0x20 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA0 Alpha. [3:0] read-write COMPONENTBITSBLUE0 Blue and V (chroma). [11:8] read-write COMPONENTBITSGREEN0 Green and U (chroma). [19:16] read-write COMPONENTBITSRED0 Red, Y (luma) and palette index. [27:24] read-write ITUFORMAT0 When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT0 Bit position of color components for RGB, YUV and index formats (layer 0). 0x24 32 read-write 0x18100800 0x1F1F1F1F COMPONENTSHIFTALPHA0 Alpha. [4:0] read-write COMPONENTSHIFTBLUE0 Blue and V (chroma). [12:8] read-write COMPONENTSHIFTGREEN0 Green and U (chroma). [20:16] read-write COMPONENTSHIFTRED0 Red, Y (luma) and palette index. [28:24] read-write LAYEROFFSET0 Position of layer 0 within the destination frame. 0x28 32 read-write 0x0 0x7FFF7FFF LAYERXOFFSET0 Horizontal offset (X). (format is signed integer) [14:0] read-write LAYERYOFFSET0 Vertical offset (Y). (format is signed integer) [30:16] read-write CLIPWINDOWOFFSET0 Clip window position for layer 0. 0x2C 32 read-write 0x0 0x7FFF7FFF CLIPWINDOWXOFFSET0 Horizontal position (X). (format is signed integer) [14:0] read-write CLIPWINDOWYOFFSET0 Vertical position (Y). (format is signed integer) [30:16] read-write CLIPWINDOWDIMENSIONS0 Clip window size for layer 0. 0x30 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH0 Width. [13:0] read-write CLIPWINDOWHEIGHT0 Height. [29:16] read-write CONSTANTCOLOR0 Constant color for layer 0. 0x34 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA0 Alpha. [7:0] read-write CONSTANTBLUE0 Blue and V (chroma). [15:8] read-write CONSTANTGREEN0 Green and U (chroma). [23:16] read-write CONSTANTRED0 Red and Y (luma). [31:24] read-write LAYERPROPERTY0 Common properties of layer 0. 0x38 32 read-write 0xB8000008 0xFFFF7FFF PALETTEENABLE0 Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower bits of the lookup index are read from memory (PaletteIdWidth0), upper bits are set to index of this layer. Palette output is extended by upper bits of index word read from memory (e.g. to store alpha together with index). Result is mapped to color channels according to ColorComponentBits/Shift settings. [0:0] read-write TILEMODE0 Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) takes precedence if a pixel becomes subject to both tiling and clipping. [2:1] read-write TILE_FILL_ZERO Use zero value 0 TILE_FILL_CONSTANT Use constant color register value 1 TILE_PAD Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. 3 ALPHASRCENABLE0 Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [3:3] read-write ALPHACONSTENABLE0 Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [4:4] read-write ALPHAMASKENABLE0 Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. [5:5] read-write ALPHATRANSENABLE0 Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [6:6] read-write RGBALPHASRCENABLE0 Value 1 enables source alpha (stored together with color component in the source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. [7:7] read-write RGBALPHACONSTENABLE0 Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. [8:8] read-write RGBALPHAMASKENABLE0 Value 1 enables mask alpha (read by another Fetch unit from a separate alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be enabled for this field to have effect. [9:9] read-write RGBALPHATRANSENABLE0 Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB0 When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no effect then. [11:11] read-write YUVCONVERSIONMODE0 Enables different kind of YUV to RGB conversions. [13:12] read-write OFF No conversion. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 GAMMAREMOVEENABLE0 Value 1 enables the stage to remove a gamma from RGB components. [14:14] read-write PALETTEOFFSET0 Palette may contain multiple areas. This offset shows to the starting position of the currently used area. [26:16] read-write PALETTEIDWIDTH0 Number minus one of least significant bits of pixel data read from the source buffer that are used as index value for color palette look-up. [29:27] read-write CLIPWINDOWENABLE0 Value 1 enables the clip window for this layer. Pixels outside the clip window get the clip color, pixels inside the source or tiling color. [30:30] read-write SOURCEBUFFERENABLE0 Value 1 enables the source buffer for this layer. When disabled the tiling color is used only (TileMode TILE_PAD not allowed). [31:31] read-write FRAMEDIMENSIONS Output frame dimension. 0x3C 32 read-write 0xEF013F 0xBFFF3FFF FRAMEWIDTH Frame width minus one. [13:0] read-write FRAMEHEIGHT Frame height minus one. [29:16] read-write EMPTYFRAME When enabled output frame is empty. FrameWidth/Height settings have no effect then. Can be used to load shadows or to generate synchronization signals only (frame/sequence complete). If enabled, InputSelect must be set to INACTIVE. [31:31] read-write FRAMERESAMPLING Resampling options for output frame. 0x40 32 read-write 0x104000 0x1FFFFFF STARTX X coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [5:0] read-write STARTY Y coordinate of first sample point relative to origin. (format is signed fix-point 4.2) [11:6] read-write DELTAX Increment of X coordinate for horizontal step in destination frame. (format is signed fix-point 4.2) [17:12] read-write DELTAY Increment of Y coordinate for vertical step in destination frame. (format is signed fix-point 4.2) [23:18] read-write SWAPDIRECTION Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied for horizontal and DeltaX for vertical step on destination frame. [24:24] read-write DECODECONTROL Control options for RLAD decompression. 0x44 32 read-write 0x88880001 0xFFFF0003 COMPRESSIONMODE Algorithm that the encoder used for compression. [1:0] read-write RLAD Run-Length Adaptive Dithering (lossy compression). 0 RLAD_UNIFORM Run-Length Adaptive Dithering (lossy compression; uniform package size). 1 RLA Run-Length Adaptive (lossless compression). 2 RL Standard Run-Length. In contrary to other modes is in big endian format. 3 RLADCOMPBITSRED Maximum for average number of bits per compressed pixel for Red or Y (luma) channel. This must match the corresponding encoder setting. [19:16] read-write RLADCOMPBITSGREEN Maximum for average number of bits per compressed pixel for Green or U (chroma) channel. This must match the corresponding encoder setting. [23:20] read-write RLADCOMPBITSBLUE Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel. This must match the corresponding encoder setting. [27:24] read-write RLADCOMPBITSALPHA Maximum for average number of bits per compressed pixel for Alpha channel. This must match the corresponding encoder setting. [31:28] read-write SOURCEBUFFERLENGTH Source buffer length for compressed data. 0x48 32 read-write 0x0 0x1FFFFFFF RLEWORDS Number of 32-bit words minus one that are required to decode the run length encoded source buffer. [28:0] read-write CONTROL Shared common control settings for all layers. 0x4C 32 read-write 0x10000 0x100BF RASTERMODE Selects a method how to generate source buffer sample points. [2:0] read-write NORMAL [IBO only, for LBO use PERSPECTIVE with corresponding Geometry] First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. 0 DECODE [FetchDecode/FetchBlit only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). 1 ARBITRARY [FetchBlit/Warp only] Arbitrary warping (filter is active). Coordinates are read from frame input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. 2 PERSPECTIVE [FetchBlit only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. See also field Geometry to reduce coordinate amount. 3 YUV422 [FetchBlit/Decode only] Source buffer is packed YUV 422. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). All correllated window widths and horizontal offsets must be even. 4 INPUTSELECT Selects function for the frame input port. [4:3] read-write INACTIVE Not used. 0 COMPPACK Used for component packing (e.g. UV or source alpha buffer). 1 ALPHAMASK Used for RGB and alpha pre-multiply stage (mask alpha buffer). 2 COORDINATE Used for arbitrary warping (coordinate buffer). 3 YUV422UPSAMPLINGMODE Selects a method for horizontal up-sampling of YUV 422/420 input data. [5:5] read-write REPLICATE Replicate mode for interspersed samples (UV samples between Y samples). 0 INTERPOLATE Interpolate mode for coaligned samples (UV samples at Y sample positions). 1 RAWPIXEL Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced for all layers by fixed values that allow passing the pixel data read from memory unchanged to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color are deactivated. Skip and Tile pixels are not affected by this setting. [7:7] read-write CLIPCOLOR Selects which color to take for pixels that do not lie inside the clip window of any layer. [16:16] read-write NULL Null color. 0 LAYER Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is then the layer's source or tiling color. 1 CONTROLTRIGGER Shadow load trigger. 0x50 32 write-only 0x0 0x0 SHDTOKGEN Writing a 1 to this will load shadow registers into the active configuration with the next start of frame and send a shadow load token to subsequent units. [0:0] write-only START Frame start trigger. 0x54 32 write-only 0x0 0x0 START Writing a 1 to this field will start generating one frame (for debugging purposes only). [0:0] write-only FETCHTYPE Fetch unit type. 0x58 32 read-only 0x0 0x0 FETCHTYPE This field can be used to determine what kind of fetch unit this is. [3:0] read-only DECODE Fetch unit with RL and RLAD decoder. 0 LAYER Fetch unit with fractional plane (8 layers). 1 WARP Fetch unit with arbitrary warping and fractional plane (8 layers). 2 ECO Fetch unit with minimum feature set for alpha, chroma and coordinate planes. 3 PERSP Fetch unit with affine, perspective and arbitrary warping. 4 ROT Fetch unit with affine and arbitrary warping. 5 DECODEL Fetch unit with RL and RLAD decoder, reduced feature set. 6 LAYERL Fetch unit with fractional plane (8 layers), reduced feature set. 7 ROTL Fetch unit with affine and arbitrary warping, reduced feature set. 8 ECOL Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. 9 BLIT Fetch unit with DECODE and PERSP capabilities. 10 DECODERSTATUS Status information of the RLAD decoder. 0x5C 32 read-write 0x0 0x3 BUFFERTOOSMALL The buffer size given by RLEWords is too small. No complete output frame could be decoded. [0:0] read-write BUFFERTOOLARGE The buffer size given by RLEWords is too large. A complete output frame could be decoded, but more data was read than necessary. [1:1] read-write READADDRESS0 Ring buffer synchronization for layer 0. 0x60 32 read-only 0x0 0xFFFFFFFF READADDRESS0 Last burst address that was read from the layer's source buffer. [31:0] read-only BURSTBUFFERPROPERTIES Burst buffer properties. 0x64 32 read-only 0x0 0x0 MANAGEDBURSTBUFFERS Maximum number of burst buffers that can be administrated in the AXI interface. [7:0] read-only BURSTLENGTHFORMAXBUFFERS Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. [12:8] read-only STATUS Status information. 0x68 32 read-write 0x0 0x11 WRITETIMEOUT Timeout detected when writing to the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [0:0] read-write READTIMEOUT Timeout detected when reading from the palette entries or shadow token trigger enables in FetchLayer derivate. Write 1 to clear. [4:4] read-write GAMMACOR4 Video Processing Block #0 GammaCor (Capture) 0x00006800 STATICCONTROL Static control settings. 0x0 32 read-write 0xE 0xF SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write BLUEWRITEENABLE Write enable for the blue color sampling point entries. [1:1] read-write GREENWRITEENABLE Write enable for the green color sampling point entries. [2:2] read-write REDWRITEENABLE Write enable for the red color sampling point entries. [3:3] read-write LUTSTART Start values for look-up table programming. 0x4 32 write-only 0x0 0x3FFFFFFF STARTBLUE Start value for blue or chroma (V) channel. (format is unsigned integer) [9:0] write-only STARTGREEN Start value for green or chroma (U) channel. (format is unsigned integer) [19:10] write-only STARTRED Start value for red or luma (Y) channel. (format is unsigned integer) [29:20] write-only LUTDELTAS Delta values for look-up table programming. 0x8 32 write-only 0x0 0x0 DELTABLUE Delta value for blue or chroma (V) channel. (format is signed integer) [9:0] write-only DELTAGREEN Delta value for green or chroma (U) channel. (format is signed integer) [19:10] write-only DELTARED Delta value for red or luma (Y) channel. (format is signed integer) [29:20] write-only CONTROL Dynamic control settings. 0xC 32 read-write 0x0 0x31 MODE Operation mode for gamma correction unit [0:0] read-write NEUTRAL Module in neutral mode, input data is bypassed to the output. 0 GAMMACOR Module in gamma correction mode. 1 ALPHAMASK Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value smaller than 0.5 are by-passed unchanged. [4:4] read-write ALPHAINVERT Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha value greater or equal 0.5 are by-passed). [5:5] read-write MATRIX4 Video Processing Block #0 Matrix (Capture) 0x00006C00 STATICCONTROL Color Matrix static control register 0x0 32 read-write 0x0 0x1 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write CONTROL Color Matrix control register 0x4 32 read-write 0x0 0x33 MODE Operation mode for color matrix [1:0] read-write NEUTRAL Module in neutral mode, input data is bypassed 0 MATRIX Module in matrix mode, input data is multiplied with matrix values 1 PREMUL Module in alpha pre-multiplication mode, input color is multiplied with input alpha 2 RSVD N/A 3 ALPHAMASK Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value smaller than 0.5 are by-passed unchanged. [4:4] read-write ALPHAINVERT Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha value greater or equal 0.5 are by-passed). [5:5] read-write RED0 Matrix values for calculation of the red output value. 0x8 32 read-write 0x400 0x1FFF1FFF A11 Value for red input. (format is signed fix-point 3.10) [12:0] read-write A12 Value for green input. (format is signed fix-point 3.10) [28:16] read-write RED1 Matrix values for calculation of the red output value. 0xC 32 read-write 0x0 0x1FFF1FFF A13 Value for blue input. (format is signed fix-point 3.10) [12:0] read-write A14 Value for alpha input. (format is signed fix-point 3.10) [28:16] read-write GREEN0 Matrix values for calculation of the green output value. 0x10 32 read-write 0x4000000 0x1FFF1FFF A21 Value for red input. (format is signed fix-point 3.10) [12:0] read-write A22 Value for green input. (format is signed fix-point 3.10) [28:16] read-write GREEN1 Matrix values for calculation of the green output value. 0x14 32 read-write 0x0 0x1FFF1FFF A23 Value for blue input. (format is signed fix-point 3.10) [12:0] read-write A24 Value for alpha input. (format is signed fix-point 3.10) [28:16] read-write BLUE0 Matrix values for calculation of the blue output value. 0x18 32 read-write 0x0 0x1FFF1FFF A31 Value for red input. (format is signed fix-point 3.10) [12:0] read-write A32 Value for green input. (format is signed fix-point 3.10) [28:16] read-write BLUE1 Matrix values for calculation of the blue output value. 0x1C 32 read-write 0x400 0x1FFF1FFF A33 Value for blue input. (format is signed fix-point 3.10) [12:0] read-write A34 Value for alpha input. (format is signed fix-point 3.10) [28:16] read-write ALPHA0 Matrix values for calculation of the alpha output value. 0x20 32 read-write 0x0 0x1FFF1FFF A41 Value for red input. (format is signed fix-point 3.10) [12:0] read-write A42 Value for green input. (format is signed fix-point 3.10) [28:16] read-write ALPHA1 Matrix values for calculation of the alpha output value. 0x24 32 read-write 0x4000000 0x1FFF1FFF A43 Value for blue input. (format is signed fix-point 3.10) [12:0] read-write A44 Value for alpha input. (format is signed fix-point 3.10) [28:16] read-write OFFSETVECTOR0 Offset vectors for red and green output. 0x28 32 read-write 0x0 0x1FFF1FFF C1 Red output offset. (format is signed integer) [12:0] read-write C2 Green output offset. (format is signed integer) [28:16] read-write OFFSETVECTOR1 Offset vectors for blue and alpha output. 0x2C 32 read-write 0x0 0x1FFF1FFF C3 Blue output offset. (format is signed integer) [12:0] read-write C4 Alpha output offset. Note that the 8-bit alpha input is up-scaled to 10-bit, before the matrix and this offset is applied, and down-scaled to 8-bit for output afterwards. (format is signed integer) [28:16] read-write GPSCALER4 GPscaler #4 (Capture) 0x00007000 STATICCONTROL Static control settings that must typically be setup once only. 0x0 32 read-write 0x0 0x1 SHDEN If ShdEn==1 shadow registers are loaded when indicated by hardware signal ( a command signal in the data stream at frame start ). If ShdEn==0 shadow registers are loaded each frame start. (format is unsigned integer) [0:0] read-write CONTROL Global operation control. 0x4 32 read-write 0x0 0x10F MODE Controls the sequence of horizontal and vertical operation for all operation modes. (format is unsigned integer) [3:0] read-write NEUTRAL Neutral mode. Pixels are by-passed unchanged, all other settings are ignored. 0 ACTIVE_AUTO Automatic mode. Behaves like ACTIVE_VER_FIRST when operation_mode=SCALE and scale_mode_h=UPSCALE, like ACTIVE_HOR_FIRST otherwise. 14 ACTIVE_HOR_FIRST Horizontal is done before vertical operation. 12 ACTIVE_VER_FIRST Vertical is done before horizontal operation. 13 ACTIVE_HOR_ONLY Only horizontal operation is done. 8 ACTIVE_VER_ONLY Only vertical operation is done. 5 OPERATION_MODE Selects the kind of operation to execute. (format is unsigned integer) [8:8] read-write SCALE Scaler is active with the corresponding settings from scaler registers; filter registers are ignored. 0 FIR FIR-Filter is active with the corresponding settings from filter registers; scaler registers are ignored. 1 OUTPUTDIMENSION Dimensions of the output frame or fame slice. This values are required for both FIR filter and scaler, since their output may have other dimension than input. The dimension of scaler's output is defined by the scale factor. The dimension of FIR filter's output depends on the tiling at the begin and the end of the slice. 0x8 32 read-write 0x0 0x3FFF3FFF OUTPUT_WIDTH Number of output pixel per input line. This number is equal to the width of the output frame minus one. (format is unsigned integer) [13:0] read-write OUTPUT_HEIGHT Number of output lines per input frame or slice. This number is equal to the height of the output frame minus one. (format is unsigned integer) [29:16] read-write SCALERCONTROL Scaler operation control. 0xC 32 read-write 0x20000 0xFF31111 SCALE_MODE_H Scale mode for horizontal scaling. (format is unsigned integer) [0:0] read-write DOWNSCALE Down-scaling (output width is less or equal input width). 0 UPSCALE Up-scaling (output width greater or equal input width) 1 SCALE_MODE_V Scale mode for vertical scaling. (format is unsigned integer) [4:4] read-write DOWNSCALE Down-scaling (output height less or equal input height). 0 UPSCALE Up-scaling (output height greater or equal input height) 1 FILTER_MODE_H Selects sampling algorithm for horizontal scaling. (format is unsigned integer) [8:8] read-write NEAREST Nearest filter (point-sampling) 0 LINEAR Box filter (linear) 1 FILTER_MODE_V Selects sampling algorithm for vertical scaling. (format is unsigned integer) [12:12] read-write NEAREST Nearest filter (point-sampling) 0 LINEAR Box filter (linear) 1 FIELD_MODE Controls generation of output field polarity for vertical scaling. (format is unsigned integer) [17:16] read-write ALWAYS0 Constant 0 indicates frame or top field. 0 ALWAYS1 Constant 1 indicates bottom field. 1 INPUT Output field polarity is taken from input field polarity. 2 TOGGLE Output field polarity toggles, starting with 0 after reset. 3 ALPHA_VALUE When 'mode' field is not 'NEUTRAL', then input alpha values are ignore and output alpha set to this constant value for all pixels. This restriction applies to GPScalerL derivative only. (format is unsigned integer) [27:20] read-write SCALERSETUPH0 Phase interpolator setup. 0x10 32 read-write 0x80000 0xFFFFF SCALE_FACTOR_H Scale factor has to be greater than 0.0 and less than or equal to 1.0. If scale_mode is UPSCALE then the inverse scale factor has to be programmed. (format is unsigned fix-point 1.19) [19:0] read-write SCALERSETUPH1 Phase interpolator setup. 0x14 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_H Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the right, a positive one to the left. (format is signed fix-point 2.19) [20:0] read-write SCALERSETUPV0 Phase interpolator setup. 0x18 32 read-write 0x80000 0xFFFFF SCALE_FACTOR_V Scale factor is greater than 0.0 and less than or equal to 1.0. If scale_mode is UPSCALE then the inverse scale factor have to be programmed. (format is unsigned fix-point 1.19) [19:0] read-write SCALERSETUPV1 Phase interpolator setup, selected if input and output field polarity is 0. 0x1C 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_V Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the bottom, a positive one to the top. (format is signed fix-point 2.19) [20:0] read-write SCALERSETUPV2 Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. 0x20 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_V1 Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the bottom, a positive one to the top. (format is signed fix-point 2.19) [20:0] read-write SCALERSETUPV3 Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. 0x24 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_V2 Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the bottom, a positive one to the top. (format is signed fix-point 2.19) [20:0] read-write SCALERSETUPV4 Phase interpolator setup, selected if input and output field polarity is 1. 0x28 32 read-write 0x0 0x1FFFFF PHASE_OFFSET_V3 Phase offset has to be larger than -2 and smaller than +2. Depending on scale_mode this value is relative to input (UPSCALE) or output pixel (DOWNSCALE). A negative value shifts the image to the bottom, a positive one to the top. (format is signed fix-point 2.19) [20:0] read-write FILTERCONTROL Filter operation control. 0x2C 32 read-write 0x0 0xFF33FF77 TAPS_H Defines the horizontal size of the FIR filter between 1 and 15 with increment of 2. Only odd filter width is supported. To program this field following formula has to be used: (filter width - 1)/2 (format is unsigned integer) [2:0] read-write TAPS_V Defines the vertical size of the FIR filter between 1 and 15 with increment of 2. Only odd filter width is supported. To program this field following formula has to be used: (filter height - 1)/2 (format is unsigned integer) [6:4] read-write BYPASS_MODE_R Bypass configuration for red color components of every pixel. (format is unsigned integer) [8:8] read-write NEUTRAL Red color is filtered. 0 ACTIVE Red color is not filtered, but is written to the line buffer. 1 BYPASS_MODE_G Bypass configuration for green color components of every pixel. (format is unsigned integer) [9:9] read-write NEUTRAL Green color is filtered. 0 ACTIVE Green color is not filtered, but is written to the line buffer. 1 BYPASS_MODE_B Bypass configuration for blue color components of every pixel. (format is unsigned integer) [10:10] read-write NEUTRAL Blue color is filtered. 0 ACTIVE Blue color is not filtered, but is written to the line buffer. 1 BYPASS_MODE_A Bypass configuration for alpha components of every pixel. (format is unsigned integer) [11:11] read-write NEUTRAL Alpha is filtered. 0 ACTIVE Alpha is not filtered, but is written to the line buffer. 1 EXPONENT_FIR FIR product sum is divided by 2**FIR_exponent and rounded. (format is unsigned integer) [15:12] read-write TILE_MODE Selects the tile mode for pixels outside the source frame. In order to enable tiling tiling_at_begin_h or tiling_at_begin_v and the corresponding output frame dimension have to be set. (format is unsigned integer) [17:16] read-write TILE_FILL_ZERO Use zero value. 0 TILE_FILL_CONSTANT Use constant color value from the field tile_color. 1 TILE_PAD Use closest pixel from source frame. 2 TILE_PAD_ZERO Use closest pixel from source buffer but zero for alpha component. 3 TILING_AT_BEGIN_H If set to true, this bit enables tiling at the begin of the slice for horizontal direction. Tiling at the end occurs automatically by setting the corresponding output size. (format is unsigned integer) [20:20] read-write TILING_AT_BEGIN_V If set to true, this bit enables tiling at the begin of the slice for vertical direction. Tiling at the end occurs automatically by setting the corresponding output size. (format is unsigned integer) [21:21] read-write TILE_COLOR_ALPHA Sets the alpha value for pixels outside of the slice. (format is unsigned integer) [31:24] read-write TILECOLORRGB Color for outside of the slice. 0x30 32 read-write 0x0 0x3FFFFFFF TILE_COLOR_RED Sets the red color value for pixels outside of the slice. (format is unsigned integer) [9:0] read-write TILE_COLOR_GREEN Sets the green color value for pixels outside of the slice. (format is unsigned integer) [19:10] read-write TILE_COLOR_BLUE Sets the blue color value for pixels outside of the slice. (format is unsigned integer) [29:20] read-write COEFFICIENTSH0 Horizontal coefficients for filter_mode FIR. 0x34 32 read-write 0x0 0xFFFFFFFF COEFF_H3 Horizontal coefficient 3. (format is signed integer) [7:0] read-write COEFF_H2 Horizontal coefficient 2. (format is signed integer) [15:8] read-write COEFF_H1 Horizontal coefficient 1. (format is signed integer) [23:16] read-write COEFF_H0 Horizontal coefficient 0. (format is signed integer) [31:24] read-write COEFFICIENTSH1 Horizontal coefficients for filter_mode FIR. 0x38 32 read-write 0x0 0xFFFFFFFF COEFF_H7 Horizontal coefficient 7. (format is signed integer) [7:0] read-write COEFF_H6 Horizontal coefficient 6. (format is signed integer) [15:8] read-write COEFF_H5 Horizontal coefficient 5. (format is signed integer) [23:16] read-write COEFF_H4 Horizontal coefficient 4. (format is signed integer) [31:24] read-write COEFFICIENTSH2 Horizontal coefficients for filter_mode FIR. 0x3C 32 read-write 0x0 0xFFFFFFFF COEFF_H11 Horizontal coefficient 11. (format is signed integer) [7:0] read-write COEFF_H10 Horizontal coefficient 10. (format is signed integer) [15:8] read-write COEFF_H9 Horizontal coefficient 9. (format is signed integer) [23:16] read-write COEFF_H8 Horizontal coefficient 8. (format is signed integer) [31:24] read-write COEFFICIENTSH3 Horizontal coefficients for filter_mode FIR. 0x40 32 read-write 0x0 0xFFFFFF00 COEFF_H14 Horizontal coefficient 14. The rightmost coefficient regardless of the filter width. In contrast to the coeff_h0 this coefficient has to be always programmed. (format is signed integer) [15:8] read-write COEFF_H13 Horizontal coefficient 13. (format is signed integer) [23:16] read-write COEFF_H12 Horizontal coefficient 12. (format is signed integer) [31:24] read-write COEFFICIENTSV0 Vertical coefficients for filter_mode FIR. 0x44 32 read-write 0x0 0xFFFFFFFF COEFF_V3 Vertical coefficient 3. (format is signed integer) [7:0] read-write COEFF_V2 Vertical coefficient 2. (format is signed integer) [15:8] read-write COEFF_V1 Vertical coefficient 1. (format is signed integer) [23:16] read-write COEFF_V0 Vertical coefficient 0. (format is signed integer) [31:24] read-write COEFFICIENTSV1 Vertical coefficients for filter_mode FIR. 0x48 32 read-write 0x0 0xFFFFFFFF COEFF_V7 Vertical coefficient 7. (format is signed integer) [7:0] read-write COEFF_V6 Vertical coefficient 6. (format is signed integer) [15:8] read-write COEFF_V5 Vertical coefficient 5. (format is signed integer) [23:16] read-write COEFF_V4 Vertical coefficient 4. (format is signed integer) [31:24] read-write COEFFICIENTSV2 Vertical coefficients for filter_mode FIR. 0x4C 32 read-write 0x0 0xFFFFFFFF COEFF_V11 Vertical coefficient 11. (format is signed integer) [7:0] read-write COEFF_V10 Vertical coefficient 10. (format is signed integer) [15:8] read-write COEFF_V9 Vertical coefficient 9. (format is signed integer) [23:16] read-write COEFF_V8 Vertical coefficient 8. (format is signed integer) [31:24] read-write COEFFICIENTSV3 Vertical coefficients for filter_mode FIR. 0x50 32 read-write 0x0 0xFFFFFF00 COEFF_V14 Vertical coefficient 14. The bottommost coefficient regardless of the filter height. In contrast to the coeff_v0 this coefficient has to be always programmed. (format is signed integer) [15:8] read-write COEFF_V13 Vertical coefficient 13. (format is signed integer) [23:16] read-write COEFF_V12 Vertical coefficient 12. (format is signed integer) [31:24] read-write HISTOGRAM4 Video Processing Block #0 Histogram (Capture) 0x00007400 CONTROL Controls some settings concerning input components and alpha mask. 0x0 32 read-write 0x0 0x3331 CLIP_EN Switch for clip window. If enabled all pixels outside the clip window are not taken into account. (format is unsigned integer) [0:0] read-write DISABLE Clip window is switched off. 0 ENABLE Clip window is switched on. 1 COLOR_SPACE_MODE Assuming that YUV(YCrCb) color components according to BT.601 or BT.709 are provided at histogram input the appropriate conversion to RGB components in [0,255] range can be selected here. (format is unsigned integer) [5:4] read-write NO_CONV No color space conversion of input components is applied. 0 YUV2RGB_BT601 YUV input components as described in BT.601 are converted to RGB in [0,255] range. 1 YUV2RGB_BT709 YUV input components as described in BT.709 are converted to RGB in [0,255] range. 2 LUM_MODE If a histogram for luma or luminance is required, the conversion formula for luma (Y component according to BT.601) or luminance (Y component according to BT.709) can be selected here. Luma or luminance calculation should only be applied if RGB components in range [0..255] are delivered directly at histogram input or when YCrCb components are converted to RGB by the appropriate setting of register field color_space_mode. Luma or luminance counting is delivered in first (component0) histogram. (format is unsigned integer) [9:8] read-write NO_CONV Component0 for first histogram is counted as it is. 0 LUMA Component0 for first histogram is replaced by luma, which is calculated from RGB input components according to BT.601. 1 LUMINANCE Component0 for first histogram is replaced by luminance, which is calculated from RGB input components according to BT.709. 2 ALPHAMASK Value 1 enables the alpha mask mode. In this mode only pixels with an alpha value larger than 0.5 are affecting the histogram bins. [12:12] read-write ALPHAINVERT Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha value smaller or equal 0.5 are affecting the histogram bins). [13:13] read-write BINPROPERTIES Configures the histogram bins. 0x4 32 read-write 0x3 0x117 BINNUM_WIDTH 2**binnum_width is the number of bins in a histogram. (format is unsigned integer) [2:0] read-write BINS_8 There are 8 bins, addressable with 3bit. 3 BINS_16 There are 16 bins, addressable with 4bit. 4 BINS_32 There are 32 bins, addressable with 5bit. 5 BINS_64 There are 64 bins, addressable with 6bit. 6 CNT_MODE Counter mode, which controls the way the bin values are accumulated. (format is unsigned integer) [4:4] read-write NEAREST Counter of nearest bin is incremented. 0 LINEAR Counters of the 2 nearest bins are increased by one minus the distance to bin center (normalized between 0 and 1), it works only for first (component0) histogram, reading of component1/2 histogram results in undefined data. 1 BINCNT_RD_MODE The field controls if the actual bin count or the sum of all bin counts up to actual bin count is provided in registers RsltComp0Bincnt, RsltComp1Bincnt and RsltComp2Bincnt. (format is unsigned integer) [8:8] read-write BINCNT Actual bin cnt is provided. 0 BINCNT_ACCU Bin count sum is provided. 1 BINCNTTHRESH Bin counter threshold value. 0x8 32 read-write 0x0 0x1FFFFFFF BINCNT_THRESH Bin counters below this threshold will be reported as 0. This threshold value will also affect the BINCNT_ACCU mode where 0 will be added for all bin counters below the threshold. (format is unsigned integer) [28:0] read-write CLIPWINUPPERLEFT Coordinates of upper left corner of clip window. 0xC 32 read-write 0x0 0x3FFF3FFF CLIP_X X coordinate of upper left corner of clip window. (format is unsigned integer) [13:0] read-write CLIP_Y Y coordinate of upper left corner of clip window. (format is unsigned integer) [29:16] read-write CLIPWINSIZE Dimensions of clip window. 0x10 32 read-write 0x0 0x3FFF3FFF CLIP_WIDTH Width of clip window, given minus one. (format is unsigned integer) [13:0] read-write CLIP_HEIGHT Height of clip window, given minus one. (format is unsigned integer) [29:16] read-write RSLTRDY Measurement result status. 0x14 32 read-only 0x0 0x1 RSLT_RDY A one indicates that measurement results (in registers Rslt...) are valid and can be read. (format is unsigned integer) [0:0] read-only RSLTFRMINF Additional information on the measurement results. 0x18 32 read-only 0x0 0x100FF FRM_IDX Each frame passing the histogram unit gets an index, which is the value of a wrapped around counter, which counts the frames independent from how the histogram unit is configured. The index of the frame of the ongoing readout can be read here. In display stream context, if the display operation ends (framegen is switched off and sequence complete occurs) this frame index is reset to 0. (format is unsigned integer) [7:0] read-only FLD_POLARITY Returns field polarity of the measured frame. This read value of this field is undefined in display stream context; use in storage, content or safety stream context only. (format is unsigned integer) [16:16] read-only RSLTCOMP0BINIDX Results of frame measurement for component 0. 0x1C 32 read-only 0x0 0x3F003F COMP0_BINIDX_MAXCNT The index of the bin of the component 0 histogram, which contains the highest counter value, which were read until now for the ongoing readout. In the case of RGB pixels, component 0 means the red value, in the case of YUV pixels, component0 means the Y value. If luma/luminance calculation is switched on by field lum_mode component0 is the calculated luma/luminance. (format is unsigned integer) [5:0] read-only COMP0_BINIDX_NXT Do not use this filed. The index of the bin, that will be next accessed by register RsltComp0Bincnt. In the case of RGB pixels, component0 means the red value, in the case of YUV pixels, component 0 means the Y value. If luma/luminance calculation is switched on by field lum_mode component0 is the calculated luma/luminance. (format is unsigned integer) [21:16] read-only RSLTCOMP1BINIDX Results of frame measurement for component 1. 0x20 32 read-only 0x0 0x3F003F COMP1_BINIDX_MAXCNT The index of the bin of the component 1 histogram, which contains the highest counter value, which were read until now for the ongoing readout. In the case of RGB pixels, component 1 means the green value. In the case of YUV pixels, component 1 means the Cb value. (format is unsigned integer) [5:0] read-only COMP1_BINIDX_NXT The index of the bin, that will be next accessed by register RsltComp1Bincnt. In the case of RGB pixels, component 1 means the green value. In the case of YUV pixels, component 1 means the Cb value. (format is unsigned integer) [21:16] read-only RSLTCOMP2BINIDX Results of frame measurement for component 2. 0x24 32 read-only 0x0 0x3F003F COMP2_BINIDX_MAXCNT The index of the bin of the component 2 histogram, which contains the highest counter value, which were read until now for the ongoing readout. In the case of RGB pixels, component 2 means the blue value. In the case of YUV pixels, component 2 means the Cr value. (format is unsigned integer) [5:0] read-only COMP2_BINIDX_NXT The index of the bin, that will be next accessed by register RsltComp2Bincnt. In the case of RGB pixels, component 2 means the blue value. In the case of YUV pixels, component 2 means the Cr value. (format is unsigned integer) [21:16] read-only RSLTCOMP0SUM Sum of all component 0 values. 0x28 32 read-only 0x0 0xFFFFFFFF COMP0_SUM Sum of all component 0 values. In the case of RGB pixels, component 0 means the red value, in the case of YUV pixels, component 0 means the Y value. If luma/luminance calculation is switched on by field lum_mode, component 0 is the calculated luma/luminance. If the read value is 0xFFFFFFFF a counter overflow has occurred and the read value should not be used (this can only happen for frame dimensions beyond 2^12 * 2^12). (format is unsigned integer) [31:0] read-only RSLTCOMP1SUM Sum of all component 1 values. 0x2C 32 read-only 0x0 0xFFFFFFFF COMP1_SUM Sum of all component 1 values. In the case of RGB pixels, component 1 means the green value. In the case of YUV pixels, component 1 means the Cb value. If the read value is 0xFFFFFFFF a counter overflow has occurred and the read value should not be used (this can only happen for frame dimensions beyond 2^12 * 2^12). (format is unsigned integer) [31:0] read-only RSLTCOMP2SUM Sum of all component 2 values. 0x30 32 read-only 0x0 0xFFFFFFFF COMP2_SUM Sum of all component 2 values. In the case of RGB pixels, component 2 means the blue value. In the case of YUV pixels, component 2 means the Cr value. If the read value is 0xFFFFFFFF a counter overflow has occurred and the read value should not be used (this can only happen for frame dimensions beyond 2^12 * 2^12). (format is unsigned integer) [31:0] read-only RSLTCOMP0BINCNT Bin counters of component 0 histogram. This register do NOT support debugger access followed by software access (they clear on read) 0x34 32 read-only 0x0 0x1FFFFFFF COMP0_BINCNT Counter of current bin number in component 0 histogram. In the case of RGB pixels, component 0 means the red value, in the case of YUV pixels, component 0 means the Y value. (format is unsigned integer) [28:0] read-only RSLTCOMP1BINCNT Bin counters of component 1 histogram. This register do NOT support debugger access followed by software access (they clear on read) 0x38 32 read-only 0x0 0x1FFFFFFF COMP1_BINCNT Counter of current bin number in component 1 histogram. In the case of RGB pixels, component 1 means the green value. In the case of YUV pixels, component 1 means the Cb value. (format is unsigned integer) [28:0] read-only RSLTCOMP2BINCNT Bin counters of component 2 histogram. This register do NOT support debugger access followed by software access (they clear on read) 0x3C 32 read-only 0x0 0x1FFFFFFF COMP2_BINCNT Counter of current bin index in component 2 histogram. In the case of RGB pixels, component 2 means the blue value. In the case of YUV pixels, component 2 means the Cb value. (format is unsigned integer) [28:0] read-only FRMSTRTTRIG Triggers for loading shadow registers and starting measurement with next input frame. 0x40 32 write-only 0x0 0x0 MSRMNT_STRT_TRIG Writing value 1 into this field initiates the measurement of the next frame. (format is unsigned integer) [0:0] write-only LAYERBLEND1 LayerBlend #1 (Display, Alpha Plane 1) 0x00007800 STATICCONTROL Static control settings. 0x0 32 read-write 0x14 0x1F SHDEN Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). [0:0] read-write SHDLDSEL Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. [2:1] read-write PRIMARY Load shadows with shadow load token on primary input (background plane). 0 SECONDARY Load shadows with shadow load token on secondary input (foreground plane). 1 BOTH Load shadows with shadow load token on any input. 2 SHDTOKSEL Controls when a shadow load token is generated on the output port, which controls shadow load in subsequent processing units. [4:3] read-write PRIMARY When a token was received on the primary input (background plane). 0 SECONDARY When a token was received on the secondary input (foreground plane). 1 BOTH When a token was received on any input. 2 CONTROL Common control settings. 0x4 32 read-write 0x1 0x3FFFF75 MODE Operation mode. [0:0] read-write NEUTRAL Module is in neutral mode. Output is same as primary input. 0 BLEND Module is in blending mode. 1 ALPHAMASKENABLE Enables Alpha Mask feature. This will limit possible output alpha values to 0 and 255. Generation of this alpha value will depend on the AlphaMaskMode field. [2:2] read-write DISABLE AlphaMask feature disabled 0 ENABLE AlphaMask feature enabled 1 ALPHAMASKMODE AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE [6:4] read-write PRIM Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 0 SEC The area of the secondary input will get an alpha value of 255 and the rest will be 0 1 PRIM_OR_SEC Behaves as if the output of modes PRIM and SEC would be ORed together 2 PRIM_AND_SEC Behaves as if the output of modes PRIM and SEC would be ANDed together 3 PRIM_INV Behaves as if the output of mode PRIM would be inverted 4 SEC_INV Behaves as if the output of mode SEC would be inverted 5 PRIM_OR_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ORed together 6 PRIM_AND_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ANDed together 7 SECLOWPASSEN Enables a horizontal low-pass filter for the secondary input port. Should be used for dual view and dual display mode when the secondary input frame has twice the resolution of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. [8:8] read-write SECREPLICATEEN Enables horizontal replication of pixels by factor 2 on secondary input port. Must be used for dual display mode when the secondary input frame has the resolution of one display (= half the resolution of the panel interface). [9:9] read-write SECEVENROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is even. R/Y is MSBit, A is LSBit. [13:10] read-write SECEVENROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is even and column index is odd. R/Y is MSBit, A is LSBit. [17:14] read-write SECODDROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is odd and column index is even. R/Y is MSBit, A is LSBit. [21:18] read-write SECODDROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is odd. R/Y is MSBit, A is LSBit. [25:22] read-write BLENDCONTROL Options for blend operations 0x8 32 read-write 0x1010 0xFF7777 PRIM_C_BLD_FUNC Primary (background) input color blending function [2:0] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 SEC_C_BLD_FUNC Secondary (overlay) input color blending function [6:4] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 PRIM_A_BLD_FUNC Primary (background) input alpha blending function [10:8] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 SEC_A_BLD_FUNC Secondary (overlay) input alpha blending function [14:12] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 BLENDALPHA Constant alpha value, used for constant alpha blending [23:16] read-write POSITION Position of secondary (overlay) input frame 0xC 32 read-write 0x0 0xFFFFFFFF XPOS horizontal position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [15:0] read-write YPOS vertical position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [31:16] read-write LAYERBLEND2 LayerBlend #2 (Display, Alpha Plane 2) 0x00007C00 STATICCONTROL Static control settings. 0x0 32 read-write 0x14 0x1F SHDEN Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). [0:0] read-write SHDLDSEL Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. [2:1] read-write PRIMARY Load shadows with shadow load token on primary input (background plane). 0 SECONDARY Load shadows with shadow load token on secondary input (foreground plane). 1 BOTH Load shadows with shadow load token on any input. 2 SHDTOKSEL Controls when a shadow load token is generated on the output port, which controls shadow load in subsequent processing units. [4:3] read-write PRIMARY When a token was received on the primary input (background plane). 0 SECONDARY When a token was received on the secondary input (foreground plane). 1 BOTH When a token was received on any input. 2 CONTROL Common control settings. 0x4 32 read-write 0x1 0x3FFFF75 MODE Operation mode. [0:0] read-write NEUTRAL Module is in neutral mode. Output is same as primary input. 0 BLEND Module is in blending mode. 1 ALPHAMASKENABLE Enables Alpha Mask feature. This will limit possible output alpha values to 0 and 255. Generation of this alpha value will depend on the AlphaMaskMode field. [2:2] read-write DISABLE AlphaMask feature disabled 0 ENABLE AlphaMask feature enabled 1 ALPHAMASKMODE AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE [6:4] read-write PRIM Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 0 SEC The area of the secondary input will get an alpha value of 255 and the rest will be 0 1 PRIM_OR_SEC Behaves as if the output of modes PRIM and SEC would be ORed together 2 PRIM_AND_SEC Behaves as if the output of modes PRIM and SEC would be ANDed together 3 PRIM_INV Behaves as if the output of mode PRIM would be inverted 4 SEC_INV Behaves as if the output of mode SEC would be inverted 5 PRIM_OR_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ORed together 6 PRIM_AND_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ANDed together 7 SECLOWPASSEN Enables a horizontal low-pass filter for the secondary input port. Should be used for dual view and dual display mode when the secondary input frame has twice the resolution of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. [8:8] read-write SECREPLICATEEN Enables horizontal replication of pixels by factor 2 on secondary input port. Must be used for dual display mode when the secondary input frame has the resolution of one display (= half the resolution of the panel interface). [9:9] read-write SECEVENROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is even. R/Y is MSBit, A is LSBit. [13:10] read-write SECEVENROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is even and column index is odd. R/Y is MSBit, A is LSBit. [17:14] read-write SECODDROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is odd and column index is even. R/Y is MSBit, A is LSBit. [21:18] read-write SECODDROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is odd. R/Y is MSBit, A is LSBit. [25:22] read-write BLENDCONTROL Options for blend operations 0x8 32 read-write 0x1010 0xFF7777 PRIM_C_BLD_FUNC Primary (background) input color blending function [2:0] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 SEC_C_BLD_FUNC Secondary (overlay) input color blending function [6:4] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 PRIM_A_BLD_FUNC Primary (background) input alpha blending function [10:8] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 SEC_A_BLD_FUNC Secondary (overlay) input alpha blending function [14:12] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 BLENDALPHA Constant alpha value, used for constant alpha blending [23:16] read-write POSITION Position of secondary (overlay) input frame 0xC 32 read-write 0x0 0xFFFFFFFF XPOS horizontal position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [15:0] read-write YPOS vertical position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [31:16] read-write LAYERBLEND3 LayerBlend #3 (Display, Alpha Plane 3) 0x00008000 STATICCONTROL Static control settings. 0x0 32 read-write 0x14 0x1F SHDEN Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). [0:0] read-write SHDLDSEL Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. [2:1] read-write PRIMARY Load shadows with shadow load token on primary input (background plane). 0 SECONDARY Load shadows with shadow load token on secondary input (foreground plane). 1 BOTH Load shadows with shadow load token on any input. 2 SHDTOKSEL Controls when a shadow load token is generated on the output port, which controls shadow load in subsequent processing units. [4:3] read-write PRIMARY When a token was received on the primary input (background plane). 0 SECONDARY When a token was received on the secondary input (foreground plane). 1 BOTH When a token was received on any input. 2 CONTROL Common control settings. 0x4 32 read-write 0x1 0x3FFFF75 MODE Operation mode. [0:0] read-write NEUTRAL Module is in neutral mode. Output is same as primary input. 0 BLEND Module is in blending mode. 1 ALPHAMASKENABLE Enables Alpha Mask feature. This will limit possible output alpha values to 0 and 255. Generation of this alpha value will depend on the AlphaMaskMode field. [2:2] read-write DISABLE AlphaMask feature disabled 0 ENABLE AlphaMask feature enabled 1 ALPHAMASKMODE AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE [6:4] read-write PRIM Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 0 SEC The area of the secondary input will get an alpha value of 255 and the rest will be 0 1 PRIM_OR_SEC Behaves as if the output of modes PRIM and SEC would be ORed together 2 PRIM_AND_SEC Behaves as if the output of modes PRIM and SEC would be ANDed together 3 PRIM_INV Behaves as if the output of mode PRIM would be inverted 4 SEC_INV Behaves as if the output of mode SEC would be inverted 5 PRIM_OR_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ORed together 6 PRIM_AND_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ANDed together 7 SECLOWPASSEN Enables a horizontal low-pass filter for the secondary input port. Should be used for dual view and dual display mode when the secondary input frame has twice the resolution of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. [8:8] read-write SECREPLICATEEN Enables horizontal replication of pixels by factor 2 on secondary input port. Must be used for dual display mode when the secondary input frame has the resolution of one display (= half the resolution of the panel interface). [9:9] read-write SECEVENROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is even. R/Y is MSBit, A is LSBit. [13:10] read-write SECEVENROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is even and column index is odd. R/Y is MSBit, A is LSBit. [17:14] read-write SECODDROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is odd and column index is even. R/Y is MSBit, A is LSBit. [21:18] read-write SECODDROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is odd. R/Y is MSBit, A is LSBit. [25:22] read-write BLENDCONTROL Options for blend operations 0x8 32 read-write 0x1010 0xFF7777 PRIM_C_BLD_FUNC Primary (background) input color blending function [2:0] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 SEC_C_BLD_FUNC Secondary (overlay) input color blending function [6:4] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 PRIM_A_BLD_FUNC Primary (background) input alpha blending function [10:8] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 SEC_A_BLD_FUNC Secondary (overlay) input alpha blending function [14:12] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 BLENDALPHA Constant alpha value, used for constant alpha blending [23:16] read-write POSITION Position of secondary (overlay) input frame 0xC 32 read-write 0x0 0xFFFFFFFF XPOS horizontal position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [15:0] read-write YPOS vertical position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [31:16] read-write LAYERBLEND4 LayerBlend #4 (Display, Alpha Plane 4) 0x00008400 STATICCONTROL Static control settings. 0x0 32 read-write 0x14 0x1F SHDEN Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). [0:0] read-write SHDLDSEL Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. [2:1] read-write PRIMARY Load shadows with shadow load token on primary input (background plane). 0 SECONDARY Load shadows with shadow load token on secondary input (foreground plane). 1 BOTH Load shadows with shadow load token on any input. 2 SHDTOKSEL Controls when a shadow load token is generated on the output port, which controls shadow load in subsequent processing units. [4:3] read-write PRIMARY When a token was received on the primary input (background plane). 0 SECONDARY When a token was received on the secondary input (foreground plane). 1 BOTH When a token was received on any input. 2 CONTROL Common control settings. 0x4 32 read-write 0x1 0x3FFFF75 MODE Operation mode. [0:0] read-write NEUTRAL Module is in neutral mode. Output is same as primary input. 0 BLEND Module is in blending mode. 1 ALPHAMASKENABLE Enables Alpha Mask feature. This will limit possible output alpha values to 0 and 255. Generation of this alpha value will depend on the AlphaMaskMode field. [2:2] read-write DISABLE AlphaMask feature disabled 0 ENABLE AlphaMask feature enabled 1 ALPHAMASKMODE AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE [6:4] read-write PRIM Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 0 SEC The area of the secondary input will get an alpha value of 255 and the rest will be 0 1 PRIM_OR_SEC Behaves as if the output of modes PRIM and SEC would be ORed together 2 PRIM_AND_SEC Behaves as if the output of modes PRIM and SEC would be ANDed together 3 PRIM_INV Behaves as if the output of mode PRIM would be inverted 4 SEC_INV Behaves as if the output of mode SEC would be inverted 5 PRIM_OR_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ORed together 6 PRIM_AND_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ANDed together 7 SECLOWPASSEN Enables a horizontal low-pass filter for the secondary input port. Should be used for dual view and dual display mode when the secondary input frame has twice the resolution of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. [8:8] read-write SECREPLICATEEN Enables horizontal replication of pixels by factor 2 on secondary input port. Must be used for dual display mode when the secondary input frame has the resolution of one display (= half the resolution of the panel interface). [9:9] read-write SECEVENROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is even. R/Y is MSBit, A is LSBit. [13:10] read-write SECEVENROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is even and column index is odd. R/Y is MSBit, A is LSBit. [17:14] read-write SECODDROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is odd and column index is even. R/Y is MSBit, A is LSBit. [21:18] read-write SECODDROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is odd. R/Y is MSBit, A is LSBit. [25:22] read-write BLENDCONTROL Options for blend operations 0x8 32 read-write 0x1010 0xFF7777 PRIM_C_BLD_FUNC Primary (background) input color blending function [2:0] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 SEC_C_BLD_FUNC Secondary (overlay) input color blending function [6:4] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 PRIM_A_BLD_FUNC Primary (background) input alpha blending function [10:8] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 SEC_A_BLD_FUNC Secondary (overlay) input alpha blending function [14:12] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 BLENDALPHA Constant alpha value, used for constant alpha blending [23:16] read-write POSITION Position of secondary (overlay) input frame 0xC 32 read-write 0x0 0xFFFFFFFF XPOS horizontal position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [15:0] read-write YPOS vertical position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [31:16] read-write LAYERBLEND5 LayerBlend #5 (Display, Alpha Plane 5) 0x00008800 STATICCONTROL Static control settings. 0x0 32 read-write 0x14 0x1F SHDEN Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). [0:0] read-write SHDLDSEL Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. [2:1] read-write PRIMARY Load shadows with shadow load token on primary input (background plane). 0 SECONDARY Load shadows with shadow load token on secondary input (foreground plane). 1 BOTH Load shadows with shadow load token on any input. 2 SHDTOKSEL Controls when a shadow load token is generated on the output port, which controls shadow load in subsequent processing units. [4:3] read-write PRIMARY When a token was received on the primary input (background plane). 0 SECONDARY When a token was received on the secondary input (foreground plane). 1 BOTH When a token was received on any input. 2 CONTROL Common control settings. 0x4 32 read-write 0x1 0x3FFFF75 MODE Operation mode. [0:0] read-write NEUTRAL Module is in neutral mode. Output is same as primary input. 0 BLEND Module is in blending mode. 1 ALPHAMASKENABLE Enables Alpha Mask feature. This will limit possible output alpha values to 0 and 255. Generation of this alpha value will depend on the AlphaMaskMode field. [2:2] read-write DISABLE AlphaMask feature disabled 0 ENABLE AlphaMask feature enabled 1 ALPHAMASKMODE AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE [6:4] read-write PRIM Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 0 SEC The area of the secondary input will get an alpha value of 255 and the rest will be 0 1 PRIM_OR_SEC Behaves as if the output of modes PRIM and SEC would be ORed together 2 PRIM_AND_SEC Behaves as if the output of modes PRIM and SEC would be ANDed together 3 PRIM_INV Behaves as if the output of mode PRIM would be inverted 4 SEC_INV Behaves as if the output of mode SEC would be inverted 5 PRIM_OR_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ORed together 6 PRIM_AND_SEC_INV Behaves as if the output of modes PRIM and SEC_INV would be ANDed together 7 SECLOWPASSEN Enables a horizontal low-pass filter for the secondary input port. Should be used for dual view and dual display mode when the secondary input frame has twice the resolution of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. [8:8] read-write SECREPLICATEEN Enables horizontal replication of pixels by factor 2 on secondary input port. Must be used for dual display mode when the secondary input frame has the resolution of one display (= half the resolution of the panel interface). [9:9] read-write SECEVENROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is even. R/Y is MSBit, A is LSBit. [13:10] read-write SECEVENROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is even and column index is odd. R/Y is MSBit, A is LSBit. [17:14] read-write SECODDROWEVENCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row index is odd and column index is even. R/Y is MSBit, A is LSBit. [21:18] read-write SECODDROWODDCOLDIS Disable bits for R/Y, G/U, B/V and A channels of secondary input when row and column index is odd. R/Y is MSBit, A is LSBit. [25:22] read-write BLENDCONTROL Options for blend operations 0x8 32 read-write 0x1010 0xFF7777 PRIM_C_BLD_FUNC Primary (background) input color blending function [2:0] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 SEC_C_BLD_FUNC Secondary (overlay) input color blending function [6:4] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 PRIM_A_BLD_FUNC Primary (background) input alpha blending function [10:8] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 SEC_A_BLD_FUNC Secondary (overlay) input alpha blending function [14:12] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 BLENDALPHA Constant alpha value, used for constant alpha blending [23:16] read-write POSITION Position of secondary (overlay) input frame 0xC 32 read-write 0x0 0xFFFFFFFF XPOS horizontal position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [15:0] read-write YPOS vertical position, first pixel is at 0, format s15 (twos complement) (format is signed integer) [31:16] read-write EXTSRC8 ExtSrc #8 (Display) 0x00008C00 STATICCONTROL ExtSrc static control register 0x0 32 read-write 0x0 0x101 SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write STARTSEL Start select selects the mode to start processing operations. [8:8] read-write INPUT Free running mode, use the incoming command word as trigger to start processing. 0 LOCAL Keep to local start configuration, use external kick or SW trigger to start processing. The behavior is similar to fetch units. 1 CLIPWINDOWOFFSET Clip window offset, to generate a clipping of the frame. It has to be within the input frame. 0x4 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWXOFFSET Clip window offset in X direction, relative to the frame origin. [13:0] read-write CLIPWINDOWYOFFSET Clip window offset in Y direction, relative to the frame origin. [29:16] read-write CLIPWINDOWDIMENSION Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame. 0x8 32 read-write 0x0 0x3FFF3FFF CLIPWINDOWWIDTH Clip window width in pixels minus one. [13:0] read-write CLIPWINDOWHEIGHT Clip window height in pixels minus one. [29:16] read-write COLORCOMPONENTBITS Color component size of raw input data. Please note that the width must be equal or lower than the output width. 0xC 32 read-write 0x8080808 0x8F0F0F0F COMPONENTBITSALPHA Component size of alpha channel [0-8]. [3:0] read-write COMPONENTBITSBLUE Component size of blue channel [0-10]. [11:8] read-write COMPONENTBITSGREEN Component size of green channel [0-10]. [19:16] read-write COMPONENTBITSRED Component size of red channel [0-10]. [27:24] read-write ITUFORMAT When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This is compliant to ITU 656 standard. [31:31] read-write COLORCOMPONENTSHIFT Color component offset of raw input data. 0x10 32 read-write 0x10080018 0x3F3F3F3F COMPONENTSHIFTALPHA Offset for alpha component. [5:0] read-write COMPONENTSHIFTBLUE Offset for blue component. [13:8] read-write COMPONENTSHIFTGREEN Offset for green component. [21:16] read-write COMPONENTSHIFTRED Offset for red component. [29:24] read-write CONSTANTCOLOR Constant color register 0x14 32 read-write 0x0 0xFFFFFFFF CONSTANTALPHA Alpha. [7:0] read-write CONSTANTBLUE Blue or V (chroma). [15:8] read-write CONSTANTGREEN Green or U (chroma). [23:16] read-write CONSTANTRED Red or Y (luma). [31:24] read-write CONTROL Common control settings. 0x18 32 read-write 0x1000 0x17FF1 CLIPWINDOWENABLE Value 1 enables the clip window feature. [0:0] read-write RASTERMODE Selects a method how generate output samples from input stream. [4:4] read-write NORMAL Input stream is RGB(A) or YUV 4:4:4. 0 YUV422 Input stream is packed YUV 4:2:2. 1 YUV422UPSAMPLINGMODE Selects a method for horizontal up-sampling when RasterMode is YUV422. [5:5] read-write REPLICATE Replicate mode for interspersed samples (UV samples between Y samples). 0 INTERPOLATE Interpolate mode for coaligned samples (UV samples at Y sample positions). 1 YUVCONVERSIONMODE Enables different kind of YUV to RGB conversions. [7:6] read-write OFF No conversion. Input data must be RGB. 0 ITU601 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). Input range is 16..235 for Y and 16..240 for U/V. 1 ITU601_FR Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). 2 ITU709 Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). Input range is 16..235 for Y and 16..240 for U/V. 3 RGBALPHASRCENABLE Value 1 enables source alpha (extracted from input stream) for RGB pre-multiply. When disabled source alpha is set to 1. [8:8] read-write RGBALPHACONSTENABLE Value 1 enables constant alpha (ConstAlpha field) for RGB pre-multiply. When disabled constant alpha is set to 1. [9:9] read-write RGBALPHATRANSENABLE Value 1 enables transparent alpha (0 or 1 depending on RGB matching ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. [10:10] read-write PREMULCONSTRGB When enabled (value 1) the values given by ConstantRed/Green/Blue are used instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/TransEnable have no effect then. [11:11] read-write ALPHASRCENABLE Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. [12:12] read-write ALPHACONSTENABLE Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. [13:13] read-write ALPHATRANSENABLE Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. [14:14] read-write GAMMAREMOVEENABLE Value 1 enables the stage to remove a gamma from RGB components. [16:16] read-write CONTROLTRIGGER ExtSrc unit trigger token generation 0x1C 32 write-only 0x0 0x0 SHDTOKGEN Write a 1 to this field for the extsrc unit to perform a shadow load with the next start of operation and set the rld bit in the start of frame control word (generate shadow load token for subsequent units). [0:0] write-only START ExtSrc unit start register 0x20 32 write-only 0x0 0x0 START Writing a one starts processing, use this only for debug purposes. [0:0] write-only DISENG0 Display Engine 0x00020000 DISENGCFG0 Top-Level Configuration 0x00000000 CTL Display engine control register. 0x0 32 read-write 0x1 0x1 DSPCLKDIVIDE Controls generation of display clock signals for display stream. [0:0] read-write DIV1 External display clock signal has pixel clock frequency. 0 DIV2 External display clock signal has twice the pixel clock frequency. 1 POLARITYCTRL Polarity control for TCon input and corresponding top-level output (TCon by-pass port). 0x4 32 read-write 0x4 0xF POLHS Polarity of hsync signal. [0:0] read-write LOW Low active 0 HIGH High active 1 POLVS Polarity of vsync signal. [1:1] read-write LOW Low active 0 HIGH High active 1 POLEN Polarity of Data_Enable signal. [2:2] read-write LOW Low active 0 HIGH High active 1 PIXINV Inversion of RGB data. [3:3] read-write NONINV No inversion of pixel data 0 INV Pixel data inverted (1. complement) 1 SIGSELECT Tap selection for Signature. 0x10 32 read-write 0x0 0x3 SIG_SELECT Selects a source for Sig unit. [1:0] read-write NONE No source. 0 FRAMEGEN Source is FrameGen output. 1 GAMMACOR Source is GammaCor output. 2 DITHER Source is Dither output. 3 DUMPSELECT Tap selection for Frame Dump. 0x20 32 read-write 0x0 0x300 DUMP_SELECT Selects a source for FrameDump unit. [9:8] read-write NONE No source. 0 FRAMEGEN Source is FrameGen output. 1 GAMMACOR Source is GammaCor output. 2 DITHER Source is Dither output. 3 SIG0 Signature Unit 0x00001000 STATICCONTROL Global configuration shared by all evaluation windows. 0x0 32 read-write 0x8000000 0xFFFF0011 SHDEN Enables shadow registers for RWS type fields (0 = write through, 1 = shadowed). [0:0] read-write SHDLDSEL Source select for events that will load shadow registers into the active configuration. [4:4] read-write LOCAL Shadows are loaded at start of frame for each evaluation window for which ShdLdReq has been set. 0 GLOBAL Shadows of all evaluation windows are loaded synchronous to the display stream (shadow load token received on frame input port). 1 ERRTHRES Number of frames with signature violation before StsSigError is set for an evaluation window. These frames do not need to be consecutive. 0 means that each frame with violation will set the status. The internal counter compared against this threshold is reset when 'ErrThreshReset' consecutive frames without signature violation occur. [23:16] read-write ERRTHRESRESET ErrThresReset must be programmed to value less than 255. Number of consecutive frames without signature violation before StsSigError is reset for an evaluation window. 0 means that each frame without violation will reset the status. The internal counter compared against this threshold is reset with each frame that has violation. [31:24] read-write PANICCOLOR Overlay color for evaluation windows in panic mode. 0x4 32 read-write 0x0 0xFFFFFF80 PANICALPHA Alpha mask bit. [7:7] read-write PANICBLUE Blue color component. [15:8] read-write PANICGREEN Green color component. [23:16] read-write PANICRED Red color component. [31:24] read-write EVALCONTROL0 Control settings for evaluation window 0. 0x8 32 read-write 0x0 0x30303 ENEVALWIN0 When enabled (value 1) a CRC signature is computed for all pixels inside this evaluation window (SigCRC). When this bit is cleared, the internal status for this window is reset (StsSigError bit and frame counters). [0:0] read-write ENCRC0 When enabled (value 1) the measured signature is checked against a reference value (SigCRCRef). [1:1] read-write ALPHAMASK0 When enabled (value 1) pixels with alpha bit = 0 are ignored for signature computation. [8:8] read-write ALPHAINV0 When enabled (value 1) the effect of AlphaMask is inverted (pixels with alpha bit = 1 are ignored then). [9:9] read-write ENLOCALPANIC0 When enabled (value 1) the error status this window (StsSigError) will replace all pixels inside the window by a constant color on the display. Skip regions due to other evaluation windows on top are not modified. AlphaMask, when enabled, is not considered for this replacement. [16:16] read-write ENGLOBALPANIC0 When enabled (value 1) the error status of this window (StsSigError) will activate the panic mode of the display stream's Frame Generator, which can switch to another display mode in response. [17:17] read-write EVALUPPERLEFT0 Upper left corner of evaluation window 0. 0xC 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT0 X coordinate. [13:0] read-write YEVALUPPERLEFT0 Y coordinate. [29:16] read-write EVALLOWERRIGHT0 Lower right corner of evaluation window 0. 0x10 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT0 X coordinate. [13:0] read-write YEVALLOWERRIGHT0 Y coordinate. [29:16] read-write SIGCRCREDREF0 Reference signature of red channel for evaluation window 0. 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF0 Reference value that is compared against measured SigCRCRed value. [31:0] read-write SIGCRCGREENREF0 Reference signature of green channel for evaluation window 0. 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF0 Reference value that is compared against measured SigCRCGreen value. [31:0] read-write SIGCRCBLUEREF0 Reference signature of blue channel for evaluation window 0. 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF0 Reference value that is compared against measured SigCRCBlue value. [31:0] read-write SIGCRCRED0 Measured signature of red channel for evaluation window 0. 0x20 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED0 CRC values from red channel. [31:0] read-only SIGCRCGREEN0 Measured signature of green channel for evaluation window 0. 0x24 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN0 CRC values from green channel. [31:0] read-only SIGCRCBLUE0 Measured signature of blue channel for evaluation window 0. 0x28 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE0 CRC values from blue channel. [31:0] read-only EVALCONTROL1 Control settings for evaluation window 1. 0x2C 32 read-write 0x0 0x30303 ENEVALWIN1 See EnEvalWin0. [0:0] read-write ENCRC1 See EnCRC0. [1:1] read-write ALPHAMASK1 See AlphaMask0. [8:8] read-write ALPHAINV1 See AlphaInv0. [9:9] read-write ENLOCALPANIC1 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC1 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT1 Upper left corner of evaluation window 1. 0x30 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT1 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT1 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT1 Lower right corner of evaluation window 1. 0x34 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT1 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT1 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF1 Reference signature of red channel for evaluation window 1. 0x38 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF1 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF1 Reference signature of green channel for evaluation window 1. 0x3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF1 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF1 Reference signature of blue channel for evaluation window 1. 0x40 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF1 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED1 Measured signature of red channel for evaluation window 1. 0x44 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED1 See SigCRCRed0. [31:0] read-only SIGCRCGREEN1 Measured signature of green channel for evaluation window 1. 0x48 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN1 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE1 Measured signature of blue channel for evaluation window 1. 0x4C 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE1 See SigCRCBlue0. [31:0] read-only EVALCONTROL2 Control settings for evaluation window 2. 0x50 32 read-write 0x0 0x30303 ENEVALWIN2 See EnEvalWin0. [0:0] read-write ENCRC2 See EnCRC0. [1:1] read-write ALPHAMASK2 See AlphaMask0. [8:8] read-write ALPHAINV2 See AlphaInv0. [9:9] read-write ENLOCALPANIC2 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC2 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT2 Upper left corner of evaluation window 2. 0x54 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT2 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT2 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT2 Lower right corner of evaluation window 2. 0x58 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT2 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT2 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF2 Reference signature of red channel for evaluation window 2. 0x5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF2 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF2 Reference signature of green channel for evaluation window 2. 0x60 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF2 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF2 Reference signature of blue channel for evaluation window 2. 0x64 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF2 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED2 Measured signature of red channel for evaluation window 2. 0x68 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED2 See SigCRCRed0. [31:0] read-only SIGCRCGREEN2 Measured signature of green channel for evaluation window 2. 0x6C 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN2 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE2 Measured signature of blue channel for evaluation window 2. 0x70 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE2 See SigCRCBlue0. [31:0] read-only EVALCONTROL3 Control settings for evaluation window 3. 0x74 32 read-write 0x0 0x30303 ENEVALWIN3 See EnEvalWin0. [0:0] read-write ENCRC3 See EnCRC0. [1:1] read-write ALPHAMASK3 See AlphaMask0. [8:8] read-write ALPHAINV3 See AlphaInv0. [9:9] read-write ENLOCALPANIC3 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC3 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT3 Upper left corner of evaluation window 3. 0x78 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT3 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT3 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT3 Lower right corner of evaluation window 3. 0x7C 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT3 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT3 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF3 Reference signature of red channel for evaluation window 3. 0x80 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF3 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF3 Reference signature of green channel for evaluation window 3. 0x84 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF3 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF3 Reference signature of blue channel for evaluation window 3. 0x88 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF3 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED3 Measured signature of red channel for evaluation window 3. 0x8C 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED3 See SigCRCRed0. [31:0] read-only SIGCRCGREEN3 Measured signature of green channel for evaluation window 3. 0x90 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN3 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE3 Measured signature of blue channel for evaluation window 3. 0x94 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE3 See SigCRCBlue0. [31:0] read-only EVALCONTROL4 Control settings for evaluation window 4. 0x98 32 read-write 0x0 0x30303 ENEVALWIN4 See EnEvalWin0. [0:0] read-write ENCRC4 See EnCRC0. [1:1] read-write ALPHAMASK4 See AlphaMask0. [8:8] read-write ALPHAINV4 See AlphaInv0. [9:9] read-write ENLOCALPANIC4 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC4 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT4 Upper left corner of evaluation window 4. 0x9C 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT4 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT4 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT4 Lower right corner of evaluation window 4. 0xA0 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT4 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT4 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF4 Reference signature of red channel for evaluation window 4. 0xA4 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF4 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF4 Reference signature of green channel for evaluation window 4. 0xA8 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF4 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF4 Reference signature of blue channel for evaluation window 4. 0xAC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF4 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED4 Measured signature of red channel for evaluation window 4. 0xB0 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED4 See SigCRCRed0. [31:0] read-only SIGCRCGREEN4 Measured signature of green channel for evaluation window 4. 0xB4 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN4 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE4 Measured signature of blue channel for evaluation window 4. 0xB8 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE4 See SigCRCBlue0. [31:0] read-only EVALCONTROL5 Control settings for evaluation window 5. 0xBC 32 read-write 0x0 0x30303 ENEVALWIN5 See EnEvalWin0. [0:0] read-write ENCRC5 See EnCRC0. [1:1] read-write ALPHAMASK5 See AlphaMask0. [8:8] read-write ALPHAINV5 See AlphaInv0. [9:9] read-write ENLOCALPANIC5 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC5 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT5 Upper left corner of evaluation window 5. 0xC0 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT5 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT5 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT5 Lower right corner of evaluation window 5. 0xC4 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT5 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT5 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF5 Reference signature of red channel for evaluation window 5. 0xC8 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF5 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF5 Reference signature of green channel for evaluation window 5. 0xCC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF5 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF5 Reference signature of blue channel for evaluation window 5. 0xD0 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF5 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED5 Measured signature of red channel for evaluation window 5. 0xD4 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED5 See SigCRCRed0. [31:0] read-only SIGCRCGREEN5 Measured signature of green channel for evaluation window 5. 0xD8 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN5 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE5 Measured signature of blue channel for evaluation window 5. 0xDC 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE5 See SigCRCBlue0. [31:0] read-only EVALCONTROL6 Control settings for evaluation window 6. 0xE0 32 read-write 0x0 0x30303 ENEVALWIN6 See EnEvalWin0. [0:0] read-write ENCRC6 See EnCRC0. [1:1] read-write ALPHAMASK6 See AlphaMask0. [8:8] read-write ALPHAINV6 See AlphaInv0. [9:9] read-write ENLOCALPANIC6 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC6 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT6 Upper left corner of evaluation window 6. 0xE4 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT6 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT6 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT6 Lower right corner of evaluation window 6. 0xE8 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT6 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT6 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF6 Reference signature of red channel for evaluation window 6. 0xEC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF6 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF6 Reference signature of green channel for evaluation window 6. 0xF0 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF6 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF6 Reference signature of blue channel for evaluation window 6. 0xF4 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF6 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED6 Measured signature of red channel for evaluation window 6. 0xF8 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED6 See SigCRCRed0. [31:0] read-only SIGCRCGREEN6 Measured signature of green channel for evaluation window 6. 0xFC 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN6 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE6 Measured signature of blue channel for evaluation window 6. 0x100 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE6 See SigCRCBlue0. [31:0] read-only EVALCONTROL7 Control settings for evaluation window 7. 0x104 32 read-write 0x0 0x30303 ENEVALWIN7 See EnEvalWin0. [0:0] read-write ENCRC7 See EnCRC0. [1:1] read-write ALPHAMASK7 See AlphaMask0. [8:8] read-write ALPHAINV7 See AlphaInv0. [9:9] read-write ENLOCALPANIC7 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC7 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT7 Upper left corner of evaluation window 7. 0x108 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT7 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT7 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT7 Lower right corner of evaluation window 7. 0x10C 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT7 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT7 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF7 Reference signature of red channel for evaluation window 7. 0x110 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF7 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF7 Reference signature of green channel for evaluation window 7. 0x114 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF7 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF7 Reference signature of blue channel for evaluation window 7. 0x118 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF7 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED7 Measured signature of red channel for evaluation window 7. 0x11C 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED7 See SigCRCRed0. [31:0] read-only SIGCRCGREEN7 Measured signature of green channel for evaluation window 7. 0x120 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN7 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE7 Measured signature of blue channel for evaluation window 7. 0x124 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE7 See SigCRCBlue0. [31:0] read-only SHADOWLOAD Shadow load control register. 0x128 32 read-write 0x0 0xFF SHDLDREQ Shadow load request for each evaluation window (bit index = window index). Writing a '1' to a bit will load the shadows into the active configuration for that window at start of next frame. Writing a '0' has no effect. The flag is reset by HW once the shadows have been loaded. A shadow load interrupt signal is generated when shadows have been loaded for at least one evaluation window. Has only effect when ShdLdSel is set to LOCAL. [7:0] read-write CONTINUOUSMODE Signature operation mode control. 0x12C 32 read-write 0x0 0x1 ENCONT EnCont = 0: disables continuous mode. Signatures will be generated only once and in idle state after completion of measurement. In this 'ONE_TIME' mode the signature must be triggered by 'Kick' field. EnCont = 1: enables continuous mode. Write '1' to this field, signature starts and measures every incoming frame until EnCont is turned to 0. 'Kick' has no effect when 'EnCont' = 1. [0:0] read-write SOFTWAREKICK Signature measurement trigger. 0x130 32 write-only 0x0 0x0 KICK ContinueMode.EnCont=0: Write '1' to this field in order to start signature computation with next frame. ContinueMode.EnCont=1: This field is ignored. [0:0] write-only STATUS Module status. 0x134 32 read-only 0x100000 0x1100FF STSSIGERROR Error status bits for all evaluation windows (bit index = window index). When a bit is set it means that measured signature value is different from reference value (SigCRCRef). The bit is set when EnCRC is active and a certain number of frames have a violation (ErrThres). It is reset when the reference check for evaluation window is disabled (EnEvalWin or EnCRC) or in case a certain number of consecutive frames have no violation (ErrThresReset). The value corresponds to the panic status of this evaluation window. [7:0] read-only STSSIGVALID Measured signature values are valid. This flag is set when the SigCRC fields have been updated for all enabled evaluation windows. In that case also the corresponding interrupt event is triggered. It is reset when SW writes a '1' to the 'Kick' field in order to start a new measurement. [16:16] read-only STSSIGIDLE StsSigIdle = 1: Signature is in Idle state. StsSigIdle = 0: Signature runs. [20:20] read-only FRAMEGEN0 Frame Generator 0x00002000 FGSTCTRL FrameGen Static Control Register 0x0 32 read-write 0x0 0x7 SHDEN Enables shadowing for RWS type configuration fields. Otherwise shadow registers are immediately updated when written. [0:0] read-write FGSYNCMODE Determines the operating mode of the framegen unit for side-by-side synchronization. The framegen unit programmed as master generates synchronization pulses. The framegen units programmed as slaves are synchronized to the master unit. There must be only one framegen unit programmed acting as master. [2:1] read-write OFF No side-by-side synchronization. 0 MASTER Framegen is master. 1 SLAVE_CYC Framegen is slave. Runs in cyclic synchronization mode. 2 SLAVE_ONCE Framegen is slave. Runs in one time synchronization mode. 3 HTCFG1 FrameGen Horizontal Timing Config Register 1 0x4 32 read-write 0x18F0140 0x3FFF3FFF HACT Horizontal size of active display area in pixels. Hact shall be greater or equal than 4. Note: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync. [13:0] read-write HTOTAL Total horizontal size of frame in pixels. (Set value +1 is the total horizontal size of frame) Htotal shall be greater or equal than Hact + Hsbp. Note1: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync. Note2: If SRAdj==1 then Htotal[0] shall be equal the value of SREven (for sec. channel only). [29:16] read-write HTCFG2 FrameGen Horizontal Timing Config Register 2 0x8 32 read-write 0x8047001F 0xBFFF3FFF HSYNC Width of HSYNC pulse in pixels. (Set value +1 is the width of HSYNC pulse) HSYNC is of zero width if HsEn==0. Note: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync. [13:0] read-write HSBP Width of HSYNC pulse plus width of horizontal back porch in pixels. (Set value +1 is the width of HSYNC pulse plus width of horizontal back porch) Hsbp shall be greater or equal than Hsync. Note: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync. [29:16] read-write HSEN Enables generation of HSYNC pulse. [31:31] read-write VTCFG1 FrameGen Vertical Timing Config Register 1 0xC 32 read-write 0xFC00F0 0x3FFF3FFF VACT Vertical size of active display area in lines. Vact shall be greater or equal than 4. Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync. [13:0] read-write VTOTAL Total vertical size of frame in lines. (Set value +1 is the total vertical size of frame) Vtotal shall be greater or equal than Vact + Vsbp. Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync. [29:16] read-write VTCFG2 FrameGen Vertical Timing Config Register 2 0x10 32 read-write 0x80090003 0xBFFF3FFF VSYNC Width of VSYNC pulse in lines. (Set value +1 is the width of VSYNC pulse) VSYNC is of zero width if VsEn==0. Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync. [13:0] read-write VSBP Width of VSYNC pulse plus width of vertical back porch in lines. (Set value +1 is the width of VSYNC pulse plus width of vertical back porch) Vsbp shall be greater or equal than Vsync. Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync. [29:16] read-write VSEN Enables generation of VSYNC pulse. [31:31] read-write INT0CONFIG Coordinates of the trigger point for generation of the Int0 interrupt signal 0x14 32 read-write 0x0 0xBFFFBFFF INT0COL Specifies on which column of the display raster the Int0 signal is triggered (1 .. Int0Col .. HTOTAL). Adaptive display timing must be taken into account when defining Int0Col (1 .. Int0Col .. HTOTAL_MIN). [13:0] read-write INT0HSEN When enabled, Int0Row setting is ignored so that the interrupt occurs every line at position given by Int0Col. [15:15] read-write INT0ROW Specifies on which row of the display raster the Int0 signal is triggered (1 .. Int0Row .. VTOTAL). Adaptive display timing must be taken into account when defining Int0Row (1 .. Int0Row .. VTOTAL_MIN). [29:16] read-write INT0EN Enables Int0. [31:31] read-write INT1CONFIG Coordinates of the trigger point for generation of the Int1 interrupt signal 0x18 32 read-write 0x0 0xBFFFBFFF INT1COL Specifies on which column of the display raster the Int1 signal is triggered (1 .. Int1Col .. HTOTAL). Adaptive display timing must be taken into account when defining Int1Col (1 .. Int1Col .. HTOTAL_MIN). [13:0] read-write INT1HSEN When enabled, Int1Row setting is ignored so that the interrupt occurs every line at position given by Int1Col. [15:15] read-write INT1ROW Specifies on which row of the display raster the Int1 signal is triggered (1 .. Int1Row .. VTOTAL). Adaptive display timing must be taken into account when defining Int1Row (1 .. Int1Row .. VTOTAL_MIN). [29:16] read-write INT1EN Enables Int1 (irq[1]). [31:31] read-write INT2CONFIG Coordinates of the trigger point for generation of the Int2 interrupt signal 0x1C 32 read-write 0x0 0xBFFFBFFF INT2COL Specifies on which column of the display raster the Int2 signal is triggered (1 .. Int2Col .. HTOTAL). Adaptive display timing must be taken into account when defining Int2Col (1 .. Int2Col .. HTOTAL_MIN). [13:0] read-write INT2HSEN When enabled, Int2Row setting is ignored so that the interrupt occurs every line at position given by Int2Col. [15:15] read-write INT2ROW Specifies on which row of the display raster the Int2 signal is triggered (1 .. Int2Row .. VTOTAL). Adaptive display timing must be taken into account when defining Int2Row (1 .. Int2Row .. VTOTAL_MIN). [29:16] read-write INT2EN Enables Int2. [31:31] read-write INT3CONFIG Coordinates of the trigger point for generation of the Int3 interrupt signal 0x20 32 read-write 0x0 0xBFFFBFFF INT3COL Specifies on which column of the display raster the Int3 signal is triggered (1 .. Int3Col .. HTOTAL). Adaptive display timing must be taken into account when defining Int3Col (1 .. Int3Col .. HTOTAL_MIN). [13:0] read-write INT3HSEN When enabled, Int3Row setting is ignored so that the interrupt occurs every line at position given by Int3Col. [15:15] read-write INT3ROW Specifies on which row of the display raster the Int3 signal is triggered (1 .. Int3Row .. VTOTAL). Adaptive display timing must be taken into account when defining Int3Row (1 .. Int3Row .. VTOTAL_MIN). [29:16] read-write INT3EN Enables Int3. [31:31] read-write PKICKCONFIG Coordinates of the trigger point for generation of the primary kick signal 0x24 32 read-write 0xF00140 0xBFFFBFFF PKICKCOL Specifies on which column of the display raster the pkick signal is triggered (1 .. PKickCol .. HTOTAL). Adaptive display timing must be taken into account when defining PKickCol (1 .. PKickCol .. HTOTAL_MIN). [13:0] read-write PKICKINT0EN If enabled, maps the primary kick signal (pkick) on the interrupt pin int0. Overrides int0en. [15:15] read-write PKICKROW Specifies on which row of the display raster the pkick signal is triggered (1 .. PKickRow .. VTOTAL). Adaptive display timing must be taken into account when defining PKickRow (1 .. PKickRow .. VTOTAL_MIN). [29:16] read-write PKICKEN Enables pkick signal. [31:31] read-write SKICKCONFIG Coordinates of the trigger point for generation of the secondary kick signal 0x28 32 read-write 0xF00140 0xFFFFBFFF SKICKCOL Specifies on which column of the display raster the skick signal is triggered (1 .. SKickCol .. HTOTAL). Adaptive display timing must be taken into account when defining SKickCol (1 .. SKickCol .. HTOTAL_MIN). [13:0] read-write SKICKINT1EN If enabled, maps the secondary kick signal (skick) on the interrupt pin int1. Overrides int1en. [15:15] read-write SKICKROW Specifies on which row of the display raster the skick signal is triggered (1 .. SKickRow .. VTOTAL). Adaptive display timing must be taken into account when defining SKickRow (1 .. SKickRow .. VTOTAL_MIN). [29:16] read-write SKICKTRIG Select source for skick generation. [30:30] read-write INTERNAL Use internal skick signal, trigger point defined by SKickRow and SKickCol. 0 EXTERNAL Use external skick input as trigger. 1 SKICKEN Enables generation of internal skick signal. [31:31] read-write SECSTATCONFIG Configuration register for controlling the behavior of the SecSyncStat field in the FgSecChStat register. 0x2C 32 read-write 0x112 0xFFF LEVGOODFRAMES Number of continuous correct frames that must be processed before SecSyncStat field goes 1 (in sync). Value of 0 is not allowed. [3:0] read-write LEVBADFRAMES Not used. [7:4] read-write LEVSKEWINRANGE Number of continuous frames the measured skew value shall be within the range defined by SyncRangeLow and SyncRangeHigh. If this condition is true, additionally LevGoodFrames valid frames must be processed before the status line of the sec. channel and the SecSyncStat status field goes to 1 indicating synchronized status. Value of 0 is not allowed. [11:8] read-write FGSRCR1 FrameGen Skew Regulation Control Register 1. 0x30 32 read-write 0x0 0x301FF SREN If enabled, skew control for secondary channel is active. If disabled, skew control for secondary channel is in fetch mode. Fetch mode: secondary channel fetches frames and can intentionally produce a backstall via setting sbusy signal to active. This mode is intended to fetch frames from memory via a stallable pipeline, like the primary interface. No timing adaption of frames takes place in this mode. [0:0] read-write SRMODE Skew Control Operating Mode. [2:1] read-write OFF Skew Regulation is off. 0 HREG Horizontal regulation enabled. 1 VREG Vertical regulation enabled. 2 BOTH Both regulation modes are enabled. 3 SRADJ Enables line length adjustment for HTOTAL. If SRQAlign=0, SREven determines whether HTOTAL has odd (SREven=0) or even (SrEven=1) number of pixels. If SRQAlign=1, SRQVal determines the value of the two LSB bits of HTOTAL. [3:3] read-write SREVEN Total line length HTOTAL is even when SRAdj is enabled. Note: This has impact on the settings for Htotal, HtotalMin and HtotalMax. [4:4] read-write SRFASTSYNC Fast Synchronization Mode. Frame Generator is started synchronized to frame timing on secondary channel when switching FgEn from 0 to 1. This allows fast locking of skew regulation. [5:5] read-write SRQALIGN Enables alignment of HTOTAL to be a multiple of 4. Overrides SREven field. Program field SRQVal for the desired value of the two LSB bits of HTOTAL. [6:6] read-write SRQVAL If SRQAlign is enabled, this field determines the fixed value of the two LSB bits of HTOTAL. Note: This has impact on the settings for Htotal, HtotalMin and HtotalMax. [8:7] read-write ZERO Fixed two LSB values of HTOTAL are 0b00. 0 ONE Fixed two LSB values of HTOTAL are 0b01. 1 TWO Fixed two LSB values of HTOTAL are 0b10. 2 THREE Fixed two LSB values of HTOTAL are 0b11. 3 SRDBGDISP If enabled, the pixels are displayed that are read from FIFO when secondary channel is not in sync yet. Otherwise constant color is displayed in unsynchronized state. [16:16] read-write SREPOFF Disables the skew Extrapolation in blanking. [17:17] read-write FGSRCR2 FrameGen Skew Regulation Control Register 2 0x34 32 read-write 0x1B70188 0x3FFF3FFF HTOTALMIN Minimum value of htotal when horizontal regulation is enabled. (Set value +1 is the minimum value of htotal, must be greater or equal Hsbp + Hactive) HTotalMin must be smaller or equal Htotal. Note: If SRAdj==1 then HtotalMin[0] shall be equal to the value of SREven. [13:0] read-write HTOTALMAX Maximum value of htotal when horizontal regulation is enabled. (Set value +1 is the maximum value of htotal) HTotalMax must be greater or equal Htotal. Note: If SRAdj==1 then HtotalMax[0] shall be equal to the value of SREven. [29:16] read-write FGSRCR3 FrameGen Skew Regulation Control Register 3 0x38 32 read-write 0x11500FB 0x3FFF3FFF VTOTALMIN Minimum value of vtotal when vertical regulation is enabled. (Set value +1 is the minimum value of vtotal, must be greater or equal Vsbp + Vactive + 1) [13:0] read-write VTOTALMAX Maximum value of vtotal when vertical regulation is enabled. (Set value +1 is the maximum value of vtotal) [29:16] read-write FGSRCR4 FrameGen Skew Regulation Control Register 4 0x3C 32 read-write 0xC8 0x1FFFFFFF TARGETSKEW Horizontal target skew value for horizontal and vertical skew regulation (signed value). (format is signed integer) [28:0] read-write FGSRCR5 FrameGen Skew Regulation Control Register 5 0x40 32 read-write 0x0 0x1FFFFFFF SYNCRANGELOW Sync range of horizontal and vertical skew regulation. Lower value (signed value). If skew stays within programmed sync range, frame status is assumed synchronized. (format is signed integer) [28:0] read-write FGSRCR6 FrameGen Skew Regulation Control Register 6 0x44 32 read-write 0x190 0x1FFFFFFF SYNCRANGEHIGH Sync range of horizontal and vertical skew regulation. Upper value (signed value). If skew stays within programmed sync range, frame status is assumed synchronized. (format is signed integer) [28:0] read-write FGKSDR FrameGen Kick System Debug Register 0x48 32 read-write 0x20002 0x70007 PCNTCPLMAX Maximum Value for ppendcnt_cpl_s complementary primary kick counter. Do not change! [2:0] read-write SCNTCPLMAX Maximum Value for spendcnt_cpl_s complementary secondary kick counter. Do not change! [18:16] read-write PACFG FrameGen Primary Area Config Register 1 (shadowed) 0x4C 32 read-write 0x10001 0x3FFF3FFF PSTARTX Primary screen upper left corner, x component. Counts from 1. Pstartx = 0 is not allowed. Primary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal. [13:0] read-write PSTARTY Primary screen upper left corner, y component. Counts from 1. Pstarty = 0 is not allowed. Primary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal. [29:16] read-write SACFG FrameGen Secondary Area Config Register 1 (shadowed) 0x50 32 read-write 0x10001 0x3FFF3FFF SSTARTX Secondary screen upper left corner, x component. Counts from 1 . Sstartx = 0 is not allowed. Secondary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal. When skew regulation feature is enabled, the secondary screen shall not overlap the active display area defined by Hact and Vact. [13:0] read-write SSTARTY Secondary screen upper left corner, y component. Counts from 1 . Sstarty = 0 is not allowed. Secondary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal. When skew regulation feature is enabled, the secondary screen shall not overlap the active display area defined by Hact and Vact. [29:16] read-write FGINCTRL FrameGen Input Control Register (shadowed) 0x54 32 read-write 0x6 0x1F FGDM Frame Generator Display Mode. [2:0] read-write BLACK Black color background is shown on the whole screen area. 0 CONSTCOL Programmable constant color is shown in the active area and black color in the blanking area. 1 PRIM Primary input only is shown. 2 SEC Secondary input only is shown. 3 PRIM_ON_TOP Both inputs overlaid with primary on top. 4 SEC_ON_TOP Both inputs overlaid with secondary on top. 5 TEST White color background with test pattern is shown in the active area and black color in the blanking area. 6 BLEND Blending of the mode PRIM with the mode SEC. 7 ENPRIMALPHA When enabled, alpha plane of primary channel is considered for screen composition. If the alpha component of the current pixel is 255, this pixel is opaque. Otherwise this pixel is transparent. Setting this field to 1 has no effect, when FgDm == BLEND. [3:3] read-write ENSECALPHA When enabled, alpha plane of secondary channel is considered for screen composition. If the alpha component of the current pixel is 255, this pixel is opaque. Otherwise this pixel is transparent. Setting this field to 1 has no effect, when FgDm == BLEND. [4:4] read-write FGINCTRLPANIC FrameGen Input Control Panic Register (shadowed) 0x58 32 read-write 0x6 0x1F FGDMPANIC Frame Generator Display Mode. [2:0] read-write BLACK Black color background is shown on the whole screen area. 0 CONSTCOL Programmable constant color is shown in the active area and black color in the blanking area. 1 PRIM Primary input only is shown. 2 SEC Secondary input only is shown. 3 PRIM_ON_TOP Both inputs overlaid with primary on top. 4 SEC_ON_TOP Both inputs overlaid with secondary on top. 5 TEST White color background with test pattern is shown in the active area and black color in the blanking area. 6 BLEND Blending of the mode PRIM with the mode SEC. 7 ENPRIMALPHAPANIC When enabled, alpha plane of primary channel is considered for screen composition. If the alpha component of the current pixel is 255, this pixel is opaque. Otherwise this pixel is transparent. Setting this field to 1 has no effect, when FgDmPanic == BLEND. [3:3] read-write ENSECALPHAPANIC When enabled, alpha plane of secondary channel is considered for screen composition. If the alpha component of the current pixel is 255, this pixel is opaque. Otherwise this pixel is transparent. Setting this field to 1 has no effect, when FgDmPanic == BLEND. [4:4] read-write FGCCR FrameGen Constant Color Register (shadowed) 0x5C 32 read-write 0x1FFFFFF 0x1FFFFFF CCBLUE Constant color - blue component. [7:0] read-write CCGREEN Constant color - green component. [15:8] read-write CCRED Constant color - red component. [23:16] read-write CCALPHA Constant color - alpha value. In case of blending the value of 1 will be extended to 0xff. [24:24] read-write BLENDCONTROL Options for blend operations. (shadowed) 0x60 32 read-write 0x1010 0xFF7777 PRIM_C_BLD_FUNC Primary (background) input color blending function [2:0] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 SEC_C_BLD_FUNC Secondary (overlay) input color blending function [6:4] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 PRIM_A_BLD_FUNC Primary (background) input alpha blending function [10:8] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 SEC_A_BLD_FUNC Secondary (overlay) input alpha blending function [14:12] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 BLENDALPHA Constant alpha value, used for constant alpha blending [23:16] read-write FGENABLE FrameGen Enable Register 0x64 32 read-write 0x0 0x1 FGEN Frame Generator Enable. Note: For loading the shadow registers at start-up of FrameGen unit write the FgSlr.ShdTokGen field immediately before writing this field. [0:0] read-write FGSLR FrameGen Shadow Load Register 0x68 32 write-only 0x0 0x0 SHDTOKGEN Generate shadow load token. Can be used to load shadow register in this and/or all subsequent units up to the next token end point. [0:0] write-only FGENSTS FrameGen Enable Status Register 0x6C 32 read-only 0x0 0x3 ENSTS Indicates the current operating mode of the frame generator. EnSts = 0 means frame generator is disabled. EnSts = 1 means frame generator is enabled. In contrast to the FgEn field of the FgEnable register this bit goes only 0 when all pending frames are processed. [0:0] read-only PANICSTAT Current status of panic mode (0=normal operation mode, 1=panic mode; not locked). [1:1] read-only FGTIMESTAMP Time stamp status. 0x70 32 read-only 0x0 0xFFFFFFFF LINEINDEX Index of the output line that is currently generated (starts with 0 for first active output line). [13:0] read-only FRAMEINDEX Index of the output frame that is currently generated (starts with 0 after reset for first output frame). Wraps around to 0 when maximum value is reached. [31:14] read-only FGCHSTAT FrameGen Channel Status Register 0x74 32 read-only 0x0 0x1030101 PFIFOEMPTY Read request to empty primary pixel FIFO detected. (Bit locked when 1, clear by using ClrPrimStat). [0:0] read-only PRIMSYNCSTAT Current status primary channel synchronization (0 = out of sync (frame tearing), 1 = in sync (normal operation); not locked). [8:8] read-only SFIFOEMPTY Read request to empty secondary pixel FIFO detected. (bit locked when 1, clear by using ClrSecStat). [16:16] read-only SKEWRANGEERR The secondary channel skew value has run out of the limit defined by SyncRangeLow and SyncRangeHigh. (bit locked when 1, clear by using ClrSecStat). [17:17] read-only SECSYNCSTAT Current status secondary channel synchronization (0 = out of sync, 1 = in sync; not locked). [24:24] read-only FGCHSTATCLR FrameGen Channel Status Clear Register 0x78 32 write-only 0x0 0x0 CLRPRIMSTAT Clears PFifoEmpty in FgChStat register. [0:0] write-only CLRSECSTAT Clears SFifoEmpty and SkewRangeErr in FgChStat register. [16:16] write-only FGSKEWMON FrameGen Skew Monitor Register for Secondary Channel Skew Control 0x7C 32 read-only 0x0 0x1FFFFFFF SKEWMON Current skew value monitor for secondary channel skew control. Updated with hlast. (For debugging purposes only). [28:0] read-only FGSFIFOMIN FrameGen Secondary FIFO Min Fill Register 0x80 32 read-only 0x0 0x0 SFIFOMIN Shows the minimal fill level of the secondary channel pixel FIFO. (For debugging purposes only). [10:0] read-only FGSFIFOMAX FrameGen Secondary FIFO Max Fill Register 0x84 32 read-only 0x0 0x0 SFIFOMAX Shows the maximal fill level of the secondary channel pixel FIFO. (For debugging purposes only). [10:0] read-only FGSFIFOFILLCLR FrameGen Secondary FIFO Fill Clear Register 0x88 32 write-only 0x0 0x0 SFIFOFILLCLR Write for clearing register FgSFifoMin and FgSFifoMax. (For debugging purposes only). [0:0] write-only FGSREPD FrameGen Skew Regulation ExtraPolation Debug Register 0x8C 32 read-only 0x0 0x1FFFFFFF EPVAL Calculated value for line skew extrapolation in blanking. Updated with condition 'hlast AND vlast'. (For debugging purposes only) [28:0] read-only FGSRFTD FrameGen Skew Regulation Frame Total Debug Register 0x90 32 read-only 0x0 0xFFFFFFF FRTOT Measured value for frame total measured in display clock cycles. Updated with condition 'hlast AND vlast' when first FrTot value is valid. (For debugging purposes only) [27:0] read-only FGTGPOSITION Current (x,y) positions of the timing generator register in FrameGen timing generator. 0x94 32 read-only 0x3F0000 0xFFFFFFF FRTGX Coordinated pixel position starting from HACT inside a total line generated in timing generator in display clock cycles. (For debugging purposes only) [13:0] read-only FRTGY Coordinated line position starting from VACT inside a total frame generated in timing generator in display clock cycles. (For debugging purposes only) [27:14] read-only GAMMACOR0 Gamma Correction Unit 0x00002400 STATICCONTROL Static control settings. 0x0 32 read-write 0xE 0xF SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write BLUEWRITEENABLE Write enable for the blue color sampling point entries. [1:1] read-write GREENWRITEENABLE Write enable for the green color sampling point entries. [2:2] read-write REDWRITEENABLE Write enable for the red color sampling point entries. [3:3] read-write LUTSTART Start values for look-up table programming. 0x4 32 write-only 0x0 0x3FFFFFFF STARTBLUE Start value for blue or chroma (V) channel. (format is unsigned integer) [9:0] write-only STARTGREEN Start value for green or chroma (U) channel. (format is unsigned integer) [19:10] write-only STARTRED Start value for red or luma (Y) channel. (format is unsigned integer) [29:20] write-only LUTDELTAS Delta values for look-up table programming. 0x8 32 write-only 0x0 0x0 DELTABLUE Delta value for blue or chroma (V) channel. (format is signed integer) [9:0] write-only DELTAGREEN Delta value for green or chroma (U) channel. (format is signed integer) [19:10] write-only DELTARED Delta value for red or luma (Y) channel. (format is signed integer) [29:20] write-only CONTROL Dynamic control settings. 0xC 32 read-write 0x0 0x31 MODE Operation mode for gamma correction unit [0:0] read-write NEUTRAL Module in neutral mode, input data is bypassed to the output. 0 GAMMACOR Module in gamma correction mode. 1 ALPHAMASK Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value smaller than 0.5 are by-passed unchanged. [4:4] read-write ALPHAINVERT Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha value greater or equal 0.5 are by-passed). [5:5] read-write DITHER0 Dither Unit 0x00002800 CONTROL Dither Unit common control. 0x0 32 read-write 0x0 0x1 MODE Mode which switches Dither Unit on/off. (format is unsigned integer) [0:0] read-write NEUTRAL Neutral mode. Pixels by-pass the Dither Unit, all other settings are ignored. 0 ACTIVE Dither Unit is active. 1 DITHERCONTROL Dither Unit processing control. 0x4 32 read-write 0x300222 0x3310777 BLUE_RANGE_SELECT Mode which sets the reduction of component widths. (format is unsigned integer) [2:0] read-write BLUE_10TO8 Reduces blue component width from 10 bit to 8bit. 2 BLUE_10TO7 Reduces blue component width from 10 bit to 7bit. 3 BLUE_10TO6 Reduces blue component width from 10 bit to 6bit. 4 BLUE_10TO5 Reduces blue component width from 10 bit to 5bit. 5 GREEN_RANGE_SELECT Mode which sets the reduction of component widths. (format is unsigned integer) [6:4] read-write GREEN_10TO8 Reduces green component width from 10 bit to 8bit. 2 GREEN_10TO7 Reduces green component width from 10 bit to 7bit. 3 GREEN_10TO6 Reduces green component width from 10 bit to 6bit. 4 GREEN_10TO5 Reduces green component width from 10 bit to 5bit. 5 RED_RANGE_SELECT Mode which sets the reduction of component widths. (format is unsigned integer) [10:8] read-write RED_10TO8 Reduces red component width from 10 bit to 8bit. 2 RED_10TO7 Reduces red component width from 10 bit to 7bit. 3 RED_10TO6 Reduces red component width from 10 bit to 6bit. 4 RED_10TO5 Reduces red component width from 10 bit to 5bit. 5 OFFSET_SELECT Selects the method how the dither offset is calculated. (format is unsigned integer) [16:16] read-write OFFS_SPATIAL Offset is a bayer matrix value, which is selected according to pixel frame position. 0 OFFS_TEMPORAL Offset is the sum from a bayer matrix value, which is selected according to pixel frame position, and a value from a regular sequence, which changes each frame. 1 ALGO_SELECT The number of output colors that can virtually be displayed by dithering is slightly lower than the number of physical input colors. This field selects how the mapping is done. (format is unsigned integer) [21:20] read-write NO_CORRECTION Best possible resolution for most dark colors. Adds a diminutive offset to overall image brightness. 1 BRIGHTNESS_CORRECTION Preserves overall image brightness. Cannot resolve most dark and most bright colors. All codes in-between are distributed perfectly smooth. 2 CONTRAST_CORRECTION Preserves overall image brightness. Best possible distribution of color codes over complete range. 3 ALPHA_MODE Enables/disables that dithering can be switched by alpha bit. (format is unsigned integer) [25:24] read-write DISABLE The alpha bit is not considered. 0 ENABLE_BY1 Red, green and blue components are only dithered, if the alpha bit is 1. 1 ENABLE_BY0 Red, green and blue components are only dithered, if the alpha bit is 0. 2 RELEASE Dither Unit release. 0x8 32 read-only 0x1 0xFFFF SUBVERSION Dither Unit subversion. (format is unsigned integer) [7:0] read-only VERSION Dither Unit version. (format is unsigned integer) [15:8] read-only TCON0 Timing Controller 0x00003000 64 4 SSQCNTS[%s] The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field 0x0 32 read-write 0x0 0x0 SSQCNTS_SEQY Y scan position [14:0] read-write SSQCNTS_FIELD Field 0b=odd field, 1b=even field [15:15] read-write SSQCNTS_SEQX X scan position [30:16] read-write SSQCNTS_OUT This bit holds the value (0,1) to be output when the X/Y scan position is reached. [31:31] read-write SSQCYCLE This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles 0x400 32 read-write 0x0 0x3F SSQCYCLE Sequencer cycle length (number -1) of sequencer cycles [5:0] read-write SWRESET TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document Note 1/ if tsig[11] pulse=n*pixel_period, (n-1)*0xFF will be blended between ResetWordStart and ResetWordEnd into miniLVDS stream Note 2/ if( EnResetWord=0) Reset-Pulse (ResetWordStart,ResetWordEnd) won't be blended into miniLVDS stream. Pixels will be transferred unchanged 0x404 32 read-write 0x3FC00410 0xFFFFFFF1 SWRESET Software reset [0:0] read-write OPERATION operation mode 0 SWRESET So long SWReset = 0x1 tcon is in 'SW reset state' and it is released by internal logic (SWReset is released and end of frame arrived), read 0b reset not active 1b reset active (that means NO pixel of video frame is excepted until 'SW reset state' is released) 1 ENRESETWORD Enable to blend ResetWord into miniLVDS stream EnResetWord[5-0] mapped to enable Blending Reset Pulse to [RLV5.RLV0]. EnResetWord[11-6] mapped to enable Blending Reset Pulse to [LLV5.LLV0]. [15:4] read-write RESETWORDEND 8-Bits value, that will be blended on falling edge of tsig[11] into miniLVDS stream [23:16] read-write RESETWORDSTART 8-Bits value, that will be blended on rising edge of tsig[11] into miniLVDS stream [31:24] read-write TCON_CTRL TCON Control register 0x408 32 read-write 0x1401408 0x3FFFFFFF CHANNELMODE Selects one of tcon operation modes, SINGLE, DUAL_INTERLEAVED or DUAL_SPLIT. If MiniLVDS operation is selected (EnLVDS = ENABLE_LVDS and LVDSMode = Mini_LVDS), tcon operates in MiniLVDS mode, independent of ChannelMode programming. SplitPosition must be specified in MiniLVDS operation in DUAL_INTERLEAVED or DUAL_SPLIT mode, the horizontal parameter of signal generator have to set twice as they are specified in the panel-specification (panel 320, tsig_start 0, tsig_stop 320 on DUAL-Mode tsig_start 0, tsig_stop 640 ... (SplitPosition is automatically adjusted) ) [1:0] read-write SINGLE Single pixel mode. Both channels channel are active at full pixel clock. If bitmap of both panels are the same, both panels are identical 0 DUAL_INTERLEAVED Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives display columns with even and 2nd one with odd index. 1 DUAL_SPLIT Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives the left and 2nd one the right half of the display. Note data_en is needed in this mode 2 TCON_SYNC Select synchronization between hsync/vsync and hlast/vlast [2:2] read-write H_VLAST tcon timing generator synchronized to hlast, vlast 0 H_VSYNC tcon timing generator synchronized to hsync, vsync where horizontal synchronization is synchronized at the falling edge of hsync 1 BYPASS Bypassing synchronization [3:3] read-write TCON_MODE tcon operation mode 0 BYPASS_MODE tcon in Bypass mode. input pixel and its sync-signals are bypassed to tcon-output 1 INV_CTRL Minimize the toggle rate of tcon output for display panel, that supports data inversion control. Otherwise set Inv_Ctrl = 0. Valid for all channels . Inv_Ctrl does not effect any function on LVDS-Output. [7:4] read-write DISABLE Disable inversion control 0 RGB_2_BITS Enable inversion control for number of RGB-Bits = 2 1 RGB_4_BITS Enable inversion control for number of RGB-Bits = 4 2 RGB_6_BITS Enable inversion control for number of RGB-Bits = 6 3 RGB_8_BITS Enable inversion control for number of RGB-Bits = 8 4 RGB_10_BITS Enable inversion control for number of RGB-Bits = 10 5 RGB_12_BITS Enable inversion control for number of RGB-Bits = 12 6 RGB_14_BITS Enable inversion control for number of RGB-Bits = 14 7 RGB_16_BITS Enable inversion control for number of RGB-Bits = 16 8 RGB_18_BITS Enable inversion control for number of RGB-Bits = 18 9 RGB_20_BITS Enable inversion control for number of RGB-Bits = 20 10 RGB_22_BITS Enable inversion control for number of RGB-Bits = 22 11 RGB_24_BITS Enable inversion control for number of RGB-Bits = 24 12 RSVD1 N/A 13 RSVD2 N/A 14 RSVD3 N/A 15 ENLVDS Enable LVDS Mode [8:8] read-write ENABLE_LVDS Enable LVDS , TTL and RSDS are disable 1 DISABLE_LVDS Disable LVDS, Enable TTL and RSDS 0 LVDSMODE Selection the LVDS Mode if EnLVDS = ENABLE_LVDS [9:9] read-write MINI_LVDS MiniLVDS 1 LVDS LVDS Mode, refer to OpenLDI 0 LVDS_BALANCE Operation mode of LVDS-OpenLDI [10:10] read-write BALANCED LVDS operates in 24 bits Balanced Mode 1 UNBALANCED LVDS operates in 24 bits Unbalanced Mode 0 LVDS_CLOCK_INV Inversion the polarity of lvds clock in OpenLDI Mode [11:11] read-write INV Invert LVDS Clock 1 NON_INV NON-Invert LVDS Clock 0 MINILVDS_OPCODE Operation mode of MiniLVDS [14:12] read-write MODE_3PAIRS MiniLVDS operates in 6 and 8 bit data, three pairs 0 MODE_4PAIRS Not Implemented 1 MODE_5PAIRS Not Implemented 2 MODE_6PAIRS MiniLVDS operates in 6 and 8 bit data, six pairs 3 RSVD1 N/A 4 RSVD2 N/A 5 RSVD3 N/A 6 RSVD4 N/A 7 DUAL_SWAP pixels of lower/upper channel can be swapped if tcon operates in DUAL-mode (include LVDS/miniLVDS) no effect in SINGLE-mode [15:15] read-write SWAP swapping pixels between lower-channel and upper-channel 1 NON_SWAP NON-swapping pixels between lower-channel and upper-channel 0 SPLITPOSITION Index of first column of right display half when ChannelMode is DUAL_SPLIT. SplitPosition and (Hact - SplitPosition) must be less or equal than max supported active frame width. If SplitPosition is greater than (Hact - SplitPosition), then Htotal must be greater than 2*SplitPosition; else Htotal must be greater than (Hact - SplitPosition). Once setting a SplitPosition, data_en is needed. The SplitPosition must be even. [29:16] read-write RSDSINVCTRL Controls inversion of output polarity when connected IO cells operate in RSDS mode 0x40C 32 read-write 0x0 0xFFF0FFF RSDS_INV Inversion vector for 1st channel. For i in [ 0 .. 11 ]; if RSDS_Inv [ i ] == 0 => NON-Inversion of RSDS [ i ] else Inversion of RSDS [ i ] [11:0] read-write RSDS_INV_DUAL Same as RSDS_inv for 2nd channel [27:16] read-write MAPBIT3_0 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 0 .. 3 0x410 32 read-write 0x3020100 0x1F1F1F1F MAPBIT0 map bit[ 0 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit0 in [ 23..0 ] => bit[ 0 ] = [ Blue, Green, Red ] [ MapBit0 ]; if MapBit0 in [29 .. 24] => bit[ 0 ] in { TSig[5] .. TSig[0] }; If MapBit0 = 31 => bit[ 0 ] = 0 ; if MapBit1= 30 => bit[ 0 ] = 1 [4:0] read-write MAPBIT1 map bit[ 1 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit1 in [ 23..0 ] => bit[ 1 ] = [ Blue, Green, Red ] [ MapBit1 ]; if MapBit1 in [29 .. 24] => bit[ 1 ] in { TSig[5] .. TSig[0] }; If MapBit1 = 31 => bit[ 1 ] = 0 ; if MapBit1= 30 => bit[ 1 ] = 1 [12:8] read-write MAPBIT2 map bit[ 2 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit2 in [ 23..0 ] => bit[ 2 ] = [ Blue, Green, Red ] [ MapBit2 ]; if MapBit2 in [29 .. 24] => bit[ 2 ] in { TSig[5] .. TSig[0] }; If MapBit2 = 31 => bit[ 2 ] = 0 ; if MapBit2= 30 => bit[ 2 ] = 1 [20:16] read-write MAPBIT3 map bit[ 3 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit3 in [ 23..0 ] => bit[ 3 ] = [ Blue, Green, Red ] [ MapBit3 ]; if MapBit3 in [29 .. 24] => bit[ 3 ] in { TSig[5] .. TSig[0] }; If MapBit3 = 31 => bit[ 3 ] = 0 ; if MapBit3= 30 => bit[ 3 ] = 1 [28:24] read-write MAPBIT7_4 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 4 .. 7 0x414 32 read-write 0x7060504 0x1F1F1F1F MAPBIT4 map bit[ 4 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit4 in [ 23..0 ] => bit[ 4 ] = [ Blue, Green, Red ] [ MapBit4 ]; if MapBit4 in [29 .. 24] => bit[ 4 ] in { TSig[5] .. TSig[0] }; If MapBit4 = 31 => bit[ 4 ] = 0 ; if MapBit4= 30 => bit[ 4 ] = 1 [4:0] read-write MAPBIT5 map bit[ 5 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit5 in [ 23..0 ] => bit[ 5 ] = [ Blue, Green, Red ] [ MapBit5 ]; if MapBit5 in [29 .. 24] => bit[ 5 ] in { TSig[5] .. TSig[0] }; If MapBit5 = 31 => bit[ 5 ] = 0 ; if MapBit5= 30 => bit[ 5 ] = 1 [12:8] read-write MAPBIT6 map bit[ 6 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit6 in [ 23..0 ] => bit[ 6 ] = [ Blue, Green, Red ] [ MapBit6 ]; if MapBit6 in [29 .. 24] => bit[ 6 ] in { TSig[5] .. TSig[0] }; If MapBit6 = 31 => bit[ 6 ] = 0 ; if MapBit6= 30 => bit[ 6 ] = 1 [20:16] read-write MAPBIT7 map bit[ 7 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit7 in [ 23..0 ] => bit[ 7 ] = [ Blue, Green, Red ] [ MapBit7 ]; if MapBit7 in [29 .. 24] => bit[ 7 ] in { TSig[5] .. TSig[0] }; If MapBit7 = 31 => bit[ 7 ] = 0 ; if MapBit7= 30 => bit[ 7 ] = 1 [28:24] read-write MAPBIT11_8 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 8 .. 11 0x418 32 read-write 0xB0A0908 0x1F1F1F1F MAPBIT8 map bit[ 8 ] from [ Blue, Green, Red ] or from TSig[5-0]. if MapBit8 in [ 23..0 ] => bit[ 8 ] = [ Blue, Green, Red ] [ MapBit8 ]; if MapBit8 in [29 .. 24] => bit[ 8 ] in { TSig[5] .. TSig[0] }; If MapBit8 = 31 => bit[ 8 ] = 0 ; if MapBit8= 30 => bit[ 8 ] = 1 [4:0] read-write MAPBIT9 map bit[ 9 ] from [ Blue, Green, Red ] or from TSig[5-0]. if MapBit9 in [ 23..0 ] => bit[ 9 ] = [ Blue, Green, Red ] [ MapBit9 ]; if MapBit9 in [29 .. 24] => bit[ 9 ] in { TSig[5] .. TSig[0] }; If MapBit9 = 31 => bit[ 9 ] = 0 ; if MapBit9= 30 => bit[ 9 ] = 1 [12:8] read-write MAPBIT10 map bit[ 10 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit10 in [ 23..0 ] => bit[ 10 ] = [ Blue, Green, Red ] [ MapBit10 ]; if MapBit10 in [29 .. 24] => bit[ 10 ] in { TSig[5] .. TSig[0] } ; If MapBit10 = 31 => bit[ 10 ] = 0 ; if MapBit10= 30 => bit[ 10 ] = 1 [20:16] read-write MAPBIT11 map bit[ 11 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit11 in [ 23..0 ] => bit[ 11 ] = [ Blue, Green, Red ] [ MapBit11 ]; if MapBit11 in [29 .. 24] => bit[ 11 ] in { TSig[5] .. TSig[0] } ; If MapBit11 = 31 => bit[ 11 ] = 0 ; if MapBit11= 30 => bit[ 11 ] = 1 [28:24] read-write MAPBIT15_12 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 12 .. 15 0x41C 32 read-write 0xF0E0D0C 0x1F1F1F1F MAPBIT12 map bit[ 12 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit12 in [ 23..0 ] => bit[ 12 ] = [ Blue, Green, Red ] [ MapBit12 ]; if MapBit12 in [29 .. 24] => bit[ 12 ] in { TSig[5] .. TSig[0] } ; If MapBit12 = 31 => bit[ 12 ] = 0 ; if MapBit12= 30 => bit[ 12 ] = 1 [4:0] read-write MAPBIT13 map bit[ 13 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit13 in [ 23..0 ] => bit[ 13 ] = [ Blue, Green, Red ] [ MapBit13 ]; if MapBit13 in [29 .. 24] => bit[ 13 ] in { TSig[5] .. TSig[0] } ; If MapBit13 = 31 => bit[ 13 ] = 0 ; if MapBit13= 30 => bit[ 13 ] = 1 [12:8] read-write MAPBIT14 map bit[ 14 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit14 in [ 23..0 ] => bit[ 14 ] = [ Blue, Green, Red ] [ MapBit14 ]; if MapBit14 in [29 .. 24] => bit[ 14 ] in { TSig[5] .. TSig[0] } ; If MapBit14 = 31 => bit[ 14 ] = 0 ; if MapBit14= 30 => bit[ 14 ] = 1 [20:16] read-write MAPBIT15 map bit[ 15 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit15 in [ 23..0 ] => bit[ 15 ] = [ Blue, Green, Red ] [ MapBit15 ]; if MapBit15 in [29 .. 24] => bit[ 15 ] in { TSig[5] .. TSig[0] } ; If MapBit15 = 31 => bit[ 15 ] = 0 ; if MapBit15= 30 => bit[ 15 ] = 1 [28:24] read-write MAPBIT19_16 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 16 .. 19 0x420 32 read-write 0x13121110 0x1F1F1F1F MAPBIT16 map bit[ 16 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit16 in [ 23..0 ] => bit[ 16 ] = [ Blue, Green, Red ] [ MapBit16 ]; if MapBit16 in [29 .. 24] => bit[ 16 ] in { TSig[5] .. TSig[0] } ; If MapBit16 = 31 => bit[ 16 ] = 0 ; if MapBit16= 30 => bit[ 16 ] = 1 [4:0] read-write MAPBIT17 map bit[ 17 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit17 in [ 23..0 ] => bit[ 17 ] = [ Blue, Green, Red ] [ MapBit17 ]; if MapBit17 in [29 .. 24] => bit[ 17 ] in { TSig[5] .. TSig[0] } ; If MapBit17 = 31 => bit[ 17 ] = 0 ; if MapBit17= 30 => bit[ 17 ] = 1 [12:8] read-write MAPBIT18 map bit[ 18 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit18 in [ 23..0 ] => bit[ 18 ] = [ Blue, Green, Red ] [ MapBit18 ]; if MapBit18 in [29 .. 24] => bit[ 18 ] in { TSig[5] .. TSig[0] } ; If MapBit18 = 31 => bit[ 18 ] = 0 ; if MapBit18= 30 => bit[ 18 ] = 1 [20:16] read-write MAPBIT19 map bit[ 19 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit19 in [ 23..0 ] => bit[ 19 ] = [ Blue, Green, Red ] [ MapBit19 ]; if MapBit19 in [29 .. 24] => bit[ 19 ] in { TSig[5] .. TSig[0] } ; If MapBit19 = 31 => bit[ 19 ] = 0 ; if MapBit19= 30 => bit[ 19 ] = 1 [28:24] read-write MAPBIT23_20 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 20 .. 23 0x424 32 read-write 0x17161514 0x1F1F1F1F MAPBIT20 map bit[ 20 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit20 in [ 23..0 ] => bit[ 20 ] = [ Blue, Green, Red ] [ MapBit20 ]; if MapBit20 in [29 .. 24] => bit[ 20 ] in { TSig[5] .. TSig[0] } ; If MapBit20 = 31 => bit[ 20 ] = 0 ; if MapBit20= 30 => bit[ 20 ] = 1 [4:0] read-write MAPBIT21 map bit[ 21 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit21 in [ 23..0 ] => bit[ 21 ] = [ Blue, Green, Red ] [ MapBit21 ]; if MapBit21 in [29 .. 24] => bit[ 21 ] in { TSig[5] .. TSig[0] } ; If MapBit21 = 31 => bit[ 21 ] = 0 ; if MapBit21= 30 => bit[ 21 ] = 1 [12:8] read-write MAPBIT22 map bit[ 22 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit22 in [ 23..0 ] => bit[ 22 ] = [ Blue, Green, Red ] [ MapBit22 ]; if MapBit22 in [29 .. 24] => bit[ 22 ] in { TSig[5] .. TSig[0] } ; If MapBit22 = 31 => bit[ 22 ] = 0 ; if MapBit22= 30 => bit[ 22 ] = 1 [20:16] read-write MAPBIT23 map bit[ 23 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit23 in [ 23..0 ] => bit[ 23 ] = [ Blue, Green, Red ] [ MapBit23 ]; if MapBit23 in [29 .. 24] => bit[ 23 ] in { TSig[5] .. TSig[0] } ; If MapBit23 = 31 => bit[ 23 ] = 0 ; if MapBit23= 30 => bit[ 23 ] = 1 [28:24] read-write MAPBIT27_24 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 24 .. 27 0x428 32 read-write 0x1B1A1918 0x1F1F1F1F MAPBIT24 map bit[24] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit24 in [ 23..0 ] => bit[24] = [ Blue, Green, Red ] [ MapBit24 ]; if MapBit24 in [29 .. 24] => bit[24] in { TSig[5] .. TSig[0] } ; If MapBit24 = 31 => bit[24] = 0 ; if MapBit24= 30 => bit[24] = 1 [4:0] read-write MAPBIT25 map bit[25] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit25 in [ 23..0 ] => bit[25] = [ Blue, Green, Red ] [ MapBit25 ]; if MapBit25 in [29 .. 24] => bit[25] in { TSig[5] .. TSig[0] } ; If MapBit25 = 31 => bit[25] = 0 ; if MapBit25= 30 => bit[25] = 1 [12:8] read-write MAPBIT26 map bit[26] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit26 in [ 23..0 ] => bit[26] = [ Blue, Green, Red ] [ MapBit26 ]; if MapBit26 in [29 .. 24] => bit[26] in { TSig[5] .. TSig[0] } ; If MapBit26 = 31 => bit[26] = 0 ; if MapBit26= 30 => bit[26] = 1 [20:16] read-write MAPBIT27 map bit[27] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit27 in [ 23..0 ] => bit[27] = [ Blue, Green, Red ] [ MapBit27 ]; if MapBit27 in [29 .. 24] => bit[27] in { TSig[5] .. TSig[0] } ; If MapBit27 = 31 => bit[27] = 0 ; if MapBit27= 30 => bit[27] = 1 [28:24] read-write MAPBIT3_0_DUAL Same as MapBit3_0 for 2nd channel 0x42C 32 read-write 0x3020100 0x1F1F1F1F MAPBIT0_DUAL Same as MapBit0 for 2nd channel [4:0] read-write MAPBIT1_DUAL Same as MapBit1 for 2nd channel [12:8] read-write MAPBIT2_DUAL Same as MapBit2 for 2nd channel [20:16] read-write MAPBIT3_DUAL Same as MapBit3 for 2nd channel [28:24] read-write MAPBIT7_4_DUAL Same as MapBit7_4 for 2nd channel 0x430 32 read-write 0x7060504 0x1F1F1F1F MAPBIT4_DUAL Same as MapBit4 for 2nd channel [4:0] read-write MAPBIT5_DUAL Same as MapBit5 for 2nd channel [12:8] read-write MAPBIT6_DUAL Same as MapBit6 for 2nd channel [20:16] read-write MAPBIT7_DUAL Same as MapBit7 for 2nd channel [28:24] read-write MAPBIT11_8_DUAL Same as MapBit11_8 for 2nd channel 0x434 32 read-write 0xB0A0908 0x1F1F1F1F MAPBIT8_DUAL Same as MapBit8 for 2nd channel [4:0] read-write MAPBIT9_DUAL Same as MapBit9 for 2nd channel [12:8] read-write MAPBIT10_DUAL Same as MapBit10 for 2nd channel [20:16] read-write MAPBIT11_DUAL Same as MapBit11 for 2nd channel [28:24] read-write MAPBIT15_12_DUAL Same as MapBit15_12 for 2nd channel 0x438 32 read-write 0xF0E0D0C 0x1F1F1F1F MAPBIT12_DUAL Same as MapBit12 for 2nd channel [4:0] read-write MAPBIT13_DUAL Same as MapBit13 for 2nd channel [12:8] read-write MAPBIT14_DUAL Same as MapBit14 for 2nd channel [20:16] read-write MAPBIT15_DUAL Same as MapBit15 for 2nd channel [28:24] read-write MAPBIT19_16_DUAL Same as MapBit19_16 for 2nd channel 0x43C 32 read-write 0x13121110 0x1F1F1F1F MAPBIT16_DUAL Same as MapBit16 for 2nd channel [4:0] read-write MAPBIT17_DUAL Same as MapBit17 for 2nd channel [12:8] read-write MAPBIT18_DUAL Same as MapBit18 for 2nd channel [20:16] read-write MAPBIT19_DUAL Same as MapBit19 for 2nd channel [28:24] read-write MAPBIT23_20_DUAL Same as MapBit23_20 for 2nd channel 0x440 32 read-write 0x17161514 0x1F1F1F1F MAPBIT20_DUAL Same as MapBit20 for 2nd channel [4:0] read-write MAPBIT21_DUAL Same as MapBit21 for 2nd channel [12:8] read-write MAPBIT22_DUAL Same as MapBit22 for 2nd channel [20:16] read-write MAPBIT23_DUAL Same as MapBit23 for 2nd channel [28:24] read-write MAPBIT27_24_DUAL Same as MapBit27_24 for 2nd channel 0x444 32 read-write 0x1B1A1918 0x1F1F1F1F MAPBIT24_DUAL Same as MapBit24 for 2nd channel [4:0] read-write MAPBIT25_DUAL Same as MapBit25 for 2nd channel [12:8] read-write MAPBIT26_DUAL Same as MapBit26 for 2nd channel [20:16] read-write MAPBIT27_DUAL Same as MapBit27 for 2nd channel [28:24] read-write SPG0POSON Sync pulse generator 0, 'Switch on' position 0x448 32 read-write 0x1480000 0xFFFFFFFF SPGPSON_Y0 Y scan position [14:0] read-write SPGPSON_FIELD0 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X0 X scan position [30:16] read-write SPGPSON_TOGGLE0 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG0MASKON The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0 0x44C 32 read-write 0xFFFF 0x7FFFFFFF SPGMKON0 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG0POSOFF Sync pulse generator 0, 'Switch off' position 0x450 32 read-write 0x1680000 0xFFFFFFFF SPGPSOFF_Y0 Y scan position [14:0] read-write SPGPSOFF_FIELD0 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X0 X scan position [30:16] read-write SPGPSOFF_TOGGLE0 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG0MASKOFF The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0 0x454 32 read-write 0xFFFF 0x7FFFFFFF SPGMKOFF0 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG1POSON Sync pulse generator 1, 'Switch on' position 0x458 32 read-write 0xF3 0xFFFFFFFF SPGPSON_Y1 Y scan position [14:0] read-write SPGPSON_FIELD1 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X1 X scan position [30:16] read-write SPGPSON_TOGGLE1 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG1MASKON The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1 0x45C 32 read-write 0x7FFF0000 0x7FFFFFFF SPGMKON1 mask bits (1= do not include this bit into position matching) [30:0] read-write SPG1POSOFF Sync pulse generator 1, 'Switch off' position 0x460 32 read-write 0xF7 0xFFFFFFFF SPGPSOFF_Y1 Y scan position [14:0] read-write SPGPSOFF_FIELD1 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X1 X scan position [30:16] read-write SPGPSOFF_TOGGLE1 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG1MASKOFF The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1 0x464 32 read-write 0x7FFF0000 0x7FFFFFFF SPGMKOFF1 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG2POSON Sync pulse generator 2, 'Switch on' position 0x468 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y2 Y scan position [14:0] read-write SPGPSON_FIELD2 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X2 X scan position [30:16] read-write SPGPSON_TOGGLE2 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG2MASKON The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2 0x46C 32 read-write 0xFFFF 0x7FFFFFFF SPGMKON2 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG2POSOFF Sync pulse generator 2, 'Switch off' position 0x470 32 read-write 0x1400000 0xFFFFFFFF SPGPSOFF_Y2 Y scan position [14:0] read-write SPGPSOFF_FIELD2 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X2 X scan position [30:16] read-write SPGPSOFF_TOGGLE2 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG2MASKOFF The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2 0x474 32 read-write 0xFFFF 0x7FFFFFFF SPGMKOFF2 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG3POSON Sync pulse generator 3, 'Switch on' position 0x478 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y3 Y scan position [14:0] read-write SPGPSON_FIELD3 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X3 X scan position [30:16] read-write SPGPSON_TOGGLE3 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG3MASKON The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3 0x47C 32 read-write 0x7FFF0000 0x7FFFFFFF SPGMKON3 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG3POSOFF Sync pulse generator 3, 'Switch off' position 0x480 32 read-write 0xF0 0xFFFFFFFF SPGPSOFF_Y3 Y scan position [14:0] read-write SPGPSOFF_FIELD3 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X3 X scan position [30:16] read-write SPGPSOFF_TOGGLE3 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG3MASKOFF The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3 0x484 32 read-write 0x7FFF0000 0x7FFFFFFF SPGMKOFF3 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG4POSON Sync pulse generator 4, 'Switch on' position 0x488 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y4 Y scan position [14:0] read-write SPGPSON_FIELD4 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X4 X scan position [30:16] read-write SPGPSON_TOGGLE4 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG4MASKON The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4 0x48C 32 read-write 0x0 0x7FFFFFFF SPGMKON4 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG4POSOFF Sync pulse generator 4, 'Switch off' position 0x490 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y4 Y scan position [14:0] read-write SPGPSOFF_FIELD4 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X4 X scan position [30:16] read-write SPGPSOFF_TOGGLE4 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG4MASKOFF The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4 0x494 32 read-write 0x0 0x7FFFFFFF SPGMKOFF4 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG5POSON Sync pulse generator 5, 'Switch on' position 0x498 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y5 Y scan position [14:0] read-write SPGPSON_FIELD5 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X5 X scan position [30:16] read-write SPGPSON_TOGGLE5 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG5MASKON The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5 0x49C 32 read-write 0x0 0x7FFFFFFF SPGMKON5 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG5POSOFF Sync pulse generator 5, 'Switch off' position 0x4A0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y5 Y scan position [14:0] read-write SPGPSOFF_FIELD5 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X5 X scan position [30:16] read-write SPGPSOFF_TOGGLE5 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG5MASKOFF The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5 0x4A4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF5 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG6POSON Sync pulse generator 6, 'Switch on' position 0x4A8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y6 Y scan position [14:0] read-write SPGPSON_FIELD6 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X6 X scan position [30:16] read-write SPGPSON_TOGGLE6 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG6MASKON The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6 0x4AC 32 read-write 0x0 0x7FFFFFFF SPGMKON6 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG6POSOFF Sync pulse generator 6, 'Switch off' position 0x4B0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y6 Y scan position [14:0] read-write SPGPSOFF_FIELD6 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X6 X scan position [30:16] read-write SPGPSOFF_TOGGLE6 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG6MASKOFF The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6 0x4B4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF6 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG7POSON Sync pulse generator 7, 'Switch on' position 0x4B8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y7 Y scan position [14:0] read-write SPGPSON_FIELD7 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X7 X scan position [30:16] read-write SPGPSON_TOGGLE7 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG7MASKON The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7 0x4BC 32 read-write 0x0 0x7FFFFFFF SPGMKON7 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG7POSOFF Sync pulse generator 7, 'Switch off' position 0x4C0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y7 Y scan position [14:0] read-write SPGPSOFF_FIELD7 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X7 X scan position [30:16] read-write SPGPSOFF_TOGGLE7 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG7MASKOFF The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7 0x4C4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF7 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG8POSON Sync pulse generator 8, 'Switch on' position 0x4C8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y8 Y scan position [14:0] read-write SPGPSON_FIELD8 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X8 X scan position [30:16] read-write SPGPSON_TOGGLE8 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG8MASKON The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8 0x4CC 32 read-write 0x0 0x7FFFFFFF SPGMKON8 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG8POSOFF Sync pulse generator 8, 'Switch off' position 0x4D0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y8 Y scan position [14:0] read-write SPGPSOFF_FIELD8 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X8 X scan position [30:16] read-write SPGPSOFF_TOGGLE8 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG8MASKOFF The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8 0x4D4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF8 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG9POSON Sync pulse generator 9, 'Switch on' position 0x4D8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y9 Y scan position [14:0] read-write SPGPSON_FIELD9 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X9 X scan position [30:16] read-write SPGPSON_TOGGLE9 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG9MASKON The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9 0x4DC 32 read-write 0x0 0x7FFFFFFF SPGMKON9 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG9POSOFF Sync pulse generator 9, 'Switch off' position 0x4E0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y9 Y scan position [14:0] read-write SPGPSOFF_FIELD9 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X9 X scan position [30:16] read-write SPGPSOFF_TOGGLE9 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG9MASKOFF The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9 0x4E4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF9 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG10POSON Sync pulse generator 10, 'Switch on' position 0x4E8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y10 Y scan position [14:0] read-write SPGPSON_FIELD10 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X10 X scan position [30:16] read-write SPGPSON_TOGGLE10 toggle enable 0b=disable, 1b=enable [31:31] read-write SPG10MASKON The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10 0x4EC 32 read-write 0x0 0x7FFFFFFF SPGMKON10 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG10POSOFF Sync pulse generator 10, 'Switch off' position 0x4F0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y10 Y scan position [14:0] read-write SPGPSOFF_FIELD10 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X10 X scan position [30:16] read-write SPGPSOFF_TOGGLE10 toggle enable 0b=disable, 1b=enable [31:31] read-write SPG10MASKOFF The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10 0x4F4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF10 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG11POSON Sync pulse generator 11, 'Switch on' position 0x4F8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y11 Y scan position [14:0] read-write SPGPSON_FIELD11 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X11 X scan position [30:16] read-write SPGPSON_TOGGLE11 toggle enable 0b=disable, 1b=enable [31:31] read-write SPG11MASKON The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11 0x4FC 32 read-write 0x0 0x7FFFFFFF SPGMKON11 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG11POSOFF Sync pulse generator 11, 'Switch off' position 0x500 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y11 Y scan position [14:0] read-write SPGPSOFF_FIELD11 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X11 X scan position [30:16] read-write SPGPSOFF_TOGGLE11 toggle enable 0b=disable, 1b=enable [31:31] read-write SPG11MASKOFF The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11 0x504 32 read-write 0x0 0x7FFFFFFF SPGMKOFF11 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SMX0SIGS Selection of input signals of sync mixer 0x508 32 read-write 0x2 0x7FFF SMX0SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX0SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX0SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX0SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX0SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX0FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x50C 32 read-write 0x1 0xFFFFFFFF SMXFCT0 Sync mixer 0 function table [31:0] read-write SMX1SIGS Selection of input signals of sync mixer 0x510 32 read-write 0x3 0x7FFF SMX1SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX1SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX1SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX1SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX1SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX1FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x514 32 read-write 0x1 0xFFFFFFFF SMXFCT1 Sync mixer 1 function table [31:0] read-write SMX2SIGS Selection of input signals of sync mixer 0x518 32 read-write 0x2C 0x7FFF SMX2SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX2SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX2SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX2SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX2SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX2FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x51C 32 read-write 0x8 0xFFFFFFFF SMXFCT2 Sync mixer 2 function table [31:0] read-write SMX3SIGS Selection of input signals of sync mixer 0x520 32 read-write 0x0 0x7FFF SMX3SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX3SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX3SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX3SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX3SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX3FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x524 32 read-write 0x0 0xFFFFFFFF SMXFCT3 Sync mixer 3 function table [31:0] read-write SMX4SIGS Selection of input signals of sync mixer 0x528 32 read-write 0x0 0x7FFF SMX4SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX4SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX4SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX4SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX4SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX4FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x52C 32 read-write 0x0 0xFFFFFFFF SMXFCT4 Sync mixer 4 function table [31:0] read-write SMX5SIGS Selection of input signals of sync mixer 0x530 32 read-write 0x0 0x7FFF SMX5SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX5SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX5SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX5SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX5SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX5FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x534 32 read-write 0x0 0xFFFFFFFF SMXFCT5 Sync mixer 5 function table [31:0] read-write SMX6SIGS Selection of input signals of sync mixer 0x538 32 read-write 0x0 0x7FFF SMX6SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX6SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX6SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX6SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX6SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX6FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x53C 32 read-write 0x0 0xFFFFFFFF SMXFCT6 Sync mixer 6 function table [31:0] read-write SMX7SIGS Selection of input signals of sync mixer 0x540 32 read-write 0x0 0x7FFF SMX7SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX7SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX7SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX7SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX7SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX7FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x544 32 read-write 0x0 0xFFFFFFFF SMXFCT7 Sync mixer 7 function table [31:0] read-write SMX8SIGS Selection of input signals of sync mixer 0x548 32 read-write 0x0 0x7FFF SMX8SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX8SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX8SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX8SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX8SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX8FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x54C 32 read-write 0x0 0xFFFFFFFF SMXFCT8 Sync mixer 8 function table [31:0] read-write SMX9SIGS Selection of input signals of sync mixer 0x550 32 read-write 0x0 0x7FFF SMX9SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX9SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX9SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX9SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX9SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX9FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x554 32 read-write 0x0 0xFFFFFFFF SMXFCT9 Sync mixer 9 function table [31:0] read-write SMX10SIGS Selection of input signals of sync mixer 0x558 32 read-write 0x0 0x7FFF SMX10SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX10SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX10SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX10SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX10SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX10FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x55C 32 read-write 0x0 0xFFFFFFFF SMXFCT10 Sync mixer 10 function table [31:0] read-write SMX11SIGS Selection of input signals of sync mixer 0x560 32 read-write 0x0 0x7FFF SMX11SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX11SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX11SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX11SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX11SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX11FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x564 32 read-write 0x0 0xFFFFFFFF SMXFCT11 Sync mixer 11 function table [31:0] read-write DISENG1 Display Engine 0x00024000 DISENGCFG1 Top-Level Configuration 0x00000000 CTL Display engine control register. 0x0 32 read-write 0x1 0x1 DSPCLKDIVIDE Controls generation of display clock signals for display stream. [0:0] read-write DIV1 External display clock signal has pixel clock frequency. 0 DIV2 External display clock signal has twice the pixel clock frequency. 1 POLARITYCTRL Polarity control for TCon input and corresponding top-level output (TCon by-pass port). 0x4 32 read-write 0x4 0xF POLHS Polarity of hsync signal. [0:0] read-write LOW Low active 0 HIGH High active 1 POLVS Polarity of vsync signal. [1:1] read-write LOW Low active 0 HIGH High active 1 POLEN Polarity of Data_Enable signal. [2:2] read-write LOW Low active 0 HIGH High active 1 PIXINV Inversion of RGB data. [3:3] read-write NONINV No inversion of pixel data 0 INV Pixel data inverted (1. complement) 1 SIGSELECT Tap selection for Signature. 0x10 32 read-write 0x0 0x3 SIG_SELECT Selects a source for Sig unit. [1:0] read-write NONE No source. 0 FRAMEGEN Source is FrameGen output. 1 GAMMACOR Source is GammaCor output. 2 DITHER Source is Dither output. 3 DUMPSELECT Tap selection for Frame Dump. 0x20 32 read-write 0x0 0x300 DUMP_SELECT Selects a source for FrameDump unit. [9:8] read-write NONE No source. 0 FRAMEGEN Source is FrameGen output. 1 GAMMACOR Source is GammaCor output. 2 DITHER Source is Dither output. 3 SIG1 Signature Unit 0x00001000 STATICCONTROL Global configuration shared by all evaluation windows. 0x0 32 read-write 0x8000000 0xFFFF0011 SHDEN Enables shadow registers for RWS type fields (0 = write through, 1 = shadowed). [0:0] read-write SHDLDSEL Source select for events that will load shadow registers into the active configuration. [4:4] read-write LOCAL Shadows are loaded at start of frame for each evaluation window for which ShdLdReq has been set. 0 GLOBAL Shadows of all evaluation windows are loaded synchronous to the display stream (shadow load token received on frame input port). 1 ERRTHRES Number of frames with signature violation before StsSigError is set for an evaluation window. These frames do not need to be consecutive. 0 means that each frame with violation will set the status. The internal counter compared against this threshold is reset when 'ErrThreshReset' consecutive frames without signature violation occur. [23:16] read-write ERRTHRESRESET ErrThresReset must be programmed to value less than 255. Number of consecutive frames without signature violation before StsSigError is reset for an evaluation window. 0 means that each frame without violation will reset the status. The internal counter compared against this threshold is reset with each frame that has violation. [31:24] read-write PANICCOLOR Overlay color for evaluation windows in panic mode. 0x4 32 read-write 0x0 0xFFFFFF80 PANICALPHA Alpha mask bit. [7:7] read-write PANICBLUE Blue color component. [15:8] read-write PANICGREEN Green color component. [23:16] read-write PANICRED Red color component. [31:24] read-write EVALCONTROL0 Control settings for evaluation window 0. 0x8 32 read-write 0x0 0x30303 ENEVALWIN0 When enabled (value 1) a CRC signature is computed for all pixels inside this evaluation window (SigCRC). When this bit is cleared, the internal status for this window is reset (StsSigError bit and frame counters). [0:0] read-write ENCRC0 When enabled (value 1) the measured signature is checked against a reference value (SigCRCRef). [1:1] read-write ALPHAMASK0 When enabled (value 1) pixels with alpha bit = 0 are ignored for signature computation. [8:8] read-write ALPHAINV0 When enabled (value 1) the effect of AlphaMask is inverted (pixels with alpha bit = 1 are ignored then). [9:9] read-write ENLOCALPANIC0 When enabled (value 1) the error status this window (StsSigError) will replace all pixels inside the window by a constant color on the display. Skip regions due to other evaluation windows on top are not modified. AlphaMask, when enabled, is not considered for this replacement. [16:16] read-write ENGLOBALPANIC0 When enabled (value 1) the error status of this window (StsSigError) will activate the panic mode of the display stream's Frame Generator, which can switch to another display mode in response. [17:17] read-write EVALUPPERLEFT0 Upper left corner of evaluation window 0. 0xC 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT0 X coordinate. [13:0] read-write YEVALUPPERLEFT0 Y coordinate. [29:16] read-write EVALLOWERRIGHT0 Lower right corner of evaluation window 0. 0x10 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT0 X coordinate. [13:0] read-write YEVALLOWERRIGHT0 Y coordinate. [29:16] read-write SIGCRCREDREF0 Reference signature of red channel for evaluation window 0. 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF0 Reference value that is compared against measured SigCRCRed value. [31:0] read-write SIGCRCGREENREF0 Reference signature of green channel for evaluation window 0. 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF0 Reference value that is compared against measured SigCRCGreen value. [31:0] read-write SIGCRCBLUEREF0 Reference signature of blue channel for evaluation window 0. 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF0 Reference value that is compared against measured SigCRCBlue value. [31:0] read-write SIGCRCRED0 Measured signature of red channel for evaluation window 0. 0x20 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED0 CRC values from red channel. [31:0] read-only SIGCRCGREEN0 Measured signature of green channel for evaluation window 0. 0x24 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN0 CRC values from green channel. [31:0] read-only SIGCRCBLUE0 Measured signature of blue channel for evaluation window 0. 0x28 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE0 CRC values from blue channel. [31:0] read-only EVALCONTROL1 Control settings for evaluation window 1. 0x2C 32 read-write 0x0 0x30303 ENEVALWIN1 See EnEvalWin0. [0:0] read-write ENCRC1 See EnCRC0. [1:1] read-write ALPHAMASK1 See AlphaMask0. [8:8] read-write ALPHAINV1 See AlphaInv0. [9:9] read-write ENLOCALPANIC1 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC1 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT1 Upper left corner of evaluation window 1. 0x30 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT1 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT1 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT1 Lower right corner of evaluation window 1. 0x34 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT1 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT1 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF1 Reference signature of red channel for evaluation window 1. 0x38 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF1 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF1 Reference signature of green channel for evaluation window 1. 0x3C 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF1 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF1 Reference signature of blue channel for evaluation window 1. 0x40 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF1 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED1 Measured signature of red channel for evaluation window 1. 0x44 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED1 See SigCRCRed0. [31:0] read-only SIGCRCGREEN1 Measured signature of green channel for evaluation window 1. 0x48 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN1 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE1 Measured signature of blue channel for evaluation window 1. 0x4C 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE1 See SigCRCBlue0. [31:0] read-only EVALCONTROL2 Control settings for evaluation window 2. 0x50 32 read-write 0x0 0x30303 ENEVALWIN2 See EnEvalWin0. [0:0] read-write ENCRC2 See EnCRC0. [1:1] read-write ALPHAMASK2 See AlphaMask0. [8:8] read-write ALPHAINV2 See AlphaInv0. [9:9] read-write ENLOCALPANIC2 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC2 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT2 Upper left corner of evaluation window 2. 0x54 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT2 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT2 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT2 Lower right corner of evaluation window 2. 0x58 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT2 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT2 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF2 Reference signature of red channel for evaluation window 2. 0x5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF2 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF2 Reference signature of green channel for evaluation window 2. 0x60 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF2 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF2 Reference signature of blue channel for evaluation window 2. 0x64 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF2 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED2 Measured signature of red channel for evaluation window 2. 0x68 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED2 See SigCRCRed0. [31:0] read-only SIGCRCGREEN2 Measured signature of green channel for evaluation window 2. 0x6C 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN2 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE2 Measured signature of blue channel for evaluation window 2. 0x70 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE2 See SigCRCBlue0. [31:0] read-only EVALCONTROL3 Control settings for evaluation window 3. 0x74 32 read-write 0x0 0x30303 ENEVALWIN3 See EnEvalWin0. [0:0] read-write ENCRC3 See EnCRC0. [1:1] read-write ALPHAMASK3 See AlphaMask0. [8:8] read-write ALPHAINV3 See AlphaInv0. [9:9] read-write ENLOCALPANIC3 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC3 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT3 Upper left corner of evaluation window 3. 0x78 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT3 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT3 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT3 Lower right corner of evaluation window 3. 0x7C 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT3 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT3 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF3 Reference signature of red channel for evaluation window 3. 0x80 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF3 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF3 Reference signature of green channel for evaluation window 3. 0x84 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF3 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF3 Reference signature of blue channel for evaluation window 3. 0x88 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF3 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED3 Measured signature of red channel for evaluation window 3. 0x8C 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED3 See SigCRCRed0. [31:0] read-only SIGCRCGREEN3 Measured signature of green channel for evaluation window 3. 0x90 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN3 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE3 Measured signature of blue channel for evaluation window 3. 0x94 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE3 See SigCRCBlue0. [31:0] read-only EVALCONTROL4 Control settings for evaluation window 4. 0x98 32 read-write 0x0 0x30303 ENEVALWIN4 See EnEvalWin0. [0:0] read-write ENCRC4 See EnCRC0. [1:1] read-write ALPHAMASK4 See AlphaMask0. [8:8] read-write ALPHAINV4 See AlphaInv0. [9:9] read-write ENLOCALPANIC4 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC4 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT4 Upper left corner of evaluation window 4. 0x9C 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT4 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT4 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT4 Lower right corner of evaluation window 4. 0xA0 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT4 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT4 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF4 Reference signature of red channel for evaluation window 4. 0xA4 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF4 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF4 Reference signature of green channel for evaluation window 4. 0xA8 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF4 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF4 Reference signature of blue channel for evaluation window 4. 0xAC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF4 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED4 Measured signature of red channel for evaluation window 4. 0xB0 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED4 See SigCRCRed0. [31:0] read-only SIGCRCGREEN4 Measured signature of green channel for evaluation window 4. 0xB4 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN4 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE4 Measured signature of blue channel for evaluation window 4. 0xB8 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE4 See SigCRCBlue0. [31:0] read-only EVALCONTROL5 Control settings for evaluation window 5. 0xBC 32 read-write 0x0 0x30303 ENEVALWIN5 See EnEvalWin0. [0:0] read-write ENCRC5 See EnCRC0. [1:1] read-write ALPHAMASK5 See AlphaMask0. [8:8] read-write ALPHAINV5 See AlphaInv0. [9:9] read-write ENLOCALPANIC5 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC5 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT5 Upper left corner of evaluation window 5. 0xC0 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT5 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT5 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT5 Lower right corner of evaluation window 5. 0xC4 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT5 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT5 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF5 Reference signature of red channel for evaluation window 5. 0xC8 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF5 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF5 Reference signature of green channel for evaluation window 5. 0xCC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF5 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF5 Reference signature of blue channel for evaluation window 5. 0xD0 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF5 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED5 Measured signature of red channel for evaluation window 5. 0xD4 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED5 See SigCRCRed0. [31:0] read-only SIGCRCGREEN5 Measured signature of green channel for evaluation window 5. 0xD8 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN5 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE5 Measured signature of blue channel for evaluation window 5. 0xDC 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE5 See SigCRCBlue0. [31:0] read-only EVALCONTROL6 Control settings for evaluation window 6. 0xE0 32 read-write 0x0 0x30303 ENEVALWIN6 See EnEvalWin0. [0:0] read-write ENCRC6 See EnCRC0. [1:1] read-write ALPHAMASK6 See AlphaMask0. [8:8] read-write ALPHAINV6 See AlphaInv0. [9:9] read-write ENLOCALPANIC6 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC6 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT6 Upper left corner of evaluation window 6. 0xE4 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT6 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT6 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT6 Lower right corner of evaluation window 6. 0xE8 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT6 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT6 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF6 Reference signature of red channel for evaluation window 6. 0xEC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF6 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF6 Reference signature of green channel for evaluation window 6. 0xF0 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF6 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF6 Reference signature of blue channel for evaluation window 6. 0xF4 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF6 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED6 Measured signature of red channel for evaluation window 6. 0xF8 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED6 See SigCRCRed0. [31:0] read-only SIGCRCGREEN6 Measured signature of green channel for evaluation window 6. 0xFC 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN6 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE6 Measured signature of blue channel for evaluation window 6. 0x100 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE6 See SigCRCBlue0. [31:0] read-only EVALCONTROL7 Control settings for evaluation window 7. 0x104 32 read-write 0x0 0x30303 ENEVALWIN7 See EnEvalWin0. [0:0] read-write ENCRC7 See EnCRC0. [1:1] read-write ALPHAMASK7 See AlphaMask0. [8:8] read-write ALPHAINV7 See AlphaInv0. [9:9] read-write ENLOCALPANIC7 See EnLocalPanic0. [16:16] read-write ENGLOBALPANIC7 See EnGlobalPanic0. [17:17] read-write EVALUPPERLEFT7 Upper left corner of evaluation window 7. 0x108 32 read-write 0x0 0x3FFF3FFF XEVALUPPERLEFT7 See XEvalUpperLeft0. [13:0] read-write YEVALUPPERLEFT7 See YEvalUpperLeft0. [29:16] read-write EVALLOWERRIGHT7 Lower right corner of evaluation window 7. 0x10C 32 read-write 0x0 0x3FFF3FFF XEVALLOWERRIGHT7 See XEvalLowerRight0. [13:0] read-write YEVALLOWERRIGHT7 See YEvalLowerRight0. [29:16] read-write SIGCRCREDREF7 Reference signature of red channel for evaluation window 7. 0x110 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCREDREF7 See SigCRCRedRef0. [31:0] read-write SIGCRCGREENREF7 Reference signature of green channel for evaluation window 7. 0x114 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREENREF7 See SigCRCGreenRef0. [31:0] read-write SIGCRCBLUEREF7 Reference signature of blue channel for evaluation window 7. 0x118 32 read-write 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUEREF7 See SigCRCBlueRef0. [31:0] read-write SIGCRCRED7 Measured signature of red channel for evaluation window 7. 0x11C 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCRED7 See SigCRCRed0. [31:0] read-only SIGCRCGREEN7 Measured signature of green channel for evaluation window 7. 0x120 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCGREEN7 See SigCRCGreen0. [31:0] read-only SIGCRCBLUE7 Measured signature of blue channel for evaluation window 7. 0x124 32 read-only 0xFFFFFFFF 0xFFFFFFFF SIGCRCBLUE7 See SigCRCBlue0. [31:0] read-only SHADOWLOAD Shadow load control register. 0x128 32 read-write 0x0 0xFF SHDLDREQ Shadow load request for each evaluation window (bit index = window index). Writing a '1' to a bit will load the shadows into the active configuration for that window at start of next frame. Writing a '0' has no effect. The flag is reset by HW once the shadows have been loaded. A shadow load interrupt signal is generated when shadows have been loaded for at least one evaluation window. Has only effect when ShdLdSel is set to LOCAL. [7:0] read-write CONTINUOUSMODE Signature operation mode control. 0x12C 32 read-write 0x0 0x1 ENCONT EnCont = 0: disables continuous mode. Signatures will be generated only once and in idle state after completion of measurement. In this 'ONE_TIME' mode the signature must be triggered by 'Kick' field. EnCont = 1: enables continuous mode. Write '1' to this field, signature starts and measures every incoming frame until EnCont is turned to 0. 'Kick' has no effect when 'EnCont' = 1. [0:0] read-write SOFTWAREKICK Signature measurement trigger. 0x130 32 write-only 0x0 0x0 KICK ContinueMode.EnCont=0: Write '1' to this field in order to start signature computation with next frame. ContinueMode.EnCont=1: This field is ignored. [0:0] write-only STATUS Module status. 0x134 32 read-only 0x100000 0x1100FF STSSIGERROR Error status bits for all evaluation windows (bit index = window index). When a bit is set it means that measured signature value is different from reference value (SigCRCRef). The bit is set when EnCRC is active and a certain number of frames have a violation (ErrThres). It is reset when the reference check for evaluation window is disabled (EnEvalWin or EnCRC) or in case a certain number of consecutive frames have no violation (ErrThresReset). The value corresponds to the panic status of this evaluation window. [7:0] read-only STSSIGVALID Measured signature values are valid. This flag is set when the SigCRC fields have been updated for all enabled evaluation windows. In that case also the corresponding interrupt event is triggered. It is reset when SW writes a '1' to the 'Kick' field in order to start a new measurement. [16:16] read-only STSSIGIDLE StsSigIdle = 1: Signature is in Idle state. StsSigIdle = 0: Signature runs. [20:20] read-only FRAMEGEN1 Frame Generator 0x00002000 FGSTCTRL FrameGen Static Control Register 0x0 32 read-write 0x0 0x7 SHDEN Enables shadowing for RWS type configuration fields. Otherwise shadow registers are immediately updated when written. [0:0] read-write FGSYNCMODE Determines the operating mode of the framegen unit for side-by-side synchronization. The framegen unit programmed as master generates synchronization pulses. The framegen units programmed as slaves are synchronized to the master unit. There must be only one framegen unit programmed acting as master. [2:1] read-write OFF No side-by-side synchronization. 0 MASTER Framegen is master. 1 SLAVE_CYC Framegen is slave. Runs in cyclic synchronization mode. 2 SLAVE_ONCE Framegen is slave. Runs in one time synchronization mode. 3 HTCFG1 FrameGen Horizontal Timing Config Register 1 0x4 32 read-write 0x18F0140 0x3FFF3FFF HACT Horizontal size of active display area in pixels. Hact shall be greater or equal than 4. Note: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync. [13:0] read-write HTOTAL Total horizontal size of frame in pixels. (Set value +1 is the total horizontal size of frame) Htotal shall be greater or equal than Hact + Hsbp. Note1: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync. Note2: If SRAdj==1 then Htotal[0] shall be equal the value of SREven (for sec. channel only). [29:16] read-write HTCFG2 FrameGen Horizontal Timing Config Register 2 0x8 32 read-write 0x8047001F 0xBFFF3FFF HSYNC Width of HSYNC pulse in pixels. (Set value +1 is the width of HSYNC pulse) HSYNC is of zero width if HsEn==0. Note: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync. [13:0] read-write HSBP Width of HSYNC pulse plus width of horizontal back porch in pixels. (Set value +1 is the width of HSYNC pulse plus width of horizontal back porch) Hsbp shall be greater or equal than Hsync. Note: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync. [29:16] read-write HSEN Enables generation of HSYNC pulse. [31:31] read-write VTCFG1 FrameGen Vertical Timing Config Register 1 0xC 32 read-write 0xFC00F0 0x3FFF3FFF VACT Vertical size of active display area in lines. Vact shall be greater or equal than 4. Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync. [13:0] read-write VTOTAL Total vertical size of frame in lines. (Set value +1 is the total vertical size of frame) Vtotal shall be greater or equal than Vact + Vsbp. Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync. [29:16] read-write VTCFG2 FrameGen Vertical Timing Config Register 2 0x10 32 read-write 0x80090003 0xBFFF3FFF VSYNC Width of VSYNC pulse in lines. (Set value +1 is the width of VSYNC pulse) VSYNC is of zero width if VsEn==0. Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync. [13:0] read-write VSBP Width of VSYNC pulse plus width of vertical back porch in lines. (Set value +1 is the width of VSYNC pulse plus width of vertical back porch) Vsbp shall be greater or equal than Vsync. Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync. [29:16] read-write VSEN Enables generation of VSYNC pulse. [31:31] read-write INT0CONFIG Coordinates of the trigger point for generation of the Int0 interrupt signal 0x14 32 read-write 0x0 0xBFFFBFFF INT0COL Specifies on which column of the display raster the Int0 signal is triggered (1 .. Int0Col .. HTOTAL). Adaptive display timing must be taken into account when defining Int0Col (1 .. Int0Col .. HTOTAL_MIN). [13:0] read-write INT0HSEN When enabled, Int0Row setting is ignored so that the interrupt occurs every line at position given by Int0Col. [15:15] read-write INT0ROW Specifies on which row of the display raster the Int0 signal is triggered (1 .. Int0Row .. VTOTAL). Adaptive display timing must be taken into account when defining Int0Row (1 .. Int0Row .. VTOTAL_MIN). [29:16] read-write INT0EN Enables Int0. [31:31] read-write INT1CONFIG Coordinates of the trigger point for generation of the Int1 interrupt signal 0x18 32 read-write 0x0 0xBFFFBFFF INT1COL Specifies on which column of the display raster the Int1 signal is triggered (1 .. Int1Col .. HTOTAL). Adaptive display timing must be taken into account when defining Int1Col (1 .. Int1Col .. HTOTAL_MIN). [13:0] read-write INT1HSEN When enabled, Int1Row setting is ignored so that the interrupt occurs every line at position given by Int1Col. [15:15] read-write INT1ROW Specifies on which row of the display raster the Int1 signal is triggered (1 .. Int1Row .. VTOTAL). Adaptive display timing must be taken into account when defining Int1Row (1 .. Int1Row .. VTOTAL_MIN). [29:16] read-write INT1EN Enables Int1 (irq[1]). [31:31] read-write INT2CONFIG Coordinates of the trigger point for generation of the Int2 interrupt signal 0x1C 32 read-write 0x0 0xBFFFBFFF INT2COL Specifies on which column of the display raster the Int2 signal is triggered (1 .. Int2Col .. HTOTAL). Adaptive display timing must be taken into account when defining Int2Col (1 .. Int2Col .. HTOTAL_MIN). [13:0] read-write INT2HSEN When enabled, Int2Row setting is ignored so that the interrupt occurs every line at position given by Int2Col. [15:15] read-write INT2ROW Specifies on which row of the display raster the Int2 signal is triggered (1 .. Int2Row .. VTOTAL). Adaptive display timing must be taken into account when defining Int2Row (1 .. Int2Row .. VTOTAL_MIN). [29:16] read-write INT2EN Enables Int2. [31:31] read-write INT3CONFIG Coordinates of the trigger point for generation of the Int3 interrupt signal 0x20 32 read-write 0x0 0xBFFFBFFF INT3COL Specifies on which column of the display raster the Int3 signal is triggered (1 .. Int3Col .. HTOTAL). Adaptive display timing must be taken into account when defining Int3Col (1 .. Int3Col .. HTOTAL_MIN). [13:0] read-write INT3HSEN When enabled, Int3Row setting is ignored so that the interrupt occurs every line at position given by Int3Col. [15:15] read-write INT3ROW Specifies on which row of the display raster the Int3 signal is triggered (1 .. Int3Row .. VTOTAL). Adaptive display timing must be taken into account when defining Int3Row (1 .. Int3Row .. VTOTAL_MIN). [29:16] read-write INT3EN Enables Int3. [31:31] read-write PKICKCONFIG Coordinates of the trigger point for generation of the primary kick signal 0x24 32 read-write 0xF00140 0xBFFFBFFF PKICKCOL Specifies on which column of the display raster the pkick signal is triggered (1 .. PKickCol .. HTOTAL). Adaptive display timing must be taken into account when defining PKickCol (1 .. PKickCol .. HTOTAL_MIN). [13:0] read-write PKICKINT0EN If enabled, maps the primary kick signal (pkick) on the interrupt pin int0. Overrides int0en. [15:15] read-write PKICKROW Specifies on which row of the display raster the pkick signal is triggered (1 .. PKickRow .. VTOTAL). Adaptive display timing must be taken into account when defining PKickRow (1 .. PKickRow .. VTOTAL_MIN). [29:16] read-write PKICKEN Enables pkick signal. [31:31] read-write SKICKCONFIG Coordinates of the trigger point for generation of the secondary kick signal 0x28 32 read-write 0xF00140 0xFFFFBFFF SKICKCOL Specifies on which column of the display raster the skick signal is triggered (1 .. SKickCol .. HTOTAL). Adaptive display timing must be taken into account when defining SKickCol (1 .. SKickCol .. HTOTAL_MIN). [13:0] read-write SKICKINT1EN If enabled, maps the secondary kick signal (skick) on the interrupt pin int1. Overrides int1en. [15:15] read-write SKICKROW Specifies on which row of the display raster the skick signal is triggered (1 .. SKickRow .. VTOTAL). Adaptive display timing must be taken into account when defining SKickRow (1 .. SKickRow .. VTOTAL_MIN). [29:16] read-write SKICKTRIG Select source for skick generation. [30:30] read-write INTERNAL Use internal skick signal, trigger point defined by SKickRow and SKickCol. 0 EXTERNAL Use external skick input as trigger. 1 SKICKEN Enables generation of internal skick signal. [31:31] read-write SECSTATCONFIG Configuration register for controlling the behavior of the SecSyncStat field in the FgSecChStat register. 0x2C 32 read-write 0x112 0xFFF LEVGOODFRAMES Number of continuous correct frames that must be processed before SecSyncStat field goes 1 (in sync). Value of 0 is not allowed. [3:0] read-write LEVBADFRAMES Not used. [7:4] read-write LEVSKEWINRANGE Number of continuous frames the measured skew value shall be within the range defined by SyncRangeLow and SyncRangeHigh. If this condition is true, additionally LevGoodFrames valid frames must be processed before the status line of the sec. channel and the SecSyncStat status field goes to 1 indicating synchronized status. Value of 0 is not allowed. [11:8] read-write FGSRCR1 FrameGen Skew Regulation Control Register 1. 0x30 32 read-write 0x0 0x301FF SREN If enabled, skew control for secondary channel is active. If disabled, skew control for secondary channel is in fetch mode. Fetch mode: secondary channel fetches frames and can intentionally produce a backstall via setting sbusy signal to active. This mode is intended to fetch frames from memory via a stallable pipeline, like the primary interface. No timing adaption of frames takes place in this mode. [0:0] read-write SRMODE Skew Control Operating Mode. [2:1] read-write OFF Skew Regulation is off. 0 HREG Horizontal regulation enabled. 1 VREG Vertical regulation enabled. 2 BOTH Both regulation modes are enabled. 3 SRADJ Enables line length adjustment for HTOTAL. If SRQAlign=0, SREven determines whether HTOTAL has odd (SREven=0) or even (SrEven=1) number of pixels. If SRQAlign=1, SRQVal determines the value of the two LSB bits of HTOTAL. [3:3] read-write SREVEN Total line length HTOTAL is even when SRAdj is enabled. Note: This has impact on the settings for Htotal, HtotalMin and HtotalMax. [4:4] read-write SRFASTSYNC Fast Synchronization Mode. Frame Generator is started synchronized to frame timing on secondary channel when switching FgEn from 0 to 1. This allows fast locking of skew regulation. [5:5] read-write SRQALIGN Enables alignment of HTOTAL to be a multiple of 4. Overrides SREven field. Program field SRQVal for the desired value of the two LSB bits of HTOTAL. [6:6] read-write SRQVAL If SRQAlign is enabled, this field determines the fixed value of the two LSB bits of HTOTAL. Note: This has impact on the settings for Htotal, HtotalMin and HtotalMax. [8:7] read-write ZERO Fixed two LSB values of HTOTAL are 0b00. 0 ONE Fixed two LSB values of HTOTAL are 0b01. 1 TWO Fixed two LSB values of HTOTAL are 0b10. 2 THREE Fixed two LSB values of HTOTAL are 0b11. 3 SRDBGDISP If enabled, the pixels are displayed that are read from FIFO when secondary channel is not in sync yet. Otherwise constant color is displayed in unsynchronized state. [16:16] read-write SREPOFF Disables the skew Extrapolation in blanking. [17:17] read-write FGSRCR2 FrameGen Skew Regulation Control Register 2 0x34 32 read-write 0x1B70188 0x3FFF3FFF HTOTALMIN Minimum value of htotal when horizontal regulation is enabled. (Set value +1 is the minimum value of htotal, must be greater or equal Hsbp + Hactive) HTotalMin must be smaller or equal Htotal. Note: If SRAdj==1 then HtotalMin[0] shall be equal to the value of SREven. [13:0] read-write HTOTALMAX Maximum value of htotal when horizontal regulation is enabled. (Set value +1 is the maximum value of htotal) HTotalMax must be greater or equal Htotal. Note: If SRAdj==1 then HtotalMax[0] shall be equal to the value of SREven. [29:16] read-write FGSRCR3 FrameGen Skew Regulation Control Register 3 0x38 32 read-write 0x11500FB 0x3FFF3FFF VTOTALMIN Minimum value of vtotal when vertical regulation is enabled. (Set value +1 is the minimum value of vtotal, must be greater or equal Vsbp + Vactive + 1) [13:0] read-write VTOTALMAX Maximum value of vtotal when vertical regulation is enabled. (Set value +1 is the maximum value of vtotal) [29:16] read-write FGSRCR4 FrameGen Skew Regulation Control Register 4 0x3C 32 read-write 0xC8 0x1FFFFFFF TARGETSKEW Horizontal target skew value for horizontal and vertical skew regulation (signed value). (format is signed integer) [28:0] read-write FGSRCR5 FrameGen Skew Regulation Control Register 5 0x40 32 read-write 0x0 0x1FFFFFFF SYNCRANGELOW Sync range of horizontal and vertical skew regulation. Lower value (signed value). If skew stays within programmed sync range, frame status is assumed synchronized. (format is signed integer) [28:0] read-write FGSRCR6 FrameGen Skew Regulation Control Register 6 0x44 32 read-write 0x190 0x1FFFFFFF SYNCRANGEHIGH Sync range of horizontal and vertical skew regulation. Upper value (signed value). If skew stays within programmed sync range, frame status is assumed synchronized. (format is signed integer) [28:0] read-write FGKSDR FrameGen Kick System Debug Register 0x48 32 read-write 0x20002 0x70007 PCNTCPLMAX Maximum Value for ppendcnt_cpl_s complementary primary kick counter. Do not change! [2:0] read-write SCNTCPLMAX Maximum Value for spendcnt_cpl_s complementary secondary kick counter. Do not change! [18:16] read-write PACFG FrameGen Primary Area Config Register 1 (shadowed) 0x4C 32 read-write 0x10001 0x3FFF3FFF PSTARTX Primary screen upper left corner, x component. Counts from 1. Pstartx = 0 is not allowed. Primary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal. [13:0] read-write PSTARTY Primary screen upper left corner, y component. Counts from 1. Pstarty = 0 is not allowed. Primary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal. [29:16] read-write SACFG FrameGen Secondary Area Config Register 1 (shadowed) 0x50 32 read-write 0x10001 0x3FFF3FFF SSTARTX Secondary screen upper left corner, x component. Counts from 1 . Sstartx = 0 is not allowed. Secondary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal. When skew regulation feature is enabled, the secondary screen shall not overlap the active display area defined by Hact and Vact. [13:0] read-write SSTARTY Secondary screen upper left corner, y component. Counts from 1 . Sstarty = 0 is not allowed. Secondary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal. When skew regulation feature is enabled, the secondary screen shall not overlap the active display area defined by Hact and Vact. [29:16] read-write FGINCTRL FrameGen Input Control Register (shadowed) 0x54 32 read-write 0x6 0x1F FGDM Frame Generator Display Mode. [2:0] read-write BLACK Black color background is shown on the whole screen area. 0 CONSTCOL Programmable constant color is shown in the active area and black color in the blanking area. 1 PRIM Primary input only is shown. 2 SEC Secondary input only is shown. 3 PRIM_ON_TOP Both inputs overlaid with primary on top. 4 SEC_ON_TOP Both inputs overlaid with secondary on top. 5 TEST White color background with test pattern is shown in the active area and black color in the blanking area. 6 BLEND Blending of the mode PRIM with the mode SEC. 7 ENPRIMALPHA When enabled, alpha plane of primary channel is considered for screen composition. If the alpha component of the current pixel is 255, this pixel is opaque. Otherwise this pixel is transparent. Setting this field to 1 has no effect, when FgDm == BLEND. [3:3] read-write ENSECALPHA When enabled, alpha plane of secondary channel is considered for screen composition. If the alpha component of the current pixel is 255, this pixel is opaque. Otherwise this pixel is transparent. Setting this field to 1 has no effect, when FgDm == BLEND. [4:4] read-write FGINCTRLPANIC FrameGen Input Control Panic Register (shadowed) 0x58 32 read-write 0x6 0x1F FGDMPANIC Frame Generator Display Mode. [2:0] read-write BLACK Black color background is shown on the whole screen area. 0 CONSTCOL Programmable constant color is shown in the active area and black color in the blanking area. 1 PRIM Primary input only is shown. 2 SEC Secondary input only is shown. 3 PRIM_ON_TOP Both inputs overlaid with primary on top. 4 SEC_ON_TOP Both inputs overlaid with secondary on top. 5 TEST White color background with test pattern is shown in the active area and black color in the blanking area. 6 BLEND Blending of the mode PRIM with the mode SEC. 7 ENPRIMALPHAPANIC When enabled, alpha plane of primary channel is considered for screen composition. If the alpha component of the current pixel is 255, this pixel is opaque. Otherwise this pixel is transparent. Setting this field to 1 has no effect, when FgDmPanic == BLEND. [3:3] read-write ENSECALPHAPANIC When enabled, alpha plane of secondary channel is considered for screen composition. If the alpha component of the current pixel is 255, this pixel is opaque. Otherwise this pixel is transparent. Setting this field to 1 has no effect, when FgDmPanic == BLEND. [4:4] read-write FGCCR FrameGen Constant Color Register (shadowed) 0x5C 32 read-write 0x1FFFFFF 0x1FFFFFF CCBLUE Constant color - blue component. [7:0] read-write CCGREEN Constant color - green component. [15:8] read-write CCRED Constant color - red component. [23:16] read-write CCALPHA Constant color - alpha value. In case of blending the value of 1 will be extended to 0xff. [24:24] read-write BLENDCONTROL Options for blend operations. (shadowed) 0x60 32 read-write 0x1010 0xFF7777 PRIM_C_BLD_FUNC Primary (background) input color blending function [2:0] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 SEC_C_BLD_FUNC Secondary (overlay) input color blending function [6:4] read-write ZERO Cout = Cin * 0 0 ONE Cout = Cin * 1 1 PRIM_ALPHA Cout = Cin * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Cout = Cin * (1 - ALPHA_prim) 3 SEC_ALPHA Cout = Cin * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Cout = Cin * (1 - ALPHA_sec) 5 CONST_ALPHA Cout = Cin * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Cout = Cin * (1 - ALPHA_const) 7 PRIM_A_BLD_FUNC Primary (background) input alpha blending function [10:8] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 SEC_A_BLD_FUNC Secondary (overlay) input alpha blending function [14:12] read-write ZERO Aout = Ain * 0 0 ONE Aout = Ain * 1 1 PRIM_ALPHA Aout = Ain * ALPHA_prim 2 ONE_MINUS_PRIM_ALPHA Aout = Ain * (1 - ALPHA_prim) 3 SEC_ALPHA Aout = Ain * ALPHA_sec 4 ONE_MINUS_SEC_ALPHA Aout = Ain * (1 - ALPHA_sec) 5 CONST_ALPHA Aout = Ain * ALPHA_const 6 ONE_MINUS_CONST_ALPHA Aout = Ain * (1 - ALPHA_const) 7 BLENDALPHA Constant alpha value, used for constant alpha blending [23:16] read-write FGENABLE FrameGen Enable Register 0x64 32 read-write 0x0 0x1 FGEN Frame Generator Enable. Note: For loading the shadow registers at start-up of FrameGen unit write the FgSlr.ShdTokGen field immediately before writing this field. [0:0] read-write FGSLR FrameGen Shadow Load Register 0x68 32 write-only 0x0 0x0 SHDTOKGEN Generate shadow load token. Can be used to load shadow register in this and/or all subsequent units up to the next token end point. [0:0] write-only FGENSTS FrameGen Enable Status Register 0x6C 32 read-only 0x0 0x3 ENSTS Indicates the current operating mode of the frame generator. EnSts = 0 means frame generator is disabled. EnSts = 1 means frame generator is enabled. In contrast to the FgEn field of the FgEnable register this bit goes only 0 when all pending frames are processed. [0:0] read-only PANICSTAT Current status of panic mode (0=normal operation mode, 1=panic mode; not locked). [1:1] read-only FGTIMESTAMP Time stamp status. 0x70 32 read-only 0x0 0xFFFFFFFF LINEINDEX Index of the output line that is currently generated (starts with 0 for first active output line). [13:0] read-only FRAMEINDEX Index of the output frame that is currently generated (starts with 0 after reset for first output frame). Wraps around to 0 when maximum value is reached. [31:14] read-only FGCHSTAT FrameGen Channel Status Register 0x74 32 read-only 0x0 0x1030101 PFIFOEMPTY Read request to empty primary pixel FIFO detected. (Bit locked when 1, clear by using ClrPrimStat). [0:0] read-only PRIMSYNCSTAT Current status primary channel synchronization (0 = out of sync (frame tearing), 1 = in sync (normal operation); not locked). [8:8] read-only SFIFOEMPTY Read request to empty secondary pixel FIFO detected. (bit locked when 1, clear by using ClrSecStat). [16:16] read-only SKEWRANGEERR The secondary channel skew value has run out of the limit defined by SyncRangeLow and SyncRangeHigh. (bit locked when 1, clear by using ClrSecStat). [17:17] read-only SECSYNCSTAT Current status secondary channel synchronization (0 = out of sync, 1 = in sync; not locked). [24:24] read-only FGCHSTATCLR FrameGen Channel Status Clear Register 0x78 32 write-only 0x0 0x0 CLRPRIMSTAT Clears PFifoEmpty in FgChStat register. [0:0] write-only CLRSECSTAT Clears SFifoEmpty and SkewRangeErr in FgChStat register. [16:16] write-only FGSKEWMON FrameGen Skew Monitor Register for Secondary Channel Skew Control 0x7C 32 read-only 0x0 0x1FFFFFFF SKEWMON Current skew value monitor for secondary channel skew control. Updated with hlast. (For debugging purposes only). [28:0] read-only FGSFIFOMIN FrameGen Secondary FIFO Min Fill Register 0x80 32 read-only 0x0 0x0 SFIFOMIN Shows the minimal fill level of the secondary channel pixel FIFO. (For debugging purposes only). [10:0] read-only FGSFIFOMAX FrameGen Secondary FIFO Max Fill Register 0x84 32 read-only 0x0 0x0 SFIFOMAX Shows the maximal fill level of the secondary channel pixel FIFO. (For debugging purposes only). [10:0] read-only FGSFIFOFILLCLR FrameGen Secondary FIFO Fill Clear Register 0x88 32 write-only 0x0 0x0 SFIFOFILLCLR Write for clearing register FgSFifoMin and FgSFifoMax. (For debugging purposes only). [0:0] write-only FGSREPD FrameGen Skew Regulation ExtraPolation Debug Register 0x8C 32 read-only 0x0 0x1FFFFFFF EPVAL Calculated value for line skew extrapolation in blanking. Updated with condition 'hlast AND vlast'. (For debugging purposes only) [28:0] read-only FGSRFTD FrameGen Skew Regulation Frame Total Debug Register 0x90 32 read-only 0x0 0xFFFFFFF FRTOT Measured value for frame total measured in display clock cycles. Updated with condition 'hlast AND vlast' when first FrTot value is valid. (For debugging purposes only) [27:0] read-only FGTGPOSITION Current (x,y) positions of the timing generator register in FrameGen timing generator. 0x94 32 read-only 0x3F0000 0xFFFFFFF FRTGX Coordinated pixel position starting from HACT inside a total line generated in timing generator in display clock cycles. (For debugging purposes only) [13:0] read-only FRTGY Coordinated line position starting from VACT inside a total frame generated in timing generator in display clock cycles. (For debugging purposes only) [27:14] read-only GAMMACOR1 Gamma Correction Unit 0x00002400 STATICCONTROL Static control settings. 0x0 32 read-write 0xE 0xF SHDEN Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). [0:0] read-write BLUEWRITEENABLE Write enable for the blue color sampling point entries. [1:1] read-write GREENWRITEENABLE Write enable for the green color sampling point entries. [2:2] read-write REDWRITEENABLE Write enable for the red color sampling point entries. [3:3] read-write LUTSTART Start values for look-up table programming. 0x4 32 write-only 0x0 0x3FFFFFFF STARTBLUE Start value for blue or chroma (V) channel. (format is unsigned integer) [9:0] write-only STARTGREEN Start value for green or chroma (U) channel. (format is unsigned integer) [19:10] write-only STARTRED Start value for red or luma (Y) channel. (format is unsigned integer) [29:20] write-only LUTDELTAS Delta values for look-up table programming. 0x8 32 write-only 0x0 0x0 DELTABLUE Delta value for blue or chroma (V) channel. (format is signed integer) [9:0] write-only DELTAGREEN Delta value for green or chroma (U) channel. (format is signed integer) [19:10] write-only DELTARED Delta value for red or luma (Y) channel. (format is signed integer) [29:20] write-only CONTROL Dynamic control settings. 0xC 32 read-write 0x0 0x31 MODE Operation mode for gamma correction unit [0:0] read-write NEUTRAL Module in neutral mode, input data is bypassed to the output. 0 GAMMACOR Module in gamma correction mode. 1 ALPHAMASK Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value smaller than 0.5 are by-passed unchanged. [4:4] read-write ALPHAINVERT Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha value greater or equal 0.5 are by-passed). [5:5] read-write DITHER1 Dither Unit 0x00002800 CONTROL Dither Unit common control. 0x0 32 read-write 0x0 0x1 MODE Mode which switches Dither Unit on/off. (format is unsigned integer) [0:0] read-write NEUTRAL Neutral mode. Pixels by-pass the Dither Unit, all other settings are ignored. 0 ACTIVE Dither Unit is active. 1 DITHERCONTROL Dither Unit processing control. 0x4 32 read-write 0x300222 0x3310777 BLUE_RANGE_SELECT Mode which sets the reduction of component widths. (format is unsigned integer) [2:0] read-write BLUE_10TO8 Reduces blue component width from 10 bit to 8bit. 2 BLUE_10TO7 Reduces blue component width from 10 bit to 7bit. 3 BLUE_10TO6 Reduces blue component width from 10 bit to 6bit. 4 BLUE_10TO5 Reduces blue component width from 10 bit to 5bit. 5 GREEN_RANGE_SELECT Mode which sets the reduction of component widths. (format is unsigned integer) [6:4] read-write GREEN_10TO8 Reduces green component width from 10 bit to 8bit. 2 GREEN_10TO7 Reduces green component width from 10 bit to 7bit. 3 GREEN_10TO6 Reduces green component width from 10 bit to 6bit. 4 GREEN_10TO5 Reduces green component width from 10 bit to 5bit. 5 RED_RANGE_SELECT Mode which sets the reduction of component widths. (format is unsigned integer) [10:8] read-write RED_10TO8 Reduces red component width from 10 bit to 8bit. 2 RED_10TO7 Reduces red component width from 10 bit to 7bit. 3 RED_10TO6 Reduces red component width from 10 bit to 6bit. 4 RED_10TO5 Reduces red component width from 10 bit to 5bit. 5 OFFSET_SELECT Selects the method how the dither offset is calculated. (format is unsigned integer) [16:16] read-write OFFS_SPATIAL Offset is a bayer matrix value, which is selected according to pixel frame position. 0 OFFS_TEMPORAL Offset is the sum from a bayer matrix value, which is selected according to pixel frame position, and a value from a regular sequence, which changes each frame. 1 ALGO_SELECT The number of output colors that can virtually be displayed by dithering is slightly lower than the number of physical input colors. This field selects how the mapping is done. (format is unsigned integer) [21:20] read-write NO_CORRECTION Best possible resolution for most dark colors. Adds a diminutive offset to overall image brightness. 1 BRIGHTNESS_CORRECTION Preserves overall image brightness. Cannot resolve most dark and most bright colors. All codes in-between are distributed perfectly smooth. 2 CONTRAST_CORRECTION Preserves overall image brightness. Best possible distribution of color codes over complete range. 3 ALPHA_MODE Enables/disables that dithering can be switched by alpha bit. (format is unsigned integer) [25:24] read-write DISABLE The alpha bit is not considered. 0 ENABLE_BY1 Red, green and blue components are only dithered, if the alpha bit is 1. 1 ENABLE_BY0 Red, green and blue components are only dithered, if the alpha bit is 0. 2 RELEASE Dither Unit release. 0x8 32 read-only 0x1 0xFFFF SUBVERSION Dither Unit subversion. (format is unsigned integer) [7:0] read-only VERSION Dither Unit version. (format is unsigned integer) [15:8] read-only TCON1 Timing Controller 0x00003000 64 4 SSQCNTS[%s] The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field 0x0 32 read-write 0x0 0x0 SSQCNTS_SEQY Y scan position [14:0] read-write SSQCNTS_FIELD Field 0b=odd field, 1b=even field [15:15] read-write SSQCNTS_SEQX X scan position [30:16] read-write SSQCNTS_OUT This bit holds the value (0,1) to be output when the X/Y scan position is reached. [31:31] read-write SSQCYCLE This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles 0x400 32 read-write 0x0 0x3F SSQCYCLE Sequencer cycle length (number -1) of sequencer cycles [5:0] read-write SWRESET TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document Note 1/ if tsig[11] pulse=n*pixel_period, (n-1)*0xFF will be blended between ResetWordStart and ResetWordEnd into miniLVDS stream Note 2/ if( EnResetWord=0) Reset-Pulse (ResetWordStart,ResetWordEnd) won't be blended into miniLVDS stream. Pixels will be transferred unchanged 0x404 32 read-write 0x3FC00410 0xFFFFFFF1 SWRESET Software reset [0:0] read-write OPERATION operation mode 0 SWRESET So long SWReset = 0x1 tcon is in 'SW reset state' and it is released by internal logic (SWReset is released and end of frame arrived), read 0b reset not active 1b reset active (that means NO pixel of video frame is excepted until 'SW reset state' is released) 1 ENRESETWORD Enable to blend ResetWord into miniLVDS stream EnResetWord[5-0] mapped to enable Blending Reset Pulse to [RLV5.RLV0]. EnResetWord[11-6] mapped to enable Blending Reset Pulse to [LLV5.LLV0]. [15:4] read-write RESETWORDEND 8-Bits value, that will be blended on falling edge of tsig[11] into miniLVDS stream [23:16] read-write RESETWORDSTART 8-Bits value, that will be blended on rising edge of tsig[11] into miniLVDS stream [31:24] read-write TCON_CTRL TCON Control register 0x408 32 read-write 0x1401408 0x3FFFFFFF CHANNELMODE Selects one of tcon operation modes, SINGLE, DUAL_INTERLEAVED or DUAL_SPLIT. If MiniLVDS operation is selected (EnLVDS = ENABLE_LVDS and LVDSMode = Mini_LVDS), tcon operates in MiniLVDS mode, independent of ChannelMode programming. SplitPosition must be specified in MiniLVDS operation in DUAL_INTERLEAVED or DUAL_SPLIT mode, the horizontal parameter of signal generator have to set twice as they are specified in the panel-specification (panel 320, tsig_start 0, tsig_stop 320 on DUAL-Mode tsig_start 0, tsig_stop 640 ... (SplitPosition is automatically adjusted) ) [1:0] read-write SINGLE Single pixel mode. Both channels channel are active at full pixel clock. If bitmap of both panels are the same, both panels are identical 0 DUAL_INTERLEAVED Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives display columns with even and 2nd one with odd index. 1 DUAL_SPLIT Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives the left and 2nd one the right half of the display. Note data_en is needed in this mode 2 TCON_SYNC Select synchronization between hsync/vsync and hlast/vlast [2:2] read-write H_VLAST tcon timing generator synchronized to hlast, vlast 0 H_VSYNC tcon timing generator synchronized to hsync, vsync where horizontal synchronization is synchronized at the falling edge of hsync 1 BYPASS Bypassing synchronization [3:3] read-write TCON_MODE tcon operation mode 0 BYPASS_MODE tcon in Bypass mode. input pixel and its sync-signals are bypassed to tcon-output 1 INV_CTRL Minimize the toggle rate of tcon output for display panel, that supports data inversion control. Otherwise set Inv_Ctrl = 0. Valid for all channels . Inv_Ctrl does not effect any function on LVDS-Output. [7:4] read-write DISABLE Disable inversion control 0 RGB_2_BITS Enable inversion control for number of RGB-Bits = 2 1 RGB_4_BITS Enable inversion control for number of RGB-Bits = 4 2 RGB_6_BITS Enable inversion control for number of RGB-Bits = 6 3 RGB_8_BITS Enable inversion control for number of RGB-Bits = 8 4 RGB_10_BITS Enable inversion control for number of RGB-Bits = 10 5 RGB_12_BITS Enable inversion control for number of RGB-Bits = 12 6 RGB_14_BITS Enable inversion control for number of RGB-Bits = 14 7 RGB_16_BITS Enable inversion control for number of RGB-Bits = 16 8 RGB_18_BITS Enable inversion control for number of RGB-Bits = 18 9 RGB_20_BITS Enable inversion control for number of RGB-Bits = 20 10 RGB_22_BITS Enable inversion control for number of RGB-Bits = 22 11 RGB_24_BITS Enable inversion control for number of RGB-Bits = 24 12 RSVD1 N/A 13 RSVD2 N/A 14 RSVD3 N/A 15 ENLVDS Enable LVDS Mode [8:8] read-write ENABLE_LVDS Enable LVDS , TTL and RSDS are disable 1 DISABLE_LVDS Disable LVDS, Enable TTL and RSDS 0 LVDSMODE Selection the LVDS Mode if EnLVDS = ENABLE_LVDS [9:9] read-write MINI_LVDS MiniLVDS 1 LVDS LVDS Mode, refer to OpenLDI 0 LVDS_BALANCE Operation mode of LVDS-OpenLDI [10:10] read-write BALANCED LVDS operates in 24 bits Balanced Mode 1 UNBALANCED LVDS operates in 24 bits Unbalanced Mode 0 LVDS_CLOCK_INV Inversion the polarity of lvds clock in OpenLDI Mode [11:11] read-write INV Invert LVDS Clock 1 NON_INV NON-Invert LVDS Clock 0 MINILVDS_OPCODE Operation mode of MiniLVDS [14:12] read-write MODE_3PAIRS MiniLVDS operates in 6 and 8 bit data, three pairs 0 MODE_4PAIRS Not Implemented 1 MODE_5PAIRS Not Implemented 2 MODE_6PAIRS MiniLVDS operates in 6 and 8 bit data, six pairs 3 RSVD1 N/A 4 RSVD2 N/A 5 RSVD3 N/A 6 RSVD4 N/A 7 DUAL_SWAP pixels of lower/upper channel can be swapped if tcon operates in DUAL-mode (include LVDS/miniLVDS) no effect in SINGLE-mode [15:15] read-write SWAP swapping pixels between lower-channel and upper-channel 1 NON_SWAP NON-swapping pixels between lower-channel and upper-channel 0 SPLITPOSITION Index of first column of right display half when ChannelMode is DUAL_SPLIT. SplitPosition and (Hact - SplitPosition) must be less or equal than max supported active frame width. If SplitPosition is greater than (Hact - SplitPosition), then Htotal must be greater than 2*SplitPosition; else Htotal must be greater than (Hact - SplitPosition). Once setting a SplitPosition, data_en is needed. The SplitPosition must be even. [29:16] read-write RSDSINVCTRL Controls inversion of output polarity when connected IO cells operate in RSDS mode 0x40C 32 read-write 0x0 0xFFF0FFF RSDS_INV Inversion vector for 1st channel. For i in [ 0 .. 11 ]; if RSDS_Inv [ i ] == 0 => NON-Inversion of RSDS [ i ] else Inversion of RSDS [ i ] [11:0] read-write RSDS_INV_DUAL Same as RSDS_inv for 2nd channel [27:16] read-write MAPBIT3_0 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 0 .. 3 0x410 32 read-write 0x3020100 0x1F1F1F1F MAPBIT0 map bit[ 0 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit0 in [ 23..0 ] => bit[ 0 ] = [ Blue, Green, Red ] [ MapBit0 ]; if MapBit0 in [29 .. 24] => bit[ 0 ] in { TSig[5] .. TSig[0] }; If MapBit0 = 31 => bit[ 0 ] = 0 ; if MapBit1= 30 => bit[ 0 ] = 1 [4:0] read-write MAPBIT1 map bit[ 1 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit1 in [ 23..0 ] => bit[ 1 ] = [ Blue, Green, Red ] [ MapBit1 ]; if MapBit1 in [29 .. 24] => bit[ 1 ] in { TSig[5] .. TSig[0] }; If MapBit1 = 31 => bit[ 1 ] = 0 ; if MapBit1= 30 => bit[ 1 ] = 1 [12:8] read-write MAPBIT2 map bit[ 2 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit2 in [ 23..0 ] => bit[ 2 ] = [ Blue, Green, Red ] [ MapBit2 ]; if MapBit2 in [29 .. 24] => bit[ 2 ] in { TSig[5] .. TSig[0] }; If MapBit2 = 31 => bit[ 2 ] = 0 ; if MapBit2= 30 => bit[ 2 ] = 1 [20:16] read-write MAPBIT3 map bit[ 3 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit3 in [ 23..0 ] => bit[ 3 ] = [ Blue, Green, Red ] [ MapBit3 ]; if MapBit3 in [29 .. 24] => bit[ 3 ] in { TSig[5] .. TSig[0] }; If MapBit3 = 31 => bit[ 3 ] = 0 ; if MapBit3= 30 => bit[ 3 ] = 1 [28:24] read-write MAPBIT7_4 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 4 .. 7 0x414 32 read-write 0x7060504 0x1F1F1F1F MAPBIT4 map bit[ 4 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit4 in [ 23..0 ] => bit[ 4 ] = [ Blue, Green, Red ] [ MapBit4 ]; if MapBit4 in [29 .. 24] => bit[ 4 ] in { TSig[5] .. TSig[0] }; If MapBit4 = 31 => bit[ 4 ] = 0 ; if MapBit4= 30 => bit[ 4 ] = 1 [4:0] read-write MAPBIT5 map bit[ 5 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit5 in [ 23..0 ] => bit[ 5 ] = [ Blue, Green, Red ] [ MapBit5 ]; if MapBit5 in [29 .. 24] => bit[ 5 ] in { TSig[5] .. TSig[0] }; If MapBit5 = 31 => bit[ 5 ] = 0 ; if MapBit5= 30 => bit[ 5 ] = 1 [12:8] read-write MAPBIT6 map bit[ 6 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit6 in [ 23..0 ] => bit[ 6 ] = [ Blue, Green, Red ] [ MapBit6 ]; if MapBit6 in [29 .. 24] => bit[ 6 ] in { TSig[5] .. TSig[0] }; If MapBit6 = 31 => bit[ 6 ] = 0 ; if MapBit6= 30 => bit[ 6 ] = 1 [20:16] read-write MAPBIT7 map bit[ 7 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit7 in [ 23..0 ] => bit[ 7 ] = [ Blue, Green, Red ] [ MapBit7 ]; if MapBit7 in [29 .. 24] => bit[ 7 ] in { TSig[5] .. TSig[0] }; If MapBit7 = 31 => bit[ 7 ] = 0 ; if MapBit7= 30 => bit[ 7 ] = 1 [28:24] read-write MAPBIT11_8 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 8 .. 11 0x418 32 read-write 0xB0A0908 0x1F1F1F1F MAPBIT8 map bit[ 8 ] from [ Blue, Green, Red ] or from TSig[5-0]. if MapBit8 in [ 23..0 ] => bit[ 8 ] = [ Blue, Green, Red ] [ MapBit8 ]; if MapBit8 in [29 .. 24] => bit[ 8 ] in { TSig[5] .. TSig[0] }; If MapBit8 = 31 => bit[ 8 ] = 0 ; if MapBit8= 30 => bit[ 8 ] = 1 [4:0] read-write MAPBIT9 map bit[ 9 ] from [ Blue, Green, Red ] or from TSig[5-0]. if MapBit9 in [ 23..0 ] => bit[ 9 ] = [ Blue, Green, Red ] [ MapBit9 ]; if MapBit9 in [29 .. 24] => bit[ 9 ] in { TSig[5] .. TSig[0] }; If MapBit9 = 31 => bit[ 9 ] = 0 ; if MapBit9= 30 => bit[ 9 ] = 1 [12:8] read-write MAPBIT10 map bit[ 10 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit10 in [ 23..0 ] => bit[ 10 ] = [ Blue, Green, Red ] [ MapBit10 ]; if MapBit10 in [29 .. 24] => bit[ 10 ] in { TSig[5] .. TSig[0] } ; If MapBit10 = 31 => bit[ 10 ] = 0 ; if MapBit10= 30 => bit[ 10 ] = 1 [20:16] read-write MAPBIT11 map bit[ 11 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit11 in [ 23..0 ] => bit[ 11 ] = [ Blue, Green, Red ] [ MapBit11 ]; if MapBit11 in [29 .. 24] => bit[ 11 ] in { TSig[5] .. TSig[0] } ; If MapBit11 = 31 => bit[ 11 ] = 0 ; if MapBit11= 30 => bit[ 11 ] = 1 [28:24] read-write MAPBIT15_12 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 12 .. 15 0x41C 32 read-write 0xF0E0D0C 0x1F1F1F1F MAPBIT12 map bit[ 12 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit12 in [ 23..0 ] => bit[ 12 ] = [ Blue, Green, Red ] [ MapBit12 ]; if MapBit12 in [29 .. 24] => bit[ 12 ] in { TSig[5] .. TSig[0] } ; If MapBit12 = 31 => bit[ 12 ] = 0 ; if MapBit12= 30 => bit[ 12 ] = 1 [4:0] read-write MAPBIT13 map bit[ 13 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit13 in [ 23..0 ] => bit[ 13 ] = [ Blue, Green, Red ] [ MapBit13 ]; if MapBit13 in [29 .. 24] => bit[ 13 ] in { TSig[5] .. TSig[0] } ; If MapBit13 = 31 => bit[ 13 ] = 0 ; if MapBit13= 30 => bit[ 13 ] = 1 [12:8] read-write MAPBIT14 map bit[ 14 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit14 in [ 23..0 ] => bit[ 14 ] = [ Blue, Green, Red ] [ MapBit14 ]; if MapBit14 in [29 .. 24] => bit[ 14 ] in { TSig[5] .. TSig[0] } ; If MapBit14 = 31 => bit[ 14 ] = 0 ; if MapBit14= 30 => bit[ 14 ] = 1 [20:16] read-write MAPBIT15 map bit[ 15 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit15 in [ 23..0 ] => bit[ 15 ] = [ Blue, Green, Red ] [ MapBit15 ]; if MapBit15 in [29 .. 24] => bit[ 15 ] in { TSig[5] .. TSig[0] } ; If MapBit15 = 31 => bit[ 15 ] = 0 ; if MapBit15= 30 => bit[ 15 ] = 1 [28:24] read-write MAPBIT19_16 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 16 .. 19 0x420 32 read-write 0x13121110 0x1F1F1F1F MAPBIT16 map bit[ 16 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit16 in [ 23..0 ] => bit[ 16 ] = [ Blue, Green, Red ] [ MapBit16 ]; if MapBit16 in [29 .. 24] => bit[ 16 ] in { TSig[5] .. TSig[0] } ; If MapBit16 = 31 => bit[ 16 ] = 0 ; if MapBit16= 30 => bit[ 16 ] = 1 [4:0] read-write MAPBIT17 map bit[ 17 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit17 in [ 23..0 ] => bit[ 17 ] = [ Blue, Green, Red ] [ MapBit17 ]; if MapBit17 in [29 .. 24] => bit[ 17 ] in { TSig[5] .. TSig[0] } ; If MapBit17 = 31 => bit[ 17 ] = 0 ; if MapBit17= 30 => bit[ 17 ] = 1 [12:8] read-write MAPBIT18 map bit[ 18 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit18 in [ 23..0 ] => bit[ 18 ] = [ Blue, Green, Red ] [ MapBit18 ]; if MapBit18 in [29 .. 24] => bit[ 18 ] in { TSig[5] .. TSig[0] } ; If MapBit18 = 31 => bit[ 18 ] = 0 ; if MapBit18= 30 => bit[ 18 ] = 1 [20:16] read-write MAPBIT19 map bit[ 19 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit19 in [ 23..0 ] => bit[ 19 ] = [ Blue, Green, Red ] [ MapBit19 ]; if MapBit19 in [29 .. 24] => bit[ 19 ] in { TSig[5] .. TSig[0] } ; If MapBit19 = 31 => bit[ 19 ] = 0 ; if MapBit19= 30 => bit[ 19 ] = 1 [28:24] read-write MAPBIT23_20 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 20 .. 23 0x424 32 read-write 0x17161514 0x1F1F1F1F MAPBIT20 map bit[ 20 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit20 in [ 23..0 ] => bit[ 20 ] = [ Blue, Green, Red ] [ MapBit20 ]; if MapBit20 in [29 .. 24] => bit[ 20 ] in { TSig[5] .. TSig[0] } ; If MapBit20 = 31 => bit[ 20 ] = 0 ; if MapBit20= 30 => bit[ 20 ] = 1 [4:0] read-write MAPBIT21 map bit[ 21 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit21 in [ 23..0 ] => bit[ 21 ] = [ Blue, Green, Red ] [ MapBit21 ]; if MapBit21 in [29 .. 24] => bit[ 21 ] in { TSig[5] .. TSig[0] } ; If MapBit21 = 31 => bit[ 21 ] = 0 ; if MapBit21= 30 => bit[ 21 ] = 1 [12:8] read-write MAPBIT22 map bit[ 22 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit22 in [ 23..0 ] => bit[ 22 ] = [ Blue, Green, Red ] [ MapBit22 ]; if MapBit22 in [29 .. 24] => bit[ 22 ] in { TSig[5] .. TSig[0] } ; If MapBit22 = 31 => bit[ 22 ] = 0 ; if MapBit22= 30 => bit[ 22 ] = 1 [20:16] read-write MAPBIT23 map bit[ 23 ] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit23 in [ 23..0 ] => bit[ 23 ] = [ Blue, Green, Red ] [ MapBit23 ]; if MapBit23 in [29 .. 24] => bit[ 23 ] in { TSig[5] .. TSig[0] } ; If MapBit23 = 31 => bit[ 23 ] = 0 ; if MapBit23= 30 => bit[ 23 ] = 1 [28:24] read-write MAPBIT27_24 Mapping of 24 bit RGB or Timing Generator TSig[5-0] to bit 24 .. 27 0x428 32 read-write 0x1B1A1918 0x1F1F1F1F MAPBIT24 map bit[24] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit24 in [ 23..0 ] => bit[24] = [ Blue, Green, Red ] [ MapBit24 ]; if MapBit24 in [29 .. 24] => bit[24] in { TSig[5] .. TSig[0] } ; If MapBit24 = 31 => bit[24] = 0 ; if MapBit24= 30 => bit[24] = 1 [4:0] read-write MAPBIT25 map bit[25] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit25 in [ 23..0 ] => bit[25] = [ Blue, Green, Red ] [ MapBit25 ]; if MapBit25 in [29 .. 24] => bit[25] in { TSig[5] .. TSig[0] } ; If MapBit25 = 31 => bit[25] = 0 ; if MapBit25= 30 => bit[25] = 1 [12:8] read-write MAPBIT26 map bit[26] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit26 in [ 23..0 ] => bit[26] = [ Blue, Green, Red ] [ MapBit26 ]; if MapBit26 in [29 .. 24] => bit[26] in { TSig[5] .. TSig[0] } ; If MapBit26 = 31 => bit[26] = 0 ; if MapBit26= 30 => bit[26] = 1 [20:16] read-write MAPBIT27 map bit[27] from [ Blue, Green, Red ] or from TSig[5-0]. If MapBit27 in [ 23..0 ] => bit[27] = [ Blue, Green, Red ] [ MapBit27 ]; if MapBit27 in [29 .. 24] => bit[27] in { TSig[5] .. TSig[0] } ; If MapBit27 = 31 => bit[27] = 0 ; if MapBit27= 30 => bit[27] = 1 [28:24] read-write MAPBIT3_0_DUAL Same as MapBit3_0 for 2nd channel 0x42C 32 read-write 0x3020100 0x1F1F1F1F MAPBIT0_DUAL Same as MapBit0 for 2nd channel [4:0] read-write MAPBIT1_DUAL Same as MapBit1 for 2nd channel [12:8] read-write MAPBIT2_DUAL Same as MapBit2 for 2nd channel [20:16] read-write MAPBIT3_DUAL Same as MapBit3 for 2nd channel [28:24] read-write MAPBIT7_4_DUAL Same as MapBit7_4 for 2nd channel 0x430 32 read-write 0x7060504 0x1F1F1F1F MAPBIT4_DUAL Same as MapBit4 for 2nd channel [4:0] read-write MAPBIT5_DUAL Same as MapBit5 for 2nd channel [12:8] read-write MAPBIT6_DUAL Same as MapBit6 for 2nd channel [20:16] read-write MAPBIT7_DUAL Same as MapBit7 for 2nd channel [28:24] read-write MAPBIT11_8_DUAL Same as MapBit11_8 for 2nd channel 0x434 32 read-write 0xB0A0908 0x1F1F1F1F MAPBIT8_DUAL Same as MapBit8 for 2nd channel [4:0] read-write MAPBIT9_DUAL Same as MapBit9 for 2nd channel [12:8] read-write MAPBIT10_DUAL Same as MapBit10 for 2nd channel [20:16] read-write MAPBIT11_DUAL Same as MapBit11 for 2nd channel [28:24] read-write MAPBIT15_12_DUAL Same as MapBit15_12 for 2nd channel 0x438 32 read-write 0xF0E0D0C 0x1F1F1F1F MAPBIT12_DUAL Same as MapBit12 for 2nd channel [4:0] read-write MAPBIT13_DUAL Same as MapBit13 for 2nd channel [12:8] read-write MAPBIT14_DUAL Same as MapBit14 for 2nd channel [20:16] read-write MAPBIT15_DUAL Same as MapBit15 for 2nd channel [28:24] read-write MAPBIT19_16_DUAL Same as MapBit19_16 for 2nd channel 0x43C 32 read-write 0x13121110 0x1F1F1F1F MAPBIT16_DUAL Same as MapBit16 for 2nd channel [4:0] read-write MAPBIT17_DUAL Same as MapBit17 for 2nd channel [12:8] read-write MAPBIT18_DUAL Same as MapBit18 for 2nd channel [20:16] read-write MAPBIT19_DUAL Same as MapBit19 for 2nd channel [28:24] read-write MAPBIT23_20_DUAL Same as MapBit23_20 for 2nd channel 0x440 32 read-write 0x17161514 0x1F1F1F1F MAPBIT20_DUAL Same as MapBit20 for 2nd channel [4:0] read-write MAPBIT21_DUAL Same as MapBit21 for 2nd channel [12:8] read-write MAPBIT22_DUAL Same as MapBit22 for 2nd channel [20:16] read-write MAPBIT23_DUAL Same as MapBit23 for 2nd channel [28:24] read-write MAPBIT27_24_DUAL Same as MapBit27_24 for 2nd channel 0x444 32 read-write 0x1B1A1918 0x1F1F1F1F MAPBIT24_DUAL Same as MapBit24 for 2nd channel [4:0] read-write MAPBIT25_DUAL Same as MapBit25 for 2nd channel [12:8] read-write MAPBIT26_DUAL Same as MapBit26 for 2nd channel [20:16] read-write MAPBIT27_DUAL Same as MapBit27 for 2nd channel [28:24] read-write SPG0POSON Sync pulse generator 0, 'Switch on' position 0x448 32 read-write 0x1480000 0xFFFFFFFF SPGPSON_Y0 Y scan position [14:0] read-write SPGPSON_FIELD0 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X0 X scan position [30:16] read-write SPGPSON_TOGGLE0 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG0MASKON The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0 0x44C 32 read-write 0xFFFF 0x7FFFFFFF SPGMKON0 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG0POSOFF Sync pulse generator 0, 'Switch off' position 0x450 32 read-write 0x1680000 0xFFFFFFFF SPGPSOFF_Y0 Y scan position [14:0] read-write SPGPSOFF_FIELD0 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X0 X scan position [30:16] read-write SPGPSOFF_TOGGLE0 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG0MASKOFF The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0 0x454 32 read-write 0xFFFF 0x7FFFFFFF SPGMKOFF0 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG1POSON Sync pulse generator 1, 'Switch on' position 0x458 32 read-write 0xF3 0xFFFFFFFF SPGPSON_Y1 Y scan position [14:0] read-write SPGPSON_FIELD1 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X1 X scan position [30:16] read-write SPGPSON_TOGGLE1 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG1MASKON The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1 0x45C 32 read-write 0x7FFF0000 0x7FFFFFFF SPGMKON1 mask bits (1= do not include this bit into position matching) [30:0] read-write SPG1POSOFF Sync pulse generator 1, 'Switch off' position 0x460 32 read-write 0xF7 0xFFFFFFFF SPGPSOFF_Y1 Y scan position [14:0] read-write SPGPSOFF_FIELD1 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X1 X scan position [30:16] read-write SPGPSOFF_TOGGLE1 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG1MASKOFF The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1 0x464 32 read-write 0x7FFF0000 0x7FFFFFFF SPGMKOFF1 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG2POSON Sync pulse generator 2, 'Switch on' position 0x468 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y2 Y scan position [14:0] read-write SPGPSON_FIELD2 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X2 X scan position [30:16] read-write SPGPSON_TOGGLE2 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG2MASKON The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2 0x46C 32 read-write 0xFFFF 0x7FFFFFFF SPGMKON2 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG2POSOFF Sync pulse generator 2, 'Switch off' position 0x470 32 read-write 0x1400000 0xFFFFFFFF SPGPSOFF_Y2 Y scan position [14:0] read-write SPGPSOFF_FIELD2 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X2 X scan position [30:16] read-write SPGPSOFF_TOGGLE2 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG2MASKOFF The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2 0x474 32 read-write 0xFFFF 0x7FFFFFFF SPGMKOFF2 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG3POSON Sync pulse generator 3, 'Switch on' position 0x478 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y3 Y scan position [14:0] read-write SPGPSON_FIELD3 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X3 X scan position [30:16] read-write SPGPSON_TOGGLE3 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG3MASKON The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3 0x47C 32 read-write 0x7FFF0000 0x7FFFFFFF SPGMKON3 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG3POSOFF Sync pulse generator 3, 'Switch off' position 0x480 32 read-write 0xF0 0xFFFFFFFF SPGPSOFF_Y3 Y scan position [14:0] read-write SPGPSOFF_FIELD3 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X3 X scan position [30:16] read-write SPGPSOFF_TOGGLE3 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG3MASKOFF The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3 0x484 32 read-write 0x7FFF0000 0x7FFFFFFF SPGMKOFF3 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG4POSON Sync pulse generator 4, 'Switch on' position 0x488 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y4 Y scan position [14:0] read-write SPGPSON_FIELD4 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X4 X scan position [30:16] read-write SPGPSON_TOGGLE4 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG4MASKON The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4 0x48C 32 read-write 0x0 0x7FFFFFFF SPGMKON4 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG4POSOFF Sync pulse generator 4, 'Switch off' position 0x490 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y4 Y scan position [14:0] read-write SPGPSOFF_FIELD4 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X4 X scan position [30:16] read-write SPGPSOFF_TOGGLE4 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG4MASKOFF The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4 0x494 32 read-write 0x0 0x7FFFFFFF SPGMKOFF4 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG5POSON Sync pulse generator 5, 'Switch on' position 0x498 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y5 Y scan position [14:0] read-write SPGPSON_FIELD5 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X5 X scan position [30:16] read-write SPGPSON_TOGGLE5 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG5MASKON The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5 0x49C 32 read-write 0x0 0x7FFFFFFF SPGMKON5 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG5POSOFF Sync pulse generator 5, 'Switch off' position 0x4A0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y5 Y scan position [14:0] read-write SPGPSOFF_FIELD5 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X5 X scan position [30:16] read-write SPGPSOFF_TOGGLE5 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG5MASKOFF The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5 0x4A4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF5 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG6POSON Sync pulse generator 6, 'Switch on' position 0x4A8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y6 Y scan position [14:0] read-write SPGPSON_FIELD6 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X6 X scan position [30:16] read-write SPGPSON_TOGGLE6 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG6MASKON The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6 0x4AC 32 read-write 0x0 0x7FFFFFFF SPGMKON6 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG6POSOFF Sync pulse generator 6, 'Switch off' position 0x4B0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y6 Y scan position [14:0] read-write SPGPSOFF_FIELD6 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X6 X scan position [30:16] read-write SPGPSOFF_TOGGLE6 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG6MASKOFF The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6 0x4B4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF6 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG7POSON Sync pulse generator 7, 'Switch on' position 0x4B8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y7 Y scan position [14:0] read-write SPGPSON_FIELD7 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X7 X scan position [30:16] read-write SPGPSON_TOGGLE7 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG7MASKON The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7 0x4BC 32 read-write 0x0 0x7FFFFFFF SPGMKON7 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG7POSOFF Sync pulse generator 7, 'Switch off' position 0x4C0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y7 Y scan position [14:0] read-write SPGPSOFF_FIELD7 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X7 X scan position [30:16] read-write SPGPSOFF_TOGGLE7 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG7MASKOFF The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7 0x4C4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF7 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG8POSON Sync pulse generator 8, 'Switch on' position 0x4C8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y8 Y scan position [14:0] read-write SPGPSON_FIELD8 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X8 X scan position [30:16] read-write SPGPSON_TOGGLE8 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG8MASKON The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8 0x4CC 32 read-write 0x0 0x7FFFFFFF SPGMKON8 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG8POSOFF Sync pulse generator 8, 'Switch off' position 0x4D0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y8 Y scan position [14:0] read-write SPGPSOFF_FIELD8 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X8 X scan position [30:16] read-write SPGPSOFF_TOGGLE8 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG8MASKOFF The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8 0x4D4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF8 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG9POSON Sync pulse generator 9, 'Switch on' position 0x4D8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y9 Y scan position [14:0] read-write SPGPSON_FIELD9 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X9 X scan position [30:16] read-write SPGPSON_TOGGLE9 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG9MASKON The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9 0x4DC 32 read-write 0x0 0x7FFFFFFF SPGMKON9 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG9POSOFF Sync pulse generator 9, 'Switch off' position 0x4E0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y9 Y scan position [14:0] read-write SPGPSOFF_FIELD9 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X9 X scan position [30:16] read-write SPGPSOFF_TOGGLE9 Toggle enable 0b=disable, 1b=enable [31:31] read-write SPG9MASKOFF The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9 0x4E4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF9 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG10POSON Sync pulse generator 10, 'Switch on' position 0x4E8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y10 Y scan position [14:0] read-write SPGPSON_FIELD10 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X10 X scan position [30:16] read-write SPGPSON_TOGGLE10 toggle enable 0b=disable, 1b=enable [31:31] read-write SPG10MASKON The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10 0x4EC 32 read-write 0x0 0x7FFFFFFF SPGMKON10 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG10POSOFF Sync pulse generator 10, 'Switch off' position 0x4F0 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y10 Y scan position [14:0] read-write SPGPSOFF_FIELD10 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X10 X scan position [30:16] read-write SPGPSOFF_TOGGLE10 toggle enable 0b=disable, 1b=enable [31:31] read-write SPG10MASKOFF The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10 0x4F4 32 read-write 0x0 0x7FFFFFFF SPGMKOFF10 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG11POSON Sync pulse generator 11, 'Switch on' position 0x4F8 32 read-write 0x0 0xFFFFFFFF SPGPSON_Y11 Y scan position [14:0] read-write SPGPSON_FIELD11 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSON_X11 X scan position [30:16] read-write SPGPSON_TOGGLE11 toggle enable 0b=disable, 1b=enable [31:31] read-write SPG11MASKON The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11 0x4FC 32 read-write 0x0 0x7FFFFFFF SPGMKON11 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SPG11POSOFF Sync pulse generator 11, 'Switch off' position 0x500 32 read-write 0x0 0xFFFFFFFF SPGPSOFF_Y11 Y scan position [14:0] read-write SPGPSOFF_FIELD11 Field 0b=odd field, 1b=even field [15:15] read-write SPGPSOFF_X11 X scan position [30:16] read-write SPGPSOFF_TOGGLE11 toggle enable 0b=disable, 1b=enable [31:31] read-write SPG11MASKOFF The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11 0x504 32 read-write 0x0 0x7FFFFFFF SPGMKOFF11 Mask bits 0b=Include this bit in position matching, 1b= Do not include this bit in position matching [30:0] read-write SMX0SIGS Selection of input signals of sync mixer 0x508 32 read-write 0x2 0x7FFF SMX0SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX0SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX0SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX0SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX0SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX0FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x50C 32 read-write 0x1 0xFFFFFFFF SMXFCT0 Sync mixer 0 function table [31:0] read-write SMX1SIGS Selection of input signals of sync mixer 0x510 32 read-write 0x3 0x7FFF SMX1SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX1SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX1SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX1SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX1SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX1FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x514 32 read-write 0x1 0xFFFFFFFF SMXFCT1 Sync mixer 1 function table [31:0] read-write SMX2SIGS Selection of input signals of sync mixer 0x518 32 read-write 0x2C 0x7FFF SMX2SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX2SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX2SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX2SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX2SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX2FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x51C 32 read-write 0x8 0xFFFFFFFF SMXFCT2 Sync mixer 2 function table [31:0] read-write SMX3SIGS Selection of input signals of sync mixer 0x520 32 read-write 0x0 0x7FFF SMX3SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX3SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX3SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX3SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX3SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX3FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x524 32 read-write 0x0 0xFFFFFFFF SMXFCT3 Sync mixer 3 function table [31:0] read-write SMX4SIGS Selection of input signals of sync mixer 0x528 32 read-write 0x0 0x7FFF SMX4SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX4SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX4SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX4SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX4SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX4FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x52C 32 read-write 0x0 0xFFFFFFFF SMXFCT4 Sync mixer 4 function table [31:0] read-write SMX5SIGS Selection of input signals of sync mixer 0x530 32 read-write 0x0 0x7FFF SMX5SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [2:0] read-write SMX5SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [5:3] read-write SMX5SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [8:6] read-write SMX5SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [11:9] read-write SMX5SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 [14:12] read-write SMX5FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x534 32 read-write 0x0 0xFFFFFFFF SMXFCT5 Sync mixer 5 function table [31:0] read-write SMX6SIGS Selection of input signals of sync mixer 0x538 32 read-write 0x0 0x7FFF SMX6SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX6SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX6SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX6SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX6SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX6FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x53C 32 read-write 0x0 0xFFFFFFFF SMXFCT6 Sync mixer 6 function table [31:0] read-write SMX7SIGS Selection of input signals of sync mixer 0x540 32 read-write 0x0 0x7FFF SMX7SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX7SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX7SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX7SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX7SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX7FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x544 32 read-write 0x0 0xFFFFFFFF SMXFCT7 Sync mixer 7 function table [31:0] read-write SMX8SIGS Selection of input signals of sync mixer 0x548 32 read-write 0x0 0x7FFF SMX8SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX8SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX8SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX8SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX8SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX8FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x54C 32 read-write 0x0 0xFFFFFFFF SMXFCT8 Sync mixer 8 function table [31:0] read-write SMX9SIGS Selection of input signals of sync mixer 0x550 32 read-write 0x0 0x7FFF SMX9SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX9SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX9SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX9SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX9SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX9FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x554 32 read-write 0x0 0xFFFFFFFF SMXFCT9 Sync mixer 9 function table [31:0] read-write SMX10SIGS Selection of input signals of sync mixer 0x558 32 read-write 0x0 0x7FFF SMX10SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX10SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX10SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX10SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX10SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX10FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x55C 32 read-write 0x0 0xFFFFFFFF SMXFCT10 Sync mixer 10 function table [31:0] read-write SMX11SIGS Selection of input signals of sync mixer 0x560 32 read-write 0x0 0x7FFF SMX11SIGS_S0 select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [2:0] read-write SMX11SIGS_S1 select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [5:3] read-write SMX11SIGS_S2 select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [8:6] read-write SMX11SIGS_S3 select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [11:9] read-write SMX11SIGS_S4 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 [14:12] read-write SMX11FCTTABLE The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection 0x564 32 read-write 0x0 0xFFFFFFFF SMXFCT11 Sync mixer 11 function table [31:0] read-write FPDLINK0 FPD-Link Interface 0x000C0000 CTL IP Control register for FPDLink 0x0 32 read-write 0x1 0x80000001 PD_TX Power down bit, when high all blocks inside the FPDLink block shall be powered down [0:0] read-write FPDLINK_POWER_DOWN Power down FPDLink, this is the default reset value 1 FPDLINK_POWER_UP Power up FPDLink 0 ENABLED Enable bit for FPDLink [31:31] read-write DIS Disable the entire mxvideoss_fpdlink 0 EN Enable FPDLink 1 CMD IP Command register for FPDLink 0x4 32 read-write 0x0 0x1 LVDS_TX_EN Enable the serializers and TX drivers for all lanes of FPDLink [0:0] read-write FPDLINK_TX_DRIVER_DISABLED Disable FPDLink TX operation 0 FPDLINK_TX_DRIVER_ENABLED Enable FPDLink TX operation 1 CLK_GEN_CMD Control register for CLK_GEN 0x8 32 read-write 0x0 0x1 MODE8 Enable Dual-Pixel (8-Lane Mode) [0:0] read-write MODE4 4 Lane LVDS mode 0 MODE8 8 lane LVDS mode 1 CLK_GEN_CTL Configuration register for CKGEN 0xC 32 read-write 0x0 0x1137733 FRANGE Control Output frequency divider, connects to the port CO on the hardIP [1:0] read-write DIV1 Internal PLL output divider programmed to 1 0 DIV2 Internal PLL output divider programmed to 2 1 DIV4 Internal PLL output divider programmed to 4 2 DIV8 Internal PLL output divider programmed to 8 3 LFCTRL Loop filter resistance selection used for low bandwidth feature [5:4] read-write DIV1 Default bandwidth as per specification 0 DIV2 Intermediate bandwidth setting lower than default bandwidth (higher than 0x2 setting) 1 DIV4 Intermediate bandwidth setting higher than 800kHz (lower than 0x01 setting) 2 DIV8 Less than 800kHz 3 CA Driver output current control bits [10:8] read-write 2P4MA Driver output current is 2.4mA 0 2P72MA Driver output current is 2.72mA 1 2P88MA Driver output current is 2.88mA 2 3P2MA Driver output current is 3.2mA 3 3P36MA Driver output current is 3.36ma, this is the default value to be programmed 4 3P68MA Driver output current is 3.68mA 5 3P84MA Driver output current is 3.84mA 6 4P32MA Driver output current is 4.32mA 7 CCM Common mode voltage control bits. [14:12] read-write 1P05 Common mode voltage set to 1.05 0 1P10 Common mode voltage set to 1.10 1 1P15 Common mode voltage set to 1.15 2 1P20 Common mode voltage set to 1.20 3 1P25 Common mode voltage set to 1.25, this is the default value to be programmed 4 1P30 Common mode voltage set to 1.30 5 1P35 Common mode voltage set to 1.35 6 1P40 Common mode voltage set to 1.40 7 CN Control N divider used for low bandwidth feature [17:16] read-write DIV1 Default bandwidth as per specification 0 DIV2 Intermediate bandwidth setting lower than default bandwidth (higher than 0x2 setting) 1 DIV4 Intermediate bandwidth setting higher than 800kHz (lower than 0x01 setting) 2 DIV8 Less than 800kHz 3 LOCK_SEL Select internal or external PLL lock [20:20] read-write INT Select Internal Lock. This is the default value 0 EXT Select External Lock 1 MSB_FIRST Controls parallel to serial transmission order of input 7-bit word [24:24] read-write LSB LSB bit is sent first 0 MSB MSB bit is sent first. This is the default value 1 CLK_GEN_STATUS Status register for CKGEN 0x10 32 read-only 0x0 0x1 PLL_LOCK Lock Detect output. Asserted when the PLL has achieved frequency lock [0:0] read-only FPDLINK1 FPD-Link Interface 0x000C8000 CTL IP Control register for FPDLink 0x0 32 read-write 0x1 0x80000001 PD_TX Power down bit, when high all blocks inside the FPDLink block shall be powered down [0:0] read-write FPDLINK_POWER_DOWN Power down FPDLink, this is the default reset value 1 FPDLINK_POWER_UP Power up FPDLink 0 ENABLED Enable bit for FPDLink [31:31] read-write DIS Disable the entire mxvideoss_fpdlink 0 EN Enable FPDLink 1 CMD IP Command register for FPDLink 0x4 32 read-write 0x0 0x1 LVDS_TX_EN Enable the serializers and TX drivers for all lanes of FPDLink [0:0] read-write FPDLINK_TX_DRIVER_DISABLED Disable FPDLink TX operation 0 FPDLINK_TX_DRIVER_ENABLED Enable FPDLink TX operation 1 CLK_GEN_CMD Control register for CLK_GEN 0x8 32 read-write 0x0 0x1 MODE8 Enable Dual-Pixel (8-Lane Mode) [0:0] read-write MODE4 4 Lane LVDS mode 0 MODE8 8 lane LVDS mode 1 CLK_GEN_CTL Configuration register for CKGEN 0xC 32 read-write 0x0 0x1137733 FRANGE Control Output frequency divider, connects to the port CO on the hardIP [1:0] read-write DIV1 Internal PLL output divider programmed to 1 0 DIV2 Internal PLL output divider programmed to 2 1 DIV4 Internal PLL output divider programmed to 4 2 DIV8 Internal PLL output divider programmed to 8 3 LFCTRL Loop filter resistance selection used for low bandwidth feature [5:4] read-write DIV1 Default bandwidth as per specification 0 DIV2 Intermediate bandwidth setting lower than default bandwidth (higher than 0x2 setting) 1 DIV4 Intermediate bandwidth setting higher than 800kHz (lower than 0x01 setting) 2 DIV8 Less than 800kHz 3 CA Driver output current control bits [10:8] read-write 2P4MA Driver output current is 2.4mA 0 2P72MA Driver output current is 2.72mA 1 2P88MA Driver output current is 2.88mA 2 3P2MA Driver output current is 3.2mA 3 3P36MA Driver output current is 3.36ma, this is the default value to be programmed 4 3P68MA Driver output current is 3.68mA 5 3P84MA Driver output current is 3.84mA 6 4P32MA Driver output current is 4.32mA 7 CCM Common mode voltage control bits. [14:12] read-write 1P05 Common mode voltage set to 1.05 0 1P10 Common mode voltage set to 1.10 1 1P15 Common mode voltage set to 1.15 2 1P20 Common mode voltage set to 1.20 3 1P25 Common mode voltage set to 1.25, this is the default value to be programmed 4 1P30 Common mode voltage set to 1.30 5 1P35 Common mode voltage set to 1.35 6 1P40 Common mode voltage set to 1.40 7 CN Control N divider used for low bandwidth feature [17:16] read-write DIV1 Default bandwidth as per specification 0 DIV2 Intermediate bandwidth setting lower than default bandwidth (higher than 0x2 setting) 1 DIV4 Intermediate bandwidth setting higher than 800kHz (lower than 0x01 setting) 2 DIV8 Less than 800kHz 3 LOCK_SEL Select internal or external PLL lock [20:20] read-write INT Select Internal Lock. This is the default value 0 EXT Select External Lock 1 MSB_FIRST Controls parallel to serial transmission order of input 7-bit word [24:24] read-write LSB LSB bit is sent first 0 MSB MSB bit is sent first. This is the default value 1 CLK_GEN_STATUS Status register for CKGEN 0x10 32 read-only 0x0 0x1 PLL_LOCK Lock Detect output. Asserted when the PLL has achieved frequency lock [0:0] read-only MIPICSI MIPICSI 0x000D0000 MIPICSI_STRUCT MIPICSI Structure 0x00000000 MIPICSI_WRAP MIPI CSI-2 D-PHY wrapper configuration and status 0x00000000 CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED Receiver enable: '0': Disabled. If a receiver is disabled, the state of the CSI-2 receiver core is initialized. Note, that MMIO registers in the core and the wrapper are accessible. Configuration of the wrapper registers should be changed only while ENABLED=0. In this state all status registers of the wrapper cannot be read. Any attempt to do so will return an error response. '1': Enabled. The CSI-2 receiver core starts its operation. Note, that CTL registers other than this ENABLED bit should not be changed in this state. It can take up to 10 cycles of selected ESC clock until wrapper status registers can be read after changing ENABLED to '1'. Note: For using MIPI a running VIDEOSS clock is required. Ensure also that VIDEOSS0_VIDEOSSCFG_IPCTRL:CTLENABLED=0x1. [31:31] read-write DPHY_CTL D-PHY Control 0x4 32 read-write 0x30101 0x70101 PD_DPHY D-PHY power down: '1': PHY is in power down. '0': PHY is in operation. [0:0] read-write AUTO_PD_EN Powers down inactive lanes reported by CFG_NUM_LANES input bus. 1'b0: inactive lanes are powered up and driving LP11. 1'b1: inactive lanes are powered down (Hi-Z). [8:8] read-write CONT_CLK_MODE Enables the slave clock lane feature to maintain HS reception state during continuous clock mode operation. 1'b1: Feature enabled 1'b0: Feature disabled Detail: This bit enables an advanced feature in continues clock mode operation. If the CSI link was configured to continuous clock mode, the master clock lane sends HS entry command only once and remains in HS mode. In such case, if the slave clock lane got accidentally out of HS (For example: ESD on CKP/CKN lines caused LP11 level) the master side will not sense such a disruption and will continue sending packets. Having slave clock lane out of HS mode, all packets will be not be received. Setting CONT_CLK_MODE pin to 1'b1, will help getting the slave clock lane back into HS mode, without receiving a new HS entry command from the master clock lane. It will basically rely on the fact that slave data lanes will receive HS entry command per every burst. If you think that such a feature is not required, you can set this bit to 1'b0. [16:16] read-write HSEL High Speed Select. 1'b0: up to 1.0 Gbps operation 1'b1: above 1.0 Gbps operation [17:17] read-write ENP_DESER To override the deserializer token detector and enable token detection in CIL. 1'b1: Sync token detection in the CIL. 1'b0: Sync token detection in the hard macro. For characterization and debug, we can disable this feature and enable it in the CIL (can be set to '1' for INT_LB, HSRX_SEQ and HSRX tests). With ENP_DESER=1 every lane operates independent, with ENP_DESER=0 all lanes at RX side will depend on lane 0 (default for CSI application). Note: Internal loopback test (INT_LB) shall use ENP_DESER=1. [18:18] read-write CLOCK_CTL Clock Control 0x8 32 read-write 0x0 0x301 ESC_SEL Escape Clock Select. '0': clk_video '1': clk_sys (clk_slow in videoss) [0:0] read-write ESC_DIV Escape Clock Divider. '00': divide by 1 '01': divide by 2 '10': divide by 3 '11': divide by 4 Note: If ESC_DIV_PRESENT=0, that bits do not have an effect. [9:8] read-write CAL_CTL Calibration Control 0x40 32 read-write 0x1 0x103 RX_RCAL On-chip termination control bits for manual calibration. This setting has only an effect when NOCAL=1. 2'b00: 20 percent higher than mid-range. Highest impedance setting 2'b01: Mid-range impedance setting. 2'b10: 15 percent lower than mid-range 2'b11: 25 percent lower than mid-range. Lowest setting. [1:0] read-write NOCAL To override calibration value set by auto-calibration circuit with RX_RCAL[1:0]. 1'b0: Auto-calibration operation. 1'b1: Bypass the calibrator. Externally control the HS-RX termination resistance with RX_RCAL[1:0] [8:8] read-write CAL_STAT Calibration Status 0x44 32 read-only 0x0 0x3 CALOUT Calibrator Outputs which internally control the HS-RX resistor calibration. Exposed as outputs for monitoring purposes. 2'b00: Expected Calibrator output for fast resistor process. 2'b01: Expected Calibrator output for typical resistor process. 2'b10: Expected Calibrator output for slow resistor process. 2'b11: Expected Calibrator output for slow resistor process. When read in case CTL.ENABLED = 0, a bus error is returned. It can take up to 10 cycles of selected ESC clock until this register can be read after changing CTL.ENABLED to '1'. [1:0] read-only TMG_DATA_CTL Timing Data Lane Control 0xC0 32 read-write 0x0 0x1F1F033F S_PRG_RXHS_SETTLE Settling time to neglect transition effects for data. Ideally in the middle of the min/max range for THS-SETTLE. Depends on the bit rate (UI, unit interval time) and ESC clock period (T_ESC). PRG_RXHS_SETTLE = round (((115 ns + 8*UI) / T_ESC) - 2.5). Examples for 60 MHz ESC clock: 5: 500 Mbps and above 6: 250 Mbps 10: 80 Mbps [5:0] read-write S_PRG_HS_PREPARE N/A [9:8] read-write S_PRG_HS_ZERO N/A [20:16] read-write S_PRG_HS_TRAIL N/A [28:24] read-write TMG_CLOCK_CTL Timing Clock Lane Control 0xC4 32 read-write 0x0 0x3F013F SC_PRG_RXHS_SETTLE Settling time to neglect transition effects for clock. See TMG_DATA_CTL. [5:0] read-write SC_PRG_HS_PREPARE N/A [8:8] read-write SC_PRG_HS_ZERO N/A [21:16] read-write MIPICSI_CORE MIPICSI2 RX Core through APB interface (3PIP) 0x00000200 CFG_NUM_LANES CFG_NUM_LANES is a register within the CSI-2 RX Controller Core. 0x0 32 read-write 0x0 0xF CFG_NUM_LANES N/A [3:0] read-write CFG_CLK_LANE_EN CFG_CLK_LANE_EN is a register within the CSI-2 RX Controller Core. 0x4 32 read-write 0x0 0x1 CFG_CLK_LANE_EN Setting this bit enables the PHY clock lane. [0:0] read-write CFG_DATA_LANE_EN CFG_DATA_LANE_EN is a register within the CSI-2 RX Controller Core. 0x8 32 read-write 0x0 0xF CFG_DATA_LANE_EN Setting bits to a '1' value enabled the according data lanes of the PHY. [3:0] read-write CFG_FLUSH_COUNT CFG_FLUSH_COUNT is a register within the CSI-2 RX Controller Core. 0xC 32 read-write 0x3 0xF CFG_FLUSH_COUNT Sets the number of cycles to wait at the end of flushing out the receive data FIFOs to guarantee that the FIFOs are empty. Data from the PHY is written into the RX controller receive FIFOs at the MIPI receive rate and is read out of the receive FIFOs at the main RX controller clock rate (clk_video). Since the core clock can be much faster than the MIPI receive rate, there is a settling time for FIFO pointers to cross clock boundaries and show that the FIFO is empty. Without this settling time, the very last write could still be in the FIFO, but the RX controller assumes it has not received all the expected data because it sees the FIFO empty and signals an exit_hs_error type error. Default recommend value is 4'd3 for this input to have the RX Controller wait 4 cycles before accepting that the FIFO is empty. If the ratio between MIPI rate and core clock is 20:1 or greater, it is recommended to set this value to 4'd7 to give additional time. Larger values may be used, but if set too high, it is possible for the controller to not have enough time to finish the current packet and be ready to receive the next packet. Example: At the lowest MIPI rate of 80Mbps, the write clock frequency will be 10Mhz (80 bits / 8 bits per byte). If RX Controller main clock (clk_video) is running at 250Mhz, the ratio is 250/10 or 25:1, so CFG_FLUSH_COUNT should be set for 4'd7. [3:0] read-write CFG_BIT_ERR CFG_BIT_ERR is a register within the CSI-2 RX Controller Core. 0x10 32 read-only 0x0 0x3FF BIT_ERR N/A [9:0] read-only IRQ_STATUS IRQ_STATUS is a register within the CSI-2 RX Controller Core. 0x14 32 read-only 0x0 0xFF IRQ_STATUS N/A [7:0] read-only IRQ_ENABLE IRQ_ENABLE is a register within the CSI-2 RX Controller Core. 0x18 32 read-write 0x0 0xFF IRQ_ENABLE IRQ mask setting. Each bit in IRQ_ENABLE corresponds to each bit in IRQ_STATUS. Setting a bit in IRQ_ENABLE to 1 will prevent the corresponding bit in IRQ_STATUS from causing MIPI Rx Controller interrupt output to assert. Note: Bits 5 and 6 do not have any meaning. [7:0] read-write IRQ_CLR IRQ_CLR is a register within the CSI-2 RX Controller Core. 0x1C 32 read-write 0x0 0xFF IRQ_CLR IRQ status clear. Writing a '1' value to each bit clears the corresponding bit in IRQ_STATUS. A '0' value must be written after the '1'. No time requirement between the '1' and '0' write operations. [7:0] read-write ULPS_CLK_STATUS ULPS_CLK_STATUS is a register within the CSI-2 RX Controller Core. 0x20 32 read-only 0x0 0x1 ULPS_CLK_STATUS Status of RX Clock Lane. [0] - Clock Lane in ULPS state when 1 [0:0] read-only ULPS_STATUS ULPS_STATUS is a register within the CSI-2 RX Controller Core. 0x24 32 read-only 0x0 0xF ULPS_STATUS Status of RX D-PHY ULPS state. [0] - Data Lane 0 in ULPS state when 1 [1] - Data Lane 1 in ULPS state when 1 [2] - Data Lane 2 in ULPS state when 1 [3] - Data Lane 3 in ULPS state when 1 [3:0] read-only ULPS_CLK_MARK_STATUS ULPS_CLK_MARK_STATUS is a register within the CSI-2 RX Controller Core. 0x28 32 read-only 0x0 0x1 ULPS_CLK_MARK_STATUS Mark status of RX ULPS state. [0] - Clock Lane in Mark state when 1 [0:0] read-only ULPS_MARK_STATUS ULPS_MARK_STATUS is a register within the CSI-2 RX Controller Core. 0x2C 32 read-only 0x0 0xF ULPS_MARK_STATUS Mark status of RX D-PHY ULPS state. [0] - Data Lane 0 in Mark state when 1 [1] - Data Lane 1 in Mark state when 1 [2] - Data Lane 2 in Mark state when 1 [3] - Data Lane 3 in Mark state when 1 [3:0] read-only CFG_DISABLE_PAYLOAD_0 CFG_DISABLE_PAYLOAD_0 is a register within the CSI-2 RX Controller Core. 0x58 32 read-write 0x0 0xFFFFFFFF CFG_DISABLE_PAYLOAD_0 N/A [31:0] read-write CFG_DISABLE_PAYLOAD_1 CFG_DISABLE_PAYLOAD_1 is a register within the CSI-2 RX Controller Core. 0x5C 32 read-write 0x0 0x1FFFF CFG_DISABLE_PAYLOAD_1 N/A [16:0] read-write INFRA Bus infrastructure 0x000F0000 VRPU VRPU configuration. 0x00000000 RD0_CTL VRAM Protection for read master with ID=0 0x0 32 read-write 0x300 0x300 PRIO Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Masters with the same priority setting form a 'priority group'. Within a 'priority group', roundrobin arbitration is performed. [9:8] read-write RD1_CTL VRAM Protection for read master with ID=1 0x4 32 read-write 0x302 0xFFFF0303 P Privileged setting ('0': user mode; '1': privileged mode). [0:0] read-write NS Security setting ('0': secure mode; '1': non-secure mode). [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 Protection context mask for protection context '0'. This field is a constant '0'. [16:16] read-only PC_MASK_15_TO_1 Protection context mask for protection contexts '15' downto '1'. Bit PC_MASK_15_TO_1[i] indicates if the GFX_MPU_RDx RD_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': GFX_MPU_RDx RD_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': GFX_MPU_RDx RD_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies CPUSS_PROT_MPU0 MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies GFX_MPU_RDx RD_CTL.PC[3:0]). [31:17] read-write RD2_CTL VRAM Protection for read master with ID=2 0x8 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD3_CTL VRAM Protection for read master with ID=3 0xC 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD4_CTL VRAM Protection for read master with ID=4 0x10 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD5_CTL VRAM Protection for read master with ID=5 0x14 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD6_CTL VRAM Protection for read master with ID=6 0x18 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD7_CTL VRAM Protection for read master with ID=7 0x1C 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD8_CTL VRAM Protection for read master with ID=8 0x20 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD9_CTL VRAM Protection for read master with ID=9 0x24 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD10_CTL VRAM Protection for read master with ID=10 0x28 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD11_CTL VRAM Protection for read master with ID=11 0x2C 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD12_CTL VRAM Protection for read master with ID=12 0x30 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD13_CTL VRAM Protection for read master with ID=13 0x34 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD14_CTL VRAM Protection for read master with ID=14 0x38 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write RD15_CTL VRAM Protection for read master with ID=15 0x3C 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See RD1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR0_CTL VRAM Protection for write master with ID=0 0x40 32 read-write 0x300 0x300 PRIO See RD0_CTL.PRIO [9:8] read-write WR1_CTL VRAM Protection for write master with ID=1 0x44 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 Protection context mask for protection contexts '15' downto '1'. Bit PC_MASK_15_TO_1[i] indicates if the GFX_MPU_WRx WR_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': GFX_MPU_WRx WR_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': GFX_MPU_WRx WR_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies CPUSS_PROT_MPU0 MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies GFX_MPU_WRx WR_CTL.PC[3:0]). [31:17] read-write WR2_CTL VRAM Protection for write master with ID=2 0x48 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR3_CTL VRAM Protection for write master with ID=3 0x4C 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR4_CTL VRAM Protection for write master with ID=4 0x50 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR5_CTL VRAM Protection for write master with ID=5 0x54 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR6_CTL VRAM Protection for write master with ID=6 0x58 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR7_CTL VRAM Protection for write master with ID=7 0x5C 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR8_CTL VRAM Protection for write master with ID=8 0x60 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR9_CTL VRAM Protection for write master with ID=9 0x64 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR10_CTL VRAM Protection for write master with ID=10 0x68 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR11_CTL VRAM Protection for write master with ID=11 0x6C 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR12_CTL VRAM Protection for write master with ID=12 0x70 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR13_CTL VRAM Protection for write master with ID=13 0x74 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR14_CTL VRAM Protection for write master with ID=14 0x78 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write WR15_CTL VRAM Protection for write master with ID=15 0x7C 32 read-write 0x302 0xFFFF0303 P See RD1_CTL.P. [0:0] read-write NS See RD1_CTL.NS. [1:1] read-write PRIO See RD0_CTL.PRIO [9:8] read-write PC_MASK_0 See RD1_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See WR1_CTL.PC_MASK_15_TO_1. [31:17] read-write 8 64 VRPU_STRUCT[%s] VRPU structures. 0x00002000 ADDR0 VRPU region address 0 (slave structure) 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT0 VRPU region attributes 0 (slave structure) 0x4 32 read-write 0x100 0x80000100 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write ADDR1 VRPU region address 1 (master structure) 0x20 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. [7:0] read-only ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only. [31:8] read-only ATT1 VRPU region attributes 1 (master structure) 0x24 32 read-write 0x7000109 0x9F00012D UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. [0:0] read-only UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. [2:2] read-only PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. [3:3] read-only PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. [5:5] read-only NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only. [28:24] read-only PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. [31:31] read-write 16 1024 GFX_MPU_RD[%s] MPU configuration for read masters. 0x00004000 RD_CTL Memory protection context for AXI read master 0x0 32 read-write 0x0 0xF PC Active protection context. Modifications to this field are constrained by the associated RDx_CTL.PC_MASK_0 and RDx_CTL.PC_MASK_15_TO_1[] fields. [3:0] read-write 16 1024 GFX_MPU_WR[%s] MPU configuration for write masters. 0x00008000 WR_CTL Memory protection context for AXI write master 0x0 32 read-write 0x0 0xF PC Active protection context. Modifications to this field are constrained by the associated WRx_CTL.PC_MASK_0 and WRx_CTL.PC_MASK_15_TO_1[] fields. [3:0] read-write PD Power Domain and Switch Block 0x40B00000 0 1024 registers CTL Power Domain Control 0x0 32 read-write 0x0 0x3 PWR_MODE Power mode. PWR_DONE flag indicates that the programmed PWR_MODE has been reached. Do not change PWR_MODE if PWR_DONE==0. [1:0] read-write OFF Power domain is switched off. 0 RESET Power domain is in reset. 1 RETAINED Power domain is switched off, but specified state is retained. This choice behaves like OFF for domains that do not support retained state at all (RETENTION_PRESENT=0). 2 ENABLED Power domain is switched on. 3 STATUS Power Domain Status 0x10 32 read-only 0x10 0x10 PWR_DONE This flag indicates if the power mode has taken effect or not. [4:4] read-only TRIM Power Switch Trim 0x80 32 read-write 0x0 0x3 PWRSW_WAIT_CNT Divider control, specified as the number of wait cycles inserted between output clock pulses. Do not change this value while any switch is transitioning. [1:0] read-write JPEGDEC JPEGDEC 0x40B10000 0 8192 registers CTL IP control register. 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable. When the IP is disabled, no other register than this one can be accessed (results in AHB error response). 0: Disabled. 1: Enabled. [31:31] read-write HF Data fetch, store and interrupt control registers. 0x00001000 AXICTL AXI cache attributes. 0x0 32 read-write 0x0 0xF0F ARCACHE ARCACHE value of AXI transactions on Fetch Unit. Must not be changed during decoding operation. [3:0] read-write AWCACHE AWCACHE value of AXI transactions on Store Unit. Must not be changed during decoding operation. [11:8] read-write BURST AXI burst settings. 0x4 32 read-write 0x0 0x101 FETCHBURSTLENGTH Maximum burst length for Fetch Unit. Must not be changed during decoding operation. 0: Length is 4 1: Length is 8 [0:0] read-write STOREBURSTLENGTH Maximum burst length for Store Unit. Must not be changed during decoding operation. 0: Length is 4 1: Length is 8 [8:8] read-write FETCHBUF0 Source buffer configuration (JPEG). 0x10 32 read-write 0x0 0xFFFFFFFF FETCHBASEADDRESS Start address of the JPEG image in bytes. There are no alignment restrictions, however, read access to memory is 32- or 64-byte aligned, depending on configured burst length. So reading ahead of the actual start address must be allowed, if it is not aligned accordingly. RWS field, which is activated by START command. [31:0] read-write FETCHBUF1 Source buffer configuration (JPEG). 0x14 32 read-write 0x0 0x3FFFFFFF FETCHLENGTH JPEG image length in bytes. There are no alignment restrictions, however, read access to memory is 32- or 64-byte aligned, depending on the configured burst length. So reading beyond the actual end address must be allowed, if it is not aligned accordingly. RWS field, which is activated by START command. [29:0] read-write STORE0BUF0 Destination buffer configuration (Y, YUV, RGB). 0x20 32 read-write 0x0 0xFFFFFFC0 STOREBASEADDRESS0 Start address of the destination buffer 0 in multiple of 64 bytes. The destination buffer 0 holds the YUV or RGB pixels for packed format and Y pixels only for semi-planar format. RWS field, which is activated by START or RESUME command. [31:6] read-write STORE0BUF1 Destination buffer configuration (Y, YUV, RGB). 0x24 32 read-write 0x0 0xFFFFFFC0 STORESTRIDE0 Line stride of the destination buffer 0 in multiple of 64 bytes. RWS field, which is activated by START or RESUME command. [31:6] read-write STORE0BUF2 Destination buffer configuration (Y, YUV, RGB). 0x28 32 read-write 0x0 0xFFFFFFC0 STORELENGTH0 Destination buffer 0 length in multiple of 64 bytes. RWS field, which is activated by START or RESUME command. [31:6] read-write STORE1BUF0 Destination buffer configuration (UV). 0x40 32 read-write 0x0 0xFFFFFFC0 STOREBASEADDRESS1 Start address of the destination buffer 1 in multiple of 64 bytes. The destination buffer 1 holds UV pixels for semi-planar format. RWS field, which is activated by START or RESUME command. [31:6] read-write STORE1BUF1 Destination buffer configuration (UV). 0x44 32 read-write 0x0 0xFFFFFFC0 STORESTRIDE1 Line stride of the destination buffer 1 in multiple of 64 bytes.RWS field, which is activated by START or RESUME command. [31:6] read-write STORE1BUF2 Destination buffer configuration (UV). 0x48 32 read-write 0x0 0xFFFFFFC0 STORELENGTH1 Destination buffer 1 length in multiple of 64 bytes. RWS field, which is activated by START or RESUME command. [31:6] read-write STORECTL Destination buffer format settings. 0x60 32 read-write 0x0 0x1 UPSAMPLING Decoded pixels are up-sampled to YUV 4:4:4. If the sub-sampling mode in the encoded JPEG data is NOT YUV 4:2:2, YUV 4:1:1 or YUV 4:2:0, this field is ignored. RWS field, which is activated by START or RESUME command. [0:0] read-write CMD Start/Resume triggers. 0x70 32 read-write 0x0 0x101 START Writing '1' to this register will activate fetch and store related shadow configuration (RWS) and then start a new decoding operation. The following registers are initialized by this operation: ERRORSTATUS STORESTATUS FETCHSTATUS DECODINGSTATUS INTR_DEC ERRORCODE CORRECTIONCROPSTATUS SUSPEND DNL DRI (only if DECODINGOPTION.MARKERSKIP=0) All Huffman Tables (only if DECODINGOPTION.MARKERSKIP=0) [0:0] read-write RESUME Writing '1' to this register will activate store related shadow configuration (RWS) and then resume a suspended decoding operation. [8:8] read-write DECODEINTRMASK Decoder core decoding end interrupt mask. 0x80 32 read-write 0x0 0x1 DECODEINTRMASK Setting this bit to '1' propagates decoding completion status (INTR_DEC.NORMALEND/INTR_DEC.CORRECTEDEND ORed) to INTR.JPEG_CORE. [0:0] read-write INTR Interrupt status bits. 0x90 32 read-write 0x0 0x30101 FRAME_COMPLETE This interrupt occurs when Store Unit finishes storing all pixels in the destination. [0:0] read-write JPEG_CORE HW sets this field to '1' when a flag in INTR_DEC is set with corresponding propagation field enabled (DECODEINTRMASK or INTR_DEC_EN). See description of INTR_DEC_EN/DECODEINTRMASK for more detail. [8:8] read-write FETCH_ERROR HW sets this field to '1' when there is an error in the on-going AXI transaction on fetch side (i.e. when one of ERRORSTATUS fields is set). Read ERRORSTATUS to see what event set this bit. [16:16] read-write STORE_ERROR HW sets this field to '1' when there is an error in the on-going AXI transaction on store side (i.e. when one of ERRORSTATUS fields is set). Read ERRORSTATUS to see what event set this bit. [17:17] read-write INTR_SET Interrupt set bits. 0x94 32 read-write 0x0 0x30101 FRAME_COMPLETE_SET Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write JPEG_CORE_SET Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). [8:8] read-write FETCH_ERROR_SET Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). [16:16] read-write STORE_ERROR_SET Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). [17:17] read-write INTR_MASK Interrupt mask bits. 0x98 32 read-write 0x0 0x30101 FRAME_COMPLETE_MASK Mask for corresponding field in INTR register. [0:0] read-write JPEG_CORE_MASK Mask for corresponding field in INTR register. [8:8] read-write FETCH_ERROR_MASK Mask for corresponding field in INTR register. [16:16] read-write STORE_ERROR_MASK Mask for corresponding field in INTR register. [17:17] read-write INTR_MASKED Interrupt masked bits. 0x9C 32 read-only 0x0 0x30101 FRAME_COMPLETE_MASKED Logical AND of corresponding INTR and INTR_MASK fields. [0:0] read-only JPEG_CORE_MASKED Logical AND of corresponding INTR and INTR_MASK fields. [8:8] read-only FETCH_ERROR_MASKED Logical AND of corresponding INTR and INTR_MASK fields. [16:16] read-only STORE_ERROR_MASKED Logical AND of corresponding INTR and INTR_MASK fields. [17:17] read-only ERRORSTATUS Error status. 0xB0 32 read-only 0x0 0x1133 ERRORREADAXI N/A [1:0] read-only ERRORWRITEAXI N/A [5:4] read-only ERRORSTOREOVERLENGTH0 The decoded pixel data is overflowed from the region defined in StoreLength0. The decoding operation is stopped and cannot be resumed. [8:8] read-only ERRORSTOREOVERLENGTH1 The decoded pixel data is overflowed from the region defined in StoreLength1. The decoding operation is stopped and cannot be resumed. [12:12] read-only OPERATINGSTATUS Operating status. 0xB4 32 read-only 0x0 0x3030003 OPERATIONMODE N/A [1:0] read-only FETCHUNITACTIVE Fetch Unit is operating. [16:16] read-only FETCHAXIACTIVE There is an active AXI read transaction by Fetch Unit [17:17] read-only STOREUNITACTIVE Store Unit is operating. [24:24] read-only STOREAXIACTIVE There is an active AXI write transaction by Store Unit [25:25] read-only FETCHSTATUS Fetch Unit status. 0xB8 32 read-only 0x0 0x3FFFFFFF FETCHBYTES Number of total fetched bytes. [29:0] read-only STORESTATUS Store Unit status. 0xBC 32 read-only 0x0 0x3FFFFFFF STOREBYTES Number of total stored bytes (sum of both buffers in case of semi-planar formats). [29:0] read-only DEC JPEG decoder core registers. 0x00001800 IMAGEPROPERTY Image property settings. 0x0 32 read-write 0x0 0x37 SUBSAMPLE Sub-sampling mode defined in SOF marker segment 000 4:4:4 001 4:2:2 110 4:1:1 010 4:2:0 011 Gray Scale 100 CMYK 111 Invalid [2:0] read-only ENDIANSTORE N/A [4:4] read-write ENDIANFETCH N/A [5:5] read-write SWRESET Software reset trigger. 0x4 32 write-only 0x0 0x80000003 CORESTART_RSVD N/A [0:0] write-only CORERESUME_RSVD N/A [1:1] write-only CORERESET Software reset of the JPEG core. Setting this field to '1' initializes the following registers (others are retained): DECODINGSTATUS INTR_DEC ERRORCODE CORRECTIONCROPSTATUS SUSPEND DNL [31:31] write-only DECODINGSTATUS Decoding status 0x8 32 read-only 0x0 0x1 DECODINGSTATUS Decoding status. 0: Not decoding 1: Decoding [0:0] read-only QUANTTABLENO Quantization table number downloaded from the JPEG image. 0xC 32 read-only 0x0 0xFF QT1COLOR Quantization table number of 1st color component [1:0] read-only QT2COLOR Quantization table number of 2nd color component [3:2] read-only QT3COLOR Quantization table number of 3rd color component [5:4] read-only QT4COLOR Quantization table number of 4th color component [7:6] read-only HUFFMANTABLENO Huffman Table number downloaded from the JPEG image. 0x10 32 read-only 0x0 0xFFFF HTDC1COLOR DC Huffman table number of 1st color component [1:0] read-only HTAC1COLOR AC Huffman table number of 1st color component [3:2] read-only HTDC2COLOR DC Huffman table number of 2nd color component [5:4] read-only HTAC2COLOR AC Huffman table number of 2nd color component [7:6] read-only HTDC3COLOR DC Huffman table number of 3rd color component [9:8] read-only HTAC3COLOR AC Huffman table number of 3rd color component [11:10] read-only HTDC4COLOR DC Huffman table number of 4th color component [13:12] read-only HTAC4COLOR AC Huffman table number of 4th color component [15:14] read-only DRI The DRI value downloaded from the JPEG image. 0x14 32 read-only 0x0 0xFFFF DRI Value downloaded from DRI marker segment. [15:0] read-only SIZEY Y size downloaded from the JPEG image. 0x18 32 read-only 0x0 0xFFFF SIZEY Y size value downloaded from SOF marker segment. [15:0] read-only SIZEX X size downloaded from the JPEG image. 0x1C 32 read-only 0x0 0xFFFF SIZEX X size value downloaded from SOF marker segment. [15:0] read-only DECODINGOPTION Decoding option settings. 0x24 32 read-write 0x0 0xA MARKERSKIP This bit enables Marker Skip Function. 0: disable 1: enable [1:1] read-write CROP This bit enables Crop Function. 0: disable 1: enable [3:3] read-write INTR_DEC_EN Interrupt Setting 0x28 32 read-write 0x0 0x8000070F APPMARKER Setting this bit to '1' propagates the corresponding INTR_DEC bit to INTR.JPEG_CORE. [0:0] read-write COMMARKER Setting this bit to '1' propagates the corresponding INTR_DEC bit to INTR.JPEG_CORE. [1:1] read-write UNKNOWNMARKER Setting this bit to '1' propagates the corresponding INTR_DEC bit to INTR.JPEG_CORE. [2:2] read-write SIZEAVAILABLE Setting this bit to '1' propagates the corresponding INTR_DEC bit to INTR.JPEG_CORE. [3:3] read-write ERRORINTERVAL Setting this bit to '1' propagates the corresponding INTR_DEC bit to INTR.JPEG_CORE. [8:8] read-write ERRORTOTALDATA Setting this bit to '1' propagates the corresponding INTR_DEC bit to INTR.JPEG_CORE. [9:9] read-write CORRECTION This bit enables Correction Function. [10:10] read-write INTMASK This field is a global mask for the propagation of INTR_DEC bits to INTR.JPEG_CORE. This field has following polarity: 0: enable propagation 1: disable propagation [31:31] read-write INTR_DEC Interrupt status 0x2C 32 read-write 0x0 0xC000070F APPMARKER HW sets this field to '1' when an APP marker is detected in the JPEG image. [0:0] read-write COMMARKER HW sets this field to '1' when a COM marker is detected in the JPEG image. [1:1] read-write UNKNOWNMARKER HW sets this field to '1' when a marker that cannot be processed by the JPEG decoder core (markers other than SOI/SOS/DQT/DHT/DRI/RSTm/EOI/SOF0 to SOFF/APPn/COM/TEM) is detected in the JPEG image. [2:2] read-write SIZEAVAILABLE HW sets this field to '1' when the JPEG decoder core has stored the x/y size and the sub-sampling mode of the JPEG image into SizeX/SizeY registers and ImageProperty register. [3:3] read-write ERRORINTERVAL HW sets this field to '1' when the interval between RSTm markers is different from the value defined in the DRI marker segment. [8:8] read-write ERRORTOTALDATA HW sets this field to '1' when the number of data in Huffman coding segment from SOS to EOI is different from the value defined in the SOF marker segment. [9:9] read-write ERRORMARKER HW sets this field to '1' when the JPEG decoder core has stopped decoding due to a marker-related problem. Read ERRORCODE register to find what caused this bit to be set. [10:10] read-write CORRECTEDEND HW sets this field to '1' when the JPEG decoder core has finished decoding with Correction Mode taking effect. Register CORRECTIONCROPSTATUS shows more detailed status of how Correction Mode has corrected the original image. [30:30] read-write NORMALEND HW sets this field to '1' when the JPEG decoder core has finished normally. [31:31] read-write ERRORCODE Error code for INTR_DEC.ErrorMarker. 0x30 32 read-only 0x1 0x3F ERRORCODE This field indicates the cause for the error interrupt for markers (INTR_DEC.ERRORMARKER). [5:0] read-only CORRECTIONCROPSTATUS Correction Mode and Crop Decoding status. This register is initialized by the decoding start trigger (CMD.START). 0x34 32 read-only 0x0 0xFB INTERVAL Huffman coding segment data exceeding the DRI have been discarded. [0:0] read-only TOTALSIZE Pixels exceeding the total image size defined in the SOF segment have been discarded. [1:1] read-only CROPEND Crop has finished successfully. [3:3] read-only CROPSIZEERROR Crop has been cancelled due to the illegal crop region specified in CROPSTARTX/Y and CROPSIZEX/Y. When this error occurs, a normal decoding without crop is performed and flags the normal end status (INTR_DEC.NORMALEND='1') when complete. [4:4] read-only MCUUNITERROR Crop has been cancelled since the crop region specified in CROPSTARTX/Y and CROPSIZEX/Y doesn't end at the MCU boundary. When this error occurs, a normal decoding without crop is performed and flags the normal end status (INTR_DEC.NORMALEND='1') when complete. [5:5] read-only NODRI DRI marker is missing in the JPEG image. When this error occurs, a normal decoding without crop is performed and flags the normal end status (INTR_DEC.NORMALEND='1') when complete. [6:6] read-only NORST The crop region specified in CROPSTARTX/Y and CROPSIZEX/Y doesn't have a RSTm marker at the end of each line. When this error occurs, the decoding is stopped immediately, and the normal end status is flagged (INTR_DEC.NORMALEND='1'). [7:7] read-only SUSPEND Suspend status. Decoding can be resumed from Suspended State by writing '1' to CMD.RESUME. 0x38 32 read-only 0x0 0x1 SUSPEND This bit indicates whether the JPEG decoder core has been suspended due to detection of an APP/COM/unknown marker or the size/sub-sampling information in the JPEG header. 0: Not suspended 1: Suspended due to detection of an APP/COM/unknown marker or the size/sub-sampling [0:0] read-only DNL DNL value downloaded from the JPEG image. This register is initialized by the decoding start trigger (CMD.START). 0x3C 32 read-only 0x0 0xFFFF DNL DNL value defined in the marker [15:0] read-only CROPSTARTY Y crop start position 0x40 32 read-write 0x0 0xFFFF CROPSTARTY Y crop start position [15:0] read-write CROPSTARTX X crop start position 0x44 32 read-write 0x0 0xFFFF CROPSTARTX X crop start position [15:0] read-write CROPSIZEY Crop size for Y direction 0x48 32 read-write 0x0 0xFFFF CROPSIZEY Crop size for Y direction [15:0] read-write CROPSIZEX Crop size for X direction 0x4C 32 read-write 0x0 0xFFFF CROPSIZEX Crop size for X direction [15:0] read-write 32 4 QUANTTABLE0[%s] Quantization Table number 0 downloaded from a JPEG image. 0x100 32 read-only 0x0 0x0 QT0CONTENT0 An entry in Quantization Table 0 [7:0] read-only QT0CONTENT1 An entry in Quantization Table 0 [23:16] read-only 32 4 QUANTTABLE1[%s] Quantization Table number 1 downloaded from a JPEG image. 0x180 32 read-only 0x0 0x0 QT1CONTENT0 An entry in Quantization Table 1 [7:0] read-only QT1CONTENT1 An entry in Quantization Table 1 [23:16] read-only 32 4 QUANTTABLE2[%s] Quantization Table number 2 downloaded from a JPEG image. 0x200 32 read-only 0x0 0x0 QT2CONTENT0 An entry in Quantization Table 2 [7:0] read-only QT2CONTENT1 An entry in Quantization Table 2 [23:16] read-only 32 4 QUANTTABLE3[%s] Quantization Table number 3 downloaded from a JPEG image. 0x280 32 read-only 0x0 0x0 QT3CONTENT0 An entry in Quantization Table 2 [7:0] read-only QT3CONTENT1 An entry in Quantization Table 2 [23:16] read-only 4 4 HUFFMANTABLEDC0CODELENGTH[%s] Shows the code length distribution for DC Huffman Table 0. For each Huffman code lengths (0 to 16), the number of used codes is shown. e.g. Field for code length 3 has the value '5' when 010/011/100/101/110 are used. 0x300 32 read-only 0x0 0xFFFFFFFF DC0NUMCODELENGTHN Number of codes with the code length of n (n=1~16) in DC Huffman Table 0. [31:0] read-only 3 4 HUFFMANTABLEDC0GROUPNO[%s] Shows the group numbers in the order of descending appearance frequencies for DC Huffman Table 0. 0x310 32 read-only 0xF0F0F0F 0xFFFFFFFF DC0GROUPNO Shows the group numbers in the order of descending appearance frequencies for DC Huffman Table 0. [31:0] read-only 4 4 HUFFMANTABLEAC0CODELENGTH[%s] Shows the code length distribution for AC Huffman Table 0. For each Huffman code lengths (0 to 16), the number of used codes is shown. e.g. Field for code length 3 has the value '5' when 010/011/100/101/110 are used. 0x320 32 read-only 0x0 0xFFFFFFFF AC0NUMCODELENGTHN Number of codes with the code length of n (n=1~16) in AC Huffman Table 0. [31:0] read-only 41 4 HUFFMANTABLEAC0GROUPNO[%s] Shows the zero run-length+group number values in the order of descending appearance frequencies for AC Huffman Table 0. 0x330 32 read-only 0xFFFFFFFF 0xFFFFFFFF AC0GROUPNO Shows the zero run-length+group number values in the order of descending appearance frequencies for AC Huffman Table 0. Note: For the last word (offset 0x3D0), only upper half-word is used. Its default value is 0xFFFF0000. [31:0] read-only 4 4 HUFFMANTABLEDC1CODELENGTH[%s] Shows the code length distribution for DC Huffman Table 1. For each Huffman code lengths (0 to 16), the number of used codes is shown. e.g. Field for code length 3 has the value '5' when 010/011/100/101/110 are used. 0x414 32 read-only 0x0 0xFFFFFFFF DC1NUMCODELENGTHN Number of codes with the code length of n (n=1~16) in DC Huffman Table 1. [31:0] read-only 3 4 HUFFMANTABLEDC1GROUPNO[%s] Shows the group numbers in the order of descending appearance frequencies for DC Huffman Table 1. 0x424 32 read-only 0xF0F0F0F 0xFFFFFFFF DC1GROUPNO Shows the group numbers in the order of descending appearance frequencies for DC Huffman Table 1. [31:0] read-only 4 4 HUFFMANTABLEAC1CODELENGTH[%s] Shows the code length distribution for AC Huffman Table 1. For each Huffman code lengths (0 to 16), the number of used codes is shown. e.g. Field for code length 3 has the value '5' when 010/011/100/101/110 are used. 0x434 32 read-only 0x0 0xFFFFFFFF AC1NUMCODELENGTHN Number of codes with the code length of n (n=1~16) in AC Huffman Table 1. [31:0] read-only 41 4 HUFFMANTABLEAC1GROUPNO[%s] Shows the zero run-length+group number values in the order of descending appearance frequencies for AC Huffman Table 1. 0x444 32 read-only 0xFFFFFFFF 0xFFFFFFFF AC1GROUPNO Shows the zero run-length+group number values in the order of descending appearance frequencies for AC Huffman Table 1. Note: For the last word (offset 0x4E4), only upper half-word is used. Its default value is 0xFFFF0000. [31:0] read-only