Cypress Semiconductor Cypress tviibe2m TVIIBE2M 1.0 TVIIBE2M (c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company)\n or an affiliate of Cypress Semiconductor Corporation.\n \n SPDX-License-Identifier: Apache-2.0\n \n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n \n http://www.apache.org/licenses/LICENSE-2.0\n \n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an "AS IS" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License. CM4 r0p1 little true true 1 3 0 8 32 0x00000000 0xFFFFFFFF PERI Peripheral interconnect 0x40000000 0 65536 registers TIMEOUT_CTL Timeout control 0x200 32 read-write 0xFFFF 0xFFFF TIMEOUT This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. [15:0] read-write TR_CMD Trigger command 0x220 32 read-write 0x0 0xE0001FFF TR_SEL Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. [7:0] read-write GROUP_SEL Specifies the trigger group: '0'-'15': trigger multiplexer groups. '16'-'31': trigger 1-to-1 groups. [12:8] read-write TR_EDGE Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. '1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. [29:29] read-write OUT_SEL Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. Note: this field is not used for trigger 1-to-1 groups. [30:30] read-write ACTIVATE SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. Note: when ACTIVATE is '1', SW should not modify the other register fields. SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write. [31:31] read-write DIV_CMD Divider command 0x400 32 read-write 0x3FF03FF 0xC3FF03FF DIV_SEL (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. [7:0] read-write TYPE_SEL Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [9:8] read-write PA_DIV_SEL (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. [23:16] read-write PA_TYPE_SEL Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [25:24] read-write DISABLE Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. [30:30] read-write ENABLE Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. [31:31] read-write 256 4 CLOCK_CTL[%s] Clock control 0xC00 32 read-write 0x3FF 0x3FF DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. [7:0] read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [9:8] read-write 256 4 DIV_8_CTL[%s] Divider control (for 8.0 divider) 0x1000 32 read-write 0x0 0xFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write 256 4 DIV_16_CTL[%s] Divider control (for 16.0 divider) 0x1400 32 read-write 0x0 0xFFFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 256 4 DIV_16_5_CTL[%s] Divider control (for 16.5 divider) 0x1800 32 read-write 0x0 0xFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 255 4 DIV_24_5_CTL[%s] Divider control (for 24.5 divider) 0x1C00 32 read-write 0x0 0xFFFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [31:8] read-write ECC_CTL ECC control 0x2000 32 read-write 0x10000 0xFF0507FF WORD_ADDR Specifies the word address where the parity is injected. - On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [10:0] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_INJ_EN Enable error injection for PERI protection structure SRAM. When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. [18:18] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:24] read-write 10 32 GR[%s] Peripheral group structure 0x00004000 CLOCK_CTL Clock control 0x0 32 read-write 0x0 0xFF00 INT8_DIV Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write SL_CTL Slave control 0x10 32 read-write 0xFFFF 0xFFFFFFFF ENABLED_0 Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [0:0] read-write ENABLED_1 Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [1:1] read-write ENABLED_2 N/A [2:2] read-write ENABLED_3 N/A [3:3] read-write ENABLED_4 N/A [4:4] read-write ENABLED_5 N/A [5:5] read-write ENABLED_6 N/A [6:6] read-write ENABLED_7 N/A [7:7] read-write ENABLED_8 N/A [8:8] read-write ENABLED_9 N/A [9:9] read-write ENABLED_10 N/A [10:10] read-write ENABLED_11 N/A [11:11] read-write ENABLED_12 N/A [12:12] read-write ENABLED_13 N/A [13:13] read-write ENABLED_14 N/A [14:14] read-write ENABLED_15 N/A [15:15] read-write DISABLED_0 Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However, once set to 1, this bit cannot be changed back to 0 anymore. [16:16] read-write DISABLED_1 N/A [17:17] read-write DISABLED_2 N/A [18:18] read-write DISABLED_3 N/A [19:19] read-write DISABLED_4 N/A [20:20] read-write DISABLED_5 N/A [21:21] read-write DISABLED_6 N/A [22:22] read-write DISABLED_7 N/A [23:23] read-write DISABLED_8 N/A [24:24] read-write DISABLED_9 N/A [25:25] read-write DISABLED_10 N/A [26:26] read-write DISABLED_11 N/A [27:27] read-write DISABLED_12 N/A [28:28] read-write DISABLED_13 N/A [29:29] read-write DISABLED_14 N/A [30:30] read-write DISABLED_15 N/A [31:31] read-write 11 1024 TR_GR[%s] Trigger group 0x00008000 256 4 TR_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x13FF TR_SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. [7:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write 11 1024 TR_1TO1_GR[%s] Trigger 1-to-1 group 0x0000C000 256 4 TR_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x1301 TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. [0:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write PERI_MS Peripheral interconnect, master interface 0x40010000 0 65536 registers 16 64 PPU_PR[%s] Programmable protection structure pair 0x00000000 SL_ADDR Slave region, base address 0x0 32 read-write 0x0 0x0 ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. [31:2] read-write SL_SIZE Slave region, size 0x4 32 read-write 0x0 0x80000000 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. [31:31] read-write SL_ATT0 Slave attributes 0 0x10 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-write PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-write PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-write PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-write PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-write PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-write PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write SL_ATT1 Slave attributes 1 0x14 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-write PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-write PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-write PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-write PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-write PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-write PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-write PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-write PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write SL_ATT2 Slave attributes 2 0x18 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-write PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-write PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-write PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-write PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-write PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-write PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-write PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-write PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-write PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-write PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-write PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-write PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-write PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-write PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-write PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-write PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write MS_ADDR Master region, base address 0x20 32 read-only 0x0 0xFFFFFFC0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. [31:6] read-only MS_SIZE Master region, size 0x24 32 read-only 0x85000000 0x9F000000 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. [28:24] read-only VALID Master region enable: '1': Enabled. [31:31] read-only MS_ATT0 Master attributes 0 0x30 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-only PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-only PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-only PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-only PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-only PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-only PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write MS_ATT1 Master attributes 1 0x34 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-only PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-only PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-only PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-only PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-only PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-only PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-only PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-only PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write MS_ATT2 Master attributes 2 0x38 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-only PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-only PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-only PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-only PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-only PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-only PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-only PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-only PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write MS_ATT3 Master attributes 3 0x3C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-only PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-only PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-only PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-only PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-only PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-only PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-only PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-only PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write 487 64 PPU_FX[%s] Fixed protection structure pair 0x00000800 SL_ADDR Slave region, base address 0x0 32 read-only 0x0 0xFFFFFFFC ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. [31:2] read-only SL_SIZE Slave region, size 0x4 32 read-only 0x80000000 0x9F000000 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-only VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. [31:31] read-only SL_ATT0 Slave attributes 0 0x10 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-write PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-write PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-write PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-write PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-write PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-write PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write SL_ATT1 Slave attributes 1 0x14 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-write PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-write PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-write PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-write PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-write PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-write PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-write PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-write PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write SL_ATT2 Slave attributes 2 0x18 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-write PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-write PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-write PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-write PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-write PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-write PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-write PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-write PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-write PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-write PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-write PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-write PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-write PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-write PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-write PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-write PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write MS_ADDR Master region, base address 0x20 32 read-only 0x0 0xFFFFFFC0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. [31:6] read-only MS_SIZE Master region, size 0x24 32 read-only 0x85000000 0x9F000000 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. [28:24] read-only VALID Master region enable: '1': Enabled. [31:31] read-only MS_ATT0 Master attributes 0 0x30 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-only PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-only PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-only PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-only PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-only PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-only PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write MS_ATT1 Master attributes 1 0x34 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-only PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-only PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-only PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-only PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-only PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-only PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-only PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-only PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write MS_ATT2 Master attributes 2 0x38 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-only PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-only PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-only PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-only PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-only PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-only PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-only PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-only PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write MS_ATT3 Master attributes 3 0x3C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-only PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-only PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-only PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-only PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-only PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-only PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-only PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-only PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write CRYPTO Cryptography component 0x40100000 0 65536 registers CTL Control 0x0 32 read-write 0x10002 0x800300F3 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'. [7:4] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_INJ_EN Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. [17:17] read-write ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. When the IP is enabled, the IP register buffer is set to '0'. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 RAM_PWR_CTL SRAM power control 0x8 32 read-write 0x3 0x3 PWR_MODE Set power mode for memory buffer SRAM. [1:0] read-write OFF See CM4_PWR_CTL 0 RSVD undefined 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 RAM_PWR_DELAY_CTL SRAM power delay control 0xC 32 read-write 0x96 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write ECC_CTL ECC control 0x10 32 read-write 0x0 0xFE001FFF WORD_ADDR Specifies the word address where the parity is injected. - On a 32-bit write access to this SRAM address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [12:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write ERROR_STATUS0 Error status 0 0x20 32 read-only 0x0 0x0 DATA32 Specifies error description information. - For INSTR_OPC_ERROR/ INSTR_CC_ERROR/ INSTR_DEV_KEY_ERROR: - Violating instruction (from instruction FIFO). - For BUS_ERROR: - Violating transfer, address. [31:0] read-only ERROR_STATUS1 Error status 1 0x24 32 read-write 0x0 0x80000000 DATA24 Specifies error description information. - For BUS_ERROR: - Violating transfer, read attribute (DATA[0]). - Violating transfer, size attribute (DATA[5:4]). '0': 8-bit transfer, '1': 16 bits transfer, '2': 32-bit transfer. [23:0] read-only IDX Error source: '0': INSTR_OPC_ERROR (instruction FIFO decoder error). '1': INSTR_CC_ERROR (instruction FIFO decoder, VU CC error). '2': BUS_ERROR (bus master interface AHB-Lite bus error). '3': TR_AP_DETECT_ERROR. '4': TR_RC_DETECT_ERROR. '5': INSTR_DEV_KEY_ERROR. '6'-'7': Undefined. [26:24] read-only VALID Specifies if ERROR_STATUS0 and ERROR_STATUS1 specify valid error information. No new error information is captured as long as VALID is '1'; i.e. the error information of the first detected error is NOT overwritten. [31:31] read-write INTR Interrupt register 0x100 32 read-write 0x0 0x3F001F INSTR_FF_LEVEL This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated. [0:0] read-write INSTR_FF_OVERFLOW This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO). [1:1] read-write TR_INITIALIZED This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized. [2:2] read-write TR_DATA_AVAILABLE This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size. [3:3] read-write PR_DATA_AVAILABLE This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value. [4:4] read-write INSTR_OPC_ERROR This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode). When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. [16:16] read-write INSTR_CC_ERROR This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions. When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. [17:17] read-write BUS_ERROR This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface. When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. [18:18] read-write TR_AP_DETECT_ERROR This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value. [19:19] read-write TR_RC_DETECT_ERROR This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value. [20:20] read-write INSTR_DEV_KEY_ERROR This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'. [21:21] read-write INTR_SET Interrupt set register 0x104 32 read-write 0x0 0x3F001F INSTR_FF_LEVEL SW writes a '1' to this field to set the corresponding field in interrupt request register. [0:0] read-write INSTR_FF_OVERFLOW SW writes a '1' to this field to set the corresponding field in interrupt request register. [1:1] read-write TR_INITIALIZED SW writes a '1' to this field to set the corresponding field in interrupt request register. [2:2] read-write TR_DATA_AVAILABLE SW writes a '1' to this field to set the corresponding field in interrupt request register. [3:3] read-write PR_DATA_AVAILABLE SW writes a '1' to this field to set the corresponding field in interrupt request register. [4:4] read-write INSTR_OPC_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [16:16] read-write INSTR_CC_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [17:17] read-write BUS_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [18:18] read-write TR_AP_DETECT_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [19:19] read-write TR_RC_DETECT_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [20:20] read-write INSTR_DEV_KEY_ERROR SW writes a '1' to this field to set the corresponding field in interrupt request register. [21:21] read-write INTR_MASK Interrupt mask register 0x108 32 read-write 0x0 0x3F001F INSTR_FF_LEVEL Mask bit for corresponding field in interrupt request register. [0:0] read-write INSTR_FF_OVERFLOW Mask bit for corresponding field in interrupt request register. [1:1] read-write TR_INITIALIZED Mask bit for corresponding field in interrupt request register. [2:2] read-write TR_DATA_AVAILABLE Mask bit for corresponding field in interrupt request register. [3:3] read-write PR_DATA_AVAILABLE Mask bit for corresponding field in interrupt request register. [4:4] read-write INSTR_OPC_ERROR Mask bit for corresponding field in interrupt request register. [16:16] read-write INSTR_CC_ERROR Mask bit for corresponding field in interrupt request register. [17:17] read-write BUS_ERROR Mask bit for corresponding field in interrupt request register. [18:18] read-write TR_AP_DETECT_ERROR Mask bit for corresponding field in interrupt request register. [19:19] read-write TR_RC_DETECT_ERROR Mask bit for corresponding field in interrupt request register. [20:20] read-write INSTR_DEV_KEY_ERROR Mask bit for corresponding field in interrupt request register. [21:21] read-write INTR_MASKED Interrupt masked register 0x10C 32 read-only 0x0 0x3F001F INSTR_FF_LEVEL Logical and of corresponding request and mask bits. [0:0] read-only INSTR_FF_OVERFLOW Logical and of corresponding request and mask bits. [1:1] read-only TR_INITIALIZED Logical and of corresponding request and mask bits. [2:2] read-only TR_DATA_AVAILABLE Logical and of corresponding request and mask bits. [3:3] read-only PR_DATA_AVAILABLE Logical and of corresponding request and mask bits. [4:4] read-only INSTR_OPC_ERROR Logical and of corresponding request and mask bits. [16:16] read-only INSTR_CC_ERROR Logical and of corresponding request and mask bits. [17:17] read-only BUS_ERROR Logical and of corresponding request and mask bits. [18:18] read-only TR_AP_DETECT_ERROR Logical and of corresponding request and mask bits. [19:19] read-only TR_RC_DETECT_ERROR Logical and of corresponding request and mask bits. [20:20] read-only INSTR_DEV_KEY_ERROR Logical and of corresponding request and mask bits. [21:21] read-only PR_LFSR_CTL0 Pseudo random LFSR control 0 0x200 32 read-write 0xD8959BC9 0xFFFFFFFF LFSR32 State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from '0'. The three PR_LFSR_CTL registers represents the state of a 32-bit, 31-bit and 29-bit LFSR. Individually, these LFSRs generate a pseudo random bit sequence that repeats itself after (2^32)-1, (2^31)-1 and (2^29)-1 bits. The numbers (2^32)-1, (2^31)-1 and (2^29)-1 are relatively prime (their greatest common denominator is '1'). The three bit sequence are combined (XOR'd) into a single bitstream to create a pseudo random bit sequence that repeats itself after ((2^32)-1) * ((2^31)-1) * ((2*29)-1) bits. The following polynomials are used: - 32-bit irreducible polynomial: x^32+x^30+x^26+x^25+1. - 31-bit irreducible polynomial: x^31+x^28+1. - 29-bit irreducible polynomial: x^29+x^27+1. [31:0] read-write PR_LFSR_CTL1 Pseudo random LFSR control 1 0x204 32 read-write 0x2BB911F8 0x7FFFFFFF LFSR31 State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0. [30:0] read-write PR_LFSR_CTL2 Pseudo random LFSR control 2 0x208 32 read-write 0x60C31B7 0x1FFFFFFF LFSR29 State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0. [28:0] read-write PR_MAX_CTL Pseudo random maximum control 0x20C 32 read-write 0xFFFFFFFF 0xFFFFFFFF DATA32 Maximum value of to be generated random number [31:0] read-write PR_CMD Pseudo random command 0x210 32 read-write 0x0 0x1 START Pseudo random command. On a generated number, HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1. [0:0] read-write PR_RESULT Pseudo random result 0x218 32 read-write 0x0 0xFFFFFFFF DATA32 Result of a pseudo random number generation operation. The resulting value DATA is in the range [0, PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated. Note that SW can write this field. This functionality can be used prevent information leakage. [31:0] read-write TR_CTL0 True random control 0 0x280 32 read-write 0x30000 0x31FFFFFF SAMPLE_CLOCK_DIV Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. 'clk_sys'. '0': sample clock is 'clk_sys'. '1': sample clock is 'clk_sys'/2. ... '255': sample clock is 'clk_sys'/256. [7:0] read-write RED_CLOCK_DIV Specifies the clock divider that is used to produce reduced bits. '0': 1 reduced bit is produced for each sample. '1': 1 reduced bit is produced for each 2 samples. ... '255': 1 reduced bit is produced for each 256 samples. The reduced bits are considered random bits and shifted into TR_RESULT0.DATA32. [15:8] read-write INIT_DELAY Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1, 255]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of '3'. Field encoding is as follows: '0': 1 sample is dropped. '1': 2 samples are dropped. ... '255': 256 samples are dropped. The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed. [23:16] read-write VON_NEUMANN_CORR Specifies if the 'von Neumann corrector' is disabled or enabled: '0': disabled. '1': enabled. The 'von Neumann corrector' post-processes the reduced bits to remove a '0' or '1' bias. The corrector operates on reduced bit pairs ('oldest bit, newest bit'): '00': no bit is produced. '01': '0' bit is produced (oldest bit). '10': '1' bit is produced (oldest bit). '11': no bit is produced. Note that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit). [24:24] read-write STOP_ON_AP_DETECT Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'): '0': Functionality is NOT stopped. '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). [28:28] read-write STOP_ON_RC_DETECT Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'): '0': Functionality is NOT stopped. '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). [29:29] read-write TR_CTL1 True random control 1 0x284 32 read-write 0x0 0x3F RO11_EN FW sets this field to '1' to enable the ring oscillator with 11 inverters. [0:0] read-write RO15_EN FW sets this field to '1' to enable the ring oscillator with 15 inverters. [1:1] read-write GARO15_EN FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters. [2:2] read-write GARO31_EN FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial. [3:3] read-write FIRO15_EN FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters. [4:4] read-write FIRO31_EN FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial. [5:5] read-write TR_CTL2 True random control 2 0x288 32 read-write 0x0 0x3F SIZE Bit size of generated random number in TR_RESULT. Legal range is in [0, 32]. [5:0] read-write TR_STATUS True random status 0x28C 32 read-only 0x0 0x1 INITIALIZED Reflects the state of the true random number generator: '0': Not initialized (TR_CTL0.INIT_DELAY has NOT passed). '1': Initialized (TR_CTL0.INIT_DELAY has passed). [0:0] read-only TR_CMD True random command 0x290 32 read-write 0x0 0x1 START True random command. On completion of the command, HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when: - A random number is generated in TR_RESULT. - All ring oscillators are off (per TR_CTL1). - A repetition count (RC) or adaptive proportion (AP) error is detected during the random number generation (INTR.TR_RC/AP_DETECT_ERROR). Note: On completion of the command, SW should check TR_CTL1 and INTR.TR_RC/AP_DETECT_ERROR to ensure that no unexpected error occurred during random number generation. [0:0] read-write TR_RESULT True random result 0x298 32 read-write 0x0 0xFFFFFFFF DATA32 Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated. Note that SW can write this field. This functionality can be used prevent information leakage. [31:0] read-write TR_GARO_CTL True random GARO control 0x2A0 32 read-write 0x0 0x7FFFFFFF POLYNOMIAL31 Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. [30:0] read-write TR_FIRO_CTL True random FIRO control 0x2A4 32 read-write 0x0 0x7FFFFFFF POLYNOMIAL31 Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. [30:0] read-write TR_MON_CTL True random monitor control 0x2C0 32 read-write 0x2 0x3 BITSTREAM_SEL Selection of the bitstream: '0': DAS bitstream. '1': RED bitstream. '2': TR bitstream. '3': Undefined. [1:0] read-write TR_MON_CMD True random monitor command 0x2C8 32 read-write 0x0 0x3 START_AP Adaptive proportion (AP) test enable: '0': Stopped. '1': Started. On a AP detection, HW sets this field to '0' and sets INTR.TR_AP_DETECT to '1. [0:0] read-write START_RC Repetition count (RC) test enable: '0': Disabled. '1': Enabled. On a RC detection, HW sets this field to '0' and sets INTR.TR_RC_DETECT to '1. [1:1] read-write TR_MON_RC_CTL True random monitor RC control 0x2D0 32 read-write 0xFF 0xFF CUTOFF_COUNT8 Cutoff count (legal range is [1, 255]): '0': Illegal. '1': 1 repetition. ... '255': 255 repetitions. [7:0] read-write TR_MON_RC_STATUS0 True random monitor RC status 0 0x2D8 32 read-only 0x0 0x1 BIT Current active bit value: '0': '0'. '1': '1'. This field is only valid when TR_MON_RC_STATUS1.REP_COUNT is NOT equal to '0'. [0:0] read-only TR_MON_RC_STATUS1 True random monitor RC status 1 0x2DC 32 read-only 0x0 0xFF REP_COUNT Number of repetitions of the current active bit counter: '0': 0 repetitions. ... '255': 255 repetitions. [7:0] read-only TR_MON_AP_CTL True random monitor AP control 0x2E0 32 read-write 0xFFFFFFFF 0xFFFFFFFF CUTOFF_COUNT16 Cutoff count (legal range is [1, 65535]). '0': Illegal. '1': 1 occurrence. ... '65535': 65535 occurrences. [15:0] read-write WINDOW_SIZE Window size (minus 1) : '0': 1 bit. ... '65535': 65536 bits. [31:16] read-write TR_MON_AP_STATUS0 True random monitor AP status 0 0x2E8 32 read-only 0x0 0x1 BIT Current active bit value: '0': '0'. '1': '1'. This field is only valid when TR_MON_AP_STATUS1.OCC_COUNT is NOT equal to '0'. [0:0] read-only TR_MON_AP_STATUS1 True random monitor AP status 1 0x2EC 32 read-only 0x0 0xFFFFFFFF OCC_COUNT Number of occurrences of the current active bit counter: '0': 0 occurrences ... '65535': 65535 occurrences [15:0] read-only WINDOW_INDEX Counter to keep track of the current index in the window (counts from '0' to TR_MON_AP_CTL.WINDOW_SIZE to '0'). [31:16] read-only STATUS Status 0x1004 32 read-only 0x0 0x80000000 BUSY Reflects the state of the IP: '0': Idle/no busy. '1': Busy: - Instruction is pending in the instruction FIFO. - Instruction is busy in a IP component (e.g. SHA1, SHA2, SHA3, DES, TDES, AES, CHACHA, ...). - Store FIFO is busy. - TR or PR command is busy. [31:31] read-only INSTR_FF_CTL Instruction FIFO control 0x1040 32 read-write 0x20000 0x30007 EVENT_LEVEL Event level. When the number of entries in the instruction FIFO is less than the amount of this field, an event is generated: - 'event' = INSTR_FF_STATUS.USED < EVENT_LEVEL. [2:0] read-write CLEAR When '1', the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. HW sets this field to '1' on when a INSTR_OPC_ERROR, INSTR_CC_ERROR or BUS_ERROR interrupt cause is activated. [16:16] read-write BLOCK This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register): '0': The write is ignored/dropped and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1'. '1': The write is blocked, resulting in AHB-Lite wait states and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1' (this cause may be masked out). The instruction is written to the FIFO as soon as a FIFO entry becomes available. The maximum time is roughly the time of the execution of the slowest/longest instruction. Note that this setting may 'lock up' /stall the CPU. When the CPU is 'locked up'/stalled it can not respond to any system interrupts. As a result, the interrupt latency is increased. Note that this may not be an issue if the associated CPU is only performing cryptography functionality, e.g. the CM0+ during boot time. [17:17] read-write INSTR_FF_STATUS Instruction FIFO status 0x1044 32 read-only 0x0 0x1000F USED Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8. [3:0] read-only EVENT Instruction FIFO event. [16:16] read-only INSTR_FF_WR Instruction FIFO write 0x1048 32 write-only 0x0 0xFFFFFFFF DATA32 Instruction or instruction operand data that is written to the instruction FIFO. [31:0] write-only LOAD0_FF_STATUS Load 0 FIFO status 0x10C0 32 read-only 0x0 0x8000001F USED5 Number of Bytes in the FIFO. The value of this field is in the range [0, 19]. [4:0] read-only BUSY Reflects the state of the FIFO: '0': FIFO load engine is idle and a new FIFO instruction can be accepted. '1': FIFO load engine is busy and NO new FIFO instruction can be accepted. [31:31] read-only LOAD1_FF_STATUS Load 1 FIFO status 0x10D0 32 read-only 0x0 0x8000001F USED5 See LOAD1_FF_STATUS.USED. [4:0] read-only BUSY See LOAD1_FF_STATUS.BUSY. [31:31] read-only STORE_FF_STATUS Store FIFO status 0x10F0 32 read-only 0x0 0x8000001F USED5 Number of Bytes in the FIFO. The value of this field is in the range [0, 16]. [4:0] read-only BUSY Reflects the state of the FIFO: '0': FIFO store engine is idle and a new FIFO instruction can be accepted (USED is '0'). '1': FIFO store engine is busy and NO new FIFO instruction can be accepted. [31:31] read-only AES_CTL AES control 0x1100 32 read-write 0x0 0x3 KEY_SIZE AES key size: '0': 128-bit key, 10 rounds AES (inverse) cipher operation. '1': 192-bit key, 12 rounds AES (inverse) cipher operation. '2': 256-bit key, 14 rounds AES (inverse) cipher operation. '3': Undefined [1:0] read-write AES128 N/A 0 AES192 N/A 1 AES256 N/A 2 RESULT Result 0x1180 32 read-write 0x0 0xFFFFFFFF DATA BLOCK_CMP operation (DATA[0]): '0': source 0 equals source 1. '1': source 0 does NOT equal source 1. CRC operation (DATA[31:0]). State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. Note that SW can write this field. This functionality can be used prevent information leakage. [31:0] read-write CRC_CTL CRC control 0x1400 32 read-write 0x0 0x101 DATA_REVERSE Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): '0': Most significant bit (bit 1) first. '1': Least significant bit (bit 0) first. [0:0] read-write REM_REVERSE Specifies whether the remainder is bit reversed (reversal is performed after XORing): '0': No. '1': Yes. [8:8] read-write CRC_DATA_CTL CRC data control 0x1410 32 read-write 0x0 0xFF DATA_XOR Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. [7:0] read-write CRC_POL_CTL CRC polynomial control 0x1420 32 read-write 0x0 0xFFFFFFFF POLYNOMIAL CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). [31:0] read-write CRC_REM_CTL CRC remainder control 0x1440 32 read-write 0x0 0xFFFFFFFF REM_XOR Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. [31:0] read-write CRC_REM_RESULT CRC remainder result 0x1448 32 read-only 0x0 0xFFFFFFFF REM Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: '0': the more significant bits (bit 31 and down) contain the remainder. '1': the less significant bits (bit 0 and up) contain the remainder. Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_REM_CTL0.REM_REVERSE and CRC_REM_CTL1.REM_XOR. [31:0] read-only VU_CTL0 Vector unit control 0 0x1480 32 read-write 0x0 0x1 ALWAYS_EXECUTE Specifies if a conditional instruction is executed or not, when its condition code evaluates to false/'0'. '0': The instruction is NOT executed. As a result, the instruction may be handled faster than when it is executed. '1': The instruction is executed, but the execution result (including status field information) is not reflected in the IP. The instruction is handled just as fast as when it is executed. Note: a conditional instruction with a condition code that evaluates to false/'0' does not affect the architectural state: VU_STATUS fields, memory or register-file data. Note: Always execution is useful to prevent/complicate differential timing and differential power attacks. [0:0] read-write VU_CTL1 Vector unit control 1 0x1484 32 read-write 0x0 0xFFFFFF00 ADDR24 Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8], VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2], a vector operand memory address VU_OPERAND_ADDR[31:0] is calculated as follows: - VU_OPERAND_ADDR[31:15] = ADDR[31:15] - VU_OPERAND_ADDR[14:8] = (ADDR[14:8] & MASK[14:8]) | (offset[14:8] & ~MASK[14:8]) - VU_OPERAND_ADDR[7:2] = offset[7:2] - VU_OPERAND_ADDR[1:0] = 0 (always word aligned) The vector unit operand memory region uses either the IP's memory buffer or system memory. For best performance, the IP's memory buffer should be used and ADDR should be set to MEM_BUFF and MASK should specify the IP memory buffer size. If a vector operand memory address is mapped on a memory hole, read accesses return a '0' and write accesses are ignored. [31:8] read-write VU_CTL2 Vector unit control 2 0x1488 32 read-write 0x7F00 0x7F00 MASK Specifies the size of the vector operand memory region. Legal values: '0b0000000': 32 KB memory region (VU_VTL1.ADDR[14:8] ignored). '0b1000000': 16 KB memory region (VU_VTL1.ADDR[13:8] ignored). '0b1100000': 8 KB memory region (VU_VTL1.ADDR[12:8] ignored). '0b1110000': 4 KB memory region (VU_VTL1.ADDR[11:8] ignored). '0b1111000': 2 KB memory region (VU_VTL1.ADDR[10:8] ignored). '0b1111100': 1 KB memory region (VU_VTL1.ADDR[9:8] ignored). '0b1111110': 512 B memory region (VU_VTL1.ADDR[8] ignored). '0b1111111': 256 B memory region. Note: the default specifies a 256 B memory region. [14:8] read-write VU_STATUS Vector unit status 0x1490 32 read-only 0x0 0xF CARRY STATUS CARRY field. [0:0] read-only EVEN STATUS EVEN field. [1:1] read-only ZERO STATUS ZERO field. [2:2] read-only ONE STATUS ONE field. [3:3] read-only 16 4 VU_RF_DATA[%s] Vector unit register-file 0x14C0 32 read-only 0x0 0xFFFFFFFF DATA32 Vector unit register-file data. A register-file register has the following layout: DATA[28:16]: data (typically used as a word offset in vector unit operand memory). DATA[12:0]: bit size minus 1. [31:0] read-only DEV_KEY_ADDR0_CTL Device key address 0 control 0x2000 32 read-write 0x0 0x80000000 VALID Specifies if the address in the associated DEV_KEY_ADDR0 is valid: '0': Address not valid; i.e. no device key specified. '1': Address valid; i.e. device key specified. Note: A LOAD_DEV_KEY instruction requires that the device key's valid field is '1'. [31:31] read-write DEV_KEY_ADDR0 Device key address 0 0x2004 32 read-write 0x0 0xFFFFFFFF ADDR32 Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5. [31:0] read-write DEV_KEY_ADDR1_CTL Device key address 1 control 0x2020 32 read-write 0x0 0x80000000 VALID See DEV_KEY_ADDR0_CTL. [31:31] read-write DEV_KEY_ADDR1 Device key address 1 control 0x2024 32 read-write 0x0 0xFFFFFFFF ADDR32 See DEV_KEY_ADDR0. [31:0] read-write DEV_KEY_STATUS Device key status 0x2080 32 read-only 0x0 0x1 LOADED Specifies if a device key is present in the IP register buffer blocks 4 and 5. HW sets this field to '1' on successful completion of a LOAD_DEV_KEY instruction. HW clears this field to '0' when a CLEAR instruction is executed (the CLEAR instruction also sets the IP register buffer to '0'). [0:0] read-only DEV_KEY_CTL0 Device key control 0 0x2100 32 read-write 0x0 0x1 ALLOWED Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory: '0': Not allowed. '1': Allowed. Note: For successful completion of a LOAD_DEV_KEY instruction, both the associated DEV_KEY_ADDR_CTL.VALID and DEV_KEY_CTL.ALLOWED fields must be '1'. On successful instruction completion, DEV_KEY_STATUS.LOADED is set to '1'. On unsuccessful completion, the instruction FIFO is cleared and the IP is locked; an Active reset or an IP reset (CTL.ENABLED), which reinitializes the IP, is required. Note: A LOAD_DEV_KEY loads the device key from memory with protection context '0'. [0:0] read-write DEV_KEY_CTL1 Device key control 1 0x2120 32 read-write 0x0 0x1 ALLOWED See DEV_KEY_CTL0. [0:0] read-write CPUSS CPU subsystem (CPUSS) 0x40200000 0 65536 registers NvicMux0 CPU User Interrupt #0 0 NvicMux1 CPU User Interrupt #1 1 NvicMux2 CPU User Interrupt #2 2 NvicMux3 CPU User Interrupt #3 3 NvicMux4 CPU User Interrupt #4 4 NvicMux5 CPU User Interrupt #5 5 NvicMux6 CPU User Interrupt #6 6 NvicMux7 CPU User Interrupt #7 7 Internal0 Internal SW Interrupt #0 8 Internal1 Internal SW Interrupt #1 9 Internal2 Internal SW Interrupt #2 10 Internal3 Internal SW Interrupt #3 11 Internal4 Internal SW Interrupt #4 12 Internal5 Internal SW Interrupt #5 13 Internal6 Internal SW Interrupt #6 14 Internal7 Internal SW Interrupt #7 15 IDENTITY Identity 0x0 32 read-only 0x0 0x0 P This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. [0:0] read-only NS This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. [1:1] read-only PC This field specifies the protection context of the transfer that reads the register. [7:4] read-only MS This field specifies the bus master identifier of the transfer that reads the register. [11:8] read-only CM4_STATUS CM4 status 0x4 32 read-only 0x13 0x13 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only PWR_DONE After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req [4:4] read-only CM4_CLOCK_CTL CM4 clock control 0x8 32 read-write 0x0 0xFF00 FAST_INT_DIV Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write CM4_CTL CM4 control 0xC 32 read-write 0x0 0x9F000000 IOC_MASK CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. [24:24] read-write DZC_MASK CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [25:25] read-write OFC_MASK CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [26:26] read-write UFC_MASK CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [27:27] read-write IXC_MASK CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. [28:28] read-write IDC_MASK CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. [31:31] read-write CM4_INT0_STATUS CM4 interrupt 0 status 0x100 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 0. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT1_STATUS CM4 interrupt 1 status 0x104 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT2_STATUS CM4 interrupt 2 status 0x108 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT3_STATUS CM4 interrupt 3 status 0x10C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT4_STATUS CM4 interrupt 4 status 0x110 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT5_STATUS CM4 interrupt 5 status 0x114 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT6_STATUS CM4 interrupt 6 status 0x118 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT7_STATUS CM4 interrupt 7 status 0x11C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_VECTOR_TABLE_BASE CM4 vector table base 0x200 32 read-write 0x0 0xFFFFFC00 ADDR22 Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. Note: the CM4 vector table is at an address that is a 1024 B multiple. [31:10] read-write 4 4 CM4_NMI_CTL[%s] CM4 NMI control 0x240 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [9:0] read-write UDB_PWR_CTL UDB power control 0x300 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Set Power mode for UDBs [1:0] read-write OFF See CM4_PWR_CTL 0 RESET See CM4_PWR_CTL 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only UDB_PWR_DELAY_CTL UDB power control 0x304 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write CM0_CTL CM0+ control 0x1000 32 read-write 0xFA050002 0xFFFF0003 SLV_STALL Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. [0:0] read-write ENABLED Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). [1:1] read-write VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM0_STATUS CM0+ status 0x1004 32 read-only 0x0 0x3 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only CM0_CLOCK_CTL CM0+ clock control 0x1008 32 read-write 0x0 0xFF00FF00 SLOW_INT_DIV Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write PERI_INT_DIV Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. [31:24] read-write CM0_INT0_STATUS CM0+ interrupt 0 status 0x1100 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 0. Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. [9:0] read-only SYSTEM_INT_VALID Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. [31:31] read-only CM0_INT1_STATUS CM0+ interrupt 1 status 0x1104 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT2_STATUS CM0+ interrupt 2 status 0x1108 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT3_STATUS CM0+ interrupt 3 status 0x110C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT4_STATUS CM0+ interrupt 4 status 0x1110 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT5_STATUS CM0+ interrupt 5 status 0x1114 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT6_STATUS CM0+ interrupt 6 status 0x1118 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT7_STATUS CM0+ interrupt 7 status 0x111C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_VECTOR_TABLE_BASE CM0+ vector table base 0x1120 32 read-write 0x0 0xFFFFFF00 ADDR24 Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. Note: the CM0+ vector table is at an address that is a 256 B multiple. [31:8] read-write 4 4 CM0_NMI_CTL[%s] CM0+ NMI control 0x1140 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [9:0] read-write CM4_PWR_CTL CM4 power control 0x1200 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF Switch CM4 off Power off, clock off, isolate, reset and no retain. 0 RESET Reset CM4 Clock off, no isolated, no retain and reset. Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. 1 RETAINED Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain. 2 ENABLED Switch CM4 on. Power on, clock on, no isolate, no reset and no retain. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM4_PWR_DELAY_CTL CM4 power control 0x1204 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write RAM0_CTL0 RAM 0 control 0x1300 32 read-write 0x30001 0x70303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_AUTO_CORRECT HW ECC autocorrect functionality: '0': Disabled. '1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. [17:17] read-write ECC_INJ_EN Enable error injection for system SRAM 0. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0. [18:18] read-write RAM0_STATUS RAM 0 status 0x1304 32 read-only 0x1 0x1 WB_EMPTY Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. '0': Write buffer NOT empty. '1': Write buffer empty. Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). [0:0] read-only 16 4 RAM0_PWR_MACRO_CTL[%s] RAM 0 power control 0x1340 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE SRAM Power mode. [1:0] read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only RAM1_CTL0 RAM 1 control 0x1380 32 read-write 0x30001 0x70303 SLOW_WS See RAM0_CTL. [1:0] read-write FAST_WS See RAM0_CTL. [9:8] read-write ECC_EN See RAM0_CTL. [16:16] read-write ECC_AUTO_CORRECT See RAM0_CTL. [17:17] read-write ECC_INJ_EN See RAM0_CTL. [18:18] read-write RAM1_STATUS RAM 1 status 0x1384 32 read-only 0x1 0x1 WB_EMPTY See RAM0_STATUS. [0:0] read-only RAM1_PWR_CTL RAM 1 power control 0x1388 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF See RAM0_PWR_MACRO_CTL. 0 RSVD undefined 1 RETAINED See RAM0_PWR_MACRO_CTL. 2 ENABLED See RAM0_PWR_MACRO_CTL. 3 VECTKEYSTAT See RAM0_PWR_MACRO_CTL. [31:16] read-only RAM2_CTL0 RAM 2 control 0x13A0 32 read-write 0x30001 0x70303 SLOW_WS See RAM0_CTL. [1:0] read-write FAST_WS See RAM0_CTL. [9:8] read-write ECC_EN See RAM0_CTL. [16:16] read-write ECC_AUTO_CORRECT See RAM0_CTL. [17:17] read-write ECC_INJ_EN See RAM0_CTL. [18:18] read-write RAM2_STATUS RAM 2 status 0x13A4 32 read-only 0x1 0x1 WB_EMPTY See RAM0_STATUS. [0:0] read-only RAM2_PWR_CTL RAM 2 power control 0x13A8 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF See RAM0_PWR_MACRO_CTL. 0 RSVD undefined 1 RETAINED See RAM0_PWR_MACRO_CTL. 2 ENABLED See RAM0_PWR_MACRO_CTL. 3 VECTKEYSTAT See RAM0_PWR_MACRO_CTL. [31:16] read-only RAM_PWR_DELAY_CTL Power up delay used for all SRAM power domains 0x13C0 32 read-write 0x96 0x3FF UP Number clock cycles (clk_slow) delay needed after power domain power up [9:0] read-write ROM_CTL ROM control 0x13C4 32 read-write 0x1 0x303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. ROM_CTL.SLOW_WS = '0' when clk_hf <=100 MHz. ROM_CTL.SLOW_WS = '1' when 100MHz < clk_hf <=clk_hf_max. Note: clk_hf_max depends on the target device. Refer datasheet. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. ROM_CTL.FAST_WS = '0' when clk_hf <= clk_hf_max. [9:8] read-write ECC_CTL ECC control 0x13C8 32 read-write 0x0 0xFFFFFFFF WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. This field needs to be written with the offset address within the memory, divided by 4. For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010. [24:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write PRODUCT_ID Product identifier and version (same as CoreSight RomTables) 0x1400 32 read-only 0x0 0xFFF FAMILY_ID Family ID. Common ID for a product family. [11:0] read-only MAJOR_REV Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) [19:16] read-only MINOR_REV Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) [23:20] read-only DP_STATUS Debug port status 0x1410 32 read-only 0x4 0x7 SWJ_CONNECTED Specifies if the SWJ debug port is connected; i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active. [0:0] read-only SWJ_DEBUG_EN Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled. [1:1] read-only SWJ_JTAG_SEL Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected. [2:2] read-only AP_CTL Access port control 0x1414 32 read-write 0x0 0x70007 CM0_ENABLE Enables the CM0 AP interface: '0': Disabled. '1': Enabled. [0:0] read-write CM4_ENABLE Enables the CM4 AP interface: '0': Disabled. '1': Enabled. [1:1] read-write SYS_ENABLE Enables the system AP interface: '0': Disabled. '1': Enabled. [2:2] read-write CM0_DISABLE Disables the CM0 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. [16:16] read-write CM4_DISABLE Disables the CM4 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. [17:17] read-write SYS_DISABLE Disables the system AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. [18:18] read-write BUFF_CTL Buffer control 0x1500 32 read-write 0x1 0x1 WRITE_BUFF Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. [0:0] read-write SYSTICK_CTL SysTick timer control 0x1600 32 read-write 0x40000147 0xC3FFFFFF TENMS Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. [23:0] read-write CLOCK_SOURCE Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. [25:24] read-write SKEW Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise. [30:30] read-write NOREF Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. [31:31] read-write MBIST_STAT Memory BIST status 0x1704 32 read-only 0x0 0x3 SFP_READY Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. [0:0] read-only SFP_FAIL Report status of the BIST run, only valid if SFP_READY=1 [1:1] read-only CAL_SUP_SET Calibration support set and read 0x1800 32 read-write 0x0 0xFFFFFFFF DATA Read without side effect, write 1 to set [31:0] read-write CAL_SUP_CLR Calibration support clear and reset 0x1804 32 read-write 0x0 0xFFFFFFFF DATA Read side effect: when read all bits are cleared, write 1 to clear a specific bit Note: no exception for the debug host, it also causes the read side effect [31:0] read-write CM0_PC_CTL CM0+ protection context control 0x2000 32 read-write 0x0 0xF VALID Valid fields for the protection context handler CM0_PCi_HANDLER registers: Bit 0: Valid field for CM0_PC0_HANDLER. Bit 1: Valid field for CM0_PC1_HANDLER. Bit 2: Valid field for CM0_PC2_HANDLER. Bit 3: Valid field for CM0_PC3_HANDLER. [3:0] read-write CM0_PC0_HANDLER CM0+ protection context 0 handler 0x2040 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. [31:0] read-write CM0_PC1_HANDLER CM0+ protection context 1 handler 0x2044 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 1 handler. [31:0] read-write CM0_PC2_HANDLER CM0+ protection context 2 handler 0x2048 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 2 handler. [31:0] read-write CM0_PC3_HANDLER CM0+ protection context 3 handler 0x204C 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 3 handler. [31:0] read-write PROTECTION Protection status 0x20C4 32 read-write 0x0 0x7 STATE Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transitions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field. [2:0] read-write TRIM_ROM_CTL ROM trim control 0x2100 32 read-write 0x0 0xFFFFFFFF TRIM N/A [31:0] read-write TRIM_RAM_CTL RAM trim control 0x2104 32 read-write 0x0 0xFFFFFFFF TRIM N/A [31:0] read-write 1023 4 CM0_SYSTEM_INT_CTL[%s] CM0+ system interrupt control 0x8000 32 read-write 0x0 0x80000000 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. [2:0] read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. [31:31] read-write 1023 4 CM4_SYSTEM_INT_CTL[%s] CM4 system interrupt control 0xA000 32 read-write 0x0 0x80000000 CPU_INT_IDX N/A [2:0] read-write CPU_INT_VALID N/A [31:31] read-write FAULT Fault structures 0x40210000 0 65536 registers 4 256 STRUCT[%s] Fault structure 0x00000000 CTL Fault control 0x0 32 read-write 0x0 0x7 TR_EN Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). [0:0] read-write OUT_EN IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. [1:1] read-write RESET_REQ_EN Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. [2:2] read-write STATUS Fault status 0xC 32 read-write 0x0 0x80000000 IDX The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. [6:0] read-write VALID Valid indication: '0': Invalid. '1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: - STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) [31:31] read-write 4 4 DATA[%s] Fault data 0x10 32 read-write 0x0 0x0 DATA Captured fault source data. Note: the DATA registers can only be written when STATUS.VALID is '0'. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. [31:0] read-write PENDING0 Fault pending 0 0x40 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. Bit 4: DMA controller MPU. ... Bit 15: DAP MPU. Bit 16: CM4 system bus MPU. Bit 17: CM4 code bus MPU (for non FLASH controller accesses). Bit 18: CM4 code bus MPU (for FLASH controller accesses). [31:0] read-only PENDING1 Fault pending 1 0x44 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 16 - 31: See STATUS register. [31:0] read-only PENDING2 Fault pending 2 0x48 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0 - 31: See STATUS register. [31:0] read-only MASK0 Fault mask 0 0x50 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 31 to 0. [31:0] read-write MASK1 Fault mask 1 0x54 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 63 to 32. [31:0] read-write MASK2 Fault mask 2 0x58 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 95 to 64. [31:0] read-write INTR Interrupt 0xC0 32 read-write 0x0 0x1 FAULT This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source data. SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). [0:0] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x1 FAULT SW writes a '1' to this field to set the corresponding field in the INTR register. [0:0] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x1 FAULT Mask bit for corresponding field in the INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x1 FAULT Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only IPC IPC 0x40220000 0 65536 registers 8 32 STRUCT[%s] IPC structure 0x00000000 ACQUIRE IPC acquire 0x0 32 read-only 0x0 0x80000000 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock. [0:0] read-only NS Secure/non-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only SUCCESS Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). [31:31] read-only RELEASE IPC release 0x4 32 write-only 0x0 0xFFFF INTR_RELEASE Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only NOTIFY IPC notification 0x8 32 write-only 0x0 0xFFFF INTR_NOTIFY This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only DATA0 IPC data 0 0xC 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write DATA1 IPC data 1 0x10 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write LOCK_STATUS IPC lock status 0x1C 32 read-only 0x0 0x80000000 P This field specifies the user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS This field specifies the secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only ACQUIRED Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. [31:31] read-only 8 32 INTR_STRUCT[%s] IPC interrupt structure 0x00001000 INTR Interrupt 0x0 32 read-write 0x0 0xFFFFFFFF RELEASE These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [15:0] read-write NOTIFY These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [31:16] read-write INTR_SET Interrupt set 0x4 32 read-write 0x0 0xFFFFFFFF RELEASE SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write NOTIFY SW writes a '1' to this field to set the corresponding field in the INTR register. [31:16] read-write INTR_MASK Interrupt mask 0x8 32 read-write 0x0 0xFFFFFFFF RELEASE Mask bit for corresponding field in the INTR register. [15:0] read-write NOTIFY Mask bit for corresponding field in the INTR register. [31:16] read-write INTR_MASKED Interrupt masked 0xC 32 read-only 0x0 0xFFFFFFFF RELEASE Logical and of corresponding request and mask bits. [15:0] read-only NOTIFY Logical and of corresponding INTR and INTR_MASK fields. [31:16] read-only PROT Protection 0x40230000 0 65536 registers SMPU SMPU 0x00000000 MS0_CTL Master 0 protection context control 0x0 32 read-write 0x303 0xFFFF0303 P Privileged setting ('0': user mode; '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities. [0:0] read-write NS Security setting ('0': secure mode; '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters. [1:1] read-write PRIO Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. [9:8] read-write PC_MASK_0 Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. [16:16] read-only PC_MASK_15_TO_1 Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). [31:17] read-write MS1_CTL Master 1 protection context control 0x4 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS2_CTL Master 2 protection context control 0x8 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS3_CTL Master 3 protection context control 0xC 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS4_CTL Master 4 protection context control 0x10 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS5_CTL Master 5 protection context control 0x14 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS6_CTL Master 6 protection context control 0x18 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS7_CTL Master 7 protection context control 0x1C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS8_CTL Master 8 protection context control 0x20 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS9_CTL Master 9 protection context control 0x24 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS10_CTL Master 10 protection context control 0x28 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS11_CTL Master 11 protection context control 0x2C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS12_CTL Master 12 protection context control 0x30 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS13_CTL Master 13 protection context control 0x34 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS14_CTL Master 14 protection context control 0x38 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS15_CTL Master 15 protection context control 0x3C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write 16 64 SMPU_STRUCT[%s] SMPU structure 0x00002000 ADDR0 SMPU region address 0 (slave structure) 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT0 SMPU region attributes 0 (slave structure) 0x4 32 read-write 0x100 0x80000100 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write ADDR1 SMPU region address 1 (master structure) 0x20 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. [7:0] read-only ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only. [31:8] read-only ATT1 SMPU region attributes 1 (master structure) 0x24 32 read-write 0x7000109 0x9F00012D UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. [0:0] read-only UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. [2:2] read-only PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. [3:3] read-only PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. [5:5] read-only NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only. [28:24] read-only PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. [31:31] read-write 16 1024 MPU[%s] MPU 0x00004000 MS_CTL Master control 0x0 32 read-write 0x0 0xF000F PC Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: * On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: IF (the new PC is the same as MS_CTL.PC) PC is not affected; PC_SAVED is not affected. ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) An AHB-Lite bus error is generated for the exception handler fetch; PC is not affected; PC_SAVED is not affected. ELSE PC = 'new PC'; PC_SAVED = PC (push operation). * On entry of any other exception/interrupt handler: PC = PC_SAVED; PC_SAVED is not affected (pop operation). Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. [3:0] read-write PC_SAVED Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. Note: this field is ONLY used by the CM0+. [19:16] read-write 127 4 MS_CTL_READ_MIR[%s] Master control read mirror 0x4 32 read-only 0x0 0xF000F PC Read-only mirror of MS_CTL.PC [3:0] read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED [19:16] read-only 8 32 MPU_STRUCT[%s] MPU structure 0x00000200 ADDR MPU region address 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT MPU region attrributes 0x4 32 read-write 0x0 0x80000000 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write FLASHC Flash controller 0x40240000 0 65536 registers FLASH_CTL Control 0x0 32 read-write 0x110000 0x77330F MAIN_WS FLASH macro main interface wait states: '0': 0 wait states. ... '15': 15 wait states [3:0] read-write MAIN_MAP Specifies mapping of FLASH macro main array. 0: Mapping A. 1: Mapping B. This field is only used when MAIN_BANK_MODE is '1' (dual bank mode). [8:8] read-write WORK_MAP Specifies mapping of FLASH macro work array. 0: Mapping A. 1: Mapping B. This field is only used when WORK_BANK_MODE is '1' (dual bank mode). [9:9] read-write MAIN_BANK_MODE Specifies bank mode of FLASH macro main array. 0: Single bank mode. 1: Dual bank mode. [12:12] read-write WORK_BANK_MODE Specifies bank mode of FLASH macro work array. 0: Single bank mode. 1: Dual bank mode. [13:13] read-write MAIN_ECC_EN Enable ECC checking for FLASH main interface: 0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled. [16:16] read-write MAIN_ECC_INJ_EN Enable error injection for FLASH main interface. When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. [17:17] read-write MAIN_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro main interface internal error. - FLASH macro main interface non-recoverable ECC error. - FLASH macro main interface recoverable ECC error. - FLASH macro main interface memory hole error. [18:18] read-write WORK_ECC_EN Enable ECC checking for FLASH work interface: 0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled. [20:20] read-write WORK_ECC_INJ_EN Enable error injection for FLASH work interface. When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. [21:21] read-write WORK_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro work interface internal error. - FLASH macro work interface non-recoverable ECC error. - FLASH macro work interface recoverable ECC error. - FLASH macro work interface memory hole error. [22:22] read-write FLASH_PWR_CTL Flash power control 0x4 32 read-write 0x3 0x3 ENABLE Controls 'enable' pin of the Flash memory. [0:0] read-write ENABLE_HV Controls 'enable_hv' pin of the Flash memory. [1:1] read-write FLASH_CMD Command 0x8 32 read-write 0x0 0x3 INV Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. [0:0] read-write BUFF_INV Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. [1:1] read-write ECC_CTL ECC control 0x2A0 32 read-write 0x0 0xFFFFFFFF WORD_ADDR Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated). [23:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. [31:24] read-write FM_SRAM_ECC_CTL0 eCT Flash SRAM ECC control 0 0x2B0 32 read-write 0x0 0xFFFFFFFF ECC_INJ_DATA 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. [31:0] read-write FM_SRAM_ECC_CTL1 eCT Flash SRAM ECC control 1 0x2B4 32 read-write 0x0 0x7F ECC_INJ_PARITY 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. [6:0] read-write FM_SRAM_ECC_CTL2 eCT Flash SRAM ECC control 2 0x2B8 32 read-only 0x0 0xFFFFFFFF CORRECTED_DATA 32-bit corrected data output of the ECC syndrome logic. [31:0] read-only FM_SRAM_ECC_CTL3 eCT Flash SRAM ECC control 3 0x2BC 32 read-write 0x1 0x111 ECC_ENABLE ECC generation/check enable for eCT Flash SRAM memory. [0:0] read-write ECC_INJ_EN eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: 1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. 2. Set the ECC_INJ_EN bit to '1'. 3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. 4. Check the corrected data in FM_SRAM_ECC_CTL2. 5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if corrupted data was written in step 1). 6. If not finished, start over at 1 with different data. [4:4] read-write ECC_TEST_FAIL Status of ECC test. 1 : ECC test failed because eCT Flash macro is busy and using the SRAM. 0: ECC was performed. [8:8] read-only CM0_CA_CTL0 CM0+ cache control 0x400 32 read-write 0xC0000001 0xC7030003 RAM_ECC_EN Enable ECC checking for cache accesses: 0: Disabled. 1: Enabled. [0:0] read-write RAM_ECC_INJ_EN Enable error injection for cache. When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address. [1:1] read-write WAY Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. [17:16] read-write SET_ADDR Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. [26:24] read-write PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. [30:30] read-write CA_EN Cache enable: 0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). 1: Enabled. [31:31] read-write CM0_CA_CTL1 CM0+ cache control 0x404 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Specifies power mode for CM0 cache. The following sequnece should be followed for turning OFF/ON the cache SRAM. Turn OFF sequence: a) Write CM0_CA_CTL0 to disable cache. b) Write CM0_CA_CTL1 to turn OFF cache SRAM. Turn ON sequence: a) Write CM0_CA_CTL1 to turn ON cache SRAM. b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. c) Write CM0_CA_CTL0 to enable cache. [1:0] read-write OFF Power OFF the CM0 cache SRAM. 0 RSVD Undefined 1 RETAINED Put CM0 cache SRAM in retained mode. 2 ENABLED Enable/Turn ON the CM0 cache SRAM. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM0_CA_CTL2 CM0+ cache control 0x408 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM0_CA_STATUS0 CM0+ cache status 0 0x440 32 read-only 0x0 0xFFFFFFFF VALID32 Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS1 CM0+ cache status 1 0x444 32 read-only 0x0 0x0 TAG Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS2 CM0+ cache status 2 0x448 32 read-only 0x0 0x0 LRU Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3. [5:0] read-only CM0_STATUS CM0+ interface status 0x460 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM0_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CM4_CA_CTL0 CM4 cache control 0x480 32 read-write 0xC0000001 0xC7030003 RAM_ECC_EN See CM0_CA_CTL. [0:0] read-write RAM_ECC_INJ_EN See CM0_CA_CTL. [1:1] read-write WAY See CM0_CA_CTL. [17:16] read-write SET_ADDR See CM0_CA_CTL. [26:24] read-write PREF_EN See CM0_CA_CTL. [30:30] read-write CA_EN See CM0_CA_CTL. [31:31] read-write CM4_CA_CTL1 CM4 cache control 0x484 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details. [1:0] read-write OFF See CM0_CA_CTL1 0 RSVD Undefined 1 RETAINED See CM0_CA_CTL1 2 ENABLED See CM0_CA_CTL1 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM4_CA_CTL2 CM4 cache control 0x488 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM4_CA_STATUS0 CM4 cache status 0 0x4C0 32 read-only 0x0 0xFFFFFFFF VALID32 See CM0_CA_STATUS0. [31:0] read-only CM4_CA_STATUS1 CM4 cache status 1 0x4C4 32 read-only 0x0 0x0 TAG See CM0_CA_STATUS1. [31:0] read-only CM4_CA_STATUS2 CM4 cache status 2 0x4C8 32 read-only 0x0 0x0 LRU See CM0_CA_STATUS2. [5:0] read-only CM4_STATUS CM4 interface status 0x4E0 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM4_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CRYPTO_BUFF_CTL Cryptography buffer control 0x500 32 read-write 0x40000000 0x40000000 PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. For eCT work Flash, prefetch will not be done. [30:30] read-write DW0_BUFF_CTL Datawire 0 buffer control 0x580 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write DW1_BUFF_CTL Datawire 1 buffer control 0x600 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write DMAC_BUFF_CTL DMA controller buffer control 0x680 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write EXT_MS0_BUFF_CTL External master 0 buffer control 0x700 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write EXT_MS1_BUFF_CTL External master 1 buffer control 0x780 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write FM_CTL_ECT Flash Macro Registers 0x0000F000 FM_CTL Flash Macro Control 0x0 32 read-write 0x0 0x8000001F FM_MODE Flash macro mode selection: d0: Read/Idle - Normal mode, read array enabled d1: Not Used - the 1st analog POR is done by enable/enable_hv d2 - POR FUR Download - Downloads critical Flash initialization data from OTP (BG, rd, redu, etc....) d3 - POR IRAM MMR Download - Downloads from OTP region the MMR / IRAM into to the 8051 RDL shadows d4 - POR SW Download - Downloads from OTP region the SW code into to the 8051 MCU SRAM d5 - POR Code_Work Prepare - Loads the Code and Work Flash MG's to be ready for user mode operation d6 - Not Used d7 - Program 32b (WORK) - Used as program confirm command for 32 (Work) bits program d8 - Program 64b (CODE) - Used as program confirm command for 64 (Code) bits program d9 - Program 256b (CODE) - Used as program confirm command for 256 (Code) bits program d10: Program Page (CODE) - Used as program confirm command for page program for Code flash d11: Not Used d12 - Sector Erase - Erase for all kinds of sectors (Code/Work/SMS) d13 - Blank check Entry (UBC) d14 - Blank Check Read 32bit (WORK) - Blank check mode d15 - Blank check Exit d16 - Not Used d17 - Erase Suspend - Suspend command to the Erase operation d18 - Erase Resume - Resume command to Erase suspended operation d19 - Not Used d20- Not Used d21- Not Used d22- Not Used d23- Not Used d24- Not Used d25- Not Used d26- Not Used d27- Not Used d28- Not Used d29- Not Used d30: Not Used d31: Not Used [4:0] read-write EMB_START '0': not active '1': starts the actual embedded operation [31:31] read-write FM_CODE_MARGIN Flash Macro Margin Mode on Code Flash 0x4 32 read-write 0x3943 0xE000FFFF MARGIN_DCS_TRIM see above table to set the DCS reference current value to be used during Margin mode. (default set to 5uS = 0x143) which gives a Margin to the Erase side. 7uA would probably be used for Margin to the PGM side [8:0] read-write MARGIN_DCS_TRIM_EN 0: internal device defaults used from Margin reads reference current 1: MARGIN_DCS_TRIM configuration is used during Margin read [9:9] read-write MARGIN_RDREG_TRIM rdreg_c trim to be used in Margin mode if enabled by MARGIN_MODE_RDREG_CHNG_EN [15:10] read-write MARGIN_PGM_ERS_B 0: ERS Margin is checked 1: PGM Margin is checked [29:29] read-write MARGIN_MODE_RDREG_CHNG_EN when set will also use the MARGIN_RDREG_TRIM from above. Default is not to use [30:30] read-write MARGIN_MODE_EN when set puts the s40ect Flash IP In Margin mode [31:31] read-write FM_ADDR Flash Macro Address 0x8 32 write-only 0x0 0xFFFFFFFF FM_ADDR Code or Work Flash Address to be used during write operations (PGM/ERS) [31:0] write-only INTR Interrupt 0x20 32 read-write 0x0 0x1 INTR Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. [0:0] read-write INTR_SET Interrupt Set 0x24 32 read-write 0x0 0x1 INTR_SET Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt Mask 0x28 32 read-write 0x0 0x1 INTR_MASK Mask for corresponding field in the INTR register [0:0] read-write INTR_MASKED Interrupt Masked 0x2C 32 read-only 0x0 0x1 INTR_MASKED Logical and of corresponding request and mask fields. [0:0] read-only ECC_OVERRIDE ECC Data In override information and control bits 0x30 32 write-only 0x0 0xC00000FF ECC_OVERRIDE_SYNDROME The override syndrome itself to be used in case one of the enables are set. It will take [7:0] in the case of Code flash and [6:0] in the case of work flash, to bypass the internal generated syndrome [7:0] write-only ECC_OVERRIDE_WORK 0: no override. Using internal ECC engine to calculate the ECC of the Work Flash [30:30] write-only ECC_OVERRIDE_CODE 0: no override. Using internal ECC engine to calculate the ECC of the Code Flash [31:31] write-only FM_DATA Flash macro data_in[31 to 0] both Code and Work Flash 0x40 32 write-only 0x0 0xFFFFFFFF FM_DATA Pgm command data in going to the internal write buffer (WBUF). [31:0] write-only BOOKMARK Bookmark register - keeps the current FW HV seq 0x64 32 read-write 0x0 0xFFFFFFFF BOOKMARK Used by FW. Keeps the Current HV cycle sequence [31:0] read-write MAIN_FLASH_SAFETY Main (Code) Flash Security enable 0x400 32 read-write 0x0 0x1 MAINFLASHWRITEENABLE '0': Main Flash embedded operations are blocked '1': Main Flash embedded operations are enabled [0:0] read-write STATUS Status read from Flash Macro 0x404 32 read-only 0x80000000 0xF800007F PGM_CODE Indicates if active PGM operation to the Code flash is taking place 0: not running 1: running [0:0] read-only PGM_WORK Indicates if active PGM operation to the Work flash is taking place 0: not running 1: running [1:1] read-only ERASE_CODE Indicates if active Erase operation to the Code flash is taking place 0: not running 1: running [2:2] read-only ERASE_WORK Indicates if active Erase operation to the Work flash is taking place 0: not running 1: running [3:3] read-only ERS_SUSPEND Indicates if Erase operation (Code/Work) is currently being suspended 0: not suspended 1: suspended [4:4] read-only BLANK_CHECK_WORK Indicates if Blank Check mode is currently running on the work flash 0: not running 1: running [5:5] read-only BLANK_CHCEK_PASS Indicates the Blank check command result is PASS (Blank) 0: Not Blank 1: Blank (PASS) [6:6] read-only POR_1B_ECC_CORRECTED Indicates internal ECC found 1b error while downloading info in POR from NVM to VM and fixed it. Valid after 2nd, 3rd and 4th POR phases (FUR, IREM & MMR, SW DOWNLOAD). If Set it is not cleaned till additional POR (rst_hf_ac_t) 0: No error 1: 1b ECC Error corrected in POR [27:27] read-only POR_2B_ECC_ERROR Indicates an internal ECC error of 2b while downloading info in POR from NVM to VM. Valid after 2nd, 3rd and 4th POR phases (FUR, IREM & MMR, SW DOWNLOAD). If Set it is not cleaned till additional POR (rst_hf_ac_t) 0: No error 1: ECC 2b Error in POR [28:28] read-only NATIVE_POR Indicates a Native Flash state (UV) or sorted one. Valid only after 2nd phase of POR (FUR DOWNLOAD). Comment: not a retained flop, therefore reset (rst_hf_act_n) puts it back to 0. If Set it is not cleaned till additional POR (rst_hf_ac_t) 0: SORTED DEVICE (Non - Native) 1: NATIVE [29:29] read-only HANG After embedded operation (pgm/erase) this flag will tell if it was successful or failed 0: PASS 1: FAIL [30:30] read-only BUSY Whenever the device is in embedded mode the RDY goes low. Should be the same as c_interrupt pin of the IP (but inverted) 1: busy in embedded 0: rdy (high also in erase suspend) [31:31] read-only WORK_FLASH_SAFETY Work Flash Security enable 0x500 32 read-write 0x0 0x1 WORKFLASHWRITEENABLE 0: Work Flash embedded operations are blocked 1: Work Flash embedded operations are enabled [0:0] read-write SRSS SRSS Core Registers (ver2) 0x40260000 0 65536 registers PWR_LVD_STATUS High Voltage / Low Voltage Detector (HVLVD) Status Register 0x40 32 read-only 0x0 0x1 HVLVD1_OUT HVLVD1 output. 0: below voltage threshold 1: above voltage threshold [0:0] read-only PWR_LVD_STATUS2 High Voltage / Low Voltage Detector (HVLVD) Status Register #2 0x44 32 read-only 0x0 0x1 HVLVD2_OUT HVLVD2 output. 0: below voltage threshold 1: above voltage threshold [0:0] read-only 16 4 CLK_DSI_SELECT[%s] Clock DSI Select Register 0x100 32 read-write 0x0 0x1F DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. [4:0] read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO0 ILO0 - Internal Low-speed Oscillator #0 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 ILO1 ILO1 - Internal Low-speed Oscillator #1, if present. 20 CLK_OUTPUT_FAST Fast Clock Output Select Register 0x140 32 read-write 0x0 0xFFF0FFF FAST_SEL0 Select signal for fast clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL0 Selects the clock path chosen by PATH_SEL0 field 5 HFCLK_SEL0 Selects the output of the HFCLK_SEL0 mux 6 SLOW_SEL0 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 7 PATH_SEL0 Selects a clock path to use in fast clock output #0 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) [7:4] read-write HFCLK_SEL0 Selects a HFCLK tree for use in fast clock output #0 [11:8] read-write FAST_SEL1 Select signal for fast clock output #1 [19:16] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL1 Selects the clock path chosen by PATH_SEL1 field 5 HFCLK_SEL1 Selects the output of the HFCLK_SEL1 mux 6 SLOW_SEL1 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 7 PATH_SEL1 Selects a clock path to use in fast clock output #1 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) [23:20] read-write HFCLK_SEL1 Selects a HFCLK tree for use in fast clock output #1 logic [27:24] read-write CLK_OUTPUT_SLOW Slow Clock Output Select Register 0x144 32 read-write 0x0 0xFF SLOW_SEL0 Select signal for slow clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO0 Internal Low Speed Oscillator (ILO0) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 ILO1 Internal Low Speed Oscillator (ILO1), if present on the product. 9 ECO_PRESCALER ECO Prescaler (ECO_PRESCALER) 10 SLOW_SEL1 Select signal for slow clock output #1 [7:4] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO0 Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 ILO1 Internal Low Speed Oscillator (ILO1), if present on the product. 9 ECO_PRESCALER ECO Prescaler (ECO_PRESCALER) 10 CLK_CAL_CNT1 Clock Calibration Counter 1 0x148 32 read-write 0x80000000 0x80FFFFFF CAL_COUNTER1 Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. [23:0] read-write CAL_COUNTER_DONE Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up [31:31] read-only CLK_CAL_CNT2 Clock Calibration Counter 2 0x14C 32 read-only 0x0 0xFFFFFF CAL_COUNTER2 Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) [23:0] read-only SRSS_INTR SRSS Interrupt Register 0x200 32 read-write 0x0 0x26 HVLVD1 Interrupt for low voltage detector HVLVD1 [1:1] read-write HVLVD2 Interrupt for low voltage detector HVLVD2 [2:2] read-write CLK_CAL Clock calibration counter is done. This field is reset during DEEPSLEEP mode. [5:5] read-write SRSS_INTR_SET SRSS Interrupt Set Register 0x204 32 read-write 0x0 0x26 HVLVD1 Set interrupt for low voltage detector HVLVD1 [1:1] read-write HVLVD2 Set interrupt for low voltage detector HVLVD2 [2:2] read-write CLK_CAL Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. [5:5] read-write SRSS_INTR_MASK SRSS Interrupt Mask Register 0x208 32 read-write 0x0 0x26 HVLVD1 Mask for low voltage detector HVLVD1 [1:1] read-write HVLVD2 Mask for low voltage detector HVLVD2 [2:2] read-write CLK_CAL Mask for clock calibration done [5:5] read-write SRSS_INTR_MASKED SRSS Interrupt Masked Register 0x20C 32 read-only 0x0 0x26 HVLVD1 Logical and of corresponding request and mask bits. [1:1] read-only HVLVD2 Logical and of corresponding request and mask bits. [2:2] read-only CLK_CAL Logical and of corresponding request and mask bits. [5:5] read-only PWR_CTL Power Mode Control 0x1000 32 read-only 0x0 0x33 POWER_MODE Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. [1:0] read-only RESET System is resetting. 0 ACTIVE At least one CPU is running. 1 SLEEP No CPUs are running. Peripherals may be running. 2 DEEPSLEEP Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. 3 DEBUG_SESSION Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) [4:4] read-only NO_SESSION No debug session active 0 SESSION_ACTIVE Debug session is active. Power modes behave differently to keep the debug session active. 1 LPM_READY Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES, HIBERNATE wakeup, or supply supervision reset than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. [5:5] read-only PWR_CTL2 Power Mode Control 2 0x1004 32 read-write 0x0 0x9F731117 LINREG_DIS Explicitly disable the linear Core Regulator. Write zero for Traveo II devices. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: Linear Core Regulator is not explicitly disabled. Hardware disables it automatically for internal sequences, including for DEEPSLEEP, HIBERNATE, and XRES low power modes. 1: Linear Core Regulator is explicitly disabled. Only use this for special cases when another source supplies vccd during ACTIVE and SLEEP modes. This setting is only legal when another source supplies vccd, but there is no special hardware protection for this case. [0:0] read-write LINREG_OK Status of the linear Core Regulator. [1:1] read-only LINREG_LPMODE Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. 1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. [2:2] read-write DPSLP_REG_DIS N/A [4:4] read-write RET_REG_DIS Disable the Retention regulator. This is only legal when another source supplies vccret, but there is no special hardware protection for this case. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: Retention Regulator is on. 1: Retention Regulator is off. [8:8] read-write NWELL_REG_DIS Disable the Nwell regulator. This is only legal when another source supplies vnwell, but there is no special hardware protection for this case. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 0: Nwell Regulator is on. 1: Nwell Regulator is off. [12:12] read-write REFV_DIS N/A [16:16] read-write REFV_OK Indicates that the normal mode of the voltage reference is ready. [17:17] read-only REFVBUF_DIS Disable the voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. [20:20] read-write REFVBUF_OK Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFVBUF_DIS=1. [21:21] read-only REFVBUF_LPMODE Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. 1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. [22:22] read-write REFI_DIS N/A [24:24] read-write REFI_OK Indicates that the current reference is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS=1. [25:25] read-only REFI_LPMODE Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. 1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. [26:26] read-write PORBOD_LPMODE Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. [27:27] read-write BGREF_LPMODE Current is reduced using a sample&hold feature. This requires ILO0 to be operating properly. This register will not set unless CLK_ILO0_CONFIG.ILO0_ENABLE==1. When changing back to continuous operation, keep ILO0 enabled for at least 5 cycles after clearing this bit to allow for internal synchronization. 0: Bandgap Reference circuits operate in higher current mode. 1: Bandgap Reference circuits operate in low power (see above for tradeoffs). [28:28] read-write PLL_LS_BYPASS Bypass level shifter inside the PLL. Unused, if no PLL is present in the product. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. [31:31] read-write PWR_HIBERNATE HIBERNATE Mode Register 0x1008 32 read-write 0x0 0xCFFEFFFF TOKEN Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. [7:0] read-write UNLOCK This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. [15:8] read-write FREEZE Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. Supply supervision is disabled during HIBERNATE mode. HIBERNATE peripherals ignore resets (excluding XRES) while FREEZE==1. [17:17] read-write MASK_HIBALARM When set, HIBERNATE will wakeup for a RTC interrupt [18:18] read-write MASK_HIBWDT When set, HIBERNATE will wakeup for WDT interrupt [19:19] read-write POLARITY_HIBPIN Each bit sets the active polarity of the corresponding wakeup pin. 0: Pin input of 0 will wakeup the part from HIBERNATE 1: Pin input of 1 will wakeup the part from HIBERNATE [23:20] read-write MASK_HIBPIN When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins. [27:24] read-write HIBERNATE_DISABLE Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. [30:30] read-write HIBERNATE Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. [31:31] read-write PWR_BUCK_CTL SIMO Buck Control Register 0x1010 32 read-write 0x5 0xC0000007 BUCK_OUT1_SEL Voltage output selection for vccbuck1 output. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V [2:0] read-write BUCK_EN Master enable for buck converter. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. [30:30] read-write BUCK_OUT1_EN Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. [31:31] read-write PWR_BUCK_CTL2 SIMO Buck Control Register 2 0x1014 32 read-write 0x0 0xC0000007 BUCK_OUT2_SEL Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V [2:0] read-write BUCK_OUT2_HW_SEL Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. [30:30] read-write BUCK_OUT2_EN Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. [31:31] read-write PWR_SSV_CTL Supply Supervision Control Register 0x1018 32 read-write 0x8080808 0x9D909D9 BODVDDD_VSEL Selects the voltage threshold for BOD on vddd. The BOD does not reliably monitor the supply during the transition. 0: vddd<2.7V 1: vddd<3.0V [0:0] read-write BODVDDD_ENABLE Enable for BOD on vddd. This cannot be disabled during normal operation. [3:3] read-write BODVDDA_VSEL Selects the voltage threshold for BOD on vdda. Ensure BODVDDA_ENABLE==0 before changing this setting to prevent false triggers. 0: vdda<2.7V 1: vdda<3.0V [4:4] read-write BODVDDA_ACTION Action taken when the BOD on vdda triggers. [7:6] read-write NOTHING No action 0 FAULT Generate a fault 1 RESET Reset the chip 2 BODVDDA_ENABLE Enable for BOD on vdda. BODVDDA_ACTION will be triggered when the BOD is disabled. If no action is desired when disabling, firmware must first write BODVDDA_ACTION=NOTHING in a separate write cycle. [8:8] read-write BODVCCD_ENABLE Enable for BOD on vccd. This cannot be disabled during normal operation. [11:11] read-write OVDVDDD_VSEL Selects the voltage threshold for OVD on vddd. The OVD does not reliably monitor the supply during the transition. 0: vddd>5.5V 1: vddd>5.0V [16:16] read-write OVDVDDD_ENABLE Enable for OVD on vddd. This cannot be disabled during normal operation. [19:19] read-write OVDVDDA_VSEL Selects the voltage threshold for OVD on vdda. Ensure OVDVDDA_ENABLE==0 before changing this setting to prevent false triggers 0: vddd>5.5V 1: vddd>5.0V [20:20] read-write OVDVDDA_ACTION Action taken when the OVD on vdda triggers. [23:22] read-write NOTHING No action 0 FAULT Generate a fault 1 RESET Reset the chip 2 OVDVDDA_ENABLE Enable for OVD on vdda. [24:24] read-write OVDVCCD_ENABLE Enable for OVD on vccd. This cannot be disabled during normal operation. [27:27] read-write PWR_SSV_STATUS Supply Supervision Status Register 0x101C 32 read-only 0x30505 0x30707 BODVDDD_OK BOD indicates vddd is ok. This will always read 1, because a detected brownout will reset the chip. [0:0] read-only BODVDDA_OK BOD indicates vdda is ok. [1:1] read-only BODVCCD_OK BOD indicates vccd is ok. This will always read 1, because a detected brownout will reset the chip. [2:2] read-only OVDVDDD_OK OVD indicates vddd is ok. This will always read 1, because a detected over-voltage condition will reset the chip. [8:8] read-only OVDVDDA_OK OVD indicates vdda is ok. [9:9] read-only OVDVCCD_OK OVD indicates vccd is ok. This will always read 1, because a detected over-over-voltage condition will reset the chip. [10:10] read-only OCD_ACT_LINREG_OK OCD indicates the current drawn from the linear Active Regulator is ok. This will always read 1, because a detected over-current condition will reset the chip. [16:16] read-only OCD_DPSLP_REG_OK OCD indicates the current drawn from the linear DeepSleep Regulator is ok. This will always read 1, because a detected over-current condition will reset the chip. [17:17] read-only PWR_LVD_CTL High Voltage / Low Voltage Detector (HVLVD) Configuration Register 0x1020 32 read-write 0x0 0x7DFFF HVLVD1_TRIPSEL Threshold selection for HVLVD1 for products. Disable the detector (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom) [3:0] read-write HVLVD1_SRCSEL Source selection for HVLVD1 [6:4] read-write VDDD Select VDDD 0 AMUXBUSA Select AMUXBUSA (VDDD branch) 1 RSVD N/A 2 VDDIO N/A 3 AMUXBUSB Select AMUXBUSB (VDDD branch) 4 HVLVD1_EN Enable HVLVD1 voltage monitor. HVLVD1 does not function during DEEPSLEEP, but it automatically returns to its configured setting after DEEPSLEEP wakeup. Do not change other HVLVD1 settings when enabled. [7:7] read-write HVLVD1_TRIPSEL_HT N/A [12:8] read-write HVLVD1_DPSLP_EN_HT Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1. [14:14] read-write HVLVD1_EN_HT Enable HVLVD1 voltage monitor. This detector monitors vddd only. Do not change other HVLVD1 settings when enabled. [15:15] read-write HVLVD1_EDGE_SEL Sets which edge(s) will trigger an action when the threshold is crossed. [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 HVLVD1_ACTION Action taken when the threshold is crossed in the programmed directions(s) [18:18] read-write INTERRUPT Generate an interrupt 0 FAULT Generate a fault 1 PWR_LVD_CTL2 High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2 0x1024 32 read-write 0x0 0x7DF00 HVLVD2_TRIPSEL_HT N/A [12:8] read-write HVLVD2_DPSLP_EN_HT Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1. [14:14] read-write HVLVD2_EN_HT Enable HVLVD2 voltage monitor. This detector monitors vddd only. Do not change other HVLVD2 settings when enabled. [15:15] read-write HVLVD2_EDGE_SEL Sets which edge(s) will trigger an action when the threshold is crossed. [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 HVLVD2_ACTION Action taken when the threshold is crossed in the programmed directions(s) [18:18] read-write INTERRUPT Generate an interrupt 0 FAULT Generate a fault 1 16 4 PWR_HIB_DATA[%s] HIBERNATE Data Register 0x1040 32 read-write 0x0 0xFFFFFFFF HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. [31:0] read-write 16 4 CLK_PATH_SELECT[%s] Clock Path Select Register 0x1200 32 read-write 0x0 0x7 PATH_MUX Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [2:0] read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 LPECO N/A 5 16 4 CLK_ROOT_SELECT[%s] Clock Root Select Register 0x1240 32 read-write 0x0 0x8000003F ROOT_MUX Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [3:0] read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 ROOT_DIV Selects predivider value for this clock root and DSI input. [5:4] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. [31:31] read-write CSV_HF Clock Supervisor (CSV) registers for Root clocks CSV_HF 0x00001400 3 16 CSV[%s] Active domain Clock Supervisor (CSV) registers CSV_HF_CSV 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0xC000FFFF STARTUP Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [15:0] read-write CSV_ACTION Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system). [30:30] read-write FAULT Do a Fault report. 0 RESET Cause a power reset. This should only be used for clk_hf0. 1 CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. A CSV error detection is reported to the Fault structure, or instead it can generate a power reset. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFFFFFFFF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [15:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [31:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFFFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [15:0] read-write CLK_SELECT Clock selection register 0x1500 32 read-write 0x0 0xFF07 LFCLK_SEL Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [2:0] read-write ILO0 ILO0 - Internal Low-speed Oscillator #0. 0 WCO WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). 1 ALTLF ALTLF - Alternate Low-Frequency Clock. Capability is product-specific 2 PILO PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. 3 ILO1 ILO1 - Internal Low-speed Oscillator #1, if present. 4 ECO_PRESCALE ECO_PRESCALE - External-Crystal Oscillator after prescaling in CLK_ECO_PRESCALE. Does not work in DEEPSLEEP or HIBERNATE modes. Intended for applications that operate in ACTIVE/SLEEP modes only. This option is only valid when an ECO present in the product. 5 PUMP_SEL N/A [11:8] read-write PUMP_DIV N/A [14:12] read-write NO_DIV N/A 0 DIV_BY_2 N/A 1 DIV_BY_4 N/A 2 DIV_BY_8 N/A 3 DIV_BY_16 N/A 4 PUMP_ENABLE N/A [15:15] read-write CLK_TIMER_CTL Timer Clock Control Register 0x1504 32 read-write 0x70000 0x80FF0301 TIMER_SEL Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [0:0] read-write IMO IMO - Internal Main Oscillator 0 HF0_DIV Select the output of the predivider configured by TIMER_HF0_DIV. 1 TIMER_HF0_DIV Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. [9:8] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. 0 DIV_BY_2 Divide HFCLK0 by 2. 1 DIV_BY_4 Divide HFCLK0 by 4. 2 DIV_BY_8 Divide HFCLK0 by 8. 3 TIMER_DIV Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. [23:16] read-write ENABLE Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled [31:31] read-write CLK_ILO0_CONFIG ILO0 Configuration 0x1508 32 read-write 0x80000000 0xC0000001 ILO0_BACKUP This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes. If backup voltage domain is implemented on the product, this bit also indicates if ILO0 should stay enabled through power-related resets on other supplies, e.g.. BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. This register is reset when the backup logic resets. 0: ILO0 turns off during XRES, HIBERNATE, and power-related resets. ILO0 configuration and trims are reset by these events. 1: ILO0 stays enabled, as described above. ILO0 configuration and trims are not reset by these events. [0:0] read-write ILO0_MON_ENABLE N/A [30:30] read-write ENABLE Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. HT-variant: This register will not clear unless PWR_CTL2.BGREF_LPMODE==0. After enabling, the first ILO0 cycle occurs within 12us and is +/-10 percent accuracy. Thereafter, ILO0 is +/-5 percent accurate. [31:31] read-write CLK_ILO1_CONFIG ILO1 Configuration 0x150C 32 read-write 0x0 0xC0000000 ILO1_MON_ENABLE N/A [30:30] read-write ENABLE Master enable for ILO1. HT-variant: After enabling, the first ILO1 cycle occurs within 12us and is +/-10 percent accuracy. Thereafter, ILO1 is +/-5 percent accurate. [31:31] read-write CLK_IMO_CONFIG IMO Configuration 0x1518 32 read-write 0x80000000 0x80000000 ENABLE Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP, HIBERNATE, and XRES. [31:31] read-write CLK_ECO_CONFIG ECO Configuration Register 0x151C 32 read-write 0x2 0x98000002 AGC_EN Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by CLK_ECO_CONFIG2.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. [1:1] read-write ECO_DIV_DISABLE ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE). SW sets this field to '1' and HW sets this field to '0'. HW sets ECO_DIV_DISABLE field to '0' immediately and HW sets CLK_ECO_PRESCALE.ECO_DIV_EN field to '0' immediately. [27:27] read-write ECO_DIV_ENABLE ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE). ECO Prescaler only works in ACTIVE and SLEEP modes. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled, its integer and fractional counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the ECO_DIV_DISABLE field. 1: Configure CLK_ECO_PRESCALE registers. 2: Enable the divider using the ECO_DIV_ENABLE field. HW sets the ECO_DIV_ENABLE field to '0' when the enabling is performed and HW set CLK_ECO_PRESCALER.ENABLED to '1' when the enabling is performed. [28:28] read-write ECO_EN Master enable for ECO oscillator. [31:31] read-write CLK_ECO_PRESCALE ECO Prescaler Configuration Register 0x1520 32 read-write 0x0 0x3FFFF01 ECO_DIV_ENABLED ECO prescaler enabled. HW sets this field to '1' as a result of an CLK_ECO_CONFIG.ECO_DIV_ENABLE command. HW sets this field to '0' as a result on a CLK_ECO_CONFIG.ECO_DIV_DISABLE command. [0:0] read-only ECO_FRAC_DIV 8-bit fractional value, sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when ECO Prescaler is enabled. [15:8] read-write ECO_INT_DIV 10-bit integer value allows for ECO frequencies up to 33.55MHz. Subtract one from the desired divide value when writing this field. For example, to divide by 1, write ECO_INT_DIV=0. Do not change this setting when ECO Prescaler is enabled. [25:16] read-write CLK_ECO_STATUS ECO Status Register 0x1524 32 read-only 0x0 0x3 ECO_OK Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. [0:0] read-only ECO_READY Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. [1:1] read-only CLK_PILO_CONFIG Precision ILO Configuration Register 0x1528 32 read-write 0x80 0xE00003FF PILO_FFREQ Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. [9:0] read-write PILO_CLK_EN Enable the PILO clock output. See PILO_EN field for required sequencing. [29:29] read-write PILO_RESET_N Reset the PILO. See PILO_EN field for required sequencing. [30:30] read-write PILO_EN Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. [31:31] read-write CLK_FLL_CONFIG FLL Configuration Register 0x1530 32 read-write 0x1000000 0x8103FFFF FLL_MULT Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) [17:0] read-write FLL_OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2 [24:24] read-write FLL_ENABLE Master enable for FLL. The FLL requires firmware sequencing when enabling and disabling. Hardware handles sequencing automatically when entering/exiting DEEPSLEEP. To enable the FLL, use the following sequence: 1) Configure FLL and CCO settings. Do not modify CLK_FLL_CONFIG3.BYPASS_SEL (must be AUTO) or CLK_FLL_CONFIG.FLL_ENABLE (must be 0). 2) Enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 3) Wait until CLK_FLL_STATUS.CCO_READY==1. 4) Ensure the reference clock has stabilized. 5) Write FLL_ENABLE=1. 6) Optionally wait until CLK_FLL_STATUS.LOCKED==1. The hardware automatically changes to the FLL output when LOCKED==1. To disable the FLL, use the following sequence: 1) Write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. 2) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional). 3) Wait at least ten cycles of either FLL reference clock or FLL output clock, whichever is slower. It is recommended to use a HW counter (e.g. clock calibration counter, event generator) running on the slower clock. 4) Disable FLL with FLL_ENABLE=0. 5) Disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. 6) Write CLK_FLL_CONFIG3.BYPASS_SEL=AUTO. 7) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional). 8) Wait three cycles of FLL reference clock. It is recommended to use a HW counter (e.g. clock calibration counter, event generator) running on the reference clock. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_CONFIG2 FLL Configuration Register 2 0x1534 32 read-write 0x20001 0xFFFF1FFF FLL_REF_DIV Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191 [12:0] read-write LOCK_TOL Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or allow less accuracy. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 255: tolerate error of 256 count values [23:16] read-write UPDATE_TOL Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings. The update tolerance is the allowed difference between the count value for the ideal formula and the measured value. UPDATE_TOL should be less than LOCK_TOL. [31:24] read-write CLK_FLL_CONFIG3 FLL Configuration Register 3 0x1538 32 read-write 0x2800 0x301FFFFF FLL_LF_IGAIN FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [3:0] read-write FLL_LF_PGAIN FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [7:4] read-write SETTLING_COUNT Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles [20:8] read-write BYPASS_SEL Bypass mux located just after FLL output. This register can be written while the FLL is enabled. When changing BYPASS_SEL, do not turn off the reference clock or CCO clock for five cycles (whichever is slower). In case of disabling FLL(FLL_ENABLE=0), additional five cycles are required. Refer to FLL disable sequence for more details in CLK_FLL_CONFIG->FLL_ENABLE. Whenever BYPASS_SEL is changed, it is required to read CLK_FLL_CONFIG3 to ensure the change takes effect. [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects FLL reference input (bypass mode). When locked, automatically selects FLL output. This can allow some processing to occur while the FLL is locking, such as after DEEPSLEEP wakeup. It is incompatible with clock supervision, because the frequency changes based on the lock signal. 0 LOCKED_OR_NOTHING Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. 1 FLL_REF Select FLL reference input (bypass mode). Ignores lock indicator 2 FLL_OUT Select FLL output. Ignores lock indicator. 3 CLK_FLL_CONFIG4 FLL Configuration Register 4 0x153C 32 read-write 0xFF 0xC1FF07FF CCO_LIMIT Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) [7:0] read-write CCO_RANGE Frequency range of CCO [10:8] read-write RANGE0 Target frequency is in range [48, 64) MHz 0 RANGE1 Target frequency is in range [64, 85) MHz 1 RANGE2 Target frequency is in range [85, 113) MHz 2 RANGE3 Target frequency is in range [113, 150) MHz 3 RANGE4 Target frequency is in range [150, 200] MHz 4 CCO_FREQ CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. [24:16] read-write CCO_HW_UPDATE_DIS Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. [30:30] read-write CCO_ENABLE Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_STATUS FLL Status Register 0x1540 32 read-write 0x0 0x7 LOCKED FLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the FLL is enabled and goes out of lock. This bit stays set until cleared by firmware. [1:1] read-write CCO_READY This indicates that the CCO is internally settled and ready to use. [2:2] read-only CLK_ECO_CONFIG2 ECO Configuration Register 2 0x1544 32 read-write 0x3 0x7FF7 WDTRIM Watch Dog Trim. Sets the minimum oscillation amplitude (Vp) for the crystal drive level. The minimum amplitude detector output is readable in CLK_ECO_STATUS.ECO_OK. 0x0: Vp > 0.05V 0x1: Vp > 0.10V 0x2: Vp > 0.15V 0x3: Vp > 0.20V 0x4: Vp > 0.25V 0x5: Vp > 0.30V 0x6: Vp > 0.35V 0x7: Vp > 0.40V [2:0] read-write ATRIM Amplitude trim. Sets maximum oscillation amplitude (Vp) to set the crystal drive level when ECO_CONFIG.AGC_EN=1. When AGC_EN=0, most values of this register are unused, except as noted. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0: Vp < 0.35V 0x1: Vp < 0.40V 0x2: Vp < 0.45V 0x3: Vp < 0.50V 0x4: Vp < 0.55V 0x5: Vp < 0.60V 0x6: Vp < 0.65V 0x7: Vp < 0.70V 0x8: Vp < 0.75V 0x9: Vp < 0.80V 0xA: Vp < 0.85V 0xB: Vp < 0.90V 0xC: Vp < 0.95V 0xD: Vp < 1.00V 0xE: Vp < 1.05V 0xF: Vp < 1.10V when AGC_EN=1. When AGC_EN=0, this setting enables maximum swing between vddd and vssd. [7:4] read-write FTRIM Filter Trim - 3rd harmonic oscillation [9:8] read-write RTRIM Feedback resistor Trim [11:10] read-write GTRIM Gain Trim - Startup time. [14:12] read-write 15 4 CLK_PLL_CONFIG[%s] PLL Configuration Register 0x1600 32 read-write 0x20116 0xBE1F1F7F FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) [6:0] read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) [12:8] read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) [20:16] read-write LOCK_DELAY N/A [26:25] read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) [27:27] read-write BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower). [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. If ENABLE=0, automatically selects PLL reference input. 0 LOCKED_OR_NOTHING Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. If ENABLE=0, no clock is output. 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. If ENABLE=0, no clock is output. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled. When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit. 1: Block is enabled [31:31] read-write 15 4 CLK_PLL_STATUS[%s] PLL Status Register 0x1640 32 read-write 0x0 0x3 LOCKED PLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. [1:1] read-write CSV_REF_SEL Select CSV Reference clock for Active domain 0x1700 32 read-write 0x0 0x7 REF_MUX Selects a source for clock clk_ref_hf. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. [2:0] read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 CSV_REF CSV registers for the CSV Reference clock CSV_REF 0x00001710 CSV Active domain Clock Supervisor (CSV) registers for CSV Reference clock CSV_REF_CSV 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0xC000FFFF STARTUP Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [15:0] read-write CSV_ACTION Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system). [30:30] read-write FAULT Do a Fault report. 0 RESET Cause a power reset. This should only be used for clk_hf0. 1 CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. A CSV error detection is reported to the Fault structure, or instead it can generate a power reset. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFFFFFFFF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [15:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [31:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFFFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [15:0] read-write CSV_LF CSV registers for LF clock CSV_LF 0x00001720 CSV LF clock Clock Supervisor registers CSV_LF_CSV 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0x800000FF STARTUP Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [7:0] read-write CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot. A CSV error detection is reported to the Fault structure. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFF00FF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [7:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [23:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [7:0] read-write CSV_ILO CSV registers for HVILO clock CSV_ILO 0x00001730 CSV ILO0 clock DeepSleep domain Clock Supervisor registers CSV_ILO_CSV 0x00000000 REF_CTL Clock Supervision Reference Control 0x0 32 read-write 0x0 0x800000FF STARTUP Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. [7:0] read-write CSV_EN Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot. A CSV error detection is reported to the Fault structure. [31:31] read-write REF_LIMIT Clock Supervision Reference Limits 0x4 32 read-write 0x0 0xFF00FF LOWER Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. [7:0] read-write UPPER Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. [23:16] read-write MON_CTL Clock Supervision Monitor Control 0x8 32 read-write 0x0 0xFF PERIOD Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks. [7:0] read-write RES_CAUSE Reset Cause Observation Register 0x1800 32 read-write 0x40000000 0x71FF01FF RESET_WDT A basic WatchDog Timer (WDT) reset has occurred since last power cycle. ULP products: This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). For products that support high-voltage cause detection, this bit blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. [0:0] read-write RESET_ACT_FAULT Fault logging system requested a reset from its Active logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [1:1] read-write RESET_DPSLP_FAULT Fault logging system requested a reset from its DeepSleep logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [2:2] read-write RESET_TC_DBGRESET Test controller or debugger asserted reset. Only resets debug domain. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [3:3] read-write RESET_SOFT A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [4:4] read-write RESET_MCWDT0 Multi-Counter Watchdog timer reset #0. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [5:5] read-write RESET_MCWDT1 Multi-Counter Watchdog timer reset #1. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [6:6] read-write RESET_MCWDT2 Multi-Counter Watchdog timer reset #2. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [7:7] read-write RESET_MCWDT3 Multi-Counter Watchdog timer reset #3. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). [8:8] read-write RESET_XRES External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. [16:16] read-write RESET_BODVDDD External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain information in the device. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [17:17] read-write RESET_BODVDDA External VDDA supply crossed the brown-out limit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [18:18] read-write RESET_BODVCCD Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions. Functional and timing supervision (CSV, WDT) is provided to create fully failsafe internal crash detection. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [19:19] read-write RESET_OVDVDDD Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [20:20] read-write RESET_OVDVDDA Overvoltage detection on the external VDDA supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [21:21] read-write RESET_OVDVCCD Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [22:22] read-write RESET_OCD_ACT_LINREG Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [23:23] read-write RESET_OCD_DPSLP_LINREG Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. [24:24] read-write RESET_PXRES PXRES triggered. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. [28:28] read-write RESET_STRUCT_XRES Structural reset was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. [29:29] read-write RESET_PORVDDD Indicator that a POR occurred. This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes. [30:30] read-write RES_CAUSE2 Reset Cause Observation Register 2 0x1804 32 read-write 0x0 0x1FFFF RESET_CSV_HF Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. [15:0] read-write RESET_CSV_REF Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources. [16:16] read-write CLK_TRIM_ILO0_CTL ILO0 Trim Register 0x3014 32 read-write 0x52C 0xF3F ILO0_FTRIM ILO0 frequency trims. LSB step size is 1.5 percent (typical) of the frequency. [5:0] read-write ILO0_MONTRIM ILO0 internal monitor trim. [11:8] read-write PWR_TRIM_PWRSYS_CTL Power System Trim Register 0x3108 32 read-write 0x17 0x1F ACT_REG_TRIM Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: 5'h07: 900mV (nominal) 5'h17: 1100mV (nominal) [4:0] read-write ACT_REG_BOOST Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default); 100mA chip: 2'b00 (default); 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. [31:30] read-write CLK_TRIM_PILO_CTL PILO Trim Register 0x3114 32 read-write 0x108500F 0x7DFF703F PILO_CFREQ Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. [5:0] read-write PILO_OSC_TRIM Trim for current in oscillator block. [14:12] read-write PILO_COMP_TRIM Trim for comparator bias current. [17:16] read-write PILO_NBIAS_TRIM Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier [19:18] read-write PILO_RES_TRIM Trim for beta-multiplier branch current [24:20] read-write PILO_ISLOPE_TRIM Trim for beta-multiplier current slope [27:26] read-write PILO_VTDIFF_TRIM Trim for VT-DIFF output (internal power supply) [30:28] read-write CLK_TRIM_PILO_CTL2 PILO Trim Register 2 0x3118 32 read-write 0xDA10E0 0xFF1FFF PILO_VREF_TRIM Trim for voltage reference [7:0] read-write PILO_IREFBM_TRIM Trim for beta-multiplier current reference [12:8] read-write PILO_IREF_TRIM Trim for current reference [23:16] read-write CLK_TRIM_PILO_CTL3 PILO Trim Register 3 0x311C 32 read-write 0x4800 0xFFFF PILO_ENGOPT Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. [15:0] read-write CLK_TRIM_ILO1_CTL ILO1 Trim Register 0x3220 32 read-write 0x52C 0xF3F ILO1_FTRIM ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency. [5:0] read-write ILO1_MONTRIM ILO1 internal monitor trim. [11:8] read-write 2 256 MCWDT[%s] Multi-Counter Watchdog Timer MCWDT 0x00008000 2 32 CTR[%s] MCWDT Configuration for Subcounter 0 and 1 MCWDT_CTR 0x00000000 CTL MCWDT Subcounter Control Register 0x0 32 read-write 0x0 0x80000001 ENABLED Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles. [0:0] read-only ENABLE Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [31:31] read-write LOWER_LIMIT MCWDT Subcounter Lower Limit Register 0x4 32 read-write 0x0 0xFFFF LOWER_LIMIT Lower limit for this MCWDT subcounter. See LOWER_ACTION. [15:0] read-write UPPER_LIMIT MCWDT Subcounter Upper Limit Register 0x8 32 read-write 0x0 0xFFFF UPPER_LIMIT Upper limit for this MCWDT subcounter. See UPPER_ACTION. [15:0] read-write WARN_LIMIT MCWDT Subcounter Warn Limit Register 0xC 32 read-write 0x0 0xFFFF WARN_LIMIT Warn limit for this MCWDT subcounter. See WARN_ACTION. [15:0] read-write CONFIG MCWDT Subcounter Configuration Register 0x10 32 read-write 0x0 0xD0001133 LOWER_ACTION Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the corresponding processor is in SLEEPDEEP. [1:0] read-write NOTHING Do nothing 0 FAULT Trigger a fault. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager. For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. For LOWER_LIMIT == 0: No action is triggered. 1 FAULT_THEN_RESET Trigger a fault. Further, trigger a system-wide reset if the fault is not serviced and the watchdog is not cleared within 6 clk_lf cycles. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager, which gives at least 3 clk_lf cycles for software to respond. For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. For LOWER_LIMIT == 0: No action is triggered. 2 UPPER_ACTION Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached, regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected. [5:4] read-write NOTHING Do nothing 0 FAULT Trigger a fault. For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For UPPER_LIMIT < 2: The action may take up to one extra clk_lf cycle to trigger. 1 FAULT_THEN_RESET Trigger a fault. Further, trigger a system-wide reset if the fault is not serviced and the watchdog is not cleared within 6 clk_lf cycles. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager, which gives at least 3 clk_lf cycles for software to respond. For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For UPPER_LIMIT < 2: The action may take up to one extra clk_lf cycle to trigger. 2 WARN_ACTION Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically. For WARN_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For WARN_LIMIT == [0,1] : The action may take up to one extra clk_lf cycle to trigger. [8:8] read-write NOTHING Do nothing 0 INT Trigger an interrupt. 1 AUTO_SERVICE Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING. [12:12] read-write DEBUG_TRIGGER_EN Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT, and then set this bit. It takes up to two clk_lf cycles for the trigger signal to be processed. Triggers that are less than two clk_lf cycles may be missed. Synchronization errors can accumulate each time it is halted. 0: Pauses the counter whenever a debug probe is connected. 1: Pauses the counter whenever a debug probe is connected and the trigger input is high. [28:28] read-write SLEEPDEEP_PAUSE Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause, due to internal synchronization. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. 0: Counter runs normally regardless of processor mode. 1: Counter pauses when corresponding processor is in SLEEPDEEP. [30:30] read-write DEBUG_RUN Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause, due to internal synchronization. When (DEBUG_RUN==1 or DEBUG_TRIGGER_EN==0) and the debugger is connected for at least two clk_lf cycles, the LOWER_ACTION is ignored until after the first service after the debugger is disconnected. After the debugger is disconnected, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. If the debugger is disconnected before two clk_lf cycles, the LOWER_ACTION may or may not be ignored. 0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. 1: When debugger connected, counter increments normally, but reset generation is blocked. To block LOWER_ACTION fault generation, write DEBUG_TRIGGER_EN==0. [31:31] read-write CNT MCWDT Subcounter Count Register 0x14 32 read-write 0x0 0xFFFF CNT Current value of subcounter for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep mode if SLEEPDEEP_PAUSE == 1. [15:0] read-write CPU_SELECT MCWDT CPU selection register 0x40 32 read-write 0x0 0x3 CPU_SEL Assigns this MCWDT to a CPU. This selects which CPU SLEEPDEEP signal is used for SLEEPDEEP_PAUSE. [1:0] read-write CTR2_CTL MCWDT Subcounter 2 Control register 0x80 32 read-write 0x0 0x80000001 ENABLED Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles. [0:0] read-only ENABLE Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [31:31] read-write CTR2_CONFIG MCWDT Subcounter 2 Configuration register 0x84 32 read-write 0x0 0xD01F0001 ACTION Action taken when the specified BIT toggles. Action will be triggered on the same edge where BITS to observe toggle. [0:0] read-write NOTHING Do nothing 0 INT Trigger an interrupt 1 BITS Bit to observe for a toggle: 0: Do ACTION after CNT[0] toggles (i.e. every tick) . 31: Do ACTION after CNT[31] toggles (i.e. every 2^31 ticks) [20:16] read-write DEBUG_TRIGGER_EN Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT, and then set this bit. It takes up to two clk_lf cycles for the trigger signal to be processed. Triggers that are less than two clk_lf cycles may be missed. Synchronization errors can accumulate each time it is halted. 0: Pauses the counter whenever a debug probe is connected. 1: Pauses the counter whenever a debug probe is connected and the trigger input is high. [28:28] read-write SLEEPDEEP_PAUSE Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause, due to internal synchronization. 0: Counter runs normally regardless of processor mode. 1: Counter pauses when corresponding processor is in SLEEPDEEP. [30:30] read-write DEBUG_RUN Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause and another two cycles to unpause, due to internal synchronization. 0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. 1: When debugger connected, counter increments normally, but reset generation is blocked. [31:31] read-write CTR2_CNT MCWDT Subcounter 2 Count Register 0x88 32 read-write 0x0 0xFFFFFFFF CNT2 Current value of subcounter 2 for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep mode if SLEEPDEEP_PAUSE == 1. [31:0] read-write LOCK MCWDT Lock Register 0x90 32 read-write 0x0 0x3 MCWDT_LOCK Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. [1:0] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 SERVICE MCWDT Service Register 0x94 32 read-write 0x0 0x3 CTR0_SERVICE Services subcounter 0. This resets the count value for subcounter 0 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending CTR0_SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write CTR0_SERVICE=1. If subcounter 0 is disabled, CTR0_SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. [0:0] read-write CTR1_SERVICE Services subcounter 1. This resets the count value for subcounter 1 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending CTR1_SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write CTR1_SERVICE=1. If subcounter 1 is disabled, CTR1_SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. [1:1] read-write INTR MCWDT Interrupt Register 0xA0 32 read-write 0x0 0x7 CTR0_INT MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. [0:0] read-write CTR1_INT MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. [1:1] read-write CTR2_INT MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. [2:2] read-write INTR_SET MCWDT Interrupt Set Register 0xA4 32 read-write 0x0 0x7 CTR0_INT Set interrupt for MCWDT_INT0 [0:0] read-write CTR1_INT Set interrupt for MCWDT_INT1 [1:1] read-write CTR2_INT Set interrupt for MCWDT_INT2 [2:2] read-write INTR_MASK MCWDT Interrupt Mask Register 0xA8 32 read-write 0x0 0x7 CTR0_INT Mask for sub-counter 0 for warning interrupt [0:0] read-write CTR1_INT Mask for sub-counter 1 for warning interrupt [1:1] read-write CTR2_INT Mask for sub-counter 2 [2:2] read-write INTR_MASKED MCWDT Interrupt Masked Register 0xAC 32 read-only 0x0 0x7 CTR0_INT Logical and of corresponding request and mask bits. [0:0] read-only CTR1_INT Logical and of corresponding request and mask bits. [1:1] read-only CTR2_INT Logical and of corresponding request and mask bits. [2:2] read-only WDT Watchdog Timer WDT 0x0000C000 CTL WDT Control Register 0x0 32 read-write 0x80000001 0x80000001 ENABLED Indicates actual state of watchdog. May lag ENABLE by up to three clk_ilo0 cycles. [0:0] read-only ENABLE Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE<>ENABLED. This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed. 0: Counter is disabled (not clocked). 1: Counter is enabled (counting up) [31:31] read-write LOWER_LIMIT WDT Lower Limit Register 0x4 32 read-write 0x0 0xFFFFFFFF LOWER_LIMIT Lower limit for watchdog. See LOWER_ACTION. [31:0] read-write UPPER_LIMIT WDT Upper Limit Register 0x8 32 read-write 0x8000 0xFFFFFFFF UPPER_LIMIT Upper limit for watchdog. See UPPER_ACTION. [31:0] read-write WARN_LIMIT WDT Warn Limit Register 0xC 32 read-write 0x0 0xFFFFFFFF WARN_LIMIT Warn limit for watchdog. See WARN_ACTION. [31:0] read-write CONFIG WDT Configuration Register 0x10 32 read-write 0x10 0xF0001111 LOWER_ACTION Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the chip is in DEEPSLEEP/HIBERNATE modes. For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. For LOWER_LIMIT == 0: No action is triggered. [0:0] read-write NOTHING Do nothing 0 RESET Trigger a reset. 1 UPPER_ACTION Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached, regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected. For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For UPPER_LIMIT < 2: The action may take up to one extra clk_ilo0 cycle to trigger. [4:4] read-write NOTHING Do nothing 0 RESET Trigger a reset. 1 WARN_ACTION Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically. For WARN_LIMIT >= 2: The action is triggered on same edge when it meets this condition. For WARN_LIMIT < 2 : The action may take up to one extra clk_ilo0 cycle to trigger. [8:8] read-write NOTHING Do nothing 0 INT Trigger an interrupt. 1 AUTO_SERVICE Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING. [12:12] read-write DEBUG_TRIGGER_EN Enables the trigger input for WDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this WDT, and then set this bit. It takes up to two clk_ilo0 cycles for the trigger signal to be processed. Triggers that are less than two clk_ilo0 cycles may be missed. Synchronization error can accumulate each time it is halted. 0: Pauses the counter whenever a debug probe is connected. 1: Pauses the counter whenever a debug probe is connected and the trigger input is high. [28:28] read-write DPSLP_PAUSE Pauses/runs this counter when the system is in DEEPSLEEP. Note it may take up to two clk_ilo0 cycles for the counter to pause, due to internal synchronization. During DEEPSLEEP wakeup, the pause request is removed when clk_hf0 starts clocking, and then it may take up to two clk_ilo0 cycles for the counter to start. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. 0: Counter behaves normally during DEEPSLEEP. 1: Counter pauses during DEEPSLEEP. [29:29] read-write HIB_PAUSE Pauses/runs this counter when the system is in HIBERNATE. Note it may take up to two clk_ilo0 cycles for the counter to pause, due to internal synchronization. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. 0: Counter behaves normally during HIBERNATE. 1: Counter pauses during HIBERNATE. [30:30] read-write DEBUG_RUN Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_ilo0 cycles for the counter to pause and another two cycles to unpause, due to internal synchronization. If the debugger is connected for at least two clk_ilo0 cycles, the LOWER_ACTION is ignored until after the first service after the debugger is disconnected. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. If the debugger is disconnected before two clk_ilo0 cycles, the LOWER_ACTION may or may not be ignored. 0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. 1: When debugger connected, counter increments normally, but reset generation is blocked. [31:31] read-write CNT WDT Count Register 0x14 32 read-write 0x0 0xFFFFFFFF CNT Current value of subcounter for this WDT. This field may lag the actual count value by up to one clk_ilo0 cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep or Hiberbate mode if DPSLP_PAUSE == 1 or HIB_PAUSE == 1. [31:0] read-write LOCK WDT Lock register 0x40 32 read-write 0x3 0x3 WDT_LOCK Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. This register also locks the clk_ilo0 settings. [1:0] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 SERVICE WDT Service register 0x44 32 read-write 0x0 0x1 SERVICE Services the watchdog. This resets the count value to zero. This may take up to three clk_ilo0 cycle to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write SERVICE=1. If WDT is disabled, SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. [0:0] read-write INTR WDT Interrupt Register 0x50 32 read-write 0x0 0x1 WDT WDT Interrupt Request. This bit is set as configured by WDT action and limits. Due to internal synchronization, it takes up to 8 SYSCLK cycles to update after a W1C or reading this register and during this time AHB bus is stalled. [0:0] read-write INTR_SET WDT Interrupt Set Register 0x54 32 read-write 0x0 0x1 WDT Set interrupt. Due to internal synchronization, it takes up to 8 SYSCLK cycles to update after a W1S or reading from this register and during this time AHB bus is stalled. [0:0] read-write INTR_MASK WDT Interrupt Mask Register 0x58 32 read-write 0x0 0x1 WDT Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. [0:0] read-write INTR_MASKED WDT Interrupt Masked Register 0x5C 32 read-only 0x0 0x1 WDT Logical and of corresponding request and mask bits. Due to internal synchronization, it takes up to 8 SYSCLK cycles to read from this register. During this time AHB bus is stalled. [0:0] read-only BACKUP SRSS Backup Domain (ver2) 0x40270000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0xFF0F3308 WCO_EN Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. [3:3] read-write CLK_SEL Clock select for RTC clock [9:8] read-write WCO Watch-crystal oscillator input, available in Active, DeepSleep and Hibernate 0 ALTBAK This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is only available in Active and DeepSleep power modes. Note that LFCLK clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO or ILO is intended as the clock source then choose it directly instead of routing through LFCLK. 1 ILO Internal Low frequency Oscillator, available in Active, DeepSleep and Hibernate. For Hibernate operation CLK_ILO_CONFIG. ILO_BACKUP must be set. 2 RSVD N/A 3 PRESCALER N/A [13:12] read-write WCO_BYPASS Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. [16:16] read-write VDDBAK_CTL Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. [18:17] read-write VBACKUP_MEAS Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. [19:19] read-write EN_CHARGE_KEY When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. [31:24] read-write RTC_RW RTC Read Write register 0x8 32 read-write 0x0 0x3 READ Read bit When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. [0:0] read-write WRITE Write bit Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. Only user RTC registers that were written to will get copied, others will not be affected. When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. [1:1] read-write CAL_CTL Oscillator calibration for absolute frequency 0xC 32 read-write 0x0 0xB000007F CALIB_VAL Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. [5:0] read-write CALIB_SIGN Calibration sign: 0= Negative sign: remove pulses (it takes more clock ticks to count one second) 1= Positive sign: add pulses (it takes less clock ticks to count one second) [6:6] read-write CAL_SEL Select calibration wave output signal [29:28] read-write CAL512 512Hz wave, not affected by calibration setting (not supported for 50/60Hz input clock: CTL.PRESCALER!=0) 0 RSVD N/A 1 CAL2 2Hz wave, includes the effect of the calibration setting, (not supported for 50/60Hz input clock: CTL.PRESCALER!=0) 2 CAL1 1Hz wave, includes the effect of the calibration setting (supported for all input clocks) 3 CAL_OUT Output enable for wave signal for calibration and allow CALIB_VAL to be written. [31:31] read-write STATUS Status 0x10 32 read-only 0x0 0x5 RTC_BUSY Pending RTC write [0:0] read-only WCO_OK Indicates that output has transitioned. [2:2] read-only RTC_TIME Calendar Seconds, Minutes, Hours, Day of Week 0x14 32 read-write 0x1000000 0x75F3F3F RTC_SEC Calendar seconds, 0-59 [5:0] read-write RTC_MIN Calendar minutes, 0-59 [13:8] read-write RTC_HOUR Calendar hours, value depending on 12/24HR mode 0=24HR: [20:16]=0-23 1=12HR: [20]:0=AM, 1=PM, [19:16]=1-12 [20:16] read-write CTRL_12HR Select 12/24HR mode: 1=12HR, 0=24HR [22:22] read-write RTC_DAY Calendar Day of the week, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write RTC_DATE Calendar Day of Month, Month, Year 0x18 32 read-write 0x101 0x7F0F1F RTC_DATE Calendar Day of the Month, 1-31 Automatic Leap Year Correction [4:0] read-write RTC_MON Calendar Month, 1-12 [11:8] read-write RTC_YEAR Calendar year, 0-99 [22:16] read-write ALM1_TIME Alarm 1 Seconds, Minute, Hours, Day of Week 0x1C 32 read-write 0x1000000 0x879FBFBF ALM_SEC Alarm seconds, 0-59 [5:0] read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match [7:7] read-write ALM_MIN Alarm minutes, 0-59 [13:8] read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match [15:15] read-write ALM_HOUR Alarm hours, value depending on 12/24HR mode 24HR: [4:0]=0-23 12HR: [4]:0=AM, 1=PM, [3:0]=1-12 [20:16] read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match [23:23] read-write ALM_DAY Alarm Day of the week, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match [31:31] read-write ALM1_DATE Alarm 1 Day of Month, Month 0x20 32 read-write 0x101 0x80008F9F ALM_DATE Alarm Day of the Month, 1-31 Leap Year corrected [4:0] read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match [7:7] read-write ALM_MON Alarm Month, 1-12 [11:8] read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match [15:15] read-write ALM_EN Master enable for alarm 1. 0: Alarm 1 is disabled. Fields for date and time are ignored. 1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. [31:31] read-write ALM2_TIME Alarm 2 Seconds, Minute, Hours, Day of Week 0x24 32 read-write 0x1000000 0x879FBFBF ALM_SEC Alarm seconds, 0-59 [5:0] read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match [7:7] read-write ALM_MIN Alarm minutes, 0-59 [13:8] read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match [15:15] read-write ALM_HOUR Alarm hours, value depending on 12/24HR mode 24HR: [4:0]=0-23 12HR: [4]:0=AM, 1=PM, [3:0]=1-12 [20:16] read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match [23:23] read-write ALM_DAY Alarm Day of the week, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match [31:31] read-write ALM2_DATE Alarm 2 Day of Month, Month 0x28 32 read-write 0x101 0x80008F9F ALM_DATE Alarm Day of the Month, 1-31 Leap Year corrected [4:0] read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match [7:7] read-write ALM_MON Alarm Month, 1-12 [11:8] read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match [15:15] read-write ALM_EN Master enable for alarm 2. 0: Alarm 2 is disabled. Fields for date and time are ignored. 1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. [31:31] read-write INTR Interrupt request register 0x2C 32 read-write 0x0 0x7 ALARM1 Alarm 1 Interrupt [0:0] read-write ALARM2 Alarm 2 Interrupt [1:1] read-write CENTURY Century overflow interrupt [2:2] read-write INTR_SET Interrupt set request register 0x30 32 read-write 0x0 0x7 ALARM1 Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write ALARM2 Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write CENTURY Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write INTR_MASK Interrupt mask register 0x34 32 read-write 0x0 0x7 ALARM1 Mask bit for corresponding bit in interrupt request register. [0:0] read-write ALARM2 Mask bit for corresponding bit in interrupt request register. [1:1] read-write CENTURY Mask bit for corresponding bit in interrupt request register. [2:2] read-write INTR_MASKED Interrupt masked request register 0x38 32 read-only 0x0 0x7 ALARM1 Logical and of corresponding request and mask bits. [0:0] read-only ALARM2 Logical and of corresponding request and mask bits. [1:1] read-only CENTURY Logical and of corresponding request and mask bits. [2:2] read-only PMIC_CTL PMIC control register 0x44 32 read-write 0xA0000000 0xE001FF00 UNLOCK This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. [15:8] read-write POLARITY N/A [16:16] read-write PMIC_EN_OUTEN Output enable for the output driver in the PMIC_EN pad. 0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present 1: Output pad is enabled for PMIC_EN pin. [29:29] read-write PMIC_ALWAYSEN Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. 0: Normal operation, PMIC_EN and PMIC_OUTEN work as described 1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. Note: This bit is a write-once bit until the next backup reset. [30:30] read-write PMIC_EN Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. [31:31] read-write RESET Backup reset register 0x48 32 read-write 0x0 0x80000000 RESET Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. [31:31] read-write 64 4 BREG[%s] Backup register region 0x1000 32 read-write 0x0 0xFFFFFFFF BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. [31:0] read-write DW0 Datawire Controller DW 0x40280000 0 65536 registers CTL Control 0x0 32 read-write 0x1 0x80000003 ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [0:0] read-write ECC_INJ_EN Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. [1:1] read-write ENABLED IP enable: '0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). '1': Enabled. [31:31] read-write STATUS Status 0x4 32 read-only 0x0 0xF0000000 P Active channel, user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS Active channel, secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only B Active channel, non-bufferable/bufferable access control: '0': non-bufferable '1': bufferable. [2:2] read-only PC Active channel protection context. [7:4] read-only PRIO Active channel priority. [9:8] read-only PREEMPTABLE Active channel preemptable. [11:11] read-only CH_IDX Active channel index. [24:16] read-only STATE State of the DW controller. '0': Default/inactive state. '1': Loading descriptor. '2': Loading data element from source location. '3': Storing data element to destination location. '4': CRC functionality (only used for CRC transfer descriptor type). '5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. '6': Error. [30:28] read-only ACTIVE Active channel present: '0': No. '1': Yes. [31:31] read-only ACT_DESCR_CTL Active descriptor control 0x20 32 read-only 0x0 0x0 DATA N/A [31:0] read-only ACT_DESCR_SRC Active descriptor source 0x24 32 read-only 0x0 0x0 DATA Copy of DESCR_SRC of the currently active descriptor. Base address of source location. [31:0] read-only ACT_DESCR_DST Active descriptor destination 0x28 32 read-only 0x0 0x0 DATA Copy of DESCR_DST of the currently active descriptor. Base address of destination location. Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes. [31:0] read-only ACT_DESCR_X_CTL Active descriptor X loop control 0x30 32 read-only 0x0 0x0 DATA Copy of DESCR_X_CTL of the currently active descriptor. [11:0] SRC_X_INCR Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. [23:12] DST_X_INCR Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. Note: this field is not used for CRC transfer descriptors and must be set to '0'. [31:24] X_COUNT Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. For a single transfer descriptor type, descriptor will not have X_CTL. [31:0] read-only ACT_DESCR_Y_CTL Active descriptor Y loop control 0x34 32 read-only 0x0 0x0 DATA Copy of DESCR_Y_CTL of the currently active descriptor. [11:0] SRC_Y_INCR Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. [23:12] DST_Y_INCR Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. [31:24] Y_COUNT Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL. [31:0] read-only ACT_DESCR_NEXT_PTR Active descriptor next pointer 0x38 32 read-only 0x0 0x0 ADDR Copy of DESCR_NEXT_PTR of the currently active descriptor. [31:2] ADDR Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. [31:2] read-only ACT_SRC Active source 0x40 32 read-only 0x0 0x0 SRC_ADDR Current address of source location. [31:0] read-only ACT_DST Active destination 0x44 32 read-only 0x0 0x0 DST_ADDR Current address of destination location. [31:0] read-only ECC_CTL ECC control 0x80 32 read-write 0x0 0xFE0003FF WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [9:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write CRC_CTL CRC control 0x100 32 read-write 0x0 0x101 DATA_REVERSE Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): '0': Most significant bit (bit 1) first. '1': Least significant bit (bit 0) first. [0:0] read-write REM_REVERSE Specifies whether the remainder is bit reversed (reversal is performed after XORing): '0': No. '1': Yes. [8:8] read-write CRC_DATA_CTL CRC data control 0x110 32 read-write 0x0 0xFF DATA_XOR Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. [7:0] read-write CRC_POL_CTL CRC polynomial control 0x120 32 read-write 0x0 0xFFFFFFFF POLYNOMIAL CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). [31:0] read-write CRC_LFSR_CTL CRC LFSR control 0x130 32 read-write 0x0 0xFFFFFFFF LFSR32 State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). [31:0] read-write CRC_REM_CTL CRC remainder control 0x140 32 read-write 0x0 0xFFFFFFFF REM_XOR Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. [31:0] read-write CRC_REM_RESULT CRC remainder result 0x148 32 read-only 0x0 0xFFFFFFFF REM Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: '0': the more significant bits (bit 31 and down) contain the remainder. '1': the less significant bits (bit 0 and up) contain the remainder. Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. [31:0] read-only 92 64 CH_STRUCT[%s] DW channel structure 0x00008000 CH_CTL Channel control 0x0 32 read-write 0x0 0x80000300 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). [9:8] read-write PREEMPTABLE Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. [11:11] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). [31:31] read-write CH_STATUS Channel status 0x4 32 read-only 0x0 0x80000000 INTR_CAUSE Specifies the source of the interrupt cause: '0': No interrupt generated '1': Interrupt based on transfer complettion configuration based on INTR_TYPE '2': Source transfer bus error '3': Destination transfer bus error '4': Source address misalignment '5': Destination address misalignment '6': Current descriptor pointer is null '7': Active channel is disabled '8': Descriptor bus error '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). [3:0] read-only PENDING Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). [31:31] read-only CH_IDX Channel current indices 0x8 32 read-write 0x0 0x0 X_IDX Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [7:0] read-write Y_IDX Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [15:8] read-write CH_CURR_PTR Channel current descriptor pointer 0xC 32 read-write 0x0 0x0 ADDR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. [31:2] read-write INTR Interrupt 0x10 32 read-write 0x0 0x1 CH Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. [0:0] read-write INTR_SET Interrupt set 0x14 32 read-write 0x0 0x1 CH Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt mask 0x18 32 read-write 0x0 0x1 CH Mask for corresponding field in INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0x1C 32 read-only 0x0 0x1 CH Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only SRAM_DATA0 SRAM data 0 0x20 32 read-write 0x0 0x0 DATA N/A [31:0] read-write SRAM_DATA1 SRAM data 1 0x24 32 read-write 0x0 0x0 DATA N/A [31:0] read-write TR_CMD Channel software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DW1 0x40290000 DMAC DMAC 0x402A0000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 ACTIVE Active channels 0x8 32 read-only 0x0 0xFF ACTIVE Specifies active channels; i.e. enabled channels whose trigger got activated. [7:0] read-only 4 256 CH[%s] DMA controller channel 0x00001000 CTL Channel control 0x0 32 read-write 0x2 0x800003F7 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. [9:8] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' when an error interrupt cause is activated. [31:31] read-write IDX Channel current indices 0x10 32 read-only 0x0 0x0 X Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor. [15:0] read-only Y Specifies the Y loop index, with Y_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor.. [31:16] read-only SRC Channel current source address 0x14 32 read-only 0x0 0x0 ADDR Current address of source location. [31:0] read-only DST Channel current destination address 0x18 32 read-only 0x0 0x0 ADDR Current address of destination location. [31:0] read-only CURR Channel current descriptor pointer 0x20 32 read-write 0x0 0x0 PTR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. [31:2] read-write TR_CMD Channle software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DESCR_STATUS Channel descriptor status 0x40 32 read-only 0x0 0x80000000 VALID Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. [31:31] read-only DESCR_CTL Channel descriptor control 0x60 32 read-only 0x0 0x0 WAIT_FOR_DEACT Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance. '0': Do not wait for trigger de-activation (for pulse sensitive triggers). '1': Wait for up to 4 cycles. '2': Wait for up to 16 cycles. '3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated. [1:0] read-only INTR_TYPE Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): '0': An interrupt is generated after a single transfer. '1': An interrupt is generated after a single 1D transfer or a memory copy transfer - If the descriptor type is 'single', the interrupt is generated after a single transfer. - If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer. - If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer. - If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer. '2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor). '3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. [3:2] read-only TR_OUT_TYPE Specifies when an output trigger is generated: '0': An output trigger is generated after a single transfer. '1': An output trigger is generated after a single 1D transfer or a memory copy transfer. - If the descriptor type is 'single', the output trigger is generated after a single transfer. - If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer. - If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer. - If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer. '2': An output trigger is generated after the execution of the current descriptor. '3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. [5:4] read-only TR_IN_TYPE Specifies the input trigger type (not to be confused with the descriptor type): '0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D. '1': A trigger results in the execution of a single 1D transfer. - If the descriptor type is 'single', the trigger results in the execution of a single transfer. - If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer. - If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer. - If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer. '2': A trigger results in the execution of the current descriptor. '3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information. [7:6] read-only DATA_PREFETCH Source data prefetch: '0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. '1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer. Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects. [8:8] read-only DATA_SIZE Specifies the data element size: '0': Byte (8 bits). '1': Halfword (16 bits). '2': Word (32 bits). DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: - DATA is 8 bit, SRC is 8 bit, DST is 8 bit. - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit. - DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0'). - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0'). - DATA is 16 bit, SRC is 16 bit, DST is 16 bit. - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit. - DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0'). - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0'). - DATA is 32 bit, SRC is 32 bit, DST is 32 bit. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type. [17:16] read-only CH_DISABLE Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): '0': Channel is not disabled. '1': Channel is disabled. [24:24] read-only SRC_TRANSFER_SIZE Specifies the bus transfer size to the source location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. [26:26] read-only DST_TRANSFER_SIZE Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. [27:27] read-only DESCR_TYPE Specifies the descriptor type (not to be confused with the trigger type): '0': Single transfer. The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c. '1': 1D transfer. The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14. '2': 2D transfer. The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c. '3': Memory copy. The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10. '4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. '5'-'7': Undefined. After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'. [30:28] read-only DESCR_SRC Channel descriptor source 0x64 32 read-only 0x0 0x0 ADDR Base address of source location. [31:0] read-only DESCR_DST Channel descriptor destination 0x68 32 read-only 0x0 0x0 ADDR Base address of destination location. [31:0] read-only DESCR_X_SIZE Channel descriptor X size 0x6C 32 read-only 0x0 0x0 X_COUNT Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed. [15:0] read-only DESCR_X_INCR Channel descriptor X increment 0x70 32 read-only 0x0 0x0 SRC_X Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. [15:0] read-only DST_X Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. [31:16] read-only DESCR_Y_SIZE Channel descriptor Y size 0x74 32 read-only 0x0 0x0 Y_COUNT Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. [15:0] read-only DESCR_Y_INCR Channel descriptor Y increment 0x78 32 read-only 0x0 0x0 SRC_Y Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. [15:0] read-only DST_Y Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. [31:16] read-only DESCR_NEXT Channel descriptor next pointer 0x7C 32 read-only 0x0 0x0 PTR Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. [31:2] read-only INTR Interrupt 0x80 32 read-write 0x0 0xFF COMPLETION Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. [0:0] read-write SRC_BUS_ERROR Activated (set to '1') on a bus error for a load from the source. [1:1] read-write DST_BUS_ERROR Activated (set to '1') on a bus error for a store to the destination. [2:2] read-write SRC_MISAL Activated (set to '1') on a misalignment of the source address. [3:3] read-write DST_MISAL Activated (set to '1') on a misalignment of the destination address. [4:4] read-write CURR_PTR_NULL Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. [5:5] read-write ACTIVE_CH_DISABLED Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. [6:6] read-write DESCR_BUS_ERROR Activated (set to '1') on a bus error for a load of the descriptor. [7:7] read-write INTR_SET Interrupt set 0x84 32 read-write 0x0 0xFF COMPLETION Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect). [0:0] read-write SRC_BUS_ERROR Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect). [1:1] read-write DST_BUS_ERROR Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect). [2:2] read-write SRC_MISAL Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect). [3:3] read-write DST_MISAL Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect). [4:4] read-write CURR_PTR_NULL Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect). [5:5] read-write ACTIVE_CH_DISABLED Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect). [6:6] read-write DESCR_BUS_ERROR Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect). [7:7] read-write INTR_MASK Interrupt mask 0x88 32 read-write 0x0 0xFF COMPLETION Mask for INTR.COMPLETION interrupt. [0:0] read-write SRC_BUS_ERROR Mask for INTR.SRC_BUS_ERROR interrupt. [1:1] read-write DST_BUS_ERROR Mask for INTR.DST_BUS_ERROR interrupt. [2:2] read-write SRC_MISAL Mask for INTR.SRC_MISAL interrupt. [3:3] read-write DST_MISAL Mask for INTR.DST_MISAL interrupt. [4:4] read-write CURR_PTR_NULL Mask for INTR.CURR_PTR_NULL interrupt. [5:5] read-write ACTIVE_CH_DISABLED Mask for INTR.ACTIVE_CH_DISABLED interrupt. [6:6] read-write DESCR_BUS_ERROR Mask for INTR.DESCR_BUS_ERROR interrupt. [7:7] read-write INTR_MASKED Interrupt masked 0x8C 32 read-only 0x0 0xFF COMPLETION Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields. [0:0] read-only SRC_BUS_ERROR Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields. [1:1] read-only DST_BUS_ERROR Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields. [2:2] read-only SRC_MISAL Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields. [3:3] read-only DST_MISAL Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields. [4:4] read-only CURR_PTR_NULL Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields. [5:5] read-only ACTIVE_CH_DISABLED Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields. [6:6] read-only DESCR_BUS_ERROR Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields. [7:7] read-only EFUSE EFUSE MXS40 registers 0x402C0000 0 512 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write TEST Test 0x4 32 read-write 0x1 0x3 MARG_READ Margin Read [1:0] read-write LOWR Low Resistance: -50 percent from nominal 0 DEFAULTR Nominal resistance (Default read condition) 1 HIGHR High Resistance: +50 percent from nominal 2 HIGHERR Higher Resistance: +100 percent from nominal 3 CMD Command 0x10 32 read-write 0x1 0x800F1F71 BIT_DATA Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. [0:0] read-write BIT_ADDR Bit address. This field specifies a bit within a Byte. [6:4] read-write BYTE_ADDR Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). [12:8] read-write MACRO_ADDR Macro address. This field specifies an eFUSE macro. [19:16] read-write START FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. [31:31] read-write SEQ_DEFAULT Sequencer Default value 0x20 32 read-write 0x1D0000 0x7F0000 STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write SEQ_READ_CTL_0 Sequencer read control 0 0x40 32 read-write 0x80560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_1 Sequencer read control 1 0x44 32 read-write 0x540004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_2 Sequencer read control 2 0x48 32 read-write 0x560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_3 Sequencer read control 3 0x4C 32 read-write 0x540003 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_4 Sequencer read control 4 0x50 32 read-write 0x80150001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_5 Sequencer read control 5 0x54 32 read-write 0x310004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_0 Sequencer program control 0 0x60 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_1 Sequencer program control 1 0x64 32 read-write 0x220020 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_2 Sequencer program control 2 0x68 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_3 Sequencer program control 3 0x6C 32 read-write 0x310005 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_4 Sequencer program control 4 0x70 32 read-write 0x80350006 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_5 Sequencer program control 5 0x74 32 read-write 0x803D0019 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write HSIOM High Speed IO Matrix (HSIOM) 0x40300000 0 16384 registers 24 16 PRT[%s] HSIOM port registers 0x00000000 PORT_SEL0 Port selection 0 0x0 32 read-write 0x0 0x1F1F1F1F IO0_SEL Selects connection for IO pin 0 route. [4:0] read-write GPIO GPIO controls 'out' 0 GPIO_DSI GPIO controls 'out', DSI controls 'output enable' 1 DSI_DSI DSI controls 'out' and 'output enable' 2 DSI_GPIO DSI controls 'out', GPIO controls 'output enable' 3 AMUXA Analog mux bus A 4 AMUXB Analog mux bus B 5 AMUXA_DSI Analog mux bus A, DSI control 6 AMUXB_DSI Analog mux bus B, DSI control 7 ACT_0 Active functionality 0 8 ACT_1 Active functionality 1 9 ACT_2 Active functionality 2 10 ACT_3 Active functionality 3 11 DS_0 DeepSleep functionality 0 12 DS_1 DeepSleep functionality 1 13 DS_2 DeepSleep functionality 2 14 DS_3 DeepSleep functionality 3 15 ACT_4 Active functionality 4 16 ACT_5 Active functionality 5 17 ACT_6 Active functionality 6 18 ACT_7 Active functionality 7 19 ACT_8 Active functionality 8 20 ACT_9 Active functionality 9 21 ACT_10 Active functionality 10 22 ACT_11 Active functionality 11 23 ACT_12 Active functionality 12 24 ACT_13 Active functionality 13 25 ACT_14 Active functionality 14 26 ACT_15 Active functionality 15 27 DS_4 DeepSleep functionality 4 28 DS_5 DeepSleep functionality 5 29 DS_6 DeepSleep functionality 6 30 DS_7 DeepSleep functionality 7 31 IO1_SEL Selects connection for IO pin 1 route. [12:8] read-write IO2_SEL Selects connection for IO pin 2 route. [20:16] read-write IO3_SEL Selects connection for IO pin 3 route. [28:24] read-write PORT_SEL1 Port selection 1 0x4 32 read-write 0x0 0x1F1F1F1F IO4_SEL Selects connection for IO pin 4 route. See PORT_SEL0 for connection details. [4:0] read-write IO5_SEL Selects connection for IO pin 5 route. [12:8] read-write IO6_SEL Selects connection for IO pin 6 route. [20:16] read-write IO7_SEL Selects connection for IO pin 7 route. [28:24] read-write 64 4 AMUX_SPLIT_CTL[%s] AMUX splitter cell control 0x2000 32 read-write 0x0 0x77 SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. [0:0] read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. [1:1] read-write SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. [2:2] read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. [4:4] read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. [5:5] read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. [6:6] read-write MONITOR_CTL_0 Power/Ground Monitor cell control 0 0x2200 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_1 Power/Ground Monitor cell control 1 0x2204 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_2 Power/Ground Monitor cell control 2 0x2208 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_3 Power/Ground Monitor cell control 3 0x220C 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write ALT_JTAG_EN Alternate JTAG IF selection register 0x2240 32 read-write 0x0 0x80000000 ENABLE Provides the selection for alternate JTAG IF connectivity. 0: Primary JTAG interface is selected 1: Secondary (alternate) JTAG interface is selected. This connectivity works ONLY in ACTIVE mode. [31:31] read-write GPIO GPIO port control/configuration 0x40310000 0 65536 registers 24 128 PRT[%s] GPIO port registers 0x00000000 OUT Port output data register 0x0 32 read-write 0x0 0xFF OUT0 IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' [0:0] read-write OUT1 IO output data for pin 1 [1:1] read-write OUT2 IO output data for pin 2 [2:2] read-write OUT3 IO output data for pin 3 [3:3] read-write OUT4 IO output data for pin 4 [4:4] read-write OUT5 IO output data for pin 5 [5:5] read-write OUT6 IO output data for pin 6 [6:6] read-write OUT7 IO output data for pin 7 [7:7] read-write OUT_CLR Port output data clear register 0x4 32 read-write 0x0 0xFF OUT0 IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'. [0:0] read-write OUT1 IO clear output for pin 1 [1:1] read-write OUT2 IO clear output for pin 2 [2:2] read-write OUT3 IO clear output for pin 3 [3:3] read-write OUT4 IO clear output for pin 4 [4:4] read-write OUT5 IO clear output for pin 5 [5:5] read-write OUT6 IO clear output for pin 6 [6:6] read-write OUT7 IO clear output for pin 7 [7:7] read-write OUT_SET Port output data set register 0x8 32 read-write 0x0 0xFF OUT0 IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'. [0:0] read-write OUT1 IO set output for pin 1 [1:1] read-write OUT2 IO set output for pin 2 [2:2] read-write OUT3 IO set output for pin 3 [3:3] read-write OUT4 IO set output for pin 4 [4:4] read-write OUT5 IO set output for pin 5 [5:5] read-write OUT6 IO set output for pin 6 [6:6] read-write OUT7 IO set output for pin 7 [7:7] read-write OUT_INV Port output data invert register 0xC 32 read-write 0x0 0xFF OUT0 IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0'). [0:0] read-write OUT1 IO invert output for pin 1 [1:1] read-write OUT2 IO invert output for pin 2 [2:2] read-write OUT3 IO invert output for pin 3 [3:3] read-write OUT4 IO invert output for pin 4 [4:4] read-write OUT5 IO invert output for pin 5 [5:5] read-write OUT6 IO invert output for pin 6 [6:6] read-write OUT7 IO invert output for pin 7 [7:7] read-write IN Port input state register 0x10 32 read-only 0x0 0x1FF IN0 IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. [0:0] read-only IN1 IO pin state for pin 1 [1:1] read-only IN2 IO pin state for pin 2 [2:2] read-only IN3 IO pin state for pin 3 [3:3] read-only IN4 IO pin state for pin 4 [4:4] read-only IN5 IO pin state for pin 5 [5:5] read-only IN6 IO pin state for pin 6 [6:6] read-only IN7 IO pin state for pin 7 [7:7] read-only FLT_IN Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. [8:8] read-only INTR Port interrupt status register 0x14 32 read-write 0x0 0x1FF01FF EDGE0 Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. [0:0] read-write EDGE1 Edge detect for IO pin 1 [1:1] read-write EDGE2 Edge detect for IO pin 2 [2:2] read-write EDGE3 Edge detect for IO pin 3 [3:3] read-write EDGE4 Edge detect for IO pin 4 [4:4] read-write EDGE5 Edge detect for IO pin 5 [5:5] read-write EDGE6 Edge detect for IO pin 6 [6:6] read-write EDGE7 Edge detect for IO pin 7 [7:7] read-write FLT_EDGE Edge detected on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write IN_IN0 IO pin state for pin 0 [16:16] read-only IN_IN1 IO pin state for pin 1 [17:17] read-only IN_IN2 IO pin state for pin 2 [18:18] read-only IN_IN3 IO pin state for pin 3 [19:19] read-only IN_IN4 IO pin state for pin 4 [20:20] read-only IN_IN5 IO pin state for pin 5 [21:21] read-only IN_IN6 IO pin state for pin 6 [22:22] read-only IN_IN7 IO pin state for pin 7 [23:23] read-only FLT_IN_IN Filtered pin state for pin selected by INTR_CFG.FLT_SEL [24:24] read-only INTR_MASK Port interrupt mask register 0x18 32 read-write 0x0 0x1FF EDGE0 Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled [0:0] read-write EDGE1 Masks edge interrupt on IO pin 1 [1:1] read-write EDGE2 Masks edge interrupt on IO pin 2 [2:2] read-write EDGE3 Masks edge interrupt on IO pin 3 [3:3] read-write EDGE4 Masks edge interrupt on IO pin 4 [4:4] read-write EDGE5 Masks edge interrupt on IO pin 5 [5:5] read-write EDGE6 Masks edge interrupt on IO pin 6 [6:6] read-write EDGE7 Masks edge interrupt on IO pin 7 [7:7] read-write FLT_EDGE Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_MASKED Port interrupt masked status register 0x1C 32 read-only 0x0 0x1FF EDGE0 Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [0:0] read-only EDGE1 Edge detected and masked on IO pin 1 [1:1] read-only EDGE2 Edge detected and masked on IO pin 2 [2:2] read-only EDGE3 Edge detected and masked on IO pin 3 [3:3] read-only EDGE4 Edge detected and masked on IO pin 4 [4:4] read-only EDGE5 Edge detected and masked on IO pin 5 [5:5] read-only EDGE6 Edge detected and masked on IO pin 6 [6:6] read-only EDGE7 Edge detected and masked on IO pin 7 [7:7] read-only FLT_EDGE Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-only INTR_SET Port interrupt set register 0x20 32 read-write 0x0 0x1FF EDGE0 Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set [0:0] read-write EDGE1 Sets edge detect interrupt for IO pin 1 [1:1] read-write EDGE2 Sets edge detect interrupt for IO pin 2 [2:2] read-write EDGE3 Sets edge detect interrupt for IO pin 3 [3:3] read-write EDGE4 Sets edge detect interrupt for IO pin 4 [4:4] read-write EDGE5 Sets edge detect interrupt for IO pin 5 [5:5] read-write EDGE6 Sets edge detect interrupt for IO pin 6 [6:6] read-write EDGE7 Sets edge detect interrupt for IO pin 7 [7:7] read-write FLT_EDGE Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_CFG Port interrupt configuration register 0x40 32 read-write 0x0 0x1FFFFF EDGE0_SEL Sets which edge will trigger an IRQ for IO pin 0 [1:0] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 EDGE1_SEL Sets which edge will trigger an IRQ for IO pin 1 [3:2] read-write EDGE2_SEL Sets which edge will trigger an IRQ for IO pin 2 [5:4] read-write EDGE3_SEL Sets which edge will trigger an IRQ for IO pin 3 [7:6] read-write EDGE4_SEL Sets which edge will trigger an IRQ for IO pin 4 [9:8] read-write EDGE5_SEL Sets which edge will trigger an IRQ for IO pin 5 [11:10] read-write EDGE6_SEL Sets which edge will trigger an IRQ for IO pin 6 [13:12] read-write EDGE7_SEL Sets which edge will trigger an IRQ for IO pin 7 [15:14] read-write FLT_EDGE_SEL Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 FLT_SEL Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. [20:18] read-write CFG Port configuration register 0x44 32 read-write 0x0 0xFFFFFFFF DRIVE_MODE0 The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. [2:0] read-write HIGHZ Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance 0 RSVD N/A 1 PULLUP Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up 2 PULLDOWN Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down 3 OD_DRIVESLOW Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 4 OD_DRIVESHIGH Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 5 STRONG Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 6 PULLUP_DOWN Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up 7 IN_EN0 Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled [3:3] read-write DRIVE_MODE1 The GPIO drive mode for IO pin 1 [6:4] read-write IN_EN1 Enables the input buffer for IO pin 1 [7:7] read-write DRIVE_MODE2 The GPIO drive mode for IO pin 2 [10:8] read-write IN_EN2 Enables the input buffer for IO pin 2 [11:11] read-write DRIVE_MODE3 The GPIO drive mode for IO pin 3 [14:12] read-write IN_EN3 Enables the input buffer for IO pin 3 [15:15] read-write DRIVE_MODE4 The GPIO drive mode for IO pin4 [18:16] read-write IN_EN4 Enables the input buffer for IO pin 4 [19:19] read-write DRIVE_MODE5 The GPIO drive mode for IO pin 5 [22:20] read-write IN_EN5 Enables the input buffer for IO pin 5 [23:23] read-write DRIVE_MODE6 The GPIO drive mode for IO pin 6 [26:24] read-write IN_EN6 Enables the input buffer for IO pin 6 [27:27] read-write DRIVE_MODE7 The GPIO drive mode for IO pin 7 [30:28] read-write IN_EN7 Enables the input buffer for IO pin 7 [31:31] read-write CFG_IN Port input buffer configuration register 0x48 32 read-write 0x0 0xFF VTRIP_SEL0_0 Configures the pin 0 input buffer mode (trip points and hysteresis) [0:0] read-write CMOS PSoC 6:: Input buffer compatible with CMOS and I2C interfaces Traveo II: Full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 0 TTL PSoC 6:: Input buffer compatible with TTL and MediaLB interfaces Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 1 VTRIP_SEL1_0 Configures the pin 1 input buffer mode (trip points and hysteresis) [1:1] read-write VTRIP_SEL2_0 Configures the pin 2 input buffer mode (trip points and hysteresis) [2:2] read-write VTRIP_SEL3_0 Configures the pin 3 input buffer mode (trip points and hysteresis) [3:3] read-write VTRIP_SEL4_0 Configures the pin 4 input buffer mode (trip points and hysteresis) [4:4] read-write VTRIP_SEL5_0 Configures the pin 5 input buffer mode (trip points and hysteresis) [5:5] read-write VTRIP_SEL6_0 Configures the pin 6 input buffer mode (trip points and hysteresis) [6:6] read-write VTRIP_SEL7_0 Configures the pin 7 input buffer mode (trip points and hysteresis) [7:7] read-write CFG_OUT Port output buffer configuration register 0x4C 32 read-write 0x0 0xFFFF00FF SLOW0 Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate [0:0] read-write SLOW1 Enables slow slew rate for IO pin 1 [1:1] read-write SLOW2 Enables slow slew rate for IO pin 2 [2:2] read-write SLOW3 Enables slow slew rate for IO pin 3 [3:3] read-write SLOW4 Enables slow slew rate for IO pin 4 [4:4] read-write SLOW5 Enables slow slew rate for IO pin 5 [5:5] read-write SLOW6 Enables slow slew rate for IO pin 6 [6:6] read-write SLOW7 Enables slow slew rate for IO pin 7 [7:7] read-write DRIVE_SEL0 Sets the GPIO drive strength for IO pin 0 [17:16] read-write DRIVE_SEL_ZERO Please refer to architecture TRM section I/O System 0 DRIVE_SEL_ONE Please refer to architecture TRM section I/O System 1 DRIVE_SEL_TWO Please refer to architecture TRM section I/O System 2 DRIVE_SEL_THREE Please refer to architecture TRM section I/O System 3 DRIVE_SEL1 Sets the GPIO drive strength for IO pin 1 [19:18] read-write DRIVE_SEL2 Sets the GPIO drive strength for IO pin 2 [21:20] read-write DRIVE_SEL3 Sets the GPIO drive strength for IO pin 3 [23:22] read-write DRIVE_SEL4 Sets the GPIO drive strength for IO pin 4 [25:24] read-write DRIVE_SEL5 Sets the GPIO drive strength for IO pin 5 [27:26] read-write DRIVE_SEL6 Sets the GPIO drive strength for IO pin 6 [29:28] read-write DRIVE_SEL7 Sets the GPIO drive strength for IO pin 7 [31:30] read-write CFG_SIO Port SIO configuration register 0x50 32 read-write 0x0 0xFFFFFFFF VREG_EN01 Selects the output buffer mode: '0': Unregulated output buffer '1': Regulated output buffer The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. [0:0] read-write IBUF_SEL01 Selects the input buffer mode: 0: Singled ended input buffer 1: Differential input buffer [1:1] read-write VTRIP_SEL01 Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): '0': Input buffer functions as a CMOS input buffer. '1': Input buffer functions as a TTL input buffer. In differential input buffer mode (IBUF_SEL = '1') '0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) '1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) [2:2] read-write VREF_SEL01 Selects reference voltage (Vref) trip-point of the input buffer: '0': Trip-point reference from pin_ref '1': Trip-point reference of SRSS internal reference Vref (1.2 V) '2': Trip-point reference of AMUXBUS_A '3': Trip-point reference of AMUXBUS_B [4:3] read-write VOH_SEL01 Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). '0': Voh = 1*reference; e.g. reference at 1.2V -> Voh = 1.2V '1': Voh = 1.25*reference; e.g. reference at 1.2V -> Voh = 1.5V '2': Voh = 1.49*reference; e.g. reference at 1.2V -> Voh = ~1.8V '3': Voh = 1.67*reference; e.g. reference at 1.2V -> Voh = 2V '4': Voh = 2.08*reference; e.g. reference at 1.2V -> Voh = 2.5V '5': Voh = 2.5*reference; e.g. reference at 1.2V -> Voh = 3V '6': Voh = 2.78*reference; e.g. reference at 1.2V -> Voh = ~3.3V '7': Voh = 4.16*reference; e.g. reference at 1.2V -> Voh = 5.0V Note: The upper value on Voh is limited to Vddio - 400mV [7:5] read-write VREG_EN23 See corresponding definition for IO pins 0 and 1 [8:8] read-write IBUF_SEL23 See corresponding definition for IO pins 0 and 1 [9:9] read-write VTRIP_SEL23 See corresponding definition for IO pins 0 and 1 [10:10] read-write VREF_SEL23 See corresponding definition for IO pins 0 and 1 [12:11] read-write VOH_SEL23 See corresponding definition for IO pins 0 and 1 [15:13] read-write VREG_EN45 See corresponding definition for IO pins 0 and 1 [16:16] read-write IBUF_SEL45 See corresponding definition for IO pins 0 and 1 [17:17] read-write VTRIP_SEL45 See corresponding definition for IO pins 0 and 1 [18:18] read-write VREF_SEL45 See corresponding definition for IO pins 0 and 1 [20:19] read-write VOH_SEL45 See corresponding definition for IO pins 0 and 1 [23:21] read-write VREG_EN67 See corresponding definition for IO pins 0 and 1 [24:24] read-write IBUF_SEL67 See corresponding definition for IO pins 0 and 1 [25:25] read-write VTRIP_SEL67 See corresponding definition for IO pins 0 and 1 [26:26] read-write VREF_SEL67 See corresponding definition for IO pins 0 and 1 [28:27] read-write VOH_SEL67 See corresponding definition for IO pins 0 and 1 [31:29] read-write CFG_IN_AUTOLVL Port input buffer AUTOLVL configuration register 0x58 32 read-write 0x0 0xFF VTRIP_SEL0_1 Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: {CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: 0,0: CMOS 0,1: TTL 1,0: input buffer is compatible with automotive. 1,1: input buffer is compatible with automotvie [0:0] read-write CMOS_OR_TTL Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. 0 AUTO Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. 1 VTRIP_SEL1_1 Input buffer compatible with automotive (elevated Vil) interfaces. [1:1] read-write VTRIP_SEL2_1 Input buffer compatible with automotive (elevated Vil) interfaces. [2:2] read-write VTRIP_SEL3_1 Input buffer compatible with automotive (elevated Vil) interfaces. [3:3] read-write VTRIP_SEL4_1 Input buffer compatible with automotive (elevated Vil) interfaces. [4:4] read-write VTRIP_SEL5_1 Input buffer compatible with automotive (elevated Vil) interfaces. [5:5] read-write VTRIP_SEL6_1 Input buffer compatible with automotive (elevated Vil) interfaces. [6:6] read-write VTRIP_SEL7_1 Input buffer compatible with automotive (elevated Vil) interfaces. [7:7] read-write INTR_CAUSE0 Interrupt port cause register 0 0x4000 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE1 Interrupt port cause register 1 0x4004 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE2 Interrupt port cause register 2 0x4008 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE3 Interrupt port cause register 3 0x400C 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only VDD_ACTIVE Extern power supply detection register 0x4010 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. '0': Supply is not present '1': Supply is present When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: 0: vbackup, 1: vddio_0, 2: vddio_1, 3: vddio_a, 4: vddio_r, 5: vddusb' [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) [31:31] read-only VDD_INTR Supply detection interrupt register 0x4014 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Supply state change detected. '0': No change to supply detected '1': Change to supply detected [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. [31:31] read-write VDD_INTR_MASK Supply detection interrupt mask register 0x4018 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Masks supply interrupt on VDDIO. '0': VDDIO interrupt forwarding disabled '1': VDDIO interrupt forwarding enabled [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write VDD_INTR_MASKED Supply detection interrupt masked register 0x401C 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Supply transition detected AND masked '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-only VDD_INTR_SET Supply detection interrupt set register 0x4020 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Sets supply interrupt. '0': Interrupt state not affected '1': Interrupt set [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write SMARTIO Programmable IO configuration 0x40320000 0 65536 registers 18 256 PRT[%s] Programmable IO port registers 0x00000000 CTL Control register 0x0 32 read-write 0x2001400 0x82001F00 BYPASS Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. '0': No bypass (programmable SMARTIO fabric is exposed). '1': Bypass (programmable SMARTIOIO fabric is hidden). [7:0] read-write CLOCK_SRC Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: '0': io_data_in[0]/'1'. ... '7': io_data_in[7]/'1'. '8': chip_data[0]/'1'. ... '15': chip_data[7]/'1'. '16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. '19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. '20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. '31': asynchronous mode/'1'. Select this when clockless operation is configured. NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. [12:8] read-write HLD_OVR IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: '0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). '1': The SMARTIO controls the IO cel hold override functionality: - In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. - In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). [24:24] read-write PIPELINE_EN Enable for pipeline register: '0': Disabled (register is bypassed). '1': Enabled. [25:25] read-write ENABLED Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: '0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. If the IP is disabled: - The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. - The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. '1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. [31:31] read-write SYNC_CTL Synchronization control register 0x10 32 read-write 0x0 0x0 IO_SYNC_EN Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. '0': No synchronization. '1': Synchronization. [7:0] read-write CHIP_SYNC_EN Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. '0': No synchronization. '1': Synchronization. [15:8] read-write 8 4 LUT_SEL[%s] LUT component input selection 0x20 32 read-write 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). [3:0] read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). [11:8] read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. [19:16] read-write 8 4 LUT_CTL[%s] LUT component control register 0x40 32 read-write 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). [7:0] read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable & (tr1_in ^ LUT[2]) & LUT[3]. clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' [9:8] read-write DU_SEL Data unit component input selection 0xC0 32 read-write 0x0 0x0 DU_TR0_SEL Data unit input signal 'tr0_in' source selection: '0': Constant '0'. '1': Constant '1'. '2': Data unit output. '10-3': LUT 7 - 0 outputs. Otherwise: Undefined. [3:0] read-write DU_TR1_SEL Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. [11:8] read-write DU_TR2_SEL Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. [19:16] read-write DU_DATA0_SEL Data unit input data 'data0_in' source selection: '0': Constant '0'. '1': chip_data[7:0]. '2': io_data_in[7:0]. '3': DATA.DATA MMIO register field. [25:24] read-write DU_DATA1_SEL Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. [29:28] read-write DU_CTL Data unit component control register 0xC4 32 read-write 0x0 0x0 DU_SIZE Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. [2:0] read-write DU_OPC Data unit opcode specifies the data unit operation: '1': INCR '2': DECR '3': INCR_WRAP '4': DECR_WRAP '5': INCR_DECR '6': INCR_DECR_WRAP '7': ROR '8': SHR '9': AND_OR '10': SHR_MAJ3 '11': SHR_EQL. Otherwise: Undefined. [11:8] read-write DATA Data register 0xF0 32 read-write 0x0 0x0 DATA Data unit input data source. [7:0] read-write TCPWM0 Timer/Counter/PWM TCPWM 0x40380000 0 131072 registers 3 32768 GRP[%s] Group of counters 0x00000000 63 128 CNT[%s] Timer/Counter/PWM Counter Module 0x00000000 CTRL Counter control register 0x0 32 read-write 0xF0 0xC73737FF AUTO_RELOAD_CC0 Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. Timer, QUAD, SR modes: '0': never switch. '1': switch on a compare match 0 event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. [0:0] read-write AUTO_RELOAD_CC1 Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. Timer, QUAD, SR modes: '0': never switch. '1': switch on a compare match 1 event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. [1:1] read-write AUTO_RELOAD_PERIOD Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event. In QUAD mode, QUAD_RANGE0_CMP range mode this field is used to select the index / wrap-around capture function. '0': Captures on index (reload) event. The counter value is copied to the PERIOD register on an index (reload) event. '1': Captures when COUNTER equals 0 or 0xffff. The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff. [2:2] read-write AUTO_RELOAD_LINE_SEL Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event. [3:3] read-write CC0_MATCH_UP_EN Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. '0': compare match 0 event generation disabled when counting up '1': compare match 0 event generation enabled when counting up This field has a function in PWM and PWM_DT modes only. [4:4] read-write CC0_MATCH_DOWN_EN Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. '0': compare match 0 event generation disabled when counting down '1': compare match 0 event generation enabled when counting down This field has a function in PWM and PWM_DT modes only. [5:5] read-write CC1_MATCH_UP_EN Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. '0': compare match 1 event generation disabled when counting up '1': compare match 1 event generation enabled when counting up This field has a function in PWM and PWM_DT modes only. [6:6] read-write CC1_MATCH_DOWN_EN Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. '0': compare match 1 event generation disabled when counting down '1': compare match 1 event generation enabled when counting down This field has a function in PWM and PWM_DT modes only. [7:7] read-write PWM_IMM_KILL Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter'). '0': synchronous kill activation. Deactivates the 'dt_line_out' and 'dt_line_compl_out' signals with the next module clock ('active count' pre-scaled 'clk_counter'). '1': immediate kill activation. Immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals. This field has a function in PWM, PWM_DT and PWM_PR modes only. [8:8] read-write PWM_STOP_ON_KILL Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only. [9:9] read-write PWM_SYNC_KILL Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. [10:10] read-write PWM_DISABLE_MODE Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped. Note: The output signal of this selection can be further modified by the immediate kill logic and line_out polarity settings (CTRL.QUAD_ENCODING_MODE). [13:12] read-write Z The behavior is the same is in previous mxtcpwm (version 1). When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are NOT driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the TCPWM output 'line_out_en' to 0. When the counter is stopped upon a stop event the PWM outputs are deactivated (to the polarity defined by CTL.QUAD_ENCODING_MODE). 0 RETAIN When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM outputs are retained (keep their previous levels). While the counter is disabled or stopped the PWM outputs can be changed via LINE_SEL (when parameter GRP_SMC_PRESENT = 1). 1 L When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '0' and the PWM output 'line_compl_out' is driven as a fixed '1'. 2 H When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '1' and the PWM output 'line_compl_out' is driven as a fixed '0'. 3 UP_DOWN_MODE Determines counter direction. In QUAD mode this field acts as QUAD_RANGE_MODE field selecting between different counter range, reload value and compare / capture behavior. [17:16] read-write COUNT_UP Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. 0 COUNT_DOWN Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 1 COUNT_UPDN1 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 2 COUNT_UPDN2 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). 3 ONE_SHOT When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. [18:18] read-write QUAD_ENCODING_MODE In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode. In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUAD_ENCODING_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUAD_ENCODING_MODE[1]. [21:20] read-write X1 X1 encoding (QUAD mode) This encoding is identical with an up / down counting functionality of the following way: Rising edges of input phiA increment or decrement the counter depending on the state of input phiB (direction input). 0 X2 X2 encoding (QUAD mode) 1 X4 X4 encoding (QUAD mode) 2 UP_DOWN Up / Down rotary counting mode. Input phiA increments the counter, input phiB decrements the counter. The trigger edge detection settings apply. 3 MODE Counter mode. [26:24] read-write TIMER Timer mode 0 RSVD1 N/A 1 CAPTURE Capture mode 2 QUAD Quadrature mode Different encoding modes can be selected by QUAD_ENCODING_MODE including up/down count functionality. Different counter range, reload value and capture behavior can be selected by QUAD_RANGE_MODE (overloaded field UP_DOWN_MODE). 3 PWM Pulse width modulation (PWM) mode 4 PWM_DT PWM with deadtime insertion mode 5 PWM_PR Pseudo random pulse width modulation 6 SR Shift register mode. 7 DBG_FREEZE_EN Specifies the counter behavior in debug mode. '0': The counter operation continues in debug mode. '1': The counter operation freezes in debug mode. [30:30] read-write ENABLED Counter enable. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_IN_SEL, TR_IN_EDGE_SEL, TR_PWM_CTRL and TR_OUT_SEL register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ('tr_out0' and tr_out1'). - the counter's line outputs ('line_out' and 'line_compl_out'). [31:31] read-write STATUS Counter status register 0x4 32 read-only 0x20 0xFFFF8FF1 DOWN When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. [0:0] read-only TR_CAPTURE0 Indicates the actual level of the selected capture 0 trigger. [4:4] read-only TR_COUNT Indicates the actual level of the selected count trigger. [5:5] read-only TR_RELOAD Indicates the actual level of the selected reload trigger. [6:6] read-only TR_STOP Indicates the actual level of the selected stop trigger. [7:7] read-only TR_START Indicates the actual level of the selected start trigger. [8:8] read-only TR_CAPTURE1 Indicates the actual level of the selected capture 1 trigger. [9:9] read-only LINE_OUT Indicates the actual level of the PWM line output signal. [10:10] read-only LINE_COMPL_OUT Indicates the actual level of the complementary PWM line output signal. [11:11] read-only RUNNING When '0', the counter is NOT running. When '1', the counter is running. This field is used to indicate that the counter is running after a start/reload event and that the counter is stopped after a stop event. When a running counter operation is paused in debug state (see CTRL.DBG_PAUSE) then the RUNNING bit is still '1'. [15:15] read-only DT_CNT_L Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter). In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. [23:16] read-only DT_CNT_H High byte of 16-bit dead time counter. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8bit wide and the only the field DT_CNT_L is used as dead time counter. [31:24] read-only COUNTER Counter count register 0x8 32 read-write 0x0 0xFFFFFFFF COUNTER 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. [31:0] read-write CC0 Counter compare/capture 0 register 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. [31:0] read-write CC0_BUFF Counter buffered compare/capture 0 register 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC Additional buffer for counter CC register. [31:0] read-write CC1 Counter compare/capture 1 register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. [31:0] read-write CC1_BUFF Counter buffered compare/capture 1 register 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC Additional buffer for counter CC1 register. [31:0] read-write PERIOD Counter period register 0x20 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. [31:0] read-write PERIOD_BUFF Counter buffered period register 0x24 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Additional buffer for counter PERIOD register. In PWM_PR mode PEROD_BUFF defines the LFSR polynomial. Each bit represents a tap of the shift register which can be feed back to the MSB via an XOR tree. Examples for GRP_CNT_WIDTH = 16: - Maximum length 16bit LFSR - polynomial x^16 + x^14 + x^13 + x^11 + 1 - taps 0,2,3,5 -> PERIOD = 0x002d - period is 2^16-1 = 65535 cycles - Maximum length 8bit LFSR: - polynomial x^8 + x^6 + x^5 + x^4 + 1 - taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR) - period is 2^8-1 = 255 cycles In SR mode PERIOD_BUFF defines which tap of the shift register generates the PWM output signals. For a delay of n cycles (from capture event to PWM output) the bit CNT_WIDTH-n should be set to '1'. For a shift register function only one tap should be use, i.e. a one-hot value must be written to PERIOD_BUFF. If multiple bits in PERIOD_BUFF are set then the taps are XOR combined. [31:0] read-write LINE_SEL Counter line selection register 0x28 32 read-write 0x32 0x77 OUT_SEL Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control. This field has a function in PWM and PWM_PR modes only. Note: The output signal of this selection can be further modified by the stop / kill logic and line_out polarity setting (CTRL.QUAD_ENCODING_MODE[0]). [2:0] read-write L fixed '0' 0 H fixed '1' 1 PWM PWM signal 'line' 2 PWM_INV inverted PWM signal 'line' 3 Z The output 'line_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the output 'line_out_en' to 0. 4 RSVD5 N/A 5 RSVD6 N/A 6 RSVD7 N/A 7 COMPL_OUT_SEL Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control. This field has a function in PWM and PWM_PR modes only. Note: The output signal of this selection can be further modified by the stop / kill logic and line_compl_out polarity setting (CTRL.QUAD_ENCODING_MODE[1]). [6:4] read-write L fixed '0' 0 H fixed '1' 1 PWM PWM signal 'line' 2 PWM_INV inverted PWM signal 'line' 3 Z The output 'line_compl_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the output 'line_compl_out_en' to 0. 4 RSVD5 N/A 5 RSVD6 N/A 6 RSVD7 N/A 7 LINE_SEL_BUFF Counter buffered line selection register 0x2C 32 read-write 0x32 0x77 OUT_SEL Buffer for LINE_SEL.OUT_SEL. Can be exchanged with LINE_SEL.LINE_OUT_SEL on a terminal count event with an actively pending switch event. This field has a function in PWM and PWM_PR modes only. [2:0] read-write COMPL_OUT_SEL Buffer for LINE_SEL.COMPL.OUT_SEL. Can be exchanged with LINE_SEL.LINE_COMPL_OUT_SEL on a terminal count event with an actively pending switch event. This field has a function in PWM and PWM_PR modes only. [6:4] read-write DT Counter PWM dead time register 0x30 32 read-write 0x0 0xFFFFFFFF DT_LINE_OUT_L In PWM_DT mode, this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. Note: This field determines the low byte of the 16-bit dead time before activating 'line_out' when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating 'line_out' and 'line_compl_out'. [7:0] read-write DT_LINE_OUT_H In PWM_DT mode, this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. [15:8] read-write DT_LINE_COMPL_OUT In PWM_DT mode, this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. [31:16] read-write TR_CMD Counter trigger command register 0x40 32 read-write 0x0 0x3D CAPTURE0 SW capture 0 trigger. When written with '1', a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.ENABLED, the field is immediately set to '0'. [0:0] read-write RELOAD SW reload trigger. For HW behavior, see COUNTER_CAPTURE0 field. [2:2] read-write STOP SW stop trigger. For HW behavior, see COUNTER_CAPTURE0 field. [3:3] read-write START SW start trigger. For HW behavior, see COUNTER_CAPTURE0 field. [4:4] read-write CAPTURE1 SW capture 1 trigger. For HW behavior, see COUNTER_CAPTURE0 field. [5:5] read-write TR_IN_SEL0 Counter input trigger selection register 0 0x44 32 read-write 0x100 0xFFFFFFFF CAPTURE0_SEL Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing, the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by setting 2 and above. The settings above are used for the general purpose trigger inputs 'tr_all_cnt_in' connected to all counters selected. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. [7:0] read-write COUNT_SEL Selects one of the 256 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. Note: In the modes: TIMER, CAPTURE, PWM, PWM_DT, and SR, If the counter is externally triggered ( COUNT_SEL > 1), an external trigger will be required for each TR_CMD to execute. For example, a write to TR_CMD.START will not start the counter until the trigger selected by COUNT_SEL asserts. The next trigger will increment the counter since the counter is now running. This goes for all TR_CMD fields. [15:8] read-write RELOAD_SEL Selects one of the 256 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In these modes, it will update the counter with 0x8000 (counter midpoint) or 0x0000 depending on the QUAD_RANGE_MODE. [23:16] read-write STOP_SEL Selects one of the 256 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. [31:24] read-write TR_IN_SEL1 Counter input trigger selection register 1 0x48 32 read-write 0x0 0xFFFF START_SEL Selects one of the 256 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). [7:0] read-write CAPTURE1_SEL Selects one of the 256 input triggers as a capture 1 trigger. [15:8] read-write TR_IN_EDGE_SEL Counter input trigger edge selection register 0x4C 32 read-write 0xFFF 0xFFF CAPTURE0_EDGE A capture 0 event will copy the counter value into the CC0 register. [1:0] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 COUNT_EDGE A counter event will increase or decrease the counter by '1'. [3:2] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 RELOAD_EDGE A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. [5:4] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 STOP_EDGE A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. [7:6] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 START_EDGE A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. [9:8] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 CAPTURE1_EDGE A capture 1 event will copy the counter value into the CC1 register. [11:10] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 TR_PWM_CTRL Counter trigger PWM control register 0x50 32 read-write 0xFF 0xFF CC0_MATCH_MODE Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC0 register should be set to '0'. For a 100 percent duty cycle, the counter CC0 register should be set to larger than the counter PERIOD register. [1:0] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 OVERFLOW_MODE Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. [3:2] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 UNDERFLOW_MODE Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. [5:4] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 CC1_MATCH_MODE Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals. [7:6] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 TR_OUT_SEL Counter output trigger selection register 0x54 32 read-write 0x32 0x77 OUT0 Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event. [2:0] read-write OVERFLOW Overflow event 0 UNDERFLOW Underflow event 1 TC Terminal count event (default selection) 2 CC0_MATCH Compare match 0 event 3 CC1_MATCH Compare match 1 event 4 LINE_OUT PWM output signal 'line_out' 5 RSVD6 N/A 6 Disabled Output trigger disabled. 7 OUT1 Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event. [6:4] read-write OVERFLOW Overflow event 0 UNDERFLOW Underflow event 1 TC Terminal count event 2 CC0_MATCH Compare match 0 event (default selection) 3 CC1_MATCH Compare match 1 event 4 LINE_OUT PWM output signal 'line_out' 5 RSVD6 N/A 6 Disabled Output trigger disabled. 7 INTR Interrupt request register 0x70 32 read-write 0x0 0x7 TC Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. [0:0] read-write CC0_MATCH Counter matches CC0 register event. Set to '1', when event is detected. Write with '1' to clear bit. [1:1] read-write CC1_MATCH Counter matches CC1 register event. Set to '1', when event is detected. Write with '1' to clear bit. [2:2] read-write INTR_SET Interrupt set request register 0x74 32 read-write 0x0 0x7 TC Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write CC0_MATCH Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write CC1_MATCH Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write INTR_MASK Interrupt mask register 0x78 32 read-write 0x0 0x7 TC Mask bit for corresponding bit in interrupt request register. [0:0] read-write CC0_MATCH Mask bit for corresponding bit in interrupt request register. [1:1] read-write CC1_MATCH Mask bit for corresponding bit in interrupt request register. [2:2] read-write INTR_MASKED Interrupt masked request register 0x7C 32 read-only 0x0 0x7 TC Logical and of corresponding request and mask bits. [0:0] read-only CC0_MATCH Logical and of corresponding request and mask bits. [1:1] read-only CC1_MATCH Logical and of corresponding request and mask bits. [2:2] read-only EVTGEN0 Event generator EVTGEN 0x403F0000 0 4096 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 COMP0_STATUS Comparator structures comparator 0 status 0x4 32 read-only 0x0 0xFFFF COMP0_OUT Active comparator 'comp0_out[]' outputs. [15:0] read-only COMP1_STATUS Comparator structures comparator 1 status 0x8 32 read-only 0x0 0xFFFF COMP1_OUT DeepSleep comparator 'comp1_out_lf[]' outputs (synchronized from clk_lf to the IP clock). [15:0] read-only COUNTER_STATUS Counter status 0x10 32 read-only 0x0 0x80000000 VALID Active counter validity: '0': Invalid. '1': Valid. The COUNTER register field INT32 is only valid when VALID is '1'. The COUNTER_STATUS and COUNTER registers are non-retention registers; i.e. the COUNTER_STATUS and COUNTER registers are reset during DeepSleep power mode. After entering the Active power mode, the Active counter is initialized with the DeepSleep counter. This initialization may take up to 1 clk_lf cycle. [31:31] read-only COUNTER Counter 0x14 32 read-only 0x0 0x0 INT32 Active counter 'counter_int[31:0]' on clk_ref_div. [31:0] read-only RATIO_CTL Ratio control 0x20 32 read-write 0x0 0xC0070000 DYNAMIC_MODE Weighted average calculation (only used when DYNAMIC is '1'): '0': new RATIO value = (RATIO + measurement + 1) / 2. '1': new RATIO value = (3*RATIO + measurement + 2) / 4. '2': new RATIO value = (7*RATIO + measurement + 4) / 8. '3': new RATIO value = (15*RATIO + measurement + 8) / 16. '4': new RATIO value = (31*RATIO + measurement + 16) / 32. '5': new RATIO value = (63*RATIO + measurement + 32) / 64. '6': new RATIO value = (127*RATIO + measurement + 64) / 128. '7': new RATIO value = (255*RATIO + measurement + 128) / 256. Note: 'measurement' (integer component only) is defined as: 256 * 'number of measured clk_ref_div cycles per clk_lf cycle'. The RATIO value (integer and fractional component) is defined as: 256*RATIO.INT16 + RATIO.FRAC8 (RATIO.INT16 = RATIO >> 8 and RATIO.FRAC8 = RATIO percent 256). [18:16] read-write DYNAMIC Specifies if RATIO_CTL.VALID and RATIO are under SW or HW control: '0': SW control. '1: HW control. Auto calibration is used to derive the RATIO value. HW measures the number of clk_ref_div cycles per clk_lf cycle. This measurement is combined with the current ratio value to calculate a new ratio value. [30:30] read-write VALID Ratio value valid: '0': Invalid. '1': Valid. The RATIO register fields INT16 and FRAC8 are only valid when VALID is '1'. [31:31] read-write RATIO Ratio 0x24 32 read-write 0x0 0x0 FRAC8 Fractional component of ratio value. [15:8] read-write INT16 Integer component of ratio value. [31:16] read-write REF_CLOCK_CTL Reference clock control 0x30 32 read-write 0x0 0xFF INT_DIV Divider control for clk_ref_div: '0': Divide by 1. ... '255': Divide by '256'. Fclk_ref_div = Fclk_ref / (INT_DIV + 1) [7:0] read-write INTR Interrupt 0x700 32 read-write 0x0 0xFFFF COMP0 This interrupt cause field is activated (HW sets the field to '1') when a comparator 0 event is generated (Active counter 'counter_int[31:0]' becomes greater or equal to COMP0.INT[31:0]). [15:0] read-write INTR_SET Interrupt set 0x704 32 read-write 0x0 0xFFFF COMP0 SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write INTR_MASK Interrupt mask 0x708 32 read-write 0x0 0xFFFF COMP0 Mask bit for corresponding field in the INTR register. [15:0] read-write INTR_MASKED Interrupt masked 0x70C 32 read-only 0x0 0xFFFF COMP0 Logical and of corresponding INTR and INTR_MASK fields. [15:0] read-only INTR_DPSLP DeepSleep interrupt 0x710 32 read-write 0x0 0xFFFF COMP1 This interrupt cause field is activated (HW sets the field to '1') when a comparator 1 event is generated (DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1.INT[31:0]). [15:0] read-write INTR_DPSLP_SET DeepSleep interrupt set 0x714 32 read-write 0x0 0xFFFF COMP1 SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write INTR_DPSLP_MASK DeepSleep interrupt mask 0x718 32 read-write 0x0 0xFFFF COMP1 Mask bit for corresponding field in the INTR register. [15:0] read-write INTR_DPSLP_MASKED DeepSleep interrupt masked 0x71C 32 read-only 0x0 0xFFFF COMP1 Logical and of corresponding INTR and INTR_MASK fields. [15:0] read-only 11 32 COMP_STRUCT[%s] Comparator structure 0x00000800 COMP_CTL Comparator control 0x0 32 read-write 0x0 0x80010003 COMP0_EN Active comparator (COMP0) enable: '0': Disabled. The comparator output 'comp0_out' is '0'. '1': Enabled. [0:0] read-write COMP1_EN DeepSleep comparator (COMP1) enable: '0': Disabled. The comparator output 'comp1_out_lf' is '0'. '1': Enabled. [1:1] read-write TR_OUT_EDGE Specifies the 'tr_out' output trigger: '0': The trigger is a level sensitive trigger. The Active comparator output ('comp0_out') is reflected on 'tr_out'. '1': The trigger is an edge sensitive trigger. Activation of the Active comparator output (rising edge on 'comp0_out') results in a two cycle '1'/high pulse on 'tr_out'. [16:16] read-write ENABLED Comparator structure enable: '0': Disabled. '1': Enabled. [31:31] read-write COMP0 Comparator 0 (Active functionality) 0x4 32 read-write 0x0 0x0 INT32 This value is a 32-bit unsigned integer in the range [0, 2^32-1]. The comparator 'comp0_out' output is activated when the Active counter 'counter_int[31:0]' becomes greater or equal to COMP0. Note: SW must ensure that COMP_CTL.COMP_EN[0] is '0' when COMP0 is written. [31:0] read-write COMP1 Comparator 1 (DeepSleep functionality) 0x8 32 read-write 0x0 0x0 INT32 This value is a 32-bit unsigned integer in the range [0, 2^32-1]. The comparator 'comp1_out_lf' output is activated when the DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1. Note: SW must ensure that COMP_CTL.COMP_EN[1] is '0' when COMP1 is written. [31:0] read-write LIN0 LIN LIN 0x40500000 0 65536 registers ERROR_CTL Error control 0x0 32 read-write 0x0 0x80EF001F CH_IDX Specifies the channel index of the channel to which HW injected channel transmitter errors applies. [4:0] read-write TX_SYNC_ERROR The synchronization field is changed from 0x55 to 0x00. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation. [16:16] read-write TX_SYNC_STOP_ERROR The synchronization field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation. [17:17] read-write TX_PARITY_ERROR In LIN mode, the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]). At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. In UART mode, a data field's parity bit is inverted. [18:18] read-write TX_PID_STOP_ERROR The PID field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation. [19:19] read-write TX_DATA_STOP_ERROR The data field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. Note: Used in UART mode. [21:21] read-write TX_CHECKSUM_ERROR The checksum field is inverted. At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation. [22:22] read-write TX_CHECKSUM_STOP_ERROR The checksum field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. [23:23] read-write ENABLED Error injection enable: '0': Disabled. '1': Enabled. [31:31] read-write TEST_CTL Test control 0x4 32 read-write 0x0 0x8001001F CH_IDX Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0, CH_NR-2], as channel index CH_NR-1 is always involved in test and cannot be connected to itself. The test mode allows BOTH of the two connected channels to be tested. Note: this testing functionality simplifies SW development, but may also be used in the field to verify correct channel functionality. [4:0] read-write MODE Test mode: '0': Partial disconnect from IOSS. This mode's isolation allows for device test without relying on an external LIN transceiver. The IOSS 'tx' IO cell can be used to observe messages outside of the device. - tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. - tx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX]. - rx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. - rx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX]. - lin_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. - lin_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. '1': Full disconnect from IOSS (the IOSS/HSIOM should disconnect 'tx_out' from the 'tx' IO cell). This mode's isolation allows for device test without effecting an operational LIN cluster. - tx_in[CH_IDX] = lin_tx_out[CH_IDX]. - tx_in[CH_NR-1] = lin_tx_out[CH_IDX]. - rx_in[CH_IDX] = lin_tx_out[CH_IDX]. - rx_in[CH_NR-1] = lin_tx_out[CH_IDX]. - lin_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. - lin_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. [16:16] read-write ENABLED Test enable: '0': Disabled. Functional mode. - tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. - tx_in[CH_NR-1] = IOSS lin_tx_in[CH_NR-1]. - rx_in[CH_IDX] = IOSS lin_rx_in[CH_IDX]. - rx_in[CH_NR-1] = IOSS lin_rx_in[CH_NR-1]. - lin_tx_out[CH_IDX] = tx_out[CH_IDX]. - lin_tx_out[CH_NR-1] = tx_out[CH_NR-1]. '1': Enabled. Test mode, specific test mode is specified by MODE. [31:31] read-write 12 256 CH[%s] LIN channel structure 0x00008000 CTL0 Control 0 0x0 32 read-write 0x400C0101 0xF91F0313 STOP_BITS STOP bit periods: '0': 1/2 bit period. '1': 1 bit period. '2': 1 1/2 bit period. '3': 2 bit periods. In LIN mode, this field should be set to '1' (the default value) . In UART mode, this field can be programmed as desired. Note: receiver STOP bit frame errors can only be detected if the number of STOP bit periods is 1 or more bit period. [1:0] read-write AUTO_EN LIN transceiver auto enable: '0': Disabled. '1': Enabled. The TX_RX_STATUS.EN_OUT field is controlled by HW. [4:4] read-write BREAK_DELIMITER_LENGTH In LIN mode, this field specifies the break delimiter length: (used in header transmission, not used in header reception). '0': 1 bit period. '1': 2 bit periods (default value). '2': 3 bit periods. '3': 4 bit periods. In UART mode, this field specifies the data field size: '0': 5 bit data field. '1': 6 bit data field. '2': 7 bit data field. '3': 8 bit data field. When the data field size is less than 8 bits, the most significant (unused) bits of the DATAx.DATAy[7:0] fields should be set to '0' for the transmitter. [9:8] read-write BREAK_WAKEUP_LENGTH Break/wakeup length (minus 1) in bit periods: '0': 1 bit period. ... '10': 11 bit periods (break length for slave nodes) ... '12': 13 bit periods (break length for master nodes) ... '30': 31 bit periods. '31': Illegal (should NOT be used!!!) This field is used for transmission/reception of BOTH break and wakeup signals. Note that these functions are mutually exclusive: - When CMD.TX_HEADER is '1', the field specifies the transmitted break field. - When CMD.TX_WAKEUP is '1', the field specifies the transmitted wakeup field. - When CMD.RX_HEADER is '1', the field specifies the to be received break field. - Otherwise, the field specifies the to be received wakeup field. Per the standard, the master wakeup duration is between 250 us and 5 ms. To support uncalibrated slaves, a slave has a detection threshold of 150 us (3 bit periods at 20 kbps). After transmission of a break or wakeup signal, the INTR.TX_BREAK_WAKEUP_DONE interrupt cause is activated. After reception of a wakeup signal, the INTR.RX_BREAK_WAKEUP_DONE interrupt cause is activated. To specify longer wakeup signals in terms of absolute time (us/ms rather than bit periods), the associated PERI clock divider value can be (temporarily) increased to make the LIN bit period longer. Note: entering bus sleep mode is achieved with the 'go-to-sleep' command. [20:16] read-write MODE Mode of operation: '0': LIN mode. '1': UART mode. [24:24] read-write LIN LIN mode. 0 UART UART mode. 1 BIT_ERROR_IGNORE Specifies behavior on a detected bit error during header or response transmission: '0': Message transfer is aborted. '1': Message transfer is NOT aborted. Note: this field does NOT effect the reporting of the bit error through INTR/STATUS.TX_HEADER/RESPONSE_BIT_ERROR; i.e. bit errors are always reported. [27:27] read-write PARITY Parity mode: '0': Even parity: even number of '1' bits (including parity). '1': Odd parity. Note: Used in UART mode only. [28:28] read-write PARITY_EN Parity generation enable: '0': Disabled. No parity bit is transferred. '1': Enabled. The parity bit is transferred after the last (most significant) data field bit. Note: Used in UART mode only. [29:29] read-write FILTER_EN RX filter (for 'lin_rx_in'): '0': No filter. '1': Median 3 (default value) operates on the last three 'lin_rx_in' values. The sequences '000', '001', '010' and '100' result in a filtered value '0'. The sequences '111', '110', '101' and '011' result in a filtered value '1'. [30:30] read-write ENABLED Channel enable: '0': Disabled. If a channel is disabled, all non-retained MMIO registers (e.g. the TX_RX_STATUS, and INTR registers) have their fields reset to their default value. '1': Enabled. [31:31] read-write CTL1 Control 1 0x4 32 read-write 0x0 0x3000000 DATA_NR Number of data fields (minus 1) in the response (not including the checksum): '0': 1 data field. '1': 2 data fields. ... '7': 8 data fields. Note: master and slave nodes need to agree upon the number of data fields before message transfer. In RX_RESPONSE case, When PID (header) is received, firmware has the time of one response data byte, to modify CTL1.DATA_NR. [2:0] read-write CHECKSUM_ENHANCED Checksum mode: '0': Classic mode. PID field is NOT included in the checksum calculation. '1': Enhanced mode. PID field is included in the checksum calculation. This mode requires special attention when the master node transmits the header and a (different) slave node transmits the response: the slave node will use the calculated partial checksum over the received PID field as a starting point for the calculation over the to be transmitted data fields. Note: If the frame identifier ID[5:0] is 0x3c or 0x3d, the classic mode will ALWAYS be used for transmission and assumed for reception, independent of the CHECKSUM_ENHANCED value. [8:8] read-write FRAME_TIMEOUT Specifies the maximum allowed length (timeout value) for a frame, frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and Tresponse_max = 1.4 x Tresponse_nom). The nominal header length Theader_nom is 34 bit periods and the nominal response length Tresponse_nom is 10 * (data_nr + 1) bit periods (data_nr is the number of data fields) Note: the LIN specification specifies the following: 'Tools and tests shall check the Tframe_max (= Theader_max + Tresponse_max). Nodes shall not check this time. The receiving node of the frame shall accept the frame up to the next frame slot (i.e. next break field), even if it is longer then Tframe_max).' [23:16] read-write FRAME_TIMEOUT_SEL Specifies the frame timeout mode: '0': No timeout functionality (default value). '1': Frame mode: detects timeout from the start of break field to checksum field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34+20 bit periods (header and a response with 1 data field). '2': Frame header mode: detects timeout from the start of break field to PID field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34 bit periods (header). '3': Frame response mode: detects timeout from the PID field STOP bits (exclusive) to checksum field STOP bits (the response space is included in the frame response). The minimum FRAME_TIMEOUT value is 20 bit periods (response with 1 data field). [25:24] read-write STATUS Status 0x8 32 read-only 0x0 0x1F03333F DATA_IDX Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0, DATA1, PID_CHECKSUM)) : '0': No data fields transferred. '1': Data field 1 transferred. ... '7': Data fields 1, 2, 3, ... and 7 transferred. '8': Data fields 1, 2, 3, ... and 8 transferred. '9': Data fields 1, 2, 3, ..., 8 and checksum field transferred. '10'-'15': Unused. Set to '0' on the start of a TX_HEADER or RX_HEADER command. [3:0] read-only HEADER_RESPONSE Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'): '0': Frame header being transferred. '1': Frame response being transferred. [4:4] read-only RX_DATA0_FRAME_ERROR Frame response, first data field frame error. HW sets this field to '1' when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command), and this data byte is 0x00. HW clears this field to '0' at the falling edge of SYNC start bit (after INTR.RX_HEADER_BREAK_WAKEUP_DONE). This field is used together with INTR.RX_RESPONSE_FRAME_ERROR to distinguish 'no response', 'error response' and 'correct response' scenarios. Note: The ongoing message transfer is NOT aborted. [5:5] read-only TX_BUSY Transmitter busy. - Set to '1' on the start of the following commands: TX_HEADER, TX_RESPONSE, TX_WAKEUP. - Set to '0' on successful completion of previous commands or when an error is detected. In 'TX_HEADER, RX_RESPONSE' case, set to '0' at the start bit falling edge in the first response data byte, after header transmission [8:8] read-only RX_BUSY Receiver busy. - Set to '1' on the start of the following commands: RX_HEADER, RX_RESPONSE. in RX_HEADER case, set at Break filed rising edge. in RX_RESPONSE case, set at the start bit falling edge in the first response data byte. - Set to '0' on successful completion of previous commands or when an error is detected. [9:9] read-only TX_DONE Transmitter done: - Set to '0' on the start of a new command. - Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble): - TX_HEADER. - TX_HEADER, TX_RESPONSE. - RX_HEADER, TX_RESPONSE. - TX_WAKEUP. [12:12] read-only RX_DONE Receiver done: - Set to '0' on the start of a new command. - Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble): - RX_HEADER, RX_RESPONSE. - TX_HEADER, RX_RESPONSE. [13:13] read-only TX_HEADER_BIT_ERROR Copy of INTR.TX_HEADER_BIT_ERROR. [16:16] read-only TX_RESPONSE_BIT_ERROR Copy of INTR.TX_RESPONSE_BIT_ERROR. [17:17] read-only RX_HEADER_FRAME_ERROR Copy of INTR.RX_HEADER_FRAME_ERROR. [24:24] read-only RX_HEADER_SYNC_ERROR Copy of INTR.RX_HEADER_SYNC_ERROR. [25:25] read-only RX_HEADER_PARITY_ERROR Copy of INTR.RX_HEADER_PARITY_ERROR. [26:26] read-only RX_RESPONSE_FRAME_ERROR Copy of INTR.RX_RESPONSE_FRAME_ERROR. [27:27] read-only RX_RESPONSE_CHECKSUM_ERROR Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR. [28:28] read-only CMD Command 0x10 32 read-write 0x0 0x307 TX_HEADER SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected): - TX_HEADER - TX_HEADER, TX_RESPONSE. - TX_HEADER, RX_RESPONSE. - RX_HEADER, TX_RESPONSE. - RX_HEADER, RX_RESPONSE. - TX_WAKEUP. The header is transmitted when the PID field STOP bits are transmitted (INTR.TX_HEADER_DONE). HW sets this field to '1', when the 'tr_cmd_tx_header' input trigger is activated. This allows for time triggered LIN message transfer. HW driven time triggered transfer eliminates the jitter that is typically associated with SW driven transfer. In UART mode, a single data field (DATA0.DATA1) is transmitted. [0:0] read-write TX_RESPONSE SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected). The response is transmitted when the checksum field STOP bits are transmitted (INTR.TX_RESPONSE_DONE). [1:1] read-write TX_WAKEUP SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected). The command generates CTL.BREAK_WAKEUP_LENGTH bit periods in the dominant state (low/'0') and transitions to the recessive state (high/'1') (INTR.TX_WAKEUP_DONE). [2:2] read-write RX_HEADER SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode). The header is received when the PID field STOP bits are received (INTR.RX_HEADER_DONE). Typically, a slave node SW sets both RX_HEADER and RX_RESPONSE to '1', anticipating a transfer of a response from the master node to this slave node. After receipt of the header PID field (INTR.RX_HEADER_PID_DONE is activated), the slave node may decide to set TX_RESPONSE to '1' (which has a higher priority than RX_RESPONSE) to transmit a response. the Break detection is performed regardless of CMD.RX_HEADER. INTR.RX_BREAK_WAKEUP_DONE will trigger at LIN_RX rising edge, when the low pulse meet CTL0.BREAK_WAKEUP_LENGTH. when Break is detected, HW check CMD.RX_HEADER before entering SYNC byte processing state. when RX_HEADER is cleared, SW has at least 11 bit times to set RX_HEADER again, before next Break is detected (RX_BREAK_WAKEUP_DONE). in this case, there is no gap, Break will never be missed. In UART mode, a single data field in received (in DATA0.DATA1). HW set this field to '0' when the data field is received, or when an error is detected. [8:8] read-write RX_RESPONSE SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected). The response is received when the checksum field STOP bits are received (INTR.RX_RESPONSE_DONE). [9:9] read-write TX_RX_STATUS TX/RX status 0x60 32 read-write 0x5000000 0x5000000 SYNC_COUNTER Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field, this fields reflects the duration of the synchronization field. Ideally, SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of eight bit period of 16 LIN channel clock periods each). - If SYNC_COUNTER is less than 128, the LIN channel clock is too slow and the PERI/PCLK divider value should be decreased. - If SYNC_COUNTER is greater than 128, the LIN channel clock is too fast and the PERI/PCLK divider value should be increased. The biggest master-slave clock discrepancy occurs when the master is slow and the slave is fast or vice versa. At a 0.5 percent master inaccuracy and a 14 percent slave inaccuracy, this results in the extreme synchronization values of (.86 * 128) / 1.005 = 109.5 and (1.14 *128) / 0.995 = 146.6. We add a little margin for a valid range of [106, 152]. Note: Only slave nodes with imprecise clocks require clock resynchronization. Master and slave nodes with precise clocks do NOT require clock resynchronization. [7:0] read-only TX_IN LIN transmitter input ('tx_in', 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality. [16:16] read-only RX_IN LIN receiver input ('rx_in', 'lin_rx_in' in functional mode). [17:17] read-only TX_OUT LIN transmitter output ('tx_out', 'lin_tx_out'). [24:24] read-only EN_OUT LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: '0': Disabled. '1': Enabled. If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver: - Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble. - After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble. Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers. [26:26] read-write PID_CHECKSUM PID and checksum 0x80 32 read-write 0x0 0x0 PID Header protected identifier (PID). - Bits 5 down to 0: frame identifier ID[5:0]. Frame identifier 0x3c is for a 'master request' frame, 0x3d is for a 'slave response' frame, 0x3e and 0x3f are for future LIN enhancements. Frame identifier ID[5:4] is optionally used for length control; i.e. specifies the number of response data fields. - Bits 1 down to 0: parity bits P[1] and P[0]. - P[1] = ! (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) - P[0] = (ID[4] ^ ID[2] ^ ID[1] ^ ID[0]) Transmission: To be transmitted PID field. SW needs to calculate the PID field parity bits P[1] and P[0]. Reception: Received PID field. Slave node SW uses the PID field to determine how to handle the response for a received frame header: TX_RESPONSE or RX_RESPONSE. [7:0] read-write CHECKSUM Checksum. Transmission: HW calculated checksum (SW does not need to calculate the checksum) over the transmitted PID field (optional per CTL.CHECKSUM_ENHANCED) and data fields. Reception: Received checksum. Note that in case of a RX_CHECKSUM_ERROR, SW can use the received PID field and the received data fields to calculate the correct checksum value. [15:8] read-only DATA0 Response data 0 0x84 32 read-write 0x0 0x0 DATA1 Data field 1. Transmission: To be transmitted data field. SW provides data field. Reception: Received data field. SW uses the data field. [7:0] read-write DATA2 Data field 2. [15:8] read-write DATA3 Data field 3. [23:16] read-write DATA4 Data field 4. [31:24] read-write DATA1 Response data 1 0x88 32 read-write 0x0 0x0 DATA5 Data field 5. [7:0] read-write DATA6 Data field 6. [15:8] read-write DATA7 Data field 7. [23:16] read-write DATA8 Data field 8. [31:24] read-write INTR Interrupt 0xC0 32 read-write 0x0 0x1F036F07 TX_HEADER_DONE HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically: - When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer. - When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. Note: used in UART mode. [0:0] read-write TX_RESPONSE_DONE HW sets this field to '1', when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. [1:1] read-write TX_WAKEUP_DONE HW sets this field to '1', when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal. [2:2] read-write RX_HEADER_DONE HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically: - When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer. - When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. Note: used in UART mode. [8:8] read-write RX_RESPONSE_DONE HW sets this field to '1', when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. Note: activation implies that RX_RESPONSE_FRAME_ERROR and RX_RESPONSE_CHECKSUM_ERROR are not activated during response reception [9:9] read-write RX_BREAK_WAKEUP_DONE HW sets this field to '1', when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal. The break or wakeup detection is always enabled, regardless of CMD register setting. [10:10] read-write RX_HEADER_SYNC_DONE HW sets this field to '1', when a synchronization field is received (including trailing STOP bits). [11:11] read-write RX_NOISE_DETECT HW sets this field to '1', when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line. Note: The ongoing frame transfer is NOT aborted. Note: Used in UART mode. [13:13] read-write TIMEOUT HW sets this field to '1', when a frame, frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL). Note: The ongoing frame transfer is NOT aborted. [14:14] read-write TX_HEADER_BIT_ERROR HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an indication of bus collisions on the LIN line. The match is performed for the Wakeup, Break, SYNC and the PID fields (for the START bit, data Byte and STOP bit). Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. Note: Used in UART mode. [16:16] read-write TX_RESPONSE_BIT_ERROR HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission). The match is performed for the data fields and the checksum field (for the START bit, data Byte and STOP bit). Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. [17:17] read-write RX_HEADER_FRAME_ERROR HW sets this field to '1', when the received START or STOP bits have an unexpected value (during header reception). Note: The ongoing message transfer is aborted (INTR.RX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. Note: Used in UART mode. [24:24] read-write RX_HEADER_SYNC_ERROR HW sets this field to '1', when the received synchronization field is not received within the synchronization counter range [106, 152] (see TX_RX_STATUS.SYNC_COUNTER). Note: The ongoing message transfer is aborted (INTR.RX_HEADER_SYNC_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. [25:25] read-write RX_HEADER_PARITY_ERROR HW sets this field to '1', when the received PID field has a parity error. Note: The ongoing message transfer is aborted (INTR.RX_PID_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. +G119 HW sets this field to '1', when the received data field has a parity error (when CTL0.PARITY_EN is '1'). [26:26] read-write RX_RESPONSE_FRAME_ERROR HW sets this field to '1', when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command, if the received data byte is 0x00. (STATUS.RX_DATA0_FRAME_ERROR is used instead). Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. [27:27] read-write RX_RESPONSE_CHECKSUM_ERROR HW sets this field to '1', when the calculated checksum over the received PID and data fields is not the same as the received checksum. Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. [28:28] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x1F036F07 TX_HEADER_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write TX_RESPONSE_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [1:1] read-write TX_WAKEUP_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [2:2] read-write RX_HEADER_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [8:8] read-write RX_RESPONSE_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [9:9] read-write RX_BREAK_WAKEUP_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [10:10] read-write RX_HEADER_SYNC_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [11:11] read-write RX_NOISE_DETECT Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [13:13] read-write TIMEOUT Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [14:14] read-write TX_HEADER_BIT_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [16:16] read-write TX_RESPONSE_BIT_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [17:17] read-write RX_HEADER_FRAME_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [24:24] read-write RX_HEADER_SYNC_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [25:25] read-write RX_HEADER_PARITY_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [26:26] read-write RX_RESPONSE_FRAME_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [27:27] read-write RX_RESPONSE_CHECKSUM_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [28:28] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x1F036F07 TX_HEADER_DONE Mask for corresponding field in INTR register. [0:0] read-write TX_RESPONSE_DONE Mask for corresponding field in INTR register. [1:1] read-write TX_WAKEUP_DONE Mask for corresponding field in INTR register. [2:2] read-write RX_HEADER_DONE Mask for corresponding field in INTR register. [8:8] read-write RX_RESPONSE_DONE Mask for corresponding field in INTR register. [9:9] read-write RX_BREAK_WAKEUP_DONE Mask for corresponding field in INTR register. [10:10] read-write RX_HEADER_SYNC_DONE Mask for corresponding field in INTR register. [11:11] read-write RX_NOISE_DETECT Mask for corresponding field in INTR register. [13:13] read-write TIMEOUT Mask for corresponding field in INTR register. [14:14] read-write TX_HEADER_BIT_ERROR Mask for corresponding field in INTR register. [16:16] read-write TX_RESPONSE_BIT_ERROR Mask for corresponding field in INTR register. [17:17] read-write RX_HEADER_FRAME_ERROR Mask for corresponding field in INTR register. [24:24] read-write RX_HEADER_SYNC_ERROR Mask for corresponding field in INTR register. [25:25] read-write RX_HEADER_PARITY_ERROR Mask for corresponding field in INTR register. [26:26] read-write RX_RESPONSE_FRAME_ERROR Mask for corresponding field in INTR register. [27:27] read-write RX_RESPONSE_CHECKSUM_ERROR Mask for corresponding field in INTR register. [28:28] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x1F036F07 TX_HEADER_DONE Logical AND of corresponding INTR and INTR_MASK fields. [0:0] read-only TX_RESPONSE_DONE Logical AND of corresponding INTR and INTR_MASK fields. [1:1] read-only TX_WAKEUP_DONE Logical AND of corresponding INTR and INTR_MASK fields. [2:2] read-only RX_HEADER_DONE Logical AND of corresponding INTR and INTR_MASK fields. [8:8] read-only RX_RESPONSE_DONE Logical AND of corresponding INTR and INTR_MASK fields. [9:9] read-only RX_BREAK_WAKEUP_DONE Logical AND of corresponding INTR and INTR_MASK fields. [10:10] read-only RX_HEADER_SYNC_DONE Logical AND of corresponding INTR and INTR_MASK fields. [11:11] read-only RX_NOISE_DETECT Logical AND of corresponding INTR and INTR_MASK fields. [13:13] read-only TIMEOUT Logical AND of corresponding INTR and INTR_MASK fields. [14:14] read-only TX_HEADER_BIT_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [16:16] read-only TX_RESPONSE_BIT_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [17:17] read-only RX_HEADER_FRAME_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [24:24] read-only RX_HEADER_SYNC_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [25:25] read-only RX_HEADER_PARITY_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [26:26] read-only RX_RESPONSE_FRAME_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [27:27] read-only RX_RESPONSE_CHECKSUM_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [28:28] read-only CXPI0 CXPI CXPI 0x40510000 0 65536 registers ERROR_CTL Error control 0x0 32 read-write 0x0 0x821C001F CH_IDX Specifies the channel index of the channel to which HW injected channel transmitter errors applies. [4:0] read-write TX_CRC_ERROR The crc field is inverted. At the receiver, this should result in INTR.RX_CRC_ERROR activation. [18:18] read-write TX_PID_PARITY_ERROR In cxpi mode, the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]). At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. [19:19] read-write TX_DATA_LENGTH_ERROR The transmitter continues to send logical '0' (during IFS) after CRC field is transmitted. At the receiver, this should result in INTR.RX_DATA_LENGTH_ERROR activation. At the transmitter, this should result in INTR.TX_DATA_LENGTH_ERROR activation. [20:20] read-write TX_DATA_STOP_ERROR The data field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_FRAME_ERROR activation. At the transmitter, this should result in INTR.TX_FRAME_ERROR activation. [25:25] read-write ENABLED Error injection enable: '0': Disabled. '1': Enabled. [31:31] read-write TEST_CTL Test control 0x4 32 read-write 0x0 0x8001001F CH_IDX Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0, CH_NR-2], as channel index CH_NR-1 is always involved in test and cannot be connected to itself. The test mode allows BOTH of the two connected channels to be tested. Note: this testing functionality simplifies SW development, but may also be used in the field to verify correct channel functionality. [4:0] read-write MODE Test mode: '0': Partial disconnect from IOSS. This mode's isolation allows for device test without relying on an external cxpi transceiver. The IOSS 'tx' IO cell can be used to observe messages outside of the device. - tx_in[CH_IDX] = IOSS cxpi_tx_in[CH_IDX]. - tx_in[CH_NR-1] = IOSS cxpi_tx_in[CH_IDX]. - rx_in[CH_IDX] = IOSS cxpi_tx_in[CH_IDX]. - rx_in[CH_NR-1] = IOSS cxpi_tx_in[CH_IDX]. - cxpi_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. - cxpi_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. '1': Full disconnect from IOSS (the IOSS/HSIOM should disconnect 'tx_out' from the 'tx' IO cell). This mode's isolation allows for device test without effecting an operational cxpi cluster. - tx_in[CH_IDX] = cxpi_tx_out[CH_IDX]. - tx_in[CH_NR-1] = cxpi_tx_out[CH_IDX]. - rx_in[CH_IDX] = cxpi_tx_out[CH_IDX]. - rx_in[CH_NR-1] = cxpi_tx_out[CH_IDX]. - cxpi_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. - cxpi_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. [16:16] read-write PARTIAL_DISCONNECT Partial disconnect 0 FULL_DISCONNECT Full disconnect 1 ENABLED Test enable: '0': Disabled. Functional mode. - tx_in[CH_IDX] = IOSS cxpi_tx_in[CH_IDX]. - tx_in[CH_NR-1] = IOSS cxpi_tx_in[CH_NR-1]. - rx_in[CH_IDX] = IOSS cxpi_rx_in[CH_IDX]. - rx_in[CH_NR-1] = IOSS cxpi_rx_in[CH_NR-1]. - cxpi_tx_out[CH_IDX] = tx_out[CH_IDX]. - cxpi_tx_out[CH_NR-1] = tx_out[CH_NR-1]. '1': Enabled. Test mode, specific test mode is specified by MODE. [31:31] read-write FUNCTIONAL_MODE Functional mode 0 TEST_MODE Test mode 1 4 256 CH[%s] CXPI channel structure 0x00008000 CTL0 Control 0 0x0 32 read-write 0x10 0xC9FF0191 MODE Mode of operation: '0': NRZ mode. '1': PWM mode. [0:0] read-write NRZ NRZ mode 0 PWM PWM mode 1 AUTO_EN CXPI transceiver auto enable: '0': Disabled. '1': Enabled. The TX_RX_STATUS.EN_OUT field is controlled by HW. [4:4] read-write RXPIDZERO_CHECK_EN Receive PID Zero Check Enable. 0 - No action if received PID[6:0] = 0 and PID[7]=1'b1. 1 - If received PID[6:0] = 0 and PID[7]=1'b1, HW (slave) does not clear CMD.RX_HEADER and will anticipate receiving header again (CMD.TX_HEADER=0). If CMD.TX_HEADER=1 in the same scenario, then HW (slave) clears CMD.RX_HEADER upon receiving the header follow by transmit PID. This mode is useful for case where polling method is used and CXPI controller is configured as slave. This would reduce dependency on SW to react to the header received within IBS=1. [7:7] read-write FILTER_EN RX filter enable (for 'cxpi_rx_in') '0': No filter '1': Median 3 (default value) operates on the last three 'cxpi_rx_in' values. The sequences '000', '001', '010', and '100' result in a filtered value '0'. The sequences '111', '110', '101', and '011' result in a filtered value '1'. [8:8] read-write IFS Inter Frame Space in bit periods: '0'' Invalid. ... '10': 10 bit periods ... '31': 31 bit periods Values of <10 are not allowed. This field is used for transmission/reception for adding waiting inter frame space. Note that after a valid transaction (after CRC), HW waits for 10 bits as EOF. Hence, by setting CTL0.IFS=0xA means that HW will wait for 10bits before transmitting a new transaction (not including the EOF). Note: 0 is not allowed when IFS_WAIT=1. SW needs to ensure it has program valid values before it can set IFS_WAIT=1. If IFS_WAIT=1 after timeout occurs, the value of CTL0.IFS would need to consider the timeout count i.e. (IFS needed - CTL2.TIMEOUT_LENGTH-1) to get the total idle time. For example if TIMEOUT_LENGTH=9 and IFS needed is 20, then CTL0.IFS is set to 10. [20:16] read-write IBS Inter Byte Space in bit periods: '0' No offset. '1' 1 IBS is inserted per every byte frame. ... '9' 9 IBS are inserted per every byte frame. Values >9 are invalid per spec. This field is used to control number of IBS after every byte frame when transmitting message frame. Note that this field is the minimum IBS inserted for every byte frame as the SW may require some time to prepare the response when it receives the PID. When receiving, this field is ignored with the exception of receiving header and transmitting response. For receiving header and transmitting response, SW can enable IBS insertion by setting TIMEOUT_SEL=1/2 prior to setting CMD.RX_HEADER=1 and CMD.RX_RESPONSE=1. If the received header corresponds to transmit response, SW clears CMD.RX_RESPONSE =0 and sets TX FIFO and CMD.TX_RESPONSE=1. HW waits for minimum IBS before transmit response (if timeout has not occurred yet). It is prohibit to program IBS>TIMEOUT_LENGTH. This field should not be changed during inflight transaction including EOF. [24:21] read-write BIT_ERROR_IGNORE Specifies behavior on a detected bit error during header or response transmission: '0': Message transfer is aborted. '1': Message transfer is NOT aborted. Note: This field does NOT effect the reporting of the bit error through INTR/STATUS.TX_BIT_ERROR; i.e. bit errors are always reported. Note: This field must not be set to '1' when it is NRZ mode. This is due to delay in transceiver will cause the transmitter behavior undefined when error occurs. [27:27] read-write ABORT_TX_MSG Message transfer is aborted 0 CONT_TX_MSG Message transfer is NOT aborted 1 MASTER CXPI master mode. '0': Indicates CXPI as slave node. '1': Indicates CXPI as master node. This bit is only valid if ENABLED=1. SW needs to set only 1 node as master within the same CXPI cluster. SW needs to set this bit either at the same time as ENABLED or before ENABLED is set. If SW needs to change the controller to different mode, it needs to make sure that HW is quiescent before doing so. [30:30] read-write SLAVE_MODE Slave mode 0 MASTER_MODE Master mode 1 ENABLED Channel enable: '0': Disabled. If a channel is disabled, CMD, STATUS, INTR MMIO registers will have their fields reset to their default value. '1': Enabled. [31:31] read-write DISABLED Disabled 0 ENABLED Enabled 1 CTL1 Control 1 0x4 32 read-write 0x0 0x7FDFF1FF T_LOW1 Low count for logic 1. This is valid only for PWM mode. The count value here indicates the number of clocks per clk_cxpi_ch to drive a '0' at CXPI bus before releasing it to indicate a logical '1'. 0: means 1 clock. 1: means 2 clocks .. 15: means 16 clocks. .. 399: means 400 clocks. Any value above 399 is invalid. Note that for NRZ mode, this field is ignored. Note that this field is used for TX. [8:0] read-write T_LOW0 Low count for logic 0. This is valid only for PWM mode. The count value here indicates the number of clocks per clk_cxpi_ch to drive a '0' at CXPI bus before releasing it to indicate a logical '0'. 0: means 1 clock. 1: means 2 clocks .. 15: means 16 clocks .. 399: means 400 clocks Any value above 399 is invalid. Note that for NRZ mode, this field is ignored. Note that this field is used for TX. [20:12] read-write T_OFFSET The value of offset that is used for sampling the 'rx'. The value of this counter is used in HW as below. - 0 : means 1 clock after detecting falling edge of 'rx' - 1 : means 2 clocks after detecting falling edge of 'rx' .. - 7 : means 8 clocks after detecting falling edge of 'rx' .. - 15 : means 16 clocks after detecting falling edge of 'rx' .. - 399 : means 400 clocks after detecting falling edge of 'rx' Any value above 399 is invalid. [30:22] read-write CTL2 Control 2 0x8 32 read-write 0x0 0xC00F3F03 RETRY Number of retries after arbitration lost. '0': No retries. .. '3': 3 retries. HW will immediately retry after arbitration lost i.e. after the message frame that won the arbitration is complete and fulfilled IFS. If SW wants to manage the retransmission then SW can program RETRY =0. In this case, HW will not retry after arbitration lost and will set TX_HEADER_ARB_LOST bit. SW needs to trigger HW to resend by programming the CMD fields again. [1:0] read-write T_WAKEUP_LENGTH Specifies the wake up pulse low period in Tbits that is transmitted during Standby mode. '0': 1 bit period '1': 2 bit period .. '49': 50 bit period Any value above 49 is invalid. This field is only valid if TX_WAKE_PULSE is set to 1. [13:8] read-write TIMEOUT_LENGTH Timeout Length (in Tbits). Specifies the number of Tbits to exceed timeout between frame bytes within a message frame. CXPI spec states that the maximum allowed inter byte space (IBS) is 9Tbits. This field is valid only when TIMEOUT_SEL=1/2. '0' - 1Tbit '1' - 2Tbits .. '9' - 10Tbits Values >9 is invalid per CXPI spec. Note for NRZ mode, although there are propagation delay from transceiver to CXPI controller, the delay is cancelled out as the timeout is compared on the RX (for transmit case, HW waits for the feedback on RX). [19:16] read-write TIMEOUT_SEL Timeout Select. '0' - Timeout check is disabled. HW clears timeout counter. '1' - Timeout check is enabled and HW will refer to TIMEOUT_LENGTH as number of Tbits allowed between header and response. '2' - Timeout check is enabled to check header-header, header-response, and header-header-response within a message frame to be space within TIMEOUT_LENGTH bit time. '3' - invalid For '1', HW will restart/start timeout counter after transmitting/receiving header. HW will hold the counter if timeout until the next header is transmitted or received. Timeout will cause HW to stop transmission of the current message frame together with interrupt to SW. For receive, HW abort reception of the frame if timeout occurs while waiting for receiving response and notify SW with interrupt. For '2', HW will re-start/start timeout counter after receiving any frame bytes within a message frame. HW will hold the counter if timeout until the IFS. Timeout will cause HW to stop transmission of the current message frame and notify SW with interrupt. For receive, HW will abort reception of the message frame if timeout occurs while waiting for receiving response and notify SW with interrupt. For all cases, HW stops counting when it is out of a message frame such as IFS or CXPI bus IDLE. If the timeout counter > TIMEOUT_LENGTH, then it will set the INTR.TIMEOUT=1. Note that, TIMEOUT_SEL=1/2 also enables the count for IBS between receive header and transmit response on top of timeout check. [31:30] read-write TIMEOUT_DISABLED Timeout check is disabled. 0 TIMEOUT_CHECK_BTW_HDR_RSP Timeout check is enabled and HW will refer to TIMEOUT_LENGHT as number of Tbits allowed between header and response. 1 TIMEOUT_CHECK_BTW_HDR_HDR_RSP Timeout check is enabled to check header-header, header-response, and header-header-response within a message frame to be space within TIMEOUT_LENGTH bit time. 2 STATUS Status 0xC 32 read-only 0x0 0x7FFC3313 RETRIES_COUNT Retries count. The value reflects the number of retries that HW tries to transmit a header/response. HW will reset counter (either case below): 1. after successfully transmit the retry attempt 2. SW clears the CMD.TX_HEADER='0' 3. HW clearing CMD.TX_HEADER=0 due to errors (TX_BIT_ERROR, TX_HEADER_ARB_LOST, TX_OVERFLOW_ERROR, TX_UNDERFLOW_ERROR, TX_DATA_LENGTH_ERROR, and TX_FRAME_ERROR) [1:0] read-only HEADER_RESPONSE Frame header/response identifier (only valid when TX_BUSY or RX_BUSY is '1') '0' - Frame header being transferred. '1' - Frame response being transferred. [4:4] read-only TX_BUSY Transmitter busy. - Set to '1' on the start of the following commands: TX_HEADER, TX_RESPONSE. - Set to '0' on successful completion of previous commands or when an error is detected. [8:8] read-only RX_BUSY Receiver busy. - Set to '1' on the start of the following commands: RX_HEADER, RX_RESPONSE. - Set to '0' on successful completion of previous commands or when an error is detected. [9:9] read-only TX_DONE Transmitter done: - Set to '0' on the start of a new command. - Set to '1' on successful completion of the following command sequences: - TX_HEADER. - TX_HEADER, TX_RESPONSE. - RX_HEADER, TX_RESPONSE. [12:12] read-only RX_DONE Receiver done: - Set to '0' on the start of a new command. - Set to '1' on successful completion of the following commmand sequences: - RX_HEADER, RX_RESPONSE. - TX_HEADER, RX_RESPONSE. [13:13] read-only TIMEOUT Copy of INTR.TIMEOUT [18:18] read-only TX_HEADER_ARB_LOST Copy of INTR.TX_HEADER_ARB_LOST [19:19] read-only TX_BIT_ERROR Copy of INTR.TX_BIT_ERROR. [20:20] read-only RX_CRC_ERROR Copy of INTR.RX_CRC_ERROR. [21:21] read-only RX_HEADER_PARITY_ERROR Copy of INTR.RX_HEADER_PARITY_ERROR. [22:22] read-only RX_DATA_LENGTH_ERROR Copy of INTR.RX_DATA_LENGTH_ERROR. [23:23] read-only TX_DATA_LENGTH_ERROR Copy of INTR.TX_DATA_LENGTH_ERROR. [24:24] read-only RX_OVERFLOW_ERROR Copy of INTR.RX_OVERFLOW_ERROR. [25:25] read-only TX_OVERFLOW_ERROR Copy of INTR.TX_OVERFLOW_ERROR. [26:26] read-only RX_UNDERFLOW_ERROR Copy of INTR.RX_UNDERFLOW_ERROR. [27:27] read-only TX_UNDERFLOW_ERROR Copy of INTR.TX_UNDERFLOW_ERROR. [28:28] read-only RX_FRAME_ERROR Copy of INTR.RX_FRAME_ERROR. [29:29] read-only TX_FRAME_ERROR Copy of INTR.TX_FRAME_ERROR. [30:30] read-only CMD Command 0x10 32 read-write 0x0 0x33F TX_HEADER SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error (such as bit error if bit_ignore=0, arbitration loss, tx data length error. For timeout please refer to SAS) is detected): - TX_HEADER - TX_HEADER, TX_RESPONSE. - TX_HEADER, RX_RESPONSE. The above is for transmission of PID without prior transmission of PTYPE. The header is transmitted when the PID field STOP bits are transmitted (INTR.TX_HEADER_DONE). HW sets this field to '1', when the 'tr_cmd_tx_header' input trigger is activated. This allows for time triggered CXPI message transfer. HW driven time triggered transfer eliminates the jitter that is typically associated with SW driven transfer. SW clears this field to '0', when it wants to cancel a pending request. Note that if SW clears this field to '0' while HW is already in the middle of the request, then the cancel will be ignored. The cancel request can happen when HW is pending a retry when it is still servicing the current transaction. Or the cancel request can occur when HW is checking IFS/bus idle-ness. Note that if PTYPE (TX_HEADER) is transmitted follow by receive response (RX_RESPONSE) or no response, HW clears TX_HEADER right after transmitting PTYPE. [0:0] read-write TX_RESPONSE SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected). - TX_HEADER, TX_RESPONSE. - RX_HEADER, TX_RESPONSE. SW can also clear this field to '0' if SW wants to cancel the TX_RESPONSE. The response is transmitted when the CRC are transmitted (INTR.TX_RESPONSE_DONE). [1:1] read-write SLEEP SW sets this field to '1' to direct HW to sleep mode. HW transits from Normal to Sleep upon SLEEP=1 and both TX and RX is idle. HW sets this field to '0' when it is in Sleep mode. Note that, SW needs to manage the entry to sleep mode by checking the conditions are met before initiating sleep mode e.g. all slave nodes supports sleep and on transmitting sleep frames to indicate sleep to all slave nodes.SW shall not program SLEEP=1 when HW is executing TX_WAKEUP_PULSE command. If SW programs SLEEP=1 during HW executing TX_WAKEUP_PULSE command, it will cause HW to abruptly stop transmitting wakeup pulse as below: 1. HW not clearing TX_WAKEUP_PULSE 2. HW not setting TX_WAKEUP_DONE 3. HW outputting TX_OUT=0. [2:2] read-write WAKE_TO_STANDBY SW sets this field to '1' to direct HW to wake up from Sleep mode to Standby mode. SW clears this field to '0' from '1' when it wants to direct HW from Standby to Normal mode. HW clears this field to '0' when it is in Normal mode or back to Sleep mode from Standby mode. For the case of CXPI master mode, HW will move its power mode from Sleep->Standby when this field is set to '1'. When SW clears this field is from '1' to '0' in Standby mode, HW will move to Normal mode while HW starts transmitting clock. To transmit wake pulse, SW need to program TX_WAKE_PULSE accordingly in Standby mode before entering Normal. For the case of CXPI slave mode and PWM mode, HW will move power mode from Sleep->Standby when this field is set to '1'. HW will wait for detection of clock before moving from Standby->Normal. SW clearing this field to '0' will have no effect. For the case of CXPI slave mode and NRZ mode, HW will move power mode from Sleep->Standby when this field is set to '1'. HW needs to be directed by SW by clearing this field to '0' to move from Standby->Normal after SW has detected clock through another IP (e.g. MXTCPWM). [3:3] read-write TX_WAKE_PULSE SW sets this field to '1' to direct HW to send wake up pulse. HW will transmit wake up pulse in Standby state only. HW will ignore this field when it's not in Standby state. '1' - HW will drive CXPI bus to low for period dictated by T_WAKEUP_LENGTH. '0:'- No wake up pulse HW clears this field to '0' after it transmit the pulse per T_WAKEUP_LENGTH. For the case where more than 1 wake pulses are required, SW is expected to set this field to '1' again (after this field is cleared to '0') per the number of times the wake pulse is required. [4:4] read-write IFS_WAIT SW sets this field to '1' to wait for IFS. HW clears this field to '0' after it detects logical '1' based on IFS. HW will keep this field to '1' if it detects logical '0' before fulfilling the number of logical '1' required. The intention of this bit is to provide capability for SW to direct HW to check bus idle-ness before transmitting. Without setting this bit before directing HW to send header, HW will not check bus idle before transmitting. Besides that, this bit will also provide SW an option to configure HW to wait for IFS before sending again PTYPE or PID to fulfill IFS if there is no response from other nodes. Note: SW needs to configure valid IFS values before setting IFS_WAIT=1. [5:5] read-write RX_HEADER SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences. (Not set to '0' when an error is detected). -RX_HEADER -RX_HEADER, TX_RESPONSE -RX_HEADER, RX_RESPONSE The above applies for cases of receiving PID without prior receiving PTYPE. The header is received when the PID field STOP bits are received (INTR.RX_HEADER_PID_DONE and INTR.RX_HEADER_DONE). Typically, a slave node SW sets both RX_HEADER and RX_RESPONSE to '1', anticipating a transfer of a response from the master node to this slave node. After receipt of the header PID/PTYPE field (INTR.RX_HEADER_PID_DONE is activated), the slave node may decide to set TX_RESPONSE to '1' (which has lower priority than RX_RESPONSE hence RX_RESPONSE need to be clear to '0' by SW) to transmit a response. Note that, for cases with RXPIDZERO_CHECK_EN=1 for slave in polling mode, RX_HEADER is cleared upon receiving PTYPE if the next course of action is to transmit PID. If the next course of action is to receive PID, then the RX_HEADER is cleared upon completion of response. [8:8] read-write RX_RESPONSE SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected). -TX_HEADER, RX_RESPONSE -RX_HEADER, RX_RESPONSE SW can set this field to '1' to be conservative on receiving response i.e. IBS=0 whenever it is receiving PID. If the PID corresponds to transmit response, the SW can then clear this field to '0' and set TX_RESPONSE=1 to direct HW to send response. The response is received after CRC are received (INTR.RX_RESPONSE_DONE). [9:9] read-write TX_RX_STATUS TX/RX status 0x40 32 read-write 0x5000000 0x5000000 TX_IN CXPI transmitter input ('tx_in', 'cxpi_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality. [16:16] read-only RX_IN CXPI receiver input ('rx_in', 'cxpi_rx_in' in functional mode). [17:17] read-only TX_OUT CXPI transmitter output ('tx_out', 'cxpi_tx_out'). [24:24] read-only EN_OUT CXPI transceiver enable ('en_out', 'cxpi_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: '0': Disabled. '1': Enabled. If CTL0.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL0.AUTO_EN is '1', HW controls this field to enable the external transceiver: - HW sets this field to '1' when it is out of Sleep state. If it moves to Sleep state, HW will clear this field to '0'. [26:26] read-write TXPID_FI TXPID and Frame Information 0x50 32 read-write 0x0 0x0 PID Header protected identifier (PID). - Bits 6 downto 0: frame identifier ID[6:0]. - Bits 7: is odd parity bit. - PID[7] = ! (ID[6] ^ ID[5] ^ ID[4] ^ ID[3] ^ ID[2] ^ ID[1] ^ ID[0]) Software does not need to program the parity bit i.e. bit[7]. HW will calculate the odd parity bit and ignore the bit[7] if SW occupies this bit. Transmission: To be transmitted PID field. HW will ignore bit[7] and compute the parity bit based on bits[6:0] Note that, this field can be use by SW to send PType byte as the HW handles both PID and PType the same way. The frame type would occupy bit[6:0] and the odd parity will be calculated by the HW. [7:0] read-write FI Frame Information. This is the byte that will be transmitted as Frame Information. Per CXPI spec, FI[7:4] denotes the data length count (DLC). FI[3:2] denotes Network Management. Bit[3] - wakeup.ind Bit[2] - sleep.ind FI[1:0] denotes CT. Please program to 2'b11 if no support of counter. [15:8] read-write DLCEXT Data Length Count Extension. This field is intended for payload of more than 12B. This field is only valid if DLC=4'b1111 (FI[7:4]). The value specified in this field will be the new payload size. Valid values are 0-255. [23:16] read-write RXPID_FI RXPID and Frame Information 0x54 32 read-only 0x0 0x0 PID Header protected identifier (PID). - Bits 6 downto 0: frame identifier ID[6:0]. - Bits 7: is odd parity bit. - PID[7] = ! (ID[6] ^ ID[5] ^ ID[4] ^ ID[3] ^ ID[2] ^ ID[1] ^ ID[0]) Reception: Received PID field. SW uses the PID field to determine how to handle the response for a received frame header: TX_RESPONSE or RX_RESPONSE. Note that, this field can be use by SW to check PType byte as the HW handles both PID and PType the same way. The frame type would occupy bit[6:0] and bit[7] is the parity bit of the frame type. This parity bit is send by the transmitting node. [7:0] read-only FI Frame Information. This is the byte that is received as Frame Information. Per CXPI spec, FI[7:4] denotes the data length count (DLC). FI[3:2] denotes Network Management. Bit[3] - wakeup.ind Bit[2] - sleep.ind FI[1:0] denotes CT. [15:8] read-only DLCEXT Data Length Count Extension. This field is intended for payload of more than 12B. This field is only valid if DLC=4'b1111 (FI[15:12]). The value specified in this field will be the new payload size. Valid values are 0-255. [23:16] read-only CRC CRC 0x58 32 read-only 0x0 0x0 RXCRC1 CRC first byte for both CRC8 and CRC16. This is valid for both Normal frame and Long frame. HW will load this field with first byte of CRC upon receiving it. [7:0] read-only RXCRC2 CRC second byte of CRC16. This is valid only for Long frames. HW will load this field with second byte of CRC upon receiving it. [15:8] read-only TXCRC1 CRC first byte for both CRC8 and CRC16. This is valid for both Normal frame and Long frame. HW will load this field with first byte of CRC for transmit. [23:16] read-only TXCRC2 CRC second byte of CRC16. This is valid only for Long frames. HW will load this field with second byte of CRC for transmit. [31:24] read-only TX_FIFO_CTL TX FIFO control 0x80 32 read-write 0x0 0x3001F TRIGGER_LEVEL Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated: -INTR.TX_FIFO_TRIGGER = (#FIFO entries < TRIGGER_LEVEL) [4:0] read-write CLEAR This is a synchronous clear signal to the TX FIFO. When '1', the TX FIFO content are cleared. If a quick clear is required, the field should be set to '1' and followed by '0'. If a clear is required for an extended time, the field should be set to 1 during the complete time. [16:16] read-write FREEZE Freeze functionality: '0': HW uses TX FIFO data and pops the data from the TX FIFO for every HW read. '1': HW read from TX FIFO does not pop the data from the TX FIFO. Note: Freeze functionality is for debug purpose only. [17:17] read-write TX_FIFO_STATUS TX FIFO status 0x84 32 read-only 0x0 0x1F USED Number of used/occupied entries in the TX FIFO. The field value is in the range [0, 16]. When '0', the TX FIFO is empty. When '16', the TX FIFO is full. [4:0] read-only AVAIL TX FIFO Avail 0-No available slot in TX FIFO 1-1 available slot in TX FIFO. 2-2 available slot in TX FIFO. .. 16-16 available slot in TX FIFO. Note that the Fifo Width is 1Byte and each slot in this context is 1 depth of the Fifo. The number of bytes are determine through the number of data bytes in a message frame. (TXPID_FI.FI/TXPID_FI.DLCEXT) [20:16] read-only TX_FIFO_WR TX FIFO write 0x88 32 write-only 0x0 0xFF DATA Transmit Data field. Transmission: To be transmitted data field. SW provides data field. HW shadows over the write data to TX FIFO after SW performs a write to this field. HW shadows the whole 8 bits to the TX FIFO and relies on the TXPID_FI.FI/TXPID_FI.DCLEXT to determine the number of bytes. SW needs to ensure that TX FIFO is not overwritten before the content is consumed by HW by checking TX_FIFO_STATUS.AVAIL. Otherwise, the previous content would be overwritten and resulting in TX FIFO's overflow error (INTR.TX_OVERFLOW_ERROR). [7:0] write-only RX_FIFO_CTL RX FIFO control 0xA0 32 read-write 0x0 0x3001F TRIGGER_LEVEL Trigger level. When RX FIFO has more entries than the number of this field, a receiver trigger event is generated. - INTR_RX.FIFO_TRIGGER = (#FIFO entries > TRIGGER_LEVEL) [4:0] read-write CLEAR When '1', the RX FIFO content are popped. If a quick clear is required, the field should be set to '1' and followed by '0'. If a clear is required for an extended time, the field should be set to 1 during the complete time. [16:16] read-write FREEZE Freeze functionality: '0': HW writes to RX FIFO and push the data to RX FIFO. '1': HW write to RX FIFO does not push the data to the RX FIFO. Note: Freeze functionality is for debug purpose only. [17:17] read-write RX_FIFO_STATUS RX FIFO status 0xA4 32 read-only 0x0 0x1F USED Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 16]. When '0', the RX FIFO is empty. When '16', the RX FIFO is full. [4:0] read-only AVAIL RX FIFO avail 0-No content in RX FIFO 1-1 available content in RX FIFO. 2-2 available content in RX FIFO. .. 16-16 available content in RX FIFO. Note that the Fifo Width is 1Byte and each content in this context means 1 fifo slot. The number of bytes in each slot are determine through the number of data bytes in a message frame. (RXPID_FI.FI/RXPID_FI.DLCEXT) [20:16] read-only RX_FIFO_RD RX FIFO read 0xA8 32 read-only 0x0 0x0 DATA Received Data field. Software uses this data field. HW shadows the first content of the RX FIFO to this field. Software reading this field will remove the content from the RX FIFO and the next content of the RX FIFO will be shadowed over to this field. This field is 8bits and reflects the width of the RX FIFO. Software needs to rely on the RXPID_FI.FI/RXPID_FI.DLCEXT fields to determine number of bytes. Note that, during debug, a read from test controller would not remove/destory the content. Software needs to ensure it does not read from this field if there is no available content (from RX_FIFO_STATUS.USED). Otherwise, the content is undefined and it would result in RX FIFO underflow error. (INTR.RX_UNDERFLOW_ERROR). [7:0] read-only RX_FIFO_RD_SILENT RX FIFO silent read 0xAC 32 read-only 0x0 0x0 DATA Data read from the RX FIFO. Reading data from this field would not pop the data from RX FIFO. This register is for debug purpose. [7:0] read-only INTR Interrupt 0xC0 32 read-write 0x0 0x7FFC3F1B TX_HEADER_DONE HW sets this field to '1', when a frame header (PID field or PType field) is transmitted (the CMD.TX_HEADER is completed). Specifically: - For PID transmission only and without prior transmission of PTYPE, when followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the message frame transfer. - For PID transmission only and without prior transmission of PTYPE, when not followed by a response command, this field is set to '1' after completion of the header transfer. -Note for the case of PTYPE is transmitted follow by CMD.RX_RESPONSE or no following response, HW sets this field to '1' after transmitting PTYPE. [0:0] read-write TX_RESPONSE_DONE HW sets this field to '1', when a frame response (frame information fields, data fields, and crc field) is transmitted (the CMD.TX_RESPONSE is completed). [1:1] read-write TX_WAKEUP_DONE HW sets this field to '1', when a wakeup signal is transmitted (per CTL2.T_WAKEUP_LENGTH). This interrupt cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal. [3:3] read-write TX_FIFO_TRIGGER HW sets this field to '1', when TX trigger is generated (#used TX FIFO < TRIGGER_LEVEL). [4:4] read-write RX_HEADER_DONE HW sets this field to '1', when a frame header (PID field or PType field) is received (the CMD.RX_HEADER is completed). Specifically: - When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the message frame transfer. - When not followed by a response command, this field is set to '1' after completion of the header transfer if RXPIDZERO_CHECK_EN=1 and header received is PID. If RXPIDZERO_CHECK_EN=0 and response commands are not set, HW will set this field to '1' after receiving PID or PTYPE. [8:8] read-write RX_RESPONSE_DONE HW sets this field to '1', when a frame response (frame information fields, data fields, and crc field) is received (the CMD.RX_RESPONSE is completed). [9:9] read-write RX_WAKEUP_DETECT HW sets this field to '1', when RX fall is detected in Sleep mode. [10:10] read-write RX_FIFO_TRIGGER HW sets this field to '1', when RX trigger is generated (#used RX FIFO > TRIGGER_LEVEL). [11:11] read-write RX_HEADER_PID_DONE HW sets this field to '1', when RX header (PID/PTYPE field) is received. [12:12] read-write TXRX_COMPLETE HW sets this field to '1', when message frame ends after EOF is completed and TX/RX_DATA_LENGTH_ERROR=0. [13:13] read-write TIMEOUT HW sets this field to '1', when the transmitted/received bytes space within a message frame is > TIMEOUT_LENGTH. SW needs to set TIMEOUT_SEL=0 before clearing TIMEOUT=0 to ensure HW does not immediately sets back the interrupt. [18:18] read-write TX_HEADER_ARB_LOST HW sets this field to '1', when it detects arbitration lost after the number of retries has exceed the maximum allowed retries. Note: The ongoing message transfer is aborted (INTR.TX_HEADER_DONE and INTR.TX_RESPONSE_DONE is NOT activated and the TX_HEADER and TX_RESPONSE command is cleared to 0). [19:19] read-write TX_BIT_ERROR HW sets this field to '1', when a transmitted 'cxpi_tx_out' value does NOT match a received 'cxpi_rx_in' value. The match is performed for the PID fields or PType (for the START bit and STOP bit only) and for the rest of the response i.e. frame information fields, data fields and the crc field (for the START bit, DATA bits, and STOP bits). Note: When CTL0.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE and INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER and TX_RESPONSE commands are set to '0'. When CTL0.BIT_ERROR_IGNORE is '1', the ongoing message transfer would be transferred. [20:20] read-write RX_CRC_ERROR HW sets this field to '1', when received CRC is not matching with the compute CRC from header and response. Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated). [21:21] read-write RX_HEADER_PARITY_ERROR HW sets this field to '1', when the received PID field or PType field has a parity error. Note: The ongoing message transfer is aborted (INTR.RX_HEADER_PID_DONE is NOT activated). [22:22] read-write RX_DATA_LENGTH_ERROR HW sets this field to '1, when the received message frame's data fields are more than the value specified in DLC (for normal frame) or DLCEXT (for long frame) i.e. after receiving CRC byte(s), HW is receiving logical '0' during EOF. For the case of receiving data length less than DLC/DLCEXT, HW will also set this field to '1'. This is the case where IBS>9 before the number of data reaches data length, then HW will report as data length error. HW starts checking after frame information byte. Note: SW needs to handle the message transfer i.e. discard or flush out. HW will still set the RX_RESPONSE_DONE. [23:23] read-write TX_DATA_LENGTH_ERROR HW sets this field to '1, when the transmit message frame's data fields are more than the value specified in DLC (for normal frame) or DLCEXT (for long frame) i.e. after transmitting CRC(s) byte, HW is receiving logical '0' during EOF. Note: HW will still set TX_RESPONSE_DONE and the TX_HEADER and TX_RESPONSE commands are set to '0'. [24:24] read-write RX_OVERFLOW_ERROR HW sets this field to '1', when the RX data is overwritten by HW before the SW reads from it. In CXPI spec, this error is denoted as overrun error. Note: Upon this error, SW should discard the RX data in RX FIFO. [25:25] read-write TX_OVERFLOW_ERROR HW sets this field to '1', when the TX data is overwritten by SW before the HW reads from it to transmit to CXPI bus. Note: The ongoing message transfer will continue when this error happens however, data transferred at CXPI bus will be bogus and HW will invert the CRC to invalidate the message at the receiving node. TX_HEADER and TX_RESPONSE commands are set to '0'. [26:26] read-write RX_UNDERFLOW_ERROR HW sets this field to '1', when RX FIFO is empty and SW reads from it. Note: Upon this error, SW should discard the RX data in RX FIFO. [27:27] read-write TX_UNDERFLOW_ERROR HW sets this field to '1', when TX FIFO is empty and HW reads from it. Note: The ongoing message transfer will continue when this error happens however, data transferred at CXPI will be bogus and HW will invert the CRC to invalidate the message at the receiving node. TX_HEADER and TX_RESPONSE commands are set to '0'. [28:28] read-write RX_FRAME_ERROR HW sets this field to '1', when the stop bit of a byte frame is incorrect. Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated and the INTR.RX_HEADER_DONE/TX_HEADER_DONE is NOT activated if the frame error occurs during header byte or if frame error occurs during response byte (if the HEADER and RESPONSE commands are set together)). [29:29] read-write TX_FRAME_ERROR HW sets this field to '1', when the stop bit of a byte frame is incorrect. This error would be a subset of TX_BIT_ERROR and also subjected to BIT_ERROR_IGNORE field. Note: The ongoing message transfer is aborted (INTR.TX_HEADER_DONE/RX_HEADER_DONE and INTR.TX_RESPONSE_DONE are NOT activated) and the TX_HEADER and TX_RESPONSE commands are set to '0'. Note: When CTL0.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE and INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER and TX_RESPONSE commands are set to '0'. When CTL0.BIT_ERROR_IGNORE is '1', the ongoing message transfer would be transferred. [30:30] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x7FFC3F1B TX_HEADER_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write TX_RESPONSE_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [1:1] read-write TX_WAKEUP_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [3:3] read-write TX_FIFO_TRIGGER Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [4:4] read-write RX_HEADER_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [8:8] read-write RX_RESPONSE_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [9:9] read-write RX_WAKEUP_DETECT Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [10:10] read-write RX_FIFO_TRIGGER Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [11:11] read-write RX_HEADER_PID_DONE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [12:12] read-write TXRX_COMPLETE Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [13:13] read-write TIMEOUT Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [18:18] read-write TX_HEADER_ARB_LOST Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [19:19] read-write TX_BIT_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [20:20] read-write RX_CRC_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [21:21] read-write RX_HEADER_PARITY_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [22:22] read-write RX_DATA_LENGTH_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [23:23] read-write TX_DATA_LENGTH_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [24:24] read-write RX_OVERFLOW_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [25:25] read-write TX_OVERFLOW_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [26:26] read-write RX_UNDERFLOW_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [27:27] read-write TX_UNDERFLOW_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [28:28] read-write RX_FRAME_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [29:29] read-write TX_FRAME_ERROR Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [30:30] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x7FFC3F1B TX_HEADER_DONE Mask for corresponding field in INTR register. [0:0] read-write TX_RESPONSE_DONE Mask for corresponding field in INTR register. [1:1] read-write TX_WAKEUP_DONE Mask for corresponding field in INTR register. [3:3] read-write TX_FIFO_TRIGGER Mask for corresponding field in INTR register. [4:4] read-write RX_HEADER_DONE Mask for corresponding field in INTR register. [8:8] read-write RX_RESPONSE_DONE Mask for corresponding field in INTR register. [9:9] read-write RX_WAKEUP_DETECT Mask for corresponding field in INTR register. [10:10] read-write RX_FIFO_TRIGGER Mask for corresponding field in INTR register. [11:11] read-write RX_HEADER_PID_DONE Mask for corresponding field in INTR register. [12:12] read-write TXRX_COMPLETE Mask for corresponding field in INTR register. [13:13] read-write TIMEOUT Mask for corresponding field in INTR register. [18:18] read-write TX_HEADER_ARB_LOST Mask for corresponding field in INTR register. [19:19] read-write TX_BIT_ERROR Mask for corresponding field in INTR register. [20:20] read-write RX_CRC_ERROR Mask for corresponding field in INTR register. [21:21] read-write RX_HEADER_PARITY_ERROR Mask for corresponding field in INTR register. [22:22] read-write RX_DATA_LENGTH_ERROR Mask for corresponding field in INTR register. [23:23] read-write TX_DATA_LENGTH_ERROR Mask for corresponding field in INTR register. [24:24] read-write RX_OVERFLOW_ERROR Mask for corresponding field in INTR register. [25:25] read-write TX_OVERFLOW_ERROR Mask for corresponding field in INTR register. [26:26] read-write RX_UNDERFLOW_ERROR Mask for corresponding field in INTR register. [27:27] read-write TX_UNDERFLOW_ERROR Mask for corresponding field in INTR register. [28:28] read-write RX_FRAME_ERROR Mask for corresponding field in INTR register. [29:29] read-write TX_FRAME_ERROR Mask for corresponding field in INTR register. [30:30] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x7FFC3F1B TX_HEADER_DONE Logical AND of corresponding INTR and INTR_MASK fields. [0:0] read-only TX_RESPONSE_DONE Logical AND of corresponding INTR and INTR_MASK fields. [1:1] read-only TX_WAKEUP_DONE Logical AND of corresponding INTR and INTR_MASK fields. [3:3] read-only TX_FIFO_TRIGGER Logical AND of corresponding INTR and INTR_MASK fields. [4:4] read-only RX_HEADER_DONE Logical AND of corresponding INTR and INTR_MASK fields. [8:8] read-only RX_RESPONSE_DONE Logical AND of corresponding INTR and INTR_MASK fields. [9:9] read-only RX_WAKEUP_DETECT Logical AND of corresponding INTR and INTR_MASK fields. [10:10] read-only RX_FIFO_TRIGGER Logical AND of corresponding INTR and INTR_MASK fields. [11:11] read-only RX_HEADER_PID_DONE Logical AND of corresponding INTR and INTR_MASK fields. [12:12] read-only TXRX_COMPLETE Logical AND of corresponding INTR and INTR_MASK fields. [13:13] read-only TIMEOUT Logical AND of corresponding INTR and INTR_MASK fields. [18:18] read-only TX_HEADER_ARB_LOST Logical AND of corresponding INTR and INTR_MASK fields. [19:19] read-only TX_BIT_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [20:20] read-only RX_CRC_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [21:21] read-only RX_HEADER_PARITY_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [22:22] read-only RX_DATA_LENGTH_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [23:23] read-only TX_DATA_LENGTH_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [24:24] read-only RX_OVERFLOW_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [25:25] read-only TX_OVERFLOW_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [26:26] read-only RX_UNDERFLOW_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [27:27] read-only TX_UNDERFLOW_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [28:28] read-only RX_FRAME_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [29:29] read-only TX_FRAME_ERROR Logical AND of corresponding INTR and INTR_MASK fields. [30:30] read-only CANFD0 CAN Controller CANFD 0x40520000 0 131072 registers 4 512 CH[%s] FIFO wrapper around M_TTCAN 3PIP, to enable DMA 0x00000000 M_TTCAN TTCAN 3PIP, includes FD 0x00000000 CREL Core Release Register 0x0 32 read-only 0x32380609 0xFFFFFFFF DAY Time Stamp Day Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [7:0] read-only MON Time Stamp Month Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [15:8] read-only YEAR Time Stamp Year One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [19:16] read-only SUBSTEP Sub-step of Core Release One digit, BCD-coded. [23:20] read-only STEP Step of Core Release One digit, BCD-coded. [27:24] read-only REL Core Release One digit, BCD-coded. [31:28] read-only ENDN Endian Register 0x4 32 read-only 0x87654321 0xFFFFFFFF ETV Endianness Test Value The endianness test value is 0x87654321. [31:0] read-only DBTP Data Bit Timing & Prescaler Register 0xC 32 read-write 0xA33 0x9F1FFF DSJW Data (Re)Synchronization Jump Width 0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [3:0] read-write DTSEG2 Data time segment after sample point 0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [7:4] read-write DTSEG1 Data time segment before sample point 0x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [12:8] read-write DBRP Data Bit Rate Prescaler 0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [20:16] read-write TDC Transmitter Delay Compensation 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled [23:23] read-write TEST Test Register 0x10 32 read-write 0x0 0x7F TAM ASC is not supported by M_TTCAN Test ASC Multiplexer Control Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE 0= Level at pin m_ttcan_ascm controlled by FSE 1= Level at pin m_ttcan_ascm = '1' [0:0] read-write TAT ASC is not supported by M_TTCAN Test ASC Transmit Control Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE 0= Level at pin m_ttcan_asct controlled by FSE 1= Level at pin m_ttcan_asct = '1' [1:1] read-write CAM ASC is not supported by M_TTCAN Check ASC Multiplexer Control Monitors level at output pin m_ttcan_ascm. 0= Output pin m_ttcan_ascm = '0' 1= Output pin m_ttcan_ascm = '1' [2:2] read-write CAT ASC is not supported by M_TTCAN Check ASC Transmit Control Monitors level at output pin m_ttcan_asct. 0= Output pin m_ttcan_asct = '0' [3:3] read-write LBCK Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled (see Section 3.1.9, Test Modes) [4:4] read-write TX Control of Transmit Pin 00 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_ttcan_tx 10 Dominant ('0') level at pin m_ttcan_tx 11 Recessive ('1') at pin m_ttcan_tx [6:5] read-write RX Receive Pin Monitors the actual value of pin m_ttcan_rx 0= The CAN bus is dominant (m_ttcan_rx = '0') 1= The CAN bus is recessive (m_ttcan_rx = '1') [7:7] read-only RWD RAM Watchdog 0x14 32 read-write 0x0 0xFFFF WDC Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled. [7:0] read-write WDV Watchdog Value Actual Message RAM Watchdog Counter Value. [15:8] read-only CCCR CC Control Register 0x18 32 read-write 0x1 0xF3FF INIT Initialization 0= Normal Operation 1= Initialization is started [0:0] read-write CCE Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') [1:1] read-write ASM Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active [2:2] read-write CSA Clock Stop Acknowledge 0= No clock stop acknowledged 1= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk [3:3] read-write CSR Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead. 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. [4:4] read-write MON_ Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled [5:5] read-write DAR Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled [6:6] read-write TEST Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled [7:7] read-write FDOE FD Operation Enable 0= FD operation disabled 1= FD operation enabled [8:8] read-write BRSE Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled [9:9] read-write PXHD Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled [12:12] read-write EFBI Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization [13:13] read-write TXP Transmit Pause If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled [14:14] read-write NISO Non ISO Operation If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD [15:15] read-write NBTP Nominal Bit Timing & Prescaler Register 0x1C 32 read-write 0x6000A03 0xFFFFFF7F NTSEG2 Nominal Time segment after sample point 0x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [6:0] read-write NTSEG1 Nominal Time segment before sample point 0x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [15:8] read-write NBRP Nominal Bit Rate Prescaler 0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [24:16] read-write NSJW Nominal (Re)Synchronization Jump Width 0x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [31:25] read-write TSCC Timestamp Counter Configuration 0x20 32 read-write 0x0 0xF0003 TSS Timestamp Select, should always be set to external timestamp counter 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as '00' [1:0] read-write TCP Timestamp Counter Prescaler (still used for TOCC) 0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1...16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [19:16] read-write TSCV Timestamp Counter Value 0x24 32 read-write 0x0 0xFFFF TSC Timestamp Counter, not used for M_TTCAN The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external Timestamp Counter value. A write access has no impact. [15:0] read-write TOCC Timeout Counter Configuration 0x28 32 read-write 0xFFFF0000 0xFFFF0007 ETOC Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled [0:0] read-write TOS Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1 [2:1] read-write TOP Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period. [31:16] read-write TOCV Timeout Counter Value 0x2C 32 read-write 0xFFFF 0xFFFF TOC Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. [15:0] read-write ECR Error Counter Register 0x40 32 read-only 0x0 0xFFFFFF TEC Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255 [7:0] read-only REC Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127 [14:8] read-only RP Receive Error Passive 0= The Receive Error Counter is below the error passive level of 128 1= The Receive Error Counter has reached the error passive level of 128 [15:15] read-only CEL CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. [23:16] read-only PSR Protocol Status Register 0x44 32 read-only 0x707 0x7F7FFF LEC Last Error Code, Set on Read0 The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2= Form Error: A fixed format part of a received frame has the wrong format. 3= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node. 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. [2:0] read-only ACT Activity Monitors the module's CAN communication state. 00= Synchronizing - node is synchronizing on CAN communication 01= Idle - node is neither receiver nor transmitter 10= Receiver - node is operating as receiver 11= Transmitter - node is operating as transmitter [4:3] read-only EP Error Passive 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1= The M_CAN is in the Error_Passive state [5:5] read-only EW Warning Status 0= Both error counters are below the Error_Warning limit of 96 1= At least one of error counter has reached the Error_Warning limit of 96 [6:6] read-only BO Bus_Off Status 0= The M_CAN is not Bus_Off 1= The M_CAN is in Bus_Off state [7:7] read-only DLEC Data Phase Last Error Code , Set on Read Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. [10:8] read-only RESI ESI flag of last received CAN FD Message , Reset on Read This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its ESI flag set 1= Last received CAN FD message had its ESI flag set [11:11] read-only RBRS BRS flag of last received CAN FD Message , Reset on Read This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its BRS flag set 1= Last received CAN FD message had its BRS flag set [12:12] read-only RFDF Received a CAN FD Message , Reset on Read This bit is set independent of acceptance filtering. 0= Since this bit was reset by the CPU, no CAN FD message has been received 1= Message in CAN FD format with FDF flag set has been received [13:13] read-only PXE Protocol Exception Event , Reset on Read 0= No protocol exception event occurred since last read access 1= Protocol exception event occurred [14:14] read-only TDCV Transmitter Delay Compensation Value 0x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. [22:16] read-only TDCR Transmitter Delay Compensation Register 0x48 32 read-write 0x0 0x7F7F TDCF Transmitter Delay Compensation Filter Window Length 0x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq [6:0] read-write TDCO Transmitter Delay Compensation Offset 0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq. [14:8] read-write IR Interrupt Register 0x50 32 read-write 0x0 0x3FFFFFFF RF0N Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0 [0:0] read-write RF0W Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark [1:1] read-write RF0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full [2:2] read-write RF0L_ Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero [3:3] read-write RF1N Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1 [4:4] read-write RF1W Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark [5:5] read-write RF1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full [6:6] read-write RF1L_ Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero [7:7] read-write HPM High Priority Message 0= No high priority message received 1= High priority message received [8:8] read-write TC Transmission Completed 0= No transmission completed 1= Transmission completed [9:9] read-write TCF Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished [10:10] read-write TFE Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty [11:11] read-write TEFN Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element [12:12] read-write TEFW Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark [13:13] read-write TEFF Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full [14:14] read-write TEFL_ Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero [15:15] read-write TSW Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around [16:16] read-write MRAF Message RAM Access Failure The flag is set, when the Rx Handler - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. - was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred [17:17] read-write TOO Timeout Occurred 0= No timeout 1= Timeout reached [18:18] read-write DRX Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into a Rx Buffer [19:19] read-write BEC M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0. Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC) [20:20] read-write BEU Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic) [21:21] read-write ELO Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred [22:22] read-write EP_ Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed [23:23] read-write EW_ Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed [24:24] read-write BO_ Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed [25:25] read-write WDI Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY [26:26] read-write PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC != 0,7) [27:27] read-write PED Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC != 0,7) [28:28] read-write ARA N/A [29:29] read-write IE Interrupt Enable 0x54 32 read-write 0x0 0x3FFFFFFF RF0NE Rx FIFO 0 New Message Interrupt Enable [0:0] read-write RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable [1:1] read-write RF0FE Rx FIFO 0 Full Interrupt Enable [2:2] read-write RF0LE Rx FIFO 0 Message Lost Interrupt Enable [3:3] read-write RF1NE Rx FIFO 1 New Message Interrupt Enable [4:4] read-write RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable [5:5] read-write RF1FE Rx FIFO 1 Full Interrupt Enable [6:6] read-write RF1LE Rx FIFO 1 Message Lost Interrupt Enable [7:7] read-write HPME High Priority Message Interrupt Enable [8:8] read-write TCE Transmission Completed Interrupt Enable [9:9] read-write TCFE Transmission Cancellation Finished Interrupt Enable [10:10] read-write TFEE Tx FIFO Empty Interrupt Enable [11:11] read-write TEFNE Tx Event FIDO New Entry Interrupt Enable [12:12] read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable [13:13] read-write TEFFE Tx Event FIFO Full Interrupt Enable [14:14] read-write TEFLE Tx Event FIFO Event Lost Interrupt Enable [15:15] read-write TSWE Timestamp Wraparound Interrupt Enable [16:16] read-write MRAFE Message RAM Access Failure Interrupt Enable [17:17] read-write TOOE Timeout Occurred Interrupt Enable [18:18] read-write DRXE Message stored to Dedicated Rx Buffer Interrupt Enable [19:19] read-write BECE Bit Error Corrected Interrupt Enable (not used in M_TTCAN) [20:20] read-write BEUE Bit Error Uncorrected Interrupt Enable [21:21] read-write ELOE Error Logging Overflow Interrupt Enable [22:22] read-write EPE Error Passive Interrupt Enable [23:23] read-write EWE Warning Status Interrupt Enable [24:24] read-write BOE Bus_Off Status Interrupt Enable [25:25] read-write WDIE Watchdog Interrupt Enable [26:26] read-write PEAE Protocol Error in Arbitration Phase Enable [27:27] read-write PEDE Protocol Error in Data Phase Enable [28:28] read-write ARAE N/A [29:29] read-write ILS Interrupt Line Select 0x58 32 read-write 0x0 0x3FFFFFFF RF0NL Rx FIFO 0 New Message Interrupt Line [0:0] read-write RF0WL Rx FIFO 0 Watermark Reached Interrupt Line [1:1] read-write RF0FL Rx FIFO 0 Full Interrupt Line [2:2] read-write RF0LL Rx FIFO 0 Message Lost Interrupt Line [3:3] read-write RF1NL Rx FIFO 1 New Message Interrupt Line [4:4] read-write RF1WL Rx FIFO 1 Watermark Reached Interrupt Line [5:5] read-write RF1FL Rx FIFO 1 Full Interrupt Line [6:6] read-write RF1LL Rx FIFO 1 Message Lost Interrupt Line [7:7] read-write HPML High Priority Message Interrupt Line [8:8] read-write TCL Transmission Completed Interrupt Line [9:9] read-write TCFL Transmission Cancellation Finished Interrupt Line [10:10] read-write TFEL Tx FIFO Empty Interrupt Line [11:11] read-write TEFNL Tx Event FIFO New Entry Interrupt Line [12:12] read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line [13:13] read-write TEFFL Tx Event FIFO Full Interrupt Line [14:14] read-write TEFLL Tx Event FIFO Event Lost Interrupt Line [15:15] read-write TSWL Timestamp Wraparound Interrupt Line [16:16] read-write MRAFL Message RAM Access Failure Interrupt Line [17:17] read-write TOOL Timeout Occurred Interrupt Line [18:18] read-write DRXL Message stored to Dedicated Rx Buffer Interrupt Line [19:19] read-write BECL Bit Error Corrected Interrupt Line (not used in M_TTCAN) [20:20] read-write BEUL Bit Error Uncorrected Interrupt Line [21:21] read-write ELOL Error Logging Overflow Interrupt Line [22:22] read-write EPL Error Passive Interrupt Line [23:23] read-write EWL Warning Status Interrupt Line [24:24] read-write BOL Bus_Off Status Interrupt Line [25:25] read-write WDIL Watchdog Interrupt Line [26:26] read-write PEAL Protocol Error in Arbitration Phase Line [27:27] read-write PEDL Protocol Error in Data Phase Line [28:28] read-write ARAL N/A [29:29] read-write ILE Interrupt Line Enable 0x5C 32 read-write 0x0 0x3 EINT0 Enable Interrupt Line 0 0= Interrupt line m_ttcan_int0 disabled 1= Interrupt line m_ttcan_int0 enabled [0:0] read-write EINT1 Enable Interrupt Line 1 0= Interrupt line m_ttcan_int1 disabled 1= Interrupt line m_ttcan_int1 enabled [1:1] read-write GFC Global Filter Configuration 0x80 32 read-write 0x0 0x3F RRFE Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs [0:0] read-write RRFS Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs [1:1] read-write ANFE Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject [3:2] read-write ANFS Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject [5:4] read-write SIDFC Standard ID Filter Configuration 0x84 32 read-write 0x0 0xFFFFFC FLSSA Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see Figure 2). [15:2] read-write LSS List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements 128= Values greater than 128 are interpreted as 128 [23:16] read-write XIDFC Extended ID Filter Configuration 0x88 32 read-write 0x0 0x7FFFFC FLESA Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address, see Figure 2). [15:2] read-write LSE List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements 64= Values greater than 64 are interpreted as 64 [22:16] read-write XIDAM Extended ID AND Mask 0x90 32 read-write 0x1FFFFFFF 0x1FFFFFFF EIDM Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. [28:0] read-write HPMS High Priority Message Status 0x94 32 read-only 0x0 0xFFFF BIDX Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'. [5:0] read-only MSI Message Storage Indicator 00= No FIFO selected 01= FIFO message lost 10= Message stored in FIFO 0 11= Message stored in FIFO 1 [7:6] read-only FIDX Filter Index Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. [14:8] read-only FLST Filter List Indicates the filter list of the matching filter element. 0= Standard Filter List 1= Extended Filter List [15:15] read-only NDAT1 New Data 1 0x98 32 read-write 0x0 0xFFFFFFFF ND New Data The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message [31:0] read-write NDAT2 New Data 2 0x9C 32 read-write 0x0 0xFFFFFFFF ND New Data The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message [31:0] read-write RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write 0x0 0xFF7FFFFC F0SA Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2). [15:2] read-write F0S Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements 64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1 [22:16] read-write F0WM Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) 64= Watermark interrupt disabled [30:24] read-write F0OM FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode [31:31] read-write RXF0S Rx FIFO 0 Status 0xA4 32 read-only 0x0 0x33F3F7F F0FL Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64. When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected. [6:0] read-only F0GI Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63. This field is updated by the software writing to RXF0A.F0AI. When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected. [13:8] read-only F0PI Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63. [21:16] read-only F0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full [24:24] read-only RF0L Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero [25:25] read-only RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write 0x0 0x3F F0AI Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. [5:0] read-write RXBC Rx Buffer Configuration 0xAC 32 read-write 0x0 0xFFFC RBSA Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). Also used to reference debug messages A,B,C. [15:2] read-write RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write 0x0 0xFF7FFFFC F1SA Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2). [15:2] read-write F1S Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements 64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1 [22:16] read-write F1WM Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) 64= Watermark interrupt disabled [30:24] read-write F1OM FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode [31:31] read-write RXF1S Rx FIFO 1 Status 0xB4 32 read-only 0x0 0xC33F3F7F F1FL Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64. When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected. [6:0] read-only F1GI Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63. This field is updated by the software writing to RXF1A.F1AI. When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected. [13:8] read-only F1PI Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63. [21:16] read-only F1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full [24:24] read-only RF1L Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero [25:25] read-only DMS Debug Message Status 00= Idle state, wait for reception of debug messages, DMA request is cleared 01= Debug message A received 10= Debug messages A, B received 11= Debug messages A, B, C received, DMA request is set [31:30] read-only RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write 0x0 0x3F F1AI Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. [5:0] read-write RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write 0x0 0x777 F0DS Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [2:0] read-write F1DS Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [6:4] read-write RBDS Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [10:8] read-write TXBC Tx Buffer Configuration 0xC0 32 read-write 0x0 0x7F3FFFFC TBSA Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). [15:2] read-write NDTB Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers 32= Values greater than 32 are interpreted as 32 [21:16] read-write TFQS Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue 32= Values greater than 32 are interpreted as 32 [29:24] read-write TFQM Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation [30:30] read-write TXFQS Tx FIFO/Queue Status 0xC4 32 read-only 0x0 0x3F1F3F TFFL Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1') [5:0] read-only TFGI Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured TXBC.TFQM = '1'). [12:8] read-only TFQPI Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31. [20:16] read-only TFQF Tx FIFO/Queue Full 0= Tx FIFO/Queue not full 1= Tx FIFO/Queue full [21:21] read-only TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write 0x0 0x7 TBDS Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [2:0] read-write TXBRP Tx Buffer Request Pending 0xCC 32 read-only 0x0 0xFFFFFFFF TRP Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0= No transmission request pending 1= Transmission request pending [31:0] read-only TXBAR Tx Buffer Add Request 0xD0 32 read-write 0x0 0xFFFFFFFF AR Add Request Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added [31:0] read-write TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write 0x0 0xFFFFFFFF CR Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending [31:0] read-write TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only 0x0 0xFFFFFFFF TO Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0= No transmission occurred 1= Transmission occurred [31:0] read-only TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only 0x0 0xFFFFFFFF CF Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0= No transmit buffer cancellation 1= Transmit buffer cancellation finished [31:0] read-only TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write 0x0 0xFFFFFFFF TIE Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable [31:0] read-write TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write 0x0 0xFFFFFFFF CFIE Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled [31:0] read-write TXEFC Tx Event FIFO Configuration 0xF0 32 read-write 0x0 0x3F3FFFFC EFSA Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2). [15:2] read-write EFS Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements 32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1 [21:16] read-write EFWM Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) 32= Watermark interrupt disabled [29:24] read-write TXEFS Tx Event FIFO Status 0xF4 32 read-only 0x0 0x31F1F3F EFFL Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32. When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected. [5:0] read-only EFGI Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31. This field is updated by the software writing to TXEFA.EFAI. When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected. [12:8] read-only EFPI Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31. [20:16] read-only EFF Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full [24:24] read-only TEFL Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. [25:25] read-only TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write 0x0 0x1F EFAI Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. [4:0] read-write TTTMC TT Trigger Memory Configuration 0x100 32 read-write 0x0 0x7FFFFC TMSA Trigger Memory Start Address Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2). [15:2] read-write TME Trigger Memory Elements 0= No Trigger Memory 1-64= Number of Trigger Memory elements 64= Values greater than 64 are interpreted as 64 [22:16] read-write TTRMC TT Reference Message Configuration 0x104 32 read-write 0x0 0xDFFFFFFF RID Reference Identifier Identifier transmitted with reference message and used for reference message filtering. Standard or extended reference identifier depending on bit XTD. A standard identifier has to be written to ID[28:18]. [28:0] read-write XTD Extended Identifier 0= 11-bit standard identifier 1= 29-bit extended identifier [30:30] read-write RMPS Reference Message Payload Select Ignored in case of time slaves. 0= Reference message has no additional payload 1= The following elements are taken from Tx Buffer 0: Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB Level 1: bytes 2-8, Level 0,2: bytes 5-8) [31:31] read-write TTOCF TT Operation Configuration 0x108 32 read-write 0x10000 0x7FFFFFB OM Operation Mode 00= Event-driven CAN communication, default 01= TTCAN level 1 10= TTCAN level 2 11= TTCAN level 0 [1:0] read-write GEN Gap Enable 0= Strictly time-triggered operation 1= External event-synchronized time-triggered operation [3:3] read-write TM Time Master 0= Time Master function disabled 1= Potential Time Master [4:4] read-write LDSDL LD of Synchronization Deviation Limit The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = 2(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration. 0x0-7 LD of Synchronization Deviation Limit (SDL <= 32...4096) [7:5] read-write IRTO Initial Reference Trigger Offset 0x00-7F Positive offset, range from 0 to 127 [14:8] read-write EECS Enable External Clock Synchronization If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation. 0= External clock synchronization in TTCAN Level 0,2 disabled 1= External clock synchronization in TTCAN Level 0,2 enabled [15:15] read-write AWL Application Watchdog Limit The application watchdog can be disabled by programming AWL to 0x00. 0x00-FF Maximum time after which the application has to serve the application watchdog. The application watchdog is incremented once each 256 NTUs. [23:16] read-write EGTF Enable Global Time Filtering 0= Global time filtering in TTCAN Level 0,2 is disabled 1= Global time filtering in TTCAN Level 0,2 is enabled [24:24] read-write ECC Enable Clock Calibration 0= Automatic clock calibration in TTCAN Level 0,2 is disabled 1= Automatic clock calibration in TTCAN Level 0,2 is enabled [25:25] read-write EVTP Event Trigger Polarity 0= Rising edge trigger 1= Falling edge trigger [26:26] read-write TTMLM TT Matrix Limits 0x10C 32 read-write 0x0 0xFFF0FFF CCM N/A [5:0] read-write CSS N/A [7:6] read-write TXEW Tx Enable Window 0x0-F Length of Tx enable window, 1-16 NTU cycles [11:8] read-write ENTT Expected Number of Tx Triggers 0x000-FFF Expected number of Tx Triggers in one Matrix Cycle [27:16] read-write TURCF TUR Configuration 0x110 32 read-write 0x10000000 0xBFFFFFFF NCL Numerator Configuration Low Write access to the TUR Numerator Configuration Low is only possible during configuration with TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new value for NCL is written outside TT Configuration Mode, the new value takes effect when TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'. 0x0000-FFFF Numerator Configuration Low [15:0] read-write DC Denominator Configuration 0x0000 Illegal value 0x0001-3FFF Denominator Configuration [29:16] read-write ELT Enable Local Time 0= Local time is stopped, default 1= Local time is enabled [31:31] read-write TTOCN TT Operation Control 0x114 32 read-write 0x0 0xBFFF SGT Set Global time Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one Host clock period. The global time preset takes effect when the node transmits the next reference message with the Master_Ref_Mark modified by the preset value written to TTGTP. [0:0] read-write ECS External Clock Synchronization Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one Host clock period. The external clock synchronization takes effect at the start of the next basic cycle. [1:1] read-write SWP Stop Watch Polarity 0= Rising edge trigger 1= Falling edge trigger [2:2] read-write SWS Stop Watch Source 00= Stop Watch disabled 01= Actual value of cycle time is copied to TTCPT.SWV 10= Actual value of local time is copied to TTCPT.SWV 11= Actual value of global time is copied to TTCPT.SWV [4:3] read-write RTIE Register Time Mark Interrupt Pulse Enable Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent of the synchronization state. 0= Register Time Mark Interrupt output m_ttcan_rtp disabled 1= Register Time Mark Interrupt output m_ttcan_rtp enabled [5:5] read-write TMC Register Time Mark Compare 00= No Register Time Mark Interrupt generated 01= Register Time Mark Interrupt if Time Mark = cycle time 10= Register Time Mark Interrupt if Time Mark = local time 11= Register Time Mark Interrupt if Time Mark = global time [7:6] read-write TTIE Trigger Time Mark Interrupt Pulse Enable External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A trigger time mark interrupt pulse is generated when the trigger memory element becomes active, and the M_TTCAN is in synchronization state In_Schedule or In_Gap. 0= Trigger Time Mark Interrupt output m_ttcan_tmp disabled 1= Trigger Time Mark Interrupt output m_ttcan_tmp enabled [8:8] read-write GCS Gap Control Select 0= Gap control independent from m_ttcan_evt 1= Gap control by input pin m_ttcan_evt [9:9] read-write FGP Finish Gap Set by the CPU, reset by each reference message 0= No reference message requested 1= Application requested start of reference message [10:10] read-write TMG Time Mark Gap 0= Reset by each reference message 1= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated [11:11] read-write NIG Next is Gap This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for external event-synchronized time-triggered operation (TTOCF.GEN = '1') 0= No action, reset by reception of any reference message 1= Transmit next reference message with Next_is_Gap = '1' [12:12] read-write ESCN External Synchronization Control If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising edge at pin m_ttcan_evt (see Section 4.11). 0= External synchronization disabled 1= External synchronization enabled [13:13] read-write LCKC TT Operation Control Register Locked Set by a write access to register TTOCN. Reset when the updated configuration has been synchronized into the CAN clock domain. 0= Write access to TTOCN enabled 1= Write access to TTOCN locked [15:15] read-only TTGTP TT Global Time Preset 0x118 32 read-write 0x0 0xFFFFFFFF TP N/A [15:0] read-write CTP Cycle Time Target Phase CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11). 0x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected [31:16] read-write TTTMK TT Time Mark 0x11C 32 read-write 0x0 0x807FFFFF TM_ Time Mark 0x0000-FFFF Time Mark [15:0] read-write TICC Time Mark Cycle Code Cycle count for which the time mark is valid. 0b000000x valid for all cycles 0b000001c valid every second cycle at cycle count mod2 = c 0b00001cc valid every fourth cycle at cycle count mod4 = cc 0b0001ccc valid every eighth cycle at cycle count mod8 = ccc 0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc 0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc 0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc [22:16] read-write LCKM TT Time Mark Register Locked Always set by a write access to registers TTOCN. Set by write access to register TTTMK when TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain. 0= Write access to TTTMK enabled 1= Write access to TTTMK locked [31:31] read-only TTIR TT Interrupt Register 0x120 32 read-write 0x0 0x7FFFF SBC Start of Basic Cycle 0= No Basic Cycle started since bit has been reset 1= Basic Cycle started [0:0] read-write SMC Start of Matrix Cycle 0= No Matrix Cycle started since bit has been reset 1= Matrix Cycle started [1:1] read-write CSM_ Change of Synchronization Mode 0= No change in master to slave relation or schedule synchronization 1= Master to slave relation or schedule synchronization changed, also set when TTOST.SPL is reset [2:2] read-write SOG Start of Gap 0= No reference message seen with Next_is_Gap bit set 1= Reference message with Next_is_Gap bit set becomes valid [3:3] read-write RTMI Register Time Mark Interrupt Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent of the synchronization state. 0= Time mark not reached 1= Time mark reached [4:4] read-write TTMI Trigger Time Mark Event Internal Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set when the trigger memory element becomes active, and the M_TTCAN is in synchronization state In_Gap or In_Schedule. 0= Time mark not reached 1= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200) [5:5] read-write SWE Stop Watch Event 0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected 1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected [6:6] read-write GTW Global Time Wrap 0= No global time wrap occurred 1= Global time wrap from 0xFFFF to 0x0000 occurred [7:7] read-write GTD Global Time Discontinuity 0= No discontinuity of global time 1= Discontinuity of global time [8:8] read-write GTE Global Time Error Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only. 0= Synchronization deviation within limit 1= Synchronization deviation exceeded limit [9:9] read-write TXU Tx Count Underflow 0= Number of Tx Trigger as expected 1= Less Tx trigger than expected in one matrix cycle [10:10] read-write TXO Tx Count Overflow 0= Number of Tx Trigger as expected 1= More Tx trigger than expected in one matrix cycle [11:11] read-write SE1 Scheduling Error 1 0= No scheduling error 1 1= Scheduling error 1 occurred [12:12] read-write SE2 Scheduling Error 2 0= No scheduling error 2 1= Scheduling error 2 occurred [13:13] read-write ELC Error Level Changed Not set when error level changed during initialization. 0= No change in error level 1= Error level changed [14:14] read-write IWT Initialization Watch Trigger The initialization is restarted by resetting IWT. 0= No missing reference message during system startup 1= No system startup due to missing reference message [15:15] read-write WT Watch Trigger 0= No missing reference message 1= Missing reference message (Level 0: cycle time 0xFF00) [16:16] read-write AW Application Watchdog 0= Application watchdog served in time 1= Application watchdog not served in time [17:17] read-write CER Configuration Error Trigger out of order. 0= No error found in trigger list 1= Error found in trigger list [18:18] read-write TTIE TT Interrupt Enable 0x124 32 read-write 0x0 0x7FFFF SBCE Start of Basic Cycle Interrupt Enable [0:0] read-write SMCE Start of Matrix Cycle Interrupt Enable [1:1] read-write CSME Change of Synchronization Mode Interrupt Enable [2:2] read-write SOGE Start of Gap Interrupt Enable [3:3] read-write RTMIE Register Time Mark Interrupt Enable [4:4] read-write TTMIE Trigger Time Mark Event Internal Enable [5:5] read-write SWEE Stop Watch Event Interrupt Enable [6:6] read-write GTWE Global Time Wrap Interrupt Enable [7:7] read-write GTDE Global Time Discontinuity Interrupt Enable [8:8] read-write GTEE Global Time Error Interrupt Enable [9:9] read-write TXUE Tx Count Underflow Interrupt Enable [10:10] read-write TXOE Tx Count Overflow Interrupt Enable [11:11] read-write SE1E Scheduling Error 1 Interrupt Enable [12:12] read-write SE2E Scheduling Error 2 Interrupt Enable [13:13] read-write ELCE Change Error Level Interrupt Enable [14:14] read-write IWTE Initialization Watch Trigger Interrupt Enable [15:15] read-write WTE Watch Trigger Interrupt Enable [16:16] read-write AWE_ Application Watchdog Interrupt Enable [17:17] read-write CERE Configuration Error Interrupt Enable [18:18] read-write TTILS TT Interrupt Line Select 0x128 32 read-write 0x0 0x7FFFF SBCL Start of Basic Cycle Interrupt Line [0:0] read-write SMCL Start of Matrix Cycle Interrupt Line [1:1] read-write CSML Change of Synchronization Mode Interrupt Line [2:2] read-write SOGL Start of Gap Interrupt Line [3:3] read-write RTMIL Register Time Mark Interrupt Line [4:4] read-write TTMIL Trigger Time Mark Event Internal Line [5:5] read-write SWEL Stop Watch Event Interrupt Line [6:6] read-write GTWL Global Time Wrap Interrupt Line [7:7] read-write GTDL Global Time Discontinuity Interrupt Line [8:8] read-write GTEL Global Time Error Interrupt Line [9:9] read-write TXUL Tx Count Underflow Interrupt Line [10:10] read-write TXOL Tx Count Overflow Interrupt Line [11:11] read-write SE1L Scheduling Error 1 Interrupt Line [12:12] read-write SE2L Scheduling Error 2 Interrupt Line [13:13] read-write ELCL Change Error Level Interrupt Line [14:14] read-write IWTL Initialization Watch Trigger Interrupt Line [15:15] read-write WTL Watch Trigger Interrupt Line [16:16] read-write AWL_ Application Watchdog Interrupt Line [17:17] read-write CERL Configuration Error Interrupt Line [18:18] read-write TTOST TT Operation Status 0x12C 32 read-only 0x80 0xFFC0FFFF EL Error Level 00= Severity 0 - No Error 01= Severity 1 - Warning 10= Severity 2 - Error 11= Severity 3 - Severe Error [1:0] read-only MS Master State 00= Master_Off, no master properties relevant 01= Operating as Time Slave 10= Operating as Backup Time Master 11= Operating as current Time Master [3:2] read-only SYS Synchronization State 00= Out of Synchronization 01= Synchronizing to TTCAN communication 10= Schedule suspended by Gap (In_Gap) 11= Synchronized to schedule (In_Schedule) [5:4] read-only QGTP Quality of Global Time Phase Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'. 0= Global time not valid 1= Global time in phase with Time Master [6:6] read-only QCS Quality of Clock Speed Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'. 0= Local clock speed not synchronized to Time Master clock speed 1= Synchronization Deviation <= SDL [7:7] read-only RTO Reference Trigger Offset The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read. 0x00-FF Actual Reference Trigger offset value [15:8] read-only WGTD Wait for Global Time Discontinuity 0= No global time preset pending 1= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = '1' or after it received a reference message. [22:22] read-only GFI Gap Finished Indicator Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another node sending a reference message. 0= Reset at the end of each reference message 1= Gap finished by M_TTCAN [23:23] read-only TMP Time Master Priority 0x0-7 Priority of actual Time Master [26:24] read-only GSI Gap Started Indicator 0= No Gap in schedule, reset by each reference message and for all time slaves 1= Gap time after Basic Cycle has started [27:27] read-only WFE Wait for Event 0= No Gap announced, reset by a reference message with Next_is_Gap = '0' 1= Reference message with Next_is_Gap = '1' received [28:28] read-only AWE Application Watchdog Event The application watchdog is served by reading TTOST. When the watchdog is not served in time, bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring Mode. 0= Application Watchdog served in time 1= Failed to serve Application Watchdog in time [29:29] read-only WECS Wait for External Clock Synchronization 0= No external clock synchronization pending 1= Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle. [30:30] read-only SPL Schedule Phase Lock The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11). 0= Phase outside range 1= Phase inside range [31:31] read-only TURNA TUR Numerator Actual 0x130 32 read-only 0x10000 0x3FFFF NAV N/A [17:0] read-only TTLGT TT Local & Global Time 0x134 32 read-only 0x0 0xFFFFFFFF LT Local Time Non-fractional part of local time, incremented once each local NTU (see Section 4.5). 0x0000-FFFF Local time value of TTCAN node [15:0] read-only GT Global Time Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5). 0x0000-FFFF Global time value of TTCAN network [31:16] read-only TTCTC TT Cycle Time & Count 0x138 32 read-only 0x3F0000 0x3FFFFF CT Cycle Time Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5). 0x0000-FFFF Cycle time value of TTCAN Basic Cycle [15:0] read-only CC Cycle Count 0x00-3F Number of actual Basic Cycle in the System Matrix [21:16] read-only TTCPT TT Capture Time 0x13C 32 read-only 0x0 0xFFFF003F CCV Cycle Count Value Cycle count value captured together with SWV. 0x00-3F Captured cycle count value [5:0] read-only SWV Stop Watch Value On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE. 0x0000-FFFF Captured Stop Watch value [31:16] read-only TTCSM TT Cycle Sync Mark 0x140 32 read-only 0x0 0xFFFF CSM Cycle Sync Mark The Cycle Sync Mark is measured [15:0] read-only RXFTOP_CTL Receive FIFO Top control 0x180 32 read-write 0x0 0x3 F0TPE FIFO 0 Top Pointer Enable. This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter. This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1). When this logic is disabled a Read from RXFTOP0_DATA is undefined. [0:0] read-write F1TPE FIFO 1 Top Pointer Enable. [1:1] read-write RXFTOP0_STAT Receive FIFO 0 Top Status 0x1A0 32 read-only 0x0 0xFFFF F0TA Current FIFO 0 Top Address. This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC) FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC [15:0] read-only RXFTOP0_DATA Receive FIFO 0 Top Data 0x1A8 32 read-only 0x0 0x0 F0TD When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met: - M_TTCAN not being reconfigured (CCCR.CCE=0) - FIFO Top Pointer logic is enabled (FnTPE=1) - FIFO is not empty (FnFL!=0) The read side effect is as follows: - if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI - FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message) - the FIFO top address FnTA is incremented (with FIFO wrap around) When this logic is disabled (F0TPE=0) a Read from this register returns undefined data. [31:0] read-only RXFTOP1_STAT Receive FIFO 1 Top Status 0x1B0 32 read-only 0x0 0xFFFF F1TA See F0TA description [15:0] read-only RXFTOP1_DATA Receive FIFO 1 Top Data 0x1B8 32 read-only 0x0 0x0 F1TD See F0TD description [31:0] read-only CTL Global CAN control register 0x1000 32 read-write 0x0 0x800000FF STOP_REQ Clock Stop Request for each TTCAN IP . The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits. [7:0] read-write MRAM_OFF MRAM off 0= Default MRAM on (with MRAM retained in DeepSleep). 1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode. [31:31] read-write STATUS Global CAN status register 0x1004 32 read-only 0x0 0xFF STOP_ACK Clock Stop Acknowledge for each TTCAN IP. These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP. When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write [7:0] read-only INTR0_CAUSE Consolidated interrupt0 cause register 0x1010 32 read-only 0x0 0xFF INT0 Show pending m_ttcan_int0 of each channel [7:0] read-only INTR1_CAUSE Consolidated interrupt1 cause register 0x1014 32 read-only 0x0 0xFF INT1 Show pending m_ttcan_int1 of each channel [7:0] read-only TS_CTL Time Stamp control register 0x1020 32 read-write 0x0 0x8000FFFF PRESCALE Time Stamp counter prescale value. When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks. [15:0] read-write ENABLED Counter enable bit 0 = Count disabled. Stop counting up and keep the counter value 1 = Count enabled. Start counting up from the current value [31:31] read-write TS_CNT Time Stamp counter value 0x1024 32 read-write 0x0 0xFFFF VALUE The counter value of the Time Stamp Counter. When enabled this counter will count Time Stamp clock ticks from the pre-scaler. When written this counter and the pre-scaler will reset to 0 (write data is ignored). [15:0] read-write ECC_CTL ECC control 0x1080 32 read-write 0x0 0x10000 ECC_EN Enable ECC for CANFD SRAM When disabled also all error injection functionality is disabled. [16:16] read-write ECC_ERR_INJ ECC error injection 0x1084 32 read-write 0xFFFC 0x7F10FFFC ERR_ADDR Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed. When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address. When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown. Note that error reporting to the fault structure cannot be suppressed. [15:2] read-write ERR_EN Enable error injection (ECC_EN must be 1). When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address. When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set). When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or AHB bus. [20:20] read-write ERR_PAR ECC Parity bits to use for ECC error injection at address ERR_ADDR. [30:24] read-write CANFD1 0x40540000 SCB0 Serial Communications Block (SPI/UART/I2C) SCB 0x40600000 0 65536 registers CTRL Generic control 0x0 32 read-write 0x300400F 0x9303D70F OVS N/A [3:0] read-write EC_AM_MODE Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. In UART mode this field should be '0'. [8:8] read-write EC_OP_MODE Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). In UART mode this field should be '0'. [9:9] read-write EZ_MODE Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. In UART mode this field should be '0'. [10:10] read-write CMD_RESP_MODE Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled. '1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). [12:12] read-write MEM_WIDTH Determines the number of bits per FIFO data element. [15:14] read-write BYTE 8-bit FIFO data elements. This mode provides the biggest amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. 0 HALFWORD 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 15]. 1 WORD 32-bit FIFO data elements. This mode provides the smallest amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH can be in a range of [0, 31]. 2 RSVD N/A 3 ADDR_ACCEPT Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers. In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. [16:16] read-write BLOCK Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX. [17:17] read-write MODE N/A [25:24] read-write I2C Inter-Integrated Circuits (I2C) mode. 0 SPI Serial Peripheral Interface (SPI) mode. 1 UART Universal Asynchronous Receiver/Transmitter (UART) mode. 2 EC_ACCESS used to enable I2CS_EC or SPIS_EC access to internal SRAM memory. 0: enable clock_scb_en, has no effect on ec_busy_pp 1: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access) Before going to deepsleep this field should be set to 1. when waking up from DeepSleep power mode, and PLL is locked (clk_scb is at expected frequency), this filed should be set to 0. [28:28] read-write ENABLED IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: - Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. - Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. - Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. - Program CTRL to enable IP, select the specific operation mode and oversampling factor. Generally hen the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). Specific to SPI master case, when SCB is idle, below registers can be changed without disabling SCB block, TX_CTRL TX_FIFO_CTRL RX_CTRL RX_FIFO_CTRL SPI_CTRL.SSEL, [31:31] read-write STATUS Generic status 0x4 32 read-only 0x0 0x0 EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. [0:0] read-only CMD_RESP_CTRL Command/response control 0x8 32 read-write 0x0 0x1FF01FF BASE_RD_ADDR I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. [8:0] read-write BASE_WR_ADDR I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. [24:16] read-write CMD_RESP_STATUS Command/response status 0xC 32 read-only 0x0 0x0 CURR_RD_ADDR I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. [8:0] read-only CURR_WR_ADDR I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. [24:16] read-only CMD_RESP_EC_BUS_BUSY Indicates whether there is an ongoing bus transfer to the IP. '0': no ongoing bus transfer. '1': ongoing bus transfer. For SPI, the field is '1' when the slave is selected. For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. [30:30] read-only CMD_RESP_EC_BUSY Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note: - When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable). - When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW. - When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW. Note that this update lasts one I2C clock cycle, or two SPI clock cycles. [31:31] read-only SPI_CTRL SPI control 0x20 32 read-write 0x3000010 0x8F017F3F SSEL_CONTINUOUS Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: data frames are always separated by slave deselection. [0:0] read-write SELECT_PRECEDE Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. [1:1] read-write CPHA Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: - Motorola mode 0. CPOL is '0', CPHA is '0': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. - Motorola mode 1. CPOL is '0', CPHA is '1': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 2. CPOL is '1', CPHA is '0': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 3. CPOL is '1', CPHA is '1': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. In SPI Motorola submode, all four CPOL/CPHA modes are valid. in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. [2:2] read-write CPOL Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: - CPOL is '0': SCLK is '0' when not transmitting data. - CPOL is '1': SCLK is '1' when not transmitting data. [3:3] read-write LATE_MISO_SAMPLE Changes the SCLK edge on which MISO is captured. Only used in master mode. When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. [4:4] read-write SCLK_CONTINUOUS Only applicable in master mode. '0': SCLK is generated, when the SPI master is enabled and data is transmitted. '1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality. [5:5] read-write SSEL_POLARITY0 Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes: '0': slave select is low/'0' active. '1': slave select is high/'1' active. For Texas Instruments submode: '0': high/'1' active precede/coincide pulse. '1': low/'0' active precede/coincide pulse. [8:8] read-write SSEL_POLARITY1 Slave select polarity. [9:9] read-write SSEL_POLARITY2 Slave select polarity. [10:10] read-write SSEL_POLARITY3 Slave select polarity. [11:11] read-write SSEL_SETUP_DEL Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit). '0': 0.75 SPI clock cycles '1': 1.75 SPI clock cycles Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0, CTRL.OVS>=3. above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle. [12:12] read-write SSEL_HOLD_DEL Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit, and SELECT deactivation). '0': 0.75 SPI clock cycles '1': 1.75 SPI clock cycles Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0, CTRL.OVS>=3. above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle. [13:13] read-write SSEL_INTER_FRAME_DEL Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation). '0': 1.5 SPI clock cycles '1': 2.5 SPI clock cycles Only applies in SPI MOTOROLA submode and when SPI_CTRL.SSEL_CONTINUOUS=0, CTRL.OVS>=3. above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle. [14:14] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. '0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin. '1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. [16:16] read-write MODE N/A [25:24] read-write SPI_MOTOROLA SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. 0 SPI_TI SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. 1 SPI_NS SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. 2 SSEL Selects one of the four incoming/outgoing SPI slave select signals: - 0: Slave 0, SSEL[0]. - 1: Slave 1, SSEL[1]. - 2: Slave 2, SSEL[2]. - 3: Slave 3, SSEL[3]. The IP should be disabled when changes are made to this field. [27:26] read-write MASTER_MODE Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. [31:31] read-write SPI_STATUS SPI status 0x24 32 read-only 0x0 0x0 BUS_BUSY SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. [0:0] read-only SPI_EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. [1:1] read-only CURR_EZ_ADDR SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only SPI_TX_CTRL SPI transmitter control 0x28 32 read-write 0x0 0x30 PARITY Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. [4:4] read-write PARITY_ENABLED Parity generation enabled ('1') or not ('0'). [5:5] read-write SPI_RX_CTRL SPI receiver control 0x2C 32 read-write 0x0 0x130 PARITY Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. [4:4] read-write PARITY_ENABLED Parity checking enabled ('1') or not ('0'). [5:5] read-write DROP_ON_PARITY_ERROR Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. [8:8] read-write UART_CTRL UART control 0x40 32 read-write 0x3000000 0x3010000 LOOPBACK Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'. This allows a SCB UART transmitter to communicate with its receiver counterpart. [16:16] read-write MODE N/A [25:24] read-write UART_STD Standard UART submode. 0 UART_SMARTCARD SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. 1 UART_IRDA Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. 2 UART_TX_CTRL UART transmitter control 0x44 32 read-write 0x2 0x137 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. [2:0] read-write PARITY Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware [5:5] read-write RETRY_ON_NACK When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. [8:8] read-write UART_RX_CTRL UART receiver control 0x48 32 read-write 0xA0002 0x10F3777 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value. [2:0] read-write PARITY Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. [5:5] read-write POLARITY Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. [6:6] read-write DROP_ON_PARITY_ERROR Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). [8:8] read-write DROP_ON_FRAME_ERROR Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. [9:9] read-write MP_MODE Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped. [10:10] read-write LIN_MODE Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. [12:12] read-write SKIP_START Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. [13:13] read-write BREAK_WIDTH Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. [19:16] read-write BREAK_LEVEL 0: low level pulse detection, like Break field in LIN protocol 1: high level pulse detection, like IFS field in CXPI protocol, or idle line state in UART [24:24] read-write UART_RX_STATUS UART receiver status 0x4C 32 read-only 0x0 0x0 BR_COUNTER Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. [11:0] read-only UART_FLOW_CTRL UART flow control 0x50 32 read-write 0x0 0x30100FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes). [7:0] read-write RTS_POLARITY Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive. '1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive. During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity. [16:16] read-write CTS_POLARITY Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive. '1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive. [24:24] read-write CTS_ENABLED Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). [25:25] read-write I2C_CTRL I2C control 0x60 32 read-write 0xFB88 0xC001FBFF HIGH_PHASE_OVS Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles. [3:0] read-write LOW_PHASE_OVS Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. The field is mainly used in master mode. In slave mode, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be >= 8 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles. in slave mode, this field is used to define number of clk_scb cycles for tSU-DAT timing (from ACK/NACK/data ready, to SCL rising edge (released from I2C slave clock stretching)) [7:4] read-write M_READY_DATA_ACK When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. [8:8] read-write M_NOT_READY_DATA_NACK When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). [9:9] read-write S_GENERAL_IGNORE When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. [11:11] read-write S_READY_ADDR_ACK When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. [12:12] read-write S_READY_DATA_ACK When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. [13:13] read-write S_NOT_READY_ADDR_NACK For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when: - EC_AM is '0', EC_OP is '0' and non EZ mode. Functionality is as follows: - 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): - EC_AM is '1' and EC_OP is '0'. - EC_AM is '1' and general call address match. - EC_AM is '1' and non EZ mode. Functionality is as follows: - 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). - 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled. [14:14] read-write S_NOT_READY_DATA_NACK For internally clocked logic only. Only used when: - non EZ mode. Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). [15:15] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. [16:16] read-write SLAVE_MODE Slave mode enabled ('1') or not ('0'). [30:30] read-write MASTER_MODE Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. [31:31] read-write I2C_STATUS I2C status 0x64 32 read-only 0x0 0x35 BUS_BUSY I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). [0:0] read-only I2C_EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. [1:1] read-only I2CS_IC_BUSY Indicates whether the internally clocked slave logic is being accessed by external I2C master. --set at ADDR_MATCH --clear at START/RESET, STOP detection, or BUS_ERROR This bit can be used by SW to determine whether I2CS_IC is busy before entering DeepSleep. [2:2] read-only S_READ I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. [4:4] read-only M_READ I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. [5:5] read-only CURR_EZ_ADDR I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only I2C_M_CMD I2C master command 0x68 32 read-write 0x0 0x1F M_START When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. [0:0] read-write M_START_ON_IDLE When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. [1:1] read-write M_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. [2:2] read-write M_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. [3:3] read-write M_STOP When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. [4:4] read-write I2C_S_CMD I2C slave command 0x6C 32 read-write 0x0 0x3 S_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). [0:0] read-write S_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. [1:1] read-write I2C_CFG I2C configuration 0x70 32 read-write 0x2A1013 0x303F1313 SDA_IN_FILT_TRIM Trim bits for 'i2c_sda_in' 50 ns filter. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [1:0] read-write SDA_IN_FILT_SEL Selection of 'i2c_sda_in' filter delay: '0': 0 ns. '1: 50 ns (filter enabled). [4:4] read-write SCL_IN_FILT_TRIM Trim bits for 'i2c_scl_in' 50 ns filter. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [9:8] read-write SCL_IN_FILT_SEL Selection of 'i2c_scl_in' filter delay: '0': 0 ns. '1: 50 ns (filter enabled). [12:12] read-write SDA_OUT_FILT0_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 0. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [17:16] read-write SDA_OUT_FILT1_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 1. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [19:18] read-write SDA_OUT_FILT2_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 2. for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values. For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values. [21:20] read-write SDA_OUT_FILT_SEL Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns. '1': 50 ns (filter 0 enabled). '2': 100 ns (filters 0 and 1 enabled). '3': 150 ns (filters 0, 1 and 2 enabled). [29:28] read-write TX_CTRL Transmitter control 0x200 32 read-write 0x107 0x1011F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 31]. For I2C the only valid value is 7. [4:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write OPEN_DRAIN Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. '0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. '1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). The open drain mode is supported for: - UART mode, 'uart_tx' IO cell. - SPI mode, 'spi_miso' IO cell. not applicable to I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. (I2C SCL/SDA always work in open-drain mode) [16:16] read-write TX_FIFO_CTRL Transmitter FIFO control 0x204 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. [7:0] read-write CLEAR When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. [17:17] read-write TX_FIFO_STATUS Transmitter FIFO status 0x208 32 read-only 0x0 0xFFFF81FF USED Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). [8:0] read-only SR_VALID Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read by the hardware. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written. [31:24] read-only TX_FIFO_WR Transmitter FIFO write 0x240 32 write-only 0x0 0xFFFFFFFF DATA Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used. A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. [31:0] write-only RX_CTRL Receiver control 0x300 32 read-write 0x107 0x31F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 31]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. [4:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write MEDIAN Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. [9:9] read-write RX_FIFO_CTRL Receiver FIFO control 0x304 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. [7:0] read-write CLEAR When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. [17:17] read-write RX_FIFO_STATUS Receiver FIFO status 0x308 32 read-only 0x0 0xFFFF81FF USED Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). [8:0] read-only SR_VALID Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written by the hardware. [31:24] read-only RX_MATCH Slave address and mask 0x310 32 read-write 0x0 0xFF00FF ADDR Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). [7:0] read-write MASK Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK)). [23:16] read-write RX_FIFO_RD Receiver FIFO read 0x340 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used. This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [31:0] read-only RX_FIFO_RD_SILENT Receiver FIFO read silent 0x344 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [31:0] read-only INTR_CAUSE Active clocked interrupt signal 0xE00 32 read-only 0x0 0x3F M Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. [0:0] read-only S Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. [1:1] read-only TX Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. [2:2] read-only RX Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. [3:3] read-only I2C_EC Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. [4:4] read-only SPI_EC Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. [5:5] read-only INTR_I2C_EC Externally clocked I2C interrupt request 0xE80 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request (with address match). Only used when EC_AM is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (I2C STOP). Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [3:3] read-write INTR_I2C_EC_MASK Externally clocked I2C interrupt mask 0xE88 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_I2C_EC_MASKED Externally clocked I2C interrupt masked 0xE8C 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_SPI_EC Externally clocked SPI interrupt request 0xEC0 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request when externally clocked selection is '1'. Only used when EC_AM is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (SPI deselection). Only available in EZ and CMD_RESP mode and when EC_OP is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only used in EZ and CMD_RESP modes and when EC_OP is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. Only used in EZ and CMD_RESP modes and when EC_OP is '1'. [3:3] read-write INTR_SPI_EC_MASK Externally clocked SPI interrupt mask 0xEC8 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_SPI_EC_MASKED Externally clocked SPI interrupt masked 0xECC 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_M Master interrupt request 0xF00 32 read-write 0x0 0x317 I2C_ARB_LOST I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. [0:0] read-write I2C_NACK I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). [1:1] read-write I2C_ACK I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). [2:2] read-write I2C_STOP I2C master STOP. Set to '1', when the master has transmitted a STOP. [4:4] read-write I2C_BUS_ERROR I2C master bus error (unexpected detection of START or STOP condition). [8:8] read-write SPI_DONE SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. [9:9] read-write INTR_M_SET Master interrupt set request 0xF04 32 read-write 0x0 0x317 I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASK Master interrupt mask 0xF08 32 read-write 0x0 0x317 I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASKED Master interrupt masked request 0xF0C 32 read-only 0x0 0x317 I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_DONE Logical and of corresponding request and mask bits. [9:9] read-only INTR_S Slave interrupt request 0xF40 32 read-write 0x0 0xFFF I2C_ARB_LOST I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [0:0] read-write I2C_NACK I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). [1:1] read-write I2C_ACK I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). [2:2] read-write I2C_WRITE_STOP I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected). [3:3] read-write I2C_STOP I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. [4:4] read-write I2C_START I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. [5:5] read-write I2C_ADDR_MATCH I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. [6:6] read-write I2C_GENERAL I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. [7:7] read-write I2C_BUS_ERROR I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [8:8] read-write SPI_EZ_WRITE_STOP SPI slave deselected after a write EZ SPI transfer occurred. [9:9] read-write SPI_EZ_STOP SPI slave deselected after any EZ SPI transfer occurred. [10:10] read-write SPI_BUS_ERROR SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [11:11] read-write INTR_S_SET Slave interrupt set request 0xF44 32 read-write 0x0 0xFFF I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_START Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASK Slave interrupt mask 0xF48 32 read-write 0x0 0xFFF I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_START Mask bit for corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Mask bit for corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Mask bit for corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Mask bit for corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASKED Slave interrupt masked request 0xF4C 32 read-only 0x0 0xFFF I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_WRITE_STOP Logical and of corresponding request and mask bits. [3:3] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_START Logical and of corresponding request and mask bits. [5:5] read-only I2C_ADDR_MATCH Logical and of corresponding request and mask bits. [6:6] read-only I2C_GENERAL Logical and of corresponding request and mask bits. [7:7] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_EZ_WRITE_STOP Logical and of corresponding request and mask bits. [9:9] read-only SPI_EZ_STOP Logical and of corresponding request and mask bits. [10:10] read-only SPI_BUS_ERROR Logical and of corresponding request and mask bits. [11:11] read-only INTR_TX Transmitter interrupt request 0xF80 32 read-write 0x0 0x7F3 TRIGGER Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL. Only used in FIFO mode. [0:0] read-write NOT_FULL TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2) MEM_WIDTH is '0': # entries != FF_DATA_NR. MEM_WIDTH is '1': # entries != FF_DATA_NR/2. MEM_WIDTH is '2': # entries != FF_DATA_NR/4. Only used in FIFO mode. [1:1] read-write EMPTY TX FIFO is empty; i.e. it has 0 entries. Only used in FIFO mode. [4:4] read-write OVERFLOW Attempt to write to a full TX FIFO. Only used in FIFO mode. [5:5] read-write UNDERFLOW Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. Only used in FIFO mode. [6:6] read-write BLOCKED AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write UART_NACK UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. [8:8] read-write UART_DONE UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit. [9:9] read-write UART_ARB_LOST UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit. [10:10] read-write INTR_TX_SET Transmitter interrupt set request 0xF84 32 read-write 0x0 0x7F3 TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write EMPTY Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write UART_NACK Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write UART_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASK Transmitter interrupt mask 0xF88 32 read-write 0x0 0x7F3 TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Mask bit for corresponding bit in interrupt request register. [1:1] read-write EMPTY Mask bit for corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write UART_NACK Mask bit for corresponding bit in interrupt request register. [8:8] read-write UART_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Mask bit for corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASKED Transmitter interrupt masked request 0xF8C 32 read-only 0x0 0x7F3 TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_FULL Logical and of corresponding request and mask bits. [1:1] read-only EMPTY Logical and of corresponding request and mask bits. [4:4] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only UART_NACK Logical and of corresponding request and mask bits. [8:8] read-only UART_DONE Logical and of corresponding request and mask bits. [9:9] read-only UART_ARB_LOST Logical and of corresponding request and mask bits. [10:10] read-only INTR_RX Receiver interrupt request 0xFC0 32 read-write 0x0 0xFED TRIGGER More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL. Only used in FIFO mode. [0:0] read-write NOT_EMPTY RX FIFO is not empty. Only used in FIFO mode. [2:2] read-write FULL RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2) MEM_WIDTH is '0': # entries == FF_DATA_NR. MEM_WIDTH is '1': # entries == FF_DATA_NR/2. MEM_WIDTH is '2': # entries == FF_DATA_NR/4. Only used in FIFO mode. [3:3] read-write OVERFLOW Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. Only used in FIFO mode. [5:5] read-write UNDERFLOW Attempt to read from an empty RX FIFO. Only used in FIFO mode. [6:6] read-write BLOCKED AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write FRAME_ERROR Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error: Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. [8:8] read-write PARITY_ERROR Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. [9:9] read-write BAUD_DETECT LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit. [10:10] read-write BREAK_DETECT Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. [11:11] read-write INTR_RX_SET Receiver interrupt set request 0xFC4 32 read-write 0x0 0xFED TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Write with '1' to set corresponding bit in interrupt status register. [2:2] read-write FULL Write with '1' to set corresponding bit in interrupt status register. [3:3] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt status register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt status register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt status register. [7:7] read-write FRAME_ERROR Write with '1' to set corresponding bit in interrupt status register. [8:8] read-write PARITY_ERROR Write with '1' to set corresponding bit in interrupt status register. [9:9] read-write BAUD_DETECT Write with '1' to set corresponding bit in interrupt status register. [10:10] read-write BREAK_DETECT Write with '1' to set corresponding bit in interrupt status register. [11:11] read-write INTR_RX_MASK Receiver interrupt mask 0xFC8 32 read-write 0x0 0xFED TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Mask bit for corresponding bit in interrupt request register. [2:2] read-write FULL Mask bit for corresponding bit in interrupt request register. [3:3] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write FRAME_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write PARITY_ERROR Mask bit for corresponding bit in interrupt request register. [9:9] read-write BAUD_DETECT Mask bit for corresponding bit in interrupt request register. [10:10] read-write BREAK_DETECT Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_RX_MASKED Receiver interrupt masked request 0xFCC 32 read-only 0x0 0xFED TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_EMPTY Logical and of corresponding request and mask bits. [2:2] read-only FULL Logical and of corresponding request and mask bits. [3:3] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only FRAME_ERROR Logical and of corresponding request and mask bits. [8:8] read-only PARITY_ERROR Logical and of corresponding request and mask bits. [9:9] read-only BAUD_DETECT Logical and of corresponding request and mask bits. [10:10] read-only BREAK_DETECT Logical and of corresponding request and mask bits. [11:11] read-only SCB1 0x40610000 SCB2 0x40620000 SCB3 0x40630000 SCB4 0x40640000 SCB5 0x40650000 SCB6 0x40660000 SCB7 0x40670000 PASS0 Programmable Analog Subsystem for S40E PASS 0x40900000 0 1048576 registers 3 4096 SAR[%s] SAR ADC with Sequencer for S40E 0x00000000 CTL Analog control register. 0x0 32 read-write 0x0 0xE00007FF PWRUP_TIME Number cycles to wait to power up after IDLE_PWRDWN. Check the STATUS.PWRUP_BUSY flag to see if the delay is still in progress. The power up delay is 1 us. [7:0] read-write IDLE_PWRDWN When idle automatically power down the analog. After an automatic power down a new trigger will power up the analog, however it will take PWRUP_TIME cycles before the first acquisition can be started. Note that re-arbitration happens at that time, i.e. the trigger that caused the power up may not get handled first. [8:8] read-write MSB_STRETCH When set use 2 cycles for the Most Significant Bit (MSB) - 0: Use 1 clock cycle for MSB - 1: Use 2 clock cycles for MSB [9:9] read-write HALF_LSB When set take an extra cycle to convert the half LSB and add it to 12-bit result for Missing Code Recovery This bit should always be set to '1' - 0: disable half LSB conversion (not recommended) - 1: enable half LSB conversion [10:10] read-write SARMUX_EN Enable the SARMUX (only valid if ENABLED=1) - 0: SARMUX disabled (put analog in power down) - 1: SARMUX enabled. [29:29] read-write ADC_EN Enable the SAR ADC and SAR sequencer (only valid if ENABLED=1) - 0: SARADC and SARSEQ are disabled (put SARADC analog in power down and stop clocks), also clears all pending triggers. - 1: SAR ADC and SARSEQ are enabled. To enable ADC0 to borrow SARMUX1-3 the corresponding ADC_EN must be set to 0. [30:30] read-write ENABLED - 0: SAR IP disabled (put analog in power down and stop clocks), also clears all pending triggers. - 1: SAR IP enabled. [31:31] read-write DIAG_CTL Diagnostic Reference control register. 0x4 32 read-write 0x0 0x8000000F DIAG_SEL Select Diagnostic Reference function [3:0] read-write VREFL DiagOut = VrefL 0 VREFH_1DIV8 DiagOut = VrefH * 1/8 1 VREFH_2DIV8 DiagOut = VrefH * 2/8 2 VREFH_3DIV8 DiagOut = VrefH * 3/8 3 VREFH_4DIV8 DiagOut = VrefH * 4/8 4 VREFH_5DIV8 DiagOut = VrefH * 5/8 5 VREFH_6DIV8 DiagOut = VrefH * 6/8 6 VREFH_7DIV8 DiagOut = VrefH * 7/8 7 VREFH DiagOut = VrefH 8 VREFX DiagOut = VrefX = VrefH * 199/200 9 VBG DiagOut = Vbg from SRSS 10 VIN1 DiagOut = Vin1 11 VIN2 DiagOut = Vin2 12 VIN3 DiagOut = Vin3 13 I_SOURCE DiagOut = Isource (10uA) 14 I_SINK DiagOut = Isink (10uA) 15 DIAG_EN Diagnostic Reference enable (only valid if ENABLED=1) - 0: Diagnostic Reference disabled (powered down resistor ladder and current mirrors, DiagOut = Vssa). - 1: Diagnostic Reference enabled, output signal select according to DIAG_SEL (note also EPASS_MMIO.PASS_CTL.REFBUF_EN must be set). [31:31] read-write PRECOND_CTL Preconditioning control register. 0x10 32 read-write 0x0 0xF PRECOND_TIME Number ADC clock cycles that Preconditioning is done before the sample window starts. If OVERLAP_EN=0 there will be 1 additional break before make cycle between preconditioning and sampling. Note that the minimum value is 1 (0 gives the same result as 1). [3:0] read-write ANA_CAL Current analog calibration values 0x80 32 read-write 0x0 0x1F00FF AOFFSET Analog offset correction [7:0] read-write AGAIN Analog gain correction [20:16] read-write DIG_CAL Current digital calibration values 0x84 32 read-write 0x0 0x3F0FFF DOFFSET Digital offset correction Subtract DOFFSET from ADC output. [11:0] read-write DGAIN Digital gain correction. Signed value to correct +/- 30 codes for the maximum input voltage. Corrected = (D - DOFFSET) + ( (D - DOFFSET) * DGAIN + 0x800) / 0x1000 [21:16] read-write ANA_CAL_ALT Alternate analog calibration values 0x90 32 read-write 0x0 0x1F00FF AOFFSET See corresponding ANA_CAL field [7:0] read-write AGAIN See corresponding ANA_CAL field [20:16] read-write DIG_CAL_ALT Alternate digital calibration values 0x94 32 read-write 0x0 0x3F0FFF DOFFSET See corresponding DIG_CAL field [11:0] read-write DGAIN See corresponding DIG_CAL field [21:16] read-write CAL_UPD_CMD Calibration update command 0x98 32 read-write 0x0 0x1 UPDATE Calibration update command: coherently copy values from alternate calibration regs to current calibration regs. Software sets this bit when the alternate calibration values have been set with the new values. Hardware will do the calibration update as soon as the ADC is idle or a 'continuous' triggered group completes. This ensures that all acquisitions within a group scan (even if preempted) are done with the same calibration values. This bit is cleared at the same time the calibration update is done. By clearing this bit software can cancel a requested update. Note: if the ADC is always busy with acquisitions for non continuously triggered groups/channels then the calibration update will remain pending forever. In such a case the software can either do a non coherent update by writing directly to the current calibration registers, or software can force the ADC to idle by disabling some or all channels. Software can check/poll this bit to see if the calibration update has taken effect. [0:0] read-write TR_PEND Trigger pending status 0x100 32 read-only 0x0 0xFFFFFFFF TR_PEND Trigger Pending. Hardware will set this bit if a hardware trigger is received. [31:0] read-only WORK_VALID Channel working data register 'valid' bits 0x180 32 read-only 0x0 0xFFFFFFFF WORK_VALID If set the corresponding WORK register is valid, i.e. was already acquired during the current group scan. If this bit is low then either the channel is not enabled, not yet acquired or it is used as a pulse detect channel. [31:0] read-only WORK_RANGE Range detected 0x184 32 read-only 0x0 0xFFFFFFFF RANGE N/A [31:0] read-only WORK_RANGE_HI Range detect above Hi flag 0x188 32 read-only 0x0 0xFFFFFFFF ABOVE_HI Out of range was detected and the value was above the Hi threshold [31:0] read-only WORK_PULSE Pulse detected 0x18C 32 read-only 0x0 0xFFFFFFFF PULSE N/A [31:0] read-only RESULT_VALID Channel result data register 'valid' bits 0x1A0 32 read-only 0x0 0xFFFFFFFF RESULT_VALID If set the corresponding RESULT register is valid, i.e. was acquired during the preceding group scan. If this bit is low, after a group scan completed, then either the channel is not enabled or is used as a pulse detect channel. [31:0] read-only RESULT_RANGE_HI Channel Range above Hi flags 0x1A4 32 read-only 0x0 0xFFFFFFFF ABOVE_HI Out of range was detected and the value was above the Hi threshold [31:0] read-only STATUS Current status of internal SAR registers (mostly for debug) 0x200 32 read-only 0x0 0xE000371F CUR_CHAN current channel being acquired, only valid if BUSY. [4:0] read-only CUR_PRIO priority of current group/channel, only valid if BUSY. [10:8] read-only CUR_PREEMPT_TYPE Preempting type of current group/channel, only valid if BUSY. [13:12] read-only DBG_FREEZE If high then the SAR is prevented from starting a new acquisition, see DBG_FREEZE_EN. [29:29] read-only PWRUP_BUSY If high then the SAR is waiting for PWRUP_TIME due to IDLE_PWRDWN [30:30] read-only BUSY If high then the SAR is busy with a conversion. [31:31] read-only AVG_STAT Current averaging status (for debug) 0x204 32 read-only 0x0 0xFF0FFFFF CUR_AVG_ACCU the current value of the averaging accumulator [19:0] read-only CUR_AVG_CNT the current value of the averaging counter. Note that the value shown is updated after the sample window and therefore runs ahead of the accumulator update. [31:24] read-only 32 64 CH[%s] Channel structure 0x00000800 TR_CTL Trigger control. 0x0 32 read-write 0x800 0x80000B77 SEL Trigger select [2:0] read-write OFF Use for channels in group, except the first channel 0 TCPWM Trigger from corresponding TCPWM channel 1 GENERIC0 Generic trigger input 0 2 GENERIC1 N/A 3 GENERIC2 N/A 4 GENERIC3 N/A 5 GENERIC4 N/A 6 CONTINUOUS Always triggered (also called idle), can only be used for at most 1 channel 7 PRIO Channel priority: '0': highest priority. '1' ... '6' '7': lowest priority. Channels with the same priority constitute a priority level. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority level with pending channels is identified. Second, within this priority level, round robin arbitration is applied. Round robin arbitration (within a priority level) gives the highest priority to the lower channel indices (within the priority level). [6:4] read-write PREEMPT_TYPE Preemption type allow for this group [9:8] read-write ABORT_CANCEL Abort ongoing acquisition, do not return Clear pending trigger for aborted group and set Cancelled interrupt. Also 'Abort' whenever this group (do not pend the trigger) is not immediately scheduled for acquisition after a new trigger arrives. For this preemption type only, only a positive edge on the trigger can trigger the channel, i.e. CONTINUOUS or level high operation is not supported (to avoid continuous Cancelled interrupts). In case CTL.IDLE_PWRDWN is used and the analog is powered down, the group cannot be immediately scheduled for acquisition and therefore a trigger for a group with this preemption type will power up the analog, but the group will ABORT and set the Cancelled interrupt 0 ABORT_RESTART Abort ongoing acquisition, up on return Restart group from first channel. 1 ABORT_RESUME Abort ongoing acquisition, up on return Resume group from aborted channel If averaging, discard averaging results so far and restart averaging. 2 FINISH_RESUME Complete ongoing acquisition (including averaging), up on return Resume group from next channel 3 GROUP_END 0: continue group with next channel 1: last channel of a group. Note that for the channel with the highest index (SAR_CH_NR) this always needs to be set [11:11] read-write DONE_LEVEL select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO [31:31] read-write PULSE tr_ch_done generates a 2 cycle pulse (clk_sys), no need to read the result to clear (also no ch_overflow detection) 0 LEVEL tr_ch_done is a level output until the result register is read (typical for DW usage, this also enables ch_overflow detection when DW is too slow) 1 SAMPLE_CTL Sample control. 0x4 32 read-write 0x0 0x0 PIN_ADDR N/A [5:0] read-write PORT_ADDR Select the physical port. This field is only valid for ADC0. ADC0 can control and connect to the SARMUX of the neighboring ADC1-3. This requires the corresponding ADC to be off while the SARMUX is left on. When ADC0 controls another SARMUX it uses the PIN_ADDR, EXT_MUX_EN/SEL of this channel to control the other SARMUX. [7:6] read-write SARMUX0 ADC uses it's own SARMUX 0 SARMUX1 ADC0 uses SARMUX1 (only valid for ADC0, undefined result if used for ADC1-3) 1 SARMUX2 ADC0 uses SARMUX2 (only valid for ADC0, undefined result if used for ADC1-3) 2 SARMUX3 ADC0 uses SARMUX3 (only valid for ADC0, undefined result if used for ADC1-3) 3 EXT_MUX_SEL External analog mux select. This bit setting is related to EXT_MUX[x]_y on pin assignment. 0x0: Select EXT_MUX[x]_0 pin 0x1: Select EXT_MUX[x]_1 pin [10:8] read-write EXT_MUX_EN External analog mux enable. This enable can be used as enable (chip select) for the external analog mux (this enable is not used as enable for the GPIO output driver). This enable also prevents unnecessary toggle activity on the select signals of the external analog mux. When this enable is low EXT_MUX_SEL value will be ignored and the previous value will be maintained. Note that an external analog mux can only be used in combination with a pin input, i.e. PIN_ADDR<32 or Vmotor. If an internal signal is selected this enable should be 0. [11:11] read-write PRECOND_MODE Select preconditioning mode. Preconditioning (dis)charges the SAR sample capacitor to the selected reference voltage for PRECOND_TIME (global) cycles, a break before make cycle will be inserted before sampling starts (SAMPLE_TIME). [13:12] read-write OFF No preconditioning 0 VREFL Discharge to VREFL 1 VREFH Charge to VREFH 2 DIAG Connect the Diagnostic reference output during preconditioning. The Diagnostic reference should be configured to output a reference voltage. Note: this selection is mutual exclusive with using the Diagnostic reference to supply an ibias current for OVERLAP. 3 OVERLAP_DIAG Select Overlap mode or SARMUX Diagnostics, in both cases the Diagnostic reference is used. With Overlap the Diagnostic reference typically sources or sinks a small current which is connected at the same time as the analog signal being sampled. For SARMUX Diagnostics the Diagnostic reference should provide a reference voltage which is selected at the SARMUX input instead of the normal analog signal being sampled. [15:14] read-write OFF No overlap or SARMUX Diagnostics 0 HALF Sample the selected analog input for 2 SAMPLE_TIME periods. During the first period use overlap sampling, i.e. connect both the analog input and Diagnostic reference. During second period only connect the analog input. 1 FULL Like normal sample the selected analog input for a single SAMPLE_TIME period but use overlap sampling, i.e. connect both the analog input and Diagnostic reference. 2 MUX_DIAG Select Diagnostic reference instead of analog signal at the input of the SARMUX. This enables a functional safety check of the SARMUX analog connections. 3 SAMPLE_TIME Sample time (aperture) in ADC clock cycles. Minimum is 1 (0 gives the same result as 1), minimum time needed for proper settling is at least 412ns, i.e.11 clock cycles at the max frequency of 26.7MHz. [27:16] read-write ALT_CAL Use alternate calibration values instead of the current calibration values. This allows the firmware to allocate one or more channels to quietly re-calibrate the ADC in the background of regular processing. 0 = use regular calibration values (ANA/DIG_CAL) 1 = use alternate calibration values (ANA/DIG_CAL_ALT) Note: typically calibration measurements select VrefL (PIN_ADDR=62) or VrefH (PIN_ADDR=63) [31:31] read-write POST_CTL Post processing control 0x8 32 read-write 0x0 0x0 POST_PROC Post processing [2:0] read-write NONE No postprocessing 0 AVG Averaging 1 AVG_RANGE Averaging followed by Range detect 2 RANGE Range detect 3 RANGE_PULSE Range detect followed by pulse detect 4 RSVD0 N/A 5 RSVD1 N/A 6 RSVD2 N/A 7 LEFT_ALIGN Left or right align data in result[15:0]. 0: the data is right aligned in result[11:0], with sign extension to 16 bits if enabled 1: the data is left aligned in result[15:4] with the lower nibble 0. Caveat if the result was more than 12 bits (e.g. after averaging) then the bits above 12 will be discarded. [6:6] read-write SIGN_EXT Output data is sign extended [7:7] read-write UNSIGNED Default: result data is unsigned (zero extended if needed) 0 SIGNED Result data is signed (sign extended if needed) 1 AVG_CNT Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled. A channel will be sampled (AVG_CNT+1) = [1..256] times. The signal will be acquired back to back (1st order accumulate and dump filter), the average result is calculated and stored and then the next enabled channel is sampled. If more than 16 sample are taken (AVG_CNT>=16) then AVG_SHIFT must be set so that the result after shifting fits in 16 bits Pulse detect positive reload value PULSE_POS_RL[7:0] [15:8] read-write SHIFT_R Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here. Software has to make sure that the result fits in less than 16 bits. Any value >12 will be treated as 12, bit [4] is always ignored. This can also be used to fit the 12-bit result in 8 bits. Pulse detect negative reload value PULSE_NEG_RL[4:0] [20:16] read-write RANGE_MODE Range detect mode [23:22] read-write BELOW_LO Below Low threshold (result < Lo) 0 INSIDE_RANGE Inside range (Lo <= result < Hi) 1 ABOVE_HI Above high threshold (Hi <= result) 2 OUTSIDE_RANGE Outside range (result < Lo || Hi <= result) 3 TR_DONE_GRP_VIO Select tr_sar_ch_done mode for last channel of a group, ignored for all other channels Also see TR_CTL.DONE_LEVEL [25:25] read-write DONE Default: tr_sar_ch_done is set when the group is done 0 GRP_RANGE_VIO tr_sar_ch_done is only set if any of the channels in the group has a Range Violation. This mode is ignored if this is not the last channel in the group. Note that if none of the channels in the group have Range detection enabled then the trigger will never get set. 1 RANGE_CTL Range thresholds 0xC 32 read-write 0x0 0x0 RANGE_LO Range detect low threshold (Lo) [15:0] read-write RANGE_HI Range detect high threshold (Hi) [31:16] read-write INTR Interrupt request register. 0x10 32 read-write 0x0 0x707 GRP_DONE Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done. Write with '1' to clear bit. [0:0] read-write GRP_CANCELLED Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED. Note that it is possible that also the GRP_DONE interrupt is set. If that is the case one or more new triggers were detected while the group was already busy, i.e. triggers are too fast. Write with '1' to clear bit. [1:1] read-write GRP_OVERFLOW Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending. Write with '1' to clear bit. [2:2] read-write CH_RANGE Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. This interrupt is mutual exclusive with Pulse detect interrupt. Write with '1' to clear bit. [8:8] read-write CH_PULSE Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero. This interrupt is mutual exclusive with Range detect interrupt. Write with '1' to clear bit. [9:9] read-write CH_OVERFLOW Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup. Write with '1' to clear bit. [10:10] read-write INTR_SET Interrupt set request register 0x14 32 read-write 0x0 0x707 GRP_DONE_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write GRP_CANCELLED_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write GRP_OVERFLOW_SET Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write CH_RANGE_SET Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write CH_PULSE_SET Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write CH_OVERFLOW_SET Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write INTR_MASK Interrupt mask register. 0x18 32 read-write 0x0 0x707 GRP_DONE_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write GRP_CANCELLED_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write GRP_OVERFLOW_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write CH_RANGE_MASK Mask bit for corresponding bit in interrupt request register. [8:8] read-write CH_PULSE_MASK Mask bit for corresponding bit in interrupt request register. [9:9] read-write CH_OVERFLOW_MASK Mask bit for corresponding bit in interrupt request register. [10:10] read-write INTR_MASKED Interrupt masked request register 0x1C 32 read-only 0x0 0x707 GRP_DONE_MASKED Logical and of corresponding request and mask bits. [0:0] read-only GRP_CANCELLED_MASKED Logical and of corresponding request and mask bits. [1:1] read-only GRP_OVERFLOW_MASKED Logical and of corresponding request and mask bits. [2:2] read-only CH_RANGE_MASKED Logical and of corresponding request and mask bits. [8:8] read-only CH_PULSE_MASKED Logical and of corresponding request and mask bits. [9:9] read-only CH_OVERFLOW_MASKED Logical and of corresponding request and mask bits. [10:10] read-only WORK Working data register 0x20 32 read-only 0x0 0xF0000000 WORK SAR conversion working data of the channel. The data is written here right after sampling this channel. [15:0] read-only ABOVE_HI_MIR mirror bit of the corresponding ABOVE_HI bit [28:28] read-only RANGE_MIR mirror bit of corresponding bit in WORK_RANGE register [29:29] read-only PULSE_MIR mirror bit of corresponding bit in WORK_PULSE register [30:30] read-only VALID_MIR mirror bit of corresponding bit in WORK_VALID register [31:31] read-only RESULT Result data register 0x24 32 read-only 0x0 0xF0000000 RESULT SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. [15:0] read-only ABOVE_HI_MIR mirror bit of the corresponding ABOVE_HI bit [28:28] read-only RANGE_INTR_MIR mirror bit of INTR.CH_RANGE bit [29:29] read-only PULSE_INTR_MIR mirror bit of INTR.CH_PULSE bit [30:30] read-only VALID_MIR mirror bit of the corresponding bit in RESULT_VALID register [31:31] read-only GRP_STAT Group status register 0x28 32 read-only 0x0 0x10707 GRP_COMPLETE Group acquisition complete. This is a copy of the INTR.GRP_DONE bit. [0:0] read-only GRP_CANCELLED Group Cancelled. This is a copy of the INTR.GRP_CANCELLED bit. [1:1] read-only GRP_OVERFLOW Group Overflow. This is a copy of the INTR.GRP_OVERFLOW bit. [2:2] read-only CH_RANGE_COMPLETE Channel Range complete. This is a copy of the INTR.CH_RANGE bit. [8:8] read-only CH_PULSE_COMPLETE Channel Pulse complete. This is a copy of the INTR.CH_PULSE bit. [9:9] read-only CH_OVERFLOW Channel Overflow. This is a copy of the INTR.CH_OVERFLOW bit. [10:10] read-only GRP_BUSY Group acquisition busy. This is a copy of the TR_PENDING bit of the first channel of the group. [16:16] read-only ENABLE Enable register 0x38 32 read-write 0x0 0x1 CHAN_EN Channel enable. - 0: the corresponding channel is disabled. Corresponding trigger will be reset immediately. - 1: the corresponding channel is enabled. Note: To disable a group either stop the trigger first or begin with disabling the lowest channel first. To enable a group either start with enabling the last channel first and the first channel last, or start the trigger after all channels are enabled. If these rules are not followed the result is undefined. [0:0] read-write TR_CMD Software triggers 0x3C 32 read-write 0x0 0x1 START Software start trigger. When written with '1', a start trigger is generated which sets the corresponding TR_PEND bit (only if the channel is enabled). A read always returns a 0. [0:0] read-write EPASS_MMIO PASS top-level MMIO (Generic Triggers) 0x000F0000 PASS_CTL PASS control register 0x0 32 read-write 0x0 0xF0600033 SUPPLY_MON_EN_A Supply monitor enable for AMUXBUS_A (amuxbus_a_mon) [0:0] read-write SUPPLY_MON_LVL_A Supply monitor level select for AMUXBUS_A [1:1] read-write VRL amuxbus_a_mon = VRL 0 VRH amuxbus_a_mon = VRH 1 SUPPLY_MON_EN_B Supply monitor enable for AMUXBUS_B (amuxbus_b_mon) [4:4] read-write SUPPLY_MON_LVL_B Supply monitor level select for AMUXBUS_B [5:5] read-write VRL amuxbus_b_mon = VRL 0 VRH amuxbus_b_mon = VRH 1 REFBUF_MODE Reference mode. The reference needs to be present when using TEMP sensor or diagnostic reference (in addition to SAR.DIAG_CTL.DIAG_EN). Note that setting this mode is not required for the ADC operation itself. [22:21] read-write OFF No reference 0 ON Reference = buffered Vbg from SRSS 1 RSVD undefined 2 BYPASS Reference = unbuffered Vbg from SRSS 3 DBG_FREEZE_EN Debug pause enable, 1 per ADC. When set a high tr_debug_freeze trigger will prevent the scheduler from starting acquisitions on a new channel. Note that averaging for an already started channel will be completed. [31:28] read-write 4 4 SAR_TR_IN_SEL[%s] per SAR generic input trigger select 0x20 32 read-write 0x43210 0xFFFFF IN0_SEL Select generic trigger for SAR generic trigger input 0 [3:0] read-write IN1_SEL Select generic trigger for SAR generic trigger input 1 [7:4] read-write IN2_SEL Select generic trigger for SAR generic trigger input 2 [11:8] read-write IN3_SEL Select generic trigger for SAR generic trigger input 3 [15:12] read-write IN4_SEL Select generic trigger for SAR generic trigger input 4 [19:16] read-write 4 4 SAR_TR_OUT_SEL[%s] per SAR generic output trigger select 0x40 32 read-write 0x100 0x3F3F OUT0_SEL Select SAR output trigger for generic trigger output 0 0-31: selects a tr_sar_ch_done trigger 32-63: selects a tr_sar_ch_rangvio trigger [5:0] read-write OUT1_SEL Select SAR output trigger for generic trigger output 1 [13:8] read-write TEST_CTL Test control bits 0x80 32 read-write 0x0 0x137D TS_CAL_CUR_IN External current input switch control, for Temperature Sensor Calibration [0:0] read-write TS_CAL_VB_OUT Voltage Base switch control, for Temperature Sensor Calibration [2:2] read-write TS_CAL_VE_OUT Voltage Emitter switch control, for Temperature Sensor Calibration [3:3] read-write TS_CAL_DIODE_EN Diode Enable, disconnect or connect the base and collector terminal of the BJT [4:4] read-write TS_CAL_DIODE_PNP_EN Enable signal for PNP transistor. This transistor will be used only during calibration for accurate estimation of chip temp. 0 = Turn PNP off 1 = Configure PNP as a diode (short base and collector) [5:5] read-write TS_CAL_VI_SEL Select current or voltage output on 'v_temp' pin, for Temperature Sensor Calibration [6:6] read-write CURRENT Current is selected 0 VOLTAGE Voltage is selected 1 TS_CAL_CUR_SEL Select the current going into the BJT, for Temperature Sensor Calibration [9:8] read-write I_1U Select 1 uA 0 I_2U Select 2 uA 1 I_5U Select 5 uA 2 I_10U Select 10 uA 3 TS_CAL_SPARE Spare [12:12] read-write