/***************************************************************************//** * \file cyhal_triggers_tviibe1m.c * * \brief * TVIIBE1M family HAL triggers header * ******************************************************************************** * \copyright * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or * an affiliate of Cypress Semiconductor Corporation. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. *******************************************************************************/ #include "cy_device_headers.h" #include "cyhal_hw_types.h" #ifdef CY_DEVICE_TVIIBE1M #include "triggers/cyhal_triggers_tviibe1m.h" const uint16_t cyhal_sources_per_mux[20] = { 55, 61, 5, 86, 94, 123, 80, 7, 11, 223, 134, 8, 64, 64, 64, 9, 9, 3, 3, 16, }; const bool cyhal_is_mux_1to1[20] = { false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux0_sources[55] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, _CYHAL_TRIGGER_CPUSS_TR_FAULT0, _CYHAL_TRIGGER_CPUSS_TR_FAULT1, _CYHAL_TRIGGER_CPUSS_TR_FAULT2, _CYHAL_TRIGGER_CPUSS_TR_FAULT3, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, _CYHAL_TRIGGER_EVTGEN0_TR_OUT3, _CYHAL_TRIGGER_EVTGEN0_TR_OUT4, _CYHAL_TRIGGER_EVTGEN0_TR_OUT5, _CYHAL_TRIGGER_EVTGEN0_TR_OUT6, _CYHAL_TRIGGER_PERI_TR_IO_INPUT0, _CYHAL_TRIGGER_PERI_TR_IO_INPUT1, _CYHAL_TRIGGER_PERI_TR_IO_INPUT2, _CYHAL_TRIGGER_PERI_TR_IO_INPUT3, _CYHAL_TRIGGER_PERI_TR_IO_INPUT4, _CYHAL_TRIGGER_PERI_TR_IO_INPUT5, _CYHAL_TRIGGER_PERI_TR_IO_INPUT6, _CYHAL_TRIGGER_PERI_TR_IO_INPUT7, _CYHAL_TRIGGER_PERI_TR_IO_INPUT8, _CYHAL_TRIGGER_PERI_TR_IO_INPUT9, _CYHAL_TRIGGER_PERI_TR_IO_INPUT10, _CYHAL_TRIGGER_PERI_TR_IO_INPUT11, _CYHAL_TRIGGER_PERI_TR_IO_INPUT12, _CYHAL_TRIGGER_PERI_TR_IO_INPUT13, _CYHAL_TRIGGER_PERI_TR_IO_INPUT14, _CYHAL_TRIGGER_PERI_TR_IO_INPUT15, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux1_sources[61] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, _CYHAL_TRIGGER_CPUSS_TR_FAULT0, _CYHAL_TRIGGER_CPUSS_TR_FAULT1, _CYHAL_TRIGGER_CPUSS_TR_FAULT2, _CYHAL_TRIGGER_CPUSS_TR_FAULT3, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, _CYHAL_TRIGGER_EVTGEN0_TR_OUT7, _CYHAL_TRIGGER_EVTGEN0_TR_OUT8, _CYHAL_TRIGGER_EVTGEN0_TR_OUT9, _CYHAL_TRIGGER_EVTGEN0_TR_OUT10, _CYHAL_TRIGGER_PERI_TR_IO_INPUT16, _CYHAL_TRIGGER_PERI_TR_IO_INPUT17, _CYHAL_TRIGGER_PERI_TR_IO_INPUT18, _CYHAL_TRIGGER_PERI_TR_IO_INPUT19, _CYHAL_TRIGGER_PERI_TR_IO_INPUT20, _CYHAL_TRIGGER_PERI_TR_IO_INPUT21, _CYHAL_TRIGGER_PERI_TR_IO_INPUT22, _CYHAL_TRIGGER_PERI_TR_IO_INPUT23, _CYHAL_TRIGGER_PERI_TR_IO_INPUT24, _CYHAL_TRIGGER_PERI_TR_IO_INPUT25, _CYHAL_TRIGGER_PERI_TR_IO_INPUT26, _CYHAL_TRIGGER_PERI_TR_IO_INPUT27, _CYHAL_TRIGGER_PERI_TR_IO_INPUT28, _CYHAL_TRIGGER_PERI_TR_IO_INPUT29, _CYHAL_TRIGGER_PERI_TR_IO_INPUT30, _CYHAL_TRIGGER_PERI_TR_IO_INPUT31, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux2_sources[5] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux3_sources[86] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_TCPWM0_TR_OUT0512, _CYHAL_TRIGGER_TCPWM0_TR_OUT0513, _CYHAL_TRIGGER_TCPWM0_TR_OUT0514, _CYHAL_TRIGGER_TCPWM0_TR_OUT0515, _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, _CYHAL_TRIGGER_TCPWM0_TR_OUT0263, _CYHAL_TRIGGER_TCPWM0_TR_OUT0264, _CYHAL_TRIGGER_TCPWM0_TR_OUT0265, _CYHAL_TRIGGER_TCPWM0_TR_OUT0266, _CYHAL_TRIGGER_TCPWM0_TR_OUT0267, _CYHAL_TRIGGER_TCPWM0_TR_OUT00, _CYHAL_TRIGGER_TCPWM0_TR_OUT01, _CYHAL_TRIGGER_TCPWM0_TR_OUT02, _CYHAL_TRIGGER_TCPWM0_TR_OUT03, _CYHAL_TRIGGER_TCPWM0_TR_OUT04, _CYHAL_TRIGGER_TCPWM0_TR_OUT05, _CYHAL_TRIGGER_TCPWM0_TR_OUT06, _CYHAL_TRIGGER_TCPWM0_TR_OUT07, _CYHAL_TRIGGER_TCPWM0_TR_OUT08, _CYHAL_TRIGGER_TCPWM0_TR_OUT09, _CYHAL_TRIGGER_TCPWM0_TR_OUT010, _CYHAL_TRIGGER_TCPWM0_TR_OUT011, _CYHAL_TRIGGER_TCPWM0_TR_OUT012, _CYHAL_TRIGGER_TCPWM0_TR_OUT013, _CYHAL_TRIGGER_TCPWM0_TR_OUT014, _CYHAL_TRIGGER_TCPWM0_TR_OUT015, _CYHAL_TRIGGER_TCPWM0_TR_OUT016, _CYHAL_TRIGGER_TCPWM0_TR_OUT017, _CYHAL_TRIGGER_TCPWM0_TR_OUT018, _CYHAL_TRIGGER_TCPWM0_TR_OUT019, _CYHAL_TRIGGER_TCPWM0_TR_OUT020, _CYHAL_TRIGGER_TCPWM0_TR_OUT021, _CYHAL_TRIGGER_TCPWM0_TR_OUT022, _CYHAL_TRIGGER_TCPWM0_TR_OUT023, _CYHAL_TRIGGER_TCPWM0_TR_OUT024, _CYHAL_TRIGGER_TCPWM0_TR_OUT025, _CYHAL_TRIGGER_TCPWM0_TR_OUT026, _CYHAL_TRIGGER_TCPWM0_TR_OUT027, _CYHAL_TRIGGER_TCPWM0_TR_OUT028, _CYHAL_TRIGGER_TCPWM0_TR_OUT029, _CYHAL_TRIGGER_TCPWM0_TR_OUT030, _CYHAL_TRIGGER_TCPWM0_TR_OUT031, _CYHAL_TRIGGER_TCPWM0_TR_OUT032, _CYHAL_TRIGGER_TCPWM0_TR_OUT033, _CYHAL_TRIGGER_TCPWM0_TR_OUT034, _CYHAL_TRIGGER_TCPWM0_TR_OUT035, _CYHAL_TRIGGER_TCPWM0_TR_OUT036, _CYHAL_TRIGGER_TCPWM0_TR_OUT037, _CYHAL_TRIGGER_TCPWM0_TR_OUT038, _CYHAL_TRIGGER_TCPWM0_TR_OUT039, _CYHAL_TRIGGER_TCPWM0_TR_OUT040, _CYHAL_TRIGGER_TCPWM0_TR_OUT041, _CYHAL_TRIGGER_TCPWM0_TR_OUT042, _CYHAL_TRIGGER_TCPWM0_TR_OUT043, _CYHAL_TRIGGER_TCPWM0_TR_OUT044, _CYHAL_TRIGGER_TCPWM0_TR_OUT045, _CYHAL_TRIGGER_TCPWM0_TR_OUT046, _CYHAL_TRIGGER_TCPWM0_TR_OUT047, _CYHAL_TRIGGER_TCPWM0_TR_OUT048, _CYHAL_TRIGGER_TCPWM0_TR_OUT049, _CYHAL_TRIGGER_TCPWM0_TR_OUT050, _CYHAL_TRIGGER_TCPWM0_TR_OUT051, _CYHAL_TRIGGER_TCPWM0_TR_OUT052, _CYHAL_TRIGGER_TCPWM0_TR_OUT053, _CYHAL_TRIGGER_TCPWM0_TR_OUT054, _CYHAL_TRIGGER_TCPWM0_TR_OUT055, _CYHAL_TRIGGER_TCPWM0_TR_OUT056, _CYHAL_TRIGGER_TCPWM0_TR_OUT057, _CYHAL_TRIGGER_TCPWM0_TR_OUT058, _CYHAL_TRIGGER_TCPWM0_TR_OUT059, _CYHAL_TRIGGER_TCPWM0_TR_OUT060, _CYHAL_TRIGGER_TCPWM0_TR_OUT061, _CYHAL_TRIGGER_TCPWM0_TR_OUT062, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux4_sources[94] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_TCPWM0_TR_OUT0512, _CYHAL_TRIGGER_TCPWM0_TR_OUT0513, _CYHAL_TRIGGER_TCPWM0_TR_OUT0514, _CYHAL_TRIGGER_TCPWM0_TR_OUT0515, _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, _CYHAL_TRIGGER_TCPWM0_TR_OUT0263, _CYHAL_TRIGGER_TCPWM0_TR_OUT0264, _CYHAL_TRIGGER_TCPWM0_TR_OUT0265, _CYHAL_TRIGGER_TCPWM0_TR_OUT0266, _CYHAL_TRIGGER_TCPWM0_TR_OUT0267, _CYHAL_TRIGGER_TCPWM0_TR_OUT00, _CYHAL_TRIGGER_TCPWM0_TR_OUT01, _CYHAL_TRIGGER_TCPWM0_TR_OUT02, _CYHAL_TRIGGER_TCPWM0_TR_OUT03, _CYHAL_TRIGGER_TCPWM0_TR_OUT04, _CYHAL_TRIGGER_TCPWM0_TR_OUT05, _CYHAL_TRIGGER_TCPWM0_TR_OUT06, _CYHAL_TRIGGER_TCPWM0_TR_OUT07, _CYHAL_TRIGGER_TCPWM0_TR_OUT08, _CYHAL_TRIGGER_TCPWM0_TR_OUT09, _CYHAL_TRIGGER_TCPWM0_TR_OUT010, _CYHAL_TRIGGER_TCPWM0_TR_OUT011, _CYHAL_TRIGGER_TCPWM0_TR_OUT012, _CYHAL_TRIGGER_TCPWM0_TR_OUT013, _CYHAL_TRIGGER_TCPWM0_TR_OUT014, _CYHAL_TRIGGER_TCPWM0_TR_OUT015, _CYHAL_TRIGGER_TCPWM0_TR_OUT016, _CYHAL_TRIGGER_TCPWM0_TR_OUT017, _CYHAL_TRIGGER_TCPWM0_TR_OUT018, _CYHAL_TRIGGER_TCPWM0_TR_OUT019, _CYHAL_TRIGGER_TCPWM0_TR_OUT020, _CYHAL_TRIGGER_TCPWM0_TR_OUT021, _CYHAL_TRIGGER_TCPWM0_TR_OUT022, _CYHAL_TRIGGER_TCPWM0_TR_OUT023, _CYHAL_TRIGGER_TCPWM0_TR_OUT024, _CYHAL_TRIGGER_TCPWM0_TR_OUT025, _CYHAL_TRIGGER_TCPWM0_TR_OUT026, _CYHAL_TRIGGER_TCPWM0_TR_OUT027, _CYHAL_TRIGGER_TCPWM0_TR_OUT028, _CYHAL_TRIGGER_TCPWM0_TR_OUT029, _CYHAL_TRIGGER_TCPWM0_TR_OUT030, _CYHAL_TRIGGER_TCPWM0_TR_OUT031, _CYHAL_TRIGGER_TCPWM0_TR_OUT032, _CYHAL_TRIGGER_TCPWM0_TR_OUT033, _CYHAL_TRIGGER_TCPWM0_TR_OUT034, _CYHAL_TRIGGER_TCPWM0_TR_OUT035, _CYHAL_TRIGGER_TCPWM0_TR_OUT036, _CYHAL_TRIGGER_TCPWM0_TR_OUT037, _CYHAL_TRIGGER_TCPWM0_TR_OUT038, _CYHAL_TRIGGER_TCPWM0_TR_OUT039, _CYHAL_TRIGGER_TCPWM0_TR_OUT040, _CYHAL_TRIGGER_TCPWM0_TR_OUT041, _CYHAL_TRIGGER_TCPWM0_TR_OUT042, _CYHAL_TRIGGER_TCPWM0_TR_OUT043, _CYHAL_TRIGGER_TCPWM0_TR_OUT044, _CYHAL_TRIGGER_TCPWM0_TR_OUT045, _CYHAL_TRIGGER_TCPWM0_TR_OUT046, _CYHAL_TRIGGER_TCPWM0_TR_OUT047, _CYHAL_TRIGGER_TCPWM0_TR_OUT048, _CYHAL_TRIGGER_TCPWM0_TR_OUT049, _CYHAL_TRIGGER_TCPWM0_TR_OUT050, _CYHAL_TRIGGER_TCPWM0_TR_OUT051, _CYHAL_TRIGGER_TCPWM0_TR_OUT052, _CYHAL_TRIGGER_TCPWM0_TR_OUT053, _CYHAL_TRIGGER_TCPWM0_TR_OUT054, _CYHAL_TRIGGER_TCPWM0_TR_OUT055, _CYHAL_TRIGGER_TCPWM0_TR_OUT056, _CYHAL_TRIGGER_TCPWM0_TR_OUT057, _CYHAL_TRIGGER_TCPWM0_TR_OUT058, _CYHAL_TRIGGER_TCPWM0_TR_OUT059, _CYHAL_TRIGGER_TCPWM0_TR_OUT060, _CYHAL_TRIGGER_TCPWM0_TR_OUT061, _CYHAL_TRIGGER_TCPWM0_TR_OUT062, _CYHAL_TRIGGER_TCPWM0_TR_OUT10, _CYHAL_TRIGGER_TCPWM0_TR_OUT11, _CYHAL_TRIGGER_TCPWM0_TR_OUT12, _CYHAL_TRIGGER_TCPWM0_TR_OUT13, _CYHAL_TRIGGER_TCPWM0_TR_OUT14, _CYHAL_TRIGGER_TCPWM0_TR_OUT15, _CYHAL_TRIGGER_TCPWM0_TR_OUT16, _CYHAL_TRIGGER_TCPWM0_TR_OUT17, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux5_sources[123] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, _CYHAL_TRIGGER_CPUSS_TR_FAULT0, _CYHAL_TRIGGER_CPUSS_TR_FAULT1, _CYHAL_TRIGGER_CPUSS_TR_FAULT2, _CYHAL_TRIGGER_CPUSS_TR_FAULT3, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, _CYHAL_TRIGGER_PERI_TR_IO_INPUT0, _CYHAL_TRIGGER_PERI_TR_IO_INPUT1, _CYHAL_TRIGGER_PERI_TR_IO_INPUT2, _CYHAL_TRIGGER_PERI_TR_IO_INPUT3, _CYHAL_TRIGGER_PERI_TR_IO_INPUT4, _CYHAL_TRIGGER_PERI_TR_IO_INPUT5, _CYHAL_TRIGGER_PERI_TR_IO_INPUT6, _CYHAL_TRIGGER_PERI_TR_IO_INPUT7, _CYHAL_TRIGGER_PERI_TR_IO_INPUT8, _CYHAL_TRIGGER_PERI_TR_IO_INPUT9, _CYHAL_TRIGGER_PERI_TR_IO_INPUT10, _CYHAL_TRIGGER_PERI_TR_IO_INPUT11, _CYHAL_TRIGGER_PERI_TR_IO_INPUT12, _CYHAL_TRIGGER_PERI_TR_IO_INPUT13, _CYHAL_TRIGGER_PERI_TR_IO_INPUT14, _CYHAL_TRIGGER_PERI_TR_IO_INPUT15, _CYHAL_TRIGGER_PERI_TR_IO_INPUT16, _CYHAL_TRIGGER_PERI_TR_IO_INPUT17, _CYHAL_TRIGGER_PERI_TR_IO_INPUT18, _CYHAL_TRIGGER_PERI_TR_IO_INPUT19, _CYHAL_TRIGGER_PERI_TR_IO_INPUT20, _CYHAL_TRIGGER_PERI_TR_IO_INPUT21, _CYHAL_TRIGGER_PERI_TR_IO_INPUT22, _CYHAL_TRIGGER_PERI_TR_IO_INPUT23, _CYHAL_TRIGGER_PERI_TR_IO_INPUT24, _CYHAL_TRIGGER_PERI_TR_IO_INPUT25, _CYHAL_TRIGGER_PERI_TR_IO_INPUT26, _CYHAL_TRIGGER_PERI_TR_IO_INPUT27, _CYHAL_TRIGGER_PERI_TR_IO_INPUT28, _CYHAL_TRIGGER_PERI_TR_IO_INPUT29, _CYHAL_TRIGGER_PERI_TR_IO_INPUT30, _CYHAL_TRIGGER_PERI_TR_IO_INPUT31, _CYHAL_TRIGGER_SCB0_TR_TX_REQ, _CYHAL_TRIGGER_SCB0_TR_RX_REQ, _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB1_TR_TX_REQ, _CYHAL_TRIGGER_SCB1_TR_RX_REQ, _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB2_TR_TX_REQ, _CYHAL_TRIGGER_SCB2_TR_RX_REQ, _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB3_TR_TX_REQ, _CYHAL_TRIGGER_SCB3_TR_RX_REQ, _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB4_TR_TX_REQ, _CYHAL_TRIGGER_SCB4_TR_RX_REQ, _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB5_TR_TX_REQ, _CYHAL_TRIGGER_SCB5_TR_RX_REQ, _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB6_TR_TX_REQ, _CYHAL_TRIGGER_SCB6_TR_RX_REQ, _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB7_TR_TX_REQ, _CYHAL_TRIGGER_SCB7_TR_RX_REQ, _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1, _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2, _CYHAL_TRIGGER_CANFD0_TR_FIFO00, _CYHAL_TRIGGER_CANFD0_TR_FIFO01, _CYHAL_TRIGGER_CANFD0_TR_FIFO02, _CYHAL_TRIGGER_CANFD0_TR_FIFO10, _CYHAL_TRIGGER_CANFD0_TR_FIFO11, _CYHAL_TRIGGER_CANFD0_TR_FIFO12, _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0, _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1, _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2, _CYHAL_TRIGGER_CANFD1_TR_FIFO00, _CYHAL_TRIGGER_CANFD1_TR_FIFO01, _CYHAL_TRIGGER_CANFD1_TR_FIFO02, _CYHAL_TRIGGER_CANFD1_TR_FIFO10, _CYHAL_TRIGGER_CANFD1_TR_FIFO11, _CYHAL_TRIGGER_CANFD1_TR_FIFO12, _CYHAL_TRIGGER_EVTGEN0_TR_OUT3, _CYHAL_TRIGGER_EVTGEN0_TR_OUT4, _CYHAL_TRIGGER_EVTGEN0_TR_OUT5, _CYHAL_TRIGGER_EVTGEN0_TR_OUT6, _CYHAL_TRIGGER_EVTGEN0_TR_OUT7, _CYHAL_TRIGGER_EVTGEN0_TR_OUT8, _CYHAL_TRIGGER_EVTGEN0_TR_OUT9, _CYHAL_TRIGGER_EVTGEN0_TR_OUT10, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux6_sources[80] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, _CYHAL_TRIGGER_CPUSS_TR_FAULT0, _CYHAL_TRIGGER_CPUSS_TR_FAULT1, _CYHAL_TRIGGER_CPUSS_TR_FAULT2, _CYHAL_TRIGGER_CPUSS_TR_FAULT3, _CYHAL_TRIGGER_EVTGEN0_TR_OUT0, _CYHAL_TRIGGER_EVTGEN0_TR_OUT1, _CYHAL_TRIGGER_EVTGEN0_TR_OUT2, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, _CYHAL_TRIGGER_PERI_TR_IO_INPUT0, _CYHAL_TRIGGER_PERI_TR_IO_INPUT1, _CYHAL_TRIGGER_PERI_TR_IO_INPUT2, _CYHAL_TRIGGER_PERI_TR_IO_INPUT3, _CYHAL_TRIGGER_PERI_TR_IO_INPUT4, _CYHAL_TRIGGER_PERI_TR_IO_INPUT5, _CYHAL_TRIGGER_PERI_TR_IO_INPUT6, _CYHAL_TRIGGER_PERI_TR_IO_INPUT7, _CYHAL_TRIGGER_PERI_TR_IO_INPUT8, _CYHAL_TRIGGER_PERI_TR_IO_INPUT9, _CYHAL_TRIGGER_PERI_TR_IO_INPUT10, _CYHAL_TRIGGER_PERI_TR_IO_INPUT11, _CYHAL_TRIGGER_PERI_TR_IO_INPUT12, _CYHAL_TRIGGER_PERI_TR_IO_INPUT13, _CYHAL_TRIGGER_PERI_TR_IO_INPUT14, _CYHAL_TRIGGER_PERI_TR_IO_INPUT15, _CYHAL_TRIGGER_PERI_TR_IO_INPUT16, _CYHAL_TRIGGER_PERI_TR_IO_INPUT17, _CYHAL_TRIGGER_PERI_TR_IO_INPUT18, _CYHAL_TRIGGER_PERI_TR_IO_INPUT19, _CYHAL_TRIGGER_PERI_TR_IO_INPUT20, _CYHAL_TRIGGER_PERI_TR_IO_INPUT21, _CYHAL_TRIGGER_PERI_TR_IO_INPUT22, _CYHAL_TRIGGER_PERI_TR_IO_INPUT23, _CYHAL_TRIGGER_PERI_TR_IO_INPUT24, _CYHAL_TRIGGER_PERI_TR_IO_INPUT25, _CYHAL_TRIGGER_PERI_TR_IO_INPUT26, _CYHAL_TRIGGER_PERI_TR_IO_INPUT27, _CYHAL_TRIGGER_PERI_TR_IO_INPUT28, _CYHAL_TRIGGER_PERI_TR_IO_INPUT29, _CYHAL_TRIGGER_PERI_TR_IO_INPUT30, _CYHAL_TRIGGER_PERI_TR_IO_INPUT31, _CYHAL_TRIGGER_TCPWM0_TR_OUT1512, _CYHAL_TRIGGER_TCPWM0_TR_OUT1513, _CYHAL_TRIGGER_TCPWM0_TR_OUT1514, _CYHAL_TRIGGER_TCPWM0_TR_OUT1515, _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, _CYHAL_TRIGGER_TCPWM0_TR_OUT1263, _CYHAL_TRIGGER_TCPWM0_TR_OUT1264, _CYHAL_TRIGGER_TCPWM0_TR_OUT1265, _CYHAL_TRIGGER_TCPWM0_TR_OUT1266, _CYHAL_TRIGGER_TCPWM0_TR_OUT1267, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux7_sources[7] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux8_sources[11] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_TR_GROUP9_OUTPUT0, _CYHAL_TRIGGER_TR_GROUP9_OUTPUT1, _CYHAL_TRIGGER_TR_GROUP9_OUTPUT2, _CYHAL_TRIGGER_TR_GROUP9_OUTPUT3, _CYHAL_TRIGGER_TR_GROUP9_OUTPUT4, _CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, _CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, _CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, _CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, _CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux9_sources[223] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88, _CYHAL_TRIGGER_SCB0_TR_TX_REQ, _CYHAL_TRIGGER_SCB1_TR_TX_REQ, _CYHAL_TRIGGER_SCB2_TR_TX_REQ, _CYHAL_TRIGGER_SCB3_TR_TX_REQ, _CYHAL_TRIGGER_SCB4_TR_TX_REQ, _CYHAL_TRIGGER_SCB5_TR_TX_REQ, _CYHAL_TRIGGER_SCB6_TR_TX_REQ, _CYHAL_TRIGGER_SCB7_TR_TX_REQ, _CYHAL_TRIGGER_SCB0_TR_RX_REQ, _CYHAL_TRIGGER_SCB1_TR_RX_REQ, _CYHAL_TRIGGER_SCB2_TR_RX_REQ, _CYHAL_TRIGGER_SCB3_TR_RX_REQ, _CYHAL_TRIGGER_SCB4_TR_RX_REQ, _CYHAL_TRIGGER_SCB5_TR_RX_REQ, _CYHAL_TRIGGER_SCB6_TR_RX_REQ, _CYHAL_TRIGGER_SCB7_TR_RX_REQ, _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1, _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2, _CYHAL_TRIGGER_CANFD0_TR_FIFO00, _CYHAL_TRIGGER_CANFD0_TR_FIFO01, _CYHAL_TRIGGER_CANFD0_TR_FIFO02, _CYHAL_TRIGGER_CANFD0_TR_FIFO10, _CYHAL_TRIGGER_CANFD0_TR_FIFO11, _CYHAL_TRIGGER_CANFD0_TR_FIFO12, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2, _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0, _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1, _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2, _CYHAL_TRIGGER_CANFD1_TR_FIFO00, _CYHAL_TRIGGER_CANFD1_TR_FIFO01, _CYHAL_TRIGGER_CANFD1_TR_FIFO02, _CYHAL_TRIGGER_CANFD1_TR_FIFO10, _CYHAL_TRIGGER_CANFD1_TR_FIFO11, _CYHAL_TRIGGER_CANFD1_TR_FIFO12, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1, _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, _CYHAL_TRIGGER_CPUSS_TR_FAULT0, _CYHAL_TRIGGER_CPUSS_TR_FAULT1, _CYHAL_TRIGGER_CPUSS_TR_FAULT2, _CYHAL_TRIGGER_CPUSS_TR_FAULT3, _CYHAL_TRIGGER_TCPWM0_TR_OUT0512, _CYHAL_TRIGGER_TCPWM0_TR_OUT0513, _CYHAL_TRIGGER_TCPWM0_TR_OUT0514, _CYHAL_TRIGGER_TCPWM0_TR_OUT0515, _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, _CYHAL_TRIGGER_TCPWM0_TR_OUT0263, _CYHAL_TRIGGER_TCPWM0_TR_OUT0264, _CYHAL_TRIGGER_TCPWM0_TR_OUT0265, _CYHAL_TRIGGER_TCPWM0_TR_OUT0266, _CYHAL_TRIGGER_TCPWM0_TR_OUT0267, _CYHAL_TRIGGER_TCPWM0_TR_OUT00, _CYHAL_TRIGGER_TCPWM0_TR_OUT01, _CYHAL_TRIGGER_TCPWM0_TR_OUT02, _CYHAL_TRIGGER_TCPWM0_TR_OUT03, _CYHAL_TRIGGER_TCPWM0_TR_OUT04, _CYHAL_TRIGGER_TCPWM0_TR_OUT05, _CYHAL_TRIGGER_TCPWM0_TR_OUT06, _CYHAL_TRIGGER_TCPWM0_TR_OUT07, _CYHAL_TRIGGER_TCPWM0_TR_OUT08, _CYHAL_TRIGGER_TCPWM0_TR_OUT09, _CYHAL_TRIGGER_TCPWM0_TR_OUT010, _CYHAL_TRIGGER_TCPWM0_TR_OUT011, _CYHAL_TRIGGER_TCPWM0_TR_OUT012, _CYHAL_TRIGGER_TCPWM0_TR_OUT013, _CYHAL_TRIGGER_TCPWM0_TR_OUT014, _CYHAL_TRIGGER_TCPWM0_TR_OUT015, _CYHAL_TRIGGER_TCPWM0_TR_OUT016, _CYHAL_TRIGGER_TCPWM0_TR_OUT017, _CYHAL_TRIGGER_TCPWM0_TR_OUT018, _CYHAL_TRIGGER_TCPWM0_TR_OUT019, _CYHAL_TRIGGER_TCPWM0_TR_OUT020, _CYHAL_TRIGGER_TCPWM0_TR_OUT021, _CYHAL_TRIGGER_TCPWM0_TR_OUT022, _CYHAL_TRIGGER_TCPWM0_TR_OUT023, _CYHAL_TRIGGER_TCPWM0_TR_OUT024, _CYHAL_TRIGGER_TCPWM0_TR_OUT025, _CYHAL_TRIGGER_TCPWM0_TR_OUT026, _CYHAL_TRIGGER_TCPWM0_TR_OUT027, _CYHAL_TRIGGER_TCPWM0_TR_OUT028, _CYHAL_TRIGGER_TCPWM0_TR_OUT029, _CYHAL_TRIGGER_TCPWM0_TR_OUT030, _CYHAL_TRIGGER_TCPWM0_TR_OUT031, _CYHAL_TRIGGER_TCPWM0_TR_OUT032, _CYHAL_TRIGGER_TCPWM0_TR_OUT033, _CYHAL_TRIGGER_TCPWM0_TR_OUT034, _CYHAL_TRIGGER_TCPWM0_TR_OUT035, _CYHAL_TRIGGER_TCPWM0_TR_OUT036, _CYHAL_TRIGGER_TCPWM0_TR_OUT037, _CYHAL_TRIGGER_TCPWM0_TR_OUT038, _CYHAL_TRIGGER_TCPWM0_TR_OUT039, _CYHAL_TRIGGER_TCPWM0_TR_OUT040, _CYHAL_TRIGGER_TCPWM0_TR_OUT041, _CYHAL_TRIGGER_TCPWM0_TR_OUT042, _CYHAL_TRIGGER_TCPWM0_TR_OUT043, _CYHAL_TRIGGER_TCPWM0_TR_OUT044, _CYHAL_TRIGGER_TCPWM0_TR_OUT045, _CYHAL_TRIGGER_TCPWM0_TR_OUT046, _CYHAL_TRIGGER_TCPWM0_TR_OUT047, _CYHAL_TRIGGER_TCPWM0_TR_OUT048, _CYHAL_TRIGGER_TCPWM0_TR_OUT049, _CYHAL_TRIGGER_TCPWM0_TR_OUT050, _CYHAL_TRIGGER_TCPWM0_TR_OUT051, _CYHAL_TRIGGER_TCPWM0_TR_OUT052, _CYHAL_TRIGGER_TCPWM0_TR_OUT053, _CYHAL_TRIGGER_TCPWM0_TR_OUT054, _CYHAL_TRIGGER_TCPWM0_TR_OUT055, _CYHAL_TRIGGER_TCPWM0_TR_OUT056, _CYHAL_TRIGGER_TCPWM0_TR_OUT057, _CYHAL_TRIGGER_TCPWM0_TR_OUT058, _CYHAL_TRIGGER_TCPWM0_TR_OUT059, _CYHAL_TRIGGER_TCPWM0_TR_OUT060, _CYHAL_TRIGGER_TCPWM0_TR_OUT061, _CYHAL_TRIGGER_TCPWM0_TR_OUT062, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux10_sources[134] = { _CYHAL_TRIGGER_CPUSS_ZERO, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, _CYHAL_TRIGGER_TCPWM0_TR_OUT1512, _CYHAL_TRIGGER_TCPWM0_TR_OUT1513, _CYHAL_TRIGGER_TCPWM0_TR_OUT1514, _CYHAL_TRIGGER_TCPWM0_TR_OUT1515, _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, _CYHAL_TRIGGER_TCPWM0_TR_OUT1263, _CYHAL_TRIGGER_TCPWM0_TR_OUT1264, _CYHAL_TRIGGER_TCPWM0_TR_OUT1265, _CYHAL_TRIGGER_TCPWM0_TR_OUT1266, _CYHAL_TRIGGER_TCPWM0_TR_OUT1267, _CYHAL_TRIGGER_TCPWM0_TR_OUT10, _CYHAL_TRIGGER_TCPWM0_TR_OUT11, _CYHAL_TRIGGER_TCPWM0_TR_OUT12, _CYHAL_TRIGGER_TCPWM0_TR_OUT13, _CYHAL_TRIGGER_TCPWM0_TR_OUT14, _CYHAL_TRIGGER_TCPWM0_TR_OUT15, _CYHAL_TRIGGER_TCPWM0_TR_OUT16, _CYHAL_TRIGGER_TCPWM0_TR_OUT17, _CYHAL_TRIGGER_TCPWM0_TR_OUT18, _CYHAL_TRIGGER_TCPWM0_TR_OUT19, _CYHAL_TRIGGER_TCPWM0_TR_OUT110, _CYHAL_TRIGGER_TCPWM0_TR_OUT111, _CYHAL_TRIGGER_TCPWM0_TR_OUT112, _CYHAL_TRIGGER_TCPWM0_TR_OUT113, _CYHAL_TRIGGER_TCPWM0_TR_OUT114, _CYHAL_TRIGGER_TCPWM0_TR_OUT115, _CYHAL_TRIGGER_TCPWM0_TR_OUT116, _CYHAL_TRIGGER_TCPWM0_TR_OUT117, _CYHAL_TRIGGER_TCPWM0_TR_OUT118, _CYHAL_TRIGGER_TCPWM0_TR_OUT119, _CYHAL_TRIGGER_TCPWM0_TR_OUT120, _CYHAL_TRIGGER_TCPWM0_TR_OUT121, _CYHAL_TRIGGER_TCPWM0_TR_OUT122, _CYHAL_TRIGGER_TCPWM0_TR_OUT123, _CYHAL_TRIGGER_TCPWM0_TR_OUT124, _CYHAL_TRIGGER_TCPWM0_TR_OUT125, _CYHAL_TRIGGER_TCPWM0_TR_OUT126, _CYHAL_TRIGGER_TCPWM0_TR_OUT127, _CYHAL_TRIGGER_TCPWM0_TR_OUT128, _CYHAL_TRIGGER_TCPWM0_TR_OUT129, _CYHAL_TRIGGER_TCPWM0_TR_OUT130, _CYHAL_TRIGGER_TCPWM0_TR_OUT131, _CYHAL_TRIGGER_TCPWM0_TR_OUT132, _CYHAL_TRIGGER_TCPWM0_TR_OUT133, _CYHAL_TRIGGER_TCPWM0_TR_OUT134, _CYHAL_TRIGGER_TCPWM0_TR_OUT135, _CYHAL_TRIGGER_TCPWM0_TR_OUT136, _CYHAL_TRIGGER_TCPWM0_TR_OUT137, _CYHAL_TRIGGER_TCPWM0_TR_OUT138, _CYHAL_TRIGGER_TCPWM0_TR_OUT139, _CYHAL_TRIGGER_TCPWM0_TR_OUT140, _CYHAL_TRIGGER_TCPWM0_TR_OUT141, _CYHAL_TRIGGER_TCPWM0_TR_OUT142, _CYHAL_TRIGGER_TCPWM0_TR_OUT143, _CYHAL_TRIGGER_TCPWM0_TR_OUT144, _CYHAL_TRIGGER_TCPWM0_TR_OUT145, _CYHAL_TRIGGER_TCPWM0_TR_OUT146, _CYHAL_TRIGGER_TCPWM0_TR_OUT147, _CYHAL_TRIGGER_TCPWM0_TR_OUT148, _CYHAL_TRIGGER_TCPWM0_TR_OUT149, _CYHAL_TRIGGER_TCPWM0_TR_OUT150, _CYHAL_TRIGGER_TCPWM0_TR_OUT151, _CYHAL_TRIGGER_TCPWM0_TR_OUT152, _CYHAL_TRIGGER_TCPWM0_TR_OUT153, _CYHAL_TRIGGER_TCPWM0_TR_OUT154, _CYHAL_TRIGGER_TCPWM0_TR_OUT155, _CYHAL_TRIGGER_TCPWM0_TR_OUT156, _CYHAL_TRIGGER_TCPWM0_TR_OUT157, _CYHAL_TRIGGER_TCPWM0_TR_OUT158, _CYHAL_TRIGGER_TCPWM0_TR_OUT159, _CYHAL_TRIGGER_TCPWM0_TR_OUT160, _CYHAL_TRIGGER_TCPWM0_TR_OUT161, _CYHAL_TRIGGER_TCPWM0_TR_OUT162, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, _CYHAL_TRIGGER_EVTGEN0_TR_OUT0, _CYHAL_TRIGGER_EVTGEN0_TR_OUT1, _CYHAL_TRIGGER_EVTGEN0_TR_OUT2, _CYHAL_TRIGGER_EVTGEN0_TR_OUT3, _CYHAL_TRIGGER_EVTGEN0_TR_OUT4, _CYHAL_TRIGGER_EVTGEN0_TR_OUT5, _CYHAL_TRIGGER_EVTGEN0_TR_OUT6, _CYHAL_TRIGGER_EVTGEN0_TR_OUT7, _CYHAL_TRIGGER_EVTGEN0_TR_OUT8, _CYHAL_TRIGGER_EVTGEN0_TR_OUT9, _CYHAL_TRIGGER_EVTGEN0_TR_OUT10, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux11_sources[8] = { _CYHAL_TRIGGER_TCPWM0_TR_OUT00, _CYHAL_TRIGGER_TCPWM0_TR_OUT01, _CYHAL_TRIGGER_TCPWM0_TR_OUT02, _CYHAL_TRIGGER_TCPWM0_TR_OUT03, _CYHAL_TRIGGER_TCPWM0_TR_OUT04, _CYHAL_TRIGGER_TCPWM0_TR_OUT05, _CYHAL_TRIGGER_TCPWM0_TR_OUT06, _CYHAL_TRIGGER_TCPWM0_TR_OUT07, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux12_sources[64] = { _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, _CYHAL_TRIGGER_TCPWM0_TR_OUT1265, _CYHAL_TRIGGER_TCPWM0_TR_OUT10, _CYHAL_TRIGGER_TCPWM0_TR_OUT11, _CYHAL_TRIGGER_TCPWM0_TR_OUT12, _CYHAL_TRIGGER_TCPWM0_TR_OUT13, _CYHAL_TRIGGER_TCPWM0_TR_OUT14, _CYHAL_TRIGGER_TCPWM0_TR_OUT15, _CYHAL_TRIGGER_TCPWM0_TR_OUT16, _CYHAL_TRIGGER_TCPWM0_TR_OUT17, _CYHAL_TRIGGER_TCPWM0_TR_OUT18, _CYHAL_TRIGGER_TCPWM0_TR_OUT19, _CYHAL_TRIGGER_TCPWM0_TR_OUT110, _CYHAL_TRIGGER_TCPWM0_TR_OUT111, _CYHAL_TRIGGER_TCPWM0_TR_OUT112, _CYHAL_TRIGGER_TCPWM0_TR_OUT113, _CYHAL_TRIGGER_TCPWM0_TR_OUT114, _CYHAL_TRIGGER_TCPWM0_TR_OUT115, _CYHAL_TRIGGER_TCPWM0_TR_OUT116, _CYHAL_TRIGGER_TCPWM0_TR_OUT117, _CYHAL_TRIGGER_TCPWM0_TR_OUT118, _CYHAL_TRIGGER_TCPWM0_TR_OUT119, _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, _CYHAL_TRIGGER_TCPWM0_TR_OUT1263, _CYHAL_TRIGGER_TCPWM0_TR_OUT1266, _CYHAL_TRIGGER_TCPWM0_TR_OUT120, _CYHAL_TRIGGER_TCPWM0_TR_OUT121, _CYHAL_TRIGGER_TCPWM0_TR_OUT122, _CYHAL_TRIGGER_TCPWM0_TR_OUT123, _CYHAL_TRIGGER_TCPWM0_TR_OUT124, _CYHAL_TRIGGER_TCPWM0_TR_OUT125, _CYHAL_TRIGGER_TCPWM0_TR_OUT126, _CYHAL_TRIGGER_TCPWM0_TR_OUT127, _CYHAL_TRIGGER_TCPWM0_TR_OUT128, _CYHAL_TRIGGER_TCPWM0_TR_OUT129, _CYHAL_TRIGGER_TCPWM0_TR_OUT130, _CYHAL_TRIGGER_TCPWM0_TR_OUT131, _CYHAL_TRIGGER_TCPWM0_TR_OUT132, _CYHAL_TRIGGER_TCPWM0_TR_OUT133, _CYHAL_TRIGGER_TCPWM0_TR_OUT134, _CYHAL_TRIGGER_TCPWM0_TR_OUT135, _CYHAL_TRIGGER_TCPWM0_TR_OUT136, _CYHAL_TRIGGER_TCPWM0_TR_OUT137, _CYHAL_TRIGGER_TCPWM0_TR_OUT138, _CYHAL_TRIGGER_TCPWM0_TR_OUT139, _CYHAL_TRIGGER_TCPWM0_TR_OUT140, _CYHAL_TRIGGER_TCPWM0_TR_OUT141, _CYHAL_TRIGGER_TCPWM0_TR_OUT142, _CYHAL_TRIGGER_TCPWM0_TR_OUT143, _CYHAL_TRIGGER_TCPWM0_TR_OUT144, _CYHAL_TRIGGER_TCPWM0_TR_OUT145, _CYHAL_TRIGGER_TCPWM0_TR_OUT146, _CYHAL_TRIGGER_TCPWM0_TR_OUT147, _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, _CYHAL_TRIGGER_TCPWM0_TR_OUT1264, _CYHAL_TRIGGER_TCPWM0_TR_OUT1267, _CYHAL_TRIGGER_TCPWM0_TR_OUT148, _CYHAL_TRIGGER_TCPWM0_TR_OUT149, _CYHAL_TRIGGER_TCPWM0_TR_OUT150, _CYHAL_TRIGGER_TCPWM0_TR_OUT151, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux13_sources[64] = { _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux14_sources[64] = { _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70, _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux15_sources[9] = { _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, _CYHAL_TRIGGER_CANFD0_TR_FIFO00, _CYHAL_TRIGGER_CANFD0_TR_FIFO10, _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1, _CYHAL_TRIGGER_CANFD0_TR_FIFO01, _CYHAL_TRIGGER_CANFD0_TR_FIFO11, _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2, _CYHAL_TRIGGER_CANFD0_TR_FIFO02, _CYHAL_TRIGGER_CANFD0_TR_FIFO12, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux16_sources[9] = { _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0, _CYHAL_TRIGGER_CANFD1_TR_FIFO00, _CYHAL_TRIGGER_CANFD1_TR_FIFO10, _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1, _CYHAL_TRIGGER_CANFD1_TR_FIFO01, _CYHAL_TRIGGER_CANFD1_TR_FIFO11, _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2, _CYHAL_TRIGGER_CANFD1_TR_FIFO02, _CYHAL_TRIGGER_CANFD1_TR_FIFO12, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux17_sources[3] = { _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19, _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux18_sources[3] = { _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27, _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30, }; const _cyhal_trigger_source_tviibe1m_t cyhal_mux19_sources[16] = { _CYHAL_TRIGGER_SCB0_TR_TX_REQ, _CYHAL_TRIGGER_SCB0_TR_RX_REQ, _CYHAL_TRIGGER_SCB1_TR_TX_REQ, _CYHAL_TRIGGER_SCB1_TR_RX_REQ, _CYHAL_TRIGGER_SCB2_TR_TX_REQ, _CYHAL_TRIGGER_SCB2_TR_RX_REQ, _CYHAL_TRIGGER_SCB3_TR_TX_REQ, _CYHAL_TRIGGER_SCB3_TR_RX_REQ, _CYHAL_TRIGGER_SCB4_TR_TX_REQ, _CYHAL_TRIGGER_SCB4_TR_RX_REQ, _CYHAL_TRIGGER_SCB5_TR_TX_REQ, _CYHAL_TRIGGER_SCB5_TR_RX_REQ, _CYHAL_TRIGGER_SCB6_TR_TX_REQ, _CYHAL_TRIGGER_SCB6_TR_RX_REQ, _CYHAL_TRIGGER_SCB7_TR_TX_REQ, _CYHAL_TRIGGER_SCB7_TR_RX_REQ, }; const _cyhal_trigger_source_tviibe1m_t* cyhal_mux_to_sources[20] = { cyhal_mux0_sources, cyhal_mux1_sources, cyhal_mux2_sources, cyhal_mux3_sources, cyhal_mux4_sources, cyhal_mux5_sources, cyhal_mux6_sources, cyhal_mux7_sources, cyhal_mux8_sources, cyhal_mux9_sources, cyhal_mux10_sources, cyhal_mux11_sources, cyhal_mux12_sources, cyhal_mux13_sources, cyhal_mux14_sources, cyhal_mux15_sources, cyhal_mux16_sources, cyhal_mux17_sources, cyhal_mux18_sources, cyhal_mux19_sources, }; const uint8_t cyhal_dest_to_mux[333] = { 134, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ 134, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK1 */ 134, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK2 */ 135, /* CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK0 */ 135, /* CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK1 */ 135, /* CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK2 */ 7, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ 7, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN1 */ 7, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN2 */ 7, /* CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN0 */ 7, /* CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN1 */ 7, /* CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN2 */ 8, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 */ 8, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 */ 2, /* CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 */ 2, /* CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 */ 2, /* CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 */ 2, /* CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 */ 132, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN29 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN30 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN31 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN32 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN33 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN34 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN35 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN36 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN37 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN38 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN39 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN40 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN41 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN42 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN43 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN44 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN45 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN46 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN47 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN48 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN49 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN50 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN51 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN52 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN53 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN54 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN55 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN56 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN57 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN58 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN59 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN60 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN61 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN62 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN63 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN64 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN65 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN66 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN67 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN68 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN69 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN70 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN71 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN72 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN73 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN74 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN75 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN76 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN77 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN78 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN79 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN80 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN81 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN82 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN83 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN84 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN85 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN86 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN87 */ 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN88 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 */ 136, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 */ 133, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN32 */ 128, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 */ 128, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 */ 128, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER2 */ 128, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER3 */ 128, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER4 */ 128, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER5 */ 128, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER6 */ 128, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER7 */ 8, /* CYHAL_TRIGGER_PASS0_TR_DEBUG_FREEZE */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN0 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN1 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN2 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN3 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN4 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN5 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN6 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN7 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN8 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN9 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN10 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN11 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN12 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN13 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN14 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN15 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN16 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN17 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN18 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN19 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN20 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN21 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN22 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN23 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN32 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN33 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN34 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN35 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN36 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN37 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN38 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN39 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN40 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN41 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN42 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN43 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN44 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN45 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN46 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN47 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN48 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN49 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN50 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN51 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN52 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN53 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN54 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN55 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN56 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN57 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN58 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN59 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN60 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN61 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN62 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN63 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN64 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN65 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN66 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN67 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN68 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN69 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN70 */ 129, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN71 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN0 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN1 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN2 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN3 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN4 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN5 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN6 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN7 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN8 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN9 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN10 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN11 */ 8, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */ 8, /* CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 */ 8, /* CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 */ 8, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */ 8, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 */ 8, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */ 8, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN2 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN5 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN8 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN11 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN14 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN17 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN20 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN23 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN26 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN29 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN32 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN35 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN38 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN41 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN44 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN47 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN50 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN53 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN56 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN59 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN62 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN65 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN68 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN71 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN74 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN77 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN80 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN83 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN86 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN89 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN92 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN95 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN98 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN101 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN104 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN107 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN110 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN113 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN116 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN119 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN122 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN125 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN128 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN131 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN134 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN137 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN140 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN143 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN146 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN149 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN152 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN155 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN770 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN773 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN776 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN779 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN782 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN785 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN788 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN791 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN794 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN797 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN800 */ 131, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN803 */ 9, /* CYHAL_TRIGGER_TR_GROUP8_INPUT1 */ 9, /* CYHAL_TRIGGER_TR_GROUP8_INPUT2 */ 9, /* CYHAL_TRIGGER_TR_GROUP8_INPUT3 */ 9, /* CYHAL_TRIGGER_TR_GROUP8_INPUT4 */ 9, /* CYHAL_TRIGGER_TR_GROUP8_INPUT5 */ 10, /* CYHAL_TRIGGER_TR_GROUP8_INPUT6 */ 10, /* CYHAL_TRIGGER_TR_GROUP8_INPUT7 */ 10, /* CYHAL_TRIGGER_TR_GROUP8_INPUT8 */ 10, /* CYHAL_TRIGGER_TR_GROUP8_INPUT9 */ 10, /* CYHAL_TRIGGER_TR_GROUP8_INPUT10 */ }; const uint8_t cyhal_mux_dest_index[333] = { 0, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ 1, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK1 */ 2, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK2 */ 0, /* CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK0 */ 1, /* CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK1 */ 2, /* CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK2 */ 0, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ 1, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN1 */ 2, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN2 */ 3, /* CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN0 */ 4, /* CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN1 */ 5, /* CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN2 */ 2, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 */ 3, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 */ 0, /* CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 */ 1, /* CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 */ 2, /* CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 */ 3, /* CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 */ 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 */ 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 */ 4, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 */ 5, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 */ 6, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 */ 7, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 */ 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 */ 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 */ 4, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 */ 5, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 */ 6, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 */ 7, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 */ 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 */ 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 */ 4, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 */ 5, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 */ 6, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 */ 7, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 */ 8, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 */ 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 */ 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 */ 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 */ 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 */ 4, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN29 */ 5, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN30 */ 6, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN31 */ 7, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN32 */ 8, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN33 */ 9, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN34 */ 10, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN35 */ 11, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN36 */ 12, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN37 */ 13, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN38 */ 14, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN39 */ 15, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN40 */ 16, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN41 */ 17, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN42 */ 18, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN43 */ 19, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN44 */ 20, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN45 */ 21, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN46 */ 22, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN47 */ 23, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN48 */ 24, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN49 */ 25, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN50 */ 26, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN51 */ 27, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN52 */ 28, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN53 */ 29, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN54 */ 30, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN55 */ 31, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN56 */ 32, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN57 */ 33, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN58 */ 34, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN59 */ 35, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN60 */ 36, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN61 */ 37, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN62 */ 38, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN63 */ 39, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN64 */ 40, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN65 */ 41, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN66 */ 42, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN67 */ 43, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN68 */ 44, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN69 */ 45, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN70 */ 46, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN71 */ 47, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN72 */ 48, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN73 */ 49, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN74 */ 50, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN75 */ 51, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN76 */ 52, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN77 */ 53, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN78 */ 54, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN79 */ 55, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN80 */ 56, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN81 */ 57, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN82 */ 58, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN83 */ 59, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN84 */ 60, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN85 */ 61, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN86 */ 62, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN87 */ 63, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN88 */ 0, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 */ 2, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 */ 3, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 */ 4, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 */ 5, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 */ 6, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 */ 7, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 */ 0, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 */ 2, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 */ 3, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 */ 4, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 */ 5, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 */ 6, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 */ 7, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 */ 8, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 */ 9, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 */ 10, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 */ 11, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 */ 12, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 */ 13, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 */ 14, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 */ 15, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 */ 0, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 */ 1, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 */ 2, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 */ 3, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 */ 4, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 */ 5, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 */ 6, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 */ 7, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 */ 8, /* CYHAL_TRIGGER_CPUSS_DW1_TR_IN32 */ 0, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 */ 1, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 */ 2, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER2 */ 3, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER3 */ 4, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER4 */ 5, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER5 */ 6, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER6 */ 7, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER7 */ 5, /* CYHAL_TRIGGER_PASS0_TR_DEBUG_FREEZE */ 0, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN0 */ 1, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN1 */ 2, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN2 */ 3, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN3 */ 4, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN4 */ 5, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN5 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN6 */ 7, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN7 */ 8, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN8 */ 9, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN9 */ 10, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN10 */ 11, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN11 */ 12, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN12 */ 13, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN13 */ 14, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN14 */ 15, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN15 */ 16, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN16 */ 17, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN17 */ 18, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN18 */ 19, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN19 */ 20, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN20 */ 21, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN21 */ 22, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN22 */ 23, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN23 */ 24, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN32 */ 25, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN33 */ 26, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN34 */ 27, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN35 */ 28, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN36 */ 29, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN37 */ 30, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN38 */ 31, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN39 */ 32, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN40 */ 33, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN41 */ 34, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN42 */ 35, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN43 */ 36, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN44 */ 37, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN45 */ 38, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN46 */ 39, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN47 */ 40, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN48 */ 41, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN49 */ 42, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN50 */ 43, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN51 */ 44, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN52 */ 45, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN53 */ 46, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN54 */ 47, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN55 */ 48, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN56 */ 49, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN57 */ 50, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN58 */ 51, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN59 */ 52, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN60 */ 53, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN61 */ 54, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN62 */ 55, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN63 */ 56, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN64 */ 57, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN65 */ 58, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN66 */ 59, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN67 */ 60, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN68 */ 61, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN69 */ 62, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN70 */ 63, /* CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN71 */ 0, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN0 */ 1, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN1 */ 2, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN2 */ 3, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN3 */ 4, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN4 */ 5, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN5 */ 6, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN6 */ 7, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN7 */ 8, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN8 */ 9, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN9 */ 10, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN10 */ 11, /* CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN11 */ 4, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */ 0, /* CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 */ 1, /* CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 */ 7, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */ 8, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 */ 6, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT */ 0, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */ 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */ 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */ 3, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */ 6, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */ 7, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */ 8, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */ 9, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */ 10, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */ 11, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */ 12, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */ 13, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */ 14, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */ 15, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */ 0, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */ 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */ 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */ 3, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */ 6, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */ 7, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */ 8, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */ 9, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */ 10, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */ 9, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */ 4, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN2 */ 5, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN5 */ 6, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN8 */ 7, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN11 */ 8, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN14 */ 9, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN17 */ 10, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN20 */ 11, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN23 */ 12, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN26 */ 13, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN29 */ 14, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN32 */ 15, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN35 */ 16, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN38 */ 17, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN41 */ 18, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN44 */ 19, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN47 */ 20, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN50 */ 21, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN53 */ 22, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN56 */ 23, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN59 */ 28, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN62 */ 29, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN65 */ 30, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN68 */ 31, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN71 */ 32, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN74 */ 33, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN77 */ 34, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN80 */ 35, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN83 */ 36, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN86 */ 37, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN89 */ 38, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN92 */ 39, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN95 */ 40, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN98 */ 41, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN101 */ 42, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN104 */ 43, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN107 */ 44, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN110 */ 45, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN113 */ 46, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN116 */ 47, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN119 */ 48, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN122 */ 49, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN125 */ 50, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN128 */ 51, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN131 */ 52, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN134 */ 53, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN137 */ 54, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN140 */ 55, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN143 */ 60, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN146 */ 61, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN149 */ 62, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN152 */ 63, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN155 */ 0, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN770 */ 24, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN773 */ 56, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN776 */ 1, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN779 */ 25, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN782 */ 57, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN785 */ 2, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN788 */ 26, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN791 */ 58, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN794 */ 3, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN797 */ 27, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN800 */ 59, /* CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN803 */ 0, /* CYHAL_TRIGGER_TR_GROUP8_INPUT1 */ 1, /* CYHAL_TRIGGER_TR_GROUP8_INPUT2 */ 2, /* CYHAL_TRIGGER_TR_GROUP8_INPUT3 */ 3, /* CYHAL_TRIGGER_TR_GROUP8_INPUT4 */ 4, /* CYHAL_TRIGGER_TR_GROUP8_INPUT5 */ 0, /* CYHAL_TRIGGER_TR_GROUP8_INPUT6 */ 1, /* CYHAL_TRIGGER_TR_GROUP8_INPUT7 */ 2, /* CYHAL_TRIGGER_TR_GROUP8_INPUT8 */ 3, /* CYHAL_TRIGGER_TR_GROUP8_INPUT9 */ 4, /* CYHAL_TRIGGER_TR_GROUP8_INPUT10 */ }; #endif /* CY_DEVICE_TVIIBE1M */