Cypress Semiconductor Cypress psoc6_04 PSoC6_04 1.0 PSoC6_04 (c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company)\n or an affiliate of Cypress Semiconductor Corporation.\n \n SPDX-License-Identifier: Apache-2.0\n \n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n \n http://www.apache.org/licenses/LICENSE-2.0\n \n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an "AS IS" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License. CM4 r0p1 little true true 1 3 0 8 32 0x00000000 0xFFFFFFFF PERI Peripheral interconnect 0x40000000 0 65536 registers TIMEOUT_CTL Timeout control 0x200 32 read-write 0xFFFF 0xFFFF TIMEOUT This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. [15:0] read-write TR_CMD Trigger command 0x220 32 read-write 0x0 0xE0001FFF TR_SEL Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. [7:0] read-write GROUP_SEL Specifies the trigger group: '0'-'15': trigger multiplexer groups. '16'-'31': trigger 1-to-1 groups. [12:8] read-write TR_EDGE Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. '1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. [29:29] read-write OUT_SEL Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. Note: this field is not used for trigger 1-to-1 groups. [30:30] read-write ACTIVATE SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. Note: when ACTIVATE is '1', SW should not modify the other register fields. SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write. [31:31] read-write DIV_CMD Divider command 0x400 32 read-write 0x3FF03FF 0xC3FF03FF DIV_SEL (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. [7:0] read-write TYPE_SEL Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [9:8] read-write PA_DIV_SEL (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. [23:16] read-write PA_TYPE_SEL Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [25:24] read-write DISABLE Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. [30:30] read-write ENABLE Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. [31:31] read-write 256 4 CLOCK_CTL[%s] Clock control 0xC00 32 read-write 0x3FF 0x3FF DIV_SEL Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. [7:0] read-write TYPE_SEL Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. [9:8] read-write 256 4 DIV_8_CTL[%s] Divider control (for 8.0 divider) 0x1000 32 read-write 0x0 0xFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write 256 4 DIV_16_CTL[%s] Divider control (for 16.0 divider) 0x1400 32 read-write 0x0 0xFFFF01 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 256 4 DIV_16_5_CTL[%s] Divider control (for 16.5 divider) 0x1800 32 read-write 0x0 0xFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [23:8] read-write 255 4 DIV_24_5_CTL[%s] Divider control (for 24.5 divider) 0x1C00 32 read-write 0x0 0xFFFFFFF9 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. [0:0] read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [7:3] read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [31:8] read-write ECC_CTL ECC control 0x2000 32 read-write 0x10000 0xFF0507FF WORD_ADDR Specifies the word address where the parity is injected. - On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [10:0] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_INJ_EN Enable error injection for PERI protection structure SRAM. When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. [18:18] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:24] read-write 10 32 GR[%s] Peripheral group structure 0x00004000 CLOCK_CTL Clock control 0x0 32 read-write 0x0 0xFF00 INT8_DIV Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write SL_CTL Slave control 0x10 32 read-write 0xFFFF 0xFFFFFFFF ENABLED_0 Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [0:0] read-write ENABLED_1 Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. [1:1] read-write ENABLED_2 N/A [2:2] read-write ENABLED_3 N/A [3:3] read-write ENABLED_4 N/A [4:4] read-write ENABLED_5 N/A [5:5] read-write ENABLED_6 N/A [6:6] read-write ENABLED_7 N/A [7:7] read-write ENABLED_8 N/A [8:8] read-write ENABLED_9 N/A [9:9] read-write ENABLED_10 N/A [10:10] read-write ENABLED_11 N/A [11:11] read-write ENABLED_12 N/A [12:12] read-write ENABLED_13 N/A [13:13] read-write ENABLED_14 N/A [14:14] read-write ENABLED_15 N/A [15:15] read-write DISABLED_0 Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However, once set to 1, this bit cannot be changed back to 0 anymore. [16:16] read-write DISABLED_1 N/A [17:17] read-write DISABLED_2 N/A [18:18] read-write DISABLED_3 N/A [19:19] read-write DISABLED_4 N/A [20:20] read-write DISABLED_5 N/A [21:21] read-write DISABLED_6 N/A [22:22] read-write DISABLED_7 N/A [23:23] read-write DISABLED_8 N/A [24:24] read-write DISABLED_9 N/A [25:25] read-write DISABLED_10 N/A [26:26] read-write DISABLED_11 N/A [27:27] read-write DISABLED_12 N/A [28:28] read-write DISABLED_13 N/A [29:29] read-write DISABLED_14 N/A [30:30] read-write DISABLED_15 N/A [31:31] read-write 12 1024 TR_GR[%s] Trigger group 0x00008000 256 4 TR_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x13FF TR_SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. [7:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write 9 1024 TR_1TO1_GR[%s] Trigger 1-to-1 group 0x0000C000 256 4 TR_CTL[%s] Trigger control register 0x0 32 read-write 0x0 0x1301 TR_SEL Specifies input trigger: '0'': constant signal level '0'. '1': input trigger. [0:0] read-write TR_INV Specifies if the output trigger is inverted. [8:8] read-write TR_EDGE Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. [9:9] read-write DBG_FREEZE_EN Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. [12:12] read-write PERI_MS Peripheral interconnect, master interface 0x40010000 0 65536 registers 8 64 PPU_PR[%s] Programmable protection structure pair 0x00000000 SL_ADDR Slave region, base address 0x0 32 read-write 0x0 0x0 ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. [31:2] read-write SL_SIZE Slave region, size 0x4 32 read-write 0x0 0x80000000 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. [31:31] read-write SL_ATT0 Slave attributes 0 0x10 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-write PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-write PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-write PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-write PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-write PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-write PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write SL_ATT1 Slave attributes 1 0x14 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-write PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-write PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-write PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-write PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-write PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-write PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-write PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-write PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write SL_ATT2 Slave attributes 2 0x18 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-write PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-write PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-write PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-write PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-write PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-write PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-write PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-write PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-write PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-write PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-write PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-write PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-write PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-write PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-write PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-write PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write MS_ADDR Master region, base address 0x20 32 read-only 0x0 0xFFFFFFC0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. [31:6] read-only MS_SIZE Master region, size 0x24 32 read-only 0x85000000 0x9F000000 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. [28:24] read-only VALID Master region enable: '1': Enabled. [31:31] read-only MS_ATT0 Master attributes 0 0x30 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-only PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-only PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-only PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-only PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-only PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-only PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write MS_ATT1 Master attributes 1 0x34 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-only PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-only PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-only PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-only PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-only PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-only PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-only PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-only PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write MS_ATT2 Master attributes 2 0x38 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-only PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-only PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-only PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-only PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-only PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-only PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-only PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-only PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write MS_ATT3 Master attributes 3 0x3C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-only PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-only PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-only PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-only PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-only PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-only PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-only PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-only PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write 227 64 PPU_FX[%s] Fixed protection structure pair 0x00000800 SL_ADDR Slave region, base address 0x0 32 read-only 0x0 0xFFFFFFFC ADDR30 This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. [31:2] read-only SL_SIZE Slave region, size 0x4 32 read-only 0x80000000 0x9F000000 REGION_SIZE This field specifies the size of the slave region: '0': Undefined. '1': 4 B region (this is the smallest region size). '2': 8 B region '3': 16 B region '4': 32 B region '5': 64 B region '6': 128 B region '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '29': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-only VALID Slave region enable: '0': Disabled. A disabled region will never result in a match on the transfer address. '1': Enabled. [31:31] read-only SL_ATT0 Slave attributes 0 0x10 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-write PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-write PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-write PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-write PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-write PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-write PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write SL_ATT1 Slave attributes 1 0x14 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-write PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-write PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-write PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-write PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-write PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-write PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-write PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-write PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write SL_ATT2 Slave attributes 2 0x18 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-write PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-write PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-write PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-write PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-write PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-write PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-write PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-write PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write SL_ATT3 Slave attributes 3 0x1C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-write PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-write PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-write PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-write PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-write PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-write PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-write PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-write PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write MS_ADDR Master region, base address 0x20 32 read-only 0x0 0xFFFFFFC0 ADDR26 This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. [31:6] read-only MS_SIZE Master region, size 0x24 32 read-only 0x85000000 0x9F000000 REGION_SIZE This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. [28:24] read-only VALID Master region enable: '1': Enabled. [31:31] read-only MS_ATT0 Master attributes 0 0x30 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC0_UR Protection context 0, user read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-only PC0_UW Protection context 0, user write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-only PC0_PR Protection context 0, privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [2:2] read-only PC0_PW Protection context 0, privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [3:3] read-only PC0_NS Protection context 0, non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [4:4] read-only PC1_UR Protection context 1, user read enable. [8:8] read-only PC1_UW Protection context 1, user write enable. [9:9] read-write PC1_PR Protection context 1, privileged read enable. [10:10] read-only PC1_PW Protection context 1, privileged write enable. [11:11] read-write PC1_NS Protection context 1, non-secure. [12:12] read-write PC2_UR Protection context 2, user read enable. [16:16] read-only PC2_UW Protection context 2, user write enable. [17:17] read-write PC2_PR Protection context 2, privileged read enable. [18:18] read-only PC2_PW Protection context 2, privileged write enable. [19:19] read-write PC2_NS Protection context 2, non-secure. [20:20] read-write PC3_UR Protection context 3, user read enable. [24:24] read-only PC3_UW Protection context 3, user write enable. [25:25] read-write PC3_PR Protection context 3, privileged read enable. [26:26] read-only PC3_PW Protection context 3, privileged write enable. [27:27] read-write PC3_NS Protection context 3, non-secure. [28:28] read-write MS_ATT1 Master attributes 1 0x34 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC4_UR Protection context 4, user read enable. [0:0] read-only PC4_UW Protection context 4, user write enable. [1:1] read-write PC4_PR Protection context 4, privileged read enable. [2:2] read-only PC4_PW Protection context 4, privileged write enable. [3:3] read-write PC4_NS Protection context 4, non-secure. [4:4] read-write PC5_UR Protection context 5, user read enable. [8:8] read-only PC5_UW Protection context 5, user write enable. [9:9] read-write PC5_PR Protection context 5, privileged read enable. [10:10] read-only PC5_PW Protection context 5, privileged write enable. [11:11] read-write PC5_NS Protection context 5, non-secure. [12:12] read-write PC6_UR Protection context 6, user read enable. [16:16] read-only PC6_UW Protection context 6, user write enable. [17:17] read-write PC6_PR Protection context 6, privileged read enable. [18:18] read-only PC6_PW Protection context 6, privileged write enable. [19:19] read-write PC6_NS Protection context 6, non-secure. [20:20] read-write PC7_UR Protection context 7, user read enable. [24:24] read-only PC7_UW Protection context 7, user write enable. [25:25] read-write PC7_PR Protection context 7, privileged read enable. [26:26] read-only PC7_PW Protection context 7, privileged write enable. [27:27] read-write PC7_NS Protection context 7, non-secure. [28:28] read-write MS_ATT2 Master attributes 2 0x38 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC8_UR Protection context 8, user read enable. [0:0] read-only PC8_UW Protection context 8, user write enable. [1:1] read-write PC8_PR Protection context 8, privileged read enable. [2:2] read-only PC8_PW Protection context 8, privileged write enable. [3:3] read-write PC8_NS Protection context 8, non-secure. [4:4] read-write PC9_UR Protection context 9, user read enable. [8:8] read-only PC9_UW Protection context 9, user write enable. [9:9] read-write PC9_PR Protection context 9, privileged read enable. [10:10] read-only PC9_PW Protection context 9, privileged write enable. [11:11] read-write PC9_NS Protection context 9, non-secure. [12:12] read-write PC10_UR Protection context 10, user read enable. [16:16] read-only PC10_UW Protection context 10, user write enable. [17:17] read-write PC10_PR Protection context 10, privileged read enable. [18:18] read-only PC10_PW Protection context 10, privileged write enable. [19:19] read-write PC10_NS Protection context 10, non-secure. [20:20] read-write PC11_UR Protection context 11, user read enable. [24:24] read-only PC11_UW Protection context 11, user write enable. [25:25] read-write PC11_PR Protection context 11, privileged read enable. [26:26] read-only PC11_PW Protection context 11, privileged write enable. [27:27] read-write PC11_NS Protection context 11, non-secure. [28:28] read-write MS_ATT3 Master attributes 3 0x3C 32 read-write 0x1F1F1F1F 0x1F1F1F1F PC12_UR Protection context 12, user read enable. [0:0] read-only PC12_UW Protection context 12, user write enable. [1:1] read-write PC12_PR Protection context 12, privileged read enable. [2:2] read-only PC12_PW Protection context 12, privileged write enable. [3:3] read-write PC12_NS Protection context 12, non-secure. [4:4] read-write PC13_UR Protection context 13, user read enable. [8:8] read-only PC13_UW Protection context 13, user write enable. [9:9] read-write PC13_PR Protection context 13, privileged read enable. [10:10] read-only PC13_PW Protection context 13, privileged write enable. [11:11] read-write PC13_NS Protection context 13, non-secure. [12:12] read-write PC14_UR Protection context 14, user read enable. [16:16] read-only PC14_UW Protection context 14, user write enable. [17:17] read-write PC14_PR Protection context 14, privileged read enable. [18:18] read-only PC14_PW Protection context 14, privileged write enable. [19:19] read-write PC14_NS Protection context 14, non-secure. [20:20] read-write PC15_UR Protection context 15, user read enable. [24:24] read-only PC15_UW Protection context 15, user write enable. [25:25] read-write PC15_PR Protection context 15, privileged read enable. [26:26] read-only PC15_PW Protection context 15, privileged write enable. [27:27] read-write PC15_NS Protection context 15, non-secure. [28:28] read-write CPUSS CPU subsystem (CPUSS) 0x40200000 0 65536 registers ioss_interrupts_gpio_0 GPIO Port Interrupt #0 0 ioss_interrupts_gpio_2 GPIO Port Interrupt #2 2 ioss_interrupts_gpio_3 GPIO Port Interrupt #3 3 ioss_interrupts_gpio_5 GPIO Port Interrupt #5 5 ioss_interrupts_gpio_6 GPIO Port Interrupt #6 6 ioss_interrupts_gpio_7 GPIO Port Interrupt #7 7 ioss_interrupts_gpio_8 GPIO Port Interrupt #8 8 ioss_interrupts_gpio_9 GPIO Port Interrupt #9 9 ioss_interrupts_gpio_10 GPIO Port Interrupt #10 10 ioss_interrupts_gpio_11 GPIO Port Interrupt #11 11 ioss_interrupts_gpio_12 GPIO Port Interrupt #12 12 ioss_interrupts_gpio_14 GPIO Port Interrupt #14 14 ioss_interrupt_gpio GPIO All Ports 15 ioss_interrupt_vdd GPIO Supply Detect Interrupt 16 lpcomp_interrupt Low Power Comparator Interrupt 17 scb_6_interrupt Serial Communication Block #6 (DeepSleep capable) 18 srss_interrupt_mcwdt_0 Multi Counter Watchdog Timer interrupt 19 srss_interrupt_mcwdt_1 Multi Counter Watchdog Timer interrupt 20 srss_interrupt_backup Backup domain interrupt 21 srss_interrupt Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) 22 cpuss_interrupts_ipc_0 CPUSS Inter Process Communication Interrupt #0 23 cpuss_interrupts_ipc_1 CPUSS Inter Process Communication Interrupt #1 24 cpuss_interrupts_ipc_2 CPUSS Inter Process Communication Interrupt #2 25 cpuss_interrupts_ipc_3 CPUSS Inter Process Communication Interrupt #3 26 cpuss_interrupts_ipc_4 CPUSS Inter Process Communication Interrupt #4 27 cpuss_interrupts_ipc_5 CPUSS Inter Process Communication Interrupt #5 28 cpuss_interrupts_ipc_6 CPUSS Inter Process Communication Interrupt #6 29 cpuss_interrupts_ipc_7 CPUSS Inter Process Communication Interrupt #7 30 cpuss_interrupts_ipc_8 CPUSS Inter Process Communication Interrupt #8 31 cpuss_interrupts_ipc_9 CPUSS Inter Process Communication Interrupt #9 32 cpuss_interrupts_ipc_10 CPUSS Inter Process Communication Interrupt #10 33 cpuss_interrupts_ipc_11 CPUSS Inter Process Communication Interrupt #11 34 cpuss_interrupts_ipc_12 CPUSS Inter Process Communication Interrupt #12 35 cpuss_interrupts_ipc_13 CPUSS Inter Process Communication Interrupt #13 36 cpuss_interrupts_ipc_14 CPUSS Inter Process Communication Interrupt #14 37 cpuss_interrupts_ipc_15 CPUSS Inter Process Communication Interrupt #15 38 pass_interrupt_sar_0 SAR ADC0 interrupt 39 pass_interrupt_sar_1 SAR ADC1 interrupt 40 pass_interrupt_ctbs individual interrupt per CTB 41 pass_interrupt_fifo_0 PASS FIFO0 43 pass_interrupt_fifo_1 PASS FIFO1 44 scb_0_interrupt Serial Communication Block #0 45 scb_1_interrupt Serial Communication Block #1 46 scb_2_interrupt Serial Communication Block #2 47 scb_4_interrupt Serial Communication Block #4 49 scb_5_interrupt Serial Communication Block #5 50 csd_interrupt CSD (Capsense) interrupt 51 cpuss_interrupts_dmac_0 CPUSS DMAC, Channel #0 52 cpuss_interrupts_dmac_1 CPUSS DMAC, Channel #1 53 cpuss_interrupts_dw0_0 CPUSS DataWire #0, Channel #0 56 cpuss_interrupts_dw0_1 CPUSS DataWire #0, Channel #1 57 cpuss_interrupts_dw0_2 CPUSS DataWire #0, Channel #2 58 cpuss_interrupts_dw0_3 CPUSS DataWire #0, Channel #3 59 cpuss_interrupts_dw0_4 CPUSS DataWire #0, Channel #4 60 cpuss_interrupts_dw0_5 CPUSS DataWire #0, Channel #5 61 cpuss_interrupts_dw0_6 CPUSS DataWire #0, Channel #6 62 cpuss_interrupts_dw0_7 CPUSS DataWire #0, Channel #7 63 cpuss_interrupts_dw0_8 CPUSS DataWire #0, Channel #8 64 cpuss_interrupts_dw0_9 CPUSS DataWire #0, Channel #9 65 cpuss_interrupts_dw0_10 CPUSS DataWire #0, Channel #10 66 cpuss_interrupts_dw0_11 CPUSS DataWire #0, Channel #11 67 cpuss_interrupts_dw0_12 CPUSS DataWire #0, Channel #12 68 cpuss_interrupts_dw0_13 CPUSS DataWire #0, Channel #13 69 cpuss_interrupts_dw0_14 CPUSS DataWire #0, Channel #14 70 cpuss_interrupts_dw0_15 CPUSS DataWire #0, Channel #15 71 cpuss_interrupts_dw0_16 CPUSS DataWire #0, Channel #16 72 cpuss_interrupts_dw0_17 CPUSS DataWire #0, Channel #17 73 cpuss_interrupts_dw0_18 CPUSS DataWire #0, Channel #18 74 cpuss_interrupts_dw0_19 CPUSS DataWire #0, Channel #19 75 cpuss_interrupts_dw0_20 CPUSS DataWire #0, Channel #20 76 cpuss_interrupts_dw0_21 CPUSS DataWire #0, Channel #21 77 cpuss_interrupts_dw0_22 CPUSS DataWire #0, Channel #22 78 cpuss_interrupts_dw0_23 CPUSS DataWire #0, Channel #23 79 cpuss_interrupts_dw0_24 CPUSS DataWire #0, Channel #24 80 cpuss_interrupts_dw0_25 CPUSS DataWire #0, Channel #25 81 cpuss_interrupts_dw0_26 CPUSS DataWire #0, Channel #26 82 cpuss_interrupts_dw0_27 CPUSS DataWire #0, Channel #27 83 cpuss_interrupts_dw0_28 CPUSS DataWire #0, Channel #28 84 cpuss_interrupts_dw1_0 CPUSS DataWire #1, Channel #0 85 cpuss_interrupts_dw1_1 CPUSS DataWire #1, Channel #1 86 cpuss_interrupts_dw1_2 CPUSS DataWire #1, Channel #2 87 cpuss_interrupts_dw1_3 CPUSS DataWire #1, Channel #3 88 cpuss_interrupts_dw1_4 CPUSS DataWire #1, Channel #4 89 cpuss_interrupts_dw1_5 CPUSS DataWire #1, Channel #5 90 cpuss_interrupts_dw1_6 CPUSS DataWire #1, Channel #6 91 cpuss_interrupts_dw1_7 CPUSS DataWire #1, Channel #7 92 cpuss_interrupts_dw1_8 CPUSS DataWire #1, Channel #8 93 cpuss_interrupts_dw1_9 CPUSS DataWire #1, Channel #9 94 cpuss_interrupts_dw1_10 CPUSS DataWire #1, Channel #10 95 cpuss_interrupts_dw1_11 CPUSS DataWire #1, Channel #11 96 cpuss_interrupts_dw1_12 CPUSS DataWire #1, Channel #12 97 cpuss_interrupts_dw1_13 CPUSS DataWire #1, Channel #13 98 cpuss_interrupts_dw1_14 CPUSS DataWire #1, Channel #14 99 cpuss_interrupts_dw1_15 CPUSS DataWire #1, Channel #15 100 cpuss_interrupts_dw1_16 CPUSS DataWire #1, Channel #16 101 cpuss_interrupts_dw1_17 CPUSS DataWire #1, Channel #17 102 cpuss_interrupts_dw1_18 CPUSS DataWire #1, Channel #18 103 cpuss_interrupts_dw1_19 CPUSS DataWire #1, Channel #19 104 cpuss_interrupts_dw1_20 CPUSS DataWire #1, Channel #20 105 cpuss_interrupts_dw1_21 CPUSS DataWire #1, Channel #21 106 cpuss_interrupts_dw1_22 CPUSS DataWire #1, Channel #22 107 cpuss_interrupts_dw1_23 CPUSS DataWire #1, Channel #23 108 cpuss_interrupts_dw1_24 CPUSS DataWire #1, Channel #24 109 cpuss_interrupts_dw1_25 CPUSS DataWire #1, Channel #25 110 cpuss_interrupts_dw1_26 CPUSS DataWire #1, Channel #26 111 cpuss_interrupts_dw1_27 CPUSS DataWire #1, Channel #27 112 cpuss_interrupts_dw1_28 CPUSS DataWire #1, Channel #28 113 cpuss_interrupts_fault_0 CPUSS Fault Structure Interrupt #0 114 cpuss_interrupts_fault_1 CPUSS Fault Structure Interrupt #1 115 cpuss_interrupt_crypto CRYPTO Accelerator Interrupt 116 cpuss_interrupt_fm FLASH Macro Interrupt 117 cpuss_interrupts_cm4_fp Floating Point operation fault 118 cpuss_interrupts_cm0_cti_0 CM0+ CTI #0 119 cpuss_interrupts_cm0_cti_1 CM0+ CTI #1 120 cpuss_interrupts_cm4_cti_0 CM4 CTI #0 121 cpuss_interrupts_cm4_cti_1 CM4 CTI #1 122 tcpwm_0_interrupts_0 TCPWM #0, Counter #0 123 tcpwm_0_interrupts_1 TCPWM #0, Counter #1 124 tcpwm_0_interrupts_2 TCPWM #0, Counter #2 125 tcpwm_0_interrupts_3 TCPWM #0, Counter #3 126 tcpwm_0_interrupts_256 TCPWM #0, Counter #256 131 tcpwm_0_interrupts_257 TCPWM #0, Counter #257 132 tcpwm_0_interrupts_258 TCPWM #0, Counter #258 133 tcpwm_0_interrupts_259 TCPWM #0, Counter #259 134 tcpwm_0_interrupts_260 TCPWM #0, Counter #260 135 tcpwm_0_interrupts_261 TCPWM #0, Counter #261 136 tcpwm_0_interrupts_262 TCPWM #0, Counter #262 137 tcpwm_0_interrupts_263 TCPWM #0, Counter #263 138 pass_interrupt_dacs Consolidated interrrupt for all DACs 146 smif_interrupt Serial Memory Interface interrupt 160 usb_interrupt_hi USB Interrupt 161 usb_interrupt_med USB Interrupt 162 usb_interrupt_lo USB Interrupt 163 canfd_0_interrupt0 Can #0, Consolidated interrupt #0 168 canfd_0_interrupts0_0 CAN #0, Interrupt #0, Channel #0 169 canfd_0_interrupts1_0 CAN #0, Interrupt #1, Channel #0 170 cpuss_interrupts_dw1_29 CPUSS DataWire #1, Channel #29 171 cpuss_interrupts_dw1_30 CPUSS DataWire #1, Channel #30 172 cpuss_interrupts_dw1_31 CPUSS DataWire #1, Channel #31 173 cpuss_interrupts_dw0_29 CPUSS DataWire #0, Channel #29 174 IDENTITY Identity 0x0 32 read-only 0x0 0x0 P This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. [0:0] read-only NS This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. [1:1] read-only PC This field specifies the protection context of the transfer that reads the register. [7:4] read-only MS This field specifies the bus master identifier of the transfer that reads the register. [11:8] read-only CM4_STATUS CM4 status 0x4 32 read-only 0x13 0x13 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only PWR_DONE After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req [4:4] read-only CM4_CLOCK_CTL CM4 clock control 0x8 32 read-write 0x0 0xFF00 FAST_INT_DIV Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write CM4_CTL CM4 control 0xC 32 read-write 0x0 0x9F000000 IOC_MASK CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. [24:24] read-write DZC_MASK CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [25:25] read-write OFC_MASK CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [26:26] read-write UFC_MASK CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. [27:27] read-write IXC_MASK CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. [28:28] read-write IDC_MASK CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. [31:31] read-write CM4_INT0_STATUS CM4 interrupt 0 status 0x100 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 0. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT1_STATUS CM4 interrupt 1 status 0x104 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT2_STATUS CM4 interrupt 2 status 0x108 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT3_STATUS CM4 interrupt 3 status 0x10C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT4_STATUS CM4 interrupt 4 status 0x110 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT5_STATUS CM4 interrupt 5 status 0x114 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT6_STATUS CM4 interrupt 6 status 0x118 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_INT7_STATUS CM4 interrupt 7 status 0x11C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM4 activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM4_VECTOR_TABLE_BASE CM4 vector table base 0x200 32 read-write 0x0 0xFFFFFC00 ADDR22 Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. Note: the CM4 vector table is at an address that is a 1024 B multiple. [31:10] read-write 4 4 CM4_NMI_CTL[%s] CM4 NMI control 0x240 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [9:0] read-write UDB_PWR_CTL UDB power control 0x300 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Set Power mode for UDBs [1:0] read-write OFF See CM4_PWR_CTL 0 RESET See CM4_PWR_CTL 1 RETAINED See CM4_PWR_CTL 2 ENABLED See CM4_PWR_CTL 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only UDB_PWR_DELAY_CTL UDB power control 0x304 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write CM0_CTL CM0+ control 0x1000 32 read-write 0xFA050002 0xFFFF0003 SLV_STALL Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. [0:0] read-write ENABLED Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). [1:1] read-write VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only CM0_STATUS CM0+ status 0x1004 32 read-only 0x0 0x3 SLEEPING Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. [0:0] read-only SLEEPDEEP Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. [1:1] read-only CM0_CLOCK_CTL CM0+ clock control 0x1008 32 read-write 0x0 0xFF00FF00 SLOW_INT_DIV Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. [15:8] read-write PERI_INT_DIV Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. [31:24] read-write CM0_INT0_STATUS CM0+ interrupt 0 status 0x1100 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 0. Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. [9:0] read-only SYSTEM_INT_VALID Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. [31:31] read-only CM0_INT1_STATUS CM0+ interrupt 1 status 0x1104 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT2_STATUS CM0+ interrupt 2 status 0x1108 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT3_STATUS CM0+ interrupt 3 status 0x110C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT4_STATUS CM0+ interrupt 4 status 0x1110 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT5_STATUS CM0+ interrupt 5 status 0x1114 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT6_STATUS CM0+ interrupt 6 status 0x1118 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_INT7_STATUS CM0+ interrupt 7 status 0x111C 32 read-only 0x0 0x80000000 SYSTEM_INT_IDX Lowest CM0+ activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS. [9:0] read-only SYSTEM_INT_VALID See description of CM0_INT0_STATUS. [31:31] read-only CM0_VECTOR_TABLE_BASE CM0+ vector table base 0x1120 32 read-write 0x0 0xFFFFFF00 ADDR24 Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. Note: the CM0+ vector table is at an address that is a 256 B multiple. [31:8] read-write 4 4 CM0_NMI_CTL[%s] CM0+ NMI control 0x1140 32 read-write 0x3FF 0x3FF SYSTEM_INT_IDX System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. [9:0] read-write CM4_PWR_CTL CM4 power control 0x1200 32 read-write 0xFA050001 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF Switch CM4 off Power off, clock off, isolate, reset and no retain. 0 RESET Reset CM4 Clock off, no isolated, no retain and reset. Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. 1 RETAINED Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain. 2 ENABLED Switch CM4 on. Power on, clock on, no isolate, no reset and no retain. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only CM4_PWR_DELAY_CTL CM4 power control 0x1204 32 read-write 0x12C 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write RAM0_CTL0 RAM 0 control 0x1300 32 read-write 0x30001 0x70303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [16:16] read-write ECC_AUTO_CORRECT HW ECC autocorrect functionality: '0': Disabled. '1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. [17:17] read-write ECC_INJ_EN Enable error injection for system SRAM 0. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0. [18:18] read-write RAM0_STATUS RAM 0 status 0x1304 32 read-only 0x1 0x1 WB_EMPTY Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. '0': Write buffer NOT empty. '1': Write buffer empty. Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). [0:0] read-only 16 4 RAM0_PWR_MACRO_CTL[%s] RAM 0 power control 0x1340 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE SRAM Power mode. [1:0] read-write OFF Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. 0 RSVD undefined 1 RETAINED Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode. 2 ENABLED Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. [31:16] read-only RAM1_CTL0 RAM 1 control 0x1380 32 read-write 0x30001 0x70303 SLOW_WS See RAM0_CTL. [1:0] read-write FAST_WS See RAM0_CTL. [9:8] read-write ECC_EN See RAM0_CTL. [16:16] read-write ECC_AUTO_CORRECT See RAM0_CTL. [17:17] read-write ECC_INJ_EN See RAM0_CTL. [18:18] read-write RAM1_STATUS RAM 1 status 0x1384 32 read-only 0x1 0x1 WB_EMPTY See RAM0_STATUS. [0:0] read-only RAM1_PWR_CTL RAM 1 power control 0x1388 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF See RAM0_PWR_MACRO_CTL. 0 RSVD undefined 1 RETAINED See RAM0_PWR_MACRO_CTL. 2 ENABLED See RAM0_PWR_MACRO_CTL. 3 VECTKEYSTAT See RAM0_PWR_MACRO_CTL. [31:16] read-only RAM2_CTL0 RAM 2 control 0x13A0 32 read-write 0x30001 0x70303 SLOW_WS See RAM0_CTL. [1:0] read-write FAST_WS See RAM0_CTL. [9:8] read-write ECC_EN See RAM0_CTL. [16:16] read-write ECC_AUTO_CORRECT See RAM0_CTL. [17:17] read-write ECC_INJ_EN See RAM0_CTL. [18:18] read-write RAM2_STATUS RAM 2 status 0x13A4 32 read-only 0x1 0x1 WB_EMPTY See RAM0_STATUS. [0:0] read-only RAM2_PWR_CTL RAM 2 power control 0x13A8 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Power mode. [1:0] read-write OFF See RAM0_PWR_MACRO_CTL. 0 RSVD undefined 1 RETAINED See RAM0_PWR_MACRO_CTL. 2 ENABLED See RAM0_PWR_MACRO_CTL. 3 VECTKEYSTAT See RAM0_PWR_MACRO_CTL. [31:16] read-only RAM_PWR_DELAY_CTL Power up delay used for all SRAM power domains 0x13C0 32 read-write 0x96 0x3FF UP Number clock cycles delay needed after power domain power up [9:0] read-write ROM_CTL ROM control 0x13C4 32 read-write 0x1 0x303 SLOW_WS Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies. [1:0] read-write FAST_WS Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. [9:8] read-write ECC_CTL ECC control 0x13C8 32 read-write 0x0 0xFFFFFFFF WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. This field needs to be written with the offset address within the memory, divided by 4. For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010. [24:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write PRODUCT_ID Product identifier and version (same as CoreSight RomTables) 0x1400 32 read-only 0x0 0xFFF FAMILY_ID Family ID a.k.a. Partnumber a.k.a. Silicon ID [11:0] read-only MAJOR_REV Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) [19:16] read-only MINOR_REV Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) [23:20] read-only DP_STATUS Debug port status 0x1410 32 read-only 0x4 0x7 SWJ_CONNECTED Specifies if the SWJ debug port is connected; i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active. [0:0] read-only SWJ_DEBUG_EN Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled. [1:1] read-only SWJ_JTAG_SEL Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected. [2:2] read-only AP_CTL Access port control 0x1414 32 read-write 0x0 0x70007 CM0_ENABLE Enables the CM0 AP interface: '0': Disabled. '1': Enabled. [0:0] read-write CM4_ENABLE Enables the CM4 AP interface: '0': Disabled. '1': Enabled. [1:1] read-write SYS_ENABLE Enables the system AP interface: '0': Disabled. '1': Enabled. [2:2] read-write CM0_DISABLE Disables the CM0 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. [16:16] read-write CM4_DISABLE Disables the CM4 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. [17:17] read-write SYS_DISABLE Disables the system AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. [18:18] read-write BUFF_CTL Buffer control 0x1500 32 read-write 0x1 0x1 WRITE_BUFF Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. [0:0] read-write SYSTICK_CTL SysTick timer control 0x1600 32 read-write 0x40000147 0xC3FFFFFF TENMS Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. [23:0] read-write CLOCK_SOURCE Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. [25:24] read-write SKEW Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise. [30:30] read-write NOREF Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. [31:31] read-write MBIST_STAT Memory BIST status 0x1704 32 read-only 0x0 0x3 SFP_READY Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. [0:0] read-only SFP_FAIL Report status of the BIST run, only valid if SFP_READY=1 [1:1] read-only CAL_SUP_SET Calibration support set and read 0x1800 32 read-write 0x0 0xFFFFFFFF DATA Read without side effect, write 1 to set [31:0] read-write CAL_SUP_CLR Calibration support clear and reset 0x1804 32 read-write 0x0 0xFFFFFFFF DATA Read side effect: when read all bits are cleared, write 1 to clear a specific bit Note: no exception for the debug host, it also causes the read side effect [31:0] read-write CM0_PC_CTL CM0+ protection context control 0x2000 32 read-write 0x0 0xF VALID Valid fields for the protection context handler CM0_PCi_HANDLER registers: Bit 0: Valid field for CM0_PC0_HANDLER. Bit 1: Valid field for CM0_PC1_HANDLER. Bit 2: Valid field for CM0_PC2_HANDLER. Bit 3: Valid field for CM0_PC3_HANDLER. [3:0] read-write CM0_PC0_HANDLER CM0+ protection context 0 handler 0x2040 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. [31:0] read-write CM0_PC1_HANDLER CM0+ protection context 1 handler 0x2044 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 1 handler. [31:0] read-write CM0_PC2_HANDLER CM0+ protection context 2 handler 0x2048 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 2 handler. [31:0] read-write CM0_PC3_HANDLER CM0+ protection context 3 handler 0x204C 32 read-write 0x0 0xFFFFFFFF ADDR Address of the protection context 3 handler. [31:0] read-write PROTECTION Protection status 0x20C4 32 read-write 0x0 0x7 STATE Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transitions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field. [2:0] read-write TRIM_ROM_CTL ROM trim control 0x2100 32 read-write 0x0 0xFFFFFFFF TRIM N/A [31:0] read-write TRIM_RAM_CTL RAM trim control 0x2104 32 read-write 0x0 0xFFFFFFFF TRIM N/A [31:0] read-write 1023 4 CM0_SYSTEM_INT_CTL[%s] CM0+ system interrupt control 0x8000 32 read-write 0x0 0x80000000 CPU_INT_IDX CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. [2:0] read-write CPU_INT_VALID Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. [31:31] read-write 1023 4 CM4_SYSTEM_INT_CTL[%s] CM4 system interrupt control 0xA000 32 read-write 0x0 0x80000000 CPU_INT_IDX N/A [2:0] read-write CPU_INT_VALID N/A [31:31] read-write FAULT Fault structures 0x40210000 0 65536 registers 2 256 STRUCT[%s] Fault structure 0x00000000 CTL Fault control 0x0 32 read-write 0x0 0x7 TR_EN Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). [0:0] read-write OUT_EN IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. [1:1] read-write RESET_REQ_EN Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. [2:2] read-write STATUS Fault status 0xC 32 read-write 0x0 0x80000000 IDX The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. [6:0] read-write VALID Valid indication: '0': Invalid. '1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: - STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) [31:31] read-write 4 4 DATA[%s] Fault data 0x10 32 read-write 0x0 0x0 DATA Captured fault source data. Note: the DATA registers can only be written when STATUS.VALID is '0'. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. [31:0] read-write PENDING0 Fault pending 0 0x40 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. Bit 4: DMA controller MPU. ... Bit 15: DAP MPU. Bit 16: CM4 system bus MPU. Bit 17: CM4 code bus MPU (for non FLASH controller accesses). Bit 18: CM4 code bus MPU (for FLASH controller accesses). [31:0] read-only PENDING1 Fault pending 1 0x44 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 16 - 31: See STATUS register. [31:0] read-only PENDING2 Fault pending 2 0x48 32 read-only 0x0 0x0 SOURCE This field specifies the following sources: Bit 0 - 31: See STATUS register. [31:0] read-only MASK0 Fault mask 0 0x50 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 31 to 0. [31:0] read-write MASK1 Fault mask 1 0x54 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 63 to 32. [31:0] read-write MASK2 Fault mask 2 0x58 32 read-write 0x0 0xFFFFFFFF SOURCE Fault source enables: Bits 31-0: Fault sources 95 to 64. [31:0] read-write INTR Interrupt 0xC0 32 read-write 0x0 0x1 FAULT This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source data. SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). [0:0] read-write INTR_SET Interrupt set 0xC4 32 read-write 0x0 0x1 FAULT SW writes a '1' to this field to set the corresponding field in the INTR register. [0:0] read-write INTR_MASK Interrupt mask 0xC8 32 read-write 0x0 0x1 FAULT Mask bit for corresponding field in the INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0xCC 32 read-only 0x0 0x1 FAULT Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only IPC IPC 0x40220000 0 65536 registers 16 32 STRUCT[%s] IPC structure 0x00000000 ACQUIRE IPC acquire 0x0 32 read-only 0x0 0x80000000 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock. [0:0] read-only NS Secure/non-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only SUCCESS Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). [31:31] read-only RELEASE IPC release 0x4 32 write-only 0x0 0xFFFF INTR_RELEASE Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only NOTIFY IPC notification 0x8 32 write-only 0x0 0xFFFF INTR_NOTIFY This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. [15:0] write-only DATA0 IPC data 0 0xC 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write DATA1 IPC data 1 0x10 32 read-write 0x0 0x0 DATA This field holds a 32-bit data element that is associated with the IPC structure. [31:0] read-write LOCK_STATUS IPC lock status 0x1C 32 read-only 0x0 0x80000000 P This field specifies the user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS This field specifies the secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only PC This field specifies the protection context that successfully acquired the lock. [7:4] read-only MS This field specifies the bus master identifier that successfully acquired the lock. [11:8] read-only ACQUIRED Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. [31:31] read-only 16 32 INTR_STRUCT[%s] IPC interrupt structure 0x00001000 INTR Interrupt 0x0 32 read-write 0x0 0xFFFFFFFF RELEASE These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [15:0] read-write NOTIFY These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. [31:16] read-write INTR_SET Interrupt set 0x4 32 read-write 0x0 0xFFFFFFFF RELEASE SW writes a '1' to this field to set the corresponding field in the INTR register. [15:0] read-write NOTIFY SW writes a '1' to this field to set the corresponding field in the INTR register. [31:16] read-write INTR_MASK Interrupt mask 0x8 32 read-write 0x0 0xFFFFFFFF RELEASE Mask bit for corresponding field in the INTR register. [15:0] read-write NOTIFY Mask bit for corresponding field in the INTR register. [31:16] read-write INTR_MASKED Interrupt masked 0xC 32 read-only 0x0 0xFFFFFFFF RELEASE Logical and of corresponding request and mask bits. [15:0] read-only NOTIFY Logical and of corresponding INTR and INTR_MASK fields. [31:16] read-only PROT Protection 0x40230000 0 65536 registers SMPU SMPU 0x00000000 MS0_CTL Master 0 protection context control 0x0 32 read-write 0x303 0xFFFF0303 P Privileged setting ('0': user mode; '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities. [0:0] read-write NS Security setting ('0': secure mode; '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters. [1:1] read-write PRIO Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. [9:8] read-write PC_MASK_0 Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. [16:16] read-only PC_MASK_15_TO_1 Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). [31:17] read-write MS1_CTL Master 1 protection context control 0x4 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS2_CTL Master 2 protection context control 0x8 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS3_CTL Master 3 protection context control 0xC 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS4_CTL Master 4 protection context control 0x10 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS5_CTL Master 5 protection context control 0x14 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS6_CTL Master 6 protection context control 0x18 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS7_CTL Master 7 protection context control 0x1C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS8_CTL Master 8 protection context control 0x20 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS9_CTL Master 9 protection context control 0x24 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS10_CTL Master 10 protection context control 0x28 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS11_CTL Master 11 protection context control 0x2C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS12_CTL Master 12 protection context control 0x30 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS13_CTL Master 13 protection context control 0x34 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS14_CTL Master 14 protection context control 0x38 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write MS15_CTL Master 15 protection context control 0x3C 32 read-write 0x303 0xFFFF0303 P See MS0_CTL.P. [0:0] read-write NS See MS0_CTL.NS. [1:1] read-write PRIO See MS0_CTL.PRIO [9:8] read-write PC_MASK_0 See MS0_CTL.PC_MASK_0. [16:16] read-only PC_MASK_15_TO_1 See MS0_CTL.PC_MASK_15_TO_1. [31:17] read-write 16 64 SMPU_STRUCT[%s] SMPU structure 0x00002000 ADDR0 SMPU region address 0 (slave structure) 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT0 SMPU region attributes 0 (slave structure) 0x4 32 read-write 0x100 0x80000100 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write ADDR1 SMPU region address 1 (master structure) 0x20 32 read-only 0x0 0xFFFFFFFF SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. [7:0] read-only ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only. [31:8] read-only ATT1 SMPU region attributes 1 (master structure) 0x24 32 read-write 0x7000109 0x9F00012D UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. [0:0] read-only UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. [2:2] read-only PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. [3:3] read-only PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. [5:5] read-only NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write PC_MASK_0 This field specifies protection context identifier based access control for protection context '0'. [8:8] read-only PC_MASK_15_TO_1 This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. [23:9] read-write REGION_SIZE This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only. [28:24] read-only PC_MATCH This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. [30:30] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. [31:31] read-write 16 1024 MPU[%s] MPU 0x00004000 MS_CTL Master control 0x0 32 read-write 0x0 0xF000F PC Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: * On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: IF (the new PC is the same as MS_CTL.PC) PC is not affected; PC_SAVED is not affected. ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) An AHB-Lite bus error is generated for the exception handler fetch; PC is not affected; PC_SAVED is not affected. ELSE PC = 'new PC'; PC_SAVED = PC (push operation). * On entry of any other exception/interrupt handler: PC = PC_SAVED; PC_SAVED is not affected (pop operation). Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. [3:0] read-write PC_SAVED Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. Note: this field is ONLY used by the CM0+. [19:16] read-write 127 4 MS_CTL_READ_MIR[%s] Master control read mirror 0x4 32 read-only 0x0 0xF000F PC Read-only mirror of MS_CTL.PC [3:0] read-only PC_SAVED Read-only mirror of MS_CTL.PC_SAVED [19:16] read-only 8 32 MPU_STRUCT[%s] MPU structure 0x00000200 ADDR MPU region address 0x0 32 read-write 0x0 0x0 SUBREGION_DISABLE This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. [7:0] read-write ADDR24 This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. [31:8] read-write ATT MPU region attrributes 0x4 32 read-write 0x0 0x80000000 UR User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). [0:0] read-write UW User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). [1:1] read-write UX User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). [2:2] read-write PR Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). [3:3] read-write PW Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). [4:4] read-write PX Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). [5:5] read-write NS Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). [6:6] read-write REGION_SIZE This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region [28:24] read-write ENABLED Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. [31:31] read-write FLASHC Flash controller 0x40240000 0 65536 registers FLASH_CTL Control 0x0 32 read-write 0x110000 0x77330F MAIN_WS FLASH macro main interface wait states: '0': 0 wait states. ... '15': 15 wait states [3:0] read-write MAIN_MAP Specifies mapping of FLASH macro main array. 0: Mapping A. 1: Mapping B. This field is only used when MAIN_BANK_MODE is '1' (dual bank mode). [8:8] read-write WORK_MAP Specifies mapping of FLASH macro work array. 0: Mapping A. 1: Mapping B. This field is only used when WORK_BANK_MODE is '1' (dual bank mode). [9:9] read-write MAIN_BANK_MODE Specifies bank mode of FLASH macro main array. 0: Single bank mode. 1: Dual bank mode. [12:12] read-write WORK_BANK_MODE Specifies bank mode of FLASH macro work array. 0: Single bank mode. 1: Dual bank mode. [13:13] read-write MAIN_ECC_EN Enable ECC checking for FLASH main interface: 0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled. [16:16] read-write MAIN_ECC_INJ_EN Enable error injection for FLASH main interface. When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. [17:17] read-write MAIN_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro main interface internal error. - FLASH macro main interface non-recoverable ECC error. - FLASH macro main interface recoverable ECC error. - FLASH macro main interface memory hole error. [18:18] read-write WORK_ECC_EN Enable ECC checking for FLASH work interface: 0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled. [20:20] read-write WORK_ECC_INJ_EN Enable error injection for FLASH work interface. When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. [21:21] read-write WORK_ERR_SILENT Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro work interface internal error. - FLASH macro work interface non-recoverable ECC error. - FLASH macro work interface recoverable ECC error. - FLASH macro work interface memory hole error. [22:22] read-write FLASH_PWR_CTL Flash power control 0x4 32 read-write 0x3 0x3 ENABLE Controls 'enable' pin of the Flash memory. [0:0] read-write ENABLE_HV Controls 'enable_hv' pin of the Flash memory. [1:1] read-write FLASH_CMD Command 0x8 32 read-write 0x0 0x3 INV Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. [0:0] read-write BUFF_INV Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. [1:1] read-write ECC_CTL ECC control 0x2A0 32 read-write 0x0 0xFFFFFFFF WORD_ADDR Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated). [23:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. [31:24] read-write FM_SRAM_ECC_CTL0 eCT Flash SRAM ECC control 0 0x2B0 32 read-write 0x0 0xFFFFFFFF ECC_INJ_DATA 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. [31:0] read-write FM_SRAM_ECC_CTL1 eCT Flash SRAM ECC control 1 0x2B4 32 read-write 0x0 0x7F ECC_INJ_PARITY 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. [6:0] read-write FM_SRAM_ECC_CTL2 eCT Flash SRAM ECC control 2 0x2B8 32 read-only 0x0 0xFFFFFFFF CORRECTED_DATA 32-bit corrected data output of the ECC syndrome logic. [31:0] read-only FM_SRAM_ECC_CTL3 eCT Flash SRAM ECC control 3 0x2BC 32 read-write 0x1 0x111 ECC_ENABLE ECC generation/check enable for eCT Flash SRAM memory. [0:0] read-write ECC_INJ_EN eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: 1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. 2. Set the ECC_INJ_EN bit to '1'. 3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. 4. Check the corrected data in FM_SRAM_ECC_CTL2. 5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if corrupted data was written in step 1). 6. If not finished, start over at 1 with different data. [4:4] read-write ECC_TEST_FAIL Status of ECC test. 1 : ECC test failed because eCT Flash macro is busy and using the SRAM. 0: ECC was performed. [8:8] read-only CM0_CA_CTL0 CM0+ cache control 0x400 32 read-write 0xC0000001 0xC7030003 RAM_ECC_EN Enable ECC checking for cache accesses: 0: Disabled. 1: Enabled. [0:0] read-write RAM_ECC_INJ_EN Enable error injection for cache. When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address. [1:1] read-write WAY Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. [17:16] read-write SET_ADDR Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. [26:24] read-write PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. [30:30] read-write CA_EN Cache enable: 0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). 1: Enabled. [31:31] read-write CM0_CA_CTL1 CM0+ cache control 0x404 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Specifies power mode for CM0 cache. The following sequnece should be followed for turning OFF/ON the cache SRAM. Turn OFF sequence: a) Write CM0_CA_CTL0 to disable cache. b) Write CM0_CA_CTL1 to turn OFF cache SRAM. Turn ON sequence: a) Write CM0_CA_CTL1 to turn ON cache SRAM. b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. c) Write CM0_CA_CTL0 to enable cache. [1:0] read-write OFF Power OFF the CM0 cache SRAM. 0 RSVD Undefined 1 RETAINED Put CM0 cache SRAM in retained mode. 2 ENABLED Enable/Turn ON the CM0 cache SRAM. 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM0_CA_CTL2 CM0+ cache control 0x408 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM0_CA_STATUS0 CM0+ cache status 0 0x440 32 read-only 0x0 0xFFFFFFFF VALID32 Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS1 CM0+ cache status 1 0x444 32 read-only 0x0 0x0 TAG Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. [31:0] read-only CM0_CA_STATUS2 CM0+ cache status 2 0x448 32 read-only 0x0 0x0 LRU Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3. [5:0] read-only CM0_STATUS CM0+ interface status 0x460 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM0_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CM4_CA_CTL0 CM4 cache control 0x480 32 read-write 0xC0000001 0xC7030003 RAM_ECC_EN See CM0_CA_CTL. [0:0] read-write RAM_ECC_INJ_EN See CM0_CA_CTL. [1:1] read-write WAY See CM0_CA_CTL. [17:16] read-write SET_ADDR See CM0_CA_CTL. [26:24] read-write PREF_EN See CM0_CA_CTL. [30:30] read-write CA_EN See CM0_CA_CTL. [31:31] read-write CM4_CA_CTL1 CM4 cache control 0x484 32 read-write 0xFA050003 0xFFFF0003 PWR_MODE Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details. [1:0] read-write OFF See CM0_CA_CTL1 0 RSVD Undefined 1 RETAINED See CM0_CA_CTL1 2 ENABLED See CM0_CA_CTL1 3 VECTKEYSTAT Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. [31:16] read-only CM4_CA_CTL2 CM4 cache control 0x488 32 read-write 0x12C 0x3FF PWRUP_DELAY Number clock cycles delay needed after power domain power up [9:0] read-write CM4_CA_STATUS0 CM4 cache status 0 0x4C0 32 read-only 0x0 0xFFFFFFFF VALID32 See CM0_CA_STATUS0. [31:0] read-only CM4_CA_STATUS1 CM4 cache status 1 0x4C4 32 read-only 0x0 0x0 TAG See CM0_CA_STATUS1. [31:0] read-only CM4_CA_STATUS2 CM4 cache status 2 0x4C8 32 read-only 0x0 0x0 LRU See CM0_CA_STATUS2. [5:0] read-only CM4_STATUS CM4 interface status 0x4E0 32 read-write 0x0 0x3 MAIN_INTERNAL_ERR Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. [0:0] read-write WORK_INTERNAL_ERR See CM4_STATUS.MAIN_INTERNAL_ERROR. [1:1] read-write CRYPTO_BUFF_CTL Cryptography buffer control 0x500 32 read-write 0x40000000 0x40000000 PREF_EN Prefetch enable: 0: Disabled. 1: Enabled. A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. For eCT work Flash, prefetch will not be done. [30:30] read-write DW0_BUFF_CTL Datawire 0 buffer control 0x580 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write DW1_BUFF_CTL Datawire 1 buffer control 0x600 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write DMAC_BUFF_CTL DMA controller buffer control 0x680 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write EXT_MS0_BUFF_CTL External master 0 buffer control 0x700 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write EXT_MS1_BUFF_CTL External master 1 buffer control 0x780 32 read-write 0x40000000 0x40000000 PREF_EN See CRYPTO_BUFF_CTL. [30:30] read-write FM_CTL Flash Macro Registers 0x0000F000 FM_CTL Flash macro control 0x0 32 read-write 0x0 0x37F030F FM_MODE Requires (IF_SEL|WR_EN)=1 Flash macro mode selection [3:0] read-write FM_SEQ Requires (IF_SEL|WR_EN)=1 Flash macro sequence selection [9:8] read-write DAA_MUX_SEL Direct memory cell access address. [22:16] read-write IF_SEL Interface selection. Specifies the interface that is used for flash memory read operations: 0: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. 1: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. Note: IF_SEL and WR_EN cannot be changed at the same time [24:24] read-write WR_EN 0: normal mode 1: Fm Write Enable Note: IF_SEL and WR_EN cannot be changed at the same time [25:25] read-write STATUS Status 0x4 32 read-only 0x1800 0xFFFFFFFF TIMER_ENABLED This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires 0: timer not running 1: Timer is enabled and not expired yet [0:0] read-only HV_REGS_ISOLATED Indicates the isolation status at HV trim and redundancy registers inputs 0: Not isolated, writing permitted 1: isolated writing disabled [1:1] read-only ILLEGAL_HVOP Indicates a bulk, sector erase, program has been requested when axa=1 0: no error 1: illegal HV operation error [2:2] read-only TURBO_N After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. Used in the testchip boot only as an 'FM READY' flag. 0: turbo mode 1: normal mode [3:3] read-only WR_EN_MON FM_CTL.WR_EN bit after being synchronized in clk_r domain [4:4] read-only IF_SEL_MON FM_CTL.IF_SEL bit after being synchronized in clk_r domain [5:5] read-only TIMER_STATUS The actual timer state sync-ed in clk_c domain: 0: timer is not running: 1: timer is running; [6:6] read-only R_GRANT_DELAY_STATUS 0: R_GRANT_DELAY timer is not running 1: R_GRANT_DELAY timer is running [7:7] read-only FM_BUSY 0': FM not busy 1: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations. [8:8] read-only FM_READY 0: FM not ready 1: FM ready [9:9] read-only POS_PUMP_VLO POS pump VLO [10:10] read-only NEG_PUMP_VHI NEG pump VHI [11:11] read-only RWW FM Type (Read While Write or Not Read While Write): 0: Non RWW FM Type 1: RWW FM Type [12:12] read-only MAX_DOUT_WIDTH Internal memory core max data out size (number of data out bits per column): 0: x128 bits 1: x256 bits [13:13] read-only SECTOR0_SR 0: Sector 0 does not contain special rows. The special rows are located in separate special sectors. 1: Sector 0 contains special rows [14:14] read-only RESET_MM Test_only, internal node: mpcon reset_mm [15:15] read-only ROW_ODD Test_only, internal node: mpcon row_odd [16:16] read-only ROW_EVEN Test_only, internal node: mpcon row_even [17:17] read-only HVOP_SUB_SECTOR_N Test_only, internal node: mpcon bk_subb [18:18] read-only HVOP_SECTOR Test_only, internal node: mpcon bk_sec [19:19] read-only HVOP_BULK_ALL Test_only, internal node: mpcon bk_all [20:20] read-only CBUS_RA_MATCH Test_only, internal node: mpcon ra match [21:21] read-only CBUS_RED_ROW_EN Test_only, internal node: mpcon red_row_en [22:22] read-only RQ_ERROR Test_only, internal node: rq_error sync-de in clk_c domain [23:23] read-only PUMP_PDAC Test_only, internal node: regif pdac outputs to pos pump [27:24] read-only PUMP_NDAC Test_only, internal node: regif ndac outputs to pos pump [31:28] read-only FM_ADDR Flash macro address 0x8 32 read-write 0x0 0x1FFFFFF RA Row address. [15:0] read-write BA Bank address. [23:16] read-write AXA Auxiliary address field: 0: regular flash memory. 1: supervisory flash memory. [24:24] read-write BOOKMARK Bookmark register - keeps the current FW HV seq 0xC 32 read-write 0x0 0xFFFFFFFF BOOKMARK Used by FW. Keeps the Current HV cycle sequence [31:0] read-write GEOMETRY Regular flash geometry 0x10 32 read-only 0x0 0xFFFFFFFF ROW_COUNT Number of rows (minus 1): 0: 1 row 1: 2 rows 2: 3 rows ... '65535': 65536 rows [15:0] read-only BANK_COUNT Number of banks (minus 1): 0: 1 bank 1: 2 banks ... '255': 256 banks [23:16] read-only WORD_SIZE_LOG2 Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: 0: 1 Byte 1: 2 Bytes 2: 4 Bytes ... 3: 128 Bytes The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. [27:24] read-only PAGE_SIZE_LOG2 Number of Bytes per page (log 2): 0: 1 Byte 1: 2 Bytes 2: 4 Bytes ... 15: 32768 Bytes The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. [31:28] read-only GEOMETRY_SUPERVISORY Supervisory flash geometry 0x14 32 read-only 0x0 0xFFFFFFFF ROW_COUNT Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT [15:0] read-only BANK_COUNT Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. [23:16] read-only WORD_SIZE_LOG2 Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. [27:24] read-only PAGE_SIZE_LOG2 Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. [31:28] read-only ANA_CTL0 Analog control 0 0x18 32 read-write 0x400 0xFFFFFFFF MDAC Trimming of the output margin Voltage as a function of Vpos and Vneg. [7:0] read-write CSLDAC Trimming of common source line DAC. [10:8] read-write FLIP_AMUXBUS_AB Flips amuxbusa and amuxbusb 0: amuxbusa, amuxbusb 1: amuxbusb, amuxbusb [11:11] read-write NDAC_MIN NDAC staircase min value [15:12] read-write PDAC_MIN PDAC staircase min value [19:16] read-write SCALE_PRG_SEQ01 PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [21:20] read-write SCALE_PRG_SEQ12 PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [23:22] read-write SCALE_PRG_SEQ23 PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [25:24] read-write SCALE_SEQ30 PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [27:26] read-write SCALE_PRG_PEON PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [29:28] read-write SCALE_PRG_PEOFF PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [31:30] read-write ANA_CTL1 Analog control 1 0x1C 32 read-write 0xD32FAFA 0xFFFFFFFF NDAC_MAX Ndac Max Value.Trimming of negative pump output Voltage. [3:0] read-write NDAC_STEP Ndac step increment [7:4] read-write PDAC_MAX Pdac Max Value.Trimming of positive pump output Voltage: [11:8] read-write PDAC_STEP Pdac step increment [15:12] read-write NPDAC_STEP_TIME Ndac/Pdac step duration: (1uS .. 255uS) * 8 When = 0 N/PDAC_MAX control the pumps [23:16] read-write NPDAC_ZERO_TIME Ndac/Pdac LO duration: (1uS .. 255uS) * 8 When 0, N/PDAC don't return to 0 [31:24] read-write WAIT_CTL Wait State control 0x28 32 read-write 0x30B09 0x3F070F0F WAIT_FM_MEM_RD Number of C interface wait cycles (on 'clk_c') for a read from the memory [3:0] read-write WAIT_FM_HV_RD Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. Common for reading HV Page Latches and the DATA_COMP_RESULT bit [11:8] read-write WAIT_FM_HV_WR Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. [18:16] read-write FM_RWW_MODE 00: Full CBUS MODE 01: RWW 10: RWW. R_GRANT is stalling r_bus for the whole program/erase duration [25:24] read-write LV_SPARE_1 Spare register [26:26] read-write DRMM 0: Normal 1: Test mode to enable Margin mode for 2 rows at a time [27:27] read-write MBA 0: Normal 1: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program). [28:28] read-write PL_SOFT_SET_EN Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API [29:29] read-write TIMER_CLK_CTL Timer prescaler (clk_t to timer clock frequency divider) 0x34 32 read-write 0x8 0xFFFFFFFF TIMER_CLOCK_FREQ Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer. Equal to the frequency in MHz of the timer clock 'clk_t'. Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4' Max clk_t frequency = 100MHz. This field is updated at runtime with the 'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table [7:0] read-write RGRANT_DELAY_PRG_PEON PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [15:8] read-write RGRANT_DELAY_PRG_PEOFF PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [23:16] read-write RGRANT_DELAY_PRG_SEQ01 PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [31:24] read-write TIMER_CTL Timer control 0x38 32 read-write 0x4000001 0xE700FFFF PERIOD Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. [14:0] read-write SCALE Timer tick scale: 0: 1 microsecond. 1: 100 microseconds. [15:15] read-write AUTO_SEQUENCE 1': Starts1 the HV automatic sequencing Cleared by HW [24:24] read-write PRE_PROG 1 during pre-program operation [25:25] read-write PRE_PROG_CSL 0: CSL lines driven by CSL_DAC 1: CSL lines driven by VNEG_G [26:26] read-write PUMP_EN Pump enable: 0: disabled 1: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM). SW sets this field to '1' to generate a single PE pulse. HW clears this field when timer is expired. [29:29] read-write ACLK_EN ACLK enable (generates a single cycle pulse for the FM): 0: disabled 1: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. [30:30] read-write TIMER_EN Timer enable: 0: disabled 1: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. [31:31] read-write ACLK_CTL MPCON clock 0x3C 32 write-only 0x0 0x1 ACLK_GEN A write to this register generates the clock pulse for HV control registers (mpcon outputs) [0:0] write-only INTR Interrupt 0x40 32 read-write 0x0 0x1 TIMER_EXPIRED Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. [0:0] read-write INTR_SET Interrupt set 0x44 32 read-write 0x0 0x1 TIMER_EXPIRED Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt mask 0x48 32 read-write 0x0 0x1 TIMER_EXPIRED Mask for corresponding field in INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0x4C 32 read-only 0x0 0x1 TIMER_EXPIRED Logical and of corresponding request and mask fields. [0:0] read-only CAL_CTL0 Cal control BG LO trim bits 0x50 32 read-write 0x38F8F 0xFFFFF VCT_TRIM_LO_HV LO Bandgap Voltage Temperature Compensation trim control. [4:0] read-write CDAC_LO_HV LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. [7:5] read-write VBG_TRIM_LO_HV LO Bandgap Voltage trim control. [12:8] read-write VBG_TC_TRIM_LO_HV LO Bandgap Voltage Temperature Compensation trim control [15:13] read-write ICREF_TC_TRIM_LO_HV LO Bandgap Current Temperature Compensation trim control [18:16] read-write IPREF_TRIMA_LO_HV Adds 100-150nA boost on IPREF_LO [19:19] read-write CAL_CTL1 Cal control BG HI trim bits 0x54 32 read-write 0x38F8F 0xFFFFF VCT_TRIM_HI_HV HI Bandgap Voltage Temperature Compensation trim control. [4:0] read-write CDAC_HI_HV HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. [7:5] read-write VBG_TRIM_HI_HV HI Bandgap Voltage trim control. [12:8] read-write VBG_TC_TRIM_HI_HV HI Bandgap Voltage Temperature Compensation trim control. [15:13] read-write ICREF_TC_TRIM_HI_HV HI Bandgap Current Temperature Compensation trim control. [18:16] read-write IPREF_TRIMA_HI_HV Adds 100-150nA boost on IPREF_HI [19:19] read-write CAL_CTL2 Cal control BG LO&HI trim bits 0x58 32 read-write 0x7BE10 0xFFFFF ICREF_TRIM_LO_HV LO Bandgap Current trim control. [4:0] read-write ICREF_TRIM_HI_HV HI Bandgap Current trim control. [9:5] read-write IPREF_TRIM_LO_HV LO Bandgap IPTAT trim control. [14:10] read-write IPREF_TRIM_HI_HV HI Bandgap IPTAT trim control. [19:15] read-write CAL_CTL3 Cal control osc trim bits, idac, sdac, itim 0x5C 32 read-write 0x2004 0xFFFFF OSC_TRIM_HV Flash macro pump clock trim control. [3:0] read-write OSC_RANGE_TRIM_HV 0: Oscillator High Frequency Range 1: Oscillator Low Frequency range [4:4] read-write VPROT_ACT_HV Forces VPROT in active mode all the time [5:5] read-write IPREF_TC_HV 0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA 1: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA [6:6] read-write VREF_SEL_HV Voltage reference: 0: internal bandgap reference 1: external voltage reference [7:7] read-write IREF_SEL_HV Current reference: 0: internal current reference 1: external current reference [8:8] read-write REG_ACT_HV 0: VBST regulator will operate in active/standby mode based on control signal. 1: Forces the VBST regulator in active mode all the time [9:9] read-write FDIV_TRIM_HV FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby. Following are the clock frequencies seen by doubler 00: F = 1MHz 01: F = 0.5MHz 10: F = 2MHz 11: F = 4MHz [11:10] read-write VDDHI_HV 0: vdd < 2.3V 1: vdd >= 2.3V '0' setting can used for vdd > 2.3V also, but with a current penalty. [12:12] read-write TURBO_PULSEW_HV Turbo pulse width trim (Typical) 00: 40 us 01: 20 us 10: 15 us 11: 8 us [14:13] read-write BGLO_EN_HV 0: Normal (Automatic change over from HI to LO) 1: Force enable LO Bandgap [15:15] read-write BGHI_EN_HV 0: Normal (Automatic change over from HI to LO) 1: Force enable HI Bandgap When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active [16:16] read-write CL_ISO_DIS_HV 0: The internal logic controls the CL isolation 1: Forces CL bypass [17:17] read-write R_GRANT_EN_HV 0: r_grant handshake disabled, r_grant always 1. 1: r_grand handshake enabled [18:18] read-write LP_ULP_SW_HV LP<-->ULP switch for trim signals: 0: LP 1: ULP [19:19] read-write CAL_CTL4 Cal Control Vlim, SA, fdiv, reg_act 0x60 32 read-write 0x12AE0 0xFFFFF VLIM_TRIM_ULP_HV VLIM_TRIM[1:0]: 00: V2 = 650mV 01: V2 = 600mV 10: V2 = 750mV 11: V2 = 700mV [1:0] read-write IDAC_ULP_HV Sets the sense current reference offset value. Refer to trim tables for details. [5:2] read-write SDAC_ULP_HV Sets the sense current reference temp slope. Refer to trim tables for details. [7:6] read-write ITIM_ULP_HV Trimming of timing current [12:8] read-write FM_READY_DEL_ULP_HV 00: Default : delay 1ns 01: Delayed by 1.5us 10: Delayed by 2.0us 11: Delayed by 2.5us [14:13] read-write SPARE451_ULP_HV N/A [15:15] read-write READY_RESTART_N_HV Toggle: 1-->0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only. [16:16] read-write VBST_S_DIS_HV 0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL. 1: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector. [17:17] read-write AUTO_HVPULSE_HV 0: HV Pulse controlled by FW 1: HV Pulse controlled by Hardware [18:18] read-write UGB_EN_HV UGB enable in TM control [19:19] read-write CAL_CTL5 Cal control 0x64 32 read-write 0x2AE0 0xFFFFF VLIM_TRIM_LP_HV VLIM_TRIM[1:0]: 00: V2 = 650mV 01: V2 = 600mV 10: V2 = 750mV 11: V2 = 700mV [1:0] read-write IDAC_LP_HV Sets the sense current reference offset value. Refer to trim tables for details. [5:2] read-write SDAC_LP_HV Sets the sense current reference temp slope. Refer to trim tables for details. [7:6] read-write ITIM_LP_HV Trimming of timing current [12:8] read-write FM_READY_DEL_LP_HV 00: Delayed by 1us 01: Delayed by 1.5us 10: Delayed by 2.0us 11: Delayed by 2.5us [14:13] read-write SPARE451_LP_HV N/A [15:15] read-write SPARE52_HV N/A [17:16] read-write AMUX_SEL_HV Amux Select in AMUX_UGB 00: Bypass UGB for both amuxbusa and amuxbusb 01: Bypass UGB for amuxbusb while passing amuxbusa through UGB. 10: Bypass UGB for amuxbusa while passing amuxbusb through UGB. 11: UGB Calibrate mode [19:18] read-write CAL_CTL6 SA trim LP/ULP 0x68 32 read-write 0x36F7F 0xFFFFF SA_CTL_TRIM_T1_ULP_HV clk_trk delay [0:0] read-write SA_CTL_TRIM_T4_ULP_HV SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim) SA_CTL_TRIM_T4_ULP_HV<1:0> = eqc (eq cap trim) [3:1] read-write SA_CTL_TRIM_T5_ULP_HV SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim) SA_CTL_TRIM_T5_ULP_HV<1:0> = evc (integration cap trim) [6:4] read-write SA_CTL_TRIM_T6_ULP_HV SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim) SA_CTL_TRIM_T6_ULP_HV<0> = ecn (enable cap trim) [8:7] read-write SA_CTL_TRIM_T8_ULP_HV saen3 pulse width trim (Current trim) [9:9] read-write SA_CTL_TRIM_T1_LP_HV clk_trk delay [10:10] read-write SA_CTL_TRIM_T4_LP_HV SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim) SA_CTL_TRIM_T4_LP_HV<1:0> = eqc (eq cap trim) [13:11] read-write SA_CTL_TRIM_T5_LP_HV SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim) SA_CTL_TRIM_T5_LP_HV<1:0> = evc (integration cap trim) [16:14] read-write SA_CTL_TRIM_T6_LP_HV SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim) SA_CTL_TRIM_T6_LP_HV<0> = ecn (enable cap trim) [18:17] read-write SA_CTL_TRIM_T8_LP_HV saen3 pulse width trim (Current trim) [19:19] read-write CAL_CTL7 Cal control 0x6C 32 read-write 0x0 0xFFFFF ERSX8_CLK_SEL_HV Clock frequency into the ersx8 shift register block 00: Oscillator clock 01: Oscillator clock / 2 10: Oscillator clock / 4 11: Oscillator clock [1:0] read-write FM_ACTIVE_HV 0: Normal operation 1: Forces FM SYS in active mode [2:2] read-write TURBO_EXT_HV 0: Normal operation 1: Uses external turbo pulse [3:3] read-write NPDAC_HWCTL_DIS_HV 0': ndac, pdac staircase hardware controlled 1: ndac, pdac staircase disabled. Enables FW control. [4:4] read-write FM_READY_DIS_HV 0': fm ready is enabled 1: fm ready is disabled (fm_ready is always '1') [5:5] read-write ERSX8_EN_ALL_HV 0': Staggered turn on/off of GWL 1: GWL are turned on/off at the same time (old FM legacy) [6:6] read-write DISABLE_LOAD_ONCE_HV 0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register. 1: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register. [7:7] read-write SPARE7_HV N/A [9:8] read-write SPARE7_ULP_HV N/A [14:10] read-write SPARE7_LP_HV N/A [19:15] read-write RED_CTL01 Redundancy Control normal sectors 0,1 0x80 32 read-write 0x0 0x1FF01FF RED_ADDR_0 Bad Row Pair Address for Sector 0 [7:0] read-write RED_EN_0 1: Redundancy Enable for Sector 0 [8:8] read-write RED_ADDR_1 Bad Row Pair Address for Sector 1 [23:16] read-write RED_EN_1 1: Redundancy Enable for Sector 1 [24:24] read-write RED_CTL23 Redundancy Control normal sectors 2,3 0x84 32 read-write 0x0 0x1FF01FF RED_ADDR_2 Bad Row Pair Address for Sector 2 [7:0] read-write RED_EN_2 1: Redundancy Enable for Sector 2 [8:8] read-write RED_ADDR_3 Bad Row Pair Address for Sector 3 [23:16] read-write RED_EN_3 1: Redundancy Enable for Sector 3 [24:24] read-write RED_CTL45 Redundancy Control normal sectors 4,5 0x88 32 read-write 0x0 0x1FF01FF RED_ADDR_4 Bad Row Pair Address for Sector 4 [7:0] read-write RED_EN_4 1: Redundancy Enable for Sector 4 [8:8] read-write RED_ADDR_5 Bad Row Pair Address for Sector 5 [23:16] read-write RED_EN_5 1: Redundancy Enable for Sector 5 [24:24] read-write RED_CTL67 Redundancy Control normal sectors 6,7 0x8C 32 read-write 0x0 0x1FF01FF RED_ADDR_6 Bad Row Pair Address for Sector 6 [7:0] read-write RED_EN_6 1: Redundancy Enable for Sector 6 [8:8] read-write RED_ADDR_7 Bad Row Pair Address for Sector 7 [23:16] read-write RED_EN_7 1: Redundancy Enable for Sector 7 [24:24] read-write RED_CTL_SM01 Redundancy Control special sectors 0,1 0x90 32 read-write 0x0 0x1FF01FF RED_ADDR_SM0 Bad Row Pair Address for Special Sector 0 [7:0] read-write RED_EN_SM0 Redundancy Enable for Special Sector 0 [8:8] read-write RED_ADDR_SM1 Bad Row Pair Address for Special Sector 1 [23:16] read-write RED_EN_SM1 Redundancy Enable for Special Sector 1 [24:24] read-write RGRANT_DELAY_PRG R-grant delay for program 0x98 32 read-write 0x1000000 0x8FFFFFFF RGRANT_DELAY_PRG_SEQ12 PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [7:0] read-write RGRANT_DELAY_PRG_SEQ23 PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [15:8] read-write RGRANT_DELAY_SEQ30 PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [23:16] read-write RGRANT_DELAY_CLK Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay The value of this field is the integer result of 'clk_t frequency / 8'. Example: for clk_t=100 this field is INT(100/8) =12. This field is updated at runtime with the 'SW_RGRANT_DELAY_CLK ' value from the HV parameters table [27:24] read-write HV_PARAMS_LOADED 0: HV Pulse common params not loaded 1: HV Pulse common params loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3 [31:31] read-write PW_SEQ12 HV Pulse Delay for seq 1&2 pre 0xA0 32 read-write 0x0 0xFFFFFFFF PW_SEQ1 Seq1 delay [15:0] read-write PW_SEQ2_PRE Seq2 pre delay [31:16] read-write PW_SEQ23 HV Pulse Delay for seq2 post & seq3 0xA4 32 read-write 0x0 0xFFFFFFFF PW_SEQ2_POST Seq2 post delay [15:0] read-write PW_SEQ3 Seq3 delay [31:16] read-write RGRANT_SCALE_ERS R-grant delay scale for erase 0xA8 32 read-write 0x0 0xFFFF03FF SCALE_ERS_SEQ01 ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [1:0] read-write SCALE_ERS_SEQ12 ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [3:2] read-write SCALE_ERS_SEQ23 ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [5:4] read-write SCALE_ERS_PEON ERASE: Scale for R_GRANT_DELAY on PE On transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [7:6] read-write SCALE_ERS_PEOFF ERASE: Scale for R_GRANT_DELAY on PE OFF transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS [9:8] read-write RGRANT_DELAY_ERS_PEON ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [23:16] read-write RGRANT_DELAY_ERS_PEOFF ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [31:24] read-write RGRANT_DELAY_ERS R-grant delay for erase 0xAC 32 read-write 0x0 0xFFFFFF RGRANT_DELAY_ERS_SEQ01 ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [7:0] read-write RGRANT_DELAY_ERS_SEQ12 ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [15:8] read-write RGRANT_DELAY_ERS_SEQ23 ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled [23:16] read-write FM_PL_WRDATA_ALL Flash macro write page latches all 0x7FC 32 read-write 0x0 0xFFFFFFFF DATA32 Write all high Voltage page latches with the same 32-bit data in a single write cycle Read always returns 0. [31:0] read-write 256 4 FM_PL_DATA[%s] Flash macro Page Latches data 0x800 32 read-write 0x0 0xFFFFFFFF DATA32 Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality. [31:0] read-write 256 4 FM_MEM_DATA[%s] Flash macro memory sense amplifier and column decoder data 0xC00 32 read-only 0x0 0xFFFFFFFF DATA32 Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. [31:0] read-only SRSS SRSS Core Registers 0x40260000 0 65536 registers PWR_CTL Power Mode Control 0x0 32 read-write 0x0 0xFFFC0033 POWER_MODE Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. [1:0] read-only RESET System is resetting. 0 ACTIVE At least one CPU is running. 1 SLEEP No CPUs are running. Peripherals may be running. 2 DEEPSLEEP Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. 3 DEBUG_SESSION Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) [4:4] read-only NO_SESSION No debug session active 0 SESSION_ACTIVE Debug session is active. Power modes behave differently to keep the debug session active, and current consumption may be higher than datasheet specification. 1 LPM_READY Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. [5:5] read-only IREF_LPMODE Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Current reference generator operates in normal mode. 1: Current reference generator operates in low power mode. Response time is reduced to save current. [18:18] read-write VREFBUF_OK Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. [19:19] read-only DPSLP_REG_DIS Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: DeepSleep Regulator is on. 1: DeepSleep Regulator is off. [20:20] read-write RET_REG_DIS Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Retention Regulator is on. 1: Retention Regulator is off. [21:21] read-write NWELL_REG_DIS Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Nwell Regulator is on. 1: Nwell Regulator is off. [22:22] read-write LINREG_DIS Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear regulator is on. 1: Linear regulator is off. [23:23] read-write LINREG_LPMODE Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear Regulator operates in normal mode. 1: Linear Regulator operates in low power mode. Load current capability is reduced, and firmware must ensure the current is kept within the limit for this operating mode. [24:24] read-write PORBOD_LPMODE Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: POR/BOD circuits operate in normal mode. 1: POR/BOD circuits operate in low power mode. Response time is reduced to save current. [25:25] read-write BGREF_LPMODE Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Bandgap Voltage and Current Reference operates in normal mode. 1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current. The Active Reference may be disabled using ACT_REF_DIS=0. [26:26] read-write PLL_LS_BYPASS Bypass level shifter inside the PLL. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. [27:27] read-write VREFBUF_LPMODE Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Voltage Reference Buffer operates in normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. 1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current. [28:28] read-write VREFBUF_DIS Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. [29:29] read-write ACT_REF_DIS Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Reference is enabled 1: Active Reference is disabled [30:30] read-write ACT_REF_OK Indicates that the normal mode of the Active Reference is ready. [31:31] read-only PWR_HIBERNATE HIBERNATE Mode Register 0x4 32 read-write 0x0 0xCFFEFFFF TOKEN Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. [7:0] read-write UNLOCK This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. [15:8] read-write FREEZE Controls whether mode and state of GPIOs and SIOs in the system are frozen. This is intended to be used as part of the HIBERNATE entry and exit sequences. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. [17:17] read-write MASK_HIBALARM When set, HIBERNATE will wakeup for a RTC interrupt [18:18] read-write MASK_HIBWDT When set, HIBERNATE will wakeup if WDT matches [19:19] read-write POLARITY_HIBPIN Each bit sets the active polarity of the corresponding wakeup pin. 0: Pin input of 0 will wakeup the part from HIBERNATE 1: Pin input of 1 will wakeup the part from HIBERNATE [23:20] read-write MASK_HIBPIN When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the HIBERNATE wakeup pins. [27:24] read-write HIBERNATE_DISABLE Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. [30:30] read-write HIBERNATE Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. [31:31] read-write PWR_LVD_CTL Low Voltage Detector (LVD) Configuration Register 0x8 32 read-write 0x0 0xFF HVLVD1_TRIPSEL Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom) [3:0] read-write HVLVD1_SRCSEL Source selection for HVLVD1 [6:4] read-write VDDD Select VDDD 0 AMUXBUSA Select AMUXBUSA (VDDD branch) 1 RSVD N/A 2 VDDIO N/A 3 AMUXBUSB Select AMUXBUSB (VDDD branch) 4 HVLVD1_EN Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. [7:7] read-write PWR_BUCK_CTL Buck Control Register 0x14 32 read-write 0x5 0xC0000007 BUCK_OUT1_SEL Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V [2:0] read-write BUCK_EN Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. [30:30] read-write BUCK_OUT1_EN Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. [31:31] read-write PWR_BUCK_CTL2 Buck Control Register 2 0x18 32 read-write 0x0 0xC0000007 BUCK_OUT2_SEL Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V [2:0] read-write BUCK_OUT2_HW_SEL Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. [30:30] read-write BUCK_OUT2_EN Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. [31:31] read-write PWR_LVD_STATUS Low Voltage Detector (LVD) Status Register 0x1C 32 read-only 0x0 0x1 HVLVD1_OK HVLVD1 output. 0: below voltage threshold 1: above voltage threshold [0:0] read-only 16 4 PWR_HIB_DATA[%s] HIBERNATE Data Register 0x80 32 read-write 0x0 0xFFFFFFFF HIB_DATA Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. [31:0] read-write WDT_CTL Watchdog Counter Control Register 0x180 32 read-write 0xC0000001 0xC0000001 WDT_EN Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. [0:0] read-write WDT_LOCK Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. [31:30] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 WDT_CNT Watchdog Counter Count Register 0x184 32 read-write 0x0 0xFFFF COUNTER Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. [15:0] read-write WDT_MATCH Watchdog Counter Match Register 0x188 32 read-write 0x1000 0xFFFFF MATCH Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). [15:0] read-write IGNORE_BITS The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. [19:16] read-write 2 64 MCWDT_STRUCT[%s] Multi-Counter Watchdog Timer MCWDT_STRUCT 0x00000200 MCWDT_CNTLOW Multi-Counter Watchdog Sub-counters 0/1 0x4 32 read-write 0x0 0xFFFFFFFF WDT_CTR0 Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. [15:0] read-write WDT_CTR1 Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled [31:16] read-write MCWDT_CNTHIGH Multi-Counter Watchdog Sub-counter 2 0x8 32 read-write 0x0 0xFFFFFFFF WDT_CTR2 Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled [31:0] read-write MCWDT_MATCH Multi-Counter Watchdog Counter Match Register 0xC 32 read-write 0x0 0xFFFFFFFF WDT_MATCH0 Match value for sub-counter 0 of this MCWDT [15:0] read-write WDT_MATCH1 Match value for sub-counter 1 of this MCWDT [31:16] read-write MCWDT_CONFIG Multi-Counter Watchdog Counter Configuration 0x10 32 read-write 0x0 0x1F010F0F WDT_MODE0 Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). [1:0] read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt 3 WDT_CLEAR0 Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. [2:2] read-write WDT_CASCADE0_1 Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters [3:3] read-write WDT_MODE1 Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). [9:8] read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt 3 WDT_CLEAR1 Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. [10:10] read-write WDT_CASCADE1_2 Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. [11:11] read-write WDT_MODE2 Watchdog Counter 2 Mode. [16:16] read-write NOTHING Free running counter with no interrupt requests 0 INT Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). 1 WDT_BITS2 Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) ... 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) [28:24] read-write MCWDT_CTL Multi-Counter Watchdog Counter Control 0x14 32 read-write 0x0 0xB0B0B WDT_ENABLE0 Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [0:0] read-write WDT_ENABLED0 Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. [1:1] read-only WDT_RESET0 Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [3:3] read-write WDT_ENABLE1 Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [8:8] read-write WDT_ENABLED1 Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. [9:9] read-only WDT_RESET1 Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [11:11] read-write WDT_ENABLE2 Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) [16:16] read-write WDT_ENABLED2 Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. [17:17] read-only WDT_RESET2 Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. [19:19] read-write MCWDT_INTR Multi-Counter Watchdog Counter Interrupt Register 0x18 32 read-write 0x0 0x7 MCWDT_INT0 MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. [0:0] read-write MCWDT_INT1 MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. [1:1] read-write MCWDT_INT2 MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. [2:2] read-write MCWDT_INTR_SET Multi-Counter Watchdog Counter Interrupt Set Register 0x1C 32 read-write 0x0 0x7 MCWDT_INT0 Set interrupt for MCWDT_INT0 [0:0] read-write MCWDT_INT1 Set interrupt for MCWDT_INT1 [1:1] read-write MCWDT_INT2 Set interrupt for MCWDT_INT2 [2:2] read-write MCWDT_INTR_MASK Multi-Counter Watchdog Counter Interrupt Mask Register 0x20 32 read-write 0x0 0x7 MCWDT_INT0 Mask for sub-counter 0 [0:0] read-write MCWDT_INT1 Mask for sub-counter 1 [1:1] read-write MCWDT_INT2 Mask for sub-counter 2 [2:2] read-write MCWDT_INTR_MASKED Multi-Counter Watchdog Counter Interrupt Masked Register 0x24 32 read-only 0x0 0x7 MCWDT_INT0 Logical and of corresponding request and mask bits. [0:0] read-only MCWDT_INT1 Logical and of corresponding request and mask bits. [1:1] read-only MCWDT_INT2 Logical and of corresponding request and mask bits. [2:2] read-only MCWDT_LOCK Multi-Counter Watchdog Counter Lock Register 0x28 32 read-write 0x0 0xC0000000 MCWDT_LOCK Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. [31:30] read-write NO_CHG No effect 0 CLR0 Clears bit 0 1 CLR1 Clears bit 1 2 SET01 Sets both bits 0 and 1 3 16 4 CLK_DSI_SELECT[%s] Clock DSI Select Register 0x300 32 read-write 0x0 0x1F DSI_MUX Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. [4:0] read-write DSI_OUT0 DSI0 - dsi_out[0] 0 DSI_OUT1 DSI1 - dsi_out[1] 1 DSI_OUT2 DSI2 - dsi_out[2] 2 DSI_OUT3 DSI3 - dsi_out[3] 3 DSI_OUT4 DSI4 - dsi_out[4] 4 DSI_OUT5 DSI5 - dsi_out[5] 5 DSI_OUT6 DSI6 - dsi_out[6] 6 DSI_OUT7 DSI7 - dsi_out[7] 7 DSI_OUT8 DSI8 - dsi_out[8] 8 DSI_OUT9 DSI9 - dsi_out[9] 9 DSI_OUT10 DSI10 - dsi_out[10] 10 DSI_OUT11 DSI11 - dsi_out[11] 11 DSI_OUT12 DSI12 - dsi_out[12] 12 DSI_OUT13 DSI13 - dsi_out[13] 13 DSI_OUT14 DSI14 - dsi_out[14] 14 DSI_OUT15 DSI15 - dsi_out[15] 15 ILO ILO - Internal Low-speed Oscillator 16 WCO WCO - Watch-Crystal Oscillator 17 ALTLF ALTLF - Alternate Low-Frequency Clock 18 PILO PILO - Precision Internal Low-speed Oscillator 19 16 4 CLK_PATH_SELECT[%s] Clock Path Select Register 0x340 32 read-write 0x0 0x7 PATH_MUX Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. [2:0] read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator 2 ALTHF ALTHF - Alternate High-Frequency clock input (product-specific clock) 3 DSI_MUX DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. 4 16 4 CLK_ROOT_SELECT[%s] Clock Root Select Register 0x380 32 read-write 0x0 0x8000003F ROOT_MUX Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. [3:0] read-write PATH0 Select PATH0 (can be configured for FLL) 0 PATH1 Select PATH1 (can be configured for PLL0, if available in the product) 1 PATH2 Select PATH2 (can be configured for PLL1, if available in the product) 2 PATH3 Select PATH3 (can be configured for PLL2, if available in the product) 3 PATH4 Select PATH4 (can be configured for PLL3, if available in the product) 4 PATH5 Select PATH5 (can be configured for PLL4, if available in the product) 5 PATH6 Select PATH6 (can be configured for PLL5, if available in the product) 6 PATH7 Select PATH7 (can be configured for PLL6, if available in the product) 7 PATH8 Select PATH8 (can be configured for PLL7, if available in the product) 8 PATH9 Select PATH9 (can be configured for PLL8, if available in the product) 9 PATH10 Select PATH10 (can be configured for PLL9, if available in the product) 10 PATH11 Select PATH11 (can be configured for PLL10, if available in the product) 11 PATH12 Select PATH12 (can be configured for PLL11, if available in the product) 12 PATH13 Select PATH13 (can be configured for PLL12, if available in the product) 13 PATH14 Select PATH14 (can be configured for PLL13, if available in the product) 14 PATH15 Select PATH15 (can be configured for PLL14, if available in the product) 15 ROOT_DIV Selects predivider value for this clock root and DSI input. [5:4] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 ENABLE Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. [31:31] read-write CLK_SELECT Clock selection register 0x500 32 read-write 0x0 0xFF03 LFCLK_SEL Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. [1:0] read-write ILO ILO - Internal Low-speed Oscillator 0 WCO WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). 1 ALTLF ALTLF - Alternate Low-Frequency Clock. Capability is product-specific 2 PILO PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. 3 PUMP_SEL Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. [11:8] read-write PUMP_DIV Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. [14:12] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 DIV_BY_16 Divide selected clock source by 16 4 PUMP_ENABLE Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: 1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. 2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. 3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. [15:15] read-write CLK_TIMER_CTL Timer Clock Control Register 0x504 32 read-write 0x70000 0x80FF0301 TIMER_SEL Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. [0:0] read-write IMO IMO - Internal Main Oscillator 0 HF0_DIV Select the output of the predivider configured by TIMER_HF0_DIV. 1 TIMER_HF0_DIV Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. [9:8] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. 0 DIV_BY_2 Divide HFCLK0 by 2. 1 DIV_BY_4 Divide HFCLK0 by 4. 2 DIV_BY_8 Divide HFCLK0 by 8. 3 TIMER_DIV Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. [23:16] read-write ENABLE Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled [31:31] read-write CLK_ILO_CONFIG ILO Configuration 0x50C 32 read-write 0x80000000 0x80000001 ILO_BACKUP If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. 0: ILO turns off at XRES/BOD event or HIBERNATE entry. 1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. [0:0] read-write ENABLE Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. [31:31] read-write CLK_IMO_CONFIG IMO Configuration 0x510 32 read-write 0x80000000 0x80000000 ENABLE Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if CLK_MFO_CONFIG.DPSLP_ENABLE==0. [31:31] read-write CLK_OUTPUT_FAST Fast Clock Output Select Register 0x514 32 read-write 0x0 0xFFF0FFF FAST_SEL0 Select signal for fast clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL0 Selects the clock path chosen by PATH_SEL0 field 5 HFCLK_SEL0 Selects the output of the HFCLK_SEL0 mux 6 SLOW_SEL0 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 7 PATH_SEL0 Selects a clock path to use in fast clock output #0 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) [7:4] read-write HFCLK_SEL0 Selects a HFCLK tree for use in fast clock output #0 [11:8] read-write FAST_SEL1 Select signal for fast clock output #1 [19:16] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. 0 ECO External Crystal Oscillator (ECO) 1 EXTCLK External clock input (EXTCLK) 2 ALTHF Alternate High-Frequency (ALTHF) clock input to SRSS 3 TIMERCLK Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 4 PATH_SEL1 Selects the clock path chosen by PATH_SEL1 field 5 HFCLK_SEL1 Selects the output of the HFCLK_SEL1 mux 6 SLOW_SEL1 Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 7 PATH_SEL1 Selects a clock path to use in fast clock output #1 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) [23:20] read-write HFCLK_SEL1 Selects a HFCLK tree for use in fast clock output #1 logic [27:24] read-write CLK_OUTPUT_SLOW Slow Clock Output Select Register 0x518 32 read-write 0x0 0xFF SLOW_SEL0 Select signal for slow clock output #0 [3:0] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 SLOW_SEL1 Select signal for slow clock output #1 [7:4] read-write NC Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 0 ILO Internal Low Speed Oscillator (ILO) 1 WCO Watch-Crystal Oscillator (WCO) 2 BAK Root of the Backup domain clock tree (BAK) 3 ALTLF Alternate low-frequency clock input to SRSS (ALTLF) 4 LFCLK Root of the low-speed clock tree (LFCLK) 5 IMO Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 6 SLPCTRL Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 PILO Precision Internal Low Speed Oscillator (PILO) 8 CLK_CAL_CNT1 Clock Calibration Counter 1 0x51C 32 read-write 0x80000000 0x80FFFFFF CAL_COUNTER1 Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. [23:0] read-write CAL_COUNTER_DONE Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up [31:31] read-only CLK_CAL_CNT2 Clock Calibration Counter 2 0x520 32 read-only 0x0 0xFFFFFF CAL_COUNTER2 Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) [23:0] read-only CLK_ECO_CONFIG ECO Configuration Register 0x52C 32 read-write 0x2 0x80000002 AGC_EN Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. [1:1] read-write ECO_EN Master enable for ECO oscillator. [31:31] read-write CLK_ECO_STATUS ECO Status Register 0x530 32 read-only 0x0 0x3 ECO_OK Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. [0:0] read-only ECO_READY Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. [1:1] read-only CLK_PILO_CONFIG Precision ILO Configuration Register 0x53C 32 read-write 0x80 0xE00003FF PILO_FFREQ Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. [9:0] read-write PILO_CLK_EN Enable the PILO clock output. See PILO_EN field for required sequencing. [29:29] read-write PILO_RESET_N Reset the PILO. See PILO_EN field for required sequencing. [30:30] read-write PILO_EN Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. [31:31] read-write CLK_MF_SELECT Medium Frequency Clock Select Register 0x544 32 read-write 0x0 0x8000FF07 MFCLK_SEL Select source for MFCLK (clk_mf). Note that not all products support all clock sources. Selecting a clock source that is not supported results in undefined behavior. [2:0] read-write MFO MFO - medium frequency oscillator 0 MFCLK_DIV Divide selected clock source by (1+MFCLK_DIV). The output of this divider is MFCLK (clk_mf). Allows for integer divisions in the range [1, 256]. Do not change this setting while ENABLE==1. [15:8] read-write ENABLE Enable for MFCLK (clk_mf). [31:31] read-write CLK_MFO_CONFIG MFO Configuration Register 0x548 32 read-write 0x80000000 0xC0000000 DPSLP_ENABLE Enable for MFO during DEEPSLEEP. This bit is ignored when ENABLE==0. When ENABLE==1: 0: MFO is automatically disabled during DEEPSLEEP and enables upon wakeup; 1: MFO is kept enabled throughout DEEPSLEEP [30:30] read-write ENABLE Enable for MFO. [31:31] read-write CLK_FLL_CONFIG FLL Configuration Register 0x580 32 read-write 0x1000000 0x8103FFFF FLL_MULT Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) [17:0] read-write FLL_OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2 [24:24] read-write FLL_ENABLE Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_CONFIG2 FLL Configuration Register 2 0x584 32 read-write 0x20001 0x1FF1FFF FLL_REF_DIV Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191 [12:0] read-write LOCK_TOL Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 511: tolerate error of 512 count values [24:16] read-write CLK_FLL_CONFIG3 FLL Configuration Register 3 0x588 32 read-write 0x2800 0x301FFFFF FLL_LF_IGAIN FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [3:0] read-write FLL_LF_PGAIN FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal [7:4] read-write SETTLING_COUNT Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles [20:8] read-write BYPASS_SEL Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. [29:28] read-write AUTO N/A 0 AUTO1 N/A 1 FLL_REF Select FLL reference input (bypass mode). Ignores lock indicator 2 FLL_OUT Select FLL output. Ignores lock indicator. 3 CLK_FLL_CONFIG4 FLL Configuration Register 4 0x58C 32 read-write 0xFF 0xC1FF07FF CCO_LIMIT Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) [7:0] read-write CCO_RANGE Frequency range of CCO [10:8] read-write RANGE0 Target frequency is in range [48, 64) MHz 0 RANGE1 Target frequency is in range [64, 85) MHz 1 RANGE2 Target frequency is in range [85, 113) MHz 2 RANGE3 Target frequency is in range [113, 150) MHz 3 RANGE4 Target frequency is in range [150, 200] MHz 4 CCO_FREQ CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. [24:16] read-write CCO_HW_UPDATE_DIS Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. [30:30] read-write CCO_ENABLE Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on [31:31] read-write CLK_FLL_STATUS FLL Status Register 0x590 32 read-write 0x0 0x7 LOCKED FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. [0:0] read-only UNLOCK_OCCURRED N/A [1:1] read-write CCO_READY This indicates that the CCO is internally settled and ready to use. [2:2] read-only 15 4 CLK_PLL_CONFIG[%s] PLL Configuration Register 0x600 32 read-write 0x20116 0xB81F1F7F FEEDBACK_DIV Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) [6:0] read-write REFERENCE_DIV Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) [12:8] read-write OUTPUT_DIV Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) [20:16] read-write PLL_LF_MODE VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) [27:27] read-write BYPASS_SEL Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. [29:28] read-write AUTO Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. 0 AUTO1 Same as AUTO 1 PLL_REF Select PLL reference input (bypass mode). Ignores lock indicator 2 PLL_OUT Select PLL output. Ignores lock indicator. 3 ENABLE Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled [31:31] read-write 15 4 CLK_PLL_STATUS[%s] PLL Status Register 0x640 32 read-write 0x0 0x3 LOCKED PLL Lock Indicator [0:0] read-only UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. [1:1] read-write SRSS_INTR SRSS Interrupt Register 0x700 32 read-write 0x0 0x23 WDT_MATCH WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. [0:0] read-write HVLVD1 Interrupt for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Clock calibration counter is done. This field is reset during DEEPSLEEP mode. [5:5] read-write SRSS_INTR_SET SRSS Interrupt Set Register 0x704 32 read-write 0x0 0x23 WDT_MATCH Set interrupt for low voltage detector WDT_MATCH [0:0] read-write HVLVD1 Set interrupt for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. [5:5] read-write SRSS_INTR_MASK SRSS Interrupt Mask Register 0x708 32 read-write 0x0 0x23 WDT_MATCH Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. [0:0] read-write HVLVD1 Mask for low voltage detector HVLVD1 [1:1] read-write CLK_CAL Mask for clock calibration done [5:5] read-write SRSS_INTR_MASKED SRSS Interrupt Masked Register 0x70C 32 read-only 0x0 0x23 WDT_MATCH Logical and of corresponding request and mask bits. [0:0] read-only HVLVD1 Logical and of corresponding request and mask bits. [1:1] read-only CLK_CAL Logical and of corresponding request and mask bits. [5:5] read-only SRSS_INTR_CFG SRSS Interrupt Configuration Register 0x710 32 read-write 0x0 0x3 HVLVD1_EDGE_SEL Sets which edge(s) will trigger an IRQ for HVLVD1 [1:0] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 RES_CAUSE Reset Cause Observation Register 0x800 32 read-write 0x0 0x1FF RESET_WDT A basic WatchDog Timer (WDT) reset has occurred since last power cycle. [0:0] read-write RESET_ACT_FAULT Fault logging system requested a reset from its Active logic. [1:1] read-write RESET_DPSLP_FAULT Fault logging system requested a reset from its DeepSleep logic. [2:2] read-write RESET_CSV_WCO_LOSS Clock supervision logic requested a reset due to loss of a watch-crystal clock. [3:3] read-write RESET_SOFT A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. [4:4] read-write RESET_MCWDT0 Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. [5:5] read-write RESET_MCWDT1 Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. [6:6] read-write RESET_MCWDT2 Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. [7:7] read-write RESET_MCWDT3 Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. [8:8] read-write RES_CAUSE2 Reset Cause Observation Register 2 0x804 32 read-write 0x0 0xFFFFFFFF RESET_CSV_HF_LOSS Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. [15:0] read-write RESET_CSV_HF_FREQ Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. [31:16] read-write PWR_TRIM_REF_CTL Reference Trim Register 0x7F00 32 read-write 0x70F00000 0xF1FF5FFF ACT_REF_TCTRIM Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [3:0] read-write ACT_REF_ITRIM Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [7:4] read-write ACT_REF_ABSTRIM Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [12:8] read-write ACT_REF_IBOOST Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: normal operation others: risk mitigation [14:14] read-write DPSLP_REF_TCTRIM DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range [19:16] read-write DPSLP_REF_ABSTRIM DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [24:20] read-write DPSLP_REF_ITRIM DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [31:28] read-write PWR_TRIM_BODOVP_CTL BOD/OVP Trim Register 0x7F04 32 read-write 0x40D04 0xFDFF7 HVPORBOD_TRIPSEL HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE. [2:0] read-write HVPORBOD_OFSTRIM HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [6:4] read-write HVPORBOD_ITRIM HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [9:7] read-write LVPORBOD_TRIPSEL LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE. [12:10] read-write LVPORBOD_OFSTRIM LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [16:14] read-write LVPORBOD_ITRIM LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. [19:17] read-write CLK_TRIM_CCO_CTL CCO Trim Register 0x7F08 32 read-write 0xA7000020 0xBF00003F CCO_RCSTRIM CCO reference current source trim. [5:0] read-write CCO_STABLE_CNT Terminal count for the stabilization counter from CCO_ENABLE until stable. [29:24] read-write ENABLE_CNT Enables the automatic stabilization counter. [31:31] read-write CLK_TRIM_CCO_CTL2 CCO Trim Register 2 0x7F0C 32 read-write 0x884110 0x1FFFFFF CCO_FCTRIM1 CCO frequency 1st range calibration [4:0] read-write CCO_FCTRIM2 CCO frequency 2nd range calibration [9:5] read-write CCO_FCTRIM3 CCO frequency 3rd range calibration [14:10] read-write CCO_FCTRIM4 CCO frequency 4th range calibration [19:15] read-write CCO_FCTRIM5 CCO frequency 5th range calibration [24:20] read-write PWR_TRIM_WAKE_CTL Wakeup Trim Register 0x7F30 32 read-write 0x0 0xFF WAKE_DELAY Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. [7:0] read-write PWR_TRIM_LVD_CTL LVD Trim Register 0xFF10 32 read-write 0x20 0x77 HVLVD1_OFSTRIM HVLVD1 offset trim [2:0] read-write HVLVD1_ITRIM HVLVD1 current trim [6:4] read-write CLK_TRIM_ILO_CTL ILO Trim Register 0xFF18 32 read-write 0x2C 0x3F ILO_FTRIM ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. [5:0] read-write PWR_TRIM_PWRSYS_CTL Power System Trim Register 0xFF1C 32 read-write 0x17 0x1F ACT_REG_TRIM Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: 5'h07: 900mV (nominal) 5'h17: 1100mV (nominal) [4:0] read-write ACT_REG_BOOST Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default); 100mA chip: 2'b00 (default); 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); This register is only reset by XRES/POR/BOD/HIBERNATE. [31:30] read-write CLK_TRIM_ECO_CTL ECO Trim Register 0xFF20 32 read-write 0x1F0003 0x3F3FF7 WDTRIM Watch Dog Trim - Delta voltage below steady state level 0x0 - 50mV 0x1 - 75mV 0x2 - 100mV 0x3 - 125mV 0x4 - 150mV 0x5 - 175mV 0x6 - 200mV 0x7 - 225mV [2:0] read-write ATRIM Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0 - 150mV 0x1 - 175mV 0x2 - 200mV 0x3 - 225mV 0x4 - 250mV 0x5 - 275mV 0x6 - 300mV 0x7 - 325mV 0x8 - 350mV 0x9 - 375mV 0xA - 400mV 0xB - 425mV 0xC - 450mV 0xD - 475mV 0xE - 500mV 0xF - 525mV [7:4] read-write FTRIM Filter Trim - 3rd harmonic oscillation [9:8] read-write RTRIM Feedback resistor Trim [11:10] read-write GTRIM Gain Trim - Startup time [13:12] read-write ITRIM Current Trim [21:16] read-write CLK_TRIM_PILO_CTL PILO Trim Register 0xFF24 32 read-write 0x108500F 0x7DFF703F PILO_CFREQ Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. [5:0] read-write PILO_OSC_TRIM Trim for current in oscillator block. [14:12] read-write PILO_COMP_TRIM Trim for comparator bias current. [17:16] read-write PILO_NBIAS_TRIM Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier [19:18] read-write PILO_RES_TRIM Trim for beta-multiplier branch current [24:20] read-write PILO_ISLOPE_TRIM Trim for beta-multiplier current slope [27:26] read-write PILO_VTDIFF_TRIM Trim for VT-DIFF output (internal power supply) [30:28] read-write CLK_TRIM_PILO_CTL2 PILO Trim Register 2 0xFF28 32 read-write 0xDA10E0 0xFF1FFF PILO_VREF_TRIM Trim for voltage reference [7:0] read-write PILO_IREFBM_TRIM Trim for beta-multiplier current reference [12:8] read-write PILO_IREF_TRIM Trim for current reference [23:16] read-write CLK_TRIM_PILO_CTL3 PILO Trim Register 3 0xFF2C 32 read-write 0x4800 0xFFFF PILO_ENGOPT Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. [15:0] read-write BACKUP SRSS Backup Domain 0x40270000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0xFF0F3308 WCO_EN Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. [3:3] read-write CLK_SEL Clock select for BAK clock [9:8] read-write WCO Watch-crystal oscillator input. 0 ALTBAK This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK. 1 PRESCALER N/A [13:12] read-write WCO_BYPASS Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. [16:16] read-write VDDBAK_CTL Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. [18:17] read-write VBACKUP_MEAS Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. [19:19] read-write EN_CHARGE_KEY When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. [31:24] read-write RTC_RW RTC Read Write register 0x8 32 read-write 0x0 0x3 READ Read bit When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. [0:0] read-write WRITE Write bit Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. Only user RTC registers that were written to will get copied, others will not be affected. When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. [1:1] read-write CAL_CTL Oscillator calibration for absolute frequency 0xC 32 read-write 0x0 0x8000007F CALIB_VAL Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. [5:0] read-write CALIB_SIGN Calibration sign: 0= Negative sign: remove pulses (it takes more clock ticks to count one second) 1= Positive sign: add pulses (it takes less clock ticks to count one second) [6:6] read-write CAL_OUT Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. [31:31] read-write STATUS Status 0x10 32 read-only 0x0 0x5 RTC_BUSY pending RTC write [0:0] read-only WCO_OK Indicates that output has transitioned. [2:2] read-only RTC_TIME Calendar Seconds, Minutes, Hours, Day of Week 0x14 32 read-write 0x0 0x77F7F7F RTC_SEC Calendar seconds in BCD, 0-59 [6:0] read-write RTC_MIN Calendar minutes in BCD, 0-59 [14:8] read-write RTC_HOUR Calendar hours in BCD, value depending on 12/24HR mode 0=24HR: [21:16]=0-23 1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 [21:16] read-write CTRL_12HR Select 12/24HR mode: 1=12HR, 0=24HR [22:22] read-write RTC_DAY Calendar Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write RTC_DATE Calendar Day of Month, Month, Year 0x18 32 read-write 0x0 0xFF1F3F RTC_DATE Calendar Day of the Month in BCD, 1-31 Automatic Leap Year Correction [5:0] read-write RTC_MON Calendar Month in BCD, 1-12 [12:8] read-write RTC_YEAR Calendar year in BCD, 0-99 [23:16] read-write ALM1_TIME Alarm 1 Seconds, Minute, Hours, Day of Week 0x1C 32 read-write 0x1000000 0x87BFFFFF ALM_SEC Alarm seconds in BCD, 0-59 [6:0] read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match [7:7] read-write ALM_MIN Alarm minutes in BCD, 0-59 [14:8] read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match [15:15] read-write ALM_HOUR Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23 [21:16] read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match [23:23] read-write ALM_DAY Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match [31:31] read-write ALM1_DATE Alarm 1 Day of Month, Month 0x20 32 read-write 0x101 0x80009FBF ALM_DATE Alarm Day of the Month in BCD, 1-31 Leap Year corrected [5:0] read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match [7:7] read-write ALM_MON Alarm Month in BCD, 1-12 [12:8] read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match [15:15] read-write ALM_EN Master enable for alarm 1. 0: Alarm 1 is disabled. Fields for date and time are ignored. 1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. [31:31] read-write ALM2_TIME Alarm 2 Seconds, Minute, Hours, Day of Week 0x24 32 read-write 0x1000000 0x87BFFFFF ALM_SEC Alarm seconds in BCD, 0-59 [6:0] read-write ALM_SEC_EN Alarm second enable: 0=ignore, 1=match [7:7] read-write ALM_MIN Alarm minutes in BCD, 0-59 [14:8] read-write ALM_MIN_EN Alarm minutes enable: 0=ignore, 1=match [15:15] read-write ALM_HOUR Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23 [21:16] read-write ALM_HOUR_EN Alarm hour enable: 0=ignore, 1=match [23:23] read-write ALM_DAY Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended [26:24] read-write ALM_DAY_EN Alarm Day of the Week enable: 0=ignore, 1=match [31:31] read-write ALM2_DATE Alarm 2 Day of Month, Month 0x28 32 read-write 0x101 0x80009FBF ALM_DATE Alarm Day of the Month in BCD, 1-31 Leap Year corrected [5:0] read-write ALM_DATE_EN Alarm Day of the Month enable: 0=ignore, 1=match [7:7] read-write ALM_MON Alarm Month in BCD, 1-12 [12:8] read-write ALM_MON_EN Alarm Month enable: 0=ignore, 1=match [15:15] read-write ALM_EN Master enable for alarm 2. 0: Alarm 2 is disabled. Fields for date and time are ignored. 1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. [31:31] read-write INTR Interrupt request register 0x2C 32 read-write 0x0 0x7 ALARM1 Alarm 1 Interrupt [0:0] read-write ALARM2 Alarm 2 Interrupt [1:1] read-write CENTURY Century overflow interrupt [2:2] read-write INTR_SET Interrupt set request register 0x30 32 read-write 0x0 0x7 ALARM1 Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write ALARM2 Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write CENTURY Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write INTR_MASK Interrupt mask register 0x34 32 read-write 0x0 0x7 ALARM1 Mask bit for corresponding bit in interrupt request register. [0:0] read-write ALARM2 Mask bit for corresponding bit in interrupt request register. [1:1] read-write CENTURY Mask bit for corresponding bit in interrupt request register. [2:2] read-write INTR_MASKED Interrupt masked request register 0x38 32 read-only 0x0 0x7 ALARM1 Logical and of corresponding request and mask bits. [0:0] read-only ALARM2 Logical and of corresponding request and mask bits. [1:1] read-only CENTURY Logical and of corresponding request and mask bits. [2:2] read-only OSCCNT 32kHz oscillator counter 0x3C 32 read-only 0x0 0xFF CNT32KHZ 32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. [7:0] read-only TICKS 128Hz tick counter 0x40 32 read-only 0x0 0x3F CNT128HZ 128Hz counter (msb=2Hz) When SECONDS is written this field will be reset. [5:0] read-only PMIC_CTL PMIC control register 0x44 32 read-write 0xA0000000 0xE001FF00 UNLOCK This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. [15:8] read-write POLARITY N/A [16:16] read-write PMIC_EN_OUTEN Output enable for the output driver in the PMIC_EN pad. 0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present 1: Output pad is enabled for PMIC_EN pin. [29:29] read-write PMIC_ALWAYSEN Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. 0: Normal operation, PMIC_EN and PMIC_OUTEN work as described 1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. Note: This bit is a write-once bit until the next backup reset. [30:30] read-write PMIC_EN Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. [31:31] read-write RESET Backup reset register 0x48 32 read-write 0x0 0x80000000 RESET Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. [31:31] read-write 64 4 BREG[%s] Backup register region 0x1000 32 read-write 0x0 0xFFFFFFFF BREG Backup memory that contains application-specific data. Memory is retained on vbackup supply. [31:0] read-write TRIM Trim Register 0xFF00 32 read-write 0x0 0x3F TRIM WCO trim [5:0] read-write DW0 Datawire Controller DW 0x40280000 0 65536 registers CTL Control 0x0 32 read-write 0x1 0x80000003 ECC_EN Enable ECC checking: '0': Disabled. '1': Enabled. [0:0] read-write ECC_INJ_EN Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. [1:1] read-write ENABLED IP enable: '0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). '1': Enabled. [31:31] read-write STATUS Status 0x4 32 read-only 0x0 0xF0000000 P Active channel, user/privileged access control: '0': user mode. '1': privileged mode. [0:0] read-only NS Active channel, secure/non-secure access control: '0': secure. '1': non-secure. [1:1] read-only B Active channel, non-bufferable/bufferable access control: '0': non-bufferable '1': bufferable. [2:2] read-only PC Active channel protection context. [7:4] read-only PRIO Active channel priority. [9:8] read-only PREEMPTABLE Active channel preemptable. [11:11] read-only CH_IDX Active channel index. [24:16] read-only STATE State of the DW controller. '0': Default/inactive state. '1': Loading descriptor. '2': Loading data element from source location. '3': Storing data element to destination location. '4': CRC functionality (only used for CRC transfer descriptor type). '5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. '6': Error. [30:28] read-only ACTIVE Active channel present: '0': No. '1': Yes. [31:31] read-only ACT_DESCR_CTL Active descriptor control 0x20 32 read-only 0x0 0x0 DATA N/A [31:0] read-only ACT_DESCR_SRC Active descriptor source 0x24 32 read-only 0x0 0x0 DATA Copy of DESCR_SRC of the currently active descriptor. Base address of source location. [31:0] read-only ACT_DESCR_DST Active descriptor destination 0x28 32 read-only 0x0 0x0 DATA Copy of DESCR_DST of the currently active descriptor. Base address of destination location. Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes. [31:0] read-only ACT_DESCR_X_CTL Active descriptor X loop control 0x30 32 read-only 0x0 0x0 DATA Copy of DESCR_X_CTL of the currently active descriptor. [11:0] SRC_X_INCR Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. [23:12] DST_X_INCR Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. Note: this field is not used for CRC transfer descriptors and must be set to '0'. [31:24] X_COUNT Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. For a single transfer descriptor type, descriptor will not have X_CTL. [31:0] read-only ACT_DESCR_Y_CTL Active descriptor Y loop control 0x34 32 read-only 0x0 0x0 DATA Copy of DESCR_Y_CTL of the currently active descriptor. [11:0] SRC_Y_INCR Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. [23:12] DST_Y_INCR Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. [31:24] Y_COUNT Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL. [31:0] read-only ACT_DESCR_NEXT_PTR Active descriptor next pointer 0x38 32 read-only 0x0 0x0 ADDR Copy of DESCR_NEXT_PTR of the currently active descriptor. [31:2] ADDR Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. [31:2] read-only ACT_SRC Active source 0x40 32 read-only 0x0 0x0 SRC_ADDR Current address of source location. [31:0] read-only ACT_DST Active destination 0x44 32 read-only 0x0 0x0 DST_ADDR Current address of destination location. [31:0] read-only ECC_CTL ECC control 0x80 32 read-write 0x0 0xFE0003FF WORD_ADDR Specifies the word address where an error will be injected. - On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. [9:0] read-write PARITY ECC parity to use for ECC error injection at address WORD_ADDR. [31:25] read-write CRC_CTL CRC control 0x100 32 read-write 0x0 0x101 DATA_REVERSE Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): '0': Most significant bit (bit 1) first. '1': Least significant bit (bit 0) first. [0:0] read-write REM_REVERSE Specifies whether the remainder is bit reversed (reversal is performed after XORing): '0': No. '1': Yes. [8:8] read-write CRC_DATA_CTL CRC data control 0x110 32 read-write 0x0 0xFF DATA_XOR Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. [7:0] read-write CRC_POL_CTL CRC polynomial control 0x120 32 read-write 0x0 0xFFFFFFFF POLYNOMIAL CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). [31:0] read-write CRC_LFSR_CTL CRC LFSR control 0x130 32 read-write 0x0 0xFFFFFFFF LFSR32 State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). [31:0] read-write CRC_REM_CTL CRC remainder control 0x140 32 read-write 0x0 0xFFFFFFFF REM_XOR Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. [31:0] read-write CRC_REM_RESULT CRC remainder result 0x148 32 read-only 0x0 0xFFFFFFFF REM Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: '0': the more significant bits (bit 31 and down) contain the remainder. '1': the less significant bits (bit 0 and up) contain the remainder. Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. [31:0] read-only 32 64 CH_STRUCT[%s] DW channel structure 0x00008000 CH_CTL Channel control 0x0 32 read-write 0x0 0x80000300 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). [9:8] read-write PREEMPTABLE Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. [11:11] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). [31:31] read-write CH_STATUS Channel status 0x4 32 read-only 0x0 0x80000000 INTR_CAUSE Specifies the source of the interrupt cause: '0': No interrupt generated '1': Interrupt based on transfer complettion configuration based on INTR_TYPE '2': Source transfer bus error '3': Destination transfer bus error '4': Source address misalignment '5': Destination address misalignment '6': Current descriptor pointer is null '7': Active channel is disabled '8': Descriptor bus error '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). [3:0] read-only PENDING Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). [31:31] read-only CH_IDX Channel current indices 0x8 32 read-write 0x0 0x0 X_IDX Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [7:0] read-write Y_IDX Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR. [15:8] read-write CH_CURR_PTR Channel current descriptor pointer 0xC 32 read-write 0x0 0x0 ADDR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. [31:2] read-write INTR Interrupt 0x10 32 read-write 0x0 0x1 CH Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. [0:0] read-write INTR_SET Interrupt set 0x14 32 read-write 0x0 0x1 CH Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). [0:0] read-write INTR_MASK Interrupt mask 0x18 32 read-write 0x0 0x1 CH Mask for corresponding field in INTR register. [0:0] read-write INTR_MASKED Interrupt masked 0x1C 32 read-only 0x0 0x1 CH Logical and of corresponding INTR and INTR_MASK fields. [0:0] read-only SRAM_DATA0 SRAM data 0 0x20 32 read-write 0x0 0x0 DATA N/A [31:0] read-write SRAM_DATA1 SRAM data 1 0x24 32 read-write 0x0 0x0 DATA N/A [31:0] read-write TR_CMD Channel software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DW1 0x40290000 DMAC DMAC 0x402A0000 0 65536 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 ACTIVE Active channels 0x8 32 read-only 0x0 0xFF ACTIVE Specifies active channels; i.e. enabled channels whose trigger got activated. [7:0] read-only 2 256 CH[%s] DMA controller channel 0x00001000 CTL Channel control 0x0 32 read-write 0x2 0x800003F7 P User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). [0:0] read-write NS Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). [1:1] read-write B Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). [2:2] read-write PC Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All transactions for this channel uses the PC field for the protection context. [7:4] read-write PRIO Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. [9:8] read-write ENABLED Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' when an error interrupt cause is activated. [31:31] read-write IDX Channel current indices 0x10 32 read-only 0x0 0x0 X Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor. [15:0] read-only Y Specifies the Y loop index, with Y_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it loads a descriptor.. [31:16] read-only SRC Channel current source address 0x14 32 read-only 0x0 0x0 ADDR Current address of source location. [31:0] read-only DST Channel current destination address 0x18 32 read-only 0x0 0x0 ADDR Current address of destination location. [31:0] read-only CURR Channel current descriptor pointer 0x20 32 read-write 0x0 0x0 PTR Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. [31:2] read-write TR_CMD Channle software trigger 0x28 32 read-write 0x0 0x1 ACTIVATE Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. [0:0] read-write DESCR_STATUS Channel descriptor status 0x40 32 read-only 0x0 0x80000000 VALID Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. [31:31] read-only DESCR_CTL Channel descriptor control 0x60 32 read-only 0x0 0x0 WAIT_FOR_DEACT Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance. '0': Do not wait for trigger de-activation (for pulse sensitive triggers). '1': Wait for up to 4 cycles. '2': Wait for up to 16 cycles. '3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated. [1:0] read-only INTR_TYPE Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): '0': An interrupt is generated after a single transfer. '1': An interrupt is generated after a single 1D transfer or a memory copy transfer - If the descriptor type is 'single', the interrupt is generated after a single transfer. - If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer. - If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer. - If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer. '2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor). '3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. [3:2] read-only TR_OUT_TYPE Specifies when an output trigger is generated: '0': An output trigger is generated after a single transfer. '1': An output trigger is generated after a single 1D transfer or a memory copy transfer. - If the descriptor type is 'single', the output trigger is generated after a single transfer. - If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer. - If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer. - If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer. '2': An output trigger is generated after the execution of the current descriptor. '3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. [5:4] read-only TR_IN_TYPE Specifies the input trigger type (not to be confused with the descriptor type): '0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D. '1': A trigger results in the execution of a single 1D transfer. - If the descriptor type is 'single', the trigger results in the execution of a single transfer. - If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer. - If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer. - If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer. '2': A trigger results in the execution of the current descriptor. '3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information. [7:6] read-only DATA_PREFETCH Source data prefetch: '0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. '1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer. Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects. [8:8] read-only DATA_SIZE Specifies the data element size: '0': Byte (8 bits). '1': Halfword (16 bits). '2': Word (32 bits). DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: - DATA is 8 bit, SRC is 8 bit, DST is 8 bit. - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit. - DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0'). - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0'). - DATA is 16 bit, SRC is 16 bit, DST is 16 bit. - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit. - DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0'). - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0'). - DATA is 32 bit, SRC is 32 bit, DST is 32 bit. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type. [17:16] read-only CH_DISABLE Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): '0': Channel is not disabled. '1': Channel is disabled. [24:24] read-only SRC_TRANSFER_SIZE Specifies the bus transfer size to the source location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. [26:26] read-only DST_TRANSFER_SIZE Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. [27:27] read-only DESCR_TYPE Specifies the descriptor type (not to be confused with the trigger type): '0': Single transfer. The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c. '1': 1D transfer. The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14. '2': 2D transfer. The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c. '3': Memory copy. The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10. '4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. '5'-'7': Undefined. After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'. [30:28] read-only DESCR_SRC Channel descriptor source 0x64 32 read-only 0x0 0x0 ADDR Base address of source location. [31:0] read-only DESCR_DST Channel descriptor destination 0x68 32 read-only 0x0 0x0 ADDR Base address of destination location. [31:0] read-only DESCR_X_SIZE Channel descriptor X size 0x6C 32 read-only 0x0 0x0 X_COUNT Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed. [15:0] read-only DESCR_X_INCR Channel descriptor X increment 0x70 32 read-only 0x0 0x0 SRC_X Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. [15:0] read-only DST_X Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. [31:16] read-only DESCR_Y_SIZE Channel descriptor Y size 0x74 32 read-only 0x0 0x0 Y_COUNT Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. [15:0] read-only DESCR_Y_INCR Channel descriptor Y increment 0x78 32 read-only 0x0 0x0 SRC_Y Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. [15:0] read-only DST_Y Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. [31:16] read-only DESCR_NEXT Channel descriptor next pointer 0x7C 32 read-only 0x0 0x0 PTR Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. [31:2] read-only INTR Interrupt 0x80 32 read-write 0x0 0xFF COMPLETION Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. [0:0] read-write SRC_BUS_ERROR Activated (set to '1') on a bus error for a load from the source. [1:1] read-write DST_BUS_ERROR Activated (set to '1') on a bus error for a store to the destination. [2:2] read-write SRC_MISAL Activated (set to '1') on a misalignment of the source address. [3:3] read-write DST_MISAL Activated (set to '1') on a misalignment of the destination address. [4:4] read-write CURR_PTR_NULL Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. [5:5] read-write ACTIVE_CH_DISABLED Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. [6:6] read-write DESCR_BUS_ERROR Activated (set to '1') on a bus error for a load of the descriptor. [7:7] read-write INTR_SET Interrupt set 0x84 32 read-write 0x0 0xFF COMPLETION Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect). [0:0] read-write SRC_BUS_ERROR Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect). [1:1] read-write DST_BUS_ERROR Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect). [2:2] read-write SRC_MISAL Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect). [3:3] read-write DST_MISAL Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect). [4:4] read-write CURR_PTR_NULL Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect). [5:5] read-write ACTIVE_CH_DISABLED Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect). [6:6] read-write DESCR_BUS_ERROR Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect). [7:7] read-write INTR_MASK Interrupt mask 0x88 32 read-write 0x0 0xFF COMPLETION Mask for INTR.COMPLETION interrupt. [0:0] read-write SRC_BUS_ERROR Mask for INTR.SRC_BUS_ERROR interrupt. [1:1] read-write DST_BUS_ERROR Mask for INTR.DST_BUS_ERROR interrupt. [2:2] read-write SRC_MISAL Mask for INTR.SRC_MISAL interrupt. [3:3] read-write DST_MISAL Mask for INTR.DST_MISAL interrupt. [4:4] read-write CURR_PTR_NULL Mask for INTR.CURR_PTR_NULL interrupt. [5:5] read-write ACTIVE_CH_DISABLED Mask for INTR.ACTIVE_CH_DISABLED interrupt. [6:6] read-write DESCR_BUS_ERROR Mask for INTR.DESCR_BUS_ERROR interrupt. [7:7] read-write INTR_MASKED Interrupt masked 0x8C 32 read-only 0x0 0xFF COMPLETION Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields. [0:0] read-only SRC_BUS_ERROR Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields. [1:1] read-only DST_BUS_ERROR Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields. [2:2] read-only SRC_MISAL Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields. [3:3] read-only DST_MISAL Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields. [4:4] read-only CURR_PTR_NULL Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields. [5:5] read-only ACTIVE_CH_DISABLED Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields. [6:6] read-only DESCR_BUS_ERROR Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields. [7:7] read-only EFUSE EFUSE MXS40 registers 0x402C0000 0 128 registers CTL Control 0x0 32 read-write 0x0 0x80000000 ENABLED IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. [31:31] read-write CMD Command 0x10 32 read-write 0x1 0x800F1F71 BIT_DATA Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. [0:0] read-write BIT_ADDR Bit address. This field specifies a bit within a Byte. [6:4] read-write BYTE_ADDR Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). [12:8] read-write MACRO_ADDR Macro address. This field specifies an eFUSE macro. [19:16] read-write START FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. [31:31] read-write SEQ_DEFAULT Sequencer Default value 0x20 32 read-write 0x1D0000 0x7F0000 STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write SEQ_READ_CTL_0 Sequencer read control 0 0x40 32 read-write 0x80560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_1 Sequencer read control 1 0x44 32 read-write 0x540004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_2 Sequencer read control 2 0x48 32 read-write 0x560001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_3 Sequencer read control 3 0x4C 32 read-write 0x540003 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_4 Sequencer read control 4 0x50 32 read-write 0x80150001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_READ_CTL_5 Sequencer read control 5 0x54 32 read-write 0x310004 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_f [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_0 Sequencer program control 0 0x60 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_1 Sequencer program control 1 0x64 32 read-write 0x220020 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_2 Sequencer program control 2 0x68 32 read-write 0x200001 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_3 Sequencer program control 3 0x6C 32 read-write 0x310005 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_4 Sequencer program control 4 0x70 32 read-write 0x80350006 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write SEQ_PROGRAM_CTL_5 Sequencer program control 5 0x74 32 read-write 0x803D0019 0x807F03FF CYCLES Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. [9:0] read-write STROBE_A Specifies value of eFUSE control signal strobe_a [16:16] read-write STROBE_B Specifies value of eFUSEcontrol signal strobe_b [17:17] read-write STROBE_C Specifies value of eFUSE control signal strobe_c [18:18] read-write STROBE_D Specifies value of eFUSE control signal strobe_d [19:19] read-write STROBE_E Specifies value of eFUSE control signal strobe_e [20:20] read-write STROBE_F Specifies value of eFUSE control signal strobe_f [21:21] read-write STROBE_G Specifies value of eFUSE control signal strobe_g [22:22] read-write DONE When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. [31:31] read-write HSIOM High Speed IO Matrix (HSIOM) 0x40300000 0 16384 registers 15 16 PRT[%s] HSIOM port registers 0x00000000 PORT_SEL0 Port selection 0 0x0 32 read-write 0x0 0x1F1F1F1F IO0_SEL Selects connection for IO pin 0 route. [4:0] read-write GPIO GPIO controls 'out' 0 GPIO_DSI GPIO controls 'out', DSI controls 'output enable' 1 DSI_DSI DSI controls 'out' and 'output enable' 2 DSI_GPIO DSI controls 'out', GPIO controls 'output enable' 3 AMUXA Analog mux bus A 4 AMUXB Analog mux bus B 5 AMUXA_DSI Analog mux bus A, DSI control 6 AMUXB_DSI Analog mux bus B, DSI control 7 ACT_0 Active functionality 0 8 ACT_1 Active functionality 1 9 ACT_2 Active functionality 2 10 ACT_3 Active functionality 3 11 DS_0 DeepSleep functionality 0 12 DS_1 DeepSleep functionality 1 13 DS_2 DeepSleep functionality 2 14 DS_3 DeepSleep functionality 3 15 ACT_4 Active functionality 4 16 ACT_5 Active functionality 5 17 ACT_6 Active functionality 6 18 ACT_7 Active functionality 7 19 ACT_8 Active functionality 8 20 ACT_9 Active functionality 9 21 ACT_10 Active functionality 10 22 ACT_11 Active functionality 11 23 ACT_12 Active functionality 12 24 ACT_13 Active functionality 13 25 ACT_14 Active functionality 14 26 ACT_15 Active functionality 15 27 DS_4 DeepSleep functionality 4 28 DS_5 DeepSleep functionality 5 29 DS_6 DeepSleep functionality 6 30 DS_7 DeepSleep functionality 7 31 IO1_SEL Selects connection for IO pin 1 route. [12:8] read-write IO2_SEL Selects connection for IO pin 2 route. [20:16] read-write IO3_SEL Selects connection for IO pin 3 route. [28:24] read-write PORT_SEL1 Port selection 1 0x4 32 read-write 0x0 0x1F1F1F1F IO4_SEL Selects connection for IO pin 4 route. See PORT_SEL0 for connection details. [4:0] read-write IO5_SEL Selects connection for IO pin 5 route. [12:8] read-write IO6_SEL Selects connection for IO pin 6 route. [20:16] read-write IO7_SEL Selects connection for IO pin 7 route. [28:24] read-write 64 4 AMUX_SPLIT_CTL[%s] AMUX splitter cell control 0x2000 32 read-write 0x0 0x77 SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. [0:0] read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. [1:1] read-write SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. [2:2] read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. [4:4] read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. [5:5] read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. [6:6] read-write MONITOR_CTL_0 Power/Ground Monitor cell control 0 0x2200 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_1 Power/Ground Monitor cell control 1 0x2204 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_2 Power/Ground Monitor cell control 2 0x2208 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write MONITOR_CTL_3 Power/Ground Monitor cell control 3 0x220C 32 read-write 0x0 0xFFFFFFFF MONITOR_EN control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open. '1': switch closed. [31:0] read-write ALT_JTAG_EN Alternate JTAG IF selection register 0x2240 32 read-write 0x0 0x80000000 ENABLE Provides the selection for alternate JTAG IF connectivity. 0: Primary JTAG interface is selected 1: Secondary (alternate) JTAG interface is selected. This connectivity works ONLY in ACTIVE mode. [31:31] read-write GPIO GPIO port control/configuration 0x40310000 0 65536 registers 15 128 PRT[%s] GPIO port registers 0x00000000 OUT Port output data register 0x0 32 read-write 0x0 0xFF OUT0 IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' [0:0] read-write OUT1 IO output data for pin 1 [1:1] read-write OUT2 IO output data for pin 2 [2:2] read-write OUT3 IO output data for pin 3 [3:3] read-write OUT4 IO output data for pin 4 [4:4] read-write OUT5 IO output data for pin 5 [5:5] read-write OUT6 IO output data for pin 6 [6:6] read-write OUT7 IO output data for pin 7 [7:7] read-write OUT_CLR Port output data clear register 0x4 32 read-write 0x0 0xFF OUT0 IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'. [0:0] read-write OUT1 IO clear output for pin 1 [1:1] read-write OUT2 IO clear output for pin 2 [2:2] read-write OUT3 IO clear output for pin 3 [3:3] read-write OUT4 IO clear output for pin 4 [4:4] read-write OUT5 IO clear output for pin 5 [5:5] read-write OUT6 IO clear output for pin 6 [6:6] read-write OUT7 IO clear output for pin 7 [7:7] read-write OUT_SET Port output data set register 0x8 32 read-write 0x0 0xFF OUT0 IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'. [0:0] read-write OUT1 IO set output for pin 1 [1:1] read-write OUT2 IO set output for pin 2 [2:2] read-write OUT3 IO set output for pin 3 [3:3] read-write OUT4 IO set output for pin 4 [4:4] read-write OUT5 IO set output for pin 5 [5:5] read-write OUT6 IO set output for pin 6 [6:6] read-write OUT7 IO set output for pin 7 [7:7] read-write OUT_INV Port output data invert register 0xC 32 read-write 0x0 0xFF OUT0 IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0'). [0:0] read-write OUT1 IO invert output for pin 1 [1:1] read-write OUT2 IO invert output for pin 2 [2:2] read-write OUT3 IO invert output for pin 3 [3:3] read-write OUT4 IO invert output for pin 4 [4:4] read-write OUT5 IO invert output for pin 5 [5:5] read-write OUT6 IO invert output for pin 6 [6:6] read-write OUT7 IO invert output for pin 7 [7:7] read-write IN Port input state register 0x10 32 read-only 0x0 0x1FF IN0 IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. [0:0] read-only IN1 IO pin state for pin 1 [1:1] read-only IN2 IO pin state for pin 2 [2:2] read-only IN3 IO pin state for pin 3 [3:3] read-only IN4 IO pin state for pin 4 [4:4] read-only IN5 IO pin state for pin 5 [5:5] read-only IN6 IO pin state for pin 6 [6:6] read-only IN7 IO pin state for pin 7 [7:7] read-only FLT_IN Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. [8:8] read-only INTR Port interrupt status register 0x14 32 read-write 0x0 0x1FF01FF EDGE0 Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. [0:0] read-write EDGE1 Edge detect for IO pin 1 [1:1] read-write EDGE2 Edge detect for IO pin 2 [2:2] read-write EDGE3 Edge detect for IO pin 3 [3:3] read-write EDGE4 Edge detect for IO pin 4 [4:4] read-write EDGE5 Edge detect for IO pin 5 [5:5] read-write EDGE6 Edge detect for IO pin 6 [6:6] read-write EDGE7 Edge detect for IO pin 7 [7:7] read-write FLT_EDGE Edge detected on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write IN_IN0 IO pin state for pin 0 [16:16] read-only IN_IN1 IO pin state for pin 1 [17:17] read-only IN_IN2 IO pin state for pin 2 [18:18] read-only IN_IN3 IO pin state for pin 3 [19:19] read-only IN_IN4 IO pin state for pin 4 [20:20] read-only IN_IN5 IO pin state for pin 5 [21:21] read-only IN_IN6 IO pin state for pin 6 [22:22] read-only IN_IN7 IO pin state for pin 7 [23:23] read-only FLT_IN_IN Filtered pin state for pin selected by INTR_CFG.FLT_SEL [24:24] read-only INTR_MASK Port interrupt mask register 0x18 32 read-write 0x0 0x1FF EDGE0 Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled [0:0] read-write EDGE1 Masks edge interrupt on IO pin 1 [1:1] read-write EDGE2 Masks edge interrupt on IO pin 2 [2:2] read-write EDGE3 Masks edge interrupt on IO pin 3 [3:3] read-write EDGE4 Masks edge interrupt on IO pin 4 [4:4] read-write EDGE5 Masks edge interrupt on IO pin 5 [5:5] read-write EDGE6 Masks edge interrupt on IO pin 6 [6:6] read-write EDGE7 Masks edge interrupt on IO pin 7 [7:7] read-write FLT_EDGE Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_MASKED Port interrupt masked status register 0x1C 32 read-only 0x0 0x1FF EDGE0 Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [0:0] read-only EDGE1 Edge detected and masked on IO pin 1 [1:1] read-only EDGE2 Edge detected and masked on IO pin 2 [2:2] read-only EDGE3 Edge detected and masked on IO pin 3 [3:3] read-only EDGE4 Edge detected and masked on IO pin 4 [4:4] read-only EDGE5 Edge detected and masked on IO pin 5 [5:5] read-only EDGE6 Edge detected and masked on IO pin 6 [6:6] read-only EDGE7 Edge detected and masked on IO pin 7 [7:7] read-only FLT_EDGE Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-only INTR_SET Port interrupt set register 0x20 32 read-write 0x0 0x1FF EDGE0 Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set [0:0] read-write EDGE1 Sets edge detect interrupt for IO pin 1 [1:1] read-write EDGE2 Sets edge detect interrupt for IO pin 2 [2:2] read-write EDGE3 Sets edge detect interrupt for IO pin 3 [3:3] read-write EDGE4 Sets edge detect interrupt for IO pin 4 [4:4] read-write EDGE5 Sets edge detect interrupt for IO pin 5 [5:5] read-write EDGE6 Sets edge detect interrupt for IO pin 6 [6:6] read-write EDGE7 Sets edge detect interrupt for IO pin 7 [7:7] read-write FLT_EDGE Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL [8:8] read-write INTR_CFG Port interrupt configuration register 0x40 32 read-write 0x0 0x1FFFFF EDGE0_SEL Sets which edge will trigger an IRQ for IO pin 0 [1:0] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 EDGE1_SEL Sets which edge will trigger an IRQ for IO pin 1 [3:2] read-write EDGE2_SEL Sets which edge will trigger an IRQ for IO pin 2 [5:4] read-write EDGE3_SEL Sets which edge will trigger an IRQ for IO pin 3 [7:6] read-write EDGE4_SEL Sets which edge will trigger an IRQ for IO pin 4 [9:8] read-write EDGE5_SEL Sets which edge will trigger an IRQ for IO pin 5 [11:10] read-write EDGE6_SEL Sets which edge will trigger an IRQ for IO pin 6 [13:12] read-write EDGE7_SEL Sets which edge will trigger an IRQ for IO pin 7 [15:14] read-write FLT_EDGE_SEL Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL [17:16] read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 FLT_SEL Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. [20:18] read-write CFG Port configuration register 0x44 32 read-write 0x0 0xFFFFFFFF DRIVE_MODE0 The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. [2:0] read-write HIGHZ Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance 0 RSVD N/A 1 PULLUP Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up 2 PULLDOWN Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down 3 OD_DRIVESLOW Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 4 OD_DRIVESHIGH Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 5 STRONG Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance 6 PULLUP_DOWN Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up 7 IN_EN0 Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled [3:3] read-write DRIVE_MODE1 The GPIO drive mode for IO pin 1 [6:4] read-write IN_EN1 Enables the input buffer for IO pin 1 [7:7] read-write DRIVE_MODE2 The GPIO drive mode for IO pin 2 [10:8] read-write IN_EN2 Enables the input buffer for IO pin 2 [11:11] read-write DRIVE_MODE3 The GPIO drive mode for IO pin 3 [14:12] read-write IN_EN3 Enables the input buffer for IO pin 3 [15:15] read-write DRIVE_MODE4 The GPIO drive mode for IO pin4 [18:16] read-write IN_EN4 Enables the input buffer for IO pin 4 [19:19] read-write DRIVE_MODE5 The GPIO drive mode for IO pin 5 [22:20] read-write IN_EN5 Enables the input buffer for IO pin 5 [23:23] read-write DRIVE_MODE6 The GPIO drive mode for IO pin 6 [26:24] read-write IN_EN6 Enables the input buffer for IO pin 6 [27:27] read-write DRIVE_MODE7 The GPIO drive mode for IO pin 7 [30:28] read-write IN_EN7 Enables the input buffer for IO pin 7 [31:31] read-write CFG_IN Port input buffer configuration register 0x48 32 read-write 0x0 0xFF VTRIP_SEL0_0 Configures the pin 0 input buffer mode (trip points and hysteresis) [0:0] read-write CMOS PSoC 6:: Input buffer compatible with CMOS and I2C interfaces Traveo II: Full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 0 TTL PSoC 6:: Input buffer compatible with TTL and MediaLB interfaces Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 1 VTRIP_SEL1_0 Configures the pin 1 input buffer mode (trip points and hysteresis) [1:1] read-write VTRIP_SEL2_0 Configures the pin 2 input buffer mode (trip points and hysteresis) [2:2] read-write VTRIP_SEL3_0 Configures the pin 3 input buffer mode (trip points and hysteresis) [3:3] read-write VTRIP_SEL4_0 Configures the pin 4 input buffer mode (trip points and hysteresis) [4:4] read-write VTRIP_SEL5_0 Configures the pin 5 input buffer mode (trip points and hysteresis) [5:5] read-write VTRIP_SEL6_0 Configures the pin 6 input buffer mode (trip points and hysteresis) [6:6] read-write VTRIP_SEL7_0 Configures the pin 7 input buffer mode (trip points and hysteresis) [7:7] read-write CFG_OUT Port output buffer configuration register 0x4C 32 read-write 0x0 0xFFFF00FF SLOW0 Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate [0:0] read-write SLOW1 Enables slow slew rate for IO pin 1 [1:1] read-write SLOW2 Enables slow slew rate for IO pin 2 [2:2] read-write SLOW3 Enables slow slew rate for IO pin 3 [3:3] read-write SLOW4 Enables slow slew rate for IO pin 4 [4:4] read-write SLOW5 Enables slow slew rate for IO pin 5 [5:5] read-write SLOW6 Enables slow slew rate for IO pin 6 [6:6] read-write SLOW7 Enables slow slew rate for IO pin 7 [7:7] read-write DRIVE_SEL0 Sets the GPIO drive strength for IO pin 0 [17:16] read-write DRIVE_SEL_ZERO Please refer to architecture TRM section I/O System 0 DRIVE_SEL_ONE Please refer to architecture TRM section I/O System 1 DRIVE_SEL_TWO Please refer to architecture TRM section I/O System 2 DRIVE_SEL_THREE Please refer to architecture TRM section I/O System 3 DRIVE_SEL1 Sets the GPIO drive strength for IO pin 1 [19:18] read-write DRIVE_SEL2 Sets the GPIO drive strength for IO pin 2 [21:20] read-write DRIVE_SEL3 Sets the GPIO drive strength for IO pin 3 [23:22] read-write DRIVE_SEL4 Sets the GPIO drive strength for IO pin 4 [25:24] read-write DRIVE_SEL5 Sets the GPIO drive strength for IO pin 5 [27:26] read-write DRIVE_SEL6 Sets the GPIO drive strength for IO pin 6 [29:28] read-write DRIVE_SEL7 Sets the GPIO drive strength for IO pin 7 [31:30] read-write CFG_SIO Port SIO configuration register 0x50 32 read-write 0x0 0xFFFFFFFF VREG_EN01 Selects the output buffer mode: '0': Unregulated output buffer '1': Regulated output buffer The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. [0:0] read-write IBUF_SEL01 Selects the input buffer mode: 0: Singled ended input buffer 1: Differential input buffer [1:1] read-write VTRIP_SEL01 Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): '0': Input buffer functions as a CMOS input buffer. '1': Input buffer functions as a TTL input buffer. In differential input buffer mode (IBUF_SEL = '1') '0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) '1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) [2:2] read-write VREF_SEL01 Selects reference voltage (Vref) trip-point of the input buffer: '0': Trip-point reference from pin_ref '1': Trip-point reference of SRSS internal reference Vref (1.2 V) '2': Trip-point reference of AMUXBUS_A '3': Trip-point reference of AMUXBUS_B [4:3] read-write VOH_SEL01 Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). '0': Voh = 1*reference; e.g. reference at 1.2V -> Voh = 1.2V '1': Voh = 1.25*reference; e.g. reference at 1.2V -> Voh = 1.5V '2': Voh = 1.49*reference; e.g. reference at 1.2V -> Voh = ~1.8V '3': Voh = 1.67*reference; e.g. reference at 1.2V -> Voh = 2V '4': Voh = 2.08*reference; e.g. reference at 1.2V -> Voh = 2.5V '5': Voh = 2.5*reference; e.g. reference at 1.2V -> Voh = 3V '6': Voh = 2.78*reference; e.g. reference at 1.2V -> Voh = ~3.3V '7': Voh = 4.16*reference; e.g. reference at 1.2V -> Voh = 5.0V Note: The upper value on Voh is limited to Vddio - 400mV [7:5] read-write VREG_EN23 See corresponding definition for IO pins 0 and 1 [8:8] read-write IBUF_SEL23 See corresponding definition for IO pins 0 and 1 [9:9] read-write VTRIP_SEL23 See corresponding definition for IO pins 0 and 1 [10:10] read-write VREF_SEL23 See corresponding definition for IO pins 0 and 1 [12:11] read-write VOH_SEL23 See corresponding definition for IO pins 0 and 1 [15:13] read-write VREG_EN45 See corresponding definition for IO pins 0 and 1 [16:16] read-write IBUF_SEL45 See corresponding definition for IO pins 0 and 1 [17:17] read-write VTRIP_SEL45 See corresponding definition for IO pins 0 and 1 [18:18] read-write VREF_SEL45 See corresponding definition for IO pins 0 and 1 [20:19] read-write VOH_SEL45 See corresponding definition for IO pins 0 and 1 [23:21] read-write VREG_EN67 See corresponding definition for IO pins 0 and 1 [24:24] read-write IBUF_SEL67 See corresponding definition for IO pins 0 and 1 [25:25] read-write VTRIP_SEL67 See corresponding definition for IO pins 0 and 1 [26:26] read-write VREF_SEL67 See corresponding definition for IO pins 0 and 1 [28:27] read-write VOH_SEL67 See corresponding definition for IO pins 0 and 1 [31:29] read-write CFG_IN_AUTOLVL Port input buffer AUTOLVL configuration register 0x58 32 read-write 0x0 0xFF VTRIP_SEL0_1 Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: {CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: 0,0: CMOS 0,1: TTL 1,0: input buffer is compatible with automotive. 1,1: input buffer is compatible with automotvie [0:0] read-write CMOS_OR_TTL Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. 0 AUTO Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. 1 VTRIP_SEL1_1 Input buffer compatible with automotive (elevated Vil) interfaces. [1:1] read-write VTRIP_SEL2_1 Input buffer compatible with automotive (elevated Vil) interfaces. [2:2] read-write VTRIP_SEL3_1 Input buffer compatible with automotive (elevated Vil) interfaces. [3:3] read-write VTRIP_SEL4_1 Input buffer compatible with automotive (elevated Vil) interfaces. [4:4] read-write VTRIP_SEL5_1 Input buffer compatible with automotive (elevated Vil) interfaces. [5:5] read-write VTRIP_SEL6_1 Input buffer compatible with automotive (elevated Vil) interfaces. [6:6] read-write VTRIP_SEL7_1 Input buffer compatible with automotive (elevated Vil) interfaces. [7:7] read-write INTR_CAUSE0 Interrupt port cause register 0 0x4000 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE1 Interrupt port cause register 1 0x4004 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE2 Interrupt port cause register 2 0x4008 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only INTR_CAUSE3 Interrupt port cause register 3 0x400C 32 read-only 0x0 0xFFFFFFFF PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt [31:0] read-only VDD_ACTIVE Extern power supply detection register 0x4010 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. '0': Supply is not present '1': Supply is present When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: 0: vbackup, 1: vddio_0, 2: vddio_1, 3: vddio_a, 4: vddio_r, 5: vddusb' [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) [31:31] read-only VDD_INTR Supply detection interrupt register 0x4014 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Supply state change detected. '0': No change to supply detected '1': Change to supply detected [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. [31:31] read-write VDD_INTR_MASK Supply detection interrupt mask register 0x4018 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Masks supply interrupt on VDDIO. '0': VDDIO interrupt forwarding disabled '1': VDDIO interrupt forwarding enabled [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write VDD_INTR_MASKED Supply detection interrupt masked register 0x401C 32 read-only 0x0 0xC000FFFF VDDIO_ACTIVE Supply transition detected AND masked '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU [15:0] read-only VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-only VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-only VDD_INTR_SET Supply detection interrupt set register 0x4020 32 read-write 0x0 0xC000FFFF VDDIO_ACTIVE Sets supply interrupt. '0': Interrupt state not affected '1': Interrupt set [15:0] read-write VDDA_ACTIVE Same as VDDIO_ACTIVE for the analog supply VDDA. [30:30] read-write VDDD_ACTIVE Same as VDDIO_ACTIVE for the digital supply VDDD. [31:31] read-write SMARTIO Programmable IO configuration 0x40320000 0 65536 registers 10 256 PRT[%s] Programmable IO port registers 0x00000000 CTL Control register 0x0 32 read-write 0x2001400 0x82001F00 BYPASS Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. '0': No bypass (programmable SMARTIO fabric is exposed). '1': Bypass (programmable SMARTIOIO fabric is hidden). [7:0] read-write CLOCK_SRC Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: '0': io_data_in[0]/'1'. ... '7': io_data_in[7]/'1'. '8': chip_data[0]/'1'. ... '15': chip_data[7]/'1'. '16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. '19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. '20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. '31': asynchronous mode/'1'. Select this when clockless operation is configured. NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. [12:8] read-write HLD_OVR IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: '0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). '1': The SMARTIO controls the IO cel hold override functionality: - In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. - In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). [24:24] read-write PIPELINE_EN Enable for pipeline register: '0': Disabled (register is bypassed). '1': Enabled. [25:25] read-write ENABLED Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: '0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. If the IP is disabled: - The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. - The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. '1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. [31:31] read-write SYNC_CTL Synchronization control register 0x10 32 read-write 0x0 0x0 IO_SYNC_EN Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. '0': No synchronization. '1': Synchronization. [7:0] read-write CHIP_SYNC_EN Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. '0': No synchronization. '1': Synchronization. [15:8] read-write 8 4 LUT_SEL[%s] LUT component input selection 0x20 32 read-write 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). [3:0] read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). [11:8] read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. [19:16] read-write 8 4 LUT_CTL[%s] LUT component control register 0x40 32 read-write 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). [7:0] read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable & (tr1_in ^ LUT[2]) & LUT[3]. clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' [9:8] read-write DU_SEL Data unit component input selection 0xC0 32 read-write 0x0 0x0 DU_TR0_SEL Data unit input signal 'tr0_in' source selection: '0': Constant '0'. '1': Constant '1'. '2': Data unit output. '10-3': LUT 7 - 0 outputs. Otherwise: Undefined. [3:0] read-write DU_TR1_SEL Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. [11:8] read-write DU_TR2_SEL Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. [19:16] read-write DU_DATA0_SEL Data unit input data 'data0_in' source selection: '0': Constant '0'. '1': chip_data[7:0]. '2': io_data_in[7:0]. '3': DATA.DATA MMIO register field. [25:24] read-write DU_DATA1_SEL Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. [29:28] read-write DU_CTL Data unit component control register 0xC4 32 read-write 0x0 0x0 DU_SIZE Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. [2:0] read-write DU_OPC Data unit opcode specifies the data unit operation: '1': INCR '2': DECR '3': INCR_WRAP '4': DECR_WRAP '5': INCR_DECR '6': INCR_DECR_WRAP '7': ROR '8': SHR '9': AND_OR '10': SHR_MAJ3 '11': SHR_EQL. Otherwise: Undefined. [11:8] read-write DATA Data register 0xF0 32 read-write 0x0 0x0 DATA Data unit input data source. [7:0] read-write LPCOMP Low Power Comparators 0x40350000 0 65536 registers CONFIG LPCOMP Configuration Register 0x0 32 read-write 0x0 0xC0000000 LPREF_EN Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation. [30:30] read-write ENABLED - 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only) - 1: IP enabled [31:31] read-write STATUS LPCOMP Status Register 0x4 32 read-only 0x0 0x10001 OUT0 Current output value of the comparator 0. [0:0] read-only OUT1 Current output value of the comparator 1. [16:16] read-only INTR LPCOMP Interrupt request register 0x10 32 read-write 0x0 0x3 COMP0 Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. [0:0] read-write COMP1 Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. [1:1] read-write INTR_SET LPCOMP Interrupt set register 0x14 32 read-write 0x0 0x3 COMP0 Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write COMP1 Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write INTR_MASK LPCOMP Interrupt request mask 0x18 32 read-write 0x0 0x3 COMP0_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write COMP1_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write INTR_MASKED LPCOMP Interrupt request masked 0x1C 32 read-only 0x0 0x3 COMP0_MASKED Logical and of corresponding request and mask bits. [0:0] read-only COMP1_MASKED Logical and of corresponding request and mask bits. [1:1] read-only CMP0_CTRL Comparator 0 control Register 0x40 32 read-write 0x0 0xCE3 MODE0 Operating mode for the comparator [1:0] read-write OFF Off 0 ULP Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. 1 LP Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. 2 NORMAL Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. 3 HYST0 Add 30mV hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis [5:5] read-write INTTYPE0 Sets which edge will trigger an IRQ [7:6] read-write DISABLE Disabled, no interrupts will be detected 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 DSI_BYPASS0 Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. [10:10] read-write DSI_LEVEL0 Synchronous comparator DSI (trigger) output : 0=pulse, 1=level [11:11] read-write CMP0_SW Comparator 0 switch control 0x50 32 read-write 0x0 0xF7 CMP0_IP0 Comparator 0 positive terminal isolation switch to GPIO [0:0] read-write CMP0_AP0 Comparator 0 positive terminal switch to amuxbusA [1:1] read-write CMP0_BP0 Comparator 0 positive terminal switch to amuxbusB [2:2] read-write CMP0_IN0 Comparator 0 negative terminal isolation switch to GPIO [4:4] read-write CMP0_AN0 Comparator 0 negative terminal switch to amuxbusA [5:5] read-write CMP0_BN0 Comparator 0 negative terminal switch to amuxbusB [6:6] read-write CMP0_VN0 Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set) [7:7] read-write CMP0_SW_CLEAR Comparator 0 switch control clear 0x54 32 read-write 0x0 0xF7 CMP0_IP0 see corresponding bit in CMP0_SW [0:0] read-write CMP0_AP0 see corresponding bit in CMP0_SW [1:1] read-write CMP0_BP0 see corresponding bit in CMP0_SW [2:2] read-write CMP0_IN0 see corresponding bit in CMP0_SW [4:4] read-write CMP0_AN0 see corresponding bit in CMP0_SW [5:5] read-write CMP0_BN0 see corresponding bit in CMP0_SW [6:6] read-write CMP0_VN0 see corresponding bit in CMP0_SW [7:7] read-write CMP1_CTRL Comparator 1 control Register 0x80 32 read-write 0x0 0xCE3 MODE1 Operating mode for the comparator [1:0] read-write OFF Off 0 ULP Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. 1 LP Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. 2 NORMAL Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. 3 HYST1 Add 30mV hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis [5:5] read-write INTTYPE1 Sets which edge will trigger an IRQ [7:6] read-write DISABLE Disabled, no interrupts will be detected 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 DSI_BYPASS1 Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. [10:10] read-write DSI_LEVEL1 Synchronous comparator DSI (trigger) output : 0=pulse, 1=level [11:11] read-write CMP1_SW Comparator 1 switch control 0x90 32 read-write 0x0 0xF7 CMP1_IP1 Comparator 1 positive terminal isolation switch to GPIO [0:0] read-write CMP1_AP1 Comparator 1 positive terminal switch to amuxbusA [1:1] read-write CMP1_BP1 Comparator 1 positive terminal switch to amuxbusB [2:2] read-write CMP1_IN1 Comparator 1 negative terminal isolation switch to GPIO [4:4] read-write CMP1_AN1 Comparator 1 negative terminal switch to amuxbusA [5:5] read-write CMP1_BN1 Comparator 1 negative terminal switch to amuxbusB [6:6] read-write CMP1_VN1 Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set) [7:7] read-write CMP1_SW_CLEAR Comparator 1 switch control clear 0x94 32 read-write 0x0 0xF7 CMP1_IP1 see corresponding bit in CMP1_SW [0:0] read-write CMP1_AP1 see corresponding bit in CMP1_SW [1:1] read-write CMP1_BP1 see corresponding bit in CMP1_SW [2:2] read-write CMP1_IN1 see corresponding bit in CMP1_SW [4:4] read-write CMP1_AN1 see corresponding bit in CMP1_SW [5:5] read-write CMP1_BN1 see corresponding bit in CMP1_SW [6:6] read-write CMP1_VN1 see corresponding bit in CMP1_SW [7:7] read-write CSD0 Capsense Controller CSD 0x40360000 0 4096 registers CONFIG Configuration and Control 0x0 32 read-write 0x4000000 0xCF0E1DF1 IREF_SEL Select Iref supply. [0:0] read-write IREF_SRSS select SRSS Iref (default) 0 IREF_PASS select PASS.AREF Iref, only available if PASS IP is on the chip. 1 FILTER_DELAY This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on. When set to 0 the digital filter is off. When set to any other value the ignoring will last for FILTER_DELAY clk_csd cycles after the start of each measurement and from the first comparator trip to the end of each measurement. [8:4] read-write SHIELD_DELAY Selects the delay by which csd_shield is delayed relative to csd_sense. [11:10] read-write OFF Delay line is off, csd_shield=csd_sense 0 D5NS Introduces a 5ns delay (typ) 1 D10NS Introduces a 10ns delay (typ) 2 D20NS Introduces a 20ns delay (typ) 3 SENSE_EN Enables the sense modulator output. 0: all switches, static or dynamic, are open and IDAC in CSD mode is off 1: switches and IDAC can be closed/on as per MMIO setting and CSD sequencer. [12:12] read-write FULL_WAVE Enables full wave cap sensing mode [17:17] read-write HALFWAVE Half Wave mode (normal). In this mode the comparator always trips in the same direction (positive or negative edge) and the same Vref, i.e. no polarity change. 0 FULLWAVE Full Wave mode. In this mode the comparator trips in opposite direction and with different Vref in each phase, i.e. the polarity flips. 1 MUTUAL_CAP Enables mutual cap sensing mode [18:18] read-write SELFCAP Self-cap mode (configure sense line as CSD_SENSE) 0 MUTUALCAP Mutual-cap mode (configure Tx line as CSD_SENSE, inverted Tx line as CSD_SHIELD and Rx Line as AMUXA). In this mode the polarity bit of the IDAC is controlled by csd_sense. 1 CSX_DUAL_CNT Enable the use of two counters for MUTUAL cap sensing mode (CSX), do not use when MUTUAL_CAP=0 [19:19] read-write ONE Use one counter for both phases (source and sink). 0 TWO Use two counters, separate count for when csd_sense is high and when csd_sense is low. 1 DSI_COUNT_SEL Select what to output on the dsi_count bus. [24:24] read-write CSD_RESULT depending on the dsi_count_val_sel input either output RESULT_VAL1.VALUE (0) or RESULT_VAL2.VALUE (1) on the dsi_count bus. Note that dsi_count_val_sel is not synchronized, i.e. it controls the mux combinatorially. 0 ADC_RESULT output ADC_RES.VIN_CNT on the dsi_count bus 1 DSI_SAMPLE_EN Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER. [25:25] read-write SAMPLE_SYNC Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1). [26:26] read-write DSI_SENSE_EN Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals. [27:27] read-write LP_MODE Select the power mode for the CSD components (REFGEN, AMBUF, CSDCMP, HSCMP): 0: High Power mode 1: Low Power mode [30:30] read-write ENABLE Master enable of the CSDv2 IP. Must be set to 1 for any CSDv2, ADC or IDAC operation to function. When 0 all analog components will be off and all switches will be open. [31:31] read-write SPARE Spare MMIO 0x4 32 read-write 0x0 0xF SPARE Spare MMIO [3:0] read-write STATUS Status Register 0x80 32 read-only 0x0 0xE CSD_SENSE Signal used to drive the Cs switches. [1:1] read-only HSCMP_OUT Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchronized) [2:2] read-only C_LT_VREF Vin < Vref 0 C_GT_VREF Vin > Vref 1 CSDCMP_OUT Output of main sensing comparator (synchronized) [3:3] read-only STAT_SEQ Current Sequencer status 0x84 32 read-only 0x0 0x70007 SEQ_STATE CSD sequencer state [2:0] read-only ADC_STATE ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started) [18:16] read-only STAT_CNTS Current status counts 0x88 32 read-only 0x0 0xFFFF NUM_CONV Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles) [15:0] read-only STAT_HCNT Current count of the HSCMP counter 0x8C 32 read-only 0x0 0xFFFF CNT Current value of HSCMP counter [15:0] read-only RESULT_VAL1 Result CSD/CSX accumulation counter value 1 0xD0 32 read-only 0x0 0xFFFFFF VALUE Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high. [15:0] read-only BAD_CONVS Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad. [23:16] read-only RESULT_VAL2 Result CSX accumulation counter value 2 0xD4 32 read-only 0x0 0xFFFF VALUE Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low. [15:0] read-only ADC_RES ADC measurement 0xE0 32 read-only 0x0 0xC001FFFF VIN_CNT Count to source/sink Cref1 + Cref2 from Vin to Vrefhi. [15:0] read-only HSCMP_POL Polarity used for IDACB for this last ADC result, 0= source, 1= sink [16:16] read-only ADC_OVERFLOW This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low. [30:30] read-only ADC_ABORT This flag is set when the ADC sequencer was aborted before tripping HSCMP. [31:31] read-only INTR CSD Interrupt Request Register 0xF0 32 read-write 0x0 0x106 SAMPLE A normal sample is complete [1:1] read-write INIT Coarse initialization complete or Sample initialization complete (the latter is typically ignored) [2:2] read-write ADC_RES ADC Result ready [8:8] read-write INTR_SET CSD Interrupt set register 0xF4 32 read-write 0x0 0x106 SAMPLE Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write INIT Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write ADC_RES Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write INTR_MASK CSD Interrupt mask register 0xF8 32 read-write 0x0 0x106 SAMPLE Mask bit for corresponding bit in interrupt request register. [1:1] read-write INIT Mask bit for corresponding bit in interrupt request register. [2:2] read-write ADC_RES Mask bit for corresponding bit in interrupt request register. [8:8] read-write INTR_MASKED CSD Interrupt masked register 0xFC 32 read-only 0x0 0x106 SAMPLE Logical and of corresponding request and mask bits. [1:1] read-only INIT Logical and of corresponding request and mask bits. [2:2] read-only ADC_RES Logical and of corresponding request and mask bits. [8:8] read-only HSCMP High Speed Comparator configuration 0x180 32 read-write 0x0 0x80000011 HSCMP_EN High Speed Comparator enable [0:0] read-write OFF Disable comparator, output is zero 0 ON On, regular operation. Note that CONFIG.LP_MODE determines the power mode level 1 HSCMP_INVERT Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT [4:4] read-write AZ_EN Auto-Zero enable, allow the Sequencer to Auto-Zero this component [31:31] read-write AMBUF Reference Generator configuration 0x184 32 read-write 0x0 0x3 PWR_MODE Amux buffer power level [1:0] read-write OFF Disable buffer 0 NORM On, normal or low power level depending on CONFIG.LP_MODE. 1 HI On, high or low power level depending on CONFIG.LP_MODE. 2 REFGEN Reference Generator configuration 0x188 32 read-write 0x0 0x9F1F71 REFGEN_EN Reference Generator Enable [0:0] read-write OFF Disable Reference Generator 0 ON On, regular operation. Note that CONFIG.LP_MODE determines the power mode level 1 BYPASS Bypass selected input reference unbuffered to Vrefhi [4:4] read-write VDDA_EN Close Vdda switch to top of resistor string (or Vrefhi?) [5:5] read-write RES_EN Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa) [6:6] read-write GAIN Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1) [12:8] read-write VREFLO_SEL Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1) [20:16] read-write VREFLO_INT Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1). [23:23] read-write CSDCMP CSD Comparator configuration 0x18C 32 read-write 0x0 0xB0000331 CSDCMP_EN CSD Comparator Enable [0:0] read-write OFF Disable comparator, output is zero 0 ON On, regular operation. Note that CONFIG.LP_MODE determines the power mode level 1 POLARITY_SEL Select which IDAC polarity to use to detect CSDCMP triggering [5:4] read-write IDACA_POL Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX 0 IDACB_POL Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common) 1 DUAL_POL Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case 2 CMP_PHASE Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap). [9:8] read-write FULL Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) 0 PHI1 Comparator is active during Phi1 only. Currently no known use-case. 1 PHI2 Comparator is active during Phi2 only. Intended usage: CSD Low EMI. 2 PHI1_2 Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave. 3 CMP_MODE Select which signal to output on dsi_sample_out. [28:28] read-write CSD CSD mode: output the filtered sample signal on dsi_sample_out 0 GP General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped. 1 FEEDBACK_MODE This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out. [29:29] read-write FLOP Use feedback from sampling flip-flop (used in most modes). 0 COMP Use feedback from comparator directly (used in single Cmod mutual cap sensing only) 1 AZ_EN Auto-Zero enable, allow the Sequencer to Auto-Zero this component [31:31] read-write SW_RES Switch Resistance configuration 0x1F0 32 read-write 0x0 0xF00FF RES_HCAV Select resistance or low EMI (slow ramp) for the HCAV switch [1:0] read-write LOW Low 0 MED Medium 1 HIGH High 2 LOWEMI Low EMI (slow ramp: 3 switches closed by fixed delay line) 3 RES_HCAG Select resistance or low EMI for the corresponding switch [3:2] read-write RES_HCBV Select resistance or low EMI for the corresponding switch [5:4] read-write RES_HCBG Select resistance or low EMI for the corresponding switch [7:6] read-write RES_F1PM Select resistance for the corresponding switch [17:16] read-write LOW Low 0 MED Medium 1 HIGH High 2 RSVD N/A 3 RES_F2PT Select resistance for the corresponding switch [19:18] read-write SENSE_PERIOD Sense clock period 0x200 32 read-write 0xC000000 0xFF70FFF SENSE_DIV The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . Note this is the base divider, clock dithering may change the actual period length. Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value. [11:0] read-write LFSR_SIZE Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set. [18:16] read-write OFF Don't use clock dithering (=spreadspectrum) (LFSR output value is zero) 0 6B 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63) 1 7B 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127) 2 9B 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511) 3 10B 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023) 4 8B 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255) 5 12B 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095) 6 LFSR_SCALE Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)). Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined. [23:20] read-write LFSR_CLEAR When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states. [24:24] read-write SEL_LFSR_MSB Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled. [25:25] read-write LFSR_BITS Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined. [27:26] read-write 2B use 2 bits: range = [-2,1] 0 3B use 3 bits: range = [-4,3] 1 4B use 4 bits: range = [-8,7] 2 5B use 5 bits: range = [-16,15] (default) 3 SENSE_DUTY Sense clock duty cycle 0x204 32 read-write 0x0 0xD0FFF SENSE_WIDTH Defines the length of the first phase of the sense clock in clk_csd cycles. A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined. Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected. [11:0] read-write SENSE_POL Polarity of the sense clock 0 = start with low phase (typical for regular negative transfer CSD) 1 = start with high phase [16:16] read-write OVERLAP_PHI1 NonOverlap or not for Phi1 (csd_sense=0). 0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO. 1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping. [18:18] read-write OVERLAP_PHI2 Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1). [19:19] read-write SW_HS_P_SEL HSCMP Pos input switch Waveform selection 0x280 32 read-write 0x0 0x11111111 SW_HMPM Set HMPM switch 0: static open 1: static closed [0:0] read-write SW_HMPT Set corresponding switch [4:4] read-write SW_HMPS Set corresponding switch [8:8] read-write SW_HMMA Set corresponding switch [12:12] read-write SW_HMMB Set corresponding switch [16:16] read-write SW_HMCA Set corresponding switch [20:20] read-write SW_HMCB Set corresponding switch [24:24] read-write SW_HMRH Set corresponding switch [28:28] read-write SW_HS_N_SEL HSCMP Neg input switch Waveform selection 0x284 32 read-write 0x0 0x77110000 SW_HCCC Set corresponding switch [16:16] read-write SW_HCCD Set corresponding switch [20:20] read-write SW_HCRH Select waveform for corresponding switch [26:24] read-write SW_HCRL Select waveform for corresponding switch [30:28] read-write SW_SHIELD_SEL Shielding switches Waveform selection 0x288 32 read-write 0x0 0x117777 SW_HCAV N/A [2:0] read-write SW_HCAG Select waveform for corresponding switch [6:4] read-write SW_HCBV N/A [10:8] read-write SW_HCBG Select waveform for corresponding switch, using csd_shield as base [14:12] read-write SW_HCCV Set corresponding switch [16:16] read-write SW_HCCG Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer. [20:20] read-write SW_AMUXBUF_SEL Amuxbuffer switches Waveform selection 0x290 32 read-write 0x0 0x11171110 SW_IRBY Set corresponding switch [4:4] read-write SW_IRLB Set corresponding switch [8:8] read-write SW_ICA Set corresponding switch [12:12] read-write SW_ICB Select waveform for corresponding switch [18:16] read-write SW_IRLI Set corresponding switch [20:20] read-write SW_IRH Set corresponding switch [24:24] read-write SW_IRL Set corresponding switch [28:28] read-write SW_BYP_SEL AMUXBUS bypass switches Waveform selection 0x294 32 read-write 0x0 0x111000 SW_BYA Set corresponding switch [12:12] read-write SW_BYB Set corresponding switch [16:16] read-write SW_CBCC Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer. [20:20] read-write SW_CMP_P_SEL CSDCMP Pos Switch Waveform selection 0x2A0 32 read-write 0x0 0x1111777 SW_SFPM Select waveform for corresponding switch [2:0] read-write SW_SFPT Select waveform for corresponding switch [6:4] read-write SW_SFPS Select waveform for corresponding switch [10:8] read-write SW_SFMA Set corresponding switch [12:12] read-write SW_SFMB Set corresponding switch [16:16] read-write SW_SFCA Set corresponding switch [20:20] read-write SW_SFCB Set corresponding switch [24:24] read-write SW_CMP_N_SEL CSDCMP Neg Switch Waveform selection 0x2A4 32 read-write 0x0 0x77000000 SW_SCRH Select waveform for corresponding switch [26:24] read-write SW_SCRL Select waveform for corresponding switch [30:28] read-write SW_REFGEN_SEL Reference Generator Switch Waveform selection 0x2A8 32 read-write 0x0 0x11110011 SW_IAIB Set corresponding switch [0:0] read-write SW_IBCB Set corresponding switch [4:4] read-write SW_SGMB Set corresponding switch [16:16] read-write SW_SGRP Set corresponding switch [20:20] read-write SW_SGRE Set corresponding switch [24:24] read-write SW_SGR Set corresponding switch [28:28] read-write SW_FW_MOD_SEL Full Wave Cmod Switch Waveform selection 0x2B0 32 read-write 0x0 0x11170701 SW_F1PM Set corresponding switch [0:0] read-write SW_F1MA Select waveform for corresponding switch [10:8] read-write SW_F1CA Select waveform for corresponding switch [18:16] read-write SW_C1CC Set corresponding switch [20:20] read-write SW_C1CD Set corresponding switch [24:24] read-write SW_C1F1 Set corresponding switch [28:28] read-write SW_FW_TANK_SEL Full Wave Csh_tank Switch Waveform selection 0x2B4 32 read-write 0x0 0x11177710 SW_F2PT Set corresponding switch [4:4] read-write SW_F2MA Select waveform for corresponding switch [10:8] read-write SW_F2CA Select waveform for corresponding switch [14:12] read-write SW_F2CB Select waveform for corresponding switch [18:16] read-write SW_C2CC Set corresponding switch [20:20] read-write SW_C2CD Set corresponding switch [24:24] read-write SW_C2F2 Set corresponding switch [28:28] read-write SW_DSI_SEL DSI output switch control Waveform selection 0x2C0 32 read-write 0x0 0xFF DSI_CSH_TANK Select waveform for dsi_csh_tank output signal 0: static open 1: static closed 2: phi1 3: phi2 4: phi1 & HSCMP 5: phi2 & HSCMP 6: HSCMP // ignores phi1/2 7: !sense // = phi1 but ignores OVERLAP_PHI1 8: phi1_delay // phi1 delayed with shield delay 9: phi2_delay // phi2 delayed with shield delay 10: !phi1 11: !phi2 12: !(phi1 & HSCMP) 13: !(phi2 & HSCMP) 14: !HSCMP // ignores phi1/2 15: sense // = phi2 but ignores OVERLAP_PHI2 [3:0] read-write DSI_CMOD Select waveform for dsi_cmod output signal [7:4] read-write IO_SEL IO output control Waveform selection 0x2D0 32 read-write 0x0 0xFFFF0FF CSD_TX_OUT Select waveform for csd_tx_out output signal [3:0] read-write CSD_TX_OUT_EN Select waveform for csd_tx_out_en output signal [7:4] read-write CSD_TX_AMUXB_EN Select waveform for csd_tx_amuxb_en output signal [15:12] read-write CSD_TX_N_OUT Select waveform for csd_tx_n_out output signal [19:16] read-write CSD_TX_N_OUT_EN Select waveform for csd_tx_n_out_en output signal [23:20] read-write CSD_TX_N_AMUXA_EN Select waveform for csd_tx_n_amuxa_en output signal [27:24] read-write SEQ_TIME Sequencer Timing 0x300 32 read-write 0x0 0xFF AZ_TIME Define Auto-Zero time in csd_sense cycles -1. [7:0] read-write SEQ_INIT_CNT Sequencer Initial conversion and sample counts 0x310 32 read-write 0x0 0xFFFF CONV_CNT Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped. [15:0] read-write SEQ_NORM_CNT Sequencer Normal conversion and sample counts 0x314 32 read-write 0x0 0xFFFF CONV_CNT Number of conversion per sample, if set to 0 the Sample_norm state will be skipped. Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1). Note for CSDv1 Sample window size = PERIOD [15:0] read-write ADC_CTL ADC Control 0x320 32 read-write 0x0 0x300FF ADC_TIME ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2 [7:0] read-write ADC_MODE Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state [17:16] read-write OFF No ADC measurement 0 VREF_CNT Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB 1 VREF_BY2_CNT Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking) 2 VIN_CNT Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi. 3 SEQ_START Sequencer start 0x340 32 read-write 0x0 0x31B START Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode). [0:0] read-write SEQ_MODE 0 = regular CSD scan + optional ADC 1 = coarse initialization, the Sequencer will go to the INIT_COARSE state. [1:1] read-write ABORT When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0. [3:3] read-write DSI_START_EN When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer. [4:4] read-write AZ0_SKIP When set the AutoZero_0 state will be skipped [8:8] read-write AZ1_SKIP When set the AutoZero_1 state will be skipped [9:9] read-write IDACA IDACA Configuration 0x400 32 read-write 0x0 0x3EF0FFF VAL Current value setting for this IDAC (7 bits). [6:0] read-write POL_DYN Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. [7:7] read-write STATIC Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. 0 DYNAMIC Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. 1 POLARITY Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_MODE==CSD also mixed with the CSD configuration and operation. However in mutual cap mode with one IDAC (config.mutual_cap=1 & config.csx_dual_idac=0) the polarity of the IDAC is controlled by csd_sense. [9:8] read-write VSSA_SRC Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. 0 VDDA_SNK Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. 1 SENSE The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. 2 SENSE_INV The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. 3 BAL_MODE Balancing mode: only applies to legs configured as CSD. [11:10] read-write FULL enabled from start of Phi2 until disabled by CSDCMP. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) 0 PHI1 enabled from start of Phi1 and disabled by CSDCMP or at end of Phi1. Enables dual IDAC CSX or Full-Wave, one for sourcing and the other for sinking. 1 PHI2 enabled from start of Phi2 and disabled by CSDCMP or at end of Phi2. Intended usage: CSD Low EMI or dual IDAC CSX or Full-Wave. 2 PHI1_2 enabled from start of both Phi1 and Phi2 and disabled by CSDCMP or at end of Phi1 or Phi2 (if non-overlap enabled). Intended usage: single IDAC CSX, or Full-Wave. 3 LEG1_MODE Controls the usage mode of LEG1 and the Polarity bit [17:16] read-write GP_STATIC General Purpose static mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. 0 GP General Purpose dynamic mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. 1 CSD_STATIC CSD static mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG1 is controlled by LEG1_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. 2 CSD CSD dynamic mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In thoses states LEG1 is controlled by LEG1_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. 3 LEG2_MODE Controls the usage mode of LEG2 [19:18] read-write GP_STATIC General Purpose static mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. 0 GP General Purpose dynamic mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. 1 CSD_STATIC CSD static mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg2 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer. 2 CSD CSD dynamic mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). In addition leg2 enable can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled. 3 DSI_CTRL_EN Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled). 0: no DSI control IDACA_POLARITY = IDACA.POLARITY IDACA_LEG1_EN = IDACA.LEG1_EN IDACA_LEG2_EN = IDACA.LEG2_EN 1: Mix MMIO with DSI control IDACA_POLARITY = IDACA.POLARITY EXOR dsi_idaca_pol IDACA_LEG1_EN = IDACA.LEG1_EN AND dsi_idaca_leg1_en IDACA_LEG2_EN = IDACA.LEG2_EN AND dsi_idaca_leg2_en [21:21] read-write RANGE IDAC multiplier [23:22] read-write IDAC_LO 1 LSB = 37.5 nA 0 IDAC_MED 1 LSB = 300 nA 1 IDAC_HI 1 LSB = 2400 nA 2 LEG1_EN output enable for leg 1 to CSDBUSA [24:24] read-write LEG2_EN output enable for leg 2 to CSDBUSA [25:25] read-write IDACB IDACB Configuration 0x500 32 read-write 0x0 0x7EF0FFF VAL Current value setting for this IDAC (7 bits). [6:0] read-write POL_DYN Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP. [7:7] read-write STATIC Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time. 0 DYNAMIC Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power. 1 POLARITY Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_EN==1 and LEG1_MODE==CSD also mixed with the CSD configuration and operation. In mutual cap mode however (see config.mutual_cap) the polarity of the IDAC is controlled by csd_sense. If LEG3_EN=1 (the other two legs must be off) then the ADC sequencer controls the IDACB polarity, optionally mixed with DSI. [9:8] read-write VSSA_SRC Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source current. 0 VDDA_SNK Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current. 1 SENSE The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. 2 SENSE_INV The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC. 3 BAL_MODE same as corresponding IDACA Balancing mode [11:10] read-write FULL same as corresponding IDACA Balancing mode 0 PHI1 same as corresponding IDACA Balancing mode 1 PHI2 same as corresponding IDACA Balancing mode 2 PHI1_2 same as corresponding IDACA Balancing mode 3 LEG1_MODE Controls the usage mode of LEG1 and the Polarity bit [17:16] read-write GP_STATIC same as corresponding IDACA.LEG1_MODE 0 GP same as corresponding IDACA.LEG1_MODE 1 CSD_STATIC same as corresponding IDACA.LEG1_MODE 2 CSD same as corresponding IDACA.LEG1_MODE 3 LEG2_MODE Controls the usage mode of LEG2 [19:18] read-write GP_STATIC same as corresponding IDACA.LEG2_MODE 0 GP same as corresponding IDACA.LEG2_MODE 1 CSD_STATIC same as corresponding IDACA.LEG2_MODE 2 CSD same as corresponding IDACA.LEG2_MODE 3 DSI_CTRL_EN Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled) 0: no DSI control IDACB_POLARITY = IDACB.POLARITY IDACB_LEG1_EN = IDACB.LEG1_EN IDACB_LEG2_EN = IDACB.LEG2_EN IDACB_LEG3_EN = IDACB.LEG3_EN 1: Mix MMIO with DSI control IDACB_POLARITY = IDACB.POLARITY EXOR dsi_idacb_pol IDACB_LEG1_EN = IDACB.LEG1_EN AND dsi_idacb_leg1_en IDACB_LEG2_EN = IDACB.LEG2_EN AND dsi_idacb_leg2_en IDACB_LEG3_EN = IDACB.LEG3_EN AND dsi_idacb_leg3_en [21:21] read-write RANGE IDAC multiplier [23:22] read-write IDAC_LO 1 LSB = 37.5 nA 0 IDAC_MED 1 LSB = 300 nA 1 IDAC_HI 1 LSB = 2400 nA 2 LEG1_EN output enable for leg 1 to CSDBUSB or CSDBUSA [24:24] read-write LEG2_EN output enable for leg 2 to CSDBUSB or CSDBUSA [25:25] read-write LEG3_EN output enable for leg3 to CSDBUSC, only allowed when RANGE = IDAC_LO. When this bit is set both other legs should be off. Note that leg3 can only be used for ADC mode, not GP mode. Which means that leg3 can only be on when the ADC Sequencer is in the ADC_measure or Calib_measure state. In those states leg3 is controlled by the ADC configuration and the HSCMP output. In addition this leg3 enable bit can optionally be mixed with DSI (see DSI_CTRL_EN). When LEG3_EN=1 also the IDACB polarity is controlled by the ADC sequencer. [26:26] read-write TCPWM0 Timer/Counter/PWM TCPWM 0x40380000 0 131072 registers 2 32768 GRP[%s] Group of counters 0x00000000 8 128 CNT[%s] Timer/Counter/PWM Counter Module 0x00000000 CTRL Counter control register 0x0 32 read-write 0xF0 0xC73737FF AUTO_RELOAD_CC0 Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. Timer, QUAD, SR modes: '0': never switch. '1': switch on a compare match 0 event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. [0:0] read-write AUTO_RELOAD_CC1 Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. Timer, QUAD, SR modes: '0': never switch. '1': switch on a compare match 1 event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. [1:1] read-write AUTO_RELOAD_PERIOD Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event. In QUAD mode, QUAD_RANGE0_CMP range mode this field is used to select the index / wrap-around capture function. '0': Captures on index (reload) event. The counter value is copied to the PERIOD register on an index (reload) event. '1': Captures when COUNTER equals 0 or 0xffff. The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff. [2:2] read-write AUTO_RELOAD_LINE_SEL Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event. [3:3] read-write CC0_MATCH_UP_EN Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. '0': compare match 0 event generation disabled when counting up '1': compare match 0 event generation enabled when counting up This field has a function in PWM and PWM_DT modes only. [4:4] read-write CC0_MATCH_DOWN_EN Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. '0': compare match 0 event generation disabled when counting down '1': compare match 0 event generation enabled when counting down This field has a function in PWM and PWM_DT modes only. [5:5] read-write CC1_MATCH_UP_EN Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. '0': compare match 1 event generation disabled when counting up '1': compare match 1 event generation enabled when counting up This field has a function in PWM and PWM_DT modes only. [6:6] read-write CC1_MATCH_DOWN_EN Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. '0': compare match 1 event generation disabled when counting down '1': compare match 1 event generation enabled when counting down This field has a function in PWM and PWM_DT modes only. [7:7] read-write PWM_IMM_KILL Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter'). '0': synchronous kill activation. Deactivates the 'dt_line_out' and 'dt_line_compl_out' signals with the next module clock ('active count' pre-scaled 'clk_counter'). '1': immediate kill activation. Immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals. This field has a function in PWM, PWM_DT and PWM_PR modes only. [8:8] read-write PWM_STOP_ON_KILL Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only. [9:9] read-write PWM_SYNC_KILL Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. [10:10] read-write PWM_DISABLE_MODE Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped. Note: The output signal of this selection can be further modified by the immediate kill logic and line_out polarity settings (CTRL.QUAD_ENCODING_MODE). [13:12] read-write Z The behavior is the same is in previous mxtcpwm (version 1). When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are NOT driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the TCPWM output 'line_out_en' to 0. When the counter is stopped upon a stop event the PWM outputs are deactivated (to the polarity defined by CTL.QUAD_ENCODING_MODE). 0 RETAIN When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM outputs are retained (keep their previous levels). While the counter is disabled or stopped the PWM outputs can be changed via LINE_SEL (when parameter GRP_SMC_PRESENT = 1). 1 L When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '0' and the PWM output 'line_compl_out' is driven as a fixed '1'. 2 H When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '1' and the PWM output 'line_compl_out' is driven as a fixed '0'. 3 UP_DOWN_MODE Determines counter direction. In QUAD mode this field acts as QUAD_RANGE_MODE field selecting between different counter range, reload value and compare / capture behavior. [17:16] read-write COUNT_UP Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. 0 COUNT_DOWN Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 1 COUNT_UPDN1 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. 2 COUNT_UPDN2 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). 3 ONE_SHOT When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. [18:18] read-write QUAD_ENCODING_MODE In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode. In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUAD_ENCODING_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUAD_ENCODING_MODE[1]. [21:20] read-write X1 X1 encoding (QUAD mode) This encoding is identical with an up / down counting functionality of the following way: Rising edges of input phiA increment or decrement the counter depending on the state of input phiB (direction input). 0 X2 X2 encoding (QUAD mode) 1 X4 X4 encoding (QUAD mode) 2 UP_DOWN Up / Down rotary counting mode. Input phiA increments the counter, input phiB decrements the counter. The trigger edge detection settings apply. 3 MODE Counter mode. [26:24] read-write TIMER Timer mode 0 RSVD1 N/A 1 CAPTURE Capture mode 2 QUAD Quadrature mode Different encoding modes can be selected by QUAD_ENCODING_MODE including up/down count functionality. Different counter range, reload value and capture behavior can be selected by QUAD_RANGE_MODE (overloaded field UP_DOWN_MODE). 3 PWM Pulse width modulation (PWM) mode 4 PWM_DT PWM with deadtime insertion mode 5 PWM_PR Pseudo random pulse width modulation 6 SR Shift register mode. 7 DBG_FREEZE_EN Specifies the counter behavior in debug mode. '0': The counter operation continues in debug mode. '1': The counter operation freezes in debug mode. [30:30] read-write ENABLED Counter enable. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_IN_SEL, TR_IN_EDGE_SEL, TR_PWM_CTRL and TR_OUT_SEL register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ('tr_out0' and tr_out1'). - the counter's line outputs ('line_out' and 'line_compl_out'). [31:31] read-write STATUS Counter status register 0x4 32 read-only 0x20 0xFFFF8FF1 DOWN When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. [0:0] read-only TR_CAPTURE0 Indicates the actual level of the selected capture 0 trigger. [4:4] read-only TR_COUNT Indicates the actual level of the selected count trigger. [5:5] read-only TR_RELOAD Indicates the actual level of the selected reload trigger. [6:6] read-only TR_STOP Indicates the actual level of the selected stop trigger. [7:7] read-only TR_START Indicates the actual level of the selected start trigger. [8:8] read-only TR_CAPTURE1 Indicates the actual level of the selected capture 1 trigger. [9:9] read-only LINE_OUT Indicates the actual level of the PWM line output signal. [10:10] read-only LINE_COMPL_OUT Indicates the actual level of the complementary PWM line output signal. [11:11] read-only RUNNING When '0', the counter is NOT running. When '1', the counter is running. This field is used to indicate that the counter is running after a start/reload event and that the counter is stopped after a stop event. When a running counter operation is paused in debug state (see CTRL.DBG_PAUSE) then the RUNNING bit is still '1'. [15:15] read-only DT_CNT_L Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter). In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. [23:16] read-only DT_CNT_H High byte of 16-bit dead time counter. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8bit wide and the only the field DT_CNT_L is used as dead time counter. [31:24] read-only COUNTER Counter count register 0x8 32 read-write 0x0 0xFFFFFFFF COUNTER 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. [31:0] read-write CC0 Counter compare/capture 0 register 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. [31:0] read-write CC0_BUFF Counter buffered compare/capture 0 register 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC Additional buffer for counter CC register. [31:0] read-write CC1 Counter compare/capture 1 register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. [31:0] read-write CC1_BUFF Counter buffered compare/capture 1 register 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF CC Additional buffer for counter CC1 register. [31:0] read-write PERIOD Counter period register 0x20 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. [31:0] read-write PERIOD_BUFF Counter buffered period register 0x24 32 read-write 0xFFFFFFFF 0xFFFFFFFF PERIOD Additional buffer for counter PERIOD register. In PWM_PR mode PEROD_BUFF defines the LFSR polynomial. Each bit represents a tap of the shift register which can be feed back to the MSB via an XOR tree. Examples for GRP_CNT_WIDTH = 16: - Maximum length 16bit LFSR - polynomial x^16 + x^14 + x^13 + x^11 + 1 - taps 0,2,3,5 -> PERIOD = 0x002d - period is 2^16-1 = 65535 cycles - Maximum length 8bit LFSR: - polynomial x^8 + x^6 + x^5 + x^4 + 1 - taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR) - period is 2^8-1 = 255 cycles In SR mode PERIOD_BUFF defines which tap of the shift register generates the PWM output signals. For a delay of n cycles (from capture event to PWM output) the bit CNT_WIDTH-n should be set to '1'. For a shift register function only one tap should be use, i.e. a one-hot value must be written to PERIOD_BUFF. If multiple bits in PERIOD_BUFF are set then the taps are XOR combined. [31:0] read-write LINE_SEL Counter line selection register 0x28 32 read-write 0x32 0x77 OUT_SEL Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control. This field has a function in PWM and PWM_PR modes only. Note: The output signal of this selection can be further modified by the stop / kill logic and line_out polarity setting (CTRL.QUAD_ENCODING_MODE[0]). [2:0] read-write L fixed '0' 0 H fixed '1' 1 PWM PWM signal 'line' 2 PWM_INV inverted PWM signal 'line' 3 Z The output 'line_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the output 'line_out_en' to 0. 4 RSVD5 N/A 5 RSVD6 N/A 6 RSVD7 N/A 7 COMPL_OUT_SEL Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control. This field has a function in PWM and PWM_PR modes only. Note: The output signal of this selection can be further modified by the stop / kill logic and line_compl_out polarity setting (CTRL.QUAD_ENCODING_MODE[1]). [6:4] read-write L fixed '0' 0 H fixed '1' 1 PWM PWM signal 'line' 2 PWM_INV inverted PWM signal 'line' 3 Z The output 'line_compl_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). Note: This is realized by driving the output 'line_compl_out_en' to 0. 4 RSVD5 N/A 5 RSVD6 N/A 6 RSVD7 N/A 7 LINE_SEL_BUFF Counter buffered line selection register 0x2C 32 read-write 0x32 0x77 OUT_SEL Buffer for LINE_SEL.OUT_SEL. Can be exchanged with LINE_SEL.LINE_OUT_SEL on a terminal count event with an actively pending switch event. This field has a function in PWM and PWM_PR modes only. [2:0] read-write COMPL_OUT_SEL Buffer for LINE_SEL.COMPL.OUT_SEL. Can be exchanged with LINE_SEL.LINE_COMPL_OUT_SEL on a terminal count event with an actively pending switch event. This field has a function in PWM and PWM_PR modes only. [6:4] read-write DT Counter PWM dead time register 0x30 32 read-write 0x0 0xFFFFFFFF DT_LINE_OUT_L In PWM_DT mode, this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. Note: This field determines the low byte of the 16-bit dead time before activating 'line_out' when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating 'line_out' and 'line_compl_out'. [7:0] read-write DT_LINE_OUT_H In PWM_DT mode, this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. [15:8] read-write DT_LINE_COMPL_OUT In PWM_DT mode, this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain. In all other modes, this field has no effect. Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. [31:16] read-write TR_CMD Counter trigger command register 0x40 32 read-write 0x0 0x3D CAPTURE0 SW capture 0 trigger. When written with '1', a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.ENABLED, the field is immediately set to '0'. [0:0] read-write RELOAD SW reload trigger. For HW behavior, see COUNTER_CAPTURE0 field. [2:2] read-write STOP SW stop trigger. For HW behavior, see COUNTER_CAPTURE0 field. [3:3] read-write START SW start trigger. For HW behavior, see COUNTER_CAPTURE0 field. [4:4] read-write CAPTURE1 SW capture 1 trigger. For HW behavior, see COUNTER_CAPTURE0 field. [5:5] read-write TR_IN_SEL0 Counter input trigger selection register 0 0x44 32 read-write 0x100 0xFFFFFFFF CAPTURE0_SEL Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing, the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by setting 2 and above. The settings above are used for the general purpose trigger inputs 'tr_all_cnt_in' connected to all counters selected. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. [7:0] read-write COUNT_SEL Selects one of the 256 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. Note: In the modes: TIMER, CAPTURE, PWM, PWM_DT, and SR, If the counter is externally triggered ( COUNT_SEL > 1), an external trigger will be required for each TR_CMD to execute. For example, a write to TR_CMD.START will not start the counter until the trigger selected by COUNT_SEL asserts. The next trigger will increment the counter since the counter is now running. This goes for all TR_CMD fields. [15:8] read-write RELOAD_SEL Selects one of the 256 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In these modes, it will update the counter with 0x8000 (counter midpoint) or 0x0000 depending on the QUAD_RANGE_MODE. [23:16] read-write STOP_SEL Selects one of the 256 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. [31:24] read-write TR_IN_SEL1 Counter input trigger selection register 1 0x48 32 read-write 0x0 0xFFFF START_SEL Selects one of the 256 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). [7:0] read-write CAPTURE1_SEL Selects one of the 256 input triggers as a capture 1 trigger. [15:8] read-write TR_IN_EDGE_SEL Counter input trigger edge selection register 0x4C 32 read-write 0xFFF 0xFFF CAPTURE0_EDGE A capture 0 event will copy the counter value into the CC0 register. [1:0] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 COUNT_EDGE A counter event will increase or decrease the counter by '1'. [3:2] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 RELOAD_EDGE A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. [5:4] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 STOP_EDGE A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. [7:6] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 START_EDGE A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. [9:8] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 CAPTURE1_EDGE A capture 1 event will copy the counter value into the CC1 register. [11:10] read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 ANY_EDGE Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 TR_PWM_CTRL Counter trigger PWM control register 0x50 32 read-write 0xFF 0xFF CC0_MATCH_MODE Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC0 register should be set to '0'. For a 100 percent duty cycle, the counter CC0 register should be set to larger than the counter PERIOD register. [1:0] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 OVERFLOW_MODE Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. [3:2] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 UNDERFLOW_MODE Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. [5:4] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 CC1_MATCH_MODE Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals. [7:6] read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 TR_OUT_SEL Counter output trigger selection register 0x54 32 read-write 0x32 0x77 OUT0 Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event. [2:0] read-write OVERFLOW Overflow event 0 UNDERFLOW Underflow event 1 TC Terminal count event (default selection) 2 CC0_MATCH Compare match 0 event 3 CC1_MATCH Compare match 1 event 4 LINE_OUT PWM output signal 'line_out' 5 RSVD6 N/A 6 Disabled Output trigger disabled. 7 OUT1 Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event. [6:4] read-write OVERFLOW Overflow event 0 UNDERFLOW Underflow event 1 TC Terminal count event 2 CC0_MATCH Compare match 0 event (default selection) 3 CC1_MATCH Compare match 1 event 4 LINE_OUT PWM output signal 'line_out' 5 RSVD6 N/A 6 Disabled Output trigger disabled. 7 INTR Interrupt request register 0x70 32 read-write 0x0 0x7 TC Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. [0:0] read-write CC0_MATCH Counter matches CC0 register event. Set to '1', when event is detected. Write with '1' to clear bit. [1:1] read-write CC1_MATCH Counter matches CC1 register event. Set to '1', when event is detected. Write with '1' to clear bit. [2:2] read-write INTR_SET Interrupt set request register 0x74 32 read-write 0x0 0x7 TC Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write CC0_MATCH Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write CC1_MATCH Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write INTR_MASK Interrupt mask register 0x78 32 read-write 0x0 0x7 TC Mask bit for corresponding bit in interrupt request register. [0:0] read-write CC0_MATCH Mask bit for corresponding bit in interrupt request register. [1:1] read-write CC1_MATCH Mask bit for corresponding bit in interrupt request register. [2:2] read-write INTR_MASKED Interrupt masked request register 0x7C 32 read-only 0x0 0x7 TC Logical and of corresponding request and mask bits. [0:0] read-only CC0_MATCH Logical and of corresponding request and mask bits. [1:1] read-only CC1_MATCH Logical and of corresponding request and mask bits. [2:2] read-only LCD0 LCD Controller Block LCD 0x403B0000 0 65536 registers ID ID & Revision 0x0 32 read-only 0x2F0F0 0xFFFFFFFF ID the ID of LCD controller peripheral is 0xF0F0 [15:0] read-only REVISION the version number is 0x0002 [31:16] read-only DIVIDER LCD Divider Register 0x4 32 read-write 0x0 0xFFFFFFFF SUBFR_DIV Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. [15:0] read-write DEAD_DIV Length of the dead time period in cycles. When set to zero, no dead time period exists. [31:16] read-write CONTROL LCD Configuration Register 0x8 32 read-write 0x0 0x80000FFF LS_EN Low speed (LS) generator enable 1: enable 0: disable [0:0] read-write HS_EN High speed (HS) generator enable 1: enable 0: disable [1:1] read-write LCD_MODE HS/LS Mode selection [2:2] read-write LS Select Low Speed Generator (Works in Active, Sleep and DeepSleep power modes). Low speed clock (clk_lf) or middle speed clock (clk_mf) can be selected for Low Speed Generator. 0 HS Select High Speed (system clock) Generator (Works in Active and Sleep power modes only). 1 TYPE LCD driving waveform type configuration. [3:3] read-write TYPE_A Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. 0 TYPE_B Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0). 1 OP_MODE Driving mode configuration [4:4] read-write PWM PWM Mode 0 CORRELATION Digital Correlation Mode 1 BIAS PWM bias selection [6:5] read-write HALF 1/2 Bias 0 THIRD 1/3 Bias 1 FOURTH 1/4 Bias 2 FIFTH 1/5 Bias 3 CLOCK_LS_SEL Low speed (LS) generator clock source selection 1: select clk_mf 0: select clk_lf [7:7] read-write COM_NUM The number of COM connections minus 2. So: 0: 2 COM's 1: 3 COM's ... 13: 15 COM's 14: 16 COM's 15: undefined [11:8] read-write LS_EN_STAT LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. The following procedure should be followed to disable the LS generator: 1. If LS_EN=0 we are done. Exit the procedure. 2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. 3. Set LS_EN=0. 4. Wait until LS_EN_STAT=0. [31:31] read-only 8 4 DATA0[%s] LCD Pin Data Registers 0x100 32 read-write 0x0 0xFFFFFFFF DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). [31:0] read-write 8 4 DATA1[%s] LCD Pin Data Registers 0x200 32 read-write 0x0 0xFFFFFFFF DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). [31:0] read-write 8 4 DATA2[%s] LCD Pin Data Registers 0x300 32 read-write 0x0 0xFFFFFFFF DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). [31:0] read-write 8 4 DATA3[%s] LCD Pin Data Registers 0x400 32 read-write 0x0 0xFFFFFFFF DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). [31:0] read-write USBFS0 USB Host and Device Controller USBFS 0x403F0000 0 65536 registers USBDEV USB Device 0x00000000 8 4 EP0_DR[%s] Control End point EP0 Data Register 0x0 32 read-write 0x0 0xFF DATA_BYTE This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. [7:0] read-write CR0 USB control 0 Register 0x20 32 read-write 0x0 0xFF DEVICE_ADDRESS These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. If USB bus reset is detected, these bits are initialized. [6:0] read-write USB_ENABLE This bit enables the device to respond to USB traffic. If USB bus reset is detected, this bit is cleared. Note: When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. [7:7] read-write CR1 USB control 1 Register 0x24 32 read-write 0x0 0xF REG_ENABLE This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. [0:0] read-write ENABLE_LOCK This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. [1:1] read-write BUS_ACTIVITY The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it. [2:2] read-write RSVD_3 N/A [3:3] read-write SIE_EP_INT_EN USB SIE Data Endpoints Interrupt Enable Register 0x28 32 read-write 0x0 0xFF EP1_INTR_EN Enables interrupt for EP1 [0:0] read-write EP2_INTR_EN Enables interrupt for EP2 [1:1] read-write EP3_INTR_EN Enables interrupt for EP3 [2:2] read-write EP4_INTR_EN Enables interrupt for EP4 [3:3] read-write EP5_INTR_EN Enables interrupt for EP5 [4:4] read-write EP6_INTR_EN Enables interrupt for EP6 [5:5] read-write EP7_INTR_EN Enables interrupt for EP7 [6:6] read-write EP8_INTR_EN Enables interrupt for EP8 [7:7] read-write SIE_EP_INT_SR USB SIE Data Endpoint Interrupt Status 0x2C 32 read-write 0x0 0xFF EP1_INTR Interrupt status for EP1 [0:0] read-write EP2_INTR Interrupt status for EP2 [1:1] read-write EP3_INTR Interrupt status for EP3 [2:2] read-write EP4_INTR Interrupt status for EP4 [3:3] read-write EP5_INTR Interrupt status for EP5 [4:4] read-write EP6_INTR Interrupt status for EP6 [5:5] read-write EP7_INTR Interrupt status for EP7 [6:6] read-write EP8_INTR Interrupt status for EP8 [7:7] read-write SIE_EP1_CNT0 Non-control endpoint count register 0x30 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP1_CNT1 Non-control endpoint count register 0x34 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP1_CR0 Non-control endpoint's control Register 0x38 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write USBIO_CR0 USBIO Control 0 Register 0x40 32 read-write 0x0 0xE0 RD Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. If D+=D- (SE0), this value is undefined. [0:0] read-only DIFF_LOW D+ < D- (K state) 0 DIFF_HIGH D+ > D- (J state) 1 TD Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. [5:5] read-write DIFF_K Force USB K state (D+ is low D- is high). 0 DIFF_J Force USB J state (D+ is high D- is low). 1 TSE0 Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. [6:6] read-write TEN USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus. [7:7] read-write USBIO_CR2 USBIO control 2 Register 0x44 32 read-write 0x0 0xFF RSVD_5_0 N/A [5:0] read-only TEST_PKT This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. [6:6] read-write RSVD_7 N/A [7:7] read-write USBIO_CR1 USBIO control 1 Register 0x48 32 read-write 0x20 0x20 DMO This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. This bit is valid if USB Device. [0:0] read-only DPO This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. This bit displays the output value of D+ pin when USB transmits SE0 or data. This bit is valid if USB Device. [1:1] read-only RSVD_2 N/A [2:2] read-write IOMODE This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. [5:5] read-write DYN_RECONFIG USB Dynamic reconfiguration register 0x50 32 read-write 0x0 0x1F DYN_CONFIG_EN This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. Use 0 for EP1, 1 for EP2, etc. [0:0] read-write DYN_RECONFIG_EPNO These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. [3:1] read-write DYN_RECONFIG_RDY_STS This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. [4:4] read-only SOF0 Start Of Frame Register 0x60 32 read-only 0x0 0xFF FRAME_NUMBER It has the lower 8 bits [7:0] of the SOF frame number. [7:0] read-only SOF1 Start Of Frame Register 0x64 32 read-only 0x0 0x7 FRAME_NUMBER_MSB It has the upper 3 bits [10:8] of the SOF frame number. [2:0] read-only SIE_EP2_CNT0 Non-control endpoint count register 0x70 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP2_CNT1 Non-control endpoint count register 0x74 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP2_CR0 Non-control endpoint's control Register 0x78 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write OSCLK_DR0 Oscillator lock data register 0 0x80 32 read-only 0x0 0x0 ADDER These bits return the lower 8 bits of the oscillator locking circuits adder output. [7:0] read-only OSCLK_DR1 Oscillator lock data register 1 0x84 32 read-only 0x0 0x0 ADDER_MSB These bits return the upper 7 bits of the oscillator locking circuits adder output. [6:0] read-only EP0_CR Endpoint0 control Register 0xA0 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 OUT_RCVD When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. [5:5] read-write IN_RCVD When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. [6:6] read-write SETUP_RCVD When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. [7:7] read-write EP0_CNT Endpoint0 count Register 0xA4 32 read-write 0x0 0xCF BYTE_COUNT These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. [3:0] read-write DATA_VALID This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP3_CNT0 Non-control endpoint count register 0xB0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP3_CNT1 Non-control endpoint count register 0xB4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP3_CR0 Non-control endpoint's control Register 0xB8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP4_CNT0 Non-control endpoint count register 0xF0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP4_CNT1 Non-control endpoint count register 0xF4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP4_CR0 Non-control endpoint's control Register 0xF8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP5_CNT0 Non-control endpoint count register 0x130 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP5_CNT1 Non-control endpoint count register 0x134 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP5_CR0 Non-control endpoint's control Register 0x138 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP6_CNT0 Non-control endpoint count register 0x170 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP6_CNT1 Non-control endpoint count register 0x174 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP6_CR0 Non-control endpoint's control Register 0x178 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP7_CNT0 Non-control endpoint count register 0x1B0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP7_CNT1 Non-control endpoint count register 0x1B4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP7_CR0 Non-control endpoint's control Register 0x1B8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write SIE_EP8_CNT0 Non-control endpoint count register 0x1F0 32 read-write 0x0 0xC7 DATA_COUNT_MSB These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. [2:0] read-write DATA_VALID This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. [6:6] read-write DATA_ERROR No ACK'd transactions since bit was last cleared. 0 DATA_VALID Indicates a transaction ended with an ACK. 1 DATA_TOGGLE This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. [7:7] read-write SIE_EP8_CNT1 Non-control endpoint count register 0x1F4 32 read-write 0x0 0xFF DATA_COUNT These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. [7:0] read-write SIE_EP8_CR0 Non-control endpoint's control Register 0x1F8 32 read-write 0x0 0xFF MODE The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. [3:0] read-write DISABLE Ignore all USB traffic to this endpoint 0 NAK_INOUT SETUP: Accept IN: NAK OUT: NAK 1 STATUS_OUT_ONLY SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others 2 STALL_INOUT SETUP: Accept IN: STALL OUT: STALL 3 ISO_OUT SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token 5 STATUS_IN_ONLY SETUP: Accept IN: Respond with 0B data OUT: Stall 6 ISO_IN SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore 7 NAK_OUT SETUP: Ignore IN: Ignore OUT: NAK 8 ACK_OUT SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. 9 ACK_OUT_STATUS_IN SETUP: Accept IN: Respond with 0B data OUT: Accept data 11 NAK_IN SETUP: Ignore IN: NAK OUT: Ignore 12 ACK_IN SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore 13 ACK_IN_STATUS_OUT SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others 15 ACKED_TXN The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. [4:4] read-write ACKED_NO No ACK'd transactions since bit was last cleared. 0 ACKED_YES Indicates a transaction ended with an ACK. 1 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. [5:5] read-write ERR_IN_TXN The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. [6:6] read-write STALL When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. [7:7] read-write ARB_EP1_CFG Endpoint Configuration Register *1 0x200 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP1_INT_EN Endpoint Interrupt Enable Register *1 0x204 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP1_SR Endpoint Interrupt Enable Register *1 0x208 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW1_WA Endpoint Write Address value *1, *2 0x210 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW1_WA_MSB Endpoint Write Address value *1, *2 0x214 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW1_RA Endpoint Read Address value *1, *2 0x218 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW1_RA_MSB Endpoint Read Address value *1, *2 0x21C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW1_DR Endpoint Data Register 0x220 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write BUF_SIZE Dedicated Endpoint Buffer Size Register *1 0x230 32 read-write 0x0 0xFF IN_BUF Buffer size for IN Endpoints. [3:0] read-write OUT_BUF Buffer size for OUT Endpoints. [7:4] read-write EP_ACTIVE Endpoint Active Indication Register *1 0x238 32 read-write 0x0 0xFF EP1_ACT Indicates that Endpoint is currently active. [0:0] read-write EP2_ACT Indicates that Endpoint is currently active. [1:1] read-write EP3_ACT Indicates that Endpoint is currently active. [2:2] read-write EP4_ACT Indicates that Endpoint is currently active. [3:3] read-write EP5_ACT Indicates that Endpoint is currently active. [4:4] read-write EP6_ACT Indicates that Endpoint is currently active. [5:5] read-write EP7_ACT Indicates that Endpoint is currently active. [6:6] read-write EP8_ACT Indicates that Endpoint is currently active. [7:7] read-write EP_TYPE Endpoint Type (IN/OUT) Indication *1 0x23C 32 read-write 0x0 0xFF EP1_TYP Endpoint Type Indication. [0:0] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP2_TYP Endpoint Type Indication. [1:1] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP3_TYP Endpoint Type Indication. [2:2] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP4_TYP Endpoint Type Indication. [3:3] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP5_TYP Endpoint Type Indication. [4:4] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP6_TYP Endpoint Type Indication. [5:5] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP7_TYP Endpoint Type Indication. [6:6] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 EP8_TYP Endpoint Type Indication. [7:7] read-write EP_IN IN outpoint 0 EP_OUT OUT outpoint 1 ARB_EP2_CFG Endpoint Configuration Register *1 0x240 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP2_INT_EN Endpoint Interrupt Enable Register *1 0x244 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP2_SR Endpoint Interrupt Enable Register *1 0x248 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW2_WA Endpoint Write Address value *1, *2 0x250 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW2_WA_MSB Endpoint Write Address value *1, *2 0x254 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW2_RA Endpoint Read Address value *1, *2 0x258 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW2_RA_MSB Endpoint Read Address value *1, *2 0x25C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW2_DR Endpoint Data Register 0x260 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_CFG Arbiter Configuration Register *1 0x270 32 read-write 0x0 0xF0 AUTO_MEM Enables Auto Memory Configuration. Manual memory configuration by default. [4:4] read-write DMA_CFG DMA Access Configuration. [6:5] read-write DMA_NONE No DMA 0 DMA_MANUAL Manual DMA 1 DMA_AUTO Auto DMA 2 CFG_CMP Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. [7:7] read-write USB_CLK_EN USB Block Clock Enable Register 0x274 32 read-write 0x0 0x1 CSR_CLK_EN Clock Enable for Core Logic clocked by AHB bus clock [0:0] read-write ARB_INT_EN Arbiter Interrupt Enable *1 0x278 32 read-write 0x0 0xFF EP1_INTR_EN Enables interrupt for EP1 [0:0] read-write EP2_INTR_EN Enables interrupt for EP2 [1:1] read-write EP3_INTR_EN Enables interrupt for EP3 [2:2] read-write EP4_INTR_EN Enables interrupt for EP4 [3:3] read-write EP5_INTR_EN Enables interrupt for EP5 [4:4] read-write EP6_INTR_EN Enables interrupt for EP6 [5:5] read-write EP7_INTR_EN Enables interrupt for EP7 [6:6] read-write EP8_INTR_EN Enables interrupt for EP8 [7:7] read-write ARB_INT_SR Arbiter Interrupt Status *1 0x27C 32 read-only 0x0 0xFF EP1_INTR Interrupt status for EP1 [0:0] read-only EP2_INTR Interrupt status for EP2 [1:1] read-only EP3_INTR Interrupt status for EP3 [2:2] read-only EP4_INTR Interrupt status for EP4 [3:3] read-only EP5_INTR Interrupt status for EP5 [4:4] read-only EP6_INTR Interrupt status for EP6 [5:5] read-only EP7_INTR Interrupt status for EP7 [6:6] read-only EP8_INTR Interrupt status for EP8 [7:7] read-only ARB_EP3_CFG Endpoint Configuration Register *1 0x280 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP3_INT_EN Endpoint Interrupt Enable Register *1 0x284 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP3_SR Endpoint Interrupt Enable Register *1 0x288 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW3_WA Endpoint Write Address value *1, *2 0x290 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW3_WA_MSB Endpoint Write Address value *1, *2 0x294 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW3_RA Endpoint Read Address value *1, *2 0x298 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW3_RA_MSB Endpoint Read Address value *1, *2 0x29C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW3_DR Endpoint Data Register 0x2A0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write CWA Common Area Write Address *1 0x2B0 32 read-write 0x0 0xFF CWA Write Address for Common Area [7:0] read-write CWA_MSB Endpoint Read Address value *1 0x2B4 32 read-write 0x0 0x1 CWA_MSB Write Address for Common Area [0:0] read-write ARB_EP4_CFG Endpoint Configuration Register *1 0x2C0 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP4_INT_EN Endpoint Interrupt Enable Register *1 0x2C4 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP4_SR Endpoint Interrupt Enable Register *1 0x2C8 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW4_WA Endpoint Write Address value *1, *2 0x2D0 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW4_WA_MSB Endpoint Write Address value *1, *2 0x2D4 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW4_RA Endpoint Read Address value *1, *2 0x2D8 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW4_RA_MSB Endpoint Read Address value *1, *2 0x2DC 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW4_DR Endpoint Data Register 0x2E0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write DMA_THRES DMA Burst / Threshold Configuration 0x2F0 32 read-write 0x0 0xFF DMA_THS DMA Threshold count [7:0] read-write DMA_THRES_MSB DMA Burst / Threshold Configuration 0x2F4 32 read-write 0x0 0x1 DMA_THS_MSB DMA Threshold count [0:0] read-write ARB_EP5_CFG Endpoint Configuration Register *1 0x300 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP5_INT_EN Endpoint Interrupt Enable Register *1 0x304 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP5_SR Endpoint Interrupt Enable Register *1 0x308 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW5_WA Endpoint Write Address value *1, *2 0x310 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW5_WA_MSB Endpoint Write Address value *1, *2 0x314 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW5_RA Endpoint Read Address value *1, *2 0x318 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW5_RA_MSB Endpoint Read Address value *1, *2 0x31C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW5_DR Endpoint Data Register 0x320 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write BUS_RST_CNT Bus Reset Count Register 0x330 32 read-write 0xA 0xF BUS_RST_CNT Bus Reset Count Length [3:0] read-write ARB_EP6_CFG Endpoint Configuration Register *1 0x340 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP6_INT_EN Endpoint Interrupt Enable Register *1 0x344 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP6_SR Endpoint Interrupt Enable Register *1 0x348 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW6_WA Endpoint Write Address value *1, *2 0x350 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW6_WA_MSB Endpoint Write Address value *1, *2 0x354 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW6_RA Endpoint Read Address value *1, *2 0x358 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW6_RA_MSB Endpoint Read Address value *1, *2 0x35C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW6_DR Endpoint Data Register 0x360 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_EP7_CFG Endpoint Configuration Register *1 0x380 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP7_INT_EN Endpoint Interrupt Enable Register *1 0x384 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP7_SR Endpoint Interrupt Enable Register *1 0x388 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW7_WA Endpoint Write Address value *1, *2 0x390 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW7_WA_MSB Endpoint Write Address value *1, *2 0x394 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW7_RA Endpoint Read Address value *1, *2 0x398 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW7_RA_MSB Endpoint Read Address value *1, *2 0x39C 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW7_DR Endpoint Data Register 0x3A0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write ARB_EP8_CFG Endpoint Configuration Register *1 0x3C0 32 read-write 0x0 0xF IN_DATA_RDY Indication that Endpoint Packet Data is Ready in Main memory [0:0] read-write DMA_REQ Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. [1:1] read-write CRC_BYPASS Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware [2:2] read-write CRC_NORMAL No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s 0 CRC_BYPASS CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s 1 RESET_PTR Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. [3:3] read-write RESET_KRYPTON Do not Reset Pointer; Krypton Backward compatibility mode 0 RESET_NORMAL Reset Pointer; recommended value for reduction of CPU Configuration Writes. 1 ARB_EP8_INT_EN Endpoint Interrupt Enable Register *1 0x3C4 32 read-write 0x0 0x3F IN_BUF_FULL_EN IN Endpoint Local Buffer Full Enable [0:0] read-write DMA_GNT_EN Endpoint DMA Grant Enable [1:1] read-write BUF_OVER_EN Endpoint Buffer Overflow Enable [2:2] read-write BUF_UNDER_EN Endpoint Buffer Underflow Enable [3:3] read-write ERR_INT_EN Endpoint Error in Transaction Interrupt Enable [4:4] read-write DMA_TERMIN_EN Endpoint DMA Terminated Enable [5:5] read-write ARB_EP8_SR Endpoint Interrupt Enable Register *1 0x3C8 32 read-write 0x0 0x2F IN_BUF_FULL IN Endpoint Local Buffer Full Interrupt [0:0] read-write DMA_GNT Endpoint DMA Grant Interrupt [1:1] read-write BUF_OVER Endpoint Buffer Overflow Interrupt [2:2] read-write BUF_UNDER Endpoint Buffer Underflow Interrupt [3:3] read-write DMA_TERMIN Endpoint DMA Terminated Interrupt [5:5] read-write ARB_RW8_WA Endpoint Write Address value *1, *2 0x3D0 32 read-write 0x0 0xFF WA Write Address for EP [7:0] read-write ARB_RW8_WA_MSB Endpoint Write Address value *1, *2 0x3D4 32 read-write 0x0 0x1 WA_MSB Write Address for EP [0:0] read-write ARB_RW8_RA Endpoint Read Address value *1, *2 0x3D8 32 read-write 0x0 0xFF RA Read Address for EP [7:0] read-write ARB_RW8_RA_MSB Endpoint Read Address value *1, *2 0x3DC 32 read-write 0x0 0x1 RA_MSB Read Address for EP [0:0] read-write ARB_RW8_DR Endpoint Data Register 0x3E0 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write 512 4 MEM_DATA[%s] DATA 0x400 32 read-write 0x0 0x0 DR Data Register for EP ; This register is linked to the memory, hence reset value is undefined [7:0] read-write SOF16 Start Of Frame Register 0x1060 32 read-only 0x0 0x7FF FRAME_NUMBER16 The frame number (11b) [10:0] read-only OSCLK_DR16 Oscillator lock data register 0x1080 32 read-only 0x0 0x0 ADDER16 These bits return the oscillator locking circuits adder output. [14:0] read-only ARB_RW1_WA16 Endpoint Write Address value *3 0x1210 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW1_RA16 Endpoint Read Address value *3 0x1218 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW1_DR16 Endpoint Data Register 0x1220 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW2_WA16 Endpoint Write Address value *3 0x1250 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW2_RA16 Endpoint Read Address value *3 0x1258 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW2_DR16 Endpoint Data Register 0x1260 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW3_WA16 Endpoint Write Address value *3 0x1290 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW3_RA16 Endpoint Read Address value *3 0x1298 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW3_DR16 Endpoint Data Register 0x12A0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write CWA16 Common Area Write Address 0x12B0 32 read-write 0x0 0x1FF CWA16 Write Address for Common Area [8:0] read-write ARB_RW4_WA16 Endpoint Write Address value *3 0x12D0 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW4_RA16 Endpoint Read Address value *3 0x12D8 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW4_DR16 Endpoint Data Register 0x12E0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write DMA_THRES16 DMA Burst / Threshold Configuration 0x12F0 32 read-write 0x0 0x1FF DMA_THS16 DMA Threshold count [8:0] read-write ARB_RW5_WA16 Endpoint Write Address value *3 0x1310 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW5_RA16 Endpoint Read Address value *3 0x1318 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW5_DR16 Endpoint Data Register 0x1320 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW6_WA16 Endpoint Write Address value *3 0x1350 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW6_RA16 Endpoint Read Address value *3 0x1358 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW6_DR16 Endpoint Data Register 0x1360 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW7_WA16 Endpoint Write Address value *3 0x1390 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW7_RA16 Endpoint Read Address value *3 0x1398 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW7_DR16 Endpoint Data Register 0x13A0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write ARB_RW8_WA16 Endpoint Write Address value *3 0x13D0 32 read-write 0x0 0x1FF WA16 Write Address for EP [8:0] read-write ARB_RW8_RA16 Endpoint Read Address value *3 0x13D8 32 read-write 0x0 0x1FF RA16 Read Address for EP [8:0] read-write ARB_RW8_DR16 Endpoint Data Register 0x13E0 32 read-write 0x0 0x0 DR16 Data Register for EP ; This register is linked to the memory, hence reset value is undefined [15:0] read-write USBLPM USB Device LPM and PHY Test 0x00002000 POWER_CTL Power Control Register 0x0 32 read-write 0x0 0x303F0004 SUSPEND Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). Note: - This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. [2:2] read-write DP_UP_EN Enables the pull up on the DP. '0' : Disable. '1' : Enable. [16:16] read-write DP_BIG Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Ohmpull up on the DP. '1' : The resister value is from 1425 to 3090Ohmpull up on the DP [17:17] read-write DP_DOWN_EN Enables the ~15k pull down on the DP. [18:18] read-write DM_UP_EN Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. '0' : Disable. '1' : Enable. [19:19] read-write DM_BIG Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Ohmpull up on the DM. '1' : The resister value is from 1425 to 3090Ohmpull up on the DM [20:20] read-write DM_DOWN_EN Enables the ~15k pull down on the DP. [21:21] read-write ENABLE_DPO Enables the single ended receiver on D+. [28:28] read-write ENABLE_DMO Enables the signle ended receiver on D-. [29:29] read-write USBIO_CTL USB IO Control Register 0x8 32 read-write 0x0 0x3F DM_P The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. [2:0] read-write OFF Mode 0: Output buffer off (high Z). Input buffer off. 0 INPUT Mode 1: Output buffer off (high Z). Input buffer on. Other values, not supported. 1 DM_M The GPIO Drive Mode for DM IO pad. [5:3] read-write FLOW_CTL Flow Control Register 0xC 32 read-write 0x0 0xFF EP1_ERR_RESP End Point 1 error response 0: do nothing (backward compatibility mode) 1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK [0:0] read-write EP2_ERR_RESP End Point 2 error response [1:1] read-write EP3_ERR_RESP End Point 3 error response [2:2] read-write EP4_ERR_RESP End Point 4 error response [3:3] read-write EP5_ERR_RESP End Point 5 error response [4:4] read-write EP6_ERR_RESP End Point 6 error response [5:5] read-write EP7_ERR_RESP End Point 7 error response [6:6] read-write EP8_ERR_RESP End Point 8 error response [7:7] read-write LPM_CTL LPM Control Register 0x10 32 read-write 0x0 0x17 LPM_EN LPM enable 0: Disabled, LPM token will not get a response (backward compatibility mode) 1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) A STALL will be sent if the bLinkState is not 0001b A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below [0:0] read-write LPM_ACK_RESP LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request 0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode 1: a LPM token will get an ACK response and the device will go to the requested low power mode [1:1] read-write NYET_EN Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). 0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. 1: a LPM token will get a NYET response [2:2] read-write SUB_RESP Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. [4:4] read-write LPM_STAT LPM Status register 0x14 32 read-only 0x0 0x1F LPM_BESL Best Effort Service Latency This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. [3:0] read-only LPM_REMOTEWAKE 0: Device is prohibited from initiating a remote wake 1: Device is allow to wake the host [4:4] read-only INTR_SIE USB SOF, BUS RESET and EP0 Interrupt Status 0x20 32 read-write 0x0 0x1F SOF_INTR Interrupt status for USB SOF [0:0] read-write BUS_RESET_INTR Interrupt status for BUS RESET [1:1] read-write EP0_INTR Interrupt status for EP0 [2:2] read-write LPM_INTR Interrupt status for LPM (Link Power Management, L1 entry) [3:3] read-write RESUME_INTR Interrupt status for Resume [4:4] read-write INTR_SIE_SET USB SOF, BUS RESET and EP0 Interrupt Set 0x24 32 read-write 0x0 0x1F SOF_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write BUS_RESET_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write EP0_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write LPM_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write RESUME_INTR_SET Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write INTR_SIE_MASK USB SOF, BUS RESET and EP0 Interrupt Mask 0x28 32 read-write 0x0 0x1F SOF_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [0:0] read-write BUS_RESET_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [1:1] read-write EP0_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [2:2] read-write LPM_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [3:3] read-write RESUME_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register [4:4] read-write INTR_SIE_MASKED USB SOF, BUS RESET and EP0 Interrupt Masked 0x2C 32 read-only 0x0 0x1F SOF_INTR_MASKED Logical and of corresponding request and mask bits. [0:0] read-only BUS_RESET_INTR_MASKED Logical and of corresponding request and mask bits. [1:1] read-only EP0_INTR_MASKED Logical and of corresponding request and mask bits. [2:2] read-only LPM_INTR_MASKED Logical and of corresponding request and mask bits. [3:3] read-only RESUME_INTR_MASKED Logical and of corresponding request and mask bits. [4:4] read-only INTR_LVL_SEL Select interrupt level for each interrupt source 0x30 32 read-write 0x0 0xFFFFC3FF SOF_LVL_SEL USB SOF Interrupt level select [1:0] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD illegal 3 BUS_RESET_LVL_SEL BUS RESET Interrupt level select [3:2] read-write EP0_LVL_SEL EP0 Interrupt level select [5:4] read-write LPM_LVL_SEL LPM Interrupt level select [7:6] read-write RESUME_LVL_SEL Resume Interrupt level select [9:8] read-write ARB_EP_LVL_SEL Arbiter Endpoint Interrupt level select [15:14] read-write EP1_LVL_SEL EP1 Interrupt level select [17:16] read-write EP2_LVL_SEL EP2 Interrupt level select [19:18] read-write EP3_LVL_SEL EP3 Interrupt level select [21:20] read-write EP4_LVL_SEL EP4 Interrupt level select [23:22] read-write EP5_LVL_SEL EP5 Interrupt level select [25:24] read-write EP6_LVL_SEL EP6 Interrupt level select [27:26] read-write EP7_LVL_SEL EP7 Interrupt level select [29:28] read-write EP8_LVL_SEL EP8 Interrupt level select [31:30] read-write INTR_CAUSE_HI High priority interrupt Cause register 0x34 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only INTR_CAUSE_MED Medium priority interrupt Cause register 0x38 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only INTR_CAUSE_LO Low priority interrupt Cause register 0x3C 32 read-only 0x0 0xFF9F SOF_INTR USB SOF Interrupt [0:0] read-only BUS_RESET_INTR BUS RESET Interrupt [1:1] read-only EP0_INTR EP0 Interrupt [2:2] read-only LPM_INTR LPM Interrupt [3:3] read-only RESUME_INTR Resume Interrupt [4:4] read-only ARB_EP_INTR Arbiter Endpoint Interrupt [7:7] read-only EP1_INTR EP1 Interrupt [8:8] read-only EP2_INTR EP2 Interrupt [9:9] read-only EP3_INTR EP3 Interrupt [10:10] read-only EP4_INTR EP4 Interrupt [11:11] read-only EP5_INTR EP5 Interrupt [12:12] read-only EP6_INTR EP6 Interrupt [13:13] read-only EP7_INTR EP7 Interrupt [14:14] read-only EP8_INTR EP8 Interrupt [15:15] read-only DFT_CTL DFT control 0x70 32 read-write 0x0 0x1F DDFT_OUT_SEL DDFT output select signal [2:0] read-write OFF Nothing connected, output 0 0 DP_SE Single Ended output of DP 1 DM_SE Single Ended output of DM 2 TXOE Output Enable 3 RCV_DF Differential Receiver output 4 GPIO_DP_OUT GPIO output of DP 5 GPIO_DM_OUT GPIO output of DM 6 DDFT_IN_SEL DDFT input select signal [4:3] read-write OFF Nothing connected, output 0 0 GPIO_DP_IN GPIO input of DP 1 GPIO_DM_IN GPIO input of DM 2 USBHOST USB Host Controller 0x00004000 HOST_CTL0 Host Control 0 Register. 0x0 32 read-write 0x0 0x80000001 HOST This bit selects an operating mode of this IP. '0' : USB Device '1' : USB Host Notes: - The mode of operation mode does not transition immediately after setting this bit. Read this bit to confirm that the operation mode has changed. - This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'. - Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. [0:0] read-write ENABLE This bit enables the operation of this IP. '0' : Disable USB Host '1' : Enable USB Host Note: - This bit doesn't affect the USB Device. [31:31] read-write HOST_CTL1 Host Control 1 Register. 0x10 32 read-write 0x83 0x83 CLKSEL This bit selects the operating clock of USB Host. '0' : Low-speed clock '1' : Full-speed clock Notes: - This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. - This bit must always be set to '1' in the USB Device mode. [0:0] read-write USTP This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. '0' : Normal operating mode. '1' : Stops the clock for the USB Host operating unit. Notes: - If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. [1:1] read-write RST This bit resets the USB Host. '0' : Normal operating mode. '1' : USB Host is reset. Notes: - This bit is to it's default value '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. - If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. [7:7] read-write HOST_CTL2 Host Control 2 Register. 0x100 32 read-write 0x1 0xFF RETRY If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). * : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' '0' : Doesn't retry token sending. '1' : Retries token sending Note: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [0:0] read-write CANCEL When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). '0' : Continues a token. '1' : Cancels a token. [1:1] read-write SOFSTEP If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. '0' : An interrupt occurred due to the HOST_HFCOMP setting. '1' : An interrupt occurred. Notes: - If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. [2:2] read-write ALIVE This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit. '0' : SOF output. '1' : SE0 output (Keep alive) [3:3] read-write RSVD_4 N/A [4:4] read-write RSVD_5 N/A [5:5] read-write TTEST N/A [7:6] read-write HOST_ERR Host Error Status Register. 0x104 32 read-write 0x3 0xFF HS These flags indicate the status of a handshake packet to be sent or received. These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). These bits are updated when sending or receiving has been ended. Write '11' to set the status back to 'NULL', all other write values are ignored. Note: This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [1:0] read-write ACK Acknowledge Packet 0 NAK Non-Acknowledge Packet 1 STALL Stall Packet 2 NULL Null Packet 3 STUFF If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. '0' : No stuffing error. '1' : Stuffing error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [2:2] read-write TGERR If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. '0' : No toggle error. '1' : Toggle error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [3:3] read-write CRC If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. '0' : No CRC error. '1' : CRC error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [4:4] read-write TOUT If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. Write '1' to clear, a write of '0' is ignored. '0' : No timeout. '1' : Timeout has detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [5:5] read-write RERR When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. '0' : No receive error. '1' : Maximum packet receive error detected. - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [6:6] read-write LSTSOF If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored. '0' : SOF sent without error. '1' : SOF error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:7] read-write HOST_STATUS Host Status Register. 0x108 32 read-write 0xC2 0x1FF CSTAT When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. '0' : Device is disconnected. '1' : Device is connected. Notes: - This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. [0:0] read-only TMODE If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. '0' : Low-speed. '1' : Full-speed. Notes: - This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. [1:1] read-only SUSP If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. Set to '1' : Suspend. Set '0' when this bit is '1' : Resume. Other conditions : Holds the status. Notes: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. - If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. - Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). - If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. [2:2] read-write SOFBUSY When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. '0' : The SOF timer is stopped. '1' : The SOF timer is active. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). - The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. [3:3] read-write URST When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete [4:4] read-write RSVD_5 N/A [5:5] read-only RSTBUSY This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. '0' : USB Host isn't being reset. '1' : USB Host is being reset. Notes: - If this bit is '1', the a token must not be executed. - This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete. [6:6] read-only CLKSEL_ST This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. '0' : Low speed '1' : Full speed Note: - If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. [7:7] read-only HOST_ST This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. '0' : USB Device '1' : USB Host Notes: - If this bit is different from the HOST bit, The execution of a token must wait these bits match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. [8:8] read-only HOST_FCOMP Host SOF Interrupt Frame Compare Register 0x10C 32 read-write 0x0 0xFF FRAMECOMP These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. Note: - This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:0] read-write HOST_RTIMER Host Retry Timer Setup Register 0x110 32 read-write 0x0 0x3FFFF RTIMER These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends. If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. [17:0] read-write HOST_ADDR Host Address Register 0x114 32 read-write 0x0 0x7F ADDRESS These bits are used to specify a token address. Note: - This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [6:0] read-write HOST_EOF Host EOF Setup Register 0x118 32 read-write 0x0 0x3FFF EOF These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. Setting example: MAXPKT = 64 bytes, full-speed mode (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit Therefore, set 0x2C9. Note: - This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [13:0] read-write HOST_FRAME Host Frame Setup Register 0x11C 32 read-write 0x0 0x7FF FRAME These bits are used to specify a frame number of SOF. Notes: - This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). - This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. [10:0] read-write HOST_TOKEN Host Token Endpoint Register 0x120 32 read-write 0x0 0x17F ENDPT These bits are used to specify an endpoint to send or receive data to or from the device. Note: - This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [3:0] read-write TKNEN These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. Notes: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The PRE packet isn't supported. - Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' - Mode should be USB Host before writing data to this bit. - When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. - Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. - Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. [6:4] read-write NONE Sends no data. 0 SETUP Sends SETUP token. 1 IN Sends IN token. 2 OUT Sends OUT token. 3 SOF Sends SOF token. 4 ISO_IN Sends Isochronous IN. 5 ISO_OUT Sends Isochronous OUT. 6 RSV N/A 7 TGGL This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. '0' : DATA0 '1' : DATA1 Notes: - This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. [8:8] read-write HOST_EP1_CTL Host Endpoint 1 Control Register 0x400 32 read-write 0x8100 0x9DFF PKS1 This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. - If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used, [8:0] read-write NULLE When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. [10:10] read-write DMAE This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the packet transfer mode. '1' : Sets the packet transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). [11:11] read-write DIR This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. [12:12] read-write BFINI This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. [15:15] read-write HOST_EP1_STATUS Host Endpoint 1 Status Register 0x404 32 read-only 0x60000 0x70000 SIZE1 These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. The indication range is from 0x000 to 0x100. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. [8:0] read-only VAL_DATA This bit shows that there is valid data in the EP1 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer [16:16] read-only INI_ST This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. '0' : Not initiatialized '1' : Initialized Note: - This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. Read this bit to confirm the transition. [17:17] read-only RSVD_18 N/A [18:18] read-only HOST_EP1_RW1_DR Host Endpoint 1 Data 1-Byte Register 0x408 32 read-write 0x0 0xFF BFDT8 Data Register for EP1 for 1-byte data [7:0] read-write HOST_EP1_RW2_DR Host Endpoint 1 Data 2-Byte Register 0x40C 32 read-write 0x0 0xFFFF BFDT16 Data Register for EP1 for 2-byte data [15:0] read-write HOST_EP2_CTL Host Endpoint 2 Control Register 0x500 32 read-write 0x8040 0x9C7F PKS2 This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. - If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2. [6:0] read-write NULLE When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. [10:10] read-write DMAE This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the automatic buffer transfer mode. '1' : Sets the automatic buffer transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). [11:11] read-write DIR This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. [12:12] read-write BFINI This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. [15:15] read-write HOST_EP2_STATUS Host Endpoint 2 Status Register 0x504 32 read-only 0x60000 0x70000 SIZE2 These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. The indication range is from 0x000 to 0x40. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. [6:0] read-only VAL_DATA This bit shows that there is valid data in the EP2 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer [16:16] read-only INI_ST This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. '0' : Not Initialized '1' : Initialized Note: - This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. [17:17] read-only RSVD_18 N/A [18:18] read-only HOST_EP2_RW1_DR Host Endpoint 2 Data 1-Byte Register 0x508 32 read-write 0x0 0xFF BFDT8 Data Register for EP2 for 1-byte data. [7:0] read-write HOST_EP2_RW2_DR Host Endpoint 2 Data 2-Byte Register 0x50C 32 read-write 0x0 0xFFFF BFDT16 Data Register for EP2 for 2 byte data. [15:0] read-write HOST_LVL1_SEL Host Interrupt Level 1 Selection Register 0x800 32 read-write 0x0 0xFFFF SOFIRQ_SEL These bits assign SOFIRQ interrupt flag to selected interrupt signals. [1:0] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD N/A 3 DIRQ_SEL These bits assign DIRQ interrupt flag to selected interrupt signals. [3:2] read-write CNNIRQ_SEL These bits assign CNNIRQ interrupt flag to selected interrupt signals. [5:4] read-write CMPIRQ_SEL These bits assign URIRQ interrupt flag to selected interrupt signals. [7:6] read-write URIRQ_SEL These bits assign URIRQ interrupt flag to selected interrupt signals. [9:8] read-write RWKIRQ_SEL These bits assign RWKIRQ interrupt flag to selected interrupt signals. [11:10] read-write RSVD_13_12 N/A [13:12] read-write TCAN_SEL These bits assign TCAN interrupt flag to selected interrupt signals. [15:14] read-write HOST_LVL2_SEL Host Interrupt Level 2 Selection Register 0x804 32 read-write 0x0 0xFF0 EP1_DRQ_SEL These bits assign EP1_DRQ interrupt flag to selected interrupt signals. [5:4] read-write HI High priority interrupt 0 MED Medium priority interrupt 1 LO Low priority interrupt 2 RSVD N/A 3 EP1_SPK_SEL These bits assign EP1_SPK interrupt flag to selected interrupt signals. [7:6] read-write EP2_DRQ_SEL These bits assign EP2_DRQ interrupt flag to selected interrupt signals. [9:8] read-write EP2_SPK_SEL These bits assign EP2_SPK interrupt flag to selected interrupt signals. [11:10] read-write INTR_USBHOST_CAUSE_HI Interrupt USB Host Cause High Register 0x900 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_USBHOST_CAUSE_MED Interrupt USB Host Cause Medium Register 0x904 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_USBHOST_CAUSE_LO Interrupt USB Host Cause Low Register 0x908 32 read-only 0x0 0xFF SOFIRQ_INT SOFIRQ interrupt [0:0] read-only DIRQ_INT DIRQ interrupt [1:1] read-only CNNIRQ_INT CNNIRQ interrupt [2:2] read-only CMPIRQ_INT CMPIRQ interrupt [3:3] read-only URIRQ_INT URIRQ interrupt [4:4] read-only RWKIRQ_INT RWKIRQ interrupt [5:5] read-only RSVD_6 N/A [6:6] read-only TCAN_INT TCAN interrupt [7:7] read-only INTR_HOST_EP_CAUSE_HI Interrupt USB Host Endpoint Cause High Register 0x920 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_HOST_EP_CAUSE_MED Interrupt USB Host Endpoint Cause Medium Register 0x924 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_HOST_EP_CAUSE_LO Interrupt USB Host Endpoint Cause Low Register 0x928 32 read-only 0x0 0x3C EP1DRQ_INT EP1DRQ interrupt [2:2] read-only EP1SPK_INT EP1SPK interrupt [3:3] read-only EP2DRQ_INT EP2DRQ interrupt [4:4] read-only EP2SPK_INT EP2SPK interrupt [5:5] read-only INTR_USBHOST Interrupt USB Host Register 0x940 32 read-write 0x0 0xFF SOFIRQ If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Does not issue an interrupt request by starting a SOF token. '1' : Issues an interrupt request by starting a SOF token. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [0:0] read-write DIRQ If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by detecting a device disconnection. '1' : Issues an interrupt request by detecting a device disconnection. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [1:1] read-write CNNIRQ If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by detecting a device connection. '1' : Issues an interrupt request by detecting a device connection. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [2:2] read-write CMPIRQ If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by token completion. '1' : Issues an interrupt request by token completion. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. - Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. [3:3] read-write URIRQ If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by USB bus resetting. '1' : Issues an interrupt request by USB bus resetting. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [4:4] read-write RWKIRQ If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by restart. '1' : Issues an interrupt request by restart. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [5:5] read-write RSVD_6 N/A [6:6] read-write TCAN If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored. '0' : Does not cancel token sending. '1' : Cancels token sending. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. [7:7] read-write INTR_USBHOST_SET Interrupt USB Host Set Register 0x944 32 read-write 0x0 0xFF SOFIRQS This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [0:0] read-write DIRQS This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [1:1] read-write CNNIRQS This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [2:2] read-write CMPIRQS This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [3:3] read-write URIRQS This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [4:4] read-write RWKIRQS This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. [5:5] read-write RSVD_6 N/A [6:6] read-write TCANS This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. [7:7] read-write INTR_USBHOST_MASK Interrupt USB Host Mask Register 0x948 32 read-write 0x0 0xFF SOFIRQM This bit masks the interrupt by SOF flag. '0' : Disables '1' : Enables [0:0] read-write DIRQM This bit masks the interrupt by DIRQ flag. '0' : Disables '1' : Enables [1:1] read-write CNNIRQM This bit masks the interrupt by CNNIRQ flag. '0' : Disables '1' : Enables [2:2] read-write CMPIRQM This bit masks the interrupt by CMPIRQ flag. '0' : Disables '1' : Enables [3:3] read-write URIRQM This bit masks the interrupt by URIRQ flag. '0' : Disables '1' : Enables [4:4] read-write RWKIRQM This bit masks the interrupt by RWKIRQ flag. '0' : Disables '1' : Enables [5:5] read-write RSVD_6 N/A [6:6] read-write TCANM This bit masks the interrupt by TCAN flag. '0' : Disables '1' : Enables [7:7] read-write INTR_USBHOST_MASKED Interrupt USB Host Masked Register 0x94C 32 read-only 0x0 0xFF SOFIRQED This bit indicates the interrupt by SOF flag. '0' : Doesn't request the interrupt by SOF '1' : Request the interrupt by SOF [0:0] read-only DIRQED This bit indicates the interrupt by DIRQ flag. '0' : Doesn't request the interrupt by DIRQ '1' : Request the interrupt by DIRQ [1:1] read-only CNNIRQED This bit indicates the interrupt by CNNIRQ flag. '0' : Doesn't request the interrupt by CNNIRQ '1' : Request the interrupt by CNNIRQ [2:2] read-only CMPIRQED This bit indicates the interrupt by CMPIRQ flag. '0' : Doesn't request the interrupt by CMPIRQ '1' : Request the interrupt by CMPIRQ [3:3] read-only URIRQED This bit indicates the interrupt by URIRQ flag. '0' : Doesn't request the interrupt by URIRQ '1' : Request the interrupt by URIRQ [4:4] read-only RWKIRQED This bit indicates the interrupt by RWKIRQ flag. '0' : Doesn't request the interrupt by RWKIRQ '1' : Request the interrupt by RWKIRQ [5:5] read-only RSVD_6 N/A [6:6] read-only TCANED This bit indicates the interrupt by TCAN flag. '0' : Doesn't request the interrupt by TCAN '1' : Request the interrupt by TCAN [7:7] read-only INTR_HOST_EP Interrupt USB Host Endpoint Register 0xA00 32 read-write 0x0 0x3C EP1DRQ This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. [2:2] read-write EP1SPK This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The EP1SPK bit is not set during data transfer in the OUT direction. [3:3] read-write EP2DRQ This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. [4:4] read-write EP2SPK This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The SPK bit is not set during data transfer in the OUT direction. [5:5] read-write INTR_HOST_EP_SET Interrupt USB Host Endpoint Set Register 0xA04 32 read-write 0x0 0x3C EP1DRQS This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. [2:2] read-write EP1SPKS This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. [3:3] read-write EP2DRQS This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. [4:4] read-write EP2SPKS This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. [5:5] read-write INTR_HOST_EP_MASK Interrupt USB Host Endpoint Mask Register 0xA08 32 read-write 0x0 0x3C EP1DRQM This bit masks the interrupt by EP1DRQ flag. '0' : Disables '1' : Enables [2:2] read-write EP1SPKM This bit masks the interrupt by EP1SPK flag. '0' : Disables '1' : Enables [3:3] read-write EP2DRQM This bit masks the interrupt by EP2DRQ flag. '0' : Disables '1' : Enables [4:4] read-write EP2SPKM This bit masks the interrupt by EP2SPK flag. '0' : Disables '1' : Enables [5:5] read-write INTR_HOST_EP_MASKED Interrupt USB Host Endpoint Masked Register 0xA0C 32 read-only 0x0 0x3C EP1DRQED This bit indicates the interrupt by EP1DRQ flag. '0' : Doesn't request the interrupt by EP1DRQ '1' : Request the interrupt by EP1DRQ [2:2] read-only EP1SPKED This bit indicates the interrupt by EP1SPK flag. '0' : Doesn't request the interrupt by EP1SPK '1' : Request the interrupt by EP1SPK [3:3] read-only EP2DRQED This bit indicates the interrupt by EP2DRQ flag. '0' : Doesn't request the interrupt by EP2DRQ '1' : Request the interrupt by EP2DRQ [4:4] read-only EP2SPKED This bit indicates the interrupt by EP2SPK flag. '0' : Doesn't request the interrupt by EP2SPK '1' : Request the interrupt by EP2SPK [5:5] read-only HOST_DMA_ENBL Host DMA Enable Register 0xB00 32 read-write 0x0 0xC DM_EP1DRQE This bit enables DMA Request by EP1DRQ. '0' : Disable '1' : Enable [2:2] read-write DM_EP2DRQE This bit enables DMA Request by EP2DRQ. '0' : Disable '1' : Enable [3:3] read-write HOST_EP1_BLK Host Endpoint 1 Block Register 0xB20 32 read-write 0x0 0xFFFF0000 BLK_NUM Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') [31:16] read-write HOST_EP2_BLK Host Endpoint 2 Block Register 0xB30 32 read-write 0x0 0xFFFF0000 BLK_NUM Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') [31:16] read-write SMIF0 Serial Memory Interface SMIF 0x40420000 0 65536 registers CTL Control 0x0 32 read-write 0x3000 0x81073001 XIP_MODE Mode of operation. Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. [0:0] read-write MMIO_MODE '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. 0 XIP_MODE 1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. 1 CLOCK_IF_RX_SEL Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. '0': 'spi_clk_out' (internal clock) '1': !'spi_clk_out' (internal clock) '2': 'spi_clk_in' (feedback clock) '3': !'spi_clk_in' (feedback clock) Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'. [13:12] read-write DESELECT_DELAY Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: '0': 1 interface clock cycle. '1': 2 interface clock cycles. '2': 3 interface clock cycles. '3': 4 interface clock cycles. '4': 5 interface clock cycles. '5': 6 interface clock cycles. '6': 7 interface clock cycles. '7': 8 interface clock cycles. During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. [18:16] read-write BLOCK Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. This field is not used for test controller accesses. [24:24] read-write BUS_ERROR 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). 0 WAIT_STATES 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). 1 ENABLED IP enable: '0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. '1': Enabled. Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. [31:31] read-write DISABLED N/A 0 ENABLED N/A 1 STATUS Status 0x4 32 read-only 0x0 0x80000000 BUSY Cache, cryptography, XIP, device interface or any other logic busy in the IP: '0': not busy '1': busy When BUSY is '0', the IP can be safely disabled without: - the potential loss of transient write data. - the potential risk of aborting an inflight SPI device interface transfer. When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. [31:31] read-only TX_CMD_FIFO_STATUS Transmitter command FIFO status 0x44 32 read-only 0x0 0x7 USED3 Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. [2:0] read-only TX_CMD_FIFO_WR Transmitter command FIFO write 0x50 32 write-only 0x0 0xFFFFF DATA20 Command data. The higher two bits DATA[19:18] specify the specific command '0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. - DATA[17:16] specifies the width of the data transfer: - '0': 1 bit/cycle (single data transfer). - '1': 2 bits/cycle (dual data transfer). - '2': 4 bits/cycle (quad data transfer). - '3': 8 bits/cycle (octal data transfer). - DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. - DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. - '0': device deselected - '1': device selected - DATA[7:0] specifies the transmitted Byte. '1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. '2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. '3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. - DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. [19:0] write-only TX_DATA_FIFO_CTL Transmitter data FIFO control 0x80 32 read-write 0x0 0x7 TRIGGER_LEVEL Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. [2:0] read-write TX_DATA_FIFO_STATUS Transmitter data FIFO status 0x84 32 read-only 0x0 0xF USED4 Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. [3:0] read-only TX_DATA_FIFO_WR1 Transmitter data FIFO write 0x90 32 write-only 0x0 0xFF DATA0 TX data (written to TX data FIFO). [7:0] write-only TX_DATA_FIFO_WR2 Transmitter data FIFO write 0x94 32 write-only 0x0 0xFFFF DATA0 TX data (written to TX data FIFO, first byte). [7:0] write-only DATA1 TX data (written to TX data FIFO, second byte). [15:8] write-only TX_DATA_FIFO_WR4 Transmitter data FIFO write 0x98 32 write-only 0x0 0xFFFFFFFF DATA0 TX data (written to TX data FIFO, first byte). [7:0] write-only DATA1 TX data (written to TX data FIFO, second byte). [15:8] write-only DATA2 TX data (written to TX data FIFO, third byte). [23:16] write-only DATA3 TX data (written to TX data FIFO, fourth byte). [31:24] write-only RX_DATA_FIFO_CTL Receiver data FIFO control 0xC0 32 read-write 0x0 0x7 TRIGGER_LEVEL Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. [2:0] read-write RX_DATA_FIFO_STATUS Receiver data FIFO status 0xC4 32 read-only 0x0 0xF USED4 Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. [3:0] read-only RX_DATA_FIFO_RD1 Receiver data FIFO read 0xD0 32 read-only 0x0 0xFF DATA0 RX data (read from RX data FIFO). [7:0] read-only RX_DATA_FIFO_RD2 Receiver data FIFO read 0xD4 32 read-only 0x0 0xFFFF DATA0 RX data (read from RX data FIFO, first byte). [7:0] read-only DATA1 RX data (read from RX data FIFO, second byte). [15:8] read-only RX_DATA_FIFO_RD4 Receiver data FIFO read 0xD8 32 read-only 0x0 0xFFFFFFFF DATA0 RX data (read from RX data FIFO, first byte). [7:0] read-only DATA1 RX data (read from RX data FIFO, second byte). [15:8] read-only DATA2 RX data (read from RX data FIFO, third byte). [23:16] read-only DATA3 RX data (read from RX data FIFO, fourth byte). [31:24] read-only RX_DATA_FIFO_RD1_SILENT Receiver data FIFO silent read 0xE0 32 read-only 0x0 0xFF DATA0 RX data (read from RX data FIFO). [7:0] read-only SLOW_CA_CTL Slow cache control 0x100 32 read-write 0xC0000000 0xC3030000 WAY Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2. [17:16] read-write SET_ADDR Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2. [25:24] read-write PREF_EN Prefetch enable: '0': Disabled. '1': Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. [30:30] read-write ENABLED Cache enable: '0': Disabled. '1': Enabled. [31:31] read-write SLOW_CA_CMD Slow cache command 0x108 32 read-write 0x0 0x1 INV Cache and prefetch buffer invalidation. SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. Note, A write access will invalidate the prefetch buffer automatically in hardware. A write access should invalidate both fast and slow caches, by firmware. Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. [0:0] read-write FAST_CA_CTL Fast cache control 0x180 32 read-write 0xC0000000 0xC3030000 WAY See SLOW_CA_CTL.WAY. [17:16] read-write SET_ADDR See SLOW_CA_CTL.SET_ADDR. [25:24] read-write PREF_EN See SLOW_CA_CTL.PREF_EN. [30:30] read-write ENABLED See SLOW_CA_CTL.ENABLED. [31:31] read-write FAST_CA_CMD Fast cache command 0x188 32 read-write 0x0 0x1 INV See SLOW_CA_CMD.INV. [0:0] read-write CRYPTO_CMD Cryptography Command 0x200 32 read-write 0x0 0x1 START SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. The operation takes roughly 13 clk_hf clock cycles. Note: An operation can only be started in MMIO_MODE. [0:0] read-write CRYPTO_INPUT0 Cryptography input 0 0x220 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT1 Cryptography input 1 0x224 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT2 Cryptography input 2 0x228 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. [31:0] read-write CRYPTO_INPUT3 Cryptography input 3 0x22C 32 read-write 0x0 0x0 INPUT Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. [31:0] read-write CRYPTO_KEY0 Cryptography key 0 0x240 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. [31:0] write-only CRYPTO_KEY1 Cryptography key 1 0x244 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. [31:0] write-only CRYPTO_KEY2 Cryptography key 2 0x248 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. [31:0] write-only CRYPTO_KEY3 Cryptography key 3 0x24C 32 write-only 0x0 0x0 KEY Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. [31:0] write-only CRYPTO_OUTPUT0 Cryptography output 0 0x260 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT1 Cryptography output 1 0x264 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT2 Cryptography output 2 0x268 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. [31:0] read-write CRYPTO_OUTPUT3 Cryptography output 3 0x26C 32 read-write 0x0 0x0 OUTPUT Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. [31:0] read-write INTR Interrupt register 0x7C0 32 read-write 0x0 0x3F TR_TX_REQ Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. [0:0] read-write TR_RX_REQ Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. [1:1] read-write XIP_ALIGNMENT_ERROR Activated in XIP mode, if: - The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. - The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. [2:2] read-write TX_CMD_FIFO_OVERFLOW Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. [3:3] read-write TX_DATA_FIFO_OVERFLOW Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. [5:5] read-write INTR_SET Interrupt set register 0x7C4 32 read-write 0x0 0x3F TR_TX_REQ Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write TR_RX_REQ Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write XIP_ALIGNMENT_ERROR Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write TX_CMD_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write TX_DATA_FIFO_OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write INTR_MASK Interrupt mask register 0x7C8 32 read-write 0x0 0x3F TR_TX_REQ Mask bit for corresponding bit in interrupt request register. [0:0] read-write TR_RX_REQ Mask bit for corresponding bit in interrupt request register. [1:1] read-write XIP_ALIGNMENT_ERROR Mask bit for corresponding bit in interrupt request register. [2:2] read-write TX_CMD_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [3:3] read-write TX_DATA_FIFO_OVERFLOW Mask bit for corresponding bit in interrupt request register. [4:4] read-write RX_DATA_FIFO_UNDERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write INTR_MASKED Interrupt masked register 0x7CC 32 read-only 0x0 0x3F TR_TX_REQ Logical and of corresponding request and mask bits. [0:0] read-only TR_RX_REQ Logical and of corresponding request and mask bits. [1:1] read-only XIP_ALIGNMENT_ERROR Logical and of corresponding request and mask bits. [2:2] read-only TX_CMD_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [3:3] read-only TX_DATA_FIFO_OVERFLOW Logical and of corresponding request and mask bits. [4:4] read-only RX_DATA_FIFO_UNDERFLOW Logical and of corresponding request and mask bits. [5:5] read-only 3 128 DEVICE[%s] Device (only used in XIP mode) 0x00000800 CTL Control 0x0 32 read-write 0x0 0x80030101 WR_EN Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device. [0:0] read-write CRYPTO_EN Cryptography on read/write accesses: '0': disabled. '1': enabled. [8:8] read-write DATA_SEL Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): '0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. '1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. '2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. '3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. [17:16] read-write ENABLED Device enable: '0': Disabled. '1': Enabled. [31:31] read-write ADDR Device region base address 0x8 32 read-write 0x0 0x0 ADDR Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. [31:8] read-write MASK Device region mask 0xC 32 read-write 0x0 0x0 MASK Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error. [31:8] read-write ADDR_CTL Address control 0x20 32 read-write 0x0 0x103 SIZE2 Specifies the size of the XIP device address in Bytes: '0': 1 Byte address. '1': 2 Byte address. '2': 3 Byte address. '3': 4 Byte address. The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. [1:0] read-write DIV2 Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. [8:8] read-write RD_CMD_CTL Read command control 0x40 32 read-write 0x0 0x800300FF CODE Command byte code. [7:0] read-write WIDTH Width of data transfer: '0': 1 bit/cycle (single data transfer). '1': 2 bits/cycle (dual data transfer). '2': 4 bits/cycle (quad data transfer). '3': 8 bits/cycle (octal data transfer). [17:16] read-write PRESENT Presence of command field: '0': not present '1': present [31:31] read-write RD_ADDR_CTL Read address control 0x44 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write RD_MODE_CTL Read mode control 0x48 32 read-write 0x0 0x800300FF CODE Mode byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of mode field: '0': not present '1': present [31:31] read-write RD_DUMMY_CTL Read dummy control 0x4C 32 read-write 0x0 0x8000001F SIZE5 Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes! [4:0] read-write PRESENT Presence of dummy cycles: '0': not present '1': present [31:31] read-write RD_DATA_CTL Read data control 0x50 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write WR_CMD_CTL Write command control 0x60 32 read-write 0x0 0x800300FF CODE Command byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of command field: '0': not present '1': present [31:31] read-write WR_ADDR_CTL Write address control 0x64 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write WR_MODE_CTL Write mode control 0x68 32 read-write 0x0 0x800300FF CODE Mode byte code. [7:0] read-write WIDTH Width of transfer. [17:16] read-write PRESENT Presence of mode field: '0': not present '1': present [31:31] read-write WR_DUMMY_CTL Write dummy control 0x6C 32 read-write 0x0 0x8000001F SIZE5 Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. [4:0] read-write PRESENT Presence of dummy cycles: '0': not present '1': present [31:31] read-write WR_DATA_CTL Write data control 0x70 32 read-write 0x0 0x30000 WIDTH Width of transfer. [17:16] read-write CANFD0 CAN Controller CANFD 0x40520000 0 131072 registers CH FIFO wrapper around M_TTCAN 3PIP, to enable DMA 0x00000000 M_TTCAN TTCAN 3PIP, includes FD 0x00000000 CREL Core Release Register 0x0 32 read-only 0x32380609 0xFFFFFFFF DAY Time Stamp Day Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [7:0] read-only MON Time Stamp Month Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [15:8] read-only YEAR Time Stamp Year One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. [19:16] read-only SUBSTEP Sub-step of Core Release One digit, BCD-coded. [23:20] read-only STEP Step of Core Release One digit, BCD-coded. [27:24] read-only REL Core Release One digit, BCD-coded. [31:28] read-only ENDN Endian Register 0x4 32 read-only 0x87654321 0xFFFFFFFF ETV Endianness Test Value The endianness test value is 0x87654321. [31:0] read-only DBTP Data Bit Timing & Prescaler Register 0xC 32 read-write 0xA33 0x9F1FFF DSJW Data (Re)Synchronization Jump Width 0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [3:0] read-write DTSEG2 Data time segment after sample point 0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [7:4] read-write DTSEG1 Data time segment before sample point 0x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [12:8] read-write DBRP Data Bit Rate Prescaler 0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [20:16] read-write TDC Transmitter Delay Compensation 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled [23:23] read-write TEST Test Register 0x10 32 read-write 0x0 0x7F TAM ASC is not supported by M_TTCAN Test ASC Multiplexer Control Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE 0= Level at pin m_ttcan_ascm controlled by FSE 1= Level at pin m_ttcan_ascm = '1' [0:0] read-write TAT ASC is not supported by M_TTCAN Test ASC Transmit Control Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE 0= Level at pin m_ttcan_asct controlled by FSE 1= Level at pin m_ttcan_asct = '1' [1:1] read-write CAM ASC is not supported by M_TTCAN Check ASC Multiplexer Control Monitors level at output pin m_ttcan_ascm. 0= Output pin m_ttcan_ascm = '0' 1= Output pin m_ttcan_ascm = '1' [2:2] read-write CAT ASC is not supported by M_TTCAN Check ASC Transmit Control Monitors level at output pin m_ttcan_asct. 0= Output pin m_ttcan_asct = '0' [3:3] read-write LBCK Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled (see Section 3.1.9, Test Modes) [4:4] read-write TX Control of Transmit Pin 00 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_ttcan_tx 10 Dominant ('0') level at pin m_ttcan_tx 11 Recessive ('1') at pin m_ttcan_tx [6:5] read-write RX Receive Pin Monitors the actual value of pin m_ttcan_rx 0= The CAN bus is dominant (m_ttcan_rx = '0') 1= The CAN bus is recessive (m_ttcan_rx = '1') [7:7] read-only RWD RAM Watchdog 0x14 32 read-write 0x0 0xFFFF WDC Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled. [7:0] read-write WDV Watchdog Value Actual Message RAM Watchdog Counter Value. [15:8] read-only CCCR CC Control Register 0x18 32 read-write 0x1 0xF3FF INIT Initialization 0= Normal Operation 1= Initialization is started [0:0] read-write CCE Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') [1:1] read-write ASM Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active [2:2] read-write CSA Clock Stop Acknowledge 0= No clock stop acknowledged 1= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk [3:3] read-write CSR Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead. 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. [4:4] read-write MON_ Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled [5:5] read-write DAR Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled [6:6] read-write TEST Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled [7:7] read-write FDOE FD Operation Enable 0= FD operation disabled 1= FD operation enabled [8:8] read-write BRSE Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled [9:9] read-write PXHD Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled [12:12] read-write EFBI Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization [13:13] read-write TXP Transmit Pause If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled [14:14] read-write NISO Non ISO Operation If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD [15:15] read-write NBTP Nominal Bit Timing & Prescaler Register 0x1C 32 read-write 0x6000A03 0xFFFFFF7F NTSEG2 Nominal Time segment after sample point 0x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [6:0] read-write NTSEG1 Nominal Time segment before sample point 0x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. [15:8] read-write NBRP Nominal Bit Rate Prescaler 0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [24:16] read-write NSJW Nominal (Re)Synchronization Jump Width 0x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [31:25] read-write TSCC Timestamp Counter Configuration 0x20 32 read-write 0x0 0xF0003 TSS Timestamp Select, should always be set to external timestamp counter 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as '00' [1:0] read-write TCP Timestamp Counter Prescaler (still used for TOCC) 0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1...16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. [19:16] read-write TSCV Timestamp Counter Value 0x24 32 read-write 0x0 0xFFFF TSC Timestamp Counter, not used for M_TTCAN The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external Timestamp Counter value. A write access has no impact. [15:0] read-write TOCC Timeout Counter Configuration 0x28 32 read-write 0xFFFF0000 0xFFFF0007 ETOC Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled [0:0] read-write TOS Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1 [2:1] read-write TOP Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period. [31:16] read-write TOCV Timeout Counter Value 0x2C 32 read-write 0xFFFF 0xFFFF TOC Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. [15:0] read-write ECR Error Counter Register 0x40 32 read-only 0x0 0xFFFFFF TEC Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255 [7:0] read-only REC Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127 [14:8] read-only RP Receive Error Passive 0= The Receive Error Counter is below the error passive level of 128 1= The Receive Error Counter has reached the error passive level of 128 [15:15] read-only CEL CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. [23:16] read-only PSR Protocol Status Register 0x44 32 read-only 0x707 0x7F7FFF LEC Last Error Code, Set on Read0 The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2= Form Error: A fixed format part of a received frame has the wrong format. 3= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node. 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. [2:0] read-only ACT Activity Monitors the module's CAN communication state. 00= Synchronizing - node is synchronizing on CAN communication 01= Idle - node is neither receiver nor transmitter 10= Receiver - node is operating as receiver 11= Transmitter - node is operating as transmitter [4:3] read-only EP Error Passive 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1= The M_CAN is in the Error_Passive state [5:5] read-only EW Warning Status 0= Both error counters are below the Error_Warning limit of 96 1= At least one of error counter has reached the Error_Warning limit of 96 [6:6] read-only BO Bus_Off Status 0= The M_CAN is not Bus_Off 1= The M_CAN is in Bus_Off state [7:7] read-only DLEC Data Phase Last Error Code , Set on Read Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. [10:8] read-only RESI ESI flag of last received CAN FD Message , Reset on Read This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its ESI flag set 1= Last received CAN FD message had its ESI flag set [11:11] read-only RBRS BRS flag of last received CAN FD Message , Reset on Read This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its BRS flag set 1= Last received CAN FD message had its BRS flag set [12:12] read-only RFDF Received a CAN FD Message , Reset on Read This bit is set independent of acceptance filtering. 0= Since this bit was reset by the CPU, no CAN FD message has been received 1= Message in CAN FD format with FDF flag set has been received [13:13] read-only PXE Protocol Exception Event , Reset on Read 0= No protocol exception event occurred since last read access 1= Protocol exception event occurred [14:14] read-only TDCV Transmitter Delay Compensation Value 0x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. [22:16] read-only TDCR Transmitter Delay Compensation Register 0x48 32 read-write 0x0 0x7F7F TDCF Transmitter Delay Compensation Filter Window Length 0x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq [6:0] read-write TDCO Transmitter Delay Compensation Offset 0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq. [14:8] read-write IR Interrupt Register 0x50 32 read-write 0x0 0x3FFFFFFF RF0N Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0 [0:0] read-write RF0W Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark [1:1] read-write RF0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full [2:2] read-write RF0L_ Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero [3:3] read-write RF1N Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1 [4:4] read-write RF1W Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark [5:5] read-write RF1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full [6:6] read-write RF1L_ Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero [7:7] read-write HPM High Priority Message 0= No high priority message received 1= High priority message received [8:8] read-write TC Transmission Completed 0= No transmission completed 1= Transmission completed [9:9] read-write TCF Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished [10:10] read-write TFE Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty [11:11] read-write TEFN Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element [12:12] read-write TEFW Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark [13:13] read-write TEFF Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full [14:14] read-write TEFL_ Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero [15:15] read-write TSW Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around [16:16] read-write MRAF Message RAM Access Failure The flag is set, when the Rx Handler - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. - was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred [17:17] read-write TOO Timeout Occurred 0= No timeout 1= Timeout reached [18:18] read-write DRX Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into a Rx Buffer [19:19] read-write BEC M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0. Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC) [20:20] read-write BEU Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic) [21:21] read-write ELO Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred [22:22] read-write EP_ Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed [23:23] read-write EW_ Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed [24:24] read-write BO_ Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed [25:25] read-write WDI Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY [26:26] read-write PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC != 0,7) [27:27] read-write PED Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC != 0,7) [28:28] read-write ARA N/A [29:29] read-write IE Interrupt Enable 0x54 32 read-write 0x0 0x3FFFFFFF RF0NE Rx FIFO 0 New Message Interrupt Enable [0:0] read-write RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable [1:1] read-write RF0FE Rx FIFO 0 Full Interrupt Enable [2:2] read-write RF0LE Rx FIFO 0 Message Lost Interrupt Enable [3:3] read-write RF1NE Rx FIFO 1 New Message Interrupt Enable [4:4] read-write RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable [5:5] read-write RF1FE Rx FIFO 1 Full Interrupt Enable [6:6] read-write RF1LE Rx FIFO 1 Message Lost Interrupt Enable [7:7] read-write HPME High Priority Message Interrupt Enable [8:8] read-write TCE Transmission Completed Interrupt Enable [9:9] read-write TCFE Transmission Cancellation Finished Interrupt Enable [10:10] read-write TFEE Tx FIFO Empty Interrupt Enable [11:11] read-write TEFNE Tx Event FIDO New Entry Interrupt Enable [12:12] read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable [13:13] read-write TEFFE Tx Event FIFO Full Interrupt Enable [14:14] read-write TEFLE Tx Event FIFO Event Lost Interrupt Enable [15:15] read-write TSWE Timestamp Wraparound Interrupt Enable [16:16] read-write MRAFE Message RAM Access Failure Interrupt Enable [17:17] read-write TOOE Timeout Occurred Interrupt Enable [18:18] read-write DRXE Message stored to Dedicated Rx Buffer Interrupt Enable [19:19] read-write BECE Bit Error Corrected Interrupt Enable (not used in M_TTCAN) [20:20] read-write BEUE Bit Error Uncorrected Interrupt Enable [21:21] read-write ELOE Error Logging Overflow Interrupt Enable [22:22] read-write EPE Error Passive Interrupt Enable [23:23] read-write EWE Warning Status Interrupt Enable [24:24] read-write BOE Bus_Off Status Interrupt Enable [25:25] read-write WDIE Watchdog Interrupt Enable [26:26] read-write PEAE Protocol Error in Arbitration Phase Enable [27:27] read-write PEDE Protocol Error in Data Phase Enable [28:28] read-write ARAE N/A [29:29] read-write ILS Interrupt Line Select 0x58 32 read-write 0x0 0x3FFFFFFF RF0NL Rx FIFO 0 New Message Interrupt Line [0:0] read-write RF0WL Rx FIFO 0 Watermark Reached Interrupt Line [1:1] read-write RF0FL Rx FIFO 0 Full Interrupt Line [2:2] read-write RF0LL Rx FIFO 0 Message Lost Interrupt Line [3:3] read-write RF1NL Rx FIFO 1 New Message Interrupt Line [4:4] read-write RF1WL Rx FIFO 1 Watermark Reached Interrupt Line [5:5] read-write RF1FL Rx FIFO 1 Full Interrupt Line [6:6] read-write RF1LL Rx FIFO 1 Message Lost Interrupt Line [7:7] read-write HPML High Priority Message Interrupt Line [8:8] read-write TCL Transmission Completed Interrupt Line [9:9] read-write TCFL Transmission Cancellation Finished Interrupt Line [10:10] read-write TFEL Tx FIFO Empty Interrupt Line [11:11] read-write TEFNL Tx Event FIFO New Entry Interrupt Line [12:12] read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line [13:13] read-write TEFFL Tx Event FIFO Full Interrupt Line [14:14] read-write TEFLL Tx Event FIFO Event Lost Interrupt Line [15:15] read-write TSWL Timestamp Wraparound Interrupt Line [16:16] read-write MRAFL Message RAM Access Failure Interrupt Line [17:17] read-write TOOL Timeout Occurred Interrupt Line [18:18] read-write DRXL Message stored to Dedicated Rx Buffer Interrupt Line [19:19] read-write BECL Bit Error Corrected Interrupt Line (not used in M_TTCAN) [20:20] read-write BEUL Bit Error Uncorrected Interrupt Line [21:21] read-write ELOL Error Logging Overflow Interrupt Line [22:22] read-write EPL Error Passive Interrupt Line [23:23] read-write EWL Warning Status Interrupt Line [24:24] read-write BOL Bus_Off Status Interrupt Line [25:25] read-write WDIL Watchdog Interrupt Line [26:26] read-write PEAL Protocol Error in Arbitration Phase Line [27:27] read-write PEDL Protocol Error in Data Phase Line [28:28] read-write ARAL N/A [29:29] read-write ILE Interrupt Line Enable 0x5C 32 read-write 0x0 0x3 EINT0 Enable Interrupt Line 0 0= Interrupt line m_ttcan_int0 disabled 1= Interrupt line m_ttcan_int0 enabled [0:0] read-write EINT1 Enable Interrupt Line 1 0= Interrupt line m_ttcan_int1 disabled 1= Interrupt line m_ttcan_int1 enabled [1:1] read-write GFC Global Filter Configuration 0x80 32 read-write 0x0 0x3F RRFE Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs [0:0] read-write RRFS Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs [1:1] read-write ANFE Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject [3:2] read-write ANFS Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject [5:4] read-write SIDFC Standard ID Filter Configuration 0x84 32 read-write 0x0 0xFFFFFC FLSSA Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see Figure 2). [15:2] read-write LSS List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements 128= Values greater than 128 are interpreted as 128 [23:16] read-write XIDFC Extended ID Filter Configuration 0x88 32 read-write 0x0 0x7FFFFC FLESA Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address, see Figure 2). [15:2] read-write LSE List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements 64= Values greater than 64 are interpreted as 64 [22:16] read-write XIDAM Extended ID AND Mask 0x90 32 read-write 0x1FFFFFFF 0x1FFFFFFF EIDM Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. [28:0] read-write HPMS High Priority Message Status 0x94 32 read-only 0x0 0xFFFF BIDX Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'. [5:0] read-only MSI Message Storage Indicator 00= No FIFO selected 01= FIFO message lost 10= Message stored in FIFO 0 11= Message stored in FIFO 1 [7:6] read-only FIDX Filter Index Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. [14:8] read-only FLST Filter List Indicates the filter list of the matching filter element. 0= Standard Filter List 1= Extended Filter List [15:15] read-only NDAT1 New Data 1 0x98 32 read-write 0x0 0xFFFFFFFF ND New Data The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message [31:0] read-write NDAT2 New Data 2 0x9C 32 read-write 0x0 0xFFFFFFFF ND New Data The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message [31:0] read-write RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write 0x0 0xFF7FFFFC F0SA Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2). [15:2] read-write F0S Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements 64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1 [22:16] read-write F0WM Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) 64= Watermark interrupt disabled [30:24] read-write F0OM FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode [31:31] read-write RXF0S Rx FIFO 0 Status 0xA4 32 read-only 0x0 0x33F3F7F F0FL Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64. When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected. [6:0] read-only F0GI Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63. This field is updated by the software writing to RXF0A.F0AI. When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected. [13:8] read-only F0PI Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63. [21:16] read-only F0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full [24:24] read-only RF0L Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero [25:25] read-only RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write 0x0 0x3F F0AI Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. [5:0] read-write RXBC Rx Buffer Configuration 0xAC 32 read-write 0x0 0xFFFC RBSA Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). Also used to reference debug messages A,B,C. [15:2] read-write RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write 0x0 0xFF7FFFFC F1SA Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2). [15:2] read-write F1S Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements 64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1 [22:16] read-write F1WM Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) 64= Watermark interrupt disabled [30:24] read-write F1OM FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode [31:31] read-write RXF1S Rx FIFO 1 Status 0xB4 32 read-only 0x0 0xC33F3F7F F1FL Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64. When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected. [6:0] read-only F1GI Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63. This field is updated by the software writing to RXF1A.F1AI. When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected. [13:8] read-only F1PI Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63. [21:16] read-only F1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full [24:24] read-only RF1L Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero [25:25] read-only DMS Debug Message Status 00= Idle state, wait for reception of debug messages, DMA request is cleared 01= Debug message A received 10= Debug messages A, B received 11= Debug messages A, B, C received, DMA request is set [31:30] read-only RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write 0x0 0x3F F1AI Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. [5:0] read-write RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write 0x0 0x777 F0DS Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [2:0] read-write F1DS Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [6:4] read-write RBDS Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [10:8] read-write TXBC Tx Buffer Configuration 0xC0 32 read-write 0x0 0x7F3FFFFC TBSA Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). [15:2] read-write NDTB Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers 32= Values greater than 32 are interpreted as 32 [21:16] read-write TFQS Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue 32= Values greater than 32 are interpreted as 32 [29:24] read-write TFQM Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation [30:30] read-write TXFQS Tx FIFO/Queue Status 0xC4 32 read-only 0x0 0x3F1F3F TFFL Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1') [5:0] read-only TFGI Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured TXBC.TFQM = '1'). [12:8] read-only TFQPI Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31. [20:16] read-only TFQF Tx FIFO/Queue Full 0= Tx FIFO/Queue not full 1= Tx FIFO/Queue full [21:21] read-only TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write 0x0 0x7 TBDS Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field [2:0] read-write TXBRP Tx Buffer Request Pending 0xCC 32 read-only 0x0 0xFFFFFFFF TRP Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0= No transmission request pending 1= Transmission request pending [31:0] read-only TXBAR Tx Buffer Add Request 0xD0 32 read-write 0x0 0xFFFFFFFF AR Add Request Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added [31:0] read-write TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write 0x0 0xFFFFFFFF CR Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending [31:0] read-write TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only 0x0 0xFFFFFFFF TO Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0= No transmission occurred 1= Transmission occurred [31:0] read-only TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only 0x0 0xFFFFFFFF CF Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0= No transmit buffer cancellation 1= Transmit buffer cancellation finished [31:0] read-only TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write 0x0 0xFFFFFFFF TIE Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable [31:0] read-write TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write 0x0 0xFFFFFFFF CFIE Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled [31:0] read-write TXEFC Tx Event FIFO Configuration 0xF0 32 read-write 0x0 0x3F3FFFFC EFSA Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2). [15:2] read-write EFS Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements 32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1 [21:16] read-write EFWM Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) 32= Watermark interrupt disabled [29:24] read-write TXEFS Tx Event FIFO Status 0xF4 32 read-only 0x0 0x31F1F3F EFFL Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32. When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected. [5:0] read-only EFGI Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31. This field is updated by the software writing to TXEFA.EFAI. When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected. [12:8] read-only EFPI Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31. [20:16] read-only EFF Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full [24:24] read-only TEFL Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. [25:25] read-only TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write 0x0 0x1F EFAI Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. [4:0] read-write TTTMC TT Trigger Memory Configuration 0x100 32 read-write 0x0 0x7FFFFC TMSA Trigger Memory Start Address Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2). [15:2] read-write TME Trigger Memory Elements 0= No Trigger Memory 1-64= Number of Trigger Memory elements 64= Values greater than 64 are interpreted as 64 [22:16] read-write TTRMC TT Reference Message Configuration 0x104 32 read-write 0x0 0xDFFFFFFF RID Reference Identifier Identifier transmitted with reference message and used for reference message filtering. Standard or extended reference identifier depending on bit XTD. A standard identifier has to be written to ID[28:18]. [28:0] read-write XTD Extended Identifier 0= 11-bit standard identifier 1= 29-bit extended identifier [30:30] read-write RMPS Reference Message Payload Select Ignored in case of time slaves. 0= Reference message has no additional payload 1= The following elements are taken from Tx Buffer 0: Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB Level 1: bytes 2-8, Level 0,2: bytes 5-8) [31:31] read-write TTOCF TT Operation Configuration 0x108 32 read-write 0x10000 0x7FFFFFB OM Operation Mode 00= Event-driven CAN communication, default 01= TTCAN level 1 10= TTCAN level 2 11= TTCAN level 0 [1:0] read-write GEN Gap Enable 0= Strictly time-triggered operation 1= External event-synchronized time-triggered operation [3:3] read-write TM Time Master 0= Time Master function disabled 1= Potential Time Master [4:4] read-write LDSDL LD of Synchronization Deviation Limit The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = 2(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration. 0x0-7 LD of Synchronization Deviation Limit (SDL <= 32...4096) [7:5] read-write IRTO Initial Reference Trigger Offset 0x00-7F Positive offset, range from 0 to 127 [14:8] read-write EECS Enable External Clock Synchronization If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation. 0= External clock synchronization in TTCAN Level 0,2 disabled 1= External clock synchronization in TTCAN Level 0,2 enabled [15:15] read-write AWL Application Watchdog Limit The application watchdog can be disabled by programming AWL to 0x00. 0x00-FF Maximum time after which the application has to serve the application watchdog. The application watchdog is incremented once each 256 NTUs. [23:16] read-write EGTF Enable Global Time Filtering 0= Global time filtering in TTCAN Level 0,2 is disabled 1= Global time filtering in TTCAN Level 0,2 is enabled [24:24] read-write ECC Enable Clock Calibration 0= Automatic clock calibration in TTCAN Level 0,2 is disabled 1= Automatic clock calibration in TTCAN Level 0,2 is enabled [25:25] read-write EVTP Event Trigger Polarity 0= Rising edge trigger 1= Falling edge trigger [26:26] read-write TTMLM TT Matrix Limits 0x10C 32 read-write 0x0 0xFFF0FFF CCM N/A [5:0] read-write CSS N/A [7:6] read-write TXEW Tx Enable Window 0x0-F Length of Tx enable window, 1-16 NTU cycles [11:8] read-write ENTT Expected Number of Tx Triggers 0x000-FFF Expected number of Tx Triggers in one Matrix Cycle [27:16] read-write TURCF TUR Configuration 0x110 32 read-write 0x10000000 0xBFFFFFFF NCL Numerator Configuration Low Write access to the TUR Numerator Configuration Low is only possible during configuration with TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new value for NCL is written outside TT Configuration Mode, the new value takes effect when TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'. 0x0000-FFFF Numerator Configuration Low [15:0] read-write DC Denominator Configuration 0x0000 Illegal value 0x0001-3FFF Denominator Configuration [29:16] read-write ELT Enable Local Time 0= Local time is stopped, default 1= Local time is enabled [31:31] read-write TTOCN TT Operation Control 0x114 32 read-write 0x0 0xBFFF SGT Set Global time Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one Host clock period. The global time preset takes effect when the node transmits the next reference message with the Master_Ref_Mark modified by the preset value written to TTGTP. [0:0] read-write ECS External Clock Synchronization Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one Host clock period. The external clock synchronization takes effect at the start of the next basic cycle. [1:1] read-write SWP Stop Watch Polarity 0= Rising edge trigger 1= Falling edge trigger [2:2] read-write SWS Stop Watch Source 00= Stop Watch disabled 01= Actual value of cycle time is copied to TTCPT.SWV 10= Actual value of local time is copied to TTCPT.SWV 11= Actual value of global time is copied to TTCPT.SWV [4:3] read-write RTIE Register Time Mark Interrupt Pulse Enable Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent of the synchronization state. 0= Register Time Mark Interrupt output m_ttcan_rtp disabled 1= Register Time Mark Interrupt output m_ttcan_rtp enabled [5:5] read-write TMC Register Time Mark Compare 00= No Register Time Mark Interrupt generated 01= Register Time Mark Interrupt if Time Mark = cycle time 10= Register Time Mark Interrupt if Time Mark = local time 11= Register Time Mark Interrupt if Time Mark = global time [7:6] read-write TTIE Trigger Time Mark Interrupt Pulse Enable External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A trigger time mark interrupt pulse is generated when the trigger memory element becomes active, and the M_TTCAN is in synchronization state In_Schedule or In_Gap. 0= Trigger Time Mark Interrupt output m_ttcan_tmp disabled 1= Trigger Time Mark Interrupt output m_ttcan_tmp enabled [8:8] read-write GCS Gap Control Select 0= Gap control independent from m_ttcan_evt 1= Gap control by input pin m_ttcan_evt [9:9] read-write FGP Finish Gap Set by the CPU, reset by each reference message 0= No reference message requested 1= Application requested start of reference message [10:10] read-write TMG Time Mark Gap 0= Reset by each reference message 1= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated [11:11] read-write NIG Next is Gap This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for external event-synchronized time-triggered operation (TTOCF.GEN = '1') 0= No action, reset by reception of any reference message 1= Transmit next reference message with Next_is_Gap = '1' [12:12] read-write ESCN External Synchronization Control If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising edge at pin m_ttcan_evt (see Section 4.11). 0= External synchronization disabled 1= External synchronization enabled [13:13] read-write LCKC TT Operation Control Register Locked Set by a write access to register TTOCN. Reset when the updated configuration has been synchronized into the CAN clock domain. 0= Write access to TTOCN enabled 1= Write access to TTOCN locked [15:15] read-only TTGTP TT Global Time Preset 0x118 32 read-write 0x0 0xFFFFFFFF TP N/A [15:0] read-write CTP Cycle Time Target Phase CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11). 0x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected [31:16] read-write TTTMK TT Time Mark 0x11C 32 read-write 0x0 0x807FFFFF TM_ Time Mark 0x0000-FFFF Time Mark [15:0] read-write TICC Time Mark Cycle Code Cycle count for which the time mark is valid. 0b000000x valid for all cycles 0b000001c valid every second cycle at cycle count mod2 = c 0b00001cc valid every fourth cycle at cycle count mod4 = cc 0b0001ccc valid every eighth cycle at cycle count mod8 = ccc 0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc 0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc 0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc [22:16] read-write LCKM TT Time Mark Register Locked Always set by a write access to registers TTOCN. Set by write access to register TTTMK when TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain. 0= Write access to TTTMK enabled 1= Write access to TTTMK locked [31:31] read-only TTIR TT Interrupt Register 0x120 32 read-write 0x0 0x7FFFF SBC Start of Basic Cycle 0= No Basic Cycle started since bit has been reset 1= Basic Cycle started [0:0] read-write SMC Start of Matrix Cycle 0= No Matrix Cycle started since bit has been reset 1= Matrix Cycle started [1:1] read-write CSM_ Change of Synchronization Mode 0= No change in master to slave relation or schedule synchronization 1= Master to slave relation or schedule synchronization changed, also set when TTOST.SPL is reset [2:2] read-write SOG Start of Gap 0= No reference message seen with Next_is_Gap bit set 1= Reference message with Next_is_Gap bit set becomes valid [3:3] read-write RTMI Register Time Mark Interrupt Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent of the synchronization state. 0= Time mark not reached 1= Time mark reached [4:4] read-write TTMI Trigger Time Mark Event Internal Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set when the trigger memory element becomes active, and the M_TTCAN is in synchronization state In_Gap or In_Schedule. 0= Time mark not reached 1= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200) [5:5] read-write SWE Stop Watch Event 0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected 1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected [6:6] read-write GTW Global Time Wrap 0= No global time wrap occurred 1= Global time wrap from 0xFFFF to 0x0000 occurred [7:7] read-write GTD Global Time Discontinuity 0= No discontinuity of global time 1= Discontinuity of global time [8:8] read-write GTE Global Time Error Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only. 0= Synchronization deviation within limit 1= Synchronization deviation exceeded limit [9:9] read-write TXU Tx Count Underflow 0= Number of Tx Trigger as expected 1= Less Tx trigger than expected in one matrix cycle [10:10] read-write TXO Tx Count Overflow 0= Number of Tx Trigger as expected 1= More Tx trigger than expected in one matrix cycle [11:11] read-write SE1 Scheduling Error 1 0= No scheduling error 1 1= Scheduling error 1 occurred [12:12] read-write SE2 Scheduling Error 2 0= No scheduling error 2 1= Scheduling error 2 occurred [13:13] read-write ELC Error Level Changed Not set when error level changed during initialization. 0= No change in error level 1= Error level changed [14:14] read-write IWT Initialization Watch Trigger The initialization is restarted by resetting IWT. 0= No missing reference message during system startup 1= No system startup due to missing reference message [15:15] read-write WT Watch Trigger 0= No missing reference message 1= Missing reference message (Level 0: cycle time 0xFF00) [16:16] read-write AW Application Watchdog 0= Application watchdog served in time 1= Application watchdog not served in time [17:17] read-write CER Configuration Error Trigger out of order. 0= No error found in trigger list 1= Error found in trigger list [18:18] read-write TTIE TT Interrupt Enable 0x124 32 read-write 0x0 0x7FFFF SBCE Start of Basic Cycle Interrupt Enable [0:0] read-write SMCE Start of Matrix Cycle Interrupt Enable [1:1] read-write CSME Change of Synchronization Mode Interrupt Enable [2:2] read-write SOGE Start of Gap Interrupt Enable [3:3] read-write RTMIE Register Time Mark Interrupt Enable [4:4] read-write TTMIE Trigger Time Mark Event Internal Enable [5:5] read-write SWEE Stop Watch Event Interrupt Enable [6:6] read-write GTWE Global Time Wrap Interrupt Enable [7:7] read-write GTDE Global Time Discontinuity Interrupt Enable [8:8] read-write GTEE Global Time Error Interrupt Enable [9:9] read-write TXUE Tx Count Underflow Interrupt Enable [10:10] read-write TXOE Tx Count Overflow Interrupt Enable [11:11] read-write SE1E Scheduling Error 1 Interrupt Enable [12:12] read-write SE2E Scheduling Error 2 Interrupt Enable [13:13] read-write ELCE Change Error Level Interrupt Enable [14:14] read-write IWTE Initialization Watch Trigger Interrupt Enable [15:15] read-write WTE Watch Trigger Interrupt Enable [16:16] read-write AWE_ Application Watchdog Interrupt Enable [17:17] read-write CERE Configuration Error Interrupt Enable [18:18] read-write TTILS TT Interrupt Line Select 0x128 32 read-write 0x0 0x7FFFF SBCL Start of Basic Cycle Interrupt Line [0:0] read-write SMCL Start of Matrix Cycle Interrupt Line [1:1] read-write CSML Change of Synchronization Mode Interrupt Line [2:2] read-write SOGL Start of Gap Interrupt Line [3:3] read-write RTMIL Register Time Mark Interrupt Line [4:4] read-write TTMIL Trigger Time Mark Event Internal Line [5:5] read-write SWEL Stop Watch Event Interrupt Line [6:6] read-write GTWL Global Time Wrap Interrupt Line [7:7] read-write GTDL Global Time Discontinuity Interrupt Line [8:8] read-write GTEL Global Time Error Interrupt Line [9:9] read-write TXUL Tx Count Underflow Interrupt Line [10:10] read-write TXOL Tx Count Overflow Interrupt Line [11:11] read-write SE1L Scheduling Error 1 Interrupt Line [12:12] read-write SE2L Scheduling Error 2 Interrupt Line [13:13] read-write ELCL Change Error Level Interrupt Line [14:14] read-write IWTL Initialization Watch Trigger Interrupt Line [15:15] read-write WTL Watch Trigger Interrupt Line [16:16] read-write AWL_ Application Watchdog Interrupt Line [17:17] read-write CERL Configuration Error Interrupt Line [18:18] read-write TTOST TT Operation Status 0x12C 32 read-only 0x80 0xFFC0FFFF EL Error Level 00= Severity 0 - No Error 01= Severity 1 - Warning 10= Severity 2 - Error 11= Severity 3 - Severe Error [1:0] read-only MS Master State 00= Master_Off, no master properties relevant 01= Operating as Time Slave 10= Operating as Backup Time Master 11= Operating as current Time Master [3:2] read-only SYS Synchronization State 00= Out of Synchronization 01= Synchronizing to TTCAN communication 10= Schedule suspended by Gap (In_Gap) 11= Synchronized to schedule (In_Schedule) [5:4] read-only QGTP Quality of Global Time Phase Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'. 0= Global time not valid 1= Global time in phase with Time Master [6:6] read-only QCS Quality of Clock Speed Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'. 0= Local clock speed not synchronized to Time Master clock speed 1= Synchronization Deviation <= SDL [7:7] read-only RTO Reference Trigger Offset The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read. 0x00-FF Actual Reference Trigger offset value [15:8] read-only WGTD Wait for Global Time Discontinuity 0= No global time preset pending 1= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = '1' or after it received a reference message. [22:22] read-only GFI Gap Finished Indicator Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another node sending a reference message. 0= Reset at the end of each reference message 1= Gap finished by M_TTCAN [23:23] read-only TMP Time Master Priority 0x0-7 Priority of actual Time Master [26:24] read-only GSI Gap Started Indicator 0= No Gap in schedule, reset by each reference message and for all time slaves 1= Gap time after Basic Cycle has started [27:27] read-only WFE Wait for Event 0= No Gap announced, reset by a reference message with Next_is_Gap = '0' 1= Reference message with Next_is_Gap = '1' received [28:28] read-only AWE Application Watchdog Event The application watchdog is served by reading TTOST. When the watchdog is not served in time, bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring Mode. 0= Application Watchdog served in time 1= Failed to serve Application Watchdog in time [29:29] read-only WECS Wait for External Clock Synchronization 0= No external clock synchronization pending 1= Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle. [30:30] read-only SPL Schedule Phase Lock The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11). 0= Phase outside range 1= Phase inside range [31:31] read-only TURNA TUR Numerator Actual 0x130 32 read-only 0x10000 0x3FFFF NAV N/A [17:0] read-only TTLGT TT Local & Global Time 0x134 32 read-only 0x0 0xFFFFFFFF LT Local Time Non-fractional part of local time, incremented once each local NTU (see Section 4.5). 0x0000-FFFF Local time value of TTCAN node [15:0] read-only GT Global Time Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5). 0x0000-FFFF Global time value of TTCAN network [31:16] read-only TTCTC TT Cycle Time & Count 0x138 32 read-only 0x3F0000 0x3FFFFF CT Cycle Time Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5). 0x0000-FFFF Cycle time value of TTCAN Basic Cycle [15:0] read-only CC Cycle Count 0x00-3F Number of actual Basic Cycle in the System Matrix [21:16] read-only TTCPT TT Capture Time 0x13C 32 read-only 0x0 0xFFFF003F CCV Cycle Count Value Cycle count value captured together with SWV. 0x00-3F Captured cycle count value [5:0] read-only SWV Stop Watch Value On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE. 0x0000-FFFF Captured Stop Watch value [31:16] read-only TTCSM TT Cycle Sync Mark 0x140 32 read-only 0x0 0xFFFF CSM Cycle Sync Mark The Cycle Sync Mark is measured [15:0] read-only RXFTOP_CTL Receive FIFO Top control 0x180 32 read-write 0x0 0x3 F0TPE FIFO 0 Top Pointer Enable. This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter. This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1). When this logic is disabled a Read from RXFTOP0_DATA is undefined. [0:0] read-write F1TPE FIFO 1 Top Pointer Enable. [1:1] read-write RXFTOP0_STAT Receive FIFO 0 Top Status 0x1A0 32 read-only 0x0 0xFFFF F0TA Current FIFO 0 Top Address. This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC) FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC [15:0] read-only RXFTOP0_DATA Receive FIFO 0 Top Data 0x1A8 32 read-only 0x0 0x0 F0TD When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met: - M_TTCAN not being reconfigured (CCCR.CCE=0) - FIFO Top Pointer logic is enabled (FnTPE=1) - FIFO is not empty (FnFL!=0) The read side effect is as follows: - if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI - FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message) - the FIFO top address FnTA is incremented (with FIFO wrap around) When this logic is disabled (F0TPE=0) a Read from this register returns undefined data. [31:0] read-only RXFTOP1_STAT Receive FIFO 1 Top Status 0x1B0 32 read-only 0x0 0xFFFF F1TA See F0TA description [15:0] read-only RXFTOP1_DATA Receive FIFO 1 Top Data 0x1B8 32 read-only 0x0 0x0 F1TD See F0TD description [31:0] read-only CTL Global CAN control register 0x1000 32 read-write 0x0 0x800000FF STOP_REQ Clock Stop Request for each TTCAN IP . The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits. [7:0] read-write MRAM_OFF MRAM off 0= Default MRAM on (with MRAM retained in DeepSleep). 1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode. [31:31] read-write STATUS Global CAN status register 0x1004 32 read-only 0x0 0xFF STOP_ACK Clock Stop Acknowledge for each TTCAN IP. These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP. When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write [7:0] read-only INTR0_CAUSE Consolidated interrupt0 cause register 0x1010 32 read-only 0x0 0xFF INT0 Show pending m_ttcan_int0 of each channel [7:0] read-only INTR1_CAUSE Consolidated interrupt1 cause register 0x1014 32 read-only 0x0 0xFF INT1 Show pending m_ttcan_int1 of each channel [7:0] read-only TS_CTL Time Stamp control register 0x1020 32 read-write 0x0 0x8000FFFF PRESCALE Time Stamp counter prescale value. When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks. [15:0] read-write ENABLED Counter enable bit 0 = Count disabled. Stop counting up and keep the counter value 1 = Count enabled. Start counting up from the current value [31:31] read-write TS_CNT Time Stamp counter value 0x1024 32 read-write 0x0 0xFFFF VALUE The counter value of the Time Stamp Counter. When enabled this counter will count Time Stamp clock ticks from the pre-scaler. When written this counter and the pre-scaler will reset to 0 (write data is ignored). [15:0] read-write ECC_CTL ECC control 0x1080 32 read-write 0x0 0x10000 ECC_EN Enable ECC for CANFD SRAM When disabled also all error injection functionality is disabled. [16:16] read-write ECC_ERR_INJ ECC error injection 0x1084 32 read-write 0xFFFC 0x7F10FFFC ERR_ADDR Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed. When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address. When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown. Note that error reporting to the fault structure cannot be suppressed. [15:2] read-write ERR_EN Enable error injection (ECC_EN must be 1). When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address. When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set). When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or AHB bus. [20:20] read-write ERR_PAR ECC Parity bits to use for ECC error injection at address ERR_ADDR. [30:24] read-write SCB0 Serial Communications Block (SPI/UART/I2C) SCB 0x40600000 0 65536 registers CTRL Generic control 0x0 32 read-write 0x300000F 0x83031F0F OVS N/A [3:0] read-write EC_AM_MODE Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. In UART mode this field should be '0'. [8:8] read-write EC_OP_MODE Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). In UART mode this field should be '0'. [9:9] read-write EZ_MODE Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. In UART mode this field should be '0'. [10:10] read-write BYTE_MODE Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements. '1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. [11:11] read-write CMD_RESP_MODE Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled. '1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). [12:12] read-write ADDR_ACCEPT Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers. In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. [16:16] read-write BLOCK Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX. [17:17] read-write MODE N/A [25:24] read-write I2C Inter-Integrated Circuits (I2C) mode. 0 SPI Serial Peripheral Interface (SPI) mode. 1 UART Universal Asynchronous Receiver/Transmitter (UART) mode. 2 ENABLED IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows: - Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. - Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. - Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. - Program CTRL to enable IP, select the specific operation mode and oversampling factor. When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content). [31:31] read-write STATUS Generic status 0x4 32 read-only 0x0 0x0 EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. [0:0] read-only CMD_RESP_CTRL Command/response control 0x8 32 read-write 0x0 0x1FF01FF BASE_RD_ADDR I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. [8:0] read-write BASE_WR_ADDR I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. [24:16] read-write CMD_RESP_STATUS Command/response status 0xC 32 read-only 0x0 0x0 CURR_RD_ADDR I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. [8:0] read-only CURR_WR_ADDR I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable. [24:16] read-only CMD_RESP_EC_BUS_BUSY Indicates whether there is an ongoing bus transfer to the IP. '0': no ongoing bus transfer. '1': ongoing bus transfer. For SPI, the field is '1' when the slave is selected. For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. [30:30] read-only CMD_RESP_EC_BUSY Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note: - When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable). - When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW. - When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW. Note that this update lasts one I2C clock cycle, or two SPI clock cycles. [31:31] read-only SPI_CTRL SPI control 0x20 32 read-write 0x3000000 0x8F010F3F SSEL_CONTINUOUS Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames. [0:0] read-write SELECT_PRECEDE Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit. [1:1] read-write CPHA Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: - Motorola mode 0. CPOL is '0', CPHA is '0': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. - Motorola mode 1. CPOL is '0', CPHA is '1': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 2. CPOL is '1', CPHA is '0': MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 3. CPOL is '1', CPHA is '1': MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. In SPI Motorola submode, all four CPOL/CPHA modes are valid. in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. [2:2] read-write CPOL Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: - CPOL is '0': SCLK is '0' when not transmitting data. - CPOL is '1': SCLK is '1' when not transmitting data. [3:3] read-write LATE_MISO_SAMPLE Changes the SCLK edge on which MISO is captured. Only used in master mode. When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. [4:4] read-write SCLK_CONTINUOUS Only applicable in master mode. '0': SCLK is generated, when the SPI master is enabled and data is transmitted. '1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality. [5:5] read-write SSEL_POLARITY0 Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes: '0': slave select is low/'0' active. '1': slave select is high/'1' active. For Texas Instruments submode: '0': high/'1' active precede/coincide pulse. '1': low/'0' active precede/coincide pulse. [8:8] read-write SSEL_POLARITY1 Slave select polarity. [9:9] read-write SSEL_POLARITY2 Slave select polarity. [10:10] read-write SSEL_POLARITY3 Slave select polarity. [11:11] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. '0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin. '1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. [16:16] read-write MODE N/A [25:24] read-write SPI_MOTOROLA SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. 0 SPI_TI SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. 1 SPI_NS SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. 2 SSEL Selects one of the four incoming/outgoing SPI slave select signals: - 0: Slave 0, SSEL[0]. - 1: Slave 1, SSEL[1]. - 2: Slave 2, SSEL[2]. - 3: Slave 3, SSEL[3]. The IP should be disabled when changes are made to this field. [27:26] read-write MASTER_MODE Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. [31:31] read-write SPI_STATUS SPI status 0x24 32 read-only 0x0 0x0 BUS_BUSY SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. [0:0] read-only SPI_EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. [1:1] read-only CURR_EZ_ADDR SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only UART_CTRL UART control 0x40 32 read-write 0x3000000 0x3010000 LOOPBACK Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'. This allows a SCB UART transmitter to communicate with its receiver counterpart. [16:16] read-write MODE N/A [25:24] read-write UART_STD Standard UART submode. 0 UART_SMARTCARD SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. 1 UART_IRDA Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. 2 UART_TX_CTRL UART transmitter control 0x44 32 read-write 0x2 0x137 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. [2:0] read-write PARITY Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware [5:5] read-write RETRY_ON_NACK When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. [8:8] read-write UART_RX_CTRL UART receiver control 0x48 32 read-write 0xA0002 0xF3777 STOP_BITS Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value. [2:0] read-write PARITY Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. [4:4] read-write PARITY_ENABLED Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. [5:5] read-write POLARITY Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. [6:6] read-write DROP_ON_PARITY_ERROR Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). [8:8] read-write DROP_ON_FRAME_ERROR Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. [9:9] read-write MP_MODE Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped. [10:10] read-write LIN_MODE Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. [12:12] read-write SKIP_START Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. [13:13] read-write BREAK_WIDTH Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. [19:16] read-write UART_RX_STATUS UART receiver status 0x4C 32 read-only 0x0 0x0 BR_COUNTER Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. [11:0] read-only UART_FLOW_CTRL UART flow control 0x50 32 read-write 0x0 0x30100FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes). [7:0] read-write RTS_POLARITY Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive. '1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive. During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity. [16:16] read-write CTS_POLARITY Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive. '1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive. [24:24] read-write CTS_ENABLED Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). [25:25] read-write I2C_CTRL I2C control 0x60 32 read-write 0xFB88 0xC001FBFF HIGH_PHASE_OVS Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles. [3:0] read-write LOW_PHASE_OVS Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be >= 8 IP clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles. [7:4] read-write M_READY_DATA_ACK When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full. [8:8] read-write M_NOT_READY_DATA_NACK When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full). [9:9] read-write S_GENERAL_IGNORE When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. [11:11] read-write S_READY_ADDR_ACK When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. [12:12] read-write S_READY_DATA_ACK When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'. [13:13] read-write S_NOT_READY_ADDR_NACK For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when: - EC_AM is '0', EC_OP is '0' and non EZ mode. Functionality is as follows: - 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): - EC_AM is '1' and EC_OP is '0'. - EC_AM is '1' and general call address match. - EC_AM is '1' and non EZ mode. Functionality is as follows: - 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). - 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled. [14:14] read-write S_NOT_READY_DATA_NACK For internally clocked logic only. Only used when: - non EZ mode. Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). [15:15] read-write LOOPBACK Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. [16:16] read-write SLAVE_MODE Slave mode enabled ('1') or not ('0'). [30:30] read-write MASTER_MODE Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself. [31:31] read-write I2C_STATUS I2C status 0x64 32 read-only 0x0 0x31 BUS_BUSY I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). [0:0] read-only I2C_EC_BUSY Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. [1:1] read-only S_READ I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. [4:4] read-only M_READ I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. [5:5] read-only CURR_EZ_ADDR I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. [15:8] read-only BASE_EZ_ADDR I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. [23:16] read-only I2C_M_CMD I2C master command 0x68 32 read-write 0x0 0x1F M_START When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. [0:0] read-write M_START_ON_IDLE When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. [1:1] read-write M_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. [2:2] read-write M_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. [3:3] read-write M_STOP When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. [4:4] read-write I2C_S_CMD I2C slave command 0x6C 32 read-write 0x0 0x3 S_ACK When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). [0:0] read-write S_NACK When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. [1:1] read-write I2C_CFG I2C configuration 0x70 32 read-write 0x2A1013 0x303F1313 SDA_IN_FILT_TRIM Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal SRAM memory. 1: enable clock_scb_en, has no effect on ec_busy_pp 0: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access) [1:0] read-write SDA_IN_FILT_SEL Selection of 'i2c_sda_in' filter delay: '0': 0 ns. '1: 50 ns (filter enabled). [4:4] read-write SCL_IN_FILT_TRIM Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. [9:8] read-write SCL_IN_FILT_SEL Selection of 'i2c_scl_in' filter delay: '0': 0 ns. '1: 50 ns (filter enabled). [12:12] read-write SDA_OUT_FILT0_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values. [17:16] read-write SDA_OUT_FILT1_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values. [19:18] read-write SDA_OUT_FILT2_TRIM Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values. [21:20] read-write SDA_OUT_FILT_SEL Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns. '1': 50 ns (filter 0 enabled). '2': 100 ns (filters 0 and 1 enabled). '3': 150 ns (filters 0, 1 and 2 enabled). [29:28] read-write TX_CTRL Transmitter control 0x200 32 read-write 0x107 0x1010F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. [3:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write OPEN_DRAIN Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. '0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. '1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). The open drain mode is supported for: - I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. - UART mode, 'uart_tx' IO cell. - SPI mode, 'spi_miso' IO cell. [16:16] read-write TX_FIFO_CTRL Transmitter FIFO control 0x204 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. [7:0] read-write CLEAR When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. [17:17] read-write TX_FIFO_STATUS Transmitter FIFO status 0x208 32 read-only 0x0 0xFFFF81FF USED Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). [8:0] read-only SR_VALID Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read by the hardware. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written. [31:24] read-only TX_FIFO_WR Transmitter FIFO write 0x240 32 write-only 0x0 0xFFFF DATA Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. [15:0] write-only RX_CTRL Receiver control 0x300 32 read-write 0x107 0x30F DATA_WIDTH Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. [3:0] read-write MSB_FIRST Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. [8:8] read-write MEDIAN Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. [9:9] read-write RX_FIFO_CTRL Receiver FIFO control 0x304 32 read-write 0x0 0x300FF TRIGGER_LEVEL Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. [7:0] read-write CLEAR When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. [16:16] read-write FREEZE When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. [17:17] read-write RX_FIFO_STATUS Receiver FIFO status 0x308 32 read-only 0x0 0xFFFF81FF USED Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). [8:0] read-only SR_VALID Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). [15:15] read-only RD_PTR FIFO read pointer: FIFO location from which a data frame is read. [23:16] read-only WR_PTR FIFO write pointer: FIFO location at which a new data frame is written by the hardware. [31:24] read-only RX_MATCH Slave address and mask 0x310 32 read-write 0x0 0xFF00FF ADDR Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). [7:0] read-write MASK Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK)). [23:16] read-write RX_FIFO_RD Receiver FIFO read 0x340 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [15:0] read-only RX_FIFO_RD_SILENT Receiver FIFO read silent 0x344 32 read-only 0x0 0x0 DATA Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. [15:0] read-only INTR_CAUSE Active clocked interrupt signal 0xE00 32 read-only 0x0 0x3F M Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. [0:0] read-only S Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. [1:1] read-only TX Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. [2:2] read-only RX Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. [3:3] read-only I2C_EC Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. [4:4] read-only SPI_EC Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. [5:5] read-only INTR_I2C_EC Externally clocked I2C interrupt request 0xE80 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request (with address match). Only used when EC_AM is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (I2C STOP). Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. [3:3] read-write INTR_I2C_EC_MASK Externally clocked I2C interrupt mask 0xE88 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_I2C_EC_MASKED Externally clocked I2C interrupt masked 0xE8C 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_SPI_EC Externally clocked SPI interrupt request 0xEC0 32 read-write 0x0 0xF WAKE_UP Wake up request. Active on incoming slave request when externally clocked selection is '1'. Only used when EC_AM is '1'. [0:0] read-write EZ_STOP STOP detection. Activated on the end of a every transfer (SPI deselection). Only available in EZ and CMD_RESP mode and when EC_OP is '1'. [1:1] read-write EZ_WRITE_STOP STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only used in EZ and CMD_RESP modes and when EC_OP is '1'. [2:2] read-write EZ_READ_STOP STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. Only used in EZ and CMD_RESP modes and when EC_OP is '1'. [3:3] read-write INTR_SPI_EC_MASK Externally clocked SPI interrupt mask 0xEC8 32 read-write 0x0 0xF WAKE_UP Mask bit for corresponding bit in interrupt request register. [0:0] read-write EZ_STOP Mask bit for corresponding bit in interrupt request register. [1:1] read-write EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [2:2] read-write EZ_READ_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write INTR_SPI_EC_MASKED Externally clocked SPI interrupt masked 0xECC 32 read-only 0x0 0xF WAKE_UP Logical and of corresponding request and mask bits. [0:0] read-only EZ_STOP Logical and of corresponding request and mask bits. [1:1] read-only EZ_WRITE_STOP Logical and of corresponding request and mask bits. [2:2] read-only EZ_READ_STOP Logical and of corresponding request and mask bits. [3:3] read-only INTR_M Master interrupt request 0xF00 32 read-write 0x0 0x317 I2C_ARB_LOST I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. [0:0] read-write I2C_NACK I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). [1:1] read-write I2C_ACK I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). [2:2] read-write I2C_STOP I2C master STOP. Set to '1', when the master has transmitted a STOP. [4:4] read-write I2C_BUS_ERROR I2C master bus error (unexpected detection of START or STOP condition). [8:8] read-write SPI_DONE SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. [9:9] read-write INTR_M_SET Master interrupt set request 0xF04 32 read-write 0x0 0x317 I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASK Master interrupt mask 0xF08 32 read-write 0x0 0x317 I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write INTR_M_MASKED Master interrupt masked request 0xF0C 32 read-only 0x0 0x317 I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_DONE Logical and of corresponding request and mask bits. [9:9] read-only INTR_S Slave interrupt request 0xF40 32 read-write 0x0 0xFFF I2C_ARB_LOST I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [0:0] read-write I2C_NACK I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). [1:1] read-write I2C_ACK I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). [2:2] read-write I2C_WRITE_STOP I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected). [3:3] read-write I2C_STOP I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. [4:4] read-write I2C_START I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. [5:5] read-write I2C_ADDR_MATCH I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. [6:6] read-write I2C_GENERAL I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. [7:7] read-write I2C_BUS_ERROR I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [8:8] read-write SPI_EZ_WRITE_STOP SPI slave deselected after a write EZ SPI transfer occurred. [9:9] read-write SPI_EZ_STOP SPI slave deselected after any EZ SPI transfer occurred. [10:10] read-write SPI_BUS_ERROR SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. [11:11] read-write INTR_S_SET Slave interrupt set request 0xF44 32 read-write 0x0 0xFFF I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write I2C_START Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Write with '1' to set corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASK Slave interrupt mask 0xF48 32 read-write 0x0 0xFFF I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. [0:0] read-write I2C_NACK Mask bit for corresponding bit in interrupt request register. [1:1] read-write I2C_ACK Mask bit for corresponding bit in interrupt request register. [2:2] read-write I2C_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [3:3] read-write I2C_STOP Mask bit for corresponding bit in interrupt request register. [4:4] read-write I2C_START Mask bit for corresponding bit in interrupt request register. [5:5] read-write I2C_ADDR_MATCH Mask bit for corresponding bit in interrupt request register. [6:6] read-write I2C_GENERAL Mask bit for corresponding bit in interrupt request register. [7:7] read-write I2C_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write SPI_EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register. [9:9] read-write SPI_EZ_STOP Mask bit for corresponding bit in interrupt request register. [10:10] read-write SPI_BUS_ERROR Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_S_MASKED Slave interrupt masked request 0xF4C 32 read-only 0x0 0xFFF I2C_ARB_LOST Logical and of corresponding request and mask bits. [0:0] read-only I2C_NACK Logical and of corresponding request and mask bits. [1:1] read-only I2C_ACK Logical and of corresponding request and mask bits. [2:2] read-only I2C_WRITE_STOP Logical and of corresponding request and mask bits. [3:3] read-only I2C_STOP Logical and of corresponding request and mask bits. [4:4] read-only I2C_START Logical and of corresponding request and mask bits. [5:5] read-only I2C_ADDR_MATCH Logical and of corresponding request and mask bits. [6:6] read-only I2C_GENERAL Logical and of corresponding request and mask bits. [7:7] read-only I2C_BUS_ERROR Logical and of corresponding request and mask bits. [8:8] read-only SPI_EZ_WRITE_STOP Logical and of corresponding request and mask bits. [9:9] read-only SPI_EZ_STOP Logical and of corresponding request and mask bits. [10:10] read-only SPI_BUS_ERROR Logical and of corresponding request and mask bits. [11:11] read-only INTR_TX Transmitter interrupt request 0xF80 32 read-write 0x0 0x7F3 TRIGGER Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL. Only used in FIFO mode. [0:0] read-write NOT_FULL TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) BYTE_MODE is '0': # entries != FF_DATA_NR/2. BYTE_MODE is '1': # entries != FF_DATA_NR. Only used in FIFO mode. [1:1] read-write EMPTY TX FIFO is empty; i.e. it has 0 entries. Only used in FIFO mode. [4:4] read-write OVERFLOW Attempt to write to a full TX FIFO. Only used in FIFO mode. [5:5] read-write UNDERFLOW Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'. Only used in FIFO mode. [6:6] read-write BLOCKED AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write UART_NACK UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. [8:8] read-write UART_DONE UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit. [9:9] read-write UART_ARB_LOST UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit. [10:10] read-write INTR_TX_SET Transmitter interrupt set request 0xF84 32 read-write 0x0 0x7F3 TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write EMPTY Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write UART_NACK Write with '1' to set corresponding bit in interrupt request register. [8:8] read-write UART_DONE Write with '1' to set corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASK Transmitter interrupt mask 0xF88 32 read-write 0x0 0x7F3 TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_FULL Mask bit for corresponding bit in interrupt request register. [1:1] read-write EMPTY Mask bit for corresponding bit in interrupt request register. [4:4] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write UART_NACK Mask bit for corresponding bit in interrupt request register. [8:8] read-write UART_DONE Mask bit for corresponding bit in interrupt request register. [9:9] read-write UART_ARB_LOST Mask bit for corresponding bit in interrupt request register. [10:10] read-write INTR_TX_MASKED Transmitter interrupt masked request 0xF8C 32 read-only 0x0 0x7F3 TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_FULL Logical and of corresponding request and mask bits. [1:1] read-only EMPTY Logical and of corresponding request and mask bits. [4:4] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only UART_NACK Logical and of corresponding request and mask bits. [8:8] read-only UART_DONE Logical and of corresponding request and mask bits. [9:9] read-only UART_ARB_LOST Logical and of corresponding request and mask bits. [10:10] read-only INTR_RX Receiver interrupt request 0xFC0 32 read-write 0x0 0xFED TRIGGER More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL. Only used in FIFO mode. [0:0] read-write NOT_EMPTY RX FIFO is not empty. Only used in FIFO mode. [2:2] read-write FULL RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2) BYTE_MODE is '0': # entries == FF_DATA_NR/2. BYTE_MODE is '1': # entries == FF_DATA_NR. Only used in FIFO mode. [3:3] read-write OVERFLOW Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. Only used in FIFO mode. [5:5] read-write UNDERFLOW Attempt to read from an empty RX FIFO. Only used in FIFO mode. [6:6] read-write BLOCKED AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. [7:7] read-write FRAME_ERROR Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error: Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. [8:8] read-write PARITY_ERROR Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. [9:9] read-write BAUD_DETECT LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit. [10:10] read-write BREAK_DETECT Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. [11:11] read-write INTR_RX_SET Receiver interrupt set request 0xFC4 32 read-write 0x0 0xFED TRIGGER Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Write with '1' to set corresponding bit in interrupt status register. [2:2] read-write FULL Write with '1' to set corresponding bit in interrupt status register. [3:3] read-write OVERFLOW Write with '1' to set corresponding bit in interrupt status register. [5:5] read-write UNDERFLOW Write with '1' to set corresponding bit in interrupt status register. [6:6] read-write BLOCKED Write with '1' to set corresponding bit in interrupt status register. [7:7] read-write FRAME_ERROR Write with '1' to set corresponding bit in interrupt status register. [8:8] read-write PARITY_ERROR Write with '1' to set corresponding bit in interrupt status register. [9:9] read-write BAUD_DETECT Write with '1' to set corresponding bit in interrupt status register. [10:10] read-write BREAK_DETECT Write with '1' to set corresponding bit in interrupt status register. [11:11] read-write INTR_RX_MASK Receiver interrupt mask 0xFC8 32 read-write 0x0 0xFED TRIGGER Mask bit for corresponding bit in interrupt request register. [0:0] read-write NOT_EMPTY Mask bit for corresponding bit in interrupt request register. [2:2] read-write FULL Mask bit for corresponding bit in interrupt request register. [3:3] read-write OVERFLOW Mask bit for corresponding bit in interrupt request register. [5:5] read-write UNDERFLOW Mask bit for corresponding bit in interrupt request register. [6:6] read-write BLOCKED Mask bit for corresponding bit in interrupt request register. [7:7] read-write FRAME_ERROR Mask bit for corresponding bit in interrupt request register. [8:8] read-write PARITY_ERROR Mask bit for corresponding bit in interrupt request register. [9:9] read-write BAUD_DETECT Mask bit for corresponding bit in interrupt request register. [10:10] read-write BREAK_DETECT Mask bit for corresponding bit in interrupt request register. [11:11] read-write INTR_RX_MASKED Receiver interrupt masked request 0xFCC 32 read-only 0x0 0xFED TRIGGER Logical and of corresponding request and mask bits. [0:0] read-only NOT_EMPTY Logical and of corresponding request and mask bits. [2:2] read-only FULL Logical and of corresponding request and mask bits. [3:3] read-only OVERFLOW Logical and of corresponding request and mask bits. [5:5] read-only UNDERFLOW Logical and of corresponding request and mask bits. [6:6] read-only BLOCKED Logical and of corresponding request and mask bits. [7:7] read-only FRAME_ERROR Logical and of corresponding request and mask bits. [8:8] read-only PARITY_ERROR Logical and of corresponding request and mask bits. [9:9] read-only BAUD_DETECT Logical and of corresponding request and mask bits. [10:10] read-only BREAK_DETECT Logical and of corresponding request and mask bits. [11:11] read-only SCB1 0x40610000 SCB2 0x40620000 SCB4 0x40640000 SCB5 0x40650000 SCB6 0x40660000 CTBM0 Continuous Time Block Mini CTBM 0x40900000 0 65536 registers CTB_CTRL global CTB and power control 0x0 32 read-write 0x0 0xC0000000 DEEPSLEEP_ON - 0: CTB IP disabled off during DeepSleep power mode - 1: CTB IP remains enabled during DeepSleep power mode (if ENABLED=1) [30:30] read-write ENABLED - 0: CTB IP disabled (put analog in power down, open all switches) - 1: CTB IP enabled [31:31] read-write OA_RES0_CTRL Opamp0 and resistor0 control 0x4 32 read-write 0x0 0x1BFF OA0_PWR_MODE Opamp0 power level, assumes Cload=15pF for the (internal only) 1x driver or 50pF for the (external) 10x driver [2:0] read-write OFF Off 0 LOW Low power mode (IDD: 350uA, GBW: 1MHz for both 1x/10x) 1 MEDIUM Medium power mode (IDD: 600uA, GBW: 3MHz for 1x & 2.5MHz for 10x) 2 HIGH High power mode for highest GBW (IDD: 1500uA, GBW: 8MHz for 1x & 6MHz for 10x) 3 RSVD N/A 4 PS_LOW Power Saver Low power mode (IDD: ~20uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is disabled) 5 PS_MEDIUM Power Saver Medium power mode (IDD: ~40uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is enabled) 6 PS_HIGH Power Saver Medium power mode (IDD: ~60uA with 1uA bias from AREF, GBW: ~200kHz for 1x/10x, offset correcting IDAC is enabled) 7 OA0_DRIVE_STR_SEL Opamp0 output strength select 0=1x, 1=10x This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM [3:3] read-write OA0_COMP_EN Opamp0 comparator enable [4:4] read-write OA0_HYST_EN Opamp0 hysteresis enable (10mV) [5:5] read-write OA0_BYPASS_DSI_SYNC Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchronize (level or pulse), 1=bypass (output async) [6:6] read-write OA0_DSI_LEVEL Opamp0 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA0_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output [7:7] read-write OA0_COMPINT Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger) [9:8] read-write DISABLE Disabled, no interrupts will be detected 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 OA0_PUMP_EN Opamp0 pump enable [11:11] read-write OA0_BOOST_EN Opamp0 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0 [12:12] read-write OA_RES1_CTRL Opamp1 and resistor1 control 0x8 32 read-write 0x0 0x1BFF OA1_PWR_MODE Opamp1 power level: see description of OA0_PWR_MODE [2:0] read-write OA1_DRIVE_STR_SEL Opamp1 output strength select 0=1x, 1=10x This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM [3:3] read-write OA1_COMP_EN Opamp1 comparator enable [4:4] read-write OA1_HYST_EN Opamp1 hysteresis enable (10mV) [5:5] read-write OA1_BYPASS_DSI_SYNC Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypass [6:6] read-write OA1_DSI_LEVEL Opamp1 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output [7:7] read-write OA1_COMPINT Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger) [9:8] read-write DISABLE Disabled, no interrupts will be detected 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 OA1_PUMP_EN Opamp1 pump enable [11:11] read-write OA1_BOOST_EN Opamp1 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0 [12:12] read-write COMP_STAT Comparator status 0xC 32 read-only 0x0 0x10001 OA0_COMP Opamp0 current comparator status [0:0] read-only OA1_COMP Opamp1 current comparator status [16:16] read-only INTR Interrupt request register 0x20 32 read-write 0x0 0x3 COMP0 Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. [0:0] read-write COMP1 Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. [1:1] read-write INTR_SET Interrupt request set register 0x24 32 read-write 0x0 0x3 COMP0_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write COMP1_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write INTR_MASK Interrupt request mask 0x28 32 read-write 0x0 0x3 COMP0_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write COMP1_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write INTR_MASKED Interrupt request masked 0x2C 32 read-only 0x0 0x3 COMP0_MASKED Logical and of corresponding request and mask bits. [0:0] read-only COMP1_MASKED Logical and of corresponding request and mask bits. [1:1] read-only OA0_SW Opamp0 switch control 0x80 32 read-write 0x0 0x24410D OA0P_A00 Opamp0 positive terminal amuxbusa [0:0] read-write OA0P_A20 Opamp0 positive terminal P0 [2:2] read-write OA0P_A30 Opamp0 positive terminal ctbbus0 [3:3] read-write OA0M_A11 Opamp0 negative terminal P1 [8:8] read-write OA0M_A81 Opamp0 negative terminal Opamp0 output [14:14] read-write OA0O_D51 Opamp0 output sarbus0 (ctbbus2 in CTB) [18:18] read-write OA0O_D81 Opamp0 output switch to short 1x with 10x drive [21:21] read-write OA0_SW_CLEAR Opamp0 switch control clear 0x84 32 read-write 0x0 0x24410D OA0P_A00 see corresponding bit in OA0_SW [0:0] read-write OA0P_A20 see corresponding bit in OA0_SW [2:2] read-write OA0P_A30 see corresponding bit in OA0_SW [3:3] read-write OA0M_A11 see corresponding bit in OA0_SW [8:8] read-write OA0M_A81 see corresponding bit in OA0_SW [14:14] read-write OA0O_D51 see corresponding bit in OA0_SW [18:18] read-write OA0O_D81 see corresponding bit in OA0_SW [21:21] read-write OA1_SW Opamp1 switch control 0x88 32 read-write 0x0 0x2C4193 OA1P_A03 Opamp1 positive terminal amuxbusb [0:0] read-write OA1P_A13 Opamp1 positive terminal P5 [1:1] read-write OA1P_A43 Opamp1 positive terminal ctbbus1 [4:4] read-write OA1P_A73 Opamp1 positive terminal to vref1 [7:7] read-write OA1M_A22 Opamp1 negative terminal P4 [8:8] read-write OA1M_A82 Opamp1 negative terminal Opamp1 output [14:14] read-write OA1O_D52 Opamp1 output sarbus0 (ctbbus2 in CTB) [18:18] read-write OA1O_D62 Opamp1 output sarbus1 (ctbbus3 in CTB) [19:19] read-write OA1O_D82 Opamp1 output switch to short 1x with 10x drive [21:21] read-write OA1_SW_CLEAR Opamp1 switch control clear 0x8C 32 read-write 0x0 0x2C4193 OA1P_A03 see corresponding bit in OA1_SW [0:0] read-write OA1P_A13 see corresponding bit in OA1_SW [1:1] read-write OA1P_A43 see corresponding bit in OA1_SW [4:4] read-write OA1P_A73 see corresponding bit in OA1_SW [7:7] read-write OA1M_A22 see corresponding bit in OA1_SW [8:8] read-write OA1M_A82 see corresponding bit in OA1_SW [14:14] read-write OA1O_D52 see corresponding bit in OA1_SW [18:18] read-write OA1O_D62 see corresponding bit in OA1_SW [19:19] read-write OA1O_D82 see corresponding bit in OA1_SW [21:21] read-write CTD_SW CTDAC connection switch control 0xA0 32 read-write 0x0 0xF732 CTDD_CRD CTDAC Reference opamp output to ctdrefdrive [1:1] read-write CTDS_CRS ctdrefsense to opamp input [4:4] read-write CTDS_COR ctdvout to opamp input [5:5] read-write CTDO_C6H P6 pin to Hold capacitor [8:8] read-write CTDO_COS ctdvout to Hold capacitor (Sample switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set [9:9] read-write CTDH_COB Drive the CTDAC output with CTBM 1x output during hold mode in Sample and Hold operation [10:10] read-write CTDH_CHD Hold capacitor connect [12:12] read-write CTDH_CA0 Hold capacitor to opamp input [13:13] read-write CTDH_CIS Hold capacitor isolation (from all the other switches) [14:14] read-write CTDH_ILR Hold capacitor leakage reduction (drive other side of CIS to capacitor voltage) [15:15] read-write CTD_SW_CLEAR CTDAC connection switch control clear 0xA4 32 read-write 0x0 0xF732 CTDD_CRD see corresponding bit in CTD_SW [1:1] read-write CTDS_CRS see corresponding bit in CTD_SW [4:4] read-write CTDS_COR see corresponding bit in CTD_SW [5:5] read-write CTDO_C6H see corresponding bit in CTD_SW [8:8] read-write CTDO_COS see corresponding bit in CTD_SW [9:9] read-write CTDH_COB see corresponding bit in CTD_SW [10:10] read-write CTDH_CHD see corresponding bit in CTD_SW [12:12] read-write CTDH_CA0 see corresponding bit in CTD_SW [13:13] read-write CTDH_CIS see corresponding bit in CTD_SW [14:14] read-write CTDH_ILR see corresponding bit in CTD_SW [15:15] read-write CTB_SW_DS_CTRL CTB bus switch control 0xC0 32 read-write 0x0 0x80000C00 P2_DS_CTRL23 for P22, D51 (dsi_out[2]) [10:10] read-write P3_DS_CTRL23 for P33, D52, D62 (dsi_out[3]) [11:11] read-write CTD_COS_DS_CTRL Hold capacitor Sample switch (COS) [31:31] read-write CTB_SW_SQ_CTRL CTB bus switch Sar Sequencer control 0xC4 32 read-write 0x0 0xC00 P2_SQ_CTRL23 for D51 [10:10] read-write P3_SQ_CTRL23 for D52, D62 [11:11] read-write CTB_SW_STATUS CTB bus switch control status 0xC8 32 read-only 0x0 0xF0000000 OA0O_D51_STAT see OA0O_D51 bit in OA0_SW [28:28] read-only OA1O_D52_STAT see OA1O_D52 bit in OA1_SW [29:29] read-only OA1O_D62_STAT see OA1O_D62 bit in OA1_SW [30:30] read-only CTD_COS_STAT see COS bit in CTD_SW [31:31] read-only OA0_OFFSET_TRIM Opamp0 trim control 0xF00 32 read-write 0x0 0x3F OA0_OFFSET_TRIM Opamp0 offset trim [5:0] read-write OA0_SLOPE_OFFSET_TRIM Opamp0 trim control 0xF04 32 read-write 0x0 0x3F OA0_SLOPE_OFFSET_TRIM Opamp0 slope offset drift trim [5:0] read-write OA0_COMP_TRIM Opamp0 trim control 0xF08 32 read-write 0x0 0x3 OA0_COMP_TRIM Opamp0 Compensation Capacitor Trim. Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 [1:0] read-write OA1_OFFSET_TRIM Opamp1 trim control 0xF0C 32 read-write 0x0 0x3F OA1_OFFSET_TRIM Opamp1 offset trim [5:0] read-write OA1_SLOPE_OFFSET_TRIM Opamp1 trim control 0xF10 32 read-write 0x0 0x3F OA1_SLOPE_OFFSET_TRIM Opamp1 slope offset drift trim [5:0] read-write OA1_COMP_TRIM Opamp1 trim control 0xF14 32 read-write 0x0 0x3 OA1_COMP_TRIM Opamp1 Compensation Capacitor Trim. Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 [1:0] read-write CTDAC0 Continuous Time DAC CTDAC 0x40940000 0 65536 registers CTDAC_CTRL Global CTDAC control 0x0 32 read-write 0x0 0xFBC0033F DEGLITCH_CNT To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles. [5:0] read-write DEGLITCH_CO6 Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles. [8:8] read-write DEGLITCH_COS Force CTB.COS switch open after each VALUE change for the set number of clock cycles. [9:9] read-write OUT_EN Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling : 0: output disabled, the output is either: - Tri-state (DISABLED_MODE=0) - or Vssa (DISABLED_MODE=1 && CTDAC_RANGE=0) - or Vref (DISABLED_MODE=1 && CTDAC_RANGE=1) 1: output enabled, CTDAC output drives the programmed VALUE [22:22] read-write CTDAC_RANGE By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1 0: Range is [0, 4095] * Vref / 4096 1: Range is [1, 4096] * Vref / 4096 [23:23] read-write CTDAC_MODE DAC mode, this determines the Value decoding [25:24] read-write UNSIGNED12 Unsigned 12-bit VDAC, i.e. no value decoding. 0 VIRT_SIGNED12 Virtual signed 12-bits' VDAC. Value decoding: add 0x800 to the 12-bit Value (=invert MSB), to convert the lowest signed number 0x800 to the lowest unsigned number 0x000. This is the same as the SAR handles 12-bit 'virtual' signed numbers. 1 RSVD2 N/A 2 RSVD3 N/A 3 DISABLED_MODE Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation) 0: Tri-state CTDAC output when disabled 1: output Vssa or Vref when disabled (see OUT_EN description) [27:27] read-write DSI_STROBE_EN DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI. 0: Ignore DSI strobe input 1: Only do a CTDAC update if allowed by the DSI strobe (throttle), see below for level or edge [28:28] read-write DSI_STROBE_LEVEL Select level or edge detect for DSI strobe - 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal the next DAC value update is done on the next CTDAC clock - 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC will do a next DAC value update on each CTDAC clock. [29:29] read-write DEEPSLEEP_ON - 0: CTDAC IP disabled off during DeepSleep power mode - 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1) [30:30] read-write ENABLED 0: CTDAC IP disabled (put analog in power down, open all switches) 1: CTDAC IP enabled [31:31] read-write INTR Interrupt request register 0x20 32 read-write 0x0 0x1 VDAC_EMPTY VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e. was copied to the current VALUE. Write with '1' to clear bit. [0:0] read-write INTR_SET Interrupt request set register 0x24 32 read-write 0x0 0x1 VDAC_EMPTY_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write INTR_MASK Interrupt request mask 0x28 32 read-write 0x0 0x1 VDAC_EMPTY_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write INTR_MASKED Interrupt request masked 0x2C 32 read-only 0x0 0x1 VDAC_EMPTY_MASKED Logical and of corresponding request and mask bits. [0:0] read-only CTDAC_SW CTDAC switch control 0xB0 32 read-write 0x0 0x101 CTDD_CVD VDDA supply to ctdrefdrive [0:0] read-write CTDO_CO6 ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set [8:8] read-write CTDAC_SW_CLEAR CTDAC switch control clear 0xB4 32 read-write 0x0 0x101 CTDD_CVD see corresponding bit in CTD_SW [0:0] read-write CTDO_CO6 see corresponding bit in CTD_SW [8:8] read-write CTDAC_VAL DAC Value 0x100 32 read-write 0x0 0xFFF VALUE Value, in CTDAC_MODE 1 this value is decoded [11:0] read-write CTDAC_VAL_NXT Next DAC value (double buffering) 0x104 32 read-write 0x0 0xFFF VALUE Next value for CTDAC_VAL.VALUE [11:0] read-write SAR0 SAR ADC with Sequencer SAR 0x409B0000 0 65536 registers CTRL Analog control register. 0x0 32 read-write 0x10000000 0xFF3FEEF7 PWR_CTRL_VREF VREF buffer low power mode. [2:0] read-write PWR_100 full power (100 percent) (default), bypass cap, max clk_sar is 18MHz. 0 PWR_80 80 percent power 1 PWR_60 60 percent power 2 PWR_50 50 percent power 3 PWR_40 40 percent power 4 PWR_30 30 percent power 5 PWR_20 20 percent power 6 PWR_10 10 percent power 7 VREF_SEL SARADC internal VREF selection. [6:4] read-write VREF0 VREF0 from PRB (VREF buffer on) 0 VREF1 VREF1 from PRB (VREF buffer on) 1 VREF2 VREF2 from PRB (VREF buffer on) 2 VREF_AROUTE VREF from AROUTE (VREF buffer on) 3 VBGR 1.024V from BandGap (VREF buffer on) 4 VREF_EXT External precision Vref direct from a pin (low impedance path). 5 VDDA_DIV_2 Vdda/2 (VREF buffer on) 6 VDDA Vdda. 7 VREF_BYP_CAP_EN VREF bypass cap enable for when VREF buffer is on [7:7] read-write NEG_SEL SARADC internal NEG selection for Single ended conversion [11:9] read-write VSSA_KELVIN NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high. 0 ART_VSSA NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC 1 P1 NEG input of SARADC is connected to P1 pin of SARMUX 2 P3 NEG input of SARADC is connected to P3 pin of SARMUX 3 P5 NEG input of SARADC is connected to P5 pin of SARMUX 4 P7 NEG input of SARADC is connected to P7 pin of SARMUX 5 ACORE NEG input of SARADC is connected to an ACORE in AROUTE 6 VREF NEG input of SARADC is shorted with VREF input of SARADC. 7 SAR_HW_CTRL_NEGVREF Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch. [13:13] read-write COMP_DLY Set the comparator latch delay in accordance with SAR conversion rate [15:14] read-write D2P5 2.5ns delay, use this for 2.5Msps 0 D4 4.0ns delay, use this for 2.0Msps 1 D10 10ns delay, use this for 1.5Msps 2 D12 12ns delay, use this for 1.0Msps or less 3 SPARE Spare controls, not yet designated, for late changes done with an ECO [19:16] read-write BOOSTPUMP_EN deprecated [20:20] read-write REFBUF_EN For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. Setting this bit is critical to proper function of switches inside SARREF block. [21:21] read-write COMP_PWR Comparator power mode. (Sample rate TBD) [26:24] read-write P100 Power = 100 percent, Use this for SAR Clock Frequency greater than 18MHz 0 P80 N/A 1 P60 Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz. 2 P50 N/A 3 P40 N/A 4 P30 N/A 5 P20 Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz 6 P10 N/A 7 DEEPSLEEP_ON - 0: SARMUX IP disabled off during DeepSleep power mode - 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1) [27:27] read-write DSI_SYNC_CONFIG - 0: bypass clock domain synchronization of the DSI config signals. - 1: synchronize the DSI config signals to peripheral clock domain. [28:28] read-write DSI_MODE SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) - 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations - 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored [29:29] read-write SWITCH_DISABLE Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control) - 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations - 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX [30:30] read-write ENABLED - 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgating) on write. - 1: SAR IP enabled. [31:31] read-write SAMPLE_CTRL Sample control register. 0x4 32 read-write 0x80008 0xDFCF01FE LEFT_ALIGN Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. [1:1] read-write SINGLE_ENDED_SIGNED Output data from a single ended conversion as a signed value If AVG_MODE = 1 (Interleaved averaging), then SINGLE_ENDED_SIGNED must be configured identically to DIFFERENTIAL_SIGNED. [2:2] read-write UNSIGNED Default: result data is unsigned (zero extended if needed) 0 SIGNED result data is signed (sign extended if needed) 1 DIFFERENTIAL_SIGNED Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1 If AVG_MODE = 1 (Interleaved averaging), then DIFFERENTIAL_SIGNED must be configured identically to SINGLE_ENDED_SIGNED. [3:3] read-write UNSIGNED result data is unsigned (zero extended if needed) 0 SIGNED Default: result data is signed (sign extended if needed) 1 AVG_CNT Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2..256] times. - In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3). - In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3). [6:4] read-write AVG_SHIFT Averaging shifting: after averaging the result is shifted right to fit in 12 bits. [7:7] read-write AVG_MODE Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available. [8:8] read-write ACCUNDUMP Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged 0 INTERLEAVED Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans. Interleaved averaging cannot be set by SAR_CLOCK_SEL.CLOCK_SEL =1. 1 CONTINUOUS - 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels. - 1: Continuously scan enabled channels, ignore triggers. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. [16:16] read-write DSI_TRIGGER_EN - 0: firmware trigger only: disable hardware trigger tr_sar_in. - 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB). [17:17] read-write DSI_TRIGGER_LEVEL - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. - 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. [18:18] read-write DSI_SYNC_TRIGGER - 0: bypass clock domain synchronization of the trigger signal. - 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. [19:19] read-write UAB_SCAN_MODE Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored. [22:22] read-write UNSCHEDULED Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable. 0 SCHEDULED Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant. This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator. 1 REPEAT_INVALID For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received: - 0: use the last known valid sample for that channel and clear the NEWVALUE flag - 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling) [23:23] read-write VALID_SEL Static UAB Valid select 0=UAB0 half 0 Valid output 1=UAB0 half 1 Valid output 2=UAB1 half 0 Valid output 3=UAB1 half 1 Valid output 4=UAB2 half 0 Valid output 5=UAB2 half 1 Valid output 6=UAB3 half 0 Valid output 7=UAB3 half 1 Valid output [26:24] read-write VALID_SEL_EN Enable static UAB Valid selection (override Hardware) [27:27] read-write VALID_IGNORE Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above [28:28] read-write TRIGGER_OUT_EN SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1). [30:30] read-write EOS_DSI_OUT_EN Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal. [31:31] read-write SAMPLE_TIME01 Sample time specification ST0 and ST1 0x10 32 read-write 0x30003 0x3FF03FF SAMPLE_TIME0 Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2. [9:0] read-write SAMPLE_TIME1 Sample time1 [25:16] read-write SAMPLE_TIME23 Sample time specification ST2 and ST3 0x14 32 read-write 0x30003 0x3FF03FF SAMPLE_TIME2 Sample time2 [9:0] read-write SAMPLE_TIME3 Sample time3 [25:16] read-write RANGE_THRES Global range detect threshold register. 0x18 32 read-write 0x0 0xFFFFFFFF RANGE_LOW Low threshold for range detect. [15:0] read-write RANGE_HIGH High threshold for range detect. [31:16] read-write RANGE_COND Global range detect mode register. 0x1C 32 read-write 0x0 0xC0000000 RANGE_COND Range condition select. [31:30] read-write BELOW result < RANGE_LOW 0 INSIDE RANGE_LOW <= result < RANGE_HIGH 1 ABOVE RANGE_HIGH <= result 2 OUTSIDE result < RANGE_LOW || RANGE_HIGH <= result 3 CHAN_EN Enable bits for the channels 0x20 32 read-write 0x0 0xFFFF CHAN_EN Channel enable. - 0: the corresponding channel is disabled. - 1: the corresponding channel is enabled, it will be included in the next scan. [15:0] read-write START_CTRL Start control register (firmware trigger). 0x24 32 read-write 0x0 0x1 FW_TRIGGER When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. This fiel+G201d cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. [0:0] read-write 16 4 CHAN_CONFIG[%s] Channel configuration register. 0x80 32 read-write 0x0 0x81773577 POS_PIN_ADDR Address of the pin to be sampled by this channel (connected to Vplus) [2:0] read-write POS_PORT_ADDR Address of the port that contains the pin to be sampled by this channel (connected to Vplus) [6:4] read-write SARMUX SARMUX pins. 0 CTB0 CTB0 1 CTB1 CTB1 2 CTB2 CTB2 3 CTB3 CTB3 4 AROUTE_VIRT2 AROUTE virtual port2 (VPORT2) 5 AROUTE_VIRT1 AROUTE virtual port1 (VPORT1) 6 SARMUX_VIRT SARMUX virtual port (VPORT0) 7 DIFFERENTIAL_EN Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored). [8:8] read-write AVG_EN Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) [10:10] read-write SAMPLE_TIME_SEL Sample time select: select which of the 4 global sample times to use for this channel [13:12] read-write NEG_PIN_ADDR Address of the neg pin to be sampled by this channel. [18:16] read-write NEG_PORT_ADDR Address of the neg port that contains the pin to be sampled by this channel. [22:20] read-write SARMUX SARMUX pins. 0 AROUTE_VIRT2 AROUTE virtual port2 (VPORT2) 5 AROUTE_VIRT1 AROUTE virtual port1 (VPORT1) 6 SARMUX_VIRT SARMUX virtual port (VPORT0) 7 NEG_ADDR_EN 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin. [24:24] read-write DSI_OUT_EN DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formatting), together with the channel number, is sent out on the DSI communication channel for processing in UDBs. [31:31] read-write 16 4 CHAN_WORK[%s] Channel working data register 0x100 32 read-only 0x0 0x88000000 WORK SAR conversion working data of the channel. The data is written here right after sampling this channel. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [15:0] read-only CHAN_WORK_NEWVALUE_MIR mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [27:27] read-only CHAN_WORK_UPDATED_MIR mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [31:31] read-only 16 4 CHAN_RESULT[%s] Channel result data register 0x180 32 read-only 0x0 0xE8000000 RESULT SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [15:0] read-only CHAN_RESULT_NEWVALUE_MIR mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [27:27] read-only SATURATE_INTR_MIR mirror bit of corresponding bit in SAR_SATURATE_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [29:29] read-only RANGE_INTR_MIR mirror bit of corresponding bit in SAR_RANGE_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [30:30] read-only CHAN_RESULT_UPDATED_MIR mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [31:31] read-only CHAN_WORK_UPDATED Channel working data register 'updated' bits 0x200 32 read-only 0x0 0xFFFF CHAN_WORK_UPDATED If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [15:0] read-only CHAN_RESULT_UPDATED Channel result data register 'updated' bits 0x204 32 read-only 0x0 0xFFFF CHAN_RESULT_UPDATED If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [15:0] read-only CHAN_WORK_NEWVALUE Channel working data register 'new value' bits 0x208 32 read-only 0x0 0xFFFF CHAN_WORK_NEWVALUE If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid. In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [15:0] read-only CHAN_RESULT_NEWVALUE Channel result data register 'new value' bits 0x20C 32 read-only 0x0 0xFFFF CHAN_RESULT_NEWVALUE If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid. In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [15:0] read-only INTR Interrupt request register. 0x210 32 read-write 0x0 0xFF EOS_INTR End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit. [0:0] read-write OVERFLOW_INTR Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. [1:1] read-write FW_COLLISION_INTR Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. [2:2] read-write DSI_COLLISION_INTR DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. [3:3] read-write INJ_EOC_INTR Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. [4:4] read-write INJ_SATURATE_INTR Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. [5:5] read-write INJ_RANGE_INTR Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. [6:6] read-write INJ_COLLISION_INTR Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit. This interrupt cannot be used if SAR_CLOCK_SEL.CLOCK_SEL =1. [7:7] read-write INTR_SET Interrupt set request register 0x214 32 read-write 0x0 0xFF EOS_SET Write with '1' to set corresponding bit in interrupt request register. [0:0] read-write OVERFLOW_SET Write with '1' to set corresponding bit in interrupt request register. [1:1] read-write FW_COLLISION_SET Write with '1' to set corresponding bit in interrupt request register. [2:2] read-write DSI_COLLISION_SET Write with '1' to set corresponding bit in interrupt request register. [3:3] read-write INJ_EOC_SET Write with '1' to set corresponding bit in interrupt request register. [4:4] read-write INJ_SATURATE_SET Write with '1' to set corresponding bit in interrupt request register. [5:5] read-write INJ_RANGE_SET Write with '1' to set corresponding bit in interrupt request register. [6:6] read-write INJ_COLLISION_SET Write with '1' to set corresponding bit in interrupt request register. [7:7] read-write INTR_MASK Interrupt mask register. 0x218 32 read-write 0x0 0xFF EOS_MASK Mask bit for corresponding bit in interrupt request register. [0:0] read-write OVERFLOW_MASK Mask bit for corresponding bit in interrupt request register. [1:1] read-write FW_COLLISION_MASK Mask bit for corresponding bit in interrupt request register. [2:2] read-write DSI_COLLISION_MASK Mask bit for corresponding bit in interrupt request register. [3:3] read-write INJ_EOC_MASK Mask bit for corresponding bit in interrupt request register. [4:4] read-write INJ_SATURATE_MASK Mask bit for corresponding bit in interrupt request register. [5:5] read-write INJ_RANGE_MASK Mask bit for corresponding bit in interrupt request register. [6:6] read-write INJ_COLLISION_MASK Mask bit for corresponding bit in interrupt request register. [7:7] read-write INTR_MASKED Interrupt masked request register 0x21C 32 read-only 0x0 0xFF EOS_MASKED Logical and of corresponding request and mask bits. [0:0] read-only OVERFLOW_MASKED Logical and of corresponding request and mask bits. [1:1] read-only FW_COLLISION_MASKED Logical and of corresponding request and mask bits. [2:2] read-only DSI_COLLISION_MASKED Logical and of corresponding request and mask bits. [3:3] read-only INJ_EOC_MASKED Logical and of corresponding request and mask bits. [4:4] read-only INJ_SATURATE_MASKED Logical and of corresponding request and mask bits. [5:5] read-only INJ_RANGE_MASKED Logical and of corresponding request and mask bits. [6:6] read-only INJ_COLLISION_MASKED Logical and of corresponding request and mask bits. [7:7] read-only SATURATE_INTR Saturate interrupt request register. 0x220 32 read-write 0x0 0xFFFF SATURATE_INTR Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. [15:0] read-write SATURATE_INTR_SET Saturate interrupt set request register 0x224 32 read-write 0x0 0xFFFF SATURATE_SET Write with '1' to set corresponding bit in interrupt request register. [15:0] read-write SATURATE_INTR_MASK Saturate interrupt mask register. 0x228 32 read-write 0x0 0xFFFF SATURATE_MASK Mask bit for corresponding bit in interrupt request register. [15:0] read-write SATURATE_INTR_MASKED Saturate interrupt masked request register 0x22C 32 read-only 0x0 0xFFFF SATURATE_MASKED Logical and of corresponding request and mask bits. [15:0] read-only RANGE_INTR Range detect interrupt request register. 0x230 32 read-write 0x0 0xFFFF RANGE_INTR Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. [15:0] read-write RANGE_INTR_SET Range detect interrupt set request register 0x234 32 read-write 0x0 0xFFFF RANGE_SET Write with '1' to set corresponding bit in interrupt request register. [15:0] read-write RANGE_INTR_MASK Range detect interrupt mask register. 0x238 32 read-write 0x0 0xFFFF RANGE_MASK Mask bit for corresponding bit in interrupt request register. [15:0] read-write RANGE_INTR_MASKED Range interrupt masked request register 0x23C 32 read-only 0x0 0xFFFF RANGE_MASKED Logical and of corresponding request and mask bits. [15:0] read-only INTR_CAUSE Interrupt cause register 0x240 32 read-only 0x0 0xC00000FF EOS_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [0:0] read-only OVERFLOW_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [1:1] read-only FW_COLLISION_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [2:2] read-only DSI_COLLISION_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [3:3] read-only INJ_EOC_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [4:4] read-only INJ_SATURATE_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [5:5] read-only INJ_RANGE_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [6:6] read-only INJ_COLLISION_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED [7:7] read-only SATURATE_MASKED_RED Reduction OR of all SAR_SATURATION_INTR_MASKED bits [30:30] read-only RANGE_MASKED_RED Reduction OR of all SAR_RANGE_INTR_MASKED bits [31:31] read-only INJ_CHAN_CONFIG Injection channel configuration register. 0x280 32 read-write 0x0 0xC0003577 INJ_PIN_ADDR Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair. [2:0] read-write INJ_PORT_ADDR Address of the port that contains the pin to be sampled by this channel. [6:4] read-write SARMUX SARMUX pins. 0 CTB0 CTB0 1 CTB1 CTB1 2 CTB2 CTB2 3 CTB3 CTB3 4 AROUTE_VIRT AROUTE virtual port 6 SARMUX_VIRT SARMUX virtual port 7 INJ_DIFFERENTIAL_EN Differential enable for this channel. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored). [8:8] read-write INJ_AVG_EN Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) [10:10] read-write INJ_SAMPLE_TIME_SEL Injection sample time select: select which of the 4 global sample times to use for this channel [13:12] read-write INJ_TAILGATING Injection channel tailgating. - 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set if the SAR is not busy. If the SAR is busy, the INJ channel addressed pin is sampled at the end of the current scan. - 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned. [30:30] read-write INJ_START_EN Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. [31:31] read-write INJ_RESULT Injection channel result register 0x290 32 read-only 0x0 0xF8000000 INJ_RESULT SAR conversion result of the channel. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [15:0] read-only INJ_NEWVALUE The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [27:27] read-only INJ_COLLISION_INTR_MIR mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [28:28] read-only INJ_SATURATE_INTR_MIR mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [29:29] read-only INJ_RANGE_INTR_MIR mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [30:30] read-only INJ_EOC_INTR_MIR mirror bit of corresponding bit in SAR_INTR register. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [31:31] read-only STATUS Current status of internal SAR registers (mostly for debug) 0x2A0 32 read-only 0x0 0xC000001F CUR_CHAN current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [4:0] read-only SW_VREF_NEG the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [30:30] read-only BUSY If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down. [31:31] read-only AVG_STAT Current averaging status (for debug) 0x2A4 32 read-only 0x0 0xFF8FFFFF CUR_AVG_ACCU the current value of the averaging accumulator. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [19:0] read-only INTRLV_BUSY If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR. [23:23] read-only CUR_AVG_CNT the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [31:24] read-only MUX_SWITCH0 SARMUX Firmware switch controls 0x300 32 read-write 0x0 0x3FFFFFFF MUX_FW_P0_VPLUS Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit. [0:0] read-write MUX_FW_P1_VPLUS Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit. [1:1] read-write MUX_FW_P2_VPLUS Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit. [2:2] read-write MUX_FW_P3_VPLUS Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit. [3:3] read-write MUX_FW_P4_VPLUS Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit. [4:4] read-write MUX_FW_P5_VPLUS Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit. [5:5] read-write MUX_FW_P6_VPLUS Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit. [6:6] read-write MUX_FW_P7_VPLUS Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit. [7:7] read-write MUX_FW_P0_VMINUS Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit. [8:8] read-write MUX_FW_P1_VMINUS Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit. [9:9] read-write MUX_FW_P2_VMINUS Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit. [10:10] read-write MUX_FW_P3_VMINUS Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit. [11:11] read-write MUX_FW_P4_VMINUS Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit. [12:12] read-write MUX_FW_P5_VMINUS Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit. [13:13] read-write MUX_FW_P6_VMINUS Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit. [14:14] read-write MUX_FW_P7_VMINUS Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit. [15:15] read-write MUX_FW_VSSA_VMINUS Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit. [16:16] read-write MUX_FW_TEMP_VPLUS Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, (also powers on the temperature sensor if AREF_CTRL.EN=1 (active mode) and AREF_CTRL.DEEPSLEEP=1 and AREF_CTRL.DEEPSLEEP_MODE=2 or 3 (required for deepsleep mode only). The Write with '1' to set bit. [17:17] read-write MUX_FW_AMUXBUSA_VPLUS Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit. [18:18] read-write MUX_FW_AMUXBUSB_VPLUS Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit. [19:19] read-write MUX_FW_AMUXBUSA_VMINUS Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit. [20:20] read-write MUX_FW_AMUXBUSB_VMINUS Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit. [21:21] read-write MUX_FW_SARBUS0_VPLUS Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit. [22:22] read-write MUX_FW_SARBUS1_VPLUS Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit. [23:23] read-write MUX_FW_SARBUS0_VMINUS Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit. [24:24] read-write MUX_FW_SARBUS1_VMINUS Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit. [25:25] read-write MUX_FW_P4_COREIO0 Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit. [26:26] read-write MUX_FW_P5_COREIO1 Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit. [27:27] read-write MUX_FW_P6_COREIO2 Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit. [28:28] read-write MUX_FW_P7_COREIO3 Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit. [29:29] read-write MUX_SWITCH_CLEAR0 SARMUX Firmware switch control clear 0x304 32 read-write 0x0 0x3FFFFFFF MUX_FW_P0_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [0:0] read-write MUX_FW_P1_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [1:1] read-write MUX_FW_P2_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [2:2] read-write MUX_FW_P3_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [3:3] read-write MUX_FW_P4_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [4:4] read-write MUX_FW_P5_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [5:5] read-write MUX_FW_P6_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [6:6] read-write MUX_FW_P7_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [7:7] read-write MUX_FW_P0_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [8:8] read-write MUX_FW_P1_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [9:9] read-write MUX_FW_P2_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [10:10] read-write MUX_FW_P3_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [11:11] read-write MUX_FW_P4_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [12:12] read-write MUX_FW_P5_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [13:13] read-write MUX_FW_P6_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [14:14] read-write MUX_FW_P7_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [15:15] read-write MUX_FW_VSSA_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [16:16] read-write MUX_FW_TEMP_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [17:17] read-write MUX_FW_AMUXBUSA_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [18:18] read-write MUX_FW_AMUXBUSB_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [19:19] read-write MUX_FW_AMUXBUSA_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [20:20] read-write MUX_FW_AMUXBUSB_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [21:21] read-write MUX_FW_SARBUS0_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [22:22] read-write MUX_FW_SARBUS1_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0 [23:23] read-write MUX_FW_SARBUS0_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [24:24] read-write MUX_FW_SARBUS1_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0 [25:25] read-write MUX_FW_P4_COREIO0 Write '1' to clear corresponding bit in MUX_SWITCH0 [26:26] read-write MUX_FW_P5_COREIO1 Write '1' to clear corresponding bit in MUX_SWITCH0 [27:27] read-write MUX_FW_P6_COREIO2 Write '1' to clear corresponding bit in MUX_SWITCH0 [28:28] read-write MUX_FW_P7_COREIO3 Write '1' to clear corresponding bit in MUX_SWITCH0 [29:29] read-write MUX_SWITCH_SQ_CTRL SARMUX switch Sar Sequencer control 0x344 32 read-write 0x0 0xCF00FF MUX_SQ_CTRL_P0 for P0 switches [0:0] read-write MUX_SQ_CTRL_P1 for P1 switches [1:1] read-write MUX_SQ_CTRL_P2 for P2 switches [2:2] read-write MUX_SQ_CTRL_P3 for P3 switches [3:3] read-write MUX_SQ_CTRL_P4 for P4 switches [4:4] read-write MUX_SQ_CTRL_P5 for P5 switches [5:5] read-write MUX_SQ_CTRL_P6 for P6 switches [6:6] read-write MUX_SQ_CTRL_P7 for P7 switches [7:7] read-write MUX_SQ_CTRL_VSSA for vssa switch [16:16] read-write MUX_SQ_CTRL_TEMP for temp switch [17:17] read-write MUX_SQ_CTRL_AMUXBUSA for amuxbusa switch [18:18] read-write MUX_SQ_CTRL_AMUXBUSB for amuxbusb switches [19:19] read-write MUX_SQ_CTRL_SARBUS0 for sarbus0 switch [22:22] read-write MUX_SQ_CTRL_SARBUS1 for sarbus1 switch [23:23] read-write MUX_SWITCH_STATUS SARMUX switch status 0x348 32 read-only 0x0 0x3FFFFFF MUX_FW_P0_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [0:0] read-only MUX_FW_P1_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [1:1] read-only MUX_FW_P2_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [2:2] read-only MUX_FW_P3_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [3:3] read-only MUX_FW_P4_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [4:4] read-only MUX_FW_P5_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [5:5] read-only MUX_FW_P6_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [6:6] read-only MUX_FW_P7_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [7:7] read-only MUX_FW_P0_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [8:8] read-only MUX_FW_P1_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [9:9] read-only MUX_FW_P2_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [10:10] read-only MUX_FW_P3_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [11:11] read-only MUX_FW_P4_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [12:12] read-only MUX_FW_P5_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [13:13] read-only MUX_FW_P6_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [14:14] read-only MUX_FW_P7_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [15:15] read-only MUX_FW_VSSA_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [16:16] read-only MUX_FW_TEMP_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [17:17] read-only MUX_FW_AMUXBUSA_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [18:18] read-only MUX_FW_AMUXBUSB_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [19:19] read-only MUX_FW_AMUXBUSA_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [20:20] read-only MUX_FW_AMUXBUSB_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [21:21] read-only MUX_FW_SARBUS0_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [22:22] read-only MUX_FW_SARBUS1_VPLUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [23:23] read-only MUX_FW_SARBUS0_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [24:24] read-only MUX_FW_SARBUS1_VMINUS switch status of corresponding bit in MUX_SWITCH0. This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [25:25] read-only SAR1 0x409C0000 PASS PASS top-level MMIO (AREF, LPOSC, FIFO, INTR, Trigger) 0x409F0000 0 65536 registers INTR_CAUSE Interrupt cause register 0x0 32 read-only 0x0 0xFFFF CTB0_INT CTB0 interrupt pending [0:0] read-only CTB1_INT CTB1 interrupt pending [1:1] read-only CTB2_INT CTB2 interrupt pending [2:2] read-only CTB3_INT CTB3 interrupt pending [3:3] read-only CTDAC0_INT CTDAC0 interrupt pending [4:4] read-only CTDAC1_INT CTDAC1 interrupt pending [5:5] read-only CTDAC2_INT CTDAC2 interrupt pending [6:6] read-only CTDAC3_INT CTDAC3 interrupt pending [7:7] read-only SAR0_INT SAR0 interrupt pending [8:8] read-only SAR1_INT SAR1 interrupt pending [9:9] read-only SAR2_INT SAR2 interrupt pending [10:10] read-only SAR3_INT SAR3 interrupt pending [11:11] read-only FIFO0_INT FIFO0 interrupt pending [12:12] read-only FIFO1_INT FIFO1 interrupt pending [13:13] read-only FIFO2_INT FIFO2 interrupt pending [14:14] read-only FIFO3_INT FIFO3 interrupt pending [15:15] read-only DPSLP_CLOCK_SEL Deepsleep clock select 0x10 32 read-write 0x20 0x71 DPSLP_CLOCK_SEL Select source for PASS DPSLP Clock [0:0] read-write CLK_LPOSC CLK_DPSLP is set to CLK_LPOSC 0 CLK_MF CLK_DPSLP is set to CLK_MF 1 DPSLP_CLOCK_DIV CLK_DPSLP divider [6:4] read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 DIV_BY_16 Divide selected clock source by 16 4 RSVD_0 N/A 5 RSVD_1 N/A 6 RSVD_2 N/A 7 ANA_PWR_CFG Analog power configuration 0x14 32 read-write 0x0 0xFFF PWR_UP_DELAY Power up time for analog blocks. Fastest power up time is achieved with a setting of 0. Additional time can be added to allow for analog settling. The power up time is in clk_dpslp cycles. This field is only applicable when SAR_CLOCK_SEL.CLOCK_SEL =1. [7:0] read-write DUTY_CYCLE_SAR_ACT_EN Enable for powering down (duty cycling) a SAR in chip active mode. This is a risk mitigation bit for power reduction in chip active mode. In order for this field affect SAR operation, the SAR must be configured for deepsleep clocking (SAR_CLOCK_SEL.CLOCK_SEL set to 1), and the SAR must be set for Timer-based hardware triggering (either by following the guidlines in SAR_OVR_CTRL.HW_TR_TIMER_SEL or SAR_SIMULT_CTRL.SIMULT_HW_TIMER_SEL). If this bit is set for a given SAR, the Timer is the only valid trigger source. Non-timer based Hardware (DSI) triggers cannot be used nor can Firmware based triggers (FW,Continuous,Injection). Furthermore, trigger collision functionality will be limited to interrupt generation only. -0: Legacy (SAR not duty cycled in chip active mode -1: SAR duty cycled in chip active mode <0>: Active Mode Duty Cycle enable for SAR0 <1>: Active Mode Duty Cycle enable for SAR1 <2>: Active Mode Duty Cycle enable for SAR2 <3>: Active Mode Duty Cycle enable for SAR3 This field is only applicable when SAR_CLOCK_SEL.CLOCK_SEL =1. This field can also affect LPOSC functionality in Active Mode (see LPOSC CONFIG.DEEPSLEEP_MODE field for details) [11:8] read-write 2 4 CTBM_CLOCK_SEL[%s] Clock select for CTBm 0x20 32 read-write 0x0 0x1 PUMP_CLOCK_SEL Select source for CTBm Pump Clock. [0:0] read-write LEGACY CTBm pump clock set by AREF.CTRL.CLOCK_PUMP_PERI_SEL (Legacy). When configured for legacy operation, the CTBm deeplseep functionality is determined solely by the CTRL.DEEPSLEEP_ON bit. 0 CLK_DPSLP CTBm pump clock sourced from CLK_DPSLP When configured for CLK_DPSLP operation, the CTBm deepsleep functionality is determined by the CTRL.DEEPSLEEP_ON bit AND SAR(s) operation (i.e. CTBm is duty cycled with the SAR(s)). In this mode, the CTBm should only be used as a buffer/gain stage for the SAR(s). 1 2 4 SAR_DPSLP_CTRL[%s] Deepsleep control for SARv3 0x30 32 read-write 0x0 0x80000000 ENABLED enable for SAR deepsleep operation. SAR_CLOCK_SEL.CLOCK_SEL must be set to 1 for this field to affect SAR operation. - 0: SAR deeepsleep operation disabled - 1: SAR deepsleep operation enabled. [31:31] read-write 2 4 SAR_CLOCK_SEL[%s] Clock select for SARv3 0x40 32 read-write 0x0 0x40000000 CLOCK_SEL SAR clock select [30:30] read-write LEGACY - 0: legacy: SAR clock source is CLK_PERI (SAR is only operational in chip ACTIVE mode) 0 CLK_DPSLP - 1: SAR clock source is CLK_DPSLP (SAR can be operational in both chip ACTIVE and DEEPSLEEP modes) 1 2 4 SAR_TR_SCAN_CNT_STATUS[%s] SAR trigger scan control status 0x50 32 read-only 0x0 0xFF SCAN_CNT_STATUS A read from this register returns the current sample count (possible values are 1 through SCAN_TR_SCAN_CNT.SCAN_CNT+1). This field cannot be read if SAR_CLOCK_SEL.CLOCK_SEL =1. [7:0] read-only SAR_TR_SCAN_CNT SAR trigger scan control 0x60 32 read-write 0x0 0xFF SCAN_CNT SAR trigger sample counter. This field determines the number of samples a SAR will take when triggered. The number of samples is SCAN_COUNT+1. This feature can be enabled for individual SARs by setting the appropriate bit of SAR_TR_CTRL.TR_SCAN_CNT_SEL. This feature can be enabled for simultaneously sampled SARs by setting SAR_SIMULT_TR_CTRL.SIMULT_TR_SCAN_CNT_SEL. If SAR.SAMPLE_CTRL.AVG_MODE is set to INTERLEAVED, the SCAN_CNT must be set an integer multiple of (1<<AVG_CNTR+1). [7:0] read-write SAR_OVR_CTRL SAR HW trigger override 0x64 32 read-write 0x0 0xFFF HW_TR_TIMER_SEL SAR hardware trigger source select (one bit per SAR). SAR must be configured for hardware triggering (SAR.SAMPLE_CTRL.DSI_TRIGGER_EN must be set to 1). -0: Legacy (tr_sar_in_<N>) -1: Timer trigger <0>: HW Trigger source for SAR0 <1>: HW Trigger source for SAR1 <2>: HW Trigger source for SAR2 <3>: HW Trigger source for SAR3 [3:0] read-write TR_SCAN_CNT_SEL SAR trigger sample select (one bit per SAR). -0: Disabled -1: Enabled, SAR takes SAR_TR_SCAN_CNT per trigger (valid for both Firmware and Edge Senstive Hardware triggering, but ignored for Level Sensitive Hardware triggering and CONTINUOUS triggering). This feature cannot be enabled if the SAR is configured for Non-Tailgating Injection (SAR.INJ_CHAN_CONFIG.INJ_TAILGATING=0 while SAR.INJ_CHAN_CONFIG.INJ_START_EN=1) <0>: trigger sample select for SAR0 <1>: trigger sample select for SAR1 <2>: trigger sample select for SAR2 <3>: trigger sample select for SAR3 [7:4] read-write EOS_INTR_SCAN_CNT_SEL SAR EOS interrupt source select (one bit per SAR). This feature is not available for FW or Continuous triggering. -0: Legacy (SAR EOS is the source of the SAR EOS interrupt) -1: Enabled, SAR EOS interrupt only occurs for the EOS when sample=SAR_TR_SCAN_CNT.SCAN_CNT. <0>: EOS interrupt sample count select for SAR0 <1>: EOS interrupt sample count select for SAR1 <2>: EOS interrupt sample count select for SAR2 <3>: EOS interrupt sample count select for SAR3 [11:8] read-write SAR_SIMULT_CTRL SAR simultaneous trigger control 0x68 32 read-write 0x80000 0x3C013F SIMULT_HW_TR_EN SAR simultaneous hardware triggering enable (one bit per SAR) -0: disabled -1: SAR trigger override enabled (SAR trigger set by SAR_OVR_CTRL register) <0>: Simultaneuous sampling enable for SAR0 <1>: Simultaneuous sampling enable for SAR1 <2>: Simultaneuous sampling enable for SAR2 <3>: Simultaneuous sampling enable for SAR3 Simultaneous sampling requires at least two bits in this field to be set. If less than two bits are set, this register will not affect SAR operation. [3:0] read-write SIMULT_HW_TR_SRC Source for Simult Hardware trigger [5:4] read-write SAR_TR_IN_0 SAR 0 HW Trigger Input 0 SAR_TR_IN_1 SAR 1 HW Trigger Input 1 SAR_TR_IN_2 SAR 2 HW Trigger Input 2 SAR_TR_IN_3 SAR 3 HW Trigger Input 3 SIMULT_HW_TR_TIMER_SEL SAR hardware trigger source select -0: SIMULT_HW_TR_SRC -1: Timer trigger [8:8] read-write SIMULT_HW_TR_LEVEL - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. - 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. [18:18] read-write SIMULT_HW_SYNC_TR - 0: bypass clock domain synchronization of the Simult trigger signal. - 1: synchronize the Simult trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. [19:19] read-write SIMULT_TR_SCAN_CNT_SEL Simultaneous trigger sample select -0: Disabled -1: Enabled, SAR takes SAR_TR_SCAN_CNT per trigger (valid for both Firmware and Edge Senstive Hardware triggering, but ignored for Level Sensitive Hardware triggering and CONTINUOUS triggering) This feature cannot be enabled if either SAR is configured for Non-Tailgating Injection (SAR.INJ_CHAN_CONFIG.INJ_TAILGATING=0 while SAR.INJ_CHAN_CONFIG.INJ_START_EN=1) [20:20] read-write SIMULT_EOS_INTR_SCAN_CNT_SEL Simultaneous SAR EOS interrupt source select. This feature is not available for FW or Continuous triggering. -0: Legacy (SAR EOS is the source of the SAR EOS interrupt) -1: Enabled, SAR EOS interrupt only occurs for the EOS when sample=SAR_TR_SCAN_CNT.SCAN_CNT. [21:21] read-write SAR_SIMULT_FW_START_CTRL SAR simultaneous start control 0x6C 32 read-write 0x0 0xF000F FW_TRIGGER This field is used to simultaneously FW trigger two or more SARs. <0>: Firmware trigger for SAR0 <1>: Firmware trigger for SAR1 <2>: Firmware trigger for SAR2 <3>: Firmware trigger for SAR3 If less than two bits are set, this field has no effect. When firmware writes to this field it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. [3:0] read-write CONTINUOUS This field is used to configure two or more SARs for continuous operation. -0: Continuous mode disabled -1: Continuously scan enabled channels, ignore triggers. <0>: Continuous Mode for SAR0 <1>: Continuous Mode for SAR1 <2>: Continuous Mode for SAR2 <3>: Continuous Mode for SAR3 If less than two bits are set, this field has no effect. This field cannot be set when SAR_CLOCK_SEL.CLOCK_SEL =1. [19:16] read-write SAR_TR_OUT_CTRL SAR trigger out control 0x70 32 read-write 0x0 0xF SAR0_TR_OUT_SEL SAR0 Trigger Out Source Select [0:0] read-write LEGACY sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition 0 BUFFER_TRIGGER_LEVEL sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition 1 SAR1_TR_OUT_SEL SAR1 Trigger Out Source Select [1:1] read-write LEGACY sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition 0 BUFFER_TRIGGER_LEVEL sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition 1 SAR2_TR_OUT_SEL SAR2 Trigger Out Source Select [2:2] read-write LEGACY sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition 0 BUFFER_TRIGGER_LEVEL sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition 1 SAR3_TR_OUT_SEL SAR3 Trigger Out Source Select [3:3] read-write LEGACY sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition 0 BUFFER_TRIGGER_LEVEL sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition 1 TIMER Programmable Analog Subsystem 0x00000100 CTRL Timer trigger control register 0x0 32 read-write 0x0 0x80000000 ENABLED 0=disabled, 1=enabled Upon enable, the timer will immediately generate a trigger pulse (lasting for one clock cycle of the selected CONFIF.CLOCK_SEL) and will generate subsequent trigger pulses (again lasting one clock cycle) whenever the timer reaches terminal count. If PERIOD.PER_VAL is set to 0, the timer trigger output will remain high as long as the timer is enabled. [31:31] read-write CONFIG Timer trigger configuration register 0x4 32 read-write 0x0 0x3 CLOCK_SEL Select Clock source of the Timer [1:0] read-write CLK_PERI Timer clocked from CLK_PERI 0 CLK_DPSLP Timer clocked from CLK_DPSLP 1 CLK_LF Timer clocked from CLK_LF 2 TBD N/A 3 PERIOD Timer trigger period register 0x8 32 read-write 0x0 0xFFFF PER_VAL Actual timer period is PER_VAL+1 (1 to 65536). Only non-zero PER_VAL are supported. (i.e. PER_VAL=0 is considered invalid). [15:0] read-write LPOSC LPOSC configuration 0x00000200 CTRL Low Power Oscillator control 0x0 32 read-write 0x80000000 0x80000000 ENABLED Master enable for LPOSC oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the LPOSC during DEEPSLEEP (unless DEEPSLEEP_MODE is set) [31:31] read-write CONFIG Low Power Oscillator configuration register 0x4 32 read-write 0x0 0x1 DEEPSLEEP_MODE LPOSC functionality while in DEEPSLEEP. If the ANA_PWR_CFG.DUTY_CYCLE_SAR_ACT_EN bit of a Deepsleep configured SAR is set, the DEEPSLEEP_MODE field for the LPOSC also applies to chip active mode (i.e. the LPOSC will get duty cycled in chip active mode if DEEPSLEEP_MODE=0 and DUTY_CYLE_SAR_ACT_EN=1 for all Deepsleep enabled SAR(s)) [0:0] read-write DUTYCYCLED LPOSC enabled by TIMER trigger 0 ALWAYS_ON LPOSC always on in deepsleep 1 ADFT Retention, Hidden 0x8 32 read-write 0x0 0x3 ADFT_SEL ADFT selection for LPOSC. 0: DFT disabled 1: Measure Vdo; expect ~0.8V 2: Measure Ibias_ptat; expect ~250nA 3: Measure Ibias_ctat; expect ~550nA [1:0] read-write 2 256 FIFO[%s] FIFO configuration 0x00000300 CTRL FIFO control register 0x0 32 read-write 0x0 0x80000000 ENABLED Enable for SAR FIFO functionality. If CONFIG.CHAIN_TO_NXT is set, the ENABLED bit of the NEXT FIFO is set when FIFO[0] is enabled. - 0: FIFO disabled - 1: FIFO enabled [31:31] read-write CONFIG FIFO configuration register 0x4 32 read-write 0x0 0x7 CHAN_ID_EN channel number (ID) enable bit -0: CHAN_ID field in RD_DATA is disabled. A read from RD_DATA will result in (4'b0,16'b RESULT) -1: CHAN_ID field in RD_DATA is enabled. A read from RD_DATA will result in (4'b CHAN_ID, 16'b RESULT) If CHAIN_EN is enabled, only FIFO[0].config.chan_id_en should be configured and the other FIFOs in the chain will inherit the FIFO[0] config. [0:0] read-write CHAIN_TO_NXT Chain FIFO to next FIFO (i.e. chain FIFO0 and FIFO1). - 0: FIFO not chained . FIFO operates independently (FIFO depth of 64) and only operates on result data from its associated SAR. - 1: FIFO chained to next FIFO. FIFO is part of a chain of FIFOs (effectively extending the FIFO depth beyond 64) and only operates on result data from SAR0. [1:1] read-write TR_INTR_CLR_RD_EN Enable for FIFO read clearing the FIFO level trigger and level interrupt. - 0: Disabled, FIFO level trigger and level interrupt generation follows LEVEL.LEVEL. - 1: Enabled, after initial FIFO level trigger and level interrupt generation, subsequent FIFO level triggers and level interrupts are blocked until at least FIFO.LEVEL+1 reads have occurred. If CHAIN_TO_NXT is enabled, only FIFO[0].CONFIG. TR_CLR_RD_EN should be configured. [2:2] read-write CLEAR FIFO clear register 0x8 32 read-write 0x0 0x1 CLEAR When firmware writes a 1 here it will trigger and clearing of the FIFO status registers (excluding interrupts), hardware clears this bit. [0:0] read-write LEVEL FIFO level register 0xC 32 read-write 0x0 0xFF LEVEL FIFO level set. A trigger (and optional interrupt) event occurs when USED.USED = LEVEL+1. (Trigger generation is also affect by CONFIG.TR_CLR_RD_EN). If CHAIN_TO_NXT is disabled, the Max LEVEL is limited to 63. If CHAIN_TO_NXT is enabled, only FIFO[0].config.level should be configured and the Max LEVEL is set by the number of FIFOs in the chain. [7:0] read-write USED FIFO used register 0x10 32 read-only 0x0 0xFF USED Number of used/occupied entries in the FIFO. If CONFIG.CHAIN_EN is disabled, the field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full. If CONFIG.CHAIN_EN is enabled, only FIFO[0].USED.USED should be read to detemine the used status. [7:0] read-only STATUS FIFO status register 0x14 32 read-only 0x0 0xFFFF RD_PTR FIFO read pointer: FIFO location from which a data is read. Note: This functionality is intended for debugging purposes. If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].STATUS.RD_PTR should be read to detemine the read pointer location of the chained FIFO. [7:0] read-only WR_PTR FIFO write pointer: FIFO location at which a new data is written by the hardware. Note: This functionality is intended for debugging purposes. If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].STATUS.WR_PTR should be read to detemine the write pointer location of the chained FIFO. [15:8] read-only RD_DATA FIFO read data register 0x18 32 read-only 0x0 0xFFFFF RESULT SAR result. Results from all enabled channels are stored in the buffer. If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].RD_DATA.RESULT should be read. [15:0] read-only CHAN_ID Channel number for a given SAR result. Requires CTRL.CHAN_ID_EN to be set. If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].RD_DATA.CHAN_ID should be read. [19:16] read-only INTR Interrupt register 0x20 32 read-write 0x0 0x7 FIFO_LEVEL HW sets this field to '1', when STATUS.USED >= CTRL.LEVEL+1 If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR.FIFO_LEVEL is updated by hardware. Write with '1' to clear bit. [0:0] read-write FIFO_OVERFLOW HW sets this field to '1', when writing to a full FIFO (FIFO_STATUS.USED is '64'). If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR.FIFO_OVERFLOW is updated by hardware. Write with '1' to clear bit. [1:1] read-write FIFO_UNDERFLOW HW sets this field to '1', when reading from an empty FIFO. HW tracks underflow after FIFO is being written to and FIFO_CTL.ENABLE==1. If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR.FIFO_UNDERFLOW is updated by hardware. Write with '1' to clear bit. [2:2] read-write INTR_SET Interrupt set register 0x24 32 read-write 0x0 0x7 FIFO_LEVEL Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). [0:0] read-write FIFO_OVERFLOW Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). [1:1] read-write FIFO_UNDERFLOW Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). [2:2] read-write INTR_MASK Interrupt mask register 0x28 32 read-write 0x0 0x7 FIFO_LEVEL Mask for corresponding field in INTR register. If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR_MASK.FIFO_LEVEL should be set. [0:0] read-write FIFO_OVERFLOW Mask for corresponding field in INTR register. If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR_MASK.FIFO_OVERFLOW should be set. [1:1] read-write FIFO_UNDERFLOW Mask for corresponding field in INTR register. If CONFIG.CHAIN_TO_NXT is enabled, only FIFO[0].INTR_MASK.FIFO_UNDERFLOW should be set. [2:2] read-write INTR_MASKED Interrupt masked register 0x2C 32 read-only 0x0 0x7 FIFO_LEVEL Logical AND of corresponding INTR and INTR_MASK fields. [0:0] read-only FIFO_OVERFLOW Logical AND of corresponding INTR and INTR_MASK fields. [1:1] read-only FIFO_UNDERFLOW Logical AND of corresponding INTR and INTR_MASK fields. [2:2] read-only AREFV2 AREF configuration 0x00000E00 AREF_CTRL global AREF control 0x0 32 read-write 0x0 0xF039FFFD AREF_MODE Control bit to trade off AREF settling and noise performance [0:0] read-write NORMAL Nominal noise normal startup mode (meets normal mode settling and noise specifications) 0 FAST_START High noise fast startup mode (meets fast mode settling and noise specifications) 1 AREF_BIAS_SCALE BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) 0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) 1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications) 2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) 3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times) [3:2] read-write AREF_RMB AREF control signals (RMB). Bit 0: Manual VBG startup circuit enable 0: normal VBG startup circuit operation 1: VBG startup circuit is forced 'always on' Bit 1: Manual disable of IPTAT2 DAC 0: normal IPTAT2 DAC operation 1: PTAT2 DAC is disabled while VBG startup is active Bit 2: Manual enable of VBG offset correction DAC 0: normal VBG offset correction DAC operation 1: VBG offset correction DAC is enabled while VBG startup is active [6:4] read-write CTB_IPTAT_SCALE CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). 0: 1uA 1: 100nA [7:7] read-write CTB_IPTAT_REDIRECT Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). 0: Opamp<n>.IPTAT = AREF.IPTAT and Opamp<n>.IZTAT= AREF.IZTAT 1: Opamp<n>.IPTAT = HiZ and Opamp<n>.IZTAT= AREF.IPTAT *Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ. [15:8] read-write IZTAT_SEL iztat current select control [16:16] read-write SRSS Use 250nA IZTAT from SRSS 0 LOCAL Use locally generated 250nA 1 CLOCK_PUMP_PERI_SEL CTBm charge pump clock source select. This field has nothing to do with the AREF. 0: Use the dedicated pump clock from SRSS (default) 1: Use one of the CLK_PERI dividers [19:19] read-write VREF_SEL bandgap voltage select control [21:20] read-write SRSS Use 0.8V Vref from SRSS 0 LOCAL Use locally generated Vref 1 EXTERNAL Use externally supplied Vref (aref_ext_vref) 2 DEEPSLEEP_MODE AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1) [29:28] read-write OFF All blocks 'OFF' in DeepSleep 0 IPTAT IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available) 1 IPTAT_IZTAT IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep) *Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep 2 IPTAT_IZTAT_VREF IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode. 3 DEEPSLEEP_ON - 0: AREF IP disabled/off during DeepSleep power mode - 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1) [30:30] read-write ENABLED Disable AREF [31:31] read-write VREF_TRIM0 VREF Trim bits 0xF00 32 read-write 0x0 0xFF VREF_ABS_TRIM N/A [7:0] read-write VREF_TRIM1 VREF Trim bits 0xF04 32 read-write 0x0 0xFF VREF_TEMPCO_TRIM N/A [7:0] read-write VREF_TRIM2 VREF Trim bits 0xF08 32 read-write 0x0 0xFF VREF_CURV_TRIM N/A [7:0] read-write VREF_TRIM3 VREF Trim bits 0xF0C 32 read-write 0x0 0xF VREF_ATTEN_TRIM Obsolete [3:0] read-write IZTAT_TRIM0 VREF Trim bits 0xF10 32 read-write 0x0 0xFF IZTAT_ABS_TRIM N/A [7:0] read-write IZTAT_TRIM1 IZTAT Trim bits 0xF14 32 read-write 0x0 0xFF IZTAT_TC_TRIM IZTAT temperature correction trim (RMB) 0x00 : No IZTAT temperature correction 0xFF : Maximum IZTAT temperature correction As this is a Risk Mitigation Register, it should be loaded with 0x08. [7:0] read-write IPTAT_TRIM0 IPTAT Trim bits 0xF18 32 read-write 0x0 0xFF IPTAT_CORE_TRIM IPTAT trim 0x0 : Minimum IPTAT current (~150nA at room) 0xF : Maximum IPTAT current (~350nA at room) [3:0] read-write IPTAT_CTBM_TRIM CTMB PTAT Current Trim 0x0 : Minimum CTMB IPTAT Current (~875nA) 0xF : Maximum CTMB IPTAT Current (~1.1uA) [7:4] read-write ICTAT_TRIM0 ICTAT Trim bits 0xF1C 32 read-write 0x0 0xF ICTAT_TRIM ICTAT trim 0x00 : Minimum ICTAT current (~150nA at room) 0x0F : Maximum ICTAT current (~350nA at room) [3:0] read-write