/* * Autogenerated file * * SPDX-License-Identifier: Apache 2.0 */ #include "gd32-af.h" /* ADC_IN0 */ #define ADC_IN0_PA0 \ GD32_PINMUX_AF('A', 0, ANALOG) /* ADC_IN1 */ #define ADC_IN1_PA1 \ GD32_PINMUX_AF('A', 1, ANALOG) /* ADC_IN2 */ #define ADC_IN2_PA2 \ GD32_PINMUX_AF('A', 2, ANALOG) /* ADC_IN3 */ #define ADC_IN3_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) /* ADC_IN4 */ #define ADC_IN4_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) /* ADC_IN5 */ #define ADC_IN5_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) /* ADC_IN6 */ #define ADC_IN6_PA6 \ GD32_PINMUX_AF('A', 6, ANALOG) /* ADC_IN7 */ #define ADC_IN7_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) /* ADC_IN8 */ #define ADC_IN8_PB0 \ GD32_PINMUX_AF('B', 0, ANALOG) /* ADC_IN9 */ #define ADC_IN9_PB1 \ GD32_PINMUX_AF('B', 1, ANALOG) /* ANALOG */ #define ANALOG_PA0 \ GD32_PINMUX_AF('A', 0, ANALOG) #define ANALOG_PA1 \ GD32_PINMUX_AF('A', 1, ANALOG) #define ANALOG_PA10 \ GD32_PINMUX_AF('A', 10, ANALOG) #define ANALOG_PA11 \ GD32_PINMUX_AF('A', 11, ANALOG) #define ANALOG_PA12 \ GD32_PINMUX_AF('A', 12, ANALOG) #define ANALOG_PA13 \ GD32_PINMUX_AF('A', 13, ANALOG) #define ANALOG_PA14 \ GD32_PINMUX_AF('A', 14, ANALOG) #define ANALOG_PA15 \ GD32_PINMUX_AF('A', 15, ANALOG) #define ANALOG_PA2 \ GD32_PINMUX_AF('A', 2, ANALOG) #define ANALOG_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) #define ANALOG_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) #define ANALOG_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) #define ANALOG_PA6 \ GD32_PINMUX_AF('A', 6, ANALOG) #define ANALOG_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) #define ANALOG_PA8 \ GD32_PINMUX_AF('A', 8, ANALOG) #define ANALOG_PA9 \ GD32_PINMUX_AF('A', 9, ANALOG) #define ANALOG_PB0 \ GD32_PINMUX_AF('B', 0, ANALOG) #define ANALOG_PB1 \ GD32_PINMUX_AF('B', 1, ANALOG) #define ANALOG_PB10 \ GD32_PINMUX_AF('B', 10, ANALOG) #define ANALOG_PB11 \ GD32_PINMUX_AF('B', 11, ANALOG) #define ANALOG_PB12 \ GD32_PINMUX_AF('B', 12, ANALOG) #define ANALOG_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) #define ANALOG_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) #define ANALOG_PB15 \ GD32_PINMUX_AF('B', 15, ANALOG) #define ANALOG_PB2 \ GD32_PINMUX_AF('B', 2, ANALOG) #define ANALOG_PB3 \ GD32_PINMUX_AF('B', 3, ANALOG) #define ANALOG_PB4 \ GD32_PINMUX_AF('B', 4, ANALOG) #define ANALOG_PB5 \ GD32_PINMUX_AF('B', 5, ANALOG) #define ANALOG_PB6 \ GD32_PINMUX_AF('B', 6, ANALOG) #define ANALOG_PB7 \ GD32_PINMUX_AF('B', 7, ANALOG) #define ANALOG_PB8 \ GD32_PINMUX_AF('B', 8, ANALOG) #define ANALOG_PB9 \ GD32_PINMUX_AF('B', 9, ANALOG) #define ANALOG_PC10 \ GD32_PINMUX_AF('C', 10, ANALOG) #define ANALOG_PC11 \ GD32_PINMUX_AF('C', 11, ANALOG) #define ANALOG_PC12 \ GD32_PINMUX_AF('C', 12, ANALOG) #define ANALOG_PC13 \ GD32_PINMUX_AF('C', 13, ANALOG) #define ANALOG_PC14 \ GD32_PINMUX_AF('C', 14, ANALOG) #define ANALOG_PC15 \ GD32_PINMUX_AF('C', 15, ANALOG) #define ANALOG_PC6 \ GD32_PINMUX_AF('C', 6, ANALOG) #define ANALOG_PC7 \ GD32_PINMUX_AF('C', 7, ANALOG) #define ANALOG_PD3 \ GD32_PINMUX_AF('D', 3, ANALOG) #define ANALOG_PF0 \ GD32_PINMUX_AF('F', 0, ANALOG) #define ANALOG_PF1 \ GD32_PINMUX_AF('F', 1, ANALOG) /* CK_OUT */ #define CK_OUT_PA8 \ GD32_PINMUX_AF('A', 8, AF0) #define CK_OUT_PA9 \ GD32_PINMUX_AF('A', 9, AF0) #define CK_OUT_PB13 \ GD32_PINMUX_AF('B', 13, AF0) /* CMP0_OUT */ #define CMP0_OUT_PA0 \ GD32_PINMUX_AF('A', 0, AF6) #define CMP0_OUT_PA11 \ GD32_PINMUX_AF('A', 11, AF6) #define CMP0_OUT_PA6 \ GD32_PINMUX_AF('A', 6, AF6) #define CMP0_OUT_PB0 \ GD32_PINMUX_AF('B', 0, AF6) #define CMP0_OUT_PB10 \ GD32_PINMUX_AF('B', 10, AF6) #define CMP0_OUT_PB8 \ GD32_PINMUX_AF('B', 8, AF6) /* CMP1_OUT */ #define CMP1_OUT_PA12 \ GD32_PINMUX_AF('A', 12, AF6) #define CMP1_OUT_PA2 \ GD32_PINMUX_AF('A', 2, AF6) #define CMP1_OUT_PA7 \ GD32_PINMUX_AF('A', 7, AF6) #define CMP1_OUT_PB11 \ GD32_PINMUX_AF('B', 11, AF6) #define CMP1_OUT_PB5 \ GD32_PINMUX_AF('B', 5, AF8) #define CMP1_OUT_PB9 \ GD32_PINMUX_AF('B', 9, AF6) /* CTC_SYNC */ #define CTC_SYNC_PA8 \ GD32_PINMUX_AF('A', 8, AF8) /* DAC_OUT */ #define DAC_OUT_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) /* EVENTOUT */ #define EVENTOUT_PA0 \ GD32_PINMUX_AF('A', 0, AF9) #define EVENTOUT_PA1 \ GD32_PINMUX_AF('A', 1, AF9) #define EVENTOUT_PA10 \ GD32_PINMUX_AF('A', 10, AF9) #define EVENTOUT_PA11 \ GD32_PINMUX_AF('A', 11, AF9) #define EVENTOUT_PA12 \ GD32_PINMUX_AF('A', 12, AF9) #define EVENTOUT_PA13 \ GD32_PINMUX_AF('A', 13, AF9) #define EVENTOUT_PA14 \ GD32_PINMUX_AF('A', 14, AF9) #define EVENTOUT_PA15 \ GD32_PINMUX_AF('A', 15, AF9) #define EVENTOUT_PA2 \ GD32_PINMUX_AF('A', 2, AF9) #define EVENTOUT_PA3 \ GD32_PINMUX_AF('A', 3, AF9) #define EVENTOUT_PA4 \ GD32_PINMUX_AF('A', 4, AF9) #define EVENTOUT_PA5 \ GD32_PINMUX_AF('A', 5, AF9) #define EVENTOUT_PA6 \ GD32_PINMUX_AF('A', 6, AF9) #define EVENTOUT_PA7 \ GD32_PINMUX_AF('A', 7, AF9) #define EVENTOUT_PA8 \ GD32_PINMUX_AF('A', 8, AF9) #define EVENTOUT_PA9 \ GD32_PINMUX_AF('A', 9, AF9) #define EVENTOUT_PB0 \ GD32_PINMUX_AF('B', 0, AF9) #define EVENTOUT_PB1 \ GD32_PINMUX_AF('B', 1, AF9) #define EVENTOUT_PB10 \ GD32_PINMUX_AF('B', 10, AF9) #define EVENTOUT_PB11 \ GD32_PINMUX_AF('B', 11, AF9) #define EVENTOUT_PB12 \ GD32_PINMUX_AF('B', 12, AF9) #define EVENTOUT_PB13 \ GD32_PINMUX_AF('B', 13, AF9) #define EVENTOUT_PB14 \ GD32_PINMUX_AF('B', 14, AF9) #define EVENTOUT_PB15 \ GD32_PINMUX_AF('B', 15, AF9) #define EVENTOUT_PB2 \ GD32_PINMUX_AF('B', 2, AF9) #define EVENTOUT_PB3 \ GD32_PINMUX_AF('B', 3, AF9) #define EVENTOUT_PB4 \ GD32_PINMUX_AF('B', 4, AF9) #define EVENTOUT_PB5 \ GD32_PINMUX_AF('B', 5, AF9) #define EVENTOUT_PB6 \ GD32_PINMUX_AF('B', 6, AF9) #define EVENTOUT_PB7 \ GD32_PINMUX_AF('B', 7, AF9) #define EVENTOUT_PB8 \ GD32_PINMUX_AF('B', 8, AF9) #define EVENTOUT_PB9 \ GD32_PINMUX_AF('B', 9, AF9) #define EVENTOUT_PC10 \ GD32_PINMUX_AF('C', 10, AF9) #define EVENTOUT_PC11 \ GD32_PINMUX_AF('C', 11, AF9) #define EVENTOUT_PC12 \ GD32_PINMUX_AF('C', 12, AF9) #define EVENTOUT_PC13 \ GD32_PINMUX_AF('C', 13, AF9) #define EVENTOUT_PC14 \ GD32_PINMUX_AF('C', 14, AF9) #define EVENTOUT_PC15 \ GD32_PINMUX_AF('C', 15, AF9) #define EVENTOUT_PC6 \ GD32_PINMUX_AF('C', 6, AF9) #define EVENTOUT_PC7 \ GD32_PINMUX_AF('C', 7, AF9) #define EVENTOUT_PF0 \ GD32_PINMUX_AF('F', 0, AF9) #define EVENTOUT_PF1 \ GD32_PINMUX_AF('F', 1, AF9) /* I2C0_SCL */ #define I2C0_SCL_PA13 \ GD32_PINMUX_AF('A', 13, AF4) #define I2C0_SCL_PA9 \ GD32_PINMUX_AF('A', 9, AF4) #define I2C0_SCL_PB6 \ GD32_PINMUX_AF('B', 6, AF4) #define I2C0_SCL_PB8 \ GD32_PINMUX_AF('B', 8, AF4) /* I2C0_SDA */ #define I2C0_SDA_PA10 \ GD32_PINMUX_AF('A', 10, AF4) #define I2C0_SDA_PA14 \ GD32_PINMUX_AF('A', 14, AF4) #define I2C0_SDA_PB7 \ GD32_PINMUX_AF('B', 7, AF4) #define I2C0_SDA_PB9 \ GD32_PINMUX_AF('B', 9, AF4) /* I2C0_SMBA */ #define I2C0_SMBA_PA1 \ GD32_PINMUX_AF('A', 1, AF4) #define I2C0_SMBA_PB5 \ GD32_PINMUX_AF('B', 5, AF4) /* I2C1_SCL */ #define I2C1_SCL_PB10 \ GD32_PINMUX_AF('B', 10, AF4) #define I2C1_SCL_PB13 \ GD32_PINMUX_AF('B', 13, AF4) #define I2C1_SCL_PB6 \ GD32_PINMUX_AF('B', 6, AF8) #define I2C1_SCL_PB8 \ GD32_PINMUX_AF('B', 8, AF8) /* I2C1_SDA */ #define I2C1_SDA_PB11 \ GD32_PINMUX_AF('B', 11, AF4) #define I2C1_SDA_PB14 \ GD32_PINMUX_AF('B', 14, AF4) #define I2C1_SDA_PB7 \ GD32_PINMUX_AF('B', 7, AF8) #define I2C1_SDA_PB9 \ GD32_PINMUX_AF('B', 9, AF8) /* I2C1_SMBA */ #define I2C1_SMBA_PB12 \ GD32_PINMUX_AF('B', 12, AF4) /* I2S1_CK */ #define I2S1_CK_PB10 \ GD32_PINMUX_AF('B', 10, AF5) #define I2S1_CK_PB13 \ GD32_PINMUX_AF('B', 13, AF6) #define I2S1_CK_PB3 \ GD32_PINMUX_AF('B', 3, AF6) #define I2S1_CK_PC10 \ GD32_PINMUX_AF('C', 10, AF5) #define I2S1_CK_PF1 \ GD32_PINMUX_AF('F', 1, AF5) /* I2S1_MCK */ #define I2S1_MCK_PC6 \ GD32_PINMUX_AF('C', 6, AF5) #define I2S1_MCK_PD3 \ GD32_PINMUX_AF('D', 3, AF6) /* I2S1_SD */ #define I2S1_SD_PB15 \ GD32_PINMUX_AF('B', 15, AF6) #define I2S1_SD_PB5 \ GD32_PINMUX_AF('B', 5, AF6) #define I2S1_SD_PC12 \ GD32_PINMUX_AF('C', 12, AF5) /* I2S1_WS */ #define I2S1_WS_PA14 \ GD32_PINMUX_AF('A', 14, AF6) #define I2S1_WS_PA15 \ GD32_PINMUX_AF('A', 15, AF6) #define I2S1_WS_PA4 \ GD32_PINMUX_AF('A', 4, AF6) #define I2S1_WS_PB12 \ GD32_PINMUX_AF('B', 12, AF6) #define I2S1_WS_PB9 \ GD32_PINMUX_AF('B', 9, AF5) #define I2S1_WS_PF0 \ GD32_PINMUX_AF('F', 0, AF5) /* LPTIMER_ETI0 */ #define LPTIMER_ETI0_PA5 \ GD32_PINMUX_AF('A', 5, AF2) #define LPTIMER_ETI0_PA7 \ GD32_PINMUX_AF('A', 7, AF2) #define LPTIMER_ETI0_PB6 \ GD32_PINMUX_AF('B', 6, AF2) /* LPTIMER_IN0 */ #define LPTIMER_IN0_PA6 \ GD32_PINMUX_AF('A', 6, AF2) #define LPTIMER_IN0_PB1 \ GD32_PINMUX_AF('B', 1, AF2) #define LPTIMER_IN0_PB5 \ GD32_PINMUX_AF('B', 5, AF2) /* LPTIMER_IN1 */ #define LPTIMER_IN1_PA9 \ GD32_PINMUX_AF('A', 9, AF2) #define LPTIMER_IN1_PB3 \ GD32_PINMUX_AF('B', 3, AF2) /* LPTIMER_OUT */ #define LPTIMER_OUT_PA4 \ GD32_PINMUX_AF('A', 4, AF2) #define LPTIMER_OUT_PA8 \ GD32_PINMUX_AF('A', 8, AF2) #define LPTIMER_OUT_PB0 \ GD32_PINMUX_AF('B', 0, AF2) #define LPTIMER_OUT_PB2 \ GD32_PINMUX_AF('B', 2, AF2) /* LPUART_CTS */ #define LPUART_CTS_PA6 \ GD32_PINMUX_AF('A', 6, AF8) #define LPUART_CTS_PB13 \ GD32_PINMUX_AF('B', 13, AF8) /* LPUART_RTS */ #define LPUART_RTS_PB1 \ GD32_PINMUX_AF('B', 1, AF8) #define LPUART_RTS_PB12 \ GD32_PINMUX_AF('B', 12, AF8) #define LPUART_RTS_PB14 \ GD32_PINMUX_AF('B', 14, AF8) /* LPUART_RX */ #define LPUART_RX_PA13 \ GD32_PINMUX_AF('A', 13, AF2) #define LPUART_RX_PA3 \ GD32_PINMUX_AF('A', 3, AF8) #define LPUART_RX_PB10 \ GD32_PINMUX_AF('B', 10, AF8) #define LPUART_RX_PB11 \ GD32_PINMUX_AF('B', 11, AF7) #define LPUART_RX_PC11 \ GD32_PINMUX_AF('C', 11, AF8) /* LPUART_TX */ #define LPUART_TX_PA14 \ GD32_PINMUX_AF('A', 14, AF2) #define LPUART_TX_PA2 \ GD32_PINMUX_AF('A', 2, AF8) #define LPUART_TX_PB10 \ GD32_PINMUX_AF('B', 10, AF7) #define LPUART_TX_PB11 \ GD32_PINMUX_AF('B', 11, AF8) #define LPUART_TX_PC10 \ GD32_PINMUX_AF('C', 10, AF8) /* RTC_OUT */ #define RTC_OUT_PB14 \ GD32_PINMUX_AF('B', 14, AF0) #define RTC_OUT_PB2 \ GD32_PINMUX_AF('B', 2, AF0) /* SPI0_IO2 */ #define SPI0_IO2_PA13 \ GD32_PINMUX_AF('A', 13, AF5) #define SPI0_IO2_PA2 \ GD32_PINMUX_AF('A', 2, AF5) #define SPI0_IO2_PB6 \ GD32_PINMUX_AF('B', 6, AF5) /* SPI0_IO3 */ #define SPI0_IO3_PA14 \ GD32_PINMUX_AF('A', 14, AF5) #define SPI0_IO3_PA3 \ GD32_PINMUX_AF('A', 3, AF5) #define SPI0_IO3_PB7 \ GD32_PINMUX_AF('B', 7, AF5) /* SPI0_MISO */ #define SPI0_MISO_PA11 \ GD32_PINMUX_AF('A', 11, AF5) #define SPI0_MISO_PA6 \ GD32_PINMUX_AF('A', 6, AF5) #define SPI0_MISO_PB4 \ GD32_PINMUX_AF('B', 4, AF5) /* SPI0_MOSI */ #define SPI0_MOSI_PA12 \ GD32_PINMUX_AF('A', 12, AF5) #define SPI0_MOSI_PA7 \ GD32_PINMUX_AF('A', 7, AF5) #define SPI0_MOSI_PB5 \ GD32_PINMUX_AF('B', 5, AF5) /* SPI0_NSS */ #define SPI0_NSS_PA13 \ GD32_PINMUX_AF('A', 13, AF6) #define SPI0_NSS_PA15 \ GD32_PINMUX_AF('A', 15, AF5) #define SPI0_NSS_PA4 \ GD32_PINMUX_AF('A', 4, AF5) #define SPI0_NSS_PB0 \ GD32_PINMUX_AF('B', 0, AF5) /* SPI0_SCK */ #define SPI0_SCK_PA1 \ GD32_PINMUX_AF('A', 1, AF5) #define SPI0_SCK_PA5 \ GD32_PINMUX_AF('A', 5, AF5) #define SPI0_SCK_PB3 \ GD32_PINMUX_AF('B', 3, AF5) /* SPI1_MISO */ #define SPI1_MISO_PB14 \ GD32_PINMUX_AF('B', 14, AF6) #define SPI1_MISO_PB4 \ GD32_PINMUX_AF('B', 4, AF6) #define SPI1_MISO_PC11 \ GD32_PINMUX_AF('C', 11, AF5) #define SPI1_MISO_PD3 \ GD32_PINMUX_AF('D', 3, AF5) /* SPI1_MOSI */ #define SPI1_MOSI_PB15 \ GD32_PINMUX_AF('B', 15, AF6) #define SPI1_MOSI_PB5 \ GD32_PINMUX_AF('B', 5, AF6) #define SPI1_MOSI_PC12 \ GD32_PINMUX_AF('C', 12, AF5) /* SPI1_NSS */ #define SPI1_NSS_PA14 \ GD32_PINMUX_AF('A', 14, AF6) #define SPI1_NSS_PA15 \ GD32_PINMUX_AF('A', 15, AF6) #define SPI1_NSS_PA4 \ GD32_PINMUX_AF('A', 4, AF6) #define SPI1_NSS_PB12 \ GD32_PINMUX_AF('B', 12, AF6) #define SPI1_NSS_PB9 \ GD32_PINMUX_AF('B', 9, AF5) #define SPI1_NSS_PF0 \ GD32_PINMUX_AF('F', 0, AF5) /* SPI1_SCK */ #define SPI1_SCK_PB10 \ GD32_PINMUX_AF('B', 10, AF5) #define SPI1_SCK_PB13 \ GD32_PINMUX_AF('B', 13, AF6) #define SPI1_SCK_PB3 \ GD32_PINMUX_AF('B', 3, AF6) #define SPI1_SCK_PC10 \ GD32_PINMUX_AF('C', 10, AF5) #define SPI1_SCK_PF1 \ GD32_PINMUX_AF('F', 1, AF5) /* SWCLK */ #define SWCLK_PA14 \ GD32_PINMUX_AF('A', 14, AF0) /* SWDIO */ #define SWDIO_PA13 \ GD32_PINMUX_AF('A', 13, AF0) /* TIMER11_CH0 */ #define TIMER11_CH0_PB14 \ GD32_PINMUX_AF('B', 14, AF2) /* TIMER11_CH1 */ #define TIMER11_CH1_PB15 \ GD32_PINMUX_AF('B', 15, AF2) /* TIMER1_CH0_ETI */ #define TIMER1_CH0_ETI_PA0 \ GD32_PINMUX_AF('A', 0, AF1) #define TIMER1_CH0_ETI_PA15 \ GD32_PINMUX_AF('A', 15, AF1) #define TIMER1_CH0_ETI_PA5 \ GD32_PINMUX_AF('A', 5, AF1) /* TIMER1_CH1 */ #define TIMER1_CH1_PA1 \ GD32_PINMUX_AF('A', 1, AF1) #define TIMER1_CH1_PB3 \ GD32_PINMUX_AF('B', 3, AF1) /* TIMER1_CH2 */ #define TIMER1_CH2_PA2 \ GD32_PINMUX_AF('A', 2, AF1) #define TIMER1_CH2_PB10 \ GD32_PINMUX_AF('B', 10, AF1) /* TIMER1_CH3 */ #define TIMER1_CH3_PA3 \ GD32_PINMUX_AF('A', 3, AF1) #define TIMER1_CH3_PB11 \ GD32_PINMUX_AF('B', 11, AF1) /* TIMER2_CH0 */ #define TIMER2_CH0_PA6 \ GD32_PINMUX_AF('A', 6, AF1) #define TIMER2_CH0_PB4 \ GD32_PINMUX_AF('B', 4, AF1) #define TIMER2_CH0_PC6 \ GD32_PINMUX_AF('C', 6, AF1) /* TIMER2_CH1 */ #define TIMER2_CH1_PA7 \ GD32_PINMUX_AF('A', 7, AF1) #define TIMER2_CH1_PB5 \ GD32_PINMUX_AF('B', 5, AF1) #define TIMER2_CH1_PC7 \ GD32_PINMUX_AF('C', 7, AF1) /* TIMER2_CH2 */ #define TIMER2_CH2_PB0 \ GD32_PINMUX_AF('B', 0, AF1) /* TIMER2_CH3 */ #define TIMER2_CH3_PB1 \ GD32_PINMUX_AF('B', 1, AF1) /* TIMER8_CH0 */ #define TIMER8_CH0_PA2 \ GD32_PINMUX_AF('A', 2, AF2) /* TIMER8_CH1 */ #define TIMER8_CH1_PA3 \ GD32_PINMUX_AF('A', 3, AF2) /* UART3_RX */ #define UART3_RX_PA1 \ GD32_PINMUX_AF('A', 1, AF8) #define UART3_RX_PC11 \ GD32_PINMUX_AF('C', 11, AF7) /* UART3_TX */ #define UART3_TX_PA0 \ GD32_PINMUX_AF('A', 0, AF8) #define UART3_TX_PC10 \ GD32_PINMUX_AF('C', 10, AF7) /* UART4_RX */ #define UART4_RX_PB4 \ GD32_PINMUX_AF('B', 4, AF8) /* UART4_TX */ #define UART4_TX_PB3 \ GD32_PINMUX_AF('B', 3, AF8) #define UART4_TX_PC12 \ GD32_PINMUX_AF('C', 12, AF7) /* USART0_CK */ #define USART0_CK_PA8 \ GD32_PINMUX_AF('A', 8, AF7) #define USART0_CK_PB5 \ GD32_PINMUX_AF('B', 5, AF7) /* USART0_CTS */ #define USART0_CTS_PA11 \ GD32_PINMUX_AF('A', 11, AF7) #define USART0_CTS_PB4 \ GD32_PINMUX_AF('B', 4, AF7) /* USART0_DE */ #define USART0_DE_PA12 \ GD32_PINMUX_AF('A', 12, AF7) #define USART0_DE_PB3 \ GD32_PINMUX_AF('B', 3, AF7) /* USART0_RTS */ #define USART0_RTS_PA12 \ GD32_PINMUX_AF('A', 12, AF7) #define USART0_RTS_PB3 \ GD32_PINMUX_AF('B', 3, AF7) /* USART0_RX */ #define USART0_RX_PA10 \ GD32_PINMUX_AF('A', 10, AF7) #define USART0_RX_PA14 \ GD32_PINMUX_AF('A', 14, AF7) #define USART0_RX_PB7 \ GD32_PINMUX_AF('B', 7, AF7) /* USART0_TX */ #define USART0_TX_PA13 \ GD32_PINMUX_AF('A', 13, AF7) #define USART0_TX_PA9 \ GD32_PINMUX_AF('A', 9, AF7) #define USART0_TX_PB6 \ GD32_PINMUX_AF('B', 6, AF7) /* USART1_CK */ #define USART1_CK_PA4 \ GD32_PINMUX_AF('A', 4, AF7) /* USART1_CTS */ #define USART1_CTS_PA0 \ GD32_PINMUX_AF('A', 0, AF7) #define USART1_CTS_PD3 \ GD32_PINMUX_AF('D', 3, AF7) /* USART1_DE */ #define USART1_DE_PA1 \ GD32_PINMUX_AF('A', 1, AF7) /* USART1_RTS */ #define USART1_RTS_PA1 \ GD32_PINMUX_AF('A', 1, AF7) /* USART1_RX */ #define USART1_RX_PA15 \ GD32_PINMUX_AF('A', 15, AF7) #define USART1_RX_PA3 \ GD32_PINMUX_AF('A', 3, AF7) /* USART1_TX */ #define USART1_TX_PA14 \ GD32_PINMUX_AF('A', 14, AF8) #define USART1_TX_PA2 \ GD32_PINMUX_AF('A', 2, AF7)