/* * Autogenerated file * * SPDX-License-Identifier: Apache 2.0 */ #include "gd32-af.h" /* ADC012_IN0 */ #define ADC012_IN0_PA0 \ GD32_PINMUX_AF('A', 0, ANALOG) /* ADC012_IN1 */ #define ADC012_IN1_PA1 \ GD32_PINMUX_AF('A', 1, ANALOG) /* ADC012_IN10 */ #define ADC012_IN10_PC0 \ GD32_PINMUX_AF('C', 0, ANALOG) /* ADC012_IN11 */ #define ADC012_IN11_PC1 \ GD32_PINMUX_AF('C', 1, ANALOG) /* ADC012_IN12 */ #define ADC012_IN12_PC2 \ GD32_PINMUX_AF('C', 2, ANALOG) /* ADC012_IN13 */ #define ADC012_IN13_PC3 \ GD32_PINMUX_AF('C', 3, ANALOG) /* ADC012_IN2 */ #define ADC012_IN2_PA2 \ GD32_PINMUX_AF('A', 2, ANALOG) /* ADC012_IN3 */ #define ADC012_IN3_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) /* ADC01_IN14 */ #define ADC01_IN14_PC4 \ GD32_PINMUX_AF('C', 4, ANALOG) /* ADC01_IN15 */ #define ADC01_IN15_PC5 \ GD32_PINMUX_AF('C', 5, ANALOG) /* ADC01_IN4 */ #define ADC01_IN4_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) /* ADC01_IN5 */ #define ADC01_IN5_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) /* ADC01_IN6 */ #define ADC01_IN6_PA6 \ GD32_PINMUX_AF('A', 6, ANALOG) /* ADC01_IN7 */ #define ADC01_IN7_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) /* ADC01_IN8 */ #define ADC01_IN8_PB0 \ GD32_PINMUX_AF('B', 0, ANALOG) /* ADC01_IN9 */ #define ADC01_IN9_PB1 \ GD32_PINMUX_AF('B', 1, ANALOG) /* ANALOG */ #define ANALOG_PA0 \ GD32_PINMUX_AF('A', 0, ANALOG) #define ANALOG_PA1 \ GD32_PINMUX_AF('A', 1, ANALOG) #define ANALOG_PA2 \ GD32_PINMUX_AF('A', 2, ANALOG) #define ANALOG_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) #define ANALOG_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) #define ANALOG_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) #define ANALOG_PA6 \ GD32_PINMUX_AF('A', 6, ANALOG) #define ANALOG_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) #define ANALOG_PA8 \ GD32_PINMUX_AF('A', 8, ANALOG) #define ANALOG_PA9 \ GD32_PINMUX_AF('A', 9, ANALOG) #define ANALOG_PA10 \ GD32_PINMUX_AF('A', 10, ANALOG) #define ANALOG_PA11 \ GD32_PINMUX_AF('A', 11, ANALOG) #define ANALOG_PA12 \ GD32_PINMUX_AF('A', 12, ANALOG) #define ANALOG_PA13 \ GD32_PINMUX_AF('A', 13, ANALOG) #define ANALOG_PA14 \ GD32_PINMUX_AF('A', 14, ANALOG) #define ANALOG_PA15 \ GD32_PINMUX_AF('A', 15, ANALOG) #define ANALOG_PB0 \ GD32_PINMUX_AF('B', 0, ANALOG) #define ANALOG_PB1 \ GD32_PINMUX_AF('B', 1, ANALOG) #define ANALOG_PB2 \ GD32_PINMUX_AF('B', 2, ANALOG) #define ANALOG_PB3 \ GD32_PINMUX_AF('B', 3, ANALOG) #define ANALOG_PB4 \ GD32_PINMUX_AF('B', 4, ANALOG) #define ANALOG_PB5 \ GD32_PINMUX_AF('B', 5, ANALOG) #define ANALOG_PB6 \ GD32_PINMUX_AF('B', 6, ANALOG) #define ANALOG_PB7 \ GD32_PINMUX_AF('B', 7, ANALOG) #define ANALOG_PB8 \ GD32_PINMUX_AF('B', 8, ANALOG) #define ANALOG_PB9 \ GD32_PINMUX_AF('B', 9, ANALOG) #define ANALOG_PB10 \ GD32_PINMUX_AF('B', 10, ANALOG) #define ANALOG_PB11 \ GD32_PINMUX_AF('B', 11, ANALOG) #define ANALOG_PB12 \ GD32_PINMUX_AF('B', 12, ANALOG) #define ANALOG_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) #define ANALOG_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) #define ANALOG_PB15 \ GD32_PINMUX_AF('B', 15, ANALOG) #define ANALOG_PC0 \ GD32_PINMUX_AF('C', 0, ANALOG) #define ANALOG_PC1 \ GD32_PINMUX_AF('C', 1, ANALOG) #define ANALOG_PC2 \ GD32_PINMUX_AF('C', 2, ANALOG) #define ANALOG_PC3 \ GD32_PINMUX_AF('C', 3, ANALOG) #define ANALOG_PC4 \ GD32_PINMUX_AF('C', 4, ANALOG) #define ANALOG_PC5 \ GD32_PINMUX_AF('C', 5, ANALOG) #define ANALOG_PC6 \ GD32_PINMUX_AF('C', 6, ANALOG) #define ANALOG_PC7 \ GD32_PINMUX_AF('C', 7, ANALOG) #define ANALOG_PC8 \ GD32_PINMUX_AF('C', 8, ANALOG) #define ANALOG_PC9 \ GD32_PINMUX_AF('C', 9, ANALOG) #define ANALOG_PC10 \ GD32_PINMUX_AF('C', 10, ANALOG) #define ANALOG_PC11 \ GD32_PINMUX_AF('C', 11, ANALOG) #define ANALOG_PC12 \ GD32_PINMUX_AF('C', 12, ANALOG) #define ANALOG_PC13 \ GD32_PINMUX_AF('C', 13, ANALOG) #define ANALOG_PC14 \ GD32_PINMUX_AF('C', 14, ANALOG) #define ANALOG_PC15 \ GD32_PINMUX_AF('C', 15, ANALOG) #define ANALOG_PD2 \ GD32_PINMUX_AF('D', 2, ANALOG) /* CAN0_RX */ #define CAN0_RX_PA11 \ GD32_PINMUX_AF('A', 11, AF9) #define CAN0_RX_PB8 \ GD32_PINMUX_AF('B', 8, AF9) /* CAN0_TX */ #define CAN0_TX_PA12 \ GD32_PINMUX_AF('A', 12, AF9) #define CAN0_TX_PB9 \ GD32_PINMUX_AF('B', 9, AF9) /* CAN1_RX */ #define CAN1_RX_PB5 \ GD32_PINMUX_AF('B', 5, AF9) #define CAN1_RX_PB12 \ GD32_PINMUX_AF('B', 12, AF9) /* CAN1_TX */ #define CAN1_TX_PB6 \ GD32_PINMUX_AF('B', 6, AF9) #define CAN1_TX_PB13 \ GD32_PINMUX_AF('B', 13, AF9) /* CK_OUT0 */ #define CK_OUT0_PA8 \ GD32_PINMUX_AF('A', 8, AF0) /* CK_OUT1 */ #define CK_OUT1_PC9 \ GD32_PINMUX_AF('C', 9, AF0) /* CTC_SYNC */ #define CTC_SYNC_PA8 \ GD32_PINMUX_AF('A', 8, AF9) /* DAC_OUT0 */ #define DAC_OUT0_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) /* DAC_OUT1 */ #define DAC_OUT1_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) /* DCI_D0 */ #define DCI_D0_PA9 \ GD32_PINMUX_AF('A', 9, AF13) #define DCI_D0_PC6 \ GD32_PINMUX_AF('C', 6, AF13) /* DCI_D1 */ #define DCI_D1_PA10 \ GD32_PINMUX_AF('A', 10, AF13) #define DCI_D1_PC7 \ GD32_PINMUX_AF('C', 7, AF13) /* DCI_D10 */ #define DCI_D10_PB5 \ GD32_PINMUX_AF('B', 5, AF13) /* DCI_D11 */ #define DCI_D11_PD2 \ GD32_PINMUX_AF('D', 2, AF13) /* DCI_D2 */ #define DCI_D2_PC8 \ GD32_PINMUX_AF('C', 8, AF13) /* DCI_D3 */ #define DCI_D3_PC9 \ GD32_PINMUX_AF('C', 9, AF13) /* DCI_D4 */ #define DCI_D4_PC11 \ GD32_PINMUX_AF('C', 11, AF13) /* DCI_D5 */ #define DCI_D5_PB6 \ GD32_PINMUX_AF('B', 6, AF13) /* DCI_D6 */ #define DCI_D6_PB8 \ GD32_PINMUX_AF('B', 8, AF13) /* DCI_D7 */ #define DCI_D7_PB9 \ GD32_PINMUX_AF('B', 9, AF13) /* DCI_D8 */ #define DCI_D8_PC10 \ GD32_PINMUX_AF('C', 10, AF13) /* DCI_D9 */ #define DCI_D9_PC12 \ GD32_PINMUX_AF('C', 12, AF13) /* DCI_HSYNC */ #define DCI_HSYNC_PA4 \ GD32_PINMUX_AF('A', 4, AF13) /* DCI_PIXCLK */ #define DCI_PIXCLK_PA6 \ GD32_PINMUX_AF('A', 6, AF13) /* DCI_VSYNC */ #define DCI_VSYNC_PB7 \ GD32_PINMUX_AF('B', 7, AF13) /* ENET_MDC */ #define ENET_MDC_PC1 \ GD32_PINMUX_AF('C', 1, AF11) /* ENET_MDIO */ #define ENET_MDIO_PA2 \ GD32_PINMUX_AF('A', 2, AF11) /* ENET_MII_COL */ #define ENET_MII_COL_PA3 \ GD32_PINMUX_AF('A', 3, AF11) /* ENET_MII_CRS */ #define ENET_MII_CRS_PA0 \ GD32_PINMUX_AF('A', 0, AF11) /* ENET_MII_RXD0 */ #define ENET_MII_RXD0_PC4 \ GD32_PINMUX_AF('C', 4, AF11) /* ENET_MII_RXD1 */ #define ENET_MII_RXD1_PC5 \ GD32_PINMUX_AF('C', 5, AF11) /* ENET_MII_RXD2 */ #define ENET_MII_RXD2_PB0 \ GD32_PINMUX_AF('B', 0, AF11) /* ENET_MII_RXD3 */ #define ENET_MII_RXD3_PB1 \ GD32_PINMUX_AF('B', 1, AF11) /* ENET_MII_RX_CLK */ #define ENET_MII_RX_CLK_PA1 \ GD32_PINMUX_AF('A', 1, AF11) /* ENET_MII_RX_DV */ #define ENET_MII_RX_DV_PA7 \ GD32_PINMUX_AF('A', 7, AF11) /* ENET_MII_RX_ER */ #define ENET_MII_RX_ER_PB9 \ GD32_PINMUX_AF('B', 9, AF1) /* ENET_MII_TXD0 */ #define ENET_MII_TXD0_PB11 \ GD32_PINMUX_AF('B', 11, AF11) /* ENET_MII_TXD1 */ #define ENET_MII_TXD1_PB12 \ GD32_PINMUX_AF('B', 12, AF11) /* ENET_MII_TXD2 */ #define ENET_MII_TXD2_PC2 \ GD32_PINMUX_AF('C', 2, AF11) /* ENET_MII_TXD3 */ #define ENET_MII_TXD3_PB8 \ GD32_PINMUX_AF('B', 8, AF11) /* ENET_MII_TX_CLK */ #define ENET_MII_TX_CLK_PC3 \ GD32_PINMUX_AF('C', 3, AF11) /* ENET_MII_TX_EN */ #define ENET_MII_TX_EN_PB10 \ GD32_PINMUX_AF('B', 10, AF11) /* ENET_PPS_OUT */ #define ENET_PPS_OUT_PB5 \ GD32_PINMUX_AF('B', 5, AF11) /* ENET_RMII_CRS_DV */ #define ENET_RMII_CRS_DV_PA7 \ GD32_PINMUX_AF('A', 7, AF11) /* ENET_RMII_REF_CLK */ #define ENET_RMII_REF_CLK_PA1 \ GD32_PINMUX_AF('A', 1, AF11) /* ENET_RMII_RXD0 */ #define ENET_RMII_RXD0_PC4 \ GD32_PINMUX_AF('C', 4, AF11) /* ENET_RMII_RXD1 */ #define ENET_RMII_RXD1_PC5 \ GD32_PINMUX_AF('C', 5, AF11) /* ENET_RMII_TXD0 */ #define ENET_RMII_TXD0_PB11 \ GD32_PINMUX_AF('B', 11, AF11) /* ENET_RMII_TXD1 */ #define ENET_RMII_TXD1_PB12 \ GD32_PINMUX_AF('B', 12, AF11) /* ENET_RMII_TX_EN */ #define ENET_RMII_TX_EN_PB10 \ GD32_PINMUX_AF('B', 10, AF11) /* EVENTOUT */ #define EVENTOUT_PA0 \ GD32_PINMUX_AF('A', 0, AF15) #define EVENTOUT_PA1 \ GD32_PINMUX_AF('A', 1, AF15) #define EVENTOUT_PA2 \ GD32_PINMUX_AF('A', 2, AF15) #define EVENTOUT_PA3 \ GD32_PINMUX_AF('A', 3, AF15) #define EVENTOUT_PA4 \ GD32_PINMUX_AF('A', 4, AF15) #define EVENTOUT_PA5 \ GD32_PINMUX_AF('A', 5, AF15) #define EVENTOUT_PA6 \ GD32_PINMUX_AF('A', 6, AF15) #define EVENTOUT_PA7 \ GD32_PINMUX_AF('A', 7, AF15) #define EVENTOUT_PA8 \ GD32_PINMUX_AF('A', 8, AF15) #define EVENTOUT_PA9 \ GD32_PINMUX_AF('A', 9, AF15) #define EVENTOUT_PA10 \ GD32_PINMUX_AF('A', 10, AF15) #define EVENTOUT_PA11 \ GD32_PINMUX_AF('A', 11, AF15) #define EVENTOUT_PA12 \ GD32_PINMUX_AF('A', 12, AF15) #define EVENTOUT_PA13 \ GD32_PINMUX_AF('A', 13, AF15) #define EVENTOUT_PA14 \ GD32_PINMUX_AF('A', 14, AF15) #define EVENTOUT_PA15 \ GD32_PINMUX_AF('A', 15, AF15) #define EVENTOUT_PB0 \ GD32_PINMUX_AF('B', 0, AF15) #define EVENTOUT_PB1 \ GD32_PINMUX_AF('B', 1, AF15) #define EVENTOUT_PB2 \ GD32_PINMUX_AF('B', 2, AF15) #define EVENTOUT_PB3 \ GD32_PINMUX_AF('B', 3, AF15) #define EVENTOUT_PB4 \ GD32_PINMUX_AF('B', 4, AF15) #define EVENTOUT_PB5 \ GD32_PINMUX_AF('B', 5, AF15) #define EVENTOUT_PB6 \ GD32_PINMUX_AF('B', 6, AF15) #define EVENTOUT_PB7 \ GD32_PINMUX_AF('B', 7, AF15) #define EVENTOUT_PB8 \ GD32_PINMUX_AF('B', 8, AF15) #define EVENTOUT_PB9 \ GD32_PINMUX_AF('B', 9, AF15) #define EVENTOUT_PB10 \ GD32_PINMUX_AF('B', 10, AF15) #define EVENTOUT_PB11 \ GD32_PINMUX_AF('B', 11, AF15) #define EVENTOUT_PB12 \ GD32_PINMUX_AF('B', 12, AF15) #define EVENTOUT_PB13 \ GD32_PINMUX_AF('B', 13, AF15) #define EVENTOUT_PB14 \ GD32_PINMUX_AF('B', 14, AF15) #define EVENTOUT_PB15 \ GD32_PINMUX_AF('B', 15, AF15) #define EVENTOUT_PC0 \ GD32_PINMUX_AF('C', 0, AF15) #define EVENTOUT_PC1 \ GD32_PINMUX_AF('C', 1, AF15) #define EVENTOUT_PC2 \ GD32_PINMUX_AF('C', 2, AF15) #define EVENTOUT_PC3 \ GD32_PINMUX_AF('C', 3, AF15) #define EVENTOUT_PC4 \ GD32_PINMUX_AF('C', 4, AF15) #define EVENTOUT_PC5 \ GD32_PINMUX_AF('C', 5, AF15) #define EVENTOUT_PC6 \ GD32_PINMUX_AF('C', 6, AF15) #define EVENTOUT_PC7 \ GD32_PINMUX_AF('C', 7, AF15) #define EVENTOUT_PC8 \ GD32_PINMUX_AF('C', 8, AF15) #define EVENTOUT_PC9 \ GD32_PINMUX_AF('C', 9, AF15) #define EVENTOUT_PC10 \ GD32_PINMUX_AF('C', 10, AF15) #define EVENTOUT_PC11 \ GD32_PINMUX_AF('C', 11, AF15) #define EVENTOUT_PC12 \ GD32_PINMUX_AF('C', 12, AF15) #define EVENTOUT_PC13 \ GD32_PINMUX_AF('C', 13, AF15) #define EVENTOUT_PC14 \ GD32_PINMUX_AF('C', 14, AF15) #define EVENTOUT_PC15 \ GD32_PINMUX_AF('C', 15, AF15) #define EVENTOUT_PD2 \ GD32_PINMUX_AF('D', 2, AF15) /* EXMC_NADV */ #define EXMC_NADV_PB7 \ GD32_PINMUX_AF('B', 7, AF12) /* EXMC_NL */ #define EXMC_NL_PB7 \ GD32_PINMUX_AF('B', 7, AF12) /* EXMC_SDCKE0 */ #define EXMC_SDCKE0_PC3 \ GD32_PINMUX_AF('C', 3, AF12) #define EXMC_SDCKE0_PC5 \ GD32_PINMUX_AF('C', 5, AF12) /* EXMC_SDCKE1 */ #define EXMC_SDCKE1_PB5 \ GD32_PINMUX_AF('B', 5, AF12) /* EXMC_SDNE0 */ #define EXMC_SDNE0_PC2 \ GD32_PINMUX_AF('C', 2, AF12) #define EXMC_SDNE0_PC4 \ GD32_PINMUX_AF('C', 4, AF12) /* EXMC_SDNE1 */ #define EXMC_SDNE1_PB6 \ GD32_PINMUX_AF('B', 6, AF11) /* EXMC_SDNWE */ #define EXMC_SDNWE_PC0 \ GD32_PINMUX_AF('C', 0, AF12) /* EXMC_SD_NWE */ #define EXMC_SD_NWE_PA7 \ GD32_PINMUX_AF('A', 7, AF12) /* I2C0_SCL */ #define I2C0_SCL_PB6 \ GD32_PINMUX_AF('B', 6, AF4) #define I2C0_SCL_PB8 \ GD32_PINMUX_AF('B', 8, AF4) /* I2C0_SDA */ #define I2C0_SDA_PB7 \ GD32_PINMUX_AF('B', 7, AF4) #define I2C0_SDA_PB9 \ GD32_PINMUX_AF('B', 9, AF4) /* I2C0_SMBA */ #define I2C0_SMBA_PB5 \ GD32_PINMUX_AF('B', 5, AF4) /* I2C0_TXFRAME */ #define I2C0_TXFRAME_PB4 \ GD32_PINMUX_AF('B', 4, AF4) /* I2C1_SCL */ #define I2C1_SCL_PB10 \ GD32_PINMUX_AF('B', 10, AF4) /* I2C1_SDA */ #define I2C1_SDA_PB3 \ GD32_PINMUX_AF('B', 3, AF9) #define I2C1_SDA_PB11 \ GD32_PINMUX_AF('B', 11, AF4) #define I2C1_SDA_PC12 \ GD32_PINMUX_AF('C', 12, AF4) /* I2C1_SMBA */ #define I2C1_SMBA_PB12 \ GD32_PINMUX_AF('B', 12, AF4) /* I2C1_TXFRAME */ #define I2C1_TXFRAME_PB13 \ GD32_PINMUX_AF('B', 13, AF4) /* I2C2_SCL */ #define I2C2_SCL_PA8 \ GD32_PINMUX_AF('A', 8, AF4) /* I2C2_SDA */ #define I2C2_SDA_PB4 \ GD32_PINMUX_AF('B', 4, AF9) #define I2C2_SDA_PC9 \ GD32_PINMUX_AF('C', 9, AF4) /* I2C2_SMBA */ #define I2C2_SMBA_PA9 \ GD32_PINMUX_AF('A', 9, AF4) /* I2C2_TXFRAME */ #define I2C2_TXFRAME_PA10 \ GD32_PINMUX_AF('A', 10, AF4) /* I2S1_ADD_SD */ #define I2S1_ADD_SD_PB14 \ GD32_PINMUX_AF('B', 14, AF6) #define I2S1_ADD_SD_PC2 \ GD32_PINMUX_AF('C', 2, AF6) /* I2S1_CK */ #define I2S1_CK_PA9 \ GD32_PINMUX_AF('A', 9, AF5) #define I2S1_CK_PB10 \ GD32_PINMUX_AF('B', 10, AF5) #define I2S1_CK_PB13 \ GD32_PINMUX_AF('B', 13, AF5) #define I2S1_CK_PC7 \ GD32_PINMUX_AF('C', 7, AF5) /* I2S1_MCK */ #define I2S1_MCK_PA3 \ GD32_PINMUX_AF('A', 3, AF5) #define I2S1_MCK_PA6 \ GD32_PINMUX_AF('A', 6, AF6) #define I2S1_MCK_PC6 \ GD32_PINMUX_AF('C', 6, AF5) /* I2S1_SD */ #define I2S1_SD_PB15 \ GD32_PINMUX_AF('B', 15, AF5) #define I2S1_SD_PC1 \ GD32_PINMUX_AF('C', 1, AF7) #define I2S1_SD_PC3 \ GD32_PINMUX_AF('C', 3, AF5) /* I2S1_WS */ #define I2S1_WS_PB9 \ GD32_PINMUX_AF('B', 9, AF5) #define I2S1_WS_PB12 \ GD32_PINMUX_AF('B', 12, AF5) /* I2S2_ADD_SD */ #define I2S2_ADD_SD_PB4 \ GD32_PINMUX_AF('B', 4, AF7) #define I2S2_ADD_SD_PC11 \ GD32_PINMUX_AF('C', 11, AF5) /* I2S2_CK */ #define I2S2_CK_PB3 \ GD32_PINMUX_AF('B', 3, AF6) #define I2S2_CK_PC10 \ GD32_PINMUX_AF('C', 10, AF6) /* I2S2_MCK */ #define I2S2_MCK_PB10 \ GD32_PINMUX_AF('B', 10, AF6) #define I2S2_MCK_PC7 \ GD32_PINMUX_AF('C', 7, AF6) /* I2S2_SD */ #define I2S2_SD_PB0 \ GD32_PINMUX_AF('B', 0, AF7) #define I2S2_SD_PB2 \ GD32_PINMUX_AF('B', 2, AF7) #define I2S2_SD_PB5 \ GD32_PINMUX_AF('B', 5, AF6) #define I2S2_SD_PC1 \ GD32_PINMUX_AF('C', 1, AF5) #define I2S2_SD_PC12 \ GD32_PINMUX_AF('C', 12, AF6) /* I2S2_WS */ #define I2S2_WS_PA4 \ GD32_PINMUX_AF('A', 4, AF6) #define I2S2_WS_PA15 \ GD32_PINMUX_AF('A', 15, AF6) /* I2S_CKIN */ #define I2S_CKIN_PA2 \ GD32_PINMUX_AF('A', 2, AF5) #define I2S_CKIN_PB11 \ GD32_PINMUX_AF('B', 11, AF5) #define I2S_CKIN_PC9 \ GD32_PINMUX_AF('C', 9, AF5) /* JTCK */ #define JTCK_PA14 \ GD32_PINMUX_AF('A', 14, AF0) /* JTDI */ #define JTDI_PA15 \ GD32_PINMUX_AF('A', 15, AF0) /* JTDO */ #define JTDO_PB3 \ GD32_PINMUX_AF('B', 3, AF0) /* JTMS */ #define JTMS_PA13 \ GD32_PINMUX_AF('A', 13, AF0) /* NJTRST */ #define NJTRST_PB4 \ GD32_PINMUX_AF('B', 4, AF0) /* RTC_REFIN */ #define RTC_REFIN_PB15 \ GD32_PINMUX_AF('B', 15, AF0) /* SDIO_CK */ #define SDIO_CK_PB2 \ GD32_PINMUX_AF('B', 2, AF12) #define SDIO_CK_PC12 \ GD32_PINMUX_AF('C', 12, AF12) /* SDIO_CMD */ #define SDIO_CMD_PA6 \ GD32_PINMUX_AF('A', 6, AF12) #define SDIO_CMD_PD2 \ GD32_PINMUX_AF('D', 2, AF12) /* SDIO_D0 */ #define SDIO_D0_PB4 \ GD32_PINMUX_AF('B', 4, AF12) #define SDIO_D0_PC8 \ GD32_PINMUX_AF('C', 8, AF12) /* SDIO_D1 */ #define SDIO_D1_PA8 \ GD32_PINMUX_AF('A', 8, AF12) #define SDIO_D1_PB0 \ GD32_PINMUX_AF('B', 0, AF12) #define SDIO_D1_PC9 \ GD32_PINMUX_AF('C', 9, AF12) /* SDIO_D2 */ #define SDIO_D2_PA9 \ GD32_PINMUX_AF('A', 9, AF12) #define SDIO_D2_PB1 \ GD32_PINMUX_AF('B', 1, AF12) #define SDIO_D2_PC10 \ GD32_PINMUX_AF('C', 10, AF12) /* SDIO_D3 */ #define SDIO_D3_PC11 \ GD32_PINMUX_AF('C', 11, AF12) /* SDIO_D4 */ #define SDIO_D4_PB8 \ GD32_PINMUX_AF('B', 8, AF12) /* SDIO_D5 */ #define SDIO_D5_PB9 \ GD32_PINMUX_AF('B', 9, AF12) /* SDIO_D6 */ #define SDIO_D6_PC6 \ GD32_PINMUX_AF('C', 6, AF12) /* SDIO_D7 */ #define SDIO_D7_PB10 \ GD32_PINMUX_AF('B', 10, AF12) #define SDIO_D7_PC7 \ GD32_PINMUX_AF('C', 7, AF12) /* SPI0_MISO */ #define SPI0_MISO_PA6 \ GD32_PINMUX_AF('A', 6, AF5) #define SPI0_MISO_PB4 \ GD32_PINMUX_AF('B', 4, AF5) /* SPI0_MOSI */ #define SPI0_MOSI_PA7 \ GD32_PINMUX_AF('A', 7, AF5) #define SPI0_MOSI_PB5 \ GD32_PINMUX_AF('B', 5, AF5) /* SPI0_NSS */ #define SPI0_NSS_PA4 \ GD32_PINMUX_AF('A', 4, AF5) #define SPI0_NSS_PA15 \ GD32_PINMUX_AF('A', 15, AF5) /* SPI0_SCK */ #define SPI0_SCK_PA5 \ GD32_PINMUX_AF('A', 5, AF5) #define SPI0_SCK_PB3 \ GD32_PINMUX_AF('B', 3, AF5) /* SPI1_MISO */ #define SPI1_MISO_PB14 \ GD32_PINMUX_AF('B', 14, AF5) #define SPI1_MISO_PC2 \ GD32_PINMUX_AF('C', 2, AF5) /* SPI1_MOSI */ #define SPI1_MOSI_PB15 \ GD32_PINMUX_AF('B', 15, AF5) #define SPI1_MOSI_PC1 \ GD32_PINMUX_AF('C', 1, AF7) #define SPI1_MOSI_PC3 \ GD32_PINMUX_AF('C', 3, AF5) /* SPI1_NSS */ #define SPI1_NSS_PB9 \ GD32_PINMUX_AF('B', 9, AF5) #define SPI1_NSS_PB12 \ GD32_PINMUX_AF('B', 12, AF5) /* SPI1_SCK */ #define SPI1_SCK_PA9 \ GD32_PINMUX_AF('A', 9, AF5) #define SPI1_SCK_PB10 \ GD32_PINMUX_AF('B', 10, AF5) #define SPI1_SCK_PB13 \ GD32_PINMUX_AF('B', 13, AF5) #define SPI1_SCK_PC7 \ GD32_PINMUX_AF('C', 7, AF5) /* SPI2_MISO */ #define SPI2_MISO_PB4 \ GD32_PINMUX_AF('B', 4, AF6) #define SPI2_MISO_PC11 \ GD32_PINMUX_AF('C', 11, AF6) /* SPI2_MOSI */ #define SPI2_MOSI_PB0 \ GD32_PINMUX_AF('B', 0, AF7) #define SPI2_MOSI_PB2 \ GD32_PINMUX_AF('B', 2, AF7) #define SPI2_MOSI_PB5 \ GD32_PINMUX_AF('B', 5, AF6) #define SPI2_MOSI_PC1 \ GD32_PINMUX_AF('C', 1, AF5) #define SPI2_MOSI_PC12 \ GD32_PINMUX_AF('C', 12, AF6) /* SPI2_NSS */ #define SPI2_NSS_PA4 \ GD32_PINMUX_AF('A', 4, AF6) #define SPI2_NSS_PA15 \ GD32_PINMUX_AF('A', 15, AF6) /* SPI2_SCK */ #define SPI2_SCK_PB3 \ GD32_PINMUX_AF('B', 3, AF6) #define SPI2_SCK_PC10 \ GD32_PINMUX_AF('C', 10, AF6) /* SWCLK */ #define SWCLK_PA14 \ GD32_PINMUX_AF('A', 14, AF0) /* SWDIO */ #define SWDIO_PA13 \ GD32_PINMUX_AF('A', 13, AF0) /* TIMER0_BRKIN */ #define TIMER0_BRKIN_PA6 \ GD32_PINMUX_AF('A', 6, AF1) #define TIMER0_BRKIN_PB12 \ GD32_PINMUX_AF('B', 12, AF1) /* TIMER0_CH0 */ #define TIMER0_CH0_PA8 \ GD32_PINMUX_AF('A', 8, AF1) /* TIMER0_CH0_ON */ #define TIMER0_CH0_ON_PA7 \ GD32_PINMUX_AF('A', 7, AF1) #define TIMER0_CH0_ON_PB13 \ GD32_PINMUX_AF('B', 13, AF1) /* TIMER0_CH1 */ #define TIMER0_CH1_PA9 \ GD32_PINMUX_AF('A', 9, AF1) /* TIMER0_CH1_ON */ #define TIMER0_CH1_ON_PB0 \ GD32_PINMUX_AF('B', 0, AF1) #define TIMER0_CH1_ON_PB14 \ GD32_PINMUX_AF('B', 14, AF1) /* TIMER0_CH2 */ #define TIMER0_CH2_PA10 \ GD32_PINMUX_AF('A', 10, AF1) /* TIMER0_CH2_ON */ #define TIMER0_CH2_ON_PB1 \ GD32_PINMUX_AF('B', 1, AF1) #define TIMER0_CH2_ON_PB15 \ GD32_PINMUX_AF('B', 15, AF1) /* TIMER0_CH3 */ #define TIMER0_CH3_PA11 \ GD32_PINMUX_AF('A', 11, AF1) /* TIMER0_ETI */ #define TIMER0_ETI_PA12 \ GD32_PINMUX_AF('A', 12, AF1) /* TIMER10_CH0 */ #define TIMER10_CH0_PB9 \ GD32_PINMUX_AF('B', 9, AF3) /* TIMER11_CH0 */ #define TIMER11_CH0_PB14 \ GD32_PINMUX_AF('B', 14, AF9) /* TIMER11_CH1 */ #define TIMER11_CH1_PB15 \ GD32_PINMUX_AF('B', 15, AF9) /* TIMER12_CH0 */ #define TIMER12_CH0_PA6 \ GD32_PINMUX_AF('A', 6, AF9) /* TIMER13_CH0 */ #define TIMER13_CH0_PA7 \ GD32_PINMUX_AF('A', 7, AF9) /* TIMER1_CH0 */ #define TIMER1_CH0_PA0 \ GD32_PINMUX_AF('A', 0, AF1) #define TIMER1_CH0_PA5 \ GD32_PINMUX_AF('A', 5, AF1) #define TIMER1_CH0_PA15 \ GD32_PINMUX_AF('A', 15, AF1) #define TIMER1_CH0_PB8 \ GD32_PINMUX_AF('B', 8, AF1) /* TIMER1_CH1 */ #define TIMER1_CH1_PA1 \ GD32_PINMUX_AF('A', 1, AF1) #define TIMER1_CH1_PB3 \ GD32_PINMUX_AF('B', 3, AF1) #define TIMER1_CH1_PB9 \ GD32_PINMUX_AF('B', 9, AF1) /* TIMER1_CH2 */ #define TIMER1_CH2_PA2 \ GD32_PINMUX_AF('A', 2, AF1) #define TIMER1_CH2_PB10 \ GD32_PINMUX_AF('B', 10, AF1) /* TIMER1_CH3 */ #define TIMER1_CH3_PA3 \ GD32_PINMUX_AF('A', 3, AF1) #define TIMER1_CH3_PB2 \ GD32_PINMUX_AF('B', 2, AF1) #define TIMER1_CH3_PB11 \ GD32_PINMUX_AF('B', 11, AF1) /* TIMER1_ETI */ #define TIMER1_ETI_PA0 \ GD32_PINMUX_AF('A', 0, AF1) #define TIMER1_ETI_PA5 \ GD32_PINMUX_AF('A', 5, AF1) #define TIMER1_ETI_PA15 \ GD32_PINMUX_AF('A', 15, AF1) #define TIMER1_ETI_PB8 \ GD32_PINMUX_AF('B', 8, AF1) /* TIMER2_CH0 */ #define TIMER2_CH0_PA6 \ GD32_PINMUX_AF('A', 6, AF2) #define TIMER2_CH0_PB4 \ GD32_PINMUX_AF('B', 4, AF2) #define TIMER2_CH0_PC6 \ GD32_PINMUX_AF('C', 6, AF2) /* TIMER2_CH1 */ #define TIMER2_CH1_PA7 \ GD32_PINMUX_AF('A', 7, AF2) #define TIMER2_CH1_PB5 \ GD32_PINMUX_AF('B', 5, AF2) #define TIMER2_CH1_PC7 \ GD32_PINMUX_AF('C', 7, AF2) /* TIMER2_CH2 */ #define TIMER2_CH2_PB0 \ GD32_PINMUX_AF('B', 0, AF2) #define TIMER2_CH2_PC8 \ GD32_PINMUX_AF('C', 8, AF2) /* TIMER2_CH3 */ #define TIMER2_CH3_PB1 \ GD32_PINMUX_AF('B', 1, AF2) #define TIMER2_CH3_PC9 \ GD32_PINMUX_AF('C', 9, AF2) /* TIMER2_ETI */ #define TIMER2_ETI_PD2 \ GD32_PINMUX_AF('D', 2, AF2) /* TIMER3_CH0 */ #define TIMER3_CH0_PB6 \ GD32_PINMUX_AF('B', 6, AF2) /* TIMER3_CH1 */ #define TIMER3_CH1_PB7 \ GD32_PINMUX_AF('B', 7, AF2) /* TIMER3_CH2 */ #define TIMER3_CH2_PB8 \ GD32_PINMUX_AF('B', 8, AF2) /* TIMER3_CH3 */ #define TIMER3_CH3_PB9 \ GD32_PINMUX_AF('B', 9, AF2) /* TIMER4_CH0 */ #define TIMER4_CH0_PA0 \ GD32_PINMUX_AF('A', 0, AF2) /* TIMER4_CH1 */ #define TIMER4_CH1_PA1 \ GD32_PINMUX_AF('A', 1, AF2) /* TIMER4_CH2 */ #define TIMER4_CH2_PA2 \ GD32_PINMUX_AF('A', 2, AF2) /* TIMER4_CH3 */ #define TIMER4_CH3_PA3 \ GD32_PINMUX_AF('A', 3, AF2) /* TIMER7_BRKIN */ #define TIMER7_BRKIN_PA6 \ GD32_PINMUX_AF('A', 6, AF3) /* TIMER7_CH0 */ #define TIMER7_CH0_PC6 \ GD32_PINMUX_AF('C', 6, AF3) /* TIMER7_CH0_ON */ #define TIMER7_CH0_ON_PA5 \ GD32_PINMUX_AF('A', 5, AF3) #define TIMER7_CH0_ON_PA7 \ GD32_PINMUX_AF('A', 7, AF3) /* TIMER7_CH1 */ #define TIMER7_CH1_PC7 \ GD32_PINMUX_AF('C', 7, AF3) /* TIMER7_CH1_ON */ #define TIMER7_CH1_ON_PB0 \ GD32_PINMUX_AF('B', 0, AF3) #define TIMER7_CH1_ON_PB14 \ GD32_PINMUX_AF('B', 14, AF3) /* TIMER7_CH2 */ #define TIMER7_CH2_PC8 \ GD32_PINMUX_AF('C', 8, AF3) /* TIMER7_CH2_ON */ #define TIMER7_CH2_ON_PB1 \ GD32_PINMUX_AF('B', 1, AF3) #define TIMER7_CH2_ON_PB15 \ GD32_PINMUX_AF('B', 15, AF3) /* TIMER7_CH3 */ #define TIMER7_CH3_PC9 \ GD32_PINMUX_AF('C', 9, AF3) /* TIMER7_ETI */ #define TIMER7_ETI_PA0 \ GD32_PINMUX_AF('A', 0, AF3) /* TIMER8_CH0 */ #define TIMER8_CH0_PA2 \ GD32_PINMUX_AF('A', 2, AF3) /* TIMER8_CH1 */ #define TIMER8_CH1_PA3 \ GD32_PINMUX_AF('A', 3, AF3) /* TIMER9_CH0 */ #define TIMER9_CH0_PB8 \ GD32_PINMUX_AF('B', 8, AF3) /* TRACED0 */ #define TRACED0_PC8 \ GD32_PINMUX_AF('C', 8, AF0) /* TRACESWO */ #define TRACESWO_PB3 \ GD32_PINMUX_AF('B', 3, AF0) /* UART3_RX */ #define UART3_RX_PA1 \ GD32_PINMUX_AF('A', 1, AF8) #define UART3_RX_PC11 \ GD32_PINMUX_AF('C', 11, AF8) /* UART3_TX */ #define UART3_TX_PA0 \ GD32_PINMUX_AF('A', 0, AF8) #define UART3_TX_PC10 \ GD32_PINMUX_AF('C', 10, AF8) /* UART4_RX */ #define UART4_RX_PD2 \ GD32_PINMUX_AF('D', 2, AF8) /* UART4_TX */ #define UART4_TX_PC12 \ GD32_PINMUX_AF('C', 12, AF8) /* USART0_CK */ #define USART0_CK_PA8 \ GD32_PINMUX_AF('A', 8, AF7) /* USART0_CTS */ #define USART0_CTS_PA11 \ GD32_PINMUX_AF('A', 11, AF7) /* USART0_RTS */ #define USART0_RTS_PA12 \ GD32_PINMUX_AF('A', 12, AF7) /* USART0_RX */ #define USART0_RX_PA10 \ GD32_PINMUX_AF('A', 10, AF7) #define USART0_RX_PB3 \ GD32_PINMUX_AF('B', 3, AF7) #define USART0_RX_PB7 \ GD32_PINMUX_AF('B', 7, AF7) /* USART0_TX */ #define USART0_TX_PA9 \ GD32_PINMUX_AF('A', 9, AF7) #define USART0_TX_PA15 \ GD32_PINMUX_AF('A', 15, AF7) #define USART0_TX_PB6 \ GD32_PINMUX_AF('B', 6, AF7) /* USART1_CK */ #define USART1_CK_PA4 \ GD32_PINMUX_AF('A', 4, AF7) /* USART1_CTS */ #define USART1_CTS_PA0 \ GD32_PINMUX_AF('A', 0, AF7) /* USART1_RTS */ #define USART1_RTS_PA1 \ GD32_PINMUX_AF('A', 1, AF7) /* USART1_RX */ #define USART1_RX_PA3 \ GD32_PINMUX_AF('A', 3, AF7) /* USART1_TX */ #define USART1_TX_PA2 \ GD32_PINMUX_AF('A', 2, AF7) /* USART2_CK */ #define USART2_CK_PB12 \ GD32_PINMUX_AF('B', 12, AF7) #define USART2_CK_PC12 \ GD32_PINMUX_AF('C', 12, AF7) /* USART2_CTS */ #define USART2_CTS_PB13 \ GD32_PINMUX_AF('B', 13, AF7) /* USART2_RTS */ #define USART2_RTS_PB14 \ GD32_PINMUX_AF('B', 14, AF7) /* USART2_RX */ #define USART2_RX_PB11 \ GD32_PINMUX_AF('B', 11, AF7) #define USART2_RX_PC5 \ GD32_PINMUX_AF('C', 5, AF7) #define USART2_RX_PC11 \ GD32_PINMUX_AF('C', 11, AF7) /* USART2_TX */ #define USART2_TX_PB10 \ GD32_PINMUX_AF('B', 10, AF7) #define USART2_TX_PC10 \ GD32_PINMUX_AF('C', 10, AF7) /* USART5_CK */ #define USART5_CK_PC8 \ GD32_PINMUX_AF('C', 8, AF8) /* USART5_RX */ #define USART5_RX_PA12 \ GD32_PINMUX_AF('A', 12, AF8) #define USART5_RX_PC7 \ GD32_PINMUX_AF('C', 7, AF8) /* USART5_TX */ #define USART5_TX_PA11 \ GD32_PINMUX_AF('A', 11, AF8) #define USART5_TX_PC6 \ GD32_PINMUX_AF('C', 6, AF8) /* USBFS_DM */ #define USBFS_DM_PA11 \ GD32_PINMUX_AF('A', 11, AF10) /* USBFS_DP */ #define USBFS_DP_PA12 \ GD32_PINMUX_AF('A', 12, AF10) /* USBFS_ID */ #define USBFS_ID_PA10 \ GD32_PINMUX_AF('A', 10, AF10) /* USBFS_SOF */ #define USBFS_SOF_PA8 \ GD32_PINMUX_AF('A', 8, AF10) /* USBHS_DM */ #define USBHS_DM_PB14 \ GD32_PINMUX_AF('B', 14, AF12) /* USBHS_DP */ #define USBHS_DP_PB15 \ GD32_PINMUX_AF('B', 15, AF12) /* USBHS_ID */ #define USBHS_ID_PB12 \ GD32_PINMUX_AF('B', 12, AF12) /* USBHS_SOF */ #define USBHS_SOF_PA4 \ GD32_PINMUX_AF('A', 4, AF12) /* USBHS_ULPI_CK */ #define USBHS_ULPI_CK_PA5 \ GD32_PINMUX_AF('A', 5, AF10) /* USBHS_ULPI_D0 */ #define USBHS_ULPI_D0_PA3 \ GD32_PINMUX_AF('A', 3, AF10) /* USBHS_ULPI_D1 */ #define USBHS_ULPI_D1_PB0 \ GD32_PINMUX_AF('B', 0, AF10) /* USBHS_ULPI_D2 */ #define USBHS_ULPI_D2_PB1 \ GD32_PINMUX_AF('B', 1, AF10) /* USBHS_ULPI_D3 */ #define USBHS_ULPI_D3_PB10 \ GD32_PINMUX_AF('B', 10, AF10) /* USBHS_ULPI_D4 */ #define USBHS_ULPI_D4_PB2 \ GD32_PINMUX_AF('B', 2, AF10) #define USBHS_ULPI_D4_PB11 \ GD32_PINMUX_AF('B', 11, AF10) /* USBHS_ULPI_D5 */ #define USBHS_ULPI_D5_PB12 \ GD32_PINMUX_AF('B', 12, AF10) /* USBHS_ULPI_D6 */ #define USBHS_ULPI_D6_PB13 \ GD32_PINMUX_AF('B', 13, AF10) /* USBHS_ULPI_D7 */ #define USBHS_ULPI_D7_PB5 \ GD32_PINMUX_AF('B', 5, AF10) /* USBHS_ULPI_DIR */ #define USBHS_ULPI_DIR_PC2 \ GD32_PINMUX_AF('C', 2, AF10) /* USBHS_ULPI_NXT */ #define USBHS_ULPI_NXT_PC3 \ GD32_PINMUX_AF('C', 3, AF10) /* USBHS_ULPI_STP */ #define USBHS_ULPI_STP_PC0 \ GD32_PINMUX_AF('C', 0, AF10)