/* * Autogenerated file * * SPDX-License-Identifier: Apache 2.0 */ #include "gd32-af.h" /* ADC_IN0 */ #define ADC_IN0_PA0 \ GD32_PINMUX_AF('A', 0, ANALOG) /* ADC_IN1 */ #define ADC_IN1_PA1 \ GD32_PINMUX_AF('A', 1, ANALOG) /* ADC_IN2 */ #define ADC_IN2_PA2 \ GD32_PINMUX_AF('A', 2, ANALOG) /* ADC_IN3 */ #define ADC_IN3_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) /* ADC_IN4 */ #define ADC_IN4_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) /* ADC_IN5 */ #define ADC_IN5_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) /* ADC_IN6 */ #define ADC_IN6_PA6 \ GD32_PINMUX_AF('A', 6, ANALOG) /* ADC_IN7 */ #define ADC_IN7_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) /* ADC_IN8 */ #define ADC_IN8_PB0 \ GD32_PINMUX_AF('B', 0, ANALOG) /* ADC_IN9 */ #define ADC_IN9_PB1 \ GD32_PINMUX_AF('B', 1, ANALOG) /* ANALOG */ #define ANALOG_PA0 \ GD32_PINMUX_AF('A', 0, ANALOG) #define ANALOG_PA1 \ GD32_PINMUX_AF('A', 1, ANALOG) #define ANALOG_PA2 \ GD32_PINMUX_AF('A', 2, ANALOG) #define ANALOG_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) #define ANALOG_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) #define ANALOG_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) #define ANALOG_PA6 \ GD32_PINMUX_AF('A', 6, ANALOG) #define ANALOG_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) #define ANALOG_PA8 \ GD32_PINMUX_AF('A', 8, ANALOG) #define ANALOG_PA9 \ GD32_PINMUX_AF('A', 9, ANALOG) #define ANALOG_PA10 \ GD32_PINMUX_AF('A', 10, ANALOG) #define ANALOG_PA11 \ GD32_PINMUX_AF('A', 11, ANALOG) #define ANALOG_PA12 \ GD32_PINMUX_AF('A', 12, ANALOG) #define ANALOG_PA13 \ GD32_PINMUX_AF('A', 13, ANALOG) #define ANALOG_PA14 \ GD32_PINMUX_AF('A', 14, ANALOG) #define ANALOG_PA15 \ GD32_PINMUX_AF('A', 15, ANALOG) #define ANALOG_PB0 \ GD32_PINMUX_AF('B', 0, ANALOG) #define ANALOG_PB1 \ GD32_PINMUX_AF('B', 1, ANALOG) #define ANALOG_PB2 \ GD32_PINMUX_AF('B', 2, ANALOG) #define ANALOG_PB3 \ GD32_PINMUX_AF('B', 3, ANALOG) #define ANALOG_PB4 \ GD32_PINMUX_AF('B', 4, ANALOG) #define ANALOG_PB5 \ GD32_PINMUX_AF('B', 5, ANALOG) #define ANALOG_PB6 \ GD32_PINMUX_AF('B', 6, ANALOG) #define ANALOG_PB7 \ GD32_PINMUX_AF('B', 7, ANALOG) #define ANALOG_PB8 \ GD32_PINMUX_AF('B', 8, ANALOG) #define ANALOG_PB9 \ GD32_PINMUX_AF('B', 9, ANALOG) #define ANALOG_PB10 \ GD32_PINMUX_AF('B', 10, ANALOG) #define ANALOG_PB11 \ GD32_PINMUX_AF('B', 11, ANALOG) #define ANALOG_PB12 \ GD32_PINMUX_AF('B', 12, ANALOG) #define ANALOG_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) #define ANALOG_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) #define ANALOG_PB15 \ GD32_PINMUX_AF('B', 15, ANALOG) #define ANALOG_PF0 \ GD32_PINMUX_AF('F', 0, ANALOG) #define ANALOG_PF6 \ GD32_PINMUX_AF('F', 6, ANALOG) #define ANALOG_PF7 \ GD32_PINMUX_AF('F', 7, ANALOG) /* CEC */ #define CEC_PA5 \ GD32_PINMUX_AF('A', 5, AF1) #define CEC_PB8 \ GD32_PINMUX_AF('B', 8, AF0) #define CEC_PB10 \ GD32_PINMUX_AF('B', 10, AF0) /* CK_OUT */ #define CK_OUT_PA8 \ GD32_PINMUX_AF('A', 8, AF0) /* CMP0_OUT */ #define CMP0_OUT_PA0 \ GD32_PINMUX_AF('A', 0, AF7) #define CMP0_OUT_PA6 \ GD32_PINMUX_AF('A', 6, AF7) #define CMP0_OUT_PA11 \ GD32_PINMUX_AF('A', 11, AF7) /* CMP1_OUT */ #define CMP1_OUT_PA2 \ GD32_PINMUX_AF('A', 2, AF7) #define CMP1_OUT_PA7 \ GD32_PINMUX_AF('A', 7, AF7) #define CMP1_OUT_PA12 \ GD32_PINMUX_AF('A', 12, AF7) /* CTC_SYNC */ #define CTC_SYNC_PA8 \ GD32_PINMUX_AF('A', 8, AF6) #define CTC_SYNC_PF0 \ GD32_PINMUX_AF('F', 0, AF0) /* DAC0_OUT */ #define DAC0_OUT_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) /* EVENTOUT */ #define EVENTOUT_PA1 \ GD32_PINMUX_AF('A', 1, AF0) #define EVENTOUT_PA6 \ GD32_PINMUX_AF('A', 6, AF6) #define EVENTOUT_PA7 \ GD32_PINMUX_AF('A', 7, AF6) #define EVENTOUT_PA8 \ GD32_PINMUX_AF('A', 8, AF3) #define EVENTOUT_PA11 \ GD32_PINMUX_AF('A', 11, AF0) #define EVENTOUT_PA12 \ GD32_PINMUX_AF('A', 12, AF0) #define EVENTOUT_PA15 \ GD32_PINMUX_AF('A', 15, AF3) #define EVENTOUT_PB0 \ GD32_PINMUX_AF('B', 0, AF0) #define EVENTOUT_PB3 \ GD32_PINMUX_AF('B', 3, AF1) #define EVENTOUT_PB4 \ GD32_PINMUX_AF('B', 4, AF2) #define EVENTOUT_PB9 \ GD32_PINMUX_AF('B', 9, AF3) #define EVENTOUT_PB11 \ GD32_PINMUX_AF('B', 11, AF0) #define EVENTOUT_PB12 \ GD32_PINMUX_AF('B', 12, AF1) /* I2C0_SCL */ #define I2C0_SCL_PA9 \ GD32_PINMUX_AF('A', 9, AF4) #define I2C0_SCL_PB6 \ GD32_PINMUX_AF('B', 6, AF1) #define I2C0_SCL_PB8 \ GD32_PINMUX_AF('B', 8, AF1) #define I2C0_SCL_PB10 \ GD32_PINMUX_AF('B', 10, AF1) #define I2C0_SCL_PF6 \ GD32_PINMUX_AF('F', 6, AF0) /* I2C0_SDA */ #define I2C0_SDA_PA10 \ GD32_PINMUX_AF('A', 10, AF4) #define I2C0_SDA_PB7 \ GD32_PINMUX_AF('B', 7, AF1) #define I2C0_SDA_PB9 \ GD32_PINMUX_AF('B', 9, AF1) #define I2C0_SDA_PB11 \ GD32_PINMUX_AF('B', 11, AF1) #define I2C0_SDA_PF7 \ GD32_PINMUX_AF('F', 7, AF0) /* I2C0_SMBA */ #define I2C0_SMBA_PB5 \ GD32_PINMUX_AF('B', 5, AF3) /* I2S0_CK */ #define I2S0_CK_PA5 \ GD32_PINMUX_AF('A', 5, AF0) #define I2S0_CK_PB3 \ GD32_PINMUX_AF('B', 3, AF0) /* I2S0_MCK */ #define I2S0_MCK_PA6 \ GD32_PINMUX_AF('A', 6, AF0) #define I2S0_MCK_PB4 \ GD32_PINMUX_AF('B', 4, AF0) #define I2S0_MCK_PB9 \ GD32_PINMUX_AF('B', 9, AF5) /* I2S0_SD */ #define I2S0_SD_PA7 \ GD32_PINMUX_AF('A', 7, AF0) #define I2S0_SD_PB5 \ GD32_PINMUX_AF('B', 5, AF0) /* I2S0_WS */ #define I2S0_WS_PA4 \ GD32_PINMUX_AF('A', 4, AF0) #define I2S0_WS_PA15 \ GD32_PINMUX_AF('A', 15, AF0) /* IFRP_OUT */ #define IFRP_OUT_PA13 \ GD32_PINMUX_AF('A', 13, AF1) #define IFRP_OUT_PB9 \ GD32_PINMUX_AF('B', 9, AF0) /* SPI0_MISO */ #define SPI0_MISO_PA6 \ GD32_PINMUX_AF('A', 6, AF0) #define SPI0_MISO_PB4 \ GD32_PINMUX_AF('B', 4, AF0) #define SPI0_MISO_PB14 \ GD32_PINMUX_AF('B', 14, AF0) /* SPI0_MOSI */ #define SPI0_MOSI_PA7 \ GD32_PINMUX_AF('A', 7, AF0) #define SPI0_MOSI_PB5 \ GD32_PINMUX_AF('B', 5, AF0) #define SPI0_MOSI_PB15 \ GD32_PINMUX_AF('B', 15, AF0) /* SPI0_NSS */ #define SPI0_NSS_PA4 \ GD32_PINMUX_AF('A', 4, AF0) #define SPI0_NSS_PA15 \ GD32_PINMUX_AF('A', 15, AF0) #define SPI0_NSS_PB12 \ GD32_PINMUX_AF('B', 12, AF0) /* SPI0_SCK */ #define SPI0_SCK_PA5 \ GD32_PINMUX_AF('A', 5, AF0) #define SPI0_SCK_PB3 \ GD32_PINMUX_AF('B', 3, AF0) #define SPI0_SCK_PB13 \ GD32_PINMUX_AF('B', 13, AF0) /* SWCLK */ #define SWCLK_PA14 \ GD32_PINMUX_AF('A', 14, AF0) /* SWDIO */ #define SWDIO_PA13 \ GD32_PINMUX_AF('A', 13, AF0) /* TIMER0_BKIN */ #define TIMER0_BKIN_PA6 \ GD32_PINMUX_AF('A', 6, AF2) #define TIMER0_BKIN_PB12 \ GD32_PINMUX_AF('B', 12, AF2) /* TIMER0_CH0 */ #define TIMER0_CH0_PA8 \ GD32_PINMUX_AF('A', 8, AF2) /* TIMER0_CH0_ON */ #define TIMER0_CH0_ON_PA7 \ GD32_PINMUX_AF('A', 7, AF2) #define TIMER0_CH0_ON_PB13 \ GD32_PINMUX_AF('B', 13, AF2) /* TIMER0_CH1 */ #define TIMER0_CH1_PA9 \ GD32_PINMUX_AF('A', 9, AF2) /* TIMER0_CH1_ON */ #define TIMER0_CH1_ON_PB0 \ GD32_PINMUX_AF('B', 0, AF2) #define TIMER0_CH1_ON_PB14 \ GD32_PINMUX_AF('B', 14, AF2) /* TIMER0_CH2 */ #define TIMER0_CH2_PA10 \ GD32_PINMUX_AF('A', 10, AF2) /* TIMER0_CH2_ON */ #define TIMER0_CH2_ON_PB1 \ GD32_PINMUX_AF('B', 1, AF2) #define TIMER0_CH2_ON_PB15 \ GD32_PINMUX_AF('B', 15, AF2) /* TIMER0_CH3 */ #define TIMER0_CH3_PA11 \ GD32_PINMUX_AF('A', 11, AF2) /* TIMER0_ETI */ #define TIMER0_ETI_PA12 \ GD32_PINMUX_AF('A', 12, AF2) /* TIMER13_CH0 */ #define TIMER13_CH0_PA4 \ GD32_PINMUX_AF('A', 4, AF4) #define TIMER13_CH0_PA7 \ GD32_PINMUX_AF('A', 7, AF4) #define TIMER13_CH0_PB1 \ GD32_PINMUX_AF('B', 1, AF0) /* TIMER14_BKIN */ #define TIMER14_BKIN_PA9 \ GD32_PINMUX_AF('A', 9, AF0) /* TIMER14_CH0 */ #define TIMER14_CH0_PA2 \ GD32_PINMUX_AF('A', 2, AF0) #define TIMER14_CH0_PB14 \ GD32_PINMUX_AF('B', 14, AF1) /* TIMER14_CH0_ON */ #define TIMER14_CH0_ON_PB15 \ GD32_PINMUX_AF('B', 15, AF3) /* TIMER14_CH1 */ #define TIMER14_CH1_PA3 \ GD32_PINMUX_AF('A', 3, AF0) #define TIMER14_CH1_PB15 \ GD32_PINMUX_AF('B', 15, AF1) /* TIMER15_BKIN */ #define TIMER15_BKIN_PB5 \ GD32_PINMUX_AF('B', 5, AF2) /* TIMER15_CH0 */ #define TIMER15_CH0_PA6 \ GD32_PINMUX_AF('A', 6, AF5) #define TIMER15_CH0_PB8 \ GD32_PINMUX_AF('B', 8, AF2) /* TIMER15_CH0_ON */ #define TIMER15_CH0_ON_PB6 \ GD32_PINMUX_AF('B', 6, AF2) /* TIMER16_BKIN */ #define TIMER16_BKIN_PA10 \ GD32_PINMUX_AF('A', 10, AF0) /* TIMER16_CH0 */ #define TIMER16_CH0_PA7 \ GD32_PINMUX_AF('A', 7, AF5) #define TIMER16_CH0_PB9 \ GD32_PINMUX_AF('B', 9, AF2) /* TIMER16_CH0_ON */ #define TIMER16_CH0_ON_PB7 \ GD32_PINMUX_AF('B', 7, AF2) /* TIMER1_CH0 */ #define TIMER1_CH0_PA0 \ GD32_PINMUX_AF('A', 0, AF2) #define TIMER1_CH0_PA5 \ GD32_PINMUX_AF('A', 5, AF2) #define TIMER1_CH0_PA15 \ GD32_PINMUX_AF('A', 15, AF2) /* TIMER1_CH1 */ #define TIMER1_CH1_PA1 \ GD32_PINMUX_AF('A', 1, AF2) #define TIMER1_CH1_PB3 \ GD32_PINMUX_AF('B', 3, AF2) /* TIMER1_CH2 */ #define TIMER1_CH2_PA2 \ GD32_PINMUX_AF('A', 2, AF2) #define TIMER1_CH2_PB10 \ GD32_PINMUX_AF('B', 10, AF2) /* TIMER1_CH3 */ #define TIMER1_CH3_PA3 \ GD32_PINMUX_AF('A', 3, AF2) #define TIMER1_CH3_PB11 \ GD32_PINMUX_AF('B', 11, AF2) /* TIMER1_ETI */ #define TIMER1_ETI_PA0 \ GD32_PINMUX_AF('A', 0, AF2) #define TIMER1_ETI_PA5 \ GD32_PINMUX_AF('A', 5, AF2) #define TIMER1_ETI_PA15 \ GD32_PINMUX_AF('A', 15, AF2) /* TIMER2_CH0 */ #define TIMER2_CH0_PA6 \ GD32_PINMUX_AF('A', 6, AF1) #define TIMER2_CH0_PB4 \ GD32_PINMUX_AF('B', 4, AF1) /* TIMER2_CH1 */ #define TIMER2_CH1_PA7 \ GD32_PINMUX_AF('A', 7, AF1) #define TIMER2_CH1_PB5 \ GD32_PINMUX_AF('B', 5, AF1) /* TIMER2_CH2 */ #define TIMER2_CH2_PB0 \ GD32_PINMUX_AF('B', 0, AF1) /* TIMER2_CH3 */ #define TIMER2_CH3_PB1 \ GD32_PINMUX_AF('B', 1, AF1) /* TSITG */ #define TSITG_PB8 \ GD32_PINMUX_AF('B', 8, AF3) #define TSITG_PB10 \ GD32_PINMUX_AF('B', 10, AF3) /* TSI_G0_IO0 */ #define TSI_G0_IO0_PA0 \ GD32_PINMUX_AF('A', 0, AF3) /* TSI_G0_IO1 */ #define TSI_G0_IO1_PA1 \ GD32_PINMUX_AF('A', 1, AF3) /* TSI_G0_IO2 */ #define TSI_G0_IO2_PA2 \ GD32_PINMUX_AF('A', 2, AF3) /* TSI_G0_IO3 */ #define TSI_G0_IO3_PA3 \ GD32_PINMUX_AF('A', 3, AF3) /* TSI_G1_IO0 */ #define TSI_G1_IO0_PA4 \ GD32_PINMUX_AF('A', 4, AF3) /* TSI_G1_IO1 */ #define TSI_G1_IO1_PA5 \ GD32_PINMUX_AF('A', 5, AF3) /* TSI_G1_IO2 */ #define TSI_G1_IO2_PA6 \ GD32_PINMUX_AF('A', 6, AF3) /* TSI_G1_IO3 */ #define TSI_G1_IO3_PA7 \ GD32_PINMUX_AF('A', 7, AF3) /* TSI_G2_IO1 */ #define TSI_G2_IO1_PB0 \ GD32_PINMUX_AF('B', 0, AF3) /* TSI_G2_IO2 */ #define TSI_G2_IO2_PB1 \ GD32_PINMUX_AF('B', 1, AF3) /* TSI_G2_IO3 */ #define TSI_G2_IO3_PB2 \ GD32_PINMUX_AF('B', 2, AF3) /* TSI_G3_IO0 */ #define TSI_G3_IO0_PA9 \ GD32_PINMUX_AF('A', 9, AF3) /* TSI_G3_IO1 */ #define TSI_G3_IO1_PA10 \ GD32_PINMUX_AF('A', 10, AF3) /* TSI_G3_IO2 */ #define TSI_G3_IO2_PA11 \ GD32_PINMUX_AF('A', 11, AF3) /* TSI_G3_IO3 */ #define TSI_G3_IO3_PA12 \ GD32_PINMUX_AF('A', 12, AF3) /* TSI_G4_IO0 */ #define TSI_G4_IO0_PB3 \ GD32_PINMUX_AF('B', 3, AF3) /* TSI_G4_IO1 */ #define TSI_G4_IO1_PB4 \ GD32_PINMUX_AF('B', 4, AF3) /* TSI_G4_IO2 */ #define TSI_G4_IO2_PB6 \ GD32_PINMUX_AF('B', 6, AF3) /* TSI_G4_IO3 */ #define TSI_G4_IO3_PB7 \ GD32_PINMUX_AF('B', 7, AF3) /* TSI_G5_IO0 */ #define TSI_G5_IO0_PB11 \ GD32_PINMUX_AF('B', 11, AF3) /* TSI_G5_IO1 */ #define TSI_G5_IO1_PB12 \ GD32_PINMUX_AF('B', 12, AF3) /* TSI_G5_IO2 */ #define TSI_G5_IO2_PB13 \ GD32_PINMUX_AF('B', 13, AF3) /* TSI_G5_IO3 */ #define TSI_G5_IO3_PB14 \ GD32_PINMUX_AF('B', 14, AF3) /* USART0_CK */ #define USART0_CK_PA4 \ GD32_PINMUX_AF('A', 4, AF1) #define USART0_CK_PA8 \ GD32_PINMUX_AF('A', 8, AF1) /* USART0_CTS */ #define USART0_CTS_PA0 \ GD32_PINMUX_AF('A', 0, AF1) #define USART0_CTS_PA11 \ GD32_PINMUX_AF('A', 11, AF1) /* USART0_RTS */ #define USART0_RTS_PA1 \ GD32_PINMUX_AF('A', 1, AF1) #define USART0_RTS_PA12 \ GD32_PINMUX_AF('A', 12, AF1) /* USART0_RX */ #define USART0_RX_PA3 \ GD32_PINMUX_AF('A', 3, AF1) #define USART0_RX_PA10 \ GD32_PINMUX_AF('A', 10, AF1) #define USART0_RX_PA15 \ GD32_PINMUX_AF('A', 15, AF1) #define USART0_RX_PB7 \ GD32_PINMUX_AF('B', 7, AF0) /* USART0_TX */ #define USART0_TX_PA2 \ GD32_PINMUX_AF('A', 2, AF1) #define USART0_TX_PA9 \ GD32_PINMUX_AF('A', 9, AF1) #define USART0_TX_PA14 \ GD32_PINMUX_AF('A', 14, AF1) #define USART0_TX_PB6 \ GD32_PINMUX_AF('B', 6, AF0) /* USART1_CK */ #define USART1_CK_PA4 \ GD32_PINMUX_AF('A', 4, AF1) /* USART1_CTS */ #define USART1_CTS_PA0 \ GD32_PINMUX_AF('A', 0, AF1) /* USART1_RTS */ #define USART1_RTS_PA1 \ GD32_PINMUX_AF('A', 1, AF1) /* USART1_RX */ #define USART1_RX_PA3 \ GD32_PINMUX_AF('A', 3, AF1) #define USART1_RX_PA15 \ GD32_PINMUX_AF('A', 15, AF1) #define USART1_RX_PB0 \ GD32_PINMUX_AF('B', 0, AF4) /* USART1_TX */ #define USART1_TX_PA2 \ GD32_PINMUX_AF('A', 2, AF1) #define USART1_TX_PA8 \ GD32_PINMUX_AF('A', 8, AF4) #define USART1_TX_PA14 \ GD32_PINMUX_AF('A', 14, AF1) /* USBFS_ID */ #define USBFS_ID_PA10 \ GD32_PINMUX_AF('A', 10, AF5) /* USBFS_SOF */ #define USBFS_SOF_PA8 \ GD32_PINMUX_AF('A', 8, AF5) /* USBFS_VBUS */ #define USBFS_VBUS_PA9 \ GD32_PINMUX_AF('A', 9, AF5)