/* * Autogenerated file * * SPDX-License-Identifier: Apache 2.0 */ #include "gd32-af.h" /* ADC0_IN0 */ #define ADC0_IN0_PC11 \ GD32_PINMUX_AF('C', 11, ANALOG) /* ADC0_IN1 */ #define ADC0_IN1_PC10 \ GD32_PINMUX_AF('C', 10, ANALOG) /* ADC0_IN10 */ #define ADC0_IN10_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) /* ADC0_IN11 */ #define ADC0_IN11_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) /* ADC0_IN3 */ #define ADC0_IN3_PD9 \ GD32_PINMUX_AF('D', 9, ANALOG) /* ADC0_IN4 */ #define ADC0_IN4_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) /* ADC0_IN5 */ #define ADC0_IN5_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) /* ADC0_IN6 */ #define ADC0_IN6_PE14 \ GD32_PINMUX_AF('E', 14, ANALOG) /* ADC0_IN7 */ #define ADC0_IN7_PE13 \ GD32_PINMUX_AF('E', 13, ANALOG) /* ADC1_IN0 */ #define ADC1_IN0_PA11 \ GD32_PINMUX_AF('A', 11, ANALOG) /* ADC1_IN1 */ #define ADC1_IN1_PA10 \ GD32_PINMUX_AF('A', 10, ANALOG) /* ADC1_IN14 */ #define ADC1_IN14_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) /* ADC1_IN15 */ #define ADC1_IN15_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) /* ADC1_IN3 */ #define ADC1_IN3_PA8 \ GD32_PINMUX_AF('A', 8, ANALOG) /* ANALOG */ #define ANALOG_PA0 \ GD32_PINMUX_AF('A', 0, ANALOG) #define ANALOG_PA1 \ GD32_PINMUX_AF('A', 1, ANALOG) #define ANALOG_PA2 \ GD32_PINMUX_AF('A', 2, ANALOG) #define ANALOG_PA3 \ GD32_PINMUX_AF('A', 3, ANALOG) #define ANALOG_PA4 \ GD32_PINMUX_AF('A', 4, ANALOG) #define ANALOG_PA5 \ GD32_PINMUX_AF('A', 5, ANALOG) #define ANALOG_PA6 \ GD32_PINMUX_AF('A', 6, ANALOG) #define ANALOG_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) #define ANALOG_PA8 \ GD32_PINMUX_AF('A', 8, ANALOG) #define ANALOG_PA10 \ GD32_PINMUX_AF('A', 10, ANALOG) #define ANALOG_PA11 \ GD32_PINMUX_AF('A', 11, ANALOG) #define ANALOG_PB3 \ GD32_PINMUX_AF('B', 3, ANALOG) #define ANALOG_PB4 \ GD32_PINMUX_AF('B', 4, ANALOG) #define ANALOG_PB7 \ GD32_PINMUX_AF('B', 7, ANALOG) #define ANALOG_PB8 \ GD32_PINMUX_AF('B', 8, ANALOG) #define ANALOG_PB9 \ GD32_PINMUX_AF('B', 9, ANALOG) #define ANALOG_PB13 \ GD32_PINMUX_AF('B', 13, ANALOG) #define ANALOG_PB14 \ GD32_PINMUX_AF('B', 14, ANALOG) #define ANALOG_PC0 \ GD32_PINMUX_AF('C', 0, ANALOG) #define ANALOG_PC10 \ GD32_PINMUX_AF('C', 10, ANALOG) #define ANALOG_PC11 \ GD32_PINMUX_AF('C', 11, ANALOG) #define ANALOG_PC15 \ GD32_PINMUX_AF('C', 15, ANALOG) #define ANALOG_PD9 \ GD32_PINMUX_AF('D', 9, ANALOG) #define ANALOG_PE13 \ GD32_PINMUX_AF('E', 13, ANALOG) #define ANALOG_PE14 \ GD32_PINMUX_AF('E', 14, ANALOG) #define ANALOG_PF0 \ GD32_PINMUX_AF('F', 0, ANALOG) #define ANALOG_PF5 \ GD32_PINMUX_AF('F', 5, ANALOG) #define ANALOG_PF6 \ GD32_PINMUX_AF('F', 6, ANALOG) #define ANALOG_PF7 \ GD32_PINMUX_AF('F', 7, ANALOG) /* CAN0_RX */ #define CAN0_RX_PA4 \ GD32_PINMUX_AF('A', 4, AF6) #define CAN0_RX_PB14 \ GD32_PINMUX_AF('B', 14, AF6) #define CAN0_RX_PF0 \ GD32_PINMUX_AF('F', 0, AF6) /* CAN0_TX */ #define CAN0_TX_PA3 \ GD32_PINMUX_AF('A', 3, AF6) #define CAN0_TX_PB13 \ GD32_PINMUX_AF('B', 13, AF6) #define CAN0_TX_PC15 \ GD32_PINMUX_AF('C', 15, AF6) /* CK_OUT0 */ #define CK_OUT0_PA1 \ GD32_PINMUX_AF('A', 1, AF0) /* CMP_OUT */ #define CMP_OUT_PB9 \ GD32_PINMUX_AF('B', 9, AF7) /* DAC_OUT */ #define DAC_OUT_PA7 \ GD32_PINMUX_AF('A', 7, ANALOG) /* EVENTOUT */ #define EVENTOUT_PA0 \ GD32_PINMUX_AF('A', 0, AF9) #define EVENTOUT_PA1 \ GD32_PINMUX_AF('A', 1, AF9) #define EVENTOUT_PA2 \ GD32_PINMUX_AF('A', 2, AF9) #define EVENTOUT_PA3 \ GD32_PINMUX_AF('A', 3, AF9) #define EVENTOUT_PA4 \ GD32_PINMUX_AF('A', 4, AF9) #define EVENTOUT_PA5 \ GD32_PINMUX_AF('A', 5, AF9) #define EVENTOUT_PA7 \ GD32_PINMUX_AF('A', 7, AF9) #define EVENTOUT_PA8 \ GD32_PINMUX_AF('A', 8, AF9) #define EVENTOUT_PA10 \ GD32_PINMUX_AF('A', 10, AF9) #define EVENTOUT_PA11 \ GD32_PINMUX_AF('A', 11, AF9) #define EVENTOUT_PB3 \ GD32_PINMUX_AF('B', 3, AF9) #define EVENTOUT_PB4 \ GD32_PINMUX_AF('B', 4, AF9) #define EVENTOUT_PB7 \ GD32_PINMUX_AF('B', 7, AF9) #define EVENTOUT_PB8 \ GD32_PINMUX_AF('B', 8, AF9) #define EVENTOUT_PB9 \ GD32_PINMUX_AF('B', 9, AF9) #define EVENTOUT_PB13 \ GD32_PINMUX_AF('B', 13, AF9) #define EVENTOUT_PB14 \ GD32_PINMUX_AF('B', 14, AF9) #define EVENTOUT_PC0 \ GD32_PINMUX_AF('C', 0, AF9) #define EVENTOUT_PC10 \ GD32_PINMUX_AF('C', 10, AF9) #define EVENTOUT_PC11 \ GD32_PINMUX_AF('C', 11, AF9) #define EVENTOUT_PC15 \ GD32_PINMUX_AF('C', 15, AF9) #define EVENTOUT_PD9 \ GD32_PINMUX_AF('D', 9, AF9) #define EVENTOUT_PE13 \ GD32_PINMUX_AF('E', 13, AF9) #define EVENTOUT_PE14 \ GD32_PINMUX_AF('E', 14, AF9) #define EVENTOUT_PF0 \ GD32_PINMUX_AF('F', 0, AF9) #define EVENTOUT_PF5 \ GD32_PINMUX_AF('F', 5, AF9) #define EVENTOUT_PF6 \ GD32_PINMUX_AF('F', 6, AF9) #define EVENTOUT_PF7 \ GD32_PINMUX_AF('F', 7, AF9) /* I2C0_SCL */ #define I2C0_SCL_PA10 \ GD32_PINMUX_AF('A', 10, AF3) #define I2C0_SCL_PC11 \ GD32_PINMUX_AF('C', 11, AF3) #define I2C0_SCL_PF6 \ GD32_PINMUX_AF('F', 6, AF3) /* I2C0_SDA */ #define I2C0_SDA_PA11 \ GD32_PINMUX_AF('A', 11, AF3) #define I2C0_SDA_PC10 \ GD32_PINMUX_AF('C', 10, AF3) #define I2C0_SDA_PF7 \ GD32_PINMUX_AF('F', 7, AF3) /* I2C1_SCL */ #define I2C1_SCL_PB7 \ GD32_PINMUX_AF('B', 7, AF5) /* I2C1_SDA */ #define I2C1_SDA_PB8 \ GD32_PINMUX_AF('B', 8, AF5) /* I2C1_SMBA */ #define I2C1_SMBA_PB9 \ GD32_PINMUX_AF('B', 9, AF5) /* I2S1_WS */ #define I2S1_WS_PA8 \ GD32_PINMUX_AF('A', 8, AF4) /* JTCK */ #define JTCK_PB8 \ GD32_PINMUX_AF('B', 8, AF0) /* JTDI */ #define JTDI_PB7 \ GD32_PINMUX_AF('B', 7, AF0) /* JTDO */ #define JTDO_PB4 \ GD32_PINMUX_AF('B', 4, AF0) /* JTMS */ #define JTMS_PB9 \ GD32_PINMUX_AF('B', 9, AF0) /* MFCOM_D0 */ #define MFCOM_D0_PB4 \ GD32_PINMUX_AF('B', 4, AF6) /* MFCOM_D1 */ #define MFCOM_D1_PB3 \ GD32_PINMUX_AF('B', 3, AF6) /* MFCOM_D2 */ #define MFCOM_D2_PC11 \ GD32_PINMUX_AF('C', 11, AF6) /* MFCOM_D3 */ #define MFCOM_D3_PC10 \ GD32_PINMUX_AF('C', 10, AF6) /* MFCOM_D4 */ #define MFCOM_D4_PA11 \ GD32_PINMUX_AF('A', 11, AF6) /* MFCOM_D5 */ #define MFCOM_D5_PA8 \ GD32_PINMUX_AF('A', 8, AF6) #define MFCOM_D5_PA10 \ GD32_PINMUX_AF('A', 10, AF6) /* MFCOM_D6 */ #define MFCOM_D6_PF0 \ GD32_PINMUX_AF('F', 0, AF7) /* MFCOM_D7 */ #define MFCOM_D7_PA8 \ GD32_PINMUX_AF('A', 8, AF5) #define MFCOM_D7_PC15 \ GD32_PINMUX_AF('C', 15, AF7) /* NJTRST */ #define NJTRST_PB3 \ GD32_PINMUX_AF('B', 3, AF0) /* SPI0_IO2 */ #define SPI0_IO2_PB3 \ GD32_PINMUX_AF('B', 3, AF4) /* SPI0_IO3 */ #define SPI0_IO3_PB4 \ GD32_PINMUX_AF('B', 4, AF4) /* SPI0_MISO */ #define SPI0_MISO_PE13 \ GD32_PINMUX_AF('E', 13, AF4) #define SPI0_MISO_PF5 \ GD32_PINMUX_AF('F', 5, AF4) /* SPI0_MOSI */ #define SPI0_MOSI_PA2 \ GD32_PINMUX_AF('A', 2, AF4) #define SPI0_MOSI_PB13 \ GD32_PINMUX_AF('B', 13, AF4) /* SPI0_NSS */ #define SPI0_NSS_PA1 \ GD32_PINMUX_AF('A', 1, AF4) #define SPI0_NSS_PB14 \ GD32_PINMUX_AF('B', 14, AF3) /* SPI0_SCK */ #define SPI0_SCK_PC0 \ GD32_PINMUX_AF('C', 0, AF4) #define SPI0_SCK_PE14 \ GD32_PINMUX_AF('E', 14, AF4) /* SPI1_NSS */ #define SPI1_NSS_PA8 \ GD32_PINMUX_AF('A', 8, AF4) /* SWCLK */ #define SWCLK_PB8 \ GD32_PINMUX_AF('B', 8, AF0) /* SWDIO */ #define SWDIO_PB9 \ GD32_PINMUX_AF('B', 9, AF0) /* TIMER0_BRKIN0 */ #define TIMER0_BRKIN0_PA8 \ GD32_PINMUX_AF('A', 8, AF1) /* TIMER0_BRKIN2 */ #define TIMER0_BRKIN2_PD9 \ GD32_PINMUX_AF('D', 9, AF2) /* TIMER0_CH0 */ #define TIMER0_CH0_PC0 \ GD32_PINMUX_AF('C', 0, AF1) /* TIMER0_CH1 */ #define TIMER0_CH1_PA4 \ GD32_PINMUX_AF('A', 4, AF1) /* TIMER0_CH2 */ #define TIMER0_CH2_PA2 \ GD32_PINMUX_AF('A', 2, AF1) /* TIMER0_CH3 */ #define TIMER0_CH3_PA0 \ GD32_PINMUX_AF('A', 0, AF1) /* TIMER0_MCH0 */ #define TIMER0_MCH0_PF5 \ GD32_PINMUX_AF('F', 5, AF1) /* TIMER0_MCH1 */ #define TIMER0_MCH1_PA3 \ GD32_PINMUX_AF('A', 3, AF1) /* TIMER0_MCH2 */ #define TIMER0_MCH2_PA1 \ GD32_PINMUX_AF('A', 1, AF1) /* TIMER19_BRKIN1 */ #define TIMER19_BRKIN1_PA7 \ GD32_PINMUX_AF('A', 7, AF3) /* TIMER19_BRKIN2 */ #define TIMER19_BRKIN2_PA6 \ GD32_PINMUX_AF('A', 6, AF2) /* TIMER19_BRKIN3 */ #define TIMER19_BRKIN3_PA5 \ GD32_PINMUX_AF('A', 5, AF2) /* TIMER19_CH0 */ #define TIMER19_CH0_PB7 \ GD32_PINMUX_AF('B', 7, AF1) #define TIMER19_CH0_PC11 \ GD32_PINMUX_AF('C', 11, AF2) /* TIMER19_CH1 */ #define TIMER19_CH1_PB7 \ GD32_PINMUX_AF('B', 7, AF2) #define TIMER19_CH1_PC15 \ GD32_PINMUX_AF('C', 15, AF2) #define TIMER19_CH1_PF0 \ GD32_PINMUX_AF('F', 0, AF1) /* TIMER19_MCH0 */ #define TIMER19_MCH0_PC11 \ GD32_PINMUX_AF('C', 11, AF1) /* TIMER19_MCH1 */ #define TIMER19_MCH1_PA7 \ GD32_PINMUX_AF('A', 7, AF1) #define TIMER19_MCH1_PC15 \ GD32_PINMUX_AF('C', 15, AF1) /* TIMER1_CH1 */ #define TIMER1_CH1_PA7 \ GD32_PINMUX_AF('A', 7, AF2) /* TIMER1_CH2 */ #define TIMER1_CH2_PB14 \ GD32_PINMUX_AF('B', 14, AF1) /* TIMER1_CH3 */ #define TIMER1_CH3_PA3 \ GD32_PINMUX_AF('A', 3, AF2) /* TIMER20_CH0 */ #define TIMER20_CH0_PA11 \ GD32_PINMUX_AF('A', 11, AF1) /* TIMER20_MCH0 */ #define TIMER20_MCH0_PA10 \ GD32_PINMUX_AF('A', 10, AF1) /* TIMER20_MCH2 */ #define TIMER20_MCH2_PA8 \ GD32_PINMUX_AF('A', 8, AF2) /* TIMER7_CH0 */ #define TIMER7_CH0_PB8 \ GD32_PINMUX_AF('B', 8, AF1) #define TIMER7_CH0_PC10 \ GD32_PINMUX_AF('C', 10, AF2) #define TIMER7_CH0_PE13 \ GD32_PINMUX_AF('E', 13, AF2) #define TIMER7_CH0_PE14 \ GD32_PINMUX_AF('E', 14, AF1) /* TIMER7_CH1 */ #define TIMER7_CH1_PB8 \ GD32_PINMUX_AF('B', 8, AF2) #define TIMER7_CH1_PE14 \ GD32_PINMUX_AF('E', 14, AF2) /* TIMER7_CH2 */ #define TIMER7_CH2_PB4 \ GD32_PINMUX_AF('B', 4, AF1) /* TIMER7_MCH0 */ #define TIMER7_MCH0_PC10 \ GD32_PINMUX_AF('C', 10, AF1) #define TIMER7_MCH0_PE13 \ GD32_PINMUX_AF('E', 13, AF1) /* TIMER7_MCH2 */ #define TIMER7_MCH2_PB3 \ GD32_PINMUX_AF('B', 3, AF1) /* TIMER_ETI0 */ #define TIMER_ETI0_PB13 \ GD32_PINMUX_AF('B', 13, AF0) /* TIMER_ETI2 */ #define TIMER_ETI2_PC15 \ GD32_PINMUX_AF('C', 15, AF0) /* TRIGSEL_IN0 */ #define TRIGSEL_IN0_PA1 \ GD32_PINMUX_AF('A', 1, AF7) /* TRIGSEL_IN1 */ #define TRIGSEL_IN1_PA2 \ GD32_PINMUX_AF('A', 2, AF7) /* TRIGSEL_IN13 */ #define TRIGSEL_IN13_PA11 \ GD32_PINMUX_AF('A', 11, AF7) /* TRIGSEL_IN2 */ #define TRIGSEL_IN2_PE13 \ GD32_PINMUX_AF('E', 13, AF7) /* TRIGSEL_IN3 */ #define TRIGSEL_IN3_PE14 \ GD32_PINMUX_AF('E', 14, AF7) /* TRIGSEL_IN4 */ #define TRIGSEL_IN4_PA8 \ GD32_PINMUX_AF('A', 8, AF7) /* TRIGSEL_IN7 */ #define TRIGSEL_IN7_PA7 \ GD32_PINMUX_AF('A', 7, AF7) /* TRIGSEL_OUT0 */ #define TRIGSEL_OUT0_PC10 \ GD32_PINMUX_AF('C', 10, AF7) /* TRIGSEL_OUT3 */ #define TRIGSEL_OUT3_PC11 \ GD32_PINMUX_AF('C', 11, AF7) /* USART0_CTS */ #define USART0_CTS_PC11 \ GD32_PINMUX_AF('C', 11, AF5) /* USART0_DE */ #define USART0_DE_PC10 \ GD32_PINMUX_AF('C', 10, AF5) /* USART0_RTS */ #define USART0_RTS_PC10 \ GD32_PINMUX_AF('C', 10, AF5) /* USART0_RX */ #define USART0_RX_PA4 \ GD32_PINMUX_AF('A', 4, AF5) #define USART0_RX_PA11 \ GD32_PINMUX_AF('A', 11, AF5) #define USART0_RX_PB14 \ GD32_PINMUX_AF('B', 14, AF5) /* USART0_TX */ #define USART0_TX_PA3 \ GD32_PINMUX_AF('A', 3, AF5) #define USART0_TX_PA10 \ GD32_PINMUX_AF('A', 10, AF5) #define USART0_TX_PB13 \ GD32_PINMUX_AF('B', 13, AF5) /* USART1_CTS */ #define USART1_CTS_PF5 \ GD32_PINMUX_AF('F', 5, AF5) /* USART1_DE */ #define USART1_DE_PD9 \ GD32_PINMUX_AF('D', 9, AF5) /* USART1_RTS */ #define USART1_RTS_PD9 \ GD32_PINMUX_AF('D', 9, AF5) /* USART2_CK */ #define USART2_CK_PA7 \ GD32_PINMUX_AF('A', 7, AF5) /* USART2_RX */ #define USART2_RX_PA6 \ GD32_PINMUX_AF('A', 6, AF5) /* USART2_TX */ #define USART2_TX_PA5 \ GD32_PINMUX_AF('A', 5, AF5)