/* * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include #include #include "sdkconfig.h" #include "bootloader_common.h" #include "soc/efuse_reg.h" #include "soc/gpio_periph.h" #include "soc/gpio_sig_map.h" #include "soc/io_mux_reg.h" #include "bootloader_init.h" #include "bootloader_clock.h" #include "bootloader_flash_config.h" #include "bootloader_mem.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" #include "esp_private/bootloader_flash_internal.h" #include "esp_rom_gpio.h" #include "esp_rom_efuse.h" #include "esp_rom_sys.h" #include "esp_rom_spiflash.h" #include "esp_attr.h" #include "esp_log.h" #include "esp_image_format.h" #include "flash_qio_mode.h" #include "soc/assist_debug_reg.h" #include "esp_cpu.h" #include "soc/dport_reg.h" #include "soc/extmem_reg.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/spi_periph.h" #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" #if !defined(CONFIG_BOOTLOADER_MCUBOOT) #include "esp_flash_internal.h" #endif static const char *TAG = "boot.esp32s2"; static void wdt_reset_cpu0_info_enable(void) { DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_ASSIST_DEBUG); DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_ASSIST_DEBUG); REG_WRITE(ASSIST_DEBUG_PRO_PDEBUGENABLE, 1); REG_WRITE(ASSIST_DEBUG_PRO_RCD_RECORDING, 1); } static void wdt_reset_info_dump(int cpu) { /* FIXME: failing EDT test due to error in early log */ #if 0 uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0, lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0; const char *cpu_name = cpu ? "APP" : "PRO"; stat = 0xdeadbeef; pid = 0; inst = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGINST); dstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS); data = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGDATA); pc = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGPC); lsstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT); lsaddr = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR); lsdata = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA); if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 && DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) { ESP_EARLY_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32" (waiti mode)", cpu_name, pc); } else { ESP_EARLY_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32, cpu_name, pc); } ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat); ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08"PRIx32, cpu_name, pid); ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst); ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat); ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data); ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc); ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat); ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr); ESP_EARLY_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata); #endif } static void bootloader_check_wdt_reset(void) { int wdt_rst = 0; soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 || rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) { // PRO CPU has been reset by WDT wdt_rst = 1; } if (wdt_rst) { // if reset by WDT dump info from trace port wdt_reset_info_dump(0); } wdt_reset_cpu0_info_enable(); } static void bootloader_super_wdt_auto_feed(void) { REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); } esp_err_t bootloader_init(void) { esp_err_t ret = ESP_OK; bootloader_super_wdt_auto_feed(); // protect memory region // In RAM_APP, memory will be initialized in `call_start_cpu0` #if !CONFIG_APP_BUILD_TYPE_RAM bootloader_init_mem(); /* check that static RAM is after the stack */ #ifndef NDEBUG { assert(&_bss_start <= &_bss_end); assert(&_data_start <= &_data_end); } #endif #ifndef __ZEPHYR__ // clear bss section bootloader_clear_bss_section(); #endif /* __ZEPHYR__ */ #endif // !CONFIG_APP_BUILD_TYPE_RAM // init eFuse virtual mode (read eFuses to RAM) #ifdef CONFIG_EFUSE_VIRTUAL ESP_EARLY_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH esp_efuse_init_virtual_mode_in_ram(); #endif #endif // config clock bootloader_clock_configure(); // initialize console, from now on, we can use esp_log bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); #ifndef CONFIG_BOOTLOADER_MCUBOOT spi_flash_init_chip_state(); if ((ret = esp_flash_init_default_chip()) != ESP_OK) { return ret; } #endif #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP // init cache hal cache_hal_init(); //init mmu mmu_hal_init(); // Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader exits with it masked. REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0); // update flash ID bootloader_flash_update_id(); // Check and run XMC startup flow if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { ESP_EARLY_LOGE(TAG, "failed when running XMC startup flow, reboot!"); return ret; } #if !CONFIG_APP_BUILD_TYPE_RAM // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { return ret; } #endif // !CONFIG_APP_BUILD_TYPE_RAM // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { return ret; } #endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); return ret; }