/** * \file * * \brief Peripheral I/O description for SAM4LC8C * * Copyright (c) 2016 Atmel Corporation, * a wholly owned subsidiary of Microchip Technology Inc. * * \asf_license_start * * \page License * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the Licence at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * \asf_license_stop * */ #ifndef _SAM4LC8C_PIO_ #define _SAM4LC8C_PIO_ #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ #define GPIO_PA00 _UL_(1 << 0) /**< \brief GPIO Mask for PA00 */ #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ #define GPIO_PA01 _UL_(1 << 1) /**< \brief GPIO Mask for PA01 */ #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ #define GPIO_PA02 _UL_(1 << 2) /**< \brief GPIO Mask for PA02 */ #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ #define GPIO_PA03 _UL_(1 << 3) /**< \brief GPIO Mask for PA03 */ #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ #define GPIO_PA04 _UL_(1 << 4) /**< \brief GPIO Mask for PA04 */ #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ #define GPIO_PA05 _UL_(1 << 5) /**< \brief GPIO Mask for PA05 */ #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ #define GPIO_PA06 _UL_(1 << 6) /**< \brief GPIO Mask for PA06 */ #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ #define GPIO_PA07 _UL_(1 << 7) /**< \brief GPIO Mask for PA07 */ #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ #define GPIO_PA08 _UL_(1 << 8) /**< \brief GPIO Mask for PA08 */ #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ #define GPIO_PA09 _UL_(1 << 9) /**< \brief GPIO Mask for PA09 */ #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ #define GPIO_PA10 _UL_(1 << 10) /**< \brief GPIO Mask for PA10 */ #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ #define GPIO_PA11 _UL_(1 << 11) /**< \brief GPIO Mask for PA11 */ #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ #define GPIO_PA12 _UL_(1 << 12) /**< \brief GPIO Mask for PA12 */ #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ #define GPIO_PA13 _UL_(1 << 13) /**< \brief GPIO Mask for PA13 */ #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ #define GPIO_PA14 _UL_(1 << 14) /**< \brief GPIO Mask for PA14 */ #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ #define GPIO_PA15 _UL_(1 << 15) /**< \brief GPIO Mask for PA15 */ #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ #define GPIO_PA16 _UL_(1 << 16) /**< \brief GPIO Mask for PA16 */ #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ #define GPIO_PA17 _UL_(1 << 17) /**< \brief GPIO Mask for PA17 */ #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ #define GPIO_PA18 _UL_(1 << 18) /**< \brief GPIO Mask for PA18 */ #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ #define GPIO_PA19 _UL_(1 << 19) /**< \brief GPIO Mask for PA19 */ #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ #define GPIO_PA20 _UL_(1 << 20) /**< \brief GPIO Mask for PA20 */ #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ #define GPIO_PA21 _UL_(1 << 21) /**< \brief GPIO Mask for PA21 */ #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ #define GPIO_PA22 _UL_(1 << 22) /**< \brief GPIO Mask for PA22 */ #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ #define GPIO_PA23 _UL_(1 << 23) /**< \brief GPIO Mask for PA23 */ #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ #define GPIO_PA24 _UL_(1 << 24) /**< \brief GPIO Mask for PA24 */ #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ #define GPIO_PA25 _UL_(1 << 25) /**< \brief GPIO Mask for PA25 */ #define PIN_PA26 26 /**< \brief Pin Number for PA26 */ #define GPIO_PA26 _UL_(1 << 26) /**< \brief GPIO Mask for PA26 */ #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ #define GPIO_PB00 _UL_(1 << 0) /**< \brief GPIO Mask for PB00 */ #define PIN_PB01 33 /**< \brief Pin Number for PB01 */ #define GPIO_PB01 _UL_(1 << 1) /**< \brief GPIO Mask for PB01 */ #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ #define GPIO_PB02 _UL_(1 << 2) /**< \brief GPIO Mask for PB02 */ #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ #define GPIO_PB03 _UL_(1 << 3) /**< \brief GPIO Mask for PB03 */ #define PIN_PB04 36 /**< \brief Pin Number for PB04 */ #define GPIO_PB04 _UL_(1 << 4) /**< \brief GPIO Mask for PB04 */ #define PIN_PB05 37 /**< \brief Pin Number for PB05 */ #define GPIO_PB05 _UL_(1 << 5) /**< \brief GPIO Mask for PB05 */ #define PIN_PB06 38 /**< \brief Pin Number for PB06 */ #define GPIO_PB06 _UL_(1 << 6) /**< \brief GPIO Mask for PB06 */ #define PIN_PB07 39 /**< \brief Pin Number for PB07 */ #define GPIO_PB07 _UL_(1 << 7) /**< \brief GPIO Mask for PB07 */ #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ #define GPIO_PB08 _UL_(1 << 8) /**< \brief GPIO Mask for PB08 */ #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ #define GPIO_PB09 _UL_(1 << 9) /**< \brief GPIO Mask for PB09 */ #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ #define GPIO_PB10 _UL_(1 << 10) /**< \brief GPIO Mask for PB10 */ #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ #define GPIO_PB11 _UL_(1 << 11) /**< \brief GPIO Mask for PB11 */ #define PIN_PB12 44 /**< \brief Pin Number for PB12 */ #define GPIO_PB12 _UL_(1 << 12) /**< \brief GPIO Mask for PB12 */ #define PIN_PB13 45 /**< \brief Pin Number for PB13 */ #define GPIO_PB13 _UL_(1 << 13) /**< \brief GPIO Mask for PB13 */ #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ #define GPIO_PB14 _UL_(1 << 14) /**< \brief GPIO Mask for PB14 */ #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ #define GPIO_PB15 _UL_(1 << 15) /**< \brief GPIO Mask for PB15 */ #define PIN_PC00 64 /**< \brief Pin Number for PC00 */ #define GPIO_PC00 _UL_(1 << 0) /**< \brief GPIO Mask for PC00 */ #define PIN_PC01 65 /**< \brief Pin Number for PC01 */ #define GPIO_PC01 _UL_(1 << 1) /**< \brief GPIO Mask for PC01 */ #define PIN_PC02 66 /**< \brief Pin Number for PC02 */ #define GPIO_PC02 _UL_(1 << 2) /**< \brief GPIO Mask for PC02 */ #define PIN_PC03 67 /**< \brief Pin Number for PC03 */ #define GPIO_PC03 _UL_(1 << 3) /**< \brief GPIO Mask for PC03 */ #define PIN_PC04 68 /**< \brief Pin Number for PC04 */ #define GPIO_PC04 _UL_(1 << 4) /**< \brief GPIO Mask for PC04 */ #define PIN_PC05 69 /**< \brief Pin Number for PC05 */ #define GPIO_PC05 _UL_(1 << 5) /**< \brief GPIO Mask for PC05 */ #define PIN_PC06 70 /**< \brief Pin Number for PC06 */ #define GPIO_PC06 _UL_(1 << 6) /**< \brief GPIO Mask for PC06 */ #define PIN_PC07 71 /**< \brief Pin Number for PC07 */ #define GPIO_PC07 _UL_(1 << 7) /**< \brief GPIO Mask for PC07 */ #define PIN_PC08 72 /**< \brief Pin Number for PC08 */ #define GPIO_PC08 _UL_(1 << 8) /**< \brief GPIO Mask for PC08 */ #define PIN_PC09 73 /**< \brief Pin Number for PC09 */ #define GPIO_PC09 _UL_(1 << 9) /**< \brief GPIO Mask for PC09 */ #define PIN_PC10 74 /**< \brief Pin Number for PC10 */ #define GPIO_PC10 _UL_(1 << 10) /**< \brief GPIO Mask for PC10 */ #define PIN_PC11 75 /**< \brief Pin Number for PC11 */ #define GPIO_PC11 _UL_(1 << 11) /**< \brief GPIO Mask for PC11 */ #define PIN_PC12 76 /**< \brief Pin Number for PC12 */ #define GPIO_PC12 _UL_(1 << 12) /**< \brief GPIO Mask for PC12 */ #define PIN_PC13 77 /**< \brief Pin Number for PC13 */ #define GPIO_PC13 _UL_(1 << 13) /**< \brief GPIO Mask for PC13 */ #define PIN_PC14 78 /**< \brief Pin Number for PC14 */ #define GPIO_PC14 _UL_(1 << 14) /**< \brief GPIO Mask for PC14 */ #define PIN_PC15 79 /**< \brief Pin Number for PC15 */ #define GPIO_PC15 _UL_(1 << 15) /**< \brief GPIO Mask for PC15 */ #define PIN_PC16 80 /**< \brief Pin Number for PC16 */ #define GPIO_PC16 _UL_(1 << 16) /**< \brief GPIO Mask for PC16 */ #define PIN_PC17 81 /**< \brief Pin Number for PC17 */ #define GPIO_PC17 _UL_(1 << 17) /**< \brief GPIO Mask for PC17 */ #define PIN_PC18 82 /**< \brief Pin Number for PC18 */ #define GPIO_PC18 _UL_(1 << 18) /**< \brief GPIO Mask for PC18 */ #define PIN_PC19 83 /**< \brief Pin Number for PC19 */ #define GPIO_PC19 _UL_(1 << 19) /**< \brief GPIO Mask for PC19 */ #define PIN_PC20 84 /**< \brief Pin Number for PC20 */ #define GPIO_PC20 _UL_(1 << 20) /**< \brief GPIO Mask for PC20 */ #define PIN_PC21 85 /**< \brief Pin Number for PC21 */ #define GPIO_PC21 _UL_(1 << 21) /**< \brief GPIO Mask for PC21 */ #define PIN_PC22 86 /**< \brief Pin Number for PC22 */ #define GPIO_PC22 _UL_(1 << 22) /**< \brief GPIO Mask for PC22 */ #define PIN_PC23 87 /**< \brief Pin Number for PC23 */ #define GPIO_PC23 _UL_(1 << 23) /**< \brief GPIO Mask for PC23 */ #define PIN_PC24 88 /**< \brief Pin Number for PC24 */ #define GPIO_PC24 _UL_(1 << 24) /**< \brief GPIO Mask for PC24 */ #define PIN_PC25 89 /**< \brief Pin Number for PC25 */ #define GPIO_PC25 _UL_(1 << 25) /**< \brief GPIO Mask for PC25 */ #define PIN_PC26 90 /**< \brief Pin Number for PC26 */ #define GPIO_PC26 _UL_(1 << 26) /**< \brief GPIO Mask for PC26 */ #define PIN_PC27 91 /**< \brief Pin Number for PC27 */ #define GPIO_PC27 _UL_(1 << 27) /**< \brief GPIO Mask for PC27 */ #define PIN_PC28 92 /**< \brief Pin Number for PC28 */ #define GPIO_PC28 _UL_(1 << 28) /**< \brief GPIO Mask for PC28 */ #define PIN_PC29 93 /**< \brief Pin Number for PC29 */ #define GPIO_PC29 _UL_(1 << 29) /**< \brief GPIO Mask for PC29 */ #define PIN_PC30 94 /**< \brief Pin Number for PC30 */ #define GPIO_PC30 _UL_(1 << 30) /**< \brief GPIO Mask for PC30 */ #define PIN_PC31 95 /**< \brief Pin Number for PC31 */ #define GPIO_PC31 _UL_(1 << 31) /**< \brief GPIO Mask for PC31 */ /* ========== GPIO definition for TWIMS0 peripheral ========== */ #define PIN_PA24B_TWIMS0_TWCK _L_(24) /**< \brief TWIMS0 signal: TWCK on PA24 mux B */ #define MUX_PA24B_TWIMS0_TWCK _L_(1) #define PINMUX_PA24B_TWIMS0_TWCK ((PIN_PA24B_TWIMS0_TWCK << 16) | MUX_PA24B_TWIMS0_TWCK) #define GPIO_PA24B_TWIMS0_TWCK _UL_(1 << 24) #define PIN_PA23B_TWIMS0_TWD _L_(23) /**< \brief TWIMS0 signal: TWD on PA23 mux B */ #define MUX_PA23B_TWIMS0_TWD _L_(1) #define PINMUX_PA23B_TWIMS0_TWD ((PIN_PA23B_TWIMS0_TWD << 16) | MUX_PA23B_TWIMS0_TWD) #define GPIO_PA23B_TWIMS0_TWD _UL_(1 << 23) /* ========== GPIO definition for TWIMS1 peripheral ========== */ #define PIN_PB01A_TWIMS1_TWCK _L_(33) /**< \brief TWIMS1 signal: TWCK on PB01 mux A */ #define MUX_PB01A_TWIMS1_TWCK _L_(0) #define PINMUX_PB01A_TWIMS1_TWCK ((PIN_PB01A_TWIMS1_TWCK << 16) | MUX_PB01A_TWIMS1_TWCK) #define GPIO_PB01A_TWIMS1_TWCK _UL_(1 << 1) #define PIN_PB00A_TWIMS1_TWD _L_(32) /**< \brief TWIMS1 signal: TWD on PB00 mux A */ #define MUX_PB00A_TWIMS1_TWD _L_(0) #define PINMUX_PB00A_TWIMS1_TWD ((PIN_PB00A_TWIMS1_TWD << 16) | MUX_PB00A_TWIMS1_TWD) #define GPIO_PB00A_TWIMS1_TWD _UL_(1 << 0) /* ========== GPIO definition for TWIMS2 peripheral ========== */ #define PIN_PA22E_TWIMS2_TWCK _L_(22) /**< \brief TWIMS2 signal: TWCK on PA22 mux E */ #define MUX_PA22E_TWIMS2_TWCK _L_(4) #define PINMUX_PA22E_TWIMS2_TWCK ((PIN_PA22E_TWIMS2_TWCK << 16) | MUX_PA22E_TWIMS2_TWCK) #define GPIO_PA22E_TWIMS2_TWCK _UL_(1 << 22) #define PIN_PA21E_TWIMS2_TWD _L_(21) /**< \brief TWIMS2 signal: TWD on PA21 mux E */ #define MUX_PA21E_TWIMS2_TWD _L_(4) #define PINMUX_PA21E_TWIMS2_TWD ((PIN_PA21E_TWIMS2_TWD << 16) | MUX_PA21E_TWIMS2_TWD) #define GPIO_PA21E_TWIMS2_TWD _UL_(1 << 21) /* ========== GPIO definition for TWIMS3 peripheral ========== */ #define PIN_PB15C_TWIMS3_TWCK _L_(47) /**< \brief TWIMS3 signal: TWCK on PB15 mux C */ #define MUX_PB15C_TWIMS3_TWCK _L_(2) #define PINMUX_PB15C_TWIMS3_TWCK ((PIN_PB15C_TWIMS3_TWCK << 16) | MUX_PB15C_TWIMS3_TWCK) #define GPIO_PB15C_TWIMS3_TWCK _UL_(1 << 15) #define PIN_PB14C_TWIMS3_TWD _L_(46) /**< \brief TWIMS3 signal: TWD on PB14 mux C */ #define MUX_PB14C_TWIMS3_TWD _L_(2) #define PINMUX_PB14C_TWIMS3_TWD ((PIN_PB14C_TWIMS3_TWD << 16) | MUX_PB14C_TWIMS3_TWD) #define GPIO_PB14C_TWIMS3_TWD _UL_(1 << 14) /* ========== GPIO definition for IISC peripheral ========== */ #define PIN_PB05D_IISC_IMCK _L_(37) /**< \brief IISC signal: IMCK on PB05 mux D */ #define MUX_PB05D_IISC_IMCK _L_(3) #define PINMUX_PB05D_IISC_IMCK ((PIN_PB05D_IISC_IMCK << 16) | MUX_PB05D_IISC_IMCK) #define GPIO_PB05D_IISC_IMCK _UL_(1 << 5) #define PIN_PC14D_IISC_IMCK _L_(78) /**< \brief IISC signal: IMCK on PC14 mux D */ #define MUX_PC14D_IISC_IMCK _L_(3) #define PINMUX_PC14D_IISC_IMCK ((PIN_PC14D_IISC_IMCK << 16) | MUX_PC14D_IISC_IMCK) #define GPIO_PC14D_IISC_IMCK _UL_(1 << 14) #define PIN_PB02D_IISC_ISCK _L_(34) /**< \brief IISC signal: ISCK on PB02 mux D */ #define MUX_PB02D_IISC_ISCK _L_(3) #define PINMUX_PB02D_IISC_ISCK ((PIN_PB02D_IISC_ISCK << 16) | MUX_PB02D_IISC_ISCK) #define GPIO_PB02D_IISC_ISCK _UL_(1 << 2) #define PIN_PC09D_IISC_ISCK _L_(73) /**< \brief IISC signal: ISCK on PC09 mux D */ #define MUX_PC09D_IISC_ISCK _L_(3) #define PINMUX_PC09D_IISC_ISCK ((PIN_PC09D_IISC_ISCK << 16) | MUX_PC09D_IISC_ISCK) #define GPIO_PC09D_IISC_ISCK _UL_(1 << 9) #define PIN_PB03D_IISC_ISDI _L_(35) /**< \brief IISC signal: ISDI on PB03 mux D */ #define MUX_PB03D_IISC_ISDI _L_(3) #define PINMUX_PB03D_IISC_ISDI ((PIN_PB03D_IISC_ISDI << 16) | MUX_PB03D_IISC_ISDI) #define GPIO_PB03D_IISC_ISDI _UL_(1 << 3) #define PIN_PC10D_IISC_ISDI _L_(74) /**< \brief IISC signal: ISDI on PC10 mux D */ #define MUX_PC10D_IISC_ISDI _L_(3) #define PINMUX_PC10D_IISC_ISDI ((PIN_PC10D_IISC_ISDI << 16) | MUX_PC10D_IISC_ISDI) #define GPIO_PC10D_IISC_ISDI _UL_(1 << 10) #define PIN_PB04D_IISC_ISDO _L_(36) /**< \brief IISC signal: ISDO on PB04 mux D */ #define MUX_PB04D_IISC_ISDO _L_(3) #define PINMUX_PB04D_IISC_ISDO ((PIN_PB04D_IISC_ISDO << 16) | MUX_PB04D_IISC_ISDO) #define GPIO_PB04D_IISC_ISDO _UL_(1 << 4) #define PIN_PC13D_IISC_ISDO _L_(77) /**< \brief IISC signal: ISDO on PC13 mux D */ #define MUX_PC13D_IISC_ISDO _L_(3) #define PINMUX_PC13D_IISC_ISDO ((PIN_PC13D_IISC_ISDO << 16) | MUX_PC13D_IISC_ISDO) #define GPIO_PC13D_IISC_ISDO _UL_(1 << 13) #define PIN_PB06D_IISC_IWS _L_(38) /**< \brief IISC signal: IWS on PB06 mux D */ #define MUX_PB06D_IISC_IWS _L_(3) #define PINMUX_PB06D_IISC_IWS ((PIN_PB06D_IISC_IWS << 16) | MUX_PB06D_IISC_IWS) #define GPIO_PB06D_IISC_IWS _UL_(1 << 6) #define PIN_PC12D_IISC_IWS _L_(76) /**< \brief IISC signal: IWS on PC12 mux D */ #define MUX_PC12D_IISC_IWS _L_(3) #define PINMUX_PC12D_IISC_IWS ((PIN_PC12D_IISC_IWS << 16) | MUX_PC12D_IISC_IWS) #define GPIO_PC12D_IISC_IWS _UL_(1 << 12) /* ========== GPIO definition for SPI peripheral ========== */ #define PIN_PA03B_SPI_MISO _L_(3) /**< \brief SPI signal: MISO on PA03 mux B */ #define MUX_PA03B_SPI_MISO _L_(1) #define PINMUX_PA03B_SPI_MISO ((PIN_PA03B_SPI_MISO << 16) | MUX_PA03B_SPI_MISO) #define GPIO_PA03B_SPI_MISO _UL_(1 << 3) #define PIN_PB14B_SPI_MISO _L_(46) /**< \brief SPI signal: MISO on PB14 mux B */ #define MUX_PB14B_SPI_MISO _L_(1) #define PINMUX_PB14B_SPI_MISO ((PIN_PB14B_SPI_MISO << 16) | MUX_PB14B_SPI_MISO) #define GPIO_PB14B_SPI_MISO _UL_(1 << 14) #define PIN_PC28B_SPI_MISO _L_(92) /**< \brief SPI signal: MISO on PC28 mux B */ #define MUX_PC28B_SPI_MISO _L_(1) #define PINMUX_PC28B_SPI_MISO ((PIN_PC28B_SPI_MISO << 16) | MUX_PC28B_SPI_MISO) #define GPIO_PC28B_SPI_MISO _UL_(1 << 28) #define PIN_PA21A_SPI_MISO _L_(21) /**< \brief SPI signal: MISO on PA21 mux A */ #define MUX_PA21A_SPI_MISO _L_(0) #define PINMUX_PA21A_SPI_MISO ((PIN_PA21A_SPI_MISO << 16) | MUX_PA21A_SPI_MISO) #define GPIO_PA21A_SPI_MISO _UL_(1 << 21) #define PIN_PC04A_SPI_MISO _L_(68) /**< \brief SPI signal: MISO on PC04 mux A */ #define MUX_PC04A_SPI_MISO _L_(0) #define PINMUX_PC04A_SPI_MISO ((PIN_PC04A_SPI_MISO << 16) | MUX_PC04A_SPI_MISO) #define GPIO_PC04A_SPI_MISO _UL_(1 << 4) #define PIN_PB15B_SPI_MOSI _L_(47) /**< \brief SPI signal: MOSI on PB15 mux B */ #define MUX_PB15B_SPI_MOSI _L_(1) #define PINMUX_PB15B_SPI_MOSI ((PIN_PB15B_SPI_MOSI << 16) | MUX_PB15B_SPI_MOSI) #define GPIO_PB15B_SPI_MOSI _UL_(1 << 15) #define PIN_PC29B_SPI_MOSI _L_(93) /**< \brief SPI signal: MOSI on PC29 mux B */ #define MUX_PC29B_SPI_MOSI _L_(1) #define PINMUX_PC29B_SPI_MOSI ((PIN_PC29B_SPI_MOSI << 16) | MUX_PC29B_SPI_MOSI) #define GPIO_PC29B_SPI_MOSI _UL_(1 << 29) #define PIN_PA22A_SPI_MOSI _L_(22) /**< \brief SPI signal: MOSI on PA22 mux A */ #define MUX_PA22A_SPI_MOSI _L_(0) #define PINMUX_PA22A_SPI_MOSI ((PIN_PA22A_SPI_MOSI << 16) | MUX_PA22A_SPI_MOSI) #define GPIO_PA22A_SPI_MOSI _UL_(1 << 22) #define PIN_PC05A_SPI_MOSI _L_(69) /**< \brief SPI signal: MOSI on PC05 mux A */ #define MUX_PC05A_SPI_MOSI _L_(0) #define PINMUX_PC05A_SPI_MOSI ((PIN_PC05A_SPI_MOSI << 16) | MUX_PC05A_SPI_MOSI) #define GPIO_PC05A_SPI_MOSI _UL_(1 << 5) #define PIN_PA02B_SPI_NPCS0 _L_(2) /**< \brief SPI signal: NPCS0 on PA02 mux B */ #define MUX_PA02B_SPI_NPCS0 _L_(1) #define PINMUX_PA02B_SPI_NPCS0 ((PIN_PA02B_SPI_NPCS0 << 16) | MUX_PA02B_SPI_NPCS0) #define GPIO_PA02B_SPI_NPCS0 _UL_(1 << 2) #define PIN_PC31B_SPI_NPCS0 _L_(95) /**< \brief SPI signal: NPCS0 on PC31 mux B */ #define MUX_PC31B_SPI_NPCS0 _L_(1) #define PINMUX_PC31B_SPI_NPCS0 ((PIN_PC31B_SPI_NPCS0 << 16) | MUX_PC31B_SPI_NPCS0) #define GPIO_PC31B_SPI_NPCS0 _UL_(1 << 31) #define PIN_PA24A_SPI_NPCS0 _L_(24) /**< \brief SPI signal: NPCS0 on PA24 mux A */ #define MUX_PA24A_SPI_NPCS0 _L_(0) #define PINMUX_PA24A_SPI_NPCS0 ((PIN_PA24A_SPI_NPCS0 << 16) | MUX_PA24A_SPI_NPCS0) #define GPIO_PA24A_SPI_NPCS0 _UL_(1 << 24) #define PIN_PC03A_SPI_NPCS0 _L_(67) /**< \brief SPI signal: NPCS0 on PC03 mux A */ #define MUX_PC03A_SPI_NPCS0 _L_(0) #define PINMUX_PC03A_SPI_NPCS0 ((PIN_PC03A_SPI_NPCS0 << 16) | MUX_PC03A_SPI_NPCS0) #define GPIO_PC03A_SPI_NPCS0 _UL_(1 << 3) #define PIN_PA13C_SPI_NPCS1 _L_(13) /**< \brief SPI signal: NPCS1 on PA13 mux C */ #define MUX_PA13C_SPI_NPCS1 _L_(2) #define PINMUX_PA13C_SPI_NPCS1 ((PIN_PA13C_SPI_NPCS1 << 16) | MUX_PA13C_SPI_NPCS1) #define GPIO_PA13C_SPI_NPCS1 _UL_(1 << 13) #define PIN_PB13B_SPI_NPCS1 _L_(45) /**< \brief SPI signal: NPCS1 on PB13 mux B */ #define MUX_PB13B_SPI_NPCS1 _L_(1) #define PINMUX_PB13B_SPI_NPCS1 ((PIN_PB13B_SPI_NPCS1 << 16) | MUX_PB13B_SPI_NPCS1) #define GPIO_PB13B_SPI_NPCS1 _UL_(1 << 13) #define PIN_PC02A_SPI_NPCS1 _L_(66) /**< \brief SPI signal: NPCS1 on PC02 mux A */ #define MUX_PC02A_SPI_NPCS1 _L_(0) #define PINMUX_PC02A_SPI_NPCS1 ((PIN_PC02A_SPI_NPCS1 << 16) | MUX_PC02A_SPI_NPCS1) #define GPIO_PC02A_SPI_NPCS1 _UL_(1 << 2) #define PIN_PA14C_SPI_NPCS2 _L_(14) /**< \brief SPI signal: NPCS2 on PA14 mux C */ #define MUX_PA14C_SPI_NPCS2 _L_(2) #define PINMUX_PA14C_SPI_NPCS2 ((PIN_PA14C_SPI_NPCS2 << 16) | MUX_PA14C_SPI_NPCS2) #define GPIO_PA14C_SPI_NPCS2 _UL_(1 << 14) #define PIN_PB11B_SPI_NPCS2 _L_(43) /**< \brief SPI signal: NPCS2 on PB11 mux B */ #define MUX_PB11B_SPI_NPCS2 _L_(1) #define PINMUX_PB11B_SPI_NPCS2 ((PIN_PB11B_SPI_NPCS2 << 16) | MUX_PB11B_SPI_NPCS2) #define GPIO_PB11B_SPI_NPCS2 _UL_(1 << 11) #define PIN_PC00A_SPI_NPCS2 _L_(64) /**< \brief SPI signal: NPCS2 on PC00 mux A */ #define MUX_PC00A_SPI_NPCS2 _L_(0) #define PINMUX_PC00A_SPI_NPCS2 ((PIN_PC00A_SPI_NPCS2 << 16) | MUX_PC00A_SPI_NPCS2) #define GPIO_PC00A_SPI_NPCS2 _UL_(1 << 0) #define PIN_PA15C_SPI_NPCS3 _L_(15) /**< \brief SPI signal: NPCS3 on PA15 mux C */ #define MUX_PA15C_SPI_NPCS3 _L_(2) #define PINMUX_PA15C_SPI_NPCS3 ((PIN_PA15C_SPI_NPCS3 << 16) | MUX_PA15C_SPI_NPCS3) #define GPIO_PA15C_SPI_NPCS3 _UL_(1 << 15) #define PIN_PB12B_SPI_NPCS3 _L_(44) /**< \brief SPI signal: NPCS3 on PB12 mux B */ #define MUX_PB12B_SPI_NPCS3 _L_(1) #define PINMUX_PB12B_SPI_NPCS3 ((PIN_PB12B_SPI_NPCS3 << 16) | MUX_PB12B_SPI_NPCS3) #define GPIO_PB12B_SPI_NPCS3 _UL_(1 << 12) #define PIN_PC01A_SPI_NPCS3 _L_(65) /**< \brief SPI signal: NPCS3 on PC01 mux A */ #define MUX_PC01A_SPI_NPCS3 _L_(0) #define PINMUX_PC01A_SPI_NPCS3 ((PIN_PC01A_SPI_NPCS3 << 16) | MUX_PC01A_SPI_NPCS3) #define GPIO_PC01A_SPI_NPCS3 _UL_(1 << 1) #define PIN_PC30B_SPI_SCK _L_(94) /**< \brief SPI signal: SCK on PC30 mux B */ #define MUX_PC30B_SPI_SCK _L_(1) #define PINMUX_PC30B_SPI_SCK ((PIN_PC30B_SPI_SCK << 16) | MUX_PC30B_SPI_SCK) #define GPIO_PC30B_SPI_SCK _UL_(1 << 30) #define PIN_PA23A_SPI_SCK _L_(23) /**< \brief SPI signal: SCK on PA23 mux A */ #define MUX_PA23A_SPI_SCK _L_(0) #define PINMUX_PA23A_SPI_SCK ((PIN_PA23A_SPI_SCK << 16) | MUX_PA23A_SPI_SCK) #define GPIO_PA23A_SPI_SCK _UL_(1 << 23) #define PIN_PC06A_SPI_SCK _L_(70) /**< \brief SPI signal: SCK on PC06 mux A */ #define MUX_PC06A_SPI_SCK _L_(0) #define PINMUX_PC06A_SPI_SCK ((PIN_PC06A_SPI_SCK << 16) | MUX_PC06A_SPI_SCK) #define GPIO_PC06A_SPI_SCK _UL_(1 << 6) /* ========== GPIO definition for TC0 peripheral ========== */ #define PIN_PB07D_TC0_A0 _L_(39) /**< \brief TC0 signal: A0 on PB07 mux D */ #define MUX_PB07D_TC0_A0 _L_(3) #define PINMUX_PB07D_TC0_A0 ((PIN_PB07D_TC0_A0 << 16) | MUX_PB07D_TC0_A0) #define GPIO_PB07D_TC0_A0 _UL_(1 << 7) #define PIN_PA08B_TC0_A0 _L_(8) /**< \brief TC0 signal: A0 on PA08 mux B */ #define MUX_PA08B_TC0_A0 _L_(1) #define PINMUX_PA08B_TC0_A0 ((PIN_PA08B_TC0_A0 << 16) | MUX_PA08B_TC0_A0) #define GPIO_PA08B_TC0_A0 _UL_(1 << 8) #define PIN_PB09D_TC0_A1 _L_(41) /**< \brief TC0 signal: A1 on PB09 mux D */ #define MUX_PB09D_TC0_A1 _L_(3) #define PINMUX_PB09D_TC0_A1 ((PIN_PB09D_TC0_A1 << 16) | MUX_PB09D_TC0_A1) #define GPIO_PB09D_TC0_A1 _UL_(1 << 9) #define PIN_PA10B_TC0_A1 _L_(10) /**< \brief TC0 signal: A1 on PA10 mux B */ #define MUX_PA10B_TC0_A1 _L_(1) #define PINMUX_PA10B_TC0_A1 ((PIN_PA10B_TC0_A1 << 16) | MUX_PA10B_TC0_A1) #define GPIO_PA10B_TC0_A1 _UL_(1 << 10) #define PIN_PB11D_TC0_A2 _L_(43) /**< \brief TC0 signal: A2 on PB11 mux D */ #define MUX_PB11D_TC0_A2 _L_(3) #define PINMUX_PB11D_TC0_A2 ((PIN_PB11D_TC0_A2 << 16) | MUX_PB11D_TC0_A2) #define GPIO_PB11D_TC0_A2 _UL_(1 << 11) #define PIN_PA12B_TC0_A2 _L_(12) /**< \brief TC0 signal: A2 on PA12 mux B */ #define MUX_PA12B_TC0_A2 _L_(1) #define PINMUX_PA12B_TC0_A2 ((PIN_PA12B_TC0_A2 << 16) | MUX_PA12B_TC0_A2) #define GPIO_PA12B_TC0_A2 _UL_(1 << 12) #define PIN_PB08D_TC0_B0 _L_(40) /**< \brief TC0 signal: B0 on PB08 mux D */ #define MUX_PB08D_TC0_B0 _L_(3) #define PINMUX_PB08D_TC0_B0 ((PIN_PB08D_TC0_B0 << 16) | MUX_PB08D_TC0_B0) #define GPIO_PB08D_TC0_B0 _UL_(1 << 8) #define PIN_PA09B_TC0_B0 _L_(9) /**< \brief TC0 signal: B0 on PA09 mux B */ #define MUX_PA09B_TC0_B0 _L_(1) #define PINMUX_PA09B_TC0_B0 ((PIN_PA09B_TC0_B0 << 16) | MUX_PA09B_TC0_B0) #define GPIO_PA09B_TC0_B0 _UL_(1 << 9) #define PIN_PB10D_TC0_B1 _L_(42) /**< \brief TC0 signal: B1 on PB10 mux D */ #define MUX_PB10D_TC0_B1 _L_(3) #define PINMUX_PB10D_TC0_B1 ((PIN_PB10D_TC0_B1 << 16) | MUX_PB10D_TC0_B1) #define GPIO_PB10D_TC0_B1 _UL_(1 << 10) #define PIN_PA11B_TC0_B1 _L_(11) /**< \brief TC0 signal: B1 on PA11 mux B */ #define MUX_PA11B_TC0_B1 _L_(1) #define PINMUX_PA11B_TC0_B1 ((PIN_PA11B_TC0_B1 << 16) | MUX_PA11B_TC0_B1) #define GPIO_PA11B_TC0_B1 _UL_(1 << 11) #define PIN_PB12D_TC0_B2 _L_(44) /**< \brief TC0 signal: B2 on PB12 mux D */ #define MUX_PB12D_TC0_B2 _L_(3) #define PINMUX_PB12D_TC0_B2 ((PIN_PB12D_TC0_B2 << 16) | MUX_PB12D_TC0_B2) #define GPIO_PB12D_TC0_B2 _UL_(1 << 12) #define PIN_PA13B_TC0_B2 _L_(13) /**< \brief TC0 signal: B2 on PA13 mux B */ #define MUX_PA13B_TC0_B2 _L_(1) #define PINMUX_PA13B_TC0_B2 ((PIN_PA13B_TC0_B2 << 16) | MUX_PA13B_TC0_B2) #define GPIO_PA13B_TC0_B2 _UL_(1 << 13) #define PIN_PB13D_TC0_CLK0 _L_(45) /**< \brief TC0 signal: CLK0 on PB13 mux D */ #define MUX_PB13D_TC0_CLK0 _L_(3) #define PINMUX_PB13D_TC0_CLK0 ((PIN_PB13D_TC0_CLK0 << 16) | MUX_PB13D_TC0_CLK0) #define GPIO_PB13D_TC0_CLK0 _UL_(1 << 13) #define PIN_PA14B_TC0_CLK0 _L_(14) /**< \brief TC0 signal: CLK0 on PA14 mux B */ #define MUX_PA14B_TC0_CLK0 _L_(1) #define PINMUX_PA14B_TC0_CLK0 ((PIN_PA14B_TC0_CLK0 << 16) | MUX_PA14B_TC0_CLK0) #define GPIO_PA14B_TC0_CLK0 _UL_(1 << 14) #define PIN_PB14D_TC0_CLK1 _L_(46) /**< \brief TC0 signal: CLK1 on PB14 mux D */ #define MUX_PB14D_TC0_CLK1 _L_(3) #define PINMUX_PB14D_TC0_CLK1 ((PIN_PB14D_TC0_CLK1 << 16) | MUX_PB14D_TC0_CLK1) #define GPIO_PB14D_TC0_CLK1 _UL_(1 << 14) #define PIN_PA15B_TC0_CLK1 _L_(15) /**< \brief TC0 signal: CLK1 on PA15 mux B */ #define MUX_PA15B_TC0_CLK1 _L_(1) #define PINMUX_PA15B_TC0_CLK1 ((PIN_PA15B_TC0_CLK1 << 16) | MUX_PA15B_TC0_CLK1) #define GPIO_PA15B_TC0_CLK1 _UL_(1 << 15) #define PIN_PB15D_TC0_CLK2 _L_(47) /**< \brief TC0 signal: CLK2 on PB15 mux D */ #define MUX_PB15D_TC0_CLK2 _L_(3) #define PINMUX_PB15D_TC0_CLK2 ((PIN_PB15D_TC0_CLK2 << 16) | MUX_PB15D_TC0_CLK2) #define GPIO_PB15D_TC0_CLK2 _UL_(1 << 15) #define PIN_PA16B_TC0_CLK2 _L_(16) /**< \brief TC0 signal: CLK2 on PA16 mux B */ #define MUX_PA16B_TC0_CLK2 _L_(1) #define PINMUX_PA16B_TC0_CLK2 ((PIN_PA16B_TC0_CLK2 << 16) | MUX_PA16B_TC0_CLK2) #define GPIO_PA16B_TC0_CLK2 _UL_(1 << 16) /* ========== GPIO definition for TC1 peripheral ========== */ #define PIN_PC00D_TC1_A0 _L_(64) /**< \brief TC1 signal: A0 on PC00 mux D */ #define MUX_PC00D_TC1_A0 _L_(3) #define PINMUX_PC00D_TC1_A0 ((PIN_PC00D_TC1_A0 << 16) | MUX_PC00D_TC1_A0) #define GPIO_PC00D_TC1_A0 _UL_(1 << 0) #define PIN_PC15A_TC1_A0 _L_(79) /**< \brief TC1 signal: A0 on PC15 mux A */ #define MUX_PC15A_TC1_A0 _L_(0) #define PINMUX_PC15A_TC1_A0 ((PIN_PC15A_TC1_A0 << 16) | MUX_PC15A_TC1_A0) #define GPIO_PC15A_TC1_A0 _UL_(1 << 15) #define PIN_PC02D_TC1_A1 _L_(66) /**< \brief TC1 signal: A1 on PC02 mux D */ #define MUX_PC02D_TC1_A1 _L_(3) #define PINMUX_PC02D_TC1_A1 ((PIN_PC02D_TC1_A1 << 16) | MUX_PC02D_TC1_A1) #define GPIO_PC02D_TC1_A1 _UL_(1 << 2) #define PIN_PC17A_TC1_A1 _L_(81) /**< \brief TC1 signal: A1 on PC17 mux A */ #define MUX_PC17A_TC1_A1 _L_(0) #define PINMUX_PC17A_TC1_A1 ((PIN_PC17A_TC1_A1 << 16) | MUX_PC17A_TC1_A1) #define GPIO_PC17A_TC1_A1 _UL_(1 << 17) #define PIN_PC04D_TC1_A2 _L_(68) /**< \brief TC1 signal: A2 on PC04 mux D */ #define MUX_PC04D_TC1_A2 _L_(3) #define PINMUX_PC04D_TC1_A2 ((PIN_PC04D_TC1_A2 << 16) | MUX_PC04D_TC1_A2) #define GPIO_PC04D_TC1_A2 _UL_(1 << 4) #define PIN_PC19A_TC1_A2 _L_(83) /**< \brief TC1 signal: A2 on PC19 mux A */ #define MUX_PC19A_TC1_A2 _L_(0) #define PINMUX_PC19A_TC1_A2 ((PIN_PC19A_TC1_A2 << 16) | MUX_PC19A_TC1_A2) #define GPIO_PC19A_TC1_A2 _UL_(1 << 19) #define PIN_PC01D_TC1_B0 _L_(65) /**< \brief TC1 signal: B0 on PC01 mux D */ #define MUX_PC01D_TC1_B0 _L_(3) #define PINMUX_PC01D_TC1_B0 ((PIN_PC01D_TC1_B0 << 16) | MUX_PC01D_TC1_B0) #define GPIO_PC01D_TC1_B0 _UL_(1 << 1) #define PIN_PC16A_TC1_B0 _L_(80) /**< \brief TC1 signal: B0 on PC16 mux A */ #define MUX_PC16A_TC1_B0 _L_(0) #define PINMUX_PC16A_TC1_B0 ((PIN_PC16A_TC1_B0 << 16) | MUX_PC16A_TC1_B0) #define GPIO_PC16A_TC1_B0 _UL_(1 << 16) #define PIN_PC03D_TC1_B1 _L_(67) /**< \brief TC1 signal: B1 on PC03 mux D */ #define MUX_PC03D_TC1_B1 _L_(3) #define PINMUX_PC03D_TC1_B1 ((PIN_PC03D_TC1_B1 << 16) | MUX_PC03D_TC1_B1) #define GPIO_PC03D_TC1_B1 _UL_(1 << 3) #define PIN_PC18A_TC1_B1 _L_(82) /**< \brief TC1 signal: B1 on PC18 mux A */ #define MUX_PC18A_TC1_B1 _L_(0) #define PINMUX_PC18A_TC1_B1 ((PIN_PC18A_TC1_B1 << 16) | MUX_PC18A_TC1_B1) #define GPIO_PC18A_TC1_B1 _UL_(1 << 18) #define PIN_PC05D_TC1_B2 _L_(69) /**< \brief TC1 signal: B2 on PC05 mux D */ #define MUX_PC05D_TC1_B2 _L_(3) #define PINMUX_PC05D_TC1_B2 ((PIN_PC05D_TC1_B2 << 16) | MUX_PC05D_TC1_B2) #define GPIO_PC05D_TC1_B2 _UL_(1 << 5) #define PIN_PC20A_TC1_B2 _L_(84) /**< \brief TC1 signal: B2 on PC20 mux A */ #define MUX_PC20A_TC1_B2 _L_(0) #define PINMUX_PC20A_TC1_B2 ((PIN_PC20A_TC1_B2 << 16) | MUX_PC20A_TC1_B2) #define GPIO_PC20A_TC1_B2 _UL_(1 << 20) #define PIN_PC06D_TC1_CLK0 _L_(70) /**< \brief TC1 signal: CLK0 on PC06 mux D */ #define MUX_PC06D_TC1_CLK0 _L_(3) #define PINMUX_PC06D_TC1_CLK0 ((PIN_PC06D_TC1_CLK0 << 16) | MUX_PC06D_TC1_CLK0) #define GPIO_PC06D_TC1_CLK0 _UL_(1 << 6) #define PIN_PC21A_TC1_CLK0 _L_(85) /**< \brief TC1 signal: CLK0 on PC21 mux A */ #define MUX_PC21A_TC1_CLK0 _L_(0) #define PINMUX_PC21A_TC1_CLK0 ((PIN_PC21A_TC1_CLK0 << 16) | MUX_PC21A_TC1_CLK0) #define GPIO_PC21A_TC1_CLK0 _UL_(1 << 21) #define PIN_PC07D_TC1_CLK1 _L_(71) /**< \brief TC1 signal: CLK1 on PC07 mux D */ #define MUX_PC07D_TC1_CLK1 _L_(3) #define PINMUX_PC07D_TC1_CLK1 ((PIN_PC07D_TC1_CLK1 << 16) | MUX_PC07D_TC1_CLK1) #define GPIO_PC07D_TC1_CLK1 _UL_(1 << 7) #define PIN_PC22A_TC1_CLK1 _L_(86) /**< \brief TC1 signal: CLK1 on PC22 mux A */ #define MUX_PC22A_TC1_CLK1 _L_(0) #define PINMUX_PC22A_TC1_CLK1 ((PIN_PC22A_TC1_CLK1 << 16) | MUX_PC22A_TC1_CLK1) #define GPIO_PC22A_TC1_CLK1 _UL_(1 << 22) #define PIN_PC08D_TC1_CLK2 _L_(72) /**< \brief TC1 signal: CLK2 on PC08 mux D */ #define MUX_PC08D_TC1_CLK2 _L_(3) #define PINMUX_PC08D_TC1_CLK2 ((PIN_PC08D_TC1_CLK2 << 16) | MUX_PC08D_TC1_CLK2) #define GPIO_PC08D_TC1_CLK2 _UL_(1 << 8) #define PIN_PC23A_TC1_CLK2 _L_(87) /**< \brief TC1 signal: CLK2 on PC23 mux A */ #define MUX_PC23A_TC1_CLK2 _L_(0) #define PINMUX_PC23A_TC1_CLK2 ((PIN_PC23A_TC1_CLK2 << 16) | MUX_PC23A_TC1_CLK2) #define GPIO_PC23A_TC1_CLK2 _UL_(1 << 23) /* ========== GPIO definition for USART0 peripheral ========== */ #define PIN_PA04B_USART0_CLK _L_(4) /**< \brief USART0 signal: CLK on PA04 mux B */ #define MUX_PA04B_USART0_CLK _L_(1) #define PINMUX_PA04B_USART0_CLK ((PIN_PA04B_USART0_CLK << 16) | MUX_PA04B_USART0_CLK) #define GPIO_PA04B_USART0_CLK _UL_(1 << 4) #define PIN_PC00B_USART0_CLK _L_(64) /**< \brief USART0 signal: CLK on PC00 mux B */ #define MUX_PC00B_USART0_CLK _L_(1) #define PINMUX_PC00B_USART0_CLK ((PIN_PC00B_USART0_CLK << 16) | MUX_PC00B_USART0_CLK) #define GPIO_PC00B_USART0_CLK _UL_(1 << 0) #define PIN_PA10A_USART0_CLK _L_(10) /**< \brief USART0 signal: CLK on PA10 mux A */ #define MUX_PA10A_USART0_CLK _L_(0) #define PINMUX_PA10A_USART0_CLK ((PIN_PA10A_USART0_CLK << 16) | MUX_PA10A_USART0_CLK) #define GPIO_PA10A_USART0_CLK _UL_(1 << 10) #define PIN_PB13A_USART0_CLK _L_(45) /**< \brief USART0 signal: CLK on PB13 mux A */ #define MUX_PB13A_USART0_CLK _L_(0) #define PINMUX_PB13A_USART0_CLK ((PIN_PB13A_USART0_CLK << 16) | MUX_PB13A_USART0_CLK) #define GPIO_PB13A_USART0_CLK _UL_(1 << 13) #define PIN_PC02B_USART0_CTS _L_(66) /**< \brief USART0 signal: CTS on PC02 mux B */ #define MUX_PC02B_USART0_CTS _L_(1) #define PINMUX_PC02B_USART0_CTS ((PIN_PC02B_USART0_CTS << 16) | MUX_PC02B_USART0_CTS) #define GPIO_PC02B_USART0_CTS _UL_(1 << 2) #define PIN_PA09A_USART0_CTS _L_(9) /**< \brief USART0 signal: CTS on PA09 mux A */ #define MUX_PA09A_USART0_CTS _L_(0) #define PINMUX_PA09A_USART0_CTS ((PIN_PA09A_USART0_CTS << 16) | MUX_PA09A_USART0_CTS) #define GPIO_PA09A_USART0_CTS _UL_(1 << 9) #define PIN_PB11A_USART0_CTS _L_(43) /**< \brief USART0 signal: CTS on PB11 mux A */ #define MUX_PB11A_USART0_CTS _L_(0) #define PINMUX_PB11A_USART0_CTS ((PIN_PB11A_USART0_CTS << 16) | MUX_PB11A_USART0_CTS) #define GPIO_PB11A_USART0_CTS _UL_(1 << 11) #define PIN_PA06B_USART0_RTS _L_(6) /**< \brief USART0 signal: RTS on PA06 mux B */ #define MUX_PA06B_USART0_RTS _L_(1) #define PINMUX_PA06B_USART0_RTS ((PIN_PA06B_USART0_RTS << 16) | MUX_PA06B_USART0_RTS) #define GPIO_PA06B_USART0_RTS _UL_(1 << 6) #define PIN_PC01B_USART0_RTS _L_(65) /**< \brief USART0 signal: RTS on PC01 mux B */ #define MUX_PC01B_USART0_RTS _L_(1) #define PINMUX_PC01B_USART0_RTS ((PIN_PC01B_USART0_RTS << 16) | MUX_PC01B_USART0_RTS) #define GPIO_PC01B_USART0_RTS _UL_(1 << 1) #define PIN_PA08A_USART0_RTS _L_(8) /**< \brief USART0 signal: RTS on PA08 mux A */ #define MUX_PA08A_USART0_RTS _L_(0) #define PINMUX_PA08A_USART0_RTS ((PIN_PA08A_USART0_RTS << 16) | MUX_PA08A_USART0_RTS) #define GPIO_PA08A_USART0_RTS _UL_(1 << 8) #define PIN_PB12A_USART0_RTS _L_(44) /**< \brief USART0 signal: RTS on PB12 mux A */ #define MUX_PB12A_USART0_RTS _L_(0) #define PINMUX_PB12A_USART0_RTS ((PIN_PB12A_USART0_RTS << 16) | MUX_PB12A_USART0_RTS) #define GPIO_PB12A_USART0_RTS _UL_(1 << 12) #define PIN_PC02C_USART0_RXD _L_(66) /**< \brief USART0 signal: RXD on PC02 mux C */ #define MUX_PC02C_USART0_RXD _L_(2) #define PINMUX_PC02C_USART0_RXD ((PIN_PC02C_USART0_RXD << 16) | MUX_PC02C_USART0_RXD) #define GPIO_PC02C_USART0_RXD _UL_(1 << 2) #define PIN_PA05B_USART0_RXD _L_(5) /**< \brief USART0 signal: RXD on PA05 mux B */ #define MUX_PA05B_USART0_RXD _L_(1) #define PINMUX_PA05B_USART0_RXD ((PIN_PA05B_USART0_RXD << 16) | MUX_PA05B_USART0_RXD) #define GPIO_PA05B_USART0_RXD _UL_(1 << 5) #define PIN_PB00B_USART0_RXD _L_(32) /**< \brief USART0 signal: RXD on PB00 mux B */ #define MUX_PB00B_USART0_RXD _L_(1) #define PINMUX_PB00B_USART0_RXD ((PIN_PB00B_USART0_RXD << 16) | MUX_PB00B_USART0_RXD) #define GPIO_PB00B_USART0_RXD _UL_(1 << 0) #define PIN_PA11A_USART0_RXD _L_(11) /**< \brief USART0 signal: RXD on PA11 mux A */ #define MUX_PA11A_USART0_RXD _L_(0) #define PINMUX_PA11A_USART0_RXD ((PIN_PA11A_USART0_RXD << 16) | MUX_PA11A_USART0_RXD) #define GPIO_PA11A_USART0_RXD _UL_(1 << 11) #define PIN_PB14A_USART0_RXD _L_(46) /**< \brief USART0 signal: RXD on PB14 mux A */ #define MUX_PB14A_USART0_RXD _L_(0) #define PINMUX_PB14A_USART0_RXD ((PIN_PB14A_USART0_RXD << 16) | MUX_PB14A_USART0_RXD) #define GPIO_PB14A_USART0_RXD _UL_(1 << 14) #define PIN_PC03C_USART0_TXD _L_(67) /**< \brief USART0 signal: TXD on PC03 mux C */ #define MUX_PC03C_USART0_TXD _L_(2) #define PINMUX_PC03C_USART0_TXD ((PIN_PC03C_USART0_TXD << 16) | MUX_PC03C_USART0_TXD) #define GPIO_PC03C_USART0_TXD _UL_(1 << 3) #define PIN_PA07B_USART0_TXD _L_(7) /**< \brief USART0 signal: TXD on PA07 mux B */ #define MUX_PA07B_USART0_TXD _L_(1) #define PINMUX_PA07B_USART0_TXD ((PIN_PA07B_USART0_TXD << 16) | MUX_PA07B_USART0_TXD) #define GPIO_PA07B_USART0_TXD _UL_(1 << 7) #define PIN_PB01B_USART0_TXD _L_(33) /**< \brief USART0 signal: TXD on PB01 mux B */ #define MUX_PB01B_USART0_TXD _L_(1) #define PINMUX_PB01B_USART0_TXD ((PIN_PB01B_USART0_TXD << 16) | MUX_PB01B_USART0_TXD) #define GPIO_PB01B_USART0_TXD _UL_(1 << 1) #define PIN_PA12A_USART0_TXD _L_(12) /**< \brief USART0 signal: TXD on PA12 mux A */ #define MUX_PA12A_USART0_TXD _L_(0) #define PINMUX_PA12A_USART0_TXD ((PIN_PA12A_USART0_TXD << 16) | MUX_PA12A_USART0_TXD) #define GPIO_PA12A_USART0_TXD _UL_(1 << 12) #define PIN_PB15A_USART0_TXD _L_(47) /**< \brief USART0 signal: TXD on PB15 mux A */ #define MUX_PB15A_USART0_TXD _L_(0) #define PINMUX_PB15A_USART0_TXD ((PIN_PB15A_USART0_TXD << 16) | MUX_PB15A_USART0_TXD) #define GPIO_PB15A_USART0_TXD _UL_(1 << 15) /* ========== GPIO definition for USART1 peripheral ========== */ #define PIN_PB03B_USART1_CLK _L_(35) /**< \brief USART1 signal: CLK on PB03 mux B */ #define MUX_PB03B_USART1_CLK _L_(1) #define PINMUX_PB03B_USART1_CLK ((PIN_PB03B_USART1_CLK << 16) | MUX_PB03B_USART1_CLK) #define GPIO_PB03B_USART1_CLK _UL_(1 << 3) #define PIN_PA14A_USART1_CLK _L_(14) /**< \brief USART1 signal: CLK on PA14 mux A */ #define MUX_PA14A_USART1_CLK _L_(0) #define PINMUX_PA14A_USART1_CLK ((PIN_PA14A_USART1_CLK << 16) | MUX_PA14A_USART1_CLK) #define GPIO_PA14A_USART1_CLK _UL_(1 << 14) #define PIN_PC25A_USART1_CLK _L_(89) /**< \brief USART1 signal: CLK on PC25 mux A */ #define MUX_PC25A_USART1_CLK _L_(0) #define PINMUX_PC25A_USART1_CLK ((PIN_PC25A_USART1_CLK << 16) | MUX_PC25A_USART1_CLK) #define GPIO_PC25A_USART1_CLK _UL_(1 << 25) #define PIN_PA21B_USART1_CTS _L_(21) /**< \brief USART1 signal: CTS on PA21 mux B */ #define MUX_PA21B_USART1_CTS _L_(1) #define PINMUX_PA21B_USART1_CTS ((PIN_PA21B_USART1_CTS << 16) | MUX_PA21B_USART1_CTS) #define GPIO_PA21B_USART1_CTS _UL_(1 << 21) #define PIN_PB02B_USART1_RTS _L_(34) /**< \brief USART1 signal: RTS on PB02 mux B */ #define MUX_PB02B_USART1_RTS _L_(1) #define PINMUX_PB02B_USART1_RTS ((PIN_PB02B_USART1_RTS << 16) | MUX_PB02B_USART1_RTS) #define GPIO_PB02B_USART1_RTS _UL_(1 << 2) #define PIN_PA13A_USART1_RTS _L_(13) /**< \brief USART1 signal: RTS on PA13 mux A */ #define MUX_PA13A_USART1_RTS _L_(0) #define PINMUX_PA13A_USART1_RTS ((PIN_PA13A_USART1_RTS << 16) | MUX_PA13A_USART1_RTS) #define GPIO_PA13A_USART1_RTS _UL_(1 << 13) #define PIN_PC24A_USART1_RTS _L_(88) /**< \brief USART1 signal: RTS on PC24 mux A */ #define MUX_PC24A_USART1_RTS _L_(0) #define PINMUX_PC24A_USART1_RTS ((PIN_PC24A_USART1_RTS << 16) | MUX_PC24A_USART1_RTS) #define GPIO_PC24A_USART1_RTS _UL_(1 << 24) #define PIN_PB04B_USART1_RXD _L_(36) /**< \brief USART1 signal: RXD on PB04 mux B */ #define MUX_PB04B_USART1_RXD _L_(1) #define PINMUX_PB04B_USART1_RXD ((PIN_PB04B_USART1_RXD << 16) | MUX_PB04B_USART1_RXD) #define GPIO_PB04B_USART1_RXD _UL_(1 << 4) #define PIN_PA15A_USART1_RXD _L_(15) /**< \brief USART1 signal: RXD on PA15 mux A */ #define MUX_PA15A_USART1_RXD _L_(0) #define PINMUX_PA15A_USART1_RXD ((PIN_PA15A_USART1_RXD << 16) | MUX_PA15A_USART1_RXD) #define GPIO_PA15A_USART1_RXD _UL_(1 << 15) #define PIN_PC26A_USART1_RXD _L_(90) /**< \brief USART1 signal: RXD on PC26 mux A */ #define MUX_PC26A_USART1_RXD _L_(0) #define PINMUX_PC26A_USART1_RXD ((PIN_PC26A_USART1_RXD << 16) | MUX_PC26A_USART1_RXD) #define GPIO_PC26A_USART1_RXD _UL_(1 << 26) #define PIN_PB05B_USART1_TXD _L_(37) /**< \brief USART1 signal: TXD on PB05 mux B */ #define MUX_PB05B_USART1_TXD _L_(1) #define PINMUX_PB05B_USART1_TXD ((PIN_PB05B_USART1_TXD << 16) | MUX_PB05B_USART1_TXD) #define GPIO_PB05B_USART1_TXD _UL_(1 << 5) #define PIN_PA16A_USART1_TXD _L_(16) /**< \brief USART1 signal: TXD on PA16 mux A */ #define MUX_PA16A_USART1_TXD _L_(0) #define PINMUX_PA16A_USART1_TXD ((PIN_PA16A_USART1_TXD << 16) | MUX_PA16A_USART1_TXD) #define GPIO_PA16A_USART1_TXD _UL_(1 << 16) #define PIN_PC27A_USART1_TXD _L_(91) /**< \brief USART1 signal: TXD on PC27 mux A */ #define MUX_PC27A_USART1_TXD _L_(0) #define PINMUX_PC27A_USART1_TXD ((PIN_PC27A_USART1_TXD << 16) | MUX_PC27A_USART1_TXD) #define GPIO_PC27A_USART1_TXD _UL_(1 << 27) /* ========== GPIO definition for USART2 peripheral ========== */ #define PIN_PC08B_USART2_CLK _L_(72) /**< \brief USART2 signal: CLK on PC08 mux B */ #define MUX_PC08B_USART2_CLK _L_(1) #define PINMUX_PC08B_USART2_CLK ((PIN_PC08B_USART2_CLK << 16) | MUX_PC08B_USART2_CLK) #define GPIO_PC08B_USART2_CLK _UL_(1 << 8) #define PIN_PA18A_USART2_CLK _L_(18) /**< \brief USART2 signal: CLK on PA18 mux A */ #define MUX_PA18A_USART2_CLK _L_(0) #define PINMUX_PA18A_USART2_CLK ((PIN_PA18A_USART2_CLK << 16) | MUX_PA18A_USART2_CLK) #define GPIO_PA18A_USART2_CLK _UL_(1 << 18) #define PIN_PC08E_USART2_CTS _L_(72) /**< \brief USART2 signal: CTS on PC08 mux E */ #define MUX_PC08E_USART2_CTS _L_(4) #define PINMUX_PC08E_USART2_CTS ((PIN_PC08E_USART2_CTS << 16) | MUX_PC08E_USART2_CTS) #define GPIO_PC08E_USART2_CTS _UL_(1 << 8) #define PIN_PA22B_USART2_CTS _L_(22) /**< \brief USART2 signal: CTS on PA22 mux B */ #define MUX_PA22B_USART2_CTS _L_(1) #define PINMUX_PA22B_USART2_CTS ((PIN_PA22B_USART2_CTS << 16) | MUX_PA22B_USART2_CTS) #define GPIO_PA22B_USART2_CTS _UL_(1 << 22) #define PIN_PC07B_USART2_RTS _L_(71) /**< \brief USART2 signal: RTS on PC07 mux B */ #define MUX_PC07B_USART2_RTS _L_(1) #define PINMUX_PC07B_USART2_RTS ((PIN_PC07B_USART2_RTS << 16) | MUX_PC07B_USART2_RTS) #define GPIO_PC07B_USART2_RTS _UL_(1 << 7) #define PIN_PA17A_USART2_RTS _L_(17) /**< \brief USART2 signal: RTS on PA17 mux A */ #define MUX_PA17A_USART2_RTS _L_(0) #define PINMUX_PA17A_USART2_RTS ((PIN_PA17A_USART2_RTS << 16) | MUX_PA17A_USART2_RTS) #define GPIO_PA17A_USART2_RTS _UL_(1 << 17) #define PIN_PA25B_USART2_RXD _L_(25) /**< \brief USART2 signal: RXD on PA25 mux B */ #define MUX_PA25B_USART2_RXD _L_(1) #define PINMUX_PA25B_USART2_RXD ((PIN_PA25B_USART2_RXD << 16) | MUX_PA25B_USART2_RXD) #define GPIO_PA25B_USART2_RXD _UL_(1 << 25) #define PIN_PC11B_USART2_RXD _L_(75) /**< \brief USART2 signal: RXD on PC11 mux B */ #define MUX_PC11B_USART2_RXD _L_(1) #define PINMUX_PC11B_USART2_RXD ((PIN_PC11B_USART2_RXD << 16) | MUX_PC11B_USART2_RXD) #define GPIO_PC11B_USART2_RXD _UL_(1 << 11) #define PIN_PA19A_USART2_RXD _L_(19) /**< \brief USART2 signal: RXD on PA19 mux A */ #define MUX_PA19A_USART2_RXD _L_(0) #define PINMUX_PA19A_USART2_RXD ((PIN_PA19A_USART2_RXD << 16) | MUX_PA19A_USART2_RXD) #define GPIO_PA19A_USART2_RXD _UL_(1 << 19) #define PIN_PA26B_USART2_TXD _L_(26) /**< \brief USART2 signal: TXD on PA26 mux B */ #define MUX_PA26B_USART2_TXD _L_(1) #define PINMUX_PA26B_USART2_TXD ((PIN_PA26B_USART2_TXD << 16) | MUX_PA26B_USART2_TXD) #define GPIO_PA26B_USART2_TXD _UL_(1 << 26) #define PIN_PC12B_USART2_TXD _L_(76) /**< \brief USART2 signal: TXD on PC12 mux B */ #define MUX_PC12B_USART2_TXD _L_(1) #define PINMUX_PC12B_USART2_TXD ((PIN_PC12B_USART2_TXD << 16) | MUX_PC12B_USART2_TXD) #define GPIO_PC12B_USART2_TXD _UL_(1 << 12) #define PIN_PA20A_USART2_TXD _L_(20) /**< \brief USART2 signal: TXD on PA20 mux A */ #define MUX_PA20A_USART2_TXD _L_(0) #define PINMUX_PA20A_USART2_TXD ((PIN_PA20A_USART2_TXD << 16) | MUX_PA20A_USART2_TXD) #define GPIO_PA20A_USART2_TXD _UL_(1 << 20) /* ========== GPIO definition for USART3 peripheral ========== */ #define PIN_PC14B_USART3_CLK _L_(78) /**< \brief USART3 signal: CLK on PC14 mux B */ #define MUX_PC14B_USART3_CLK _L_(1) #define PINMUX_PC14B_USART3_CLK ((PIN_PC14B_USART3_CLK << 16) | MUX_PC14B_USART3_CLK) #define GPIO_PC14B_USART3_CLK _UL_(1 << 14) #define PIN_PB08A_USART3_CLK _L_(40) /**< \brief USART3 signal: CLK on PB08 mux A */ #define MUX_PB08A_USART3_CLK _L_(0) #define PINMUX_PB08A_USART3_CLK ((PIN_PB08A_USART3_CLK << 16) | MUX_PB08A_USART3_CLK) #define GPIO_PB08A_USART3_CLK _UL_(1 << 8) #define PIN_PC31A_USART3_CLK _L_(95) /**< \brief USART3 signal: CLK on PC31 mux A */ #define MUX_PC31A_USART3_CLK _L_(0) #define PINMUX_PC31A_USART3_CLK ((PIN_PC31A_USART3_CLK << 16) | MUX_PC31A_USART3_CLK) #define GPIO_PC31A_USART3_CLK _UL_(1 << 31) #define PIN_PB07A_USART3_CTS _L_(39) /**< \brief USART3 signal: CTS on PB07 mux A */ #define MUX_PB07A_USART3_CTS _L_(0) #define PINMUX_PB07A_USART3_CTS ((PIN_PB07A_USART3_CTS << 16) | MUX_PB07A_USART3_CTS) #define GPIO_PB07A_USART3_CTS _UL_(1 << 7) #define PIN_PC13B_USART3_RTS _L_(77) /**< \brief USART3 signal: RTS on PC13 mux B */ #define MUX_PC13B_USART3_RTS _L_(1) #define PINMUX_PC13B_USART3_RTS ((PIN_PC13B_USART3_RTS << 16) | MUX_PC13B_USART3_RTS) #define GPIO_PC13B_USART3_RTS _UL_(1 << 13) #define PIN_PB06A_USART3_RTS _L_(38) /**< \brief USART3 signal: RTS on PB06 mux A */ #define MUX_PB06A_USART3_RTS _L_(0) #define PINMUX_PB06A_USART3_RTS ((PIN_PB06A_USART3_RTS << 16) | MUX_PB06A_USART3_RTS) #define GPIO_PB06A_USART3_RTS _UL_(1 << 6) #define PIN_PC30A_USART3_RTS _L_(94) /**< \brief USART3 signal: RTS on PC30 mux A */ #define MUX_PC30A_USART3_RTS _L_(0) #define PINMUX_PC30A_USART3_RTS ((PIN_PC30A_USART3_RTS << 16) | MUX_PC30A_USART3_RTS) #define GPIO_PC30A_USART3_RTS _UL_(1 << 30) #define PIN_PC09B_USART3_RXD _L_(73) /**< \brief USART3 signal: RXD on PC09 mux B */ #define MUX_PC09B_USART3_RXD _L_(1) #define PINMUX_PC09B_USART3_RXD ((PIN_PC09B_USART3_RXD << 16) | MUX_PC09B_USART3_RXD) #define GPIO_PC09B_USART3_RXD _UL_(1 << 9) #define PIN_PB09A_USART3_RXD _L_(41) /**< \brief USART3 signal: RXD on PB09 mux A */ #define MUX_PB09A_USART3_RXD _L_(0) #define PINMUX_PB09A_USART3_RXD ((PIN_PB09A_USART3_RXD << 16) | MUX_PB09A_USART3_RXD) #define GPIO_PB09A_USART3_RXD _UL_(1 << 9) #define PIN_PC28A_USART3_RXD _L_(92) /**< \brief USART3 signal: RXD on PC28 mux A */ #define MUX_PC28A_USART3_RXD _L_(0) #define PINMUX_PC28A_USART3_RXD ((PIN_PC28A_USART3_RXD << 16) | MUX_PC28A_USART3_RXD) #define GPIO_PC28A_USART3_RXD _UL_(1 << 28) #define PIN_PC10B_USART3_TXD _L_(74) /**< \brief USART3 signal: TXD on PC10 mux B */ #define MUX_PC10B_USART3_TXD _L_(1) #define PINMUX_PC10B_USART3_TXD ((PIN_PC10B_USART3_TXD << 16) | MUX_PC10B_USART3_TXD) #define GPIO_PC10B_USART3_TXD _UL_(1 << 10) #define PIN_PB10A_USART3_TXD _L_(42) /**< \brief USART3 signal: TXD on PB10 mux A */ #define MUX_PB10A_USART3_TXD _L_(0) #define PINMUX_PB10A_USART3_TXD ((PIN_PB10A_USART3_TXD << 16) | MUX_PB10A_USART3_TXD) #define GPIO_PB10A_USART3_TXD _UL_(1 << 10) #define PIN_PC29A_USART3_TXD _L_(93) /**< \brief USART3 signal: TXD on PC29 mux A */ #define MUX_PC29A_USART3_TXD _L_(0) #define PINMUX_PC29A_USART3_TXD ((PIN_PC29A_USART3_TXD << 16) | MUX_PC29A_USART3_TXD) #define GPIO_PC29A_USART3_TXD _UL_(1 << 29) /* ========== GPIO definition for ADCIFE peripheral ========== */ #define PIN_PA04A_ADCIFE_AD0 _L_(4) /**< \brief ADCIFE signal: AD0 on PA04 mux A */ #define MUX_PA04A_ADCIFE_AD0 _L_(0) #define PINMUX_PA04A_ADCIFE_AD0 ((PIN_PA04A_ADCIFE_AD0 << 16) | MUX_PA04A_ADCIFE_AD0) #define GPIO_PA04A_ADCIFE_AD0 _UL_(1 << 4) #define PIN_PA05A_ADCIFE_AD1 _L_(5) /**< \brief ADCIFE signal: AD1 on PA05 mux A */ #define MUX_PA05A_ADCIFE_AD1 _L_(0) #define PINMUX_PA05A_ADCIFE_AD1 ((PIN_PA05A_ADCIFE_AD1 << 16) | MUX_PA05A_ADCIFE_AD1) #define GPIO_PA05A_ADCIFE_AD1 _UL_(1 << 5) #define PIN_PA07A_ADCIFE_AD2 _L_(7) /**< \brief ADCIFE signal: AD2 on PA07 mux A */ #define MUX_PA07A_ADCIFE_AD2 _L_(0) #define PINMUX_PA07A_ADCIFE_AD2 ((PIN_PA07A_ADCIFE_AD2 << 16) | MUX_PA07A_ADCIFE_AD2) #define GPIO_PA07A_ADCIFE_AD2 _UL_(1 << 7) #define PIN_PB02A_ADCIFE_AD3 _L_(34) /**< \brief ADCIFE signal: AD3 on PB02 mux A */ #define MUX_PB02A_ADCIFE_AD3 _L_(0) #define PINMUX_PB02A_ADCIFE_AD3 ((PIN_PB02A_ADCIFE_AD3 << 16) | MUX_PB02A_ADCIFE_AD3) #define GPIO_PB02A_ADCIFE_AD3 _UL_(1 << 2) #define PIN_PB03A_ADCIFE_AD4 _L_(35) /**< \brief ADCIFE signal: AD4 on PB03 mux A */ #define MUX_PB03A_ADCIFE_AD4 _L_(0) #define PINMUX_PB03A_ADCIFE_AD4 ((PIN_PB03A_ADCIFE_AD4 << 16) | MUX_PB03A_ADCIFE_AD4) #define GPIO_PB03A_ADCIFE_AD4 _UL_(1 << 3) #define PIN_PB04A_ADCIFE_AD5 _L_(36) /**< \brief ADCIFE signal: AD5 on PB04 mux A */ #define MUX_PB04A_ADCIFE_AD5 _L_(0) #define PINMUX_PB04A_ADCIFE_AD5 ((PIN_PB04A_ADCIFE_AD5 << 16) | MUX_PB04A_ADCIFE_AD5) #define GPIO_PB04A_ADCIFE_AD5 _UL_(1 << 4) #define PIN_PB05A_ADCIFE_AD6 _L_(37) /**< \brief ADCIFE signal: AD6 on PB05 mux A */ #define MUX_PB05A_ADCIFE_AD6 _L_(0) #define PINMUX_PB05A_ADCIFE_AD6 ((PIN_PB05A_ADCIFE_AD6 << 16) | MUX_PB05A_ADCIFE_AD6) #define GPIO_PB05A_ADCIFE_AD6 _UL_(1 << 5) #define PIN_PC07A_ADCIFE_AD7 _L_(71) /**< \brief ADCIFE signal: AD7 on PC07 mux A */ #define MUX_PC07A_ADCIFE_AD7 _L_(0) #define PINMUX_PC07A_ADCIFE_AD7 ((PIN_PC07A_ADCIFE_AD7 << 16) | MUX_PC07A_ADCIFE_AD7) #define GPIO_PC07A_ADCIFE_AD7 _UL_(1 << 7) #define PIN_PC08A_ADCIFE_AD8 _L_(72) /**< \brief ADCIFE signal: AD8 on PC08 mux A */ #define MUX_PC08A_ADCIFE_AD8 _L_(0) #define PINMUX_PC08A_ADCIFE_AD8 ((PIN_PC08A_ADCIFE_AD8 << 16) | MUX_PC08A_ADCIFE_AD8) #define GPIO_PC08A_ADCIFE_AD8 _UL_(1 << 8) #define PIN_PC09A_ADCIFE_AD9 _L_(73) /**< \brief ADCIFE signal: AD9 on PC09 mux A */ #define MUX_PC09A_ADCIFE_AD9 _L_(0) #define PINMUX_PC09A_ADCIFE_AD9 ((PIN_PC09A_ADCIFE_AD9 << 16) | MUX_PC09A_ADCIFE_AD9) #define GPIO_PC09A_ADCIFE_AD9 _UL_(1 << 9) #define PIN_PC10A_ADCIFE_AD10 _L_(74) /**< \brief ADCIFE signal: AD10 on PC10 mux A */ #define MUX_PC10A_ADCIFE_AD10 _L_(0) #define PINMUX_PC10A_ADCIFE_AD10 ((PIN_PC10A_ADCIFE_AD10 << 16) | MUX_PC10A_ADCIFE_AD10) #define GPIO_PC10A_ADCIFE_AD10 _UL_(1 << 10) #define PIN_PC11A_ADCIFE_AD11 _L_(75) /**< \brief ADCIFE signal: AD11 on PC11 mux A */ #define MUX_PC11A_ADCIFE_AD11 _L_(0) #define PINMUX_PC11A_ADCIFE_AD11 ((PIN_PC11A_ADCIFE_AD11 << 16) | MUX_PC11A_ADCIFE_AD11) #define GPIO_PC11A_ADCIFE_AD11 _UL_(1 << 11) #define PIN_PC12A_ADCIFE_AD12 _L_(76) /**< \brief ADCIFE signal: AD12 on PC12 mux A */ #define MUX_PC12A_ADCIFE_AD12 _L_(0) #define PINMUX_PC12A_ADCIFE_AD12 ((PIN_PC12A_ADCIFE_AD12 << 16) | MUX_PC12A_ADCIFE_AD12) #define GPIO_PC12A_ADCIFE_AD12 _UL_(1 << 12) #define PIN_PC13A_ADCIFE_AD13 _L_(77) /**< \brief ADCIFE signal: AD13 on PC13 mux A */ #define MUX_PC13A_ADCIFE_AD13 _L_(0) #define PINMUX_PC13A_ADCIFE_AD13 ((PIN_PC13A_ADCIFE_AD13 << 16) | MUX_PC13A_ADCIFE_AD13) #define GPIO_PC13A_ADCIFE_AD13 _UL_(1 << 13) #define PIN_PC14A_ADCIFE_AD14 _L_(78) /**< \brief ADCIFE signal: AD14 on PC14 mux A */ #define MUX_PC14A_ADCIFE_AD14 _L_(0) #define PINMUX_PC14A_ADCIFE_AD14 ((PIN_PC14A_ADCIFE_AD14 << 16) | MUX_PC14A_ADCIFE_AD14) #define GPIO_PC14A_ADCIFE_AD14 _UL_(1 << 14) #define PIN_PA05E_ADCIFE_TRIGGER _L_(5) /**< \brief ADCIFE signal: TRIGGER on PA05 mux E */ #define MUX_PA05E_ADCIFE_TRIGGER _L_(4) #define PINMUX_PA05E_ADCIFE_TRIGGER ((PIN_PA05E_ADCIFE_TRIGGER << 16) | MUX_PA05E_ADCIFE_TRIGGER) #define GPIO_PA05E_ADCIFE_TRIGGER _UL_(1 << 5) /* ========== GPIO definition for DACC peripheral ========== */ #define PIN_PB04E_DACC_EXT_TRIG0 _L_(36) /**< \brief DACC signal: EXT_TRIG0 on PB04 mux E */ #define MUX_PB04E_DACC_EXT_TRIG0 _L_(4) #define PINMUX_PB04E_DACC_EXT_TRIG0 ((PIN_PB04E_DACC_EXT_TRIG0 << 16) | MUX_PB04E_DACC_EXT_TRIG0) #define GPIO_PB04E_DACC_EXT_TRIG0 _UL_(1 << 4) #define PIN_PA06A_DACC_VOUT _L_(6) /**< \brief DACC signal: VOUT on PA06 mux A */ #define MUX_PA06A_DACC_VOUT _L_(0) #define PINMUX_PA06A_DACC_VOUT ((PIN_PA06A_DACC_VOUT << 16) | MUX_PA06A_DACC_VOUT) #define GPIO_PA06A_DACC_VOUT _UL_(1 << 6) /* ========== GPIO definition for ACIFC peripheral ========== */ #define PIN_PA06E_ACIFC_ACAN0 _L_(6) /**< \brief ACIFC signal: ACAN0 on PA06 mux E */ #define MUX_PA06E_ACIFC_ACAN0 _L_(4) #define PINMUX_PA06E_ACIFC_ACAN0 ((PIN_PA06E_ACIFC_ACAN0 << 16) | MUX_PA06E_ACIFC_ACAN0) #define GPIO_PA06E_ACIFC_ACAN0 _UL_(1 << 6) #define PIN_PC09E_ACIFC_ACAN1 _L_(73) /**< \brief ACIFC signal: ACAN1 on PC09 mux E */ #define MUX_PC09E_ACIFC_ACAN1 _L_(4) #define PINMUX_PC09E_ACIFC_ACAN1 ((PIN_PC09E_ACIFC_ACAN1 << 16) | MUX_PC09E_ACIFC_ACAN1) #define GPIO_PC09E_ACIFC_ACAN1 _UL_(1 << 9) #define PIN_PA07E_ACIFC_ACAP0 _L_(7) /**< \brief ACIFC signal: ACAP0 on PA07 mux E */ #define MUX_PA07E_ACIFC_ACAP0 _L_(4) #define PINMUX_PA07E_ACIFC_ACAP0 ((PIN_PA07E_ACIFC_ACAP0 << 16) | MUX_PA07E_ACIFC_ACAP0) #define GPIO_PA07E_ACIFC_ACAP0 _UL_(1 << 7) #define PIN_PC10E_ACIFC_ACAP1 _L_(74) /**< \brief ACIFC signal: ACAP1 on PC10 mux E */ #define MUX_PC10E_ACIFC_ACAP1 _L_(4) #define PINMUX_PC10E_ACIFC_ACAP1 ((PIN_PC10E_ACIFC_ACAP1 << 16) | MUX_PC10E_ACIFC_ACAP1) #define GPIO_PC10E_ACIFC_ACAP1 _UL_(1 << 10) #define PIN_PB02E_ACIFC_ACBN0 _L_(34) /**< \brief ACIFC signal: ACBN0 on PB02 mux E */ #define MUX_PB02E_ACIFC_ACBN0 _L_(4) #define PINMUX_PB02E_ACIFC_ACBN0 ((PIN_PB02E_ACIFC_ACBN0 << 16) | MUX_PB02E_ACIFC_ACBN0) #define GPIO_PB02E_ACIFC_ACBN0 _UL_(1 << 2) #define PIN_PC13E_ACIFC_ACBN1 _L_(77) /**< \brief ACIFC signal: ACBN1 on PC13 mux E */ #define MUX_PC13E_ACIFC_ACBN1 _L_(4) #define PINMUX_PC13E_ACIFC_ACBN1 ((PIN_PC13E_ACIFC_ACBN1 << 16) | MUX_PC13E_ACIFC_ACBN1) #define GPIO_PC13E_ACIFC_ACBN1 _UL_(1 << 13) #define PIN_PB03E_ACIFC_ACBP0 _L_(35) /**< \brief ACIFC signal: ACBP0 on PB03 mux E */ #define MUX_PB03E_ACIFC_ACBP0 _L_(4) #define PINMUX_PB03E_ACIFC_ACBP0 ((PIN_PB03E_ACIFC_ACBP0 << 16) | MUX_PB03E_ACIFC_ACBP0) #define GPIO_PB03E_ACIFC_ACBP0 _UL_(1 << 3) #define PIN_PC14E_ACIFC_ACBP1 _L_(78) /**< \brief ACIFC signal: ACBP1 on PC14 mux E */ #define MUX_PC14E_ACIFC_ACBP1 _L_(4) #define PINMUX_PC14E_ACIFC_ACBP1 ((PIN_PC14E_ACIFC_ACBP1 << 16) | MUX_PC14E_ACIFC_ACBP1) #define GPIO_PC14E_ACIFC_ACBP1 _UL_(1 << 14) /* ========== GPIO definition for GLOC peripheral ========== */ #define PIN_PA06D_GLOC_IN0 _L_(6) /**< \brief GLOC signal: IN0 on PA06 mux D */ #define MUX_PA06D_GLOC_IN0 _L_(3) #define PINMUX_PA06D_GLOC_IN0 ((PIN_PA06D_GLOC_IN0 << 16) | MUX_PA06D_GLOC_IN0) #define GPIO_PA06D_GLOC_IN0 _UL_(1 << 6) #define PIN_PA20D_GLOC_IN0 _L_(20) /**< \brief GLOC signal: IN0 on PA20 mux D */ #define MUX_PA20D_GLOC_IN0 _L_(3) #define PINMUX_PA20D_GLOC_IN0 ((PIN_PA20D_GLOC_IN0 << 16) | MUX_PA20D_GLOC_IN0) #define GPIO_PA20D_GLOC_IN0 _UL_(1 << 20) #define PIN_PA04D_GLOC_IN1 _L_(4) /**< \brief GLOC signal: IN1 on PA04 mux D */ #define MUX_PA04D_GLOC_IN1 _L_(3) #define PINMUX_PA04D_GLOC_IN1 ((PIN_PA04D_GLOC_IN1 << 16) | MUX_PA04D_GLOC_IN1) #define GPIO_PA04D_GLOC_IN1 _UL_(1 << 4) #define PIN_PA21D_GLOC_IN1 _L_(21) /**< \brief GLOC signal: IN1 on PA21 mux D */ #define MUX_PA21D_GLOC_IN1 _L_(3) #define PINMUX_PA21D_GLOC_IN1 ((PIN_PA21D_GLOC_IN1 << 16) | MUX_PA21D_GLOC_IN1) #define GPIO_PA21D_GLOC_IN1 _UL_(1 << 21) #define PIN_PA05D_GLOC_IN2 _L_(5) /**< \brief GLOC signal: IN2 on PA05 mux D */ #define MUX_PA05D_GLOC_IN2 _L_(3) #define PINMUX_PA05D_GLOC_IN2 ((PIN_PA05D_GLOC_IN2 << 16) | MUX_PA05D_GLOC_IN2) #define GPIO_PA05D_GLOC_IN2 _UL_(1 << 5) #define PIN_PA22D_GLOC_IN2 _L_(22) /**< \brief GLOC signal: IN2 on PA22 mux D */ #define MUX_PA22D_GLOC_IN2 _L_(3) #define PINMUX_PA22D_GLOC_IN2 ((PIN_PA22D_GLOC_IN2 << 16) | MUX_PA22D_GLOC_IN2) #define GPIO_PA22D_GLOC_IN2 _UL_(1 << 22) #define PIN_PA07D_GLOC_IN3 _L_(7) /**< \brief GLOC signal: IN3 on PA07 mux D */ #define MUX_PA07D_GLOC_IN3 _L_(3) #define PINMUX_PA07D_GLOC_IN3 ((PIN_PA07D_GLOC_IN3 << 16) | MUX_PA07D_GLOC_IN3) #define GPIO_PA07D_GLOC_IN3 _UL_(1 << 7) #define PIN_PA23D_GLOC_IN3 _L_(23) /**< \brief GLOC signal: IN3 on PA23 mux D */ #define MUX_PA23D_GLOC_IN3 _L_(3) #define PINMUX_PA23D_GLOC_IN3 ((PIN_PA23D_GLOC_IN3 << 16) | MUX_PA23D_GLOC_IN3) #define GPIO_PA23D_GLOC_IN3 _UL_(1 << 23) #define PIN_PC15D_GLOC_IN4 _L_(79) /**< \brief GLOC signal: IN4 on PC15 mux D */ #define MUX_PC15D_GLOC_IN4 _L_(3) #define PINMUX_PC15D_GLOC_IN4 ((PIN_PC15D_GLOC_IN4 << 16) | MUX_PC15D_GLOC_IN4) #define GPIO_PC15D_GLOC_IN4 _UL_(1 << 15) #define PIN_PB06C_GLOC_IN4 _L_(38) /**< \brief GLOC signal: IN4 on PB06 mux C */ #define MUX_PB06C_GLOC_IN4 _L_(2) #define PINMUX_PB06C_GLOC_IN4 ((PIN_PB06C_GLOC_IN4 << 16) | MUX_PB06C_GLOC_IN4) #define GPIO_PB06C_GLOC_IN4 _UL_(1 << 6) #define PIN_PC28C_GLOC_IN4 _L_(92) /**< \brief GLOC signal: IN4 on PC28 mux C */ #define MUX_PC28C_GLOC_IN4 _L_(2) #define PINMUX_PC28C_GLOC_IN4 ((PIN_PC28C_GLOC_IN4 << 16) | MUX_PC28C_GLOC_IN4) #define GPIO_PC28C_GLOC_IN4 _UL_(1 << 28) #define PIN_PC16D_GLOC_IN5 _L_(80) /**< \brief GLOC signal: IN5 on PC16 mux D */ #define MUX_PC16D_GLOC_IN5 _L_(3) #define PINMUX_PC16D_GLOC_IN5 ((PIN_PC16D_GLOC_IN5 << 16) | MUX_PC16D_GLOC_IN5) #define GPIO_PC16D_GLOC_IN5 _UL_(1 << 16) #define PIN_PB07C_GLOC_IN5 _L_(39) /**< \brief GLOC signal: IN5 on PB07 mux C */ #define MUX_PB07C_GLOC_IN5 _L_(2) #define PINMUX_PB07C_GLOC_IN5 ((PIN_PB07C_GLOC_IN5 << 16) | MUX_PB07C_GLOC_IN5) #define GPIO_PB07C_GLOC_IN5 _UL_(1 << 7) #define PIN_PC29C_GLOC_IN5 _L_(93) /**< \brief GLOC signal: IN5 on PC29 mux C */ #define MUX_PC29C_GLOC_IN5 _L_(2) #define PINMUX_PC29C_GLOC_IN5 ((PIN_PC29C_GLOC_IN5 << 16) | MUX_PC29C_GLOC_IN5) #define GPIO_PC29C_GLOC_IN5 _UL_(1 << 29) #define PIN_PC17D_GLOC_IN6 _L_(81) /**< \brief GLOC signal: IN6 on PC17 mux D */ #define MUX_PC17D_GLOC_IN6 _L_(3) #define PINMUX_PC17D_GLOC_IN6 ((PIN_PC17D_GLOC_IN6 << 16) | MUX_PC17D_GLOC_IN6) #define GPIO_PC17D_GLOC_IN6 _UL_(1 << 17) #define PIN_PB08C_GLOC_IN6 _L_(40) /**< \brief GLOC signal: IN6 on PB08 mux C */ #define MUX_PB08C_GLOC_IN6 _L_(2) #define PINMUX_PB08C_GLOC_IN6 ((PIN_PB08C_GLOC_IN6 << 16) | MUX_PB08C_GLOC_IN6) #define GPIO_PB08C_GLOC_IN6 _UL_(1 << 8) #define PIN_PC30C_GLOC_IN6 _L_(94) /**< \brief GLOC signal: IN6 on PC30 mux C */ #define MUX_PC30C_GLOC_IN6 _L_(2) #define PINMUX_PC30C_GLOC_IN6 ((PIN_PC30C_GLOC_IN6 << 16) | MUX_PC30C_GLOC_IN6) #define GPIO_PC30C_GLOC_IN6 _UL_(1 << 30) #define PIN_PC18D_GLOC_IN7 _L_(82) /**< \brief GLOC signal: IN7 on PC18 mux D */ #define MUX_PC18D_GLOC_IN7 _L_(3) #define PINMUX_PC18D_GLOC_IN7 ((PIN_PC18D_GLOC_IN7 << 16) | MUX_PC18D_GLOC_IN7) #define GPIO_PC18D_GLOC_IN7 _UL_(1 << 18) #define PIN_PB09C_GLOC_IN7 _L_(41) /**< \brief GLOC signal: IN7 on PB09 mux C */ #define MUX_PB09C_GLOC_IN7 _L_(2) #define PINMUX_PB09C_GLOC_IN7 ((PIN_PB09C_GLOC_IN7 << 16) | MUX_PB09C_GLOC_IN7) #define GPIO_PB09C_GLOC_IN7 _UL_(1 << 9) #define PIN_PA08D_GLOC_OUT0 _L_(8) /**< \brief GLOC signal: OUT0 on PA08 mux D */ #define MUX_PA08D_GLOC_OUT0 _L_(3) #define PINMUX_PA08D_GLOC_OUT0 ((PIN_PA08D_GLOC_OUT0 << 16) | MUX_PA08D_GLOC_OUT0) #define GPIO_PA08D_GLOC_OUT0 _UL_(1 << 8) #define PIN_PA24D_GLOC_OUT0 _L_(24) /**< \brief GLOC signal: OUT0 on PA24 mux D */ #define MUX_PA24D_GLOC_OUT0 _L_(3) #define PINMUX_PA24D_GLOC_OUT0 ((PIN_PA24D_GLOC_OUT0 << 16) | MUX_PA24D_GLOC_OUT0) #define GPIO_PA24D_GLOC_OUT0 _UL_(1 << 24) #define PIN_PC19D_GLOC_OUT1 _L_(83) /**< \brief GLOC signal: OUT1 on PC19 mux D */ #define MUX_PC19D_GLOC_OUT1 _L_(3) #define PINMUX_PC19D_GLOC_OUT1 ((PIN_PC19D_GLOC_OUT1 << 16) | MUX_PC19D_GLOC_OUT1) #define GPIO_PC19D_GLOC_OUT1 _UL_(1 << 19) #define PIN_PB10C_GLOC_OUT1 _L_(42) /**< \brief GLOC signal: OUT1 on PB10 mux C */ #define MUX_PB10C_GLOC_OUT1 _L_(2) #define PINMUX_PB10C_GLOC_OUT1 ((PIN_PB10C_GLOC_OUT1 << 16) | MUX_PB10C_GLOC_OUT1) #define GPIO_PB10C_GLOC_OUT1 _UL_(1 << 10) #define PIN_PC31C_GLOC_OUT1 _L_(95) /**< \brief GLOC signal: OUT1 on PC31 mux C */ #define MUX_PC31C_GLOC_OUT1 _L_(2) #define PINMUX_PC31C_GLOC_OUT1 ((PIN_PC31C_GLOC_OUT1 << 16) | MUX_PC31C_GLOC_OUT1) #define GPIO_PC31C_GLOC_OUT1 _UL_(1 << 31) /* ========== GPIO definition for ABDACB peripheral ========== */ #define PIN_PC12C_ABDACB_CLK _L_(76) /**< \brief ABDACB signal: CLK on PC12 mux C */ #define MUX_PC12C_ABDACB_CLK _L_(2) #define PINMUX_PC12C_ABDACB_CLK ((PIN_PC12C_ABDACB_CLK << 16) | MUX_PC12C_ABDACB_CLK) #define GPIO_PC12C_ABDACB_CLK _UL_(1 << 12) #define PIN_PB02C_ABDACB_DAC0 _L_(34) /**< \brief ABDACB signal: DAC0 on PB02 mux C */ #define MUX_PB02C_ABDACB_DAC0 _L_(2) #define PINMUX_PB02C_ABDACB_DAC0 ((PIN_PB02C_ABDACB_DAC0 << 16) | MUX_PB02C_ABDACB_DAC0) #define GPIO_PB02C_ABDACB_DAC0 _UL_(1 << 2) #define PIN_PC09C_ABDACB_DAC0 _L_(73) /**< \brief ABDACB signal: DAC0 on PC09 mux C */ #define MUX_PC09C_ABDACB_DAC0 _L_(2) #define PINMUX_PC09C_ABDACB_DAC0 ((PIN_PC09C_ABDACB_DAC0 << 16) | MUX_PC09C_ABDACB_DAC0) #define GPIO_PC09C_ABDACB_DAC0 _UL_(1 << 9) #define PIN_PA17B_ABDACB_DAC0 _L_(17) /**< \brief ABDACB signal: DAC0 on PA17 mux B */ #define MUX_PA17B_ABDACB_DAC0 _L_(1) #define PINMUX_PA17B_ABDACB_DAC0 ((PIN_PA17B_ABDACB_DAC0 << 16) | MUX_PA17B_ABDACB_DAC0) #define GPIO_PA17B_ABDACB_DAC0 _UL_(1 << 17) #define PIN_PB04C_ABDACB_DAC1 _L_(36) /**< \brief ABDACB signal: DAC1 on PB04 mux C */ #define MUX_PB04C_ABDACB_DAC1 _L_(2) #define PINMUX_PB04C_ABDACB_DAC1 ((PIN_PB04C_ABDACB_DAC1 << 16) | MUX_PB04C_ABDACB_DAC1) #define GPIO_PB04C_ABDACB_DAC1 _UL_(1 << 4) #define PIN_PC13C_ABDACB_DAC1 _L_(77) /**< \brief ABDACB signal: DAC1 on PC13 mux C */ #define MUX_PC13C_ABDACB_DAC1 _L_(2) #define PINMUX_PC13C_ABDACB_DAC1 ((PIN_PC13C_ABDACB_DAC1 << 16) | MUX_PC13C_ABDACB_DAC1) #define GPIO_PC13C_ABDACB_DAC1 _UL_(1 << 13) #define PIN_PA19B_ABDACB_DAC1 _L_(19) /**< \brief ABDACB signal: DAC1 on PA19 mux B */ #define MUX_PA19B_ABDACB_DAC1 _L_(1) #define PINMUX_PA19B_ABDACB_DAC1 ((PIN_PA19B_ABDACB_DAC1 << 16) | MUX_PA19B_ABDACB_DAC1) #define GPIO_PA19B_ABDACB_DAC1 _UL_(1 << 19) #define PIN_PB03C_ABDACB_DACN0 _L_(35) /**< \brief ABDACB signal: DACN0 on PB03 mux C */ #define MUX_PB03C_ABDACB_DACN0 _L_(2) #define PINMUX_PB03C_ABDACB_DACN0 ((PIN_PB03C_ABDACB_DACN0 << 16) | MUX_PB03C_ABDACB_DACN0) #define GPIO_PB03C_ABDACB_DACN0 _UL_(1 << 3) #define PIN_PC10C_ABDACB_DACN0 _L_(74) /**< \brief ABDACB signal: DACN0 on PC10 mux C */ #define MUX_PC10C_ABDACB_DACN0 _L_(2) #define PINMUX_PC10C_ABDACB_DACN0 ((PIN_PC10C_ABDACB_DACN0 << 16) | MUX_PC10C_ABDACB_DACN0) #define GPIO_PC10C_ABDACB_DACN0 _UL_(1 << 10) #define PIN_PA18B_ABDACB_DACN0 _L_(18) /**< \brief ABDACB signal: DACN0 on PA18 mux B */ #define MUX_PA18B_ABDACB_DACN0 _L_(1) #define PINMUX_PA18B_ABDACB_DACN0 ((PIN_PA18B_ABDACB_DACN0 << 16) | MUX_PA18B_ABDACB_DACN0) #define GPIO_PA18B_ABDACB_DACN0 _UL_(1 << 18) #define PIN_PB05C_ABDACB_DACN1 _L_(37) /**< \brief ABDACB signal: DACN1 on PB05 mux C */ #define MUX_PB05C_ABDACB_DACN1 _L_(2) #define PINMUX_PB05C_ABDACB_DACN1 ((PIN_PB05C_ABDACB_DACN1 << 16) | MUX_PB05C_ABDACB_DACN1) #define GPIO_PB05C_ABDACB_DACN1 _UL_(1 << 5) #define PIN_PC14C_ABDACB_DACN1 _L_(78) /**< \brief ABDACB signal: DACN1 on PC14 mux C */ #define MUX_PC14C_ABDACB_DACN1 _L_(2) #define PINMUX_PC14C_ABDACB_DACN1 ((PIN_PC14C_ABDACB_DACN1 << 16) | MUX_PC14C_ABDACB_DACN1) #define GPIO_PC14C_ABDACB_DACN1 _UL_(1 << 14) #define PIN_PA20B_ABDACB_DACN1 _L_(20) /**< \brief ABDACB signal: DACN1 on PA20 mux B */ #define MUX_PA20B_ABDACB_DACN1 _L_(1) #define PINMUX_PA20B_ABDACB_DACN1 ((PIN_PA20B_ABDACB_DACN1 << 16) | MUX_PA20B_ABDACB_DACN1) #define GPIO_PA20B_ABDACB_DACN1 _UL_(1 << 20) /* ========== GPIO definition for PARC peripheral ========== */ #define PIN_PA17D_PARC_PCCK _L_(17) /**< \brief PARC signal: PCCK on PA17 mux D */ #define MUX_PA17D_PARC_PCCK _L_(3) #define PINMUX_PA17D_PARC_PCCK ((PIN_PA17D_PARC_PCCK << 16) | MUX_PA17D_PARC_PCCK) #define GPIO_PA17D_PARC_PCCK _UL_(1 << 17) #define PIN_PC21D_PARC_PCCK _L_(85) /**< \brief PARC signal: PCCK on PC21 mux D */ #define MUX_PC21D_PARC_PCCK _L_(3) #define PINMUX_PC21D_PARC_PCCK ((PIN_PC21D_PARC_PCCK << 16) | MUX_PC21D_PARC_PCCK) #define GPIO_PC21D_PARC_PCCK _UL_(1 << 21) #define PIN_PA09D_PARC_PCDATA0 _L_(9) /**< \brief PARC signal: PCDATA0 on PA09 mux D */ #define MUX_PA09D_PARC_PCDATA0 _L_(3) #define PINMUX_PA09D_PARC_PCDATA0 ((PIN_PA09D_PARC_PCDATA0 << 16) | MUX_PA09D_PARC_PCDATA0) #define GPIO_PA09D_PARC_PCDATA0 _UL_(1 << 9) #define PIN_PC24D_PARC_PCDATA0 _L_(88) /**< \brief PARC signal: PCDATA0 on PC24 mux D */ #define MUX_PC24D_PARC_PCDATA0 _L_(3) #define PINMUX_PC24D_PARC_PCDATA0 ((PIN_PC24D_PARC_PCDATA0 << 16) | MUX_PC24D_PARC_PCDATA0) #define GPIO_PC24D_PARC_PCDATA0 _UL_(1 << 24) #define PIN_PA10D_PARC_PCDATA1 _L_(10) /**< \brief PARC signal: PCDATA1 on PA10 mux D */ #define MUX_PA10D_PARC_PCDATA1 _L_(3) #define PINMUX_PA10D_PARC_PCDATA1 ((PIN_PA10D_PARC_PCDATA1 << 16) | MUX_PA10D_PARC_PCDATA1) #define GPIO_PA10D_PARC_PCDATA1 _UL_(1 << 10) #define PIN_PC25D_PARC_PCDATA1 _L_(89) /**< \brief PARC signal: PCDATA1 on PC25 mux D */ #define MUX_PC25D_PARC_PCDATA1 _L_(3) #define PINMUX_PC25D_PARC_PCDATA1 ((PIN_PC25D_PARC_PCDATA1 << 16) | MUX_PC25D_PARC_PCDATA1) #define GPIO_PC25D_PARC_PCDATA1 _UL_(1 << 25) #define PIN_PA11D_PARC_PCDATA2 _L_(11) /**< \brief PARC signal: PCDATA2 on PA11 mux D */ #define MUX_PA11D_PARC_PCDATA2 _L_(3) #define PINMUX_PA11D_PARC_PCDATA2 ((PIN_PA11D_PARC_PCDATA2 << 16) | MUX_PA11D_PARC_PCDATA2) #define GPIO_PA11D_PARC_PCDATA2 _UL_(1 << 11) #define PIN_PC26D_PARC_PCDATA2 _L_(90) /**< \brief PARC signal: PCDATA2 on PC26 mux D */ #define MUX_PC26D_PARC_PCDATA2 _L_(3) #define PINMUX_PC26D_PARC_PCDATA2 ((PIN_PC26D_PARC_PCDATA2 << 16) | MUX_PC26D_PARC_PCDATA2) #define GPIO_PC26D_PARC_PCDATA2 _UL_(1 << 26) #define PIN_PA12D_PARC_PCDATA3 _L_(12) /**< \brief PARC signal: PCDATA3 on PA12 mux D */ #define MUX_PA12D_PARC_PCDATA3 _L_(3) #define PINMUX_PA12D_PARC_PCDATA3 ((PIN_PA12D_PARC_PCDATA3 << 16) | MUX_PA12D_PARC_PCDATA3) #define GPIO_PA12D_PARC_PCDATA3 _UL_(1 << 12) #define PIN_PC27D_PARC_PCDATA3 _L_(91) /**< \brief PARC signal: PCDATA3 on PC27 mux D */ #define MUX_PC27D_PARC_PCDATA3 _L_(3) #define PINMUX_PC27D_PARC_PCDATA3 ((PIN_PC27D_PARC_PCDATA3 << 16) | MUX_PC27D_PARC_PCDATA3) #define GPIO_PC27D_PARC_PCDATA3 _UL_(1 << 27) #define PIN_PA13D_PARC_PCDATA4 _L_(13) /**< \brief PARC signal: PCDATA4 on PA13 mux D */ #define MUX_PA13D_PARC_PCDATA4 _L_(3) #define PINMUX_PA13D_PARC_PCDATA4 ((PIN_PA13D_PARC_PCDATA4 << 16) | MUX_PA13D_PARC_PCDATA4) #define GPIO_PA13D_PARC_PCDATA4 _UL_(1 << 13) #define PIN_PC28D_PARC_PCDATA4 _L_(92) /**< \brief PARC signal: PCDATA4 on PC28 mux D */ #define MUX_PC28D_PARC_PCDATA4 _L_(3) #define PINMUX_PC28D_PARC_PCDATA4 ((PIN_PC28D_PARC_PCDATA4 << 16) | MUX_PC28D_PARC_PCDATA4) #define GPIO_PC28D_PARC_PCDATA4 _UL_(1 << 28) #define PIN_PA14D_PARC_PCDATA5 _L_(14) /**< \brief PARC signal: PCDATA5 on PA14 mux D */ #define MUX_PA14D_PARC_PCDATA5 _L_(3) #define PINMUX_PA14D_PARC_PCDATA5 ((PIN_PA14D_PARC_PCDATA5 << 16) | MUX_PA14D_PARC_PCDATA5) #define GPIO_PA14D_PARC_PCDATA5 _UL_(1 << 14) #define PIN_PC29D_PARC_PCDATA5 _L_(93) /**< \brief PARC signal: PCDATA5 on PC29 mux D */ #define MUX_PC29D_PARC_PCDATA5 _L_(3) #define PINMUX_PC29D_PARC_PCDATA5 ((PIN_PC29D_PARC_PCDATA5 << 16) | MUX_PC29D_PARC_PCDATA5) #define GPIO_PC29D_PARC_PCDATA5 _UL_(1 << 29) #define PIN_PA15D_PARC_PCDATA6 _L_(15) /**< \brief PARC signal: PCDATA6 on PA15 mux D */ #define MUX_PA15D_PARC_PCDATA6 _L_(3) #define PINMUX_PA15D_PARC_PCDATA6 ((PIN_PA15D_PARC_PCDATA6 << 16) | MUX_PA15D_PARC_PCDATA6) #define GPIO_PA15D_PARC_PCDATA6 _UL_(1 << 15) #define PIN_PC30D_PARC_PCDATA6 _L_(94) /**< \brief PARC signal: PCDATA6 on PC30 mux D */ #define MUX_PC30D_PARC_PCDATA6 _L_(3) #define PINMUX_PC30D_PARC_PCDATA6 ((PIN_PC30D_PARC_PCDATA6 << 16) | MUX_PC30D_PARC_PCDATA6) #define GPIO_PC30D_PARC_PCDATA6 _UL_(1 << 30) #define PIN_PA16D_PARC_PCDATA7 _L_(16) /**< \brief PARC signal: PCDATA7 on PA16 mux D */ #define MUX_PA16D_PARC_PCDATA7 _L_(3) #define PINMUX_PA16D_PARC_PCDATA7 ((PIN_PA16D_PARC_PCDATA7 << 16) | MUX_PA16D_PARC_PCDATA7) #define GPIO_PA16D_PARC_PCDATA7 _UL_(1 << 16) #define PIN_PC31D_PARC_PCDATA7 _L_(95) /**< \brief PARC signal: PCDATA7 on PC31 mux D */ #define MUX_PC31D_PARC_PCDATA7 _L_(3) #define PINMUX_PC31D_PARC_PCDATA7 ((PIN_PC31D_PARC_PCDATA7 << 16) | MUX_PC31D_PARC_PCDATA7) #define GPIO_PC31D_PARC_PCDATA7 _UL_(1 << 31) #define PIN_PA18D_PARC_PCEN1 _L_(18) /**< \brief PARC signal: PCEN1 on PA18 mux D */ #define MUX_PA18D_PARC_PCEN1 _L_(3) #define PINMUX_PA18D_PARC_PCEN1 ((PIN_PA18D_PARC_PCEN1 << 16) | MUX_PA18D_PARC_PCEN1) #define GPIO_PA18D_PARC_PCEN1 _UL_(1 << 18) #define PIN_PC22D_PARC_PCEN1 _L_(86) /**< \brief PARC signal: PCEN1 on PC22 mux D */ #define MUX_PC22D_PARC_PCEN1 _L_(3) #define PINMUX_PC22D_PARC_PCEN1 ((PIN_PC22D_PARC_PCEN1 << 16) | MUX_PC22D_PARC_PCEN1) #define GPIO_PC22D_PARC_PCEN1 _UL_(1 << 22) #define PIN_PA19D_PARC_PCEN2 _L_(19) /**< \brief PARC signal: PCEN2 on PA19 mux D */ #define MUX_PA19D_PARC_PCEN2 _L_(3) #define PINMUX_PA19D_PARC_PCEN2 ((PIN_PA19D_PARC_PCEN2 << 16) | MUX_PA19D_PARC_PCEN2) #define GPIO_PA19D_PARC_PCEN2 _UL_(1 << 19) #define PIN_PC23D_PARC_PCEN2 _L_(87) /**< \brief PARC signal: PCEN2 on PC23 mux D */ #define MUX_PC23D_PARC_PCEN2 _L_(3) #define PINMUX_PC23D_PARC_PCEN2 ((PIN_PC23D_PARC_PCEN2 << 16) | MUX_PC23D_PARC_PCEN2) #define GPIO_PC23D_PARC_PCEN2 _UL_(1 << 23) /* ========== GPIO definition for CATB peripheral ========== */ #define PIN_PA02G_CATB_DIS _L_(2) /**< \brief CATB signal: DIS on PA02 mux G */ #define MUX_PA02G_CATB_DIS _L_(6) #define PINMUX_PA02G_CATB_DIS ((PIN_PA02G_CATB_DIS << 16) | MUX_PA02G_CATB_DIS) #define GPIO_PA02G_CATB_DIS _UL_(1 << 2) #define PIN_PA12G_CATB_DIS _L_(12) /**< \brief CATB signal: DIS on PA12 mux G */ #define MUX_PA12G_CATB_DIS _L_(6) #define PINMUX_PA12G_CATB_DIS ((PIN_PA12G_CATB_DIS << 16) | MUX_PA12G_CATB_DIS) #define GPIO_PA12G_CATB_DIS _UL_(1 << 12) #define PIN_PA23G_CATB_DIS _L_(23) /**< \brief CATB signal: DIS on PA23 mux G */ #define MUX_PA23G_CATB_DIS _L_(6) #define PINMUX_PA23G_CATB_DIS ((PIN_PA23G_CATB_DIS << 16) | MUX_PA23G_CATB_DIS) #define GPIO_PA23G_CATB_DIS _UL_(1 << 23) #define PIN_PB03G_CATB_DIS _L_(35) /**< \brief CATB signal: DIS on PB03 mux G */ #define MUX_PB03G_CATB_DIS _L_(6) #define PINMUX_PB03G_CATB_DIS ((PIN_PB03G_CATB_DIS << 16) | MUX_PB03G_CATB_DIS) #define GPIO_PB03G_CATB_DIS _UL_(1 << 3) #define PIN_PB12G_CATB_DIS _L_(44) /**< \brief CATB signal: DIS on PB12 mux G */ #define MUX_PB12G_CATB_DIS _L_(6) #define PINMUX_PB12G_CATB_DIS ((PIN_PB12G_CATB_DIS << 16) | MUX_PB12G_CATB_DIS) #define GPIO_PB12G_CATB_DIS _UL_(1 << 12) #define PIN_PC05G_CATB_DIS _L_(69) /**< \brief CATB signal: DIS on PC05 mux G */ #define MUX_PC05G_CATB_DIS _L_(6) #define PINMUX_PC05G_CATB_DIS ((PIN_PC05G_CATB_DIS << 16) | MUX_PC05G_CATB_DIS) #define GPIO_PC05G_CATB_DIS _UL_(1 << 5) #define PIN_PC14G_CATB_DIS _L_(78) /**< \brief CATB signal: DIS on PC14 mux G */ #define MUX_PC14G_CATB_DIS _L_(6) #define PINMUX_PC14G_CATB_DIS ((PIN_PC14G_CATB_DIS << 16) | MUX_PC14G_CATB_DIS) #define GPIO_PC14G_CATB_DIS _UL_(1 << 14) #define PIN_PC23G_CATB_DIS _L_(87) /**< \brief CATB signal: DIS on PC23 mux G */ #define MUX_PC23G_CATB_DIS _L_(6) #define PINMUX_PC23G_CATB_DIS ((PIN_PC23G_CATB_DIS << 16) | MUX_PC23G_CATB_DIS) #define GPIO_PC23G_CATB_DIS _UL_(1 << 23) #define PIN_PA04G_CATB_SENSE0 _L_(4) /**< \brief CATB signal: SENSE0 on PA04 mux G */ #define MUX_PA04G_CATB_SENSE0 _L_(6) #define PINMUX_PA04G_CATB_SENSE0 ((PIN_PA04G_CATB_SENSE0 << 16) | MUX_PA04G_CATB_SENSE0) #define GPIO_PA04G_CATB_SENSE0 _UL_(1 << 4) #define PIN_PB13G_CATB_SENSE0 _L_(45) /**< \brief CATB signal: SENSE0 on PB13 mux G */ #define MUX_PB13G_CATB_SENSE0 _L_(6) #define PINMUX_PB13G_CATB_SENSE0 ((PIN_PB13G_CATB_SENSE0 << 16) | MUX_PB13G_CATB_SENSE0) #define GPIO_PB13G_CATB_SENSE0 _UL_(1 << 13) #define PIN_PA05G_CATB_SENSE1 _L_(5) /**< \brief CATB signal: SENSE1 on PA05 mux G */ #define MUX_PA05G_CATB_SENSE1 _L_(6) #define PINMUX_PA05G_CATB_SENSE1 ((PIN_PA05G_CATB_SENSE1 << 16) | MUX_PA05G_CATB_SENSE1) #define GPIO_PA05G_CATB_SENSE1 _UL_(1 << 5) #define PIN_PB14G_CATB_SENSE1 _L_(46) /**< \brief CATB signal: SENSE1 on PB14 mux G */ #define MUX_PB14G_CATB_SENSE1 _L_(6) #define PINMUX_PB14G_CATB_SENSE1 ((PIN_PB14G_CATB_SENSE1 << 16) | MUX_PB14G_CATB_SENSE1) #define GPIO_PB14G_CATB_SENSE1 _UL_(1 << 14) #define PIN_PA06G_CATB_SENSE2 _L_(6) /**< \brief CATB signal: SENSE2 on PA06 mux G */ #define MUX_PA06G_CATB_SENSE2 _L_(6) #define PINMUX_PA06G_CATB_SENSE2 ((PIN_PA06G_CATB_SENSE2 << 16) | MUX_PA06G_CATB_SENSE2) #define GPIO_PA06G_CATB_SENSE2 _UL_(1 << 6) #define PIN_PB15G_CATB_SENSE2 _L_(47) /**< \brief CATB signal: SENSE2 on PB15 mux G */ #define MUX_PB15G_CATB_SENSE2 _L_(6) #define PINMUX_PB15G_CATB_SENSE2 ((PIN_PB15G_CATB_SENSE2 << 16) | MUX_PB15G_CATB_SENSE2) #define GPIO_PB15G_CATB_SENSE2 _UL_(1 << 15) #define PIN_PA07G_CATB_SENSE3 _L_(7) /**< \brief CATB signal: SENSE3 on PA07 mux G */ #define MUX_PA07G_CATB_SENSE3 _L_(6) #define PINMUX_PA07G_CATB_SENSE3 ((PIN_PA07G_CATB_SENSE3 << 16) | MUX_PA07G_CATB_SENSE3) #define GPIO_PA07G_CATB_SENSE3 _UL_(1 << 7) #define PIN_PC00G_CATB_SENSE3 _L_(64) /**< \brief CATB signal: SENSE3 on PC00 mux G */ #define MUX_PC00G_CATB_SENSE3 _L_(6) #define PINMUX_PC00G_CATB_SENSE3 ((PIN_PC00G_CATB_SENSE3 << 16) | MUX_PC00G_CATB_SENSE3) #define GPIO_PC00G_CATB_SENSE3 _UL_(1 << 0) #define PIN_PA08G_CATB_SENSE4 _L_(8) /**< \brief CATB signal: SENSE4 on PA08 mux G */ #define MUX_PA08G_CATB_SENSE4 _L_(6) #define PINMUX_PA08G_CATB_SENSE4 ((PIN_PA08G_CATB_SENSE4 << 16) | MUX_PA08G_CATB_SENSE4) #define GPIO_PA08G_CATB_SENSE4 _UL_(1 << 8) #define PIN_PC01G_CATB_SENSE4 _L_(65) /**< \brief CATB signal: SENSE4 on PC01 mux G */ #define MUX_PC01G_CATB_SENSE4 _L_(6) #define PINMUX_PC01G_CATB_SENSE4 ((PIN_PC01G_CATB_SENSE4 << 16) | MUX_PC01G_CATB_SENSE4) #define GPIO_PC01G_CATB_SENSE4 _UL_(1 << 1) #define PIN_PA09G_CATB_SENSE5 _L_(9) /**< \brief CATB signal: SENSE5 on PA09 mux G */ #define MUX_PA09G_CATB_SENSE5 _L_(6) #define PINMUX_PA09G_CATB_SENSE5 ((PIN_PA09G_CATB_SENSE5 << 16) | MUX_PA09G_CATB_SENSE5) #define GPIO_PA09G_CATB_SENSE5 _UL_(1 << 9) #define PIN_PC02G_CATB_SENSE5 _L_(66) /**< \brief CATB signal: SENSE5 on PC02 mux G */ #define MUX_PC02G_CATB_SENSE5 _L_(6) #define PINMUX_PC02G_CATB_SENSE5 ((PIN_PC02G_CATB_SENSE5 << 16) | MUX_PC02G_CATB_SENSE5) #define GPIO_PC02G_CATB_SENSE5 _UL_(1 << 2) #define PIN_PA10G_CATB_SENSE6 _L_(10) /**< \brief CATB signal: SENSE6 on PA10 mux G */ #define MUX_PA10G_CATB_SENSE6 _L_(6) #define PINMUX_PA10G_CATB_SENSE6 ((PIN_PA10G_CATB_SENSE6 << 16) | MUX_PA10G_CATB_SENSE6) #define GPIO_PA10G_CATB_SENSE6 _UL_(1 << 10) #define PIN_PC03G_CATB_SENSE6 _L_(67) /**< \brief CATB signal: SENSE6 on PC03 mux G */ #define MUX_PC03G_CATB_SENSE6 _L_(6) #define PINMUX_PC03G_CATB_SENSE6 ((PIN_PC03G_CATB_SENSE6 << 16) | MUX_PC03G_CATB_SENSE6) #define GPIO_PC03G_CATB_SENSE6 _UL_(1 << 3) #define PIN_PA11G_CATB_SENSE7 _L_(11) /**< \brief CATB signal: SENSE7 on PA11 mux G */ #define MUX_PA11G_CATB_SENSE7 _L_(6) #define PINMUX_PA11G_CATB_SENSE7 ((PIN_PA11G_CATB_SENSE7 << 16) | MUX_PA11G_CATB_SENSE7) #define GPIO_PA11G_CATB_SENSE7 _UL_(1 << 11) #define PIN_PC04G_CATB_SENSE7 _L_(68) /**< \brief CATB signal: SENSE7 on PC04 mux G */ #define MUX_PC04G_CATB_SENSE7 _L_(6) #define PINMUX_PC04G_CATB_SENSE7 ((PIN_PC04G_CATB_SENSE7 << 16) | MUX_PC04G_CATB_SENSE7) #define GPIO_PC04G_CATB_SENSE7 _UL_(1 << 4) #define PIN_PA13G_CATB_SENSE8 _L_(13) /**< \brief CATB signal: SENSE8 on PA13 mux G */ #define MUX_PA13G_CATB_SENSE8 _L_(6) #define PINMUX_PA13G_CATB_SENSE8 ((PIN_PA13G_CATB_SENSE8 << 16) | MUX_PA13G_CATB_SENSE8) #define GPIO_PA13G_CATB_SENSE8 _UL_(1 << 13) #define PIN_PC06G_CATB_SENSE8 _L_(70) /**< \brief CATB signal: SENSE8 on PC06 mux G */ #define MUX_PC06G_CATB_SENSE8 _L_(6) #define PINMUX_PC06G_CATB_SENSE8 ((PIN_PC06G_CATB_SENSE8 << 16) | MUX_PC06G_CATB_SENSE8) #define GPIO_PC06G_CATB_SENSE8 _UL_(1 << 6) #define PIN_PA14G_CATB_SENSE9 _L_(14) /**< \brief CATB signal: SENSE9 on PA14 mux G */ #define MUX_PA14G_CATB_SENSE9 _L_(6) #define PINMUX_PA14G_CATB_SENSE9 ((PIN_PA14G_CATB_SENSE9 << 16) | MUX_PA14G_CATB_SENSE9) #define GPIO_PA14G_CATB_SENSE9 _UL_(1 << 14) #define PIN_PC07G_CATB_SENSE9 _L_(71) /**< \brief CATB signal: SENSE9 on PC07 mux G */ #define MUX_PC07G_CATB_SENSE9 _L_(6) #define PINMUX_PC07G_CATB_SENSE9 ((PIN_PC07G_CATB_SENSE9 << 16) | MUX_PC07G_CATB_SENSE9) #define GPIO_PC07G_CATB_SENSE9 _UL_(1 << 7) #define PIN_PA15G_CATB_SENSE10 _L_(15) /**< \brief CATB signal: SENSE10 on PA15 mux G */ #define MUX_PA15G_CATB_SENSE10 _L_(6) #define PINMUX_PA15G_CATB_SENSE10 ((PIN_PA15G_CATB_SENSE10 << 16) | MUX_PA15G_CATB_SENSE10) #define GPIO_PA15G_CATB_SENSE10 _UL_(1 << 15) #define PIN_PC08G_CATB_SENSE10 _L_(72) /**< \brief CATB signal: SENSE10 on PC08 mux G */ #define MUX_PC08G_CATB_SENSE10 _L_(6) #define PINMUX_PC08G_CATB_SENSE10 ((PIN_PC08G_CATB_SENSE10 << 16) | MUX_PC08G_CATB_SENSE10) #define GPIO_PC08G_CATB_SENSE10 _UL_(1 << 8) #define PIN_PA16G_CATB_SENSE11 _L_(16) /**< \brief CATB signal: SENSE11 on PA16 mux G */ #define MUX_PA16G_CATB_SENSE11 _L_(6) #define PINMUX_PA16G_CATB_SENSE11 ((PIN_PA16G_CATB_SENSE11 << 16) | MUX_PA16G_CATB_SENSE11) #define GPIO_PA16G_CATB_SENSE11 _UL_(1 << 16) #define PIN_PC09G_CATB_SENSE11 _L_(73) /**< \brief CATB signal: SENSE11 on PC09 mux G */ #define MUX_PC09G_CATB_SENSE11 _L_(6) #define PINMUX_PC09G_CATB_SENSE11 ((PIN_PC09G_CATB_SENSE11 << 16) | MUX_PC09G_CATB_SENSE11) #define GPIO_PC09G_CATB_SENSE11 _UL_(1 << 9) #define PIN_PA17G_CATB_SENSE12 _L_(17) /**< \brief CATB signal: SENSE12 on PA17 mux G */ #define MUX_PA17G_CATB_SENSE12 _L_(6) #define PINMUX_PA17G_CATB_SENSE12 ((PIN_PA17G_CATB_SENSE12 << 16) | MUX_PA17G_CATB_SENSE12) #define GPIO_PA17G_CATB_SENSE12 _UL_(1 << 17) #define PIN_PC10G_CATB_SENSE12 _L_(74) /**< \brief CATB signal: SENSE12 on PC10 mux G */ #define MUX_PC10G_CATB_SENSE12 _L_(6) #define PINMUX_PC10G_CATB_SENSE12 ((PIN_PC10G_CATB_SENSE12 << 16) | MUX_PC10G_CATB_SENSE12) #define GPIO_PC10G_CATB_SENSE12 _UL_(1 << 10) #define PIN_PA18G_CATB_SENSE13 _L_(18) /**< \brief CATB signal: SENSE13 on PA18 mux G */ #define MUX_PA18G_CATB_SENSE13 _L_(6) #define PINMUX_PA18G_CATB_SENSE13 ((PIN_PA18G_CATB_SENSE13 << 16) | MUX_PA18G_CATB_SENSE13) #define GPIO_PA18G_CATB_SENSE13 _UL_(1 << 18) #define PIN_PC11G_CATB_SENSE13 _L_(75) /**< \brief CATB signal: SENSE13 on PC11 mux G */ #define MUX_PC11G_CATB_SENSE13 _L_(6) #define PINMUX_PC11G_CATB_SENSE13 ((PIN_PC11G_CATB_SENSE13 << 16) | MUX_PC11G_CATB_SENSE13) #define GPIO_PC11G_CATB_SENSE13 _UL_(1 << 11) #define PIN_PA19G_CATB_SENSE14 _L_(19) /**< \brief CATB signal: SENSE14 on PA19 mux G */ #define MUX_PA19G_CATB_SENSE14 _L_(6) #define PINMUX_PA19G_CATB_SENSE14 ((PIN_PA19G_CATB_SENSE14 << 16) | MUX_PA19G_CATB_SENSE14) #define GPIO_PA19G_CATB_SENSE14 _UL_(1 << 19) #define PIN_PC12G_CATB_SENSE14 _L_(76) /**< \brief CATB signal: SENSE14 on PC12 mux G */ #define MUX_PC12G_CATB_SENSE14 _L_(6) #define PINMUX_PC12G_CATB_SENSE14 ((PIN_PC12G_CATB_SENSE14 << 16) | MUX_PC12G_CATB_SENSE14) #define GPIO_PC12G_CATB_SENSE14 _UL_(1 << 12) #define PIN_PA20G_CATB_SENSE15 _L_(20) /**< \brief CATB signal: SENSE15 on PA20 mux G */ #define MUX_PA20G_CATB_SENSE15 _L_(6) #define PINMUX_PA20G_CATB_SENSE15 ((PIN_PA20G_CATB_SENSE15 << 16) | MUX_PA20G_CATB_SENSE15) #define GPIO_PA20G_CATB_SENSE15 _UL_(1 << 20) #define PIN_PC13G_CATB_SENSE15 _L_(77) /**< \brief CATB signal: SENSE15 on PC13 mux G */ #define MUX_PC13G_CATB_SENSE15 _L_(6) #define PINMUX_PC13G_CATB_SENSE15 ((PIN_PC13G_CATB_SENSE15 << 16) | MUX_PC13G_CATB_SENSE15) #define GPIO_PC13G_CATB_SENSE15 _UL_(1 << 13) #define PIN_PA21G_CATB_SENSE16 _L_(21) /**< \brief CATB signal: SENSE16 on PA21 mux G */ #define MUX_PA21G_CATB_SENSE16 _L_(6) #define PINMUX_PA21G_CATB_SENSE16 ((PIN_PA21G_CATB_SENSE16 << 16) | MUX_PA21G_CATB_SENSE16) #define GPIO_PA21G_CATB_SENSE16 _UL_(1 << 21) #define PIN_PC15G_CATB_SENSE16 _L_(79) /**< \brief CATB signal: SENSE16 on PC15 mux G */ #define MUX_PC15G_CATB_SENSE16 _L_(6) #define PINMUX_PC15G_CATB_SENSE16 ((PIN_PC15G_CATB_SENSE16 << 16) | MUX_PC15G_CATB_SENSE16) #define GPIO_PC15G_CATB_SENSE16 _UL_(1 << 15) #define PIN_PA22G_CATB_SENSE17 _L_(22) /**< \brief CATB signal: SENSE17 on PA22 mux G */ #define MUX_PA22G_CATB_SENSE17 _L_(6) #define PINMUX_PA22G_CATB_SENSE17 ((PIN_PA22G_CATB_SENSE17 << 16) | MUX_PA22G_CATB_SENSE17) #define GPIO_PA22G_CATB_SENSE17 _UL_(1 << 22) #define PIN_PC16G_CATB_SENSE17 _L_(80) /**< \brief CATB signal: SENSE17 on PC16 mux G */ #define MUX_PC16G_CATB_SENSE17 _L_(6) #define PINMUX_PC16G_CATB_SENSE17 ((PIN_PC16G_CATB_SENSE17 << 16) | MUX_PC16G_CATB_SENSE17) #define GPIO_PC16G_CATB_SENSE17 _UL_(1 << 16) #define PIN_PA24G_CATB_SENSE18 _L_(24) /**< \brief CATB signal: SENSE18 on PA24 mux G */ #define MUX_PA24G_CATB_SENSE18 _L_(6) #define PINMUX_PA24G_CATB_SENSE18 ((PIN_PA24G_CATB_SENSE18 << 16) | MUX_PA24G_CATB_SENSE18) #define GPIO_PA24G_CATB_SENSE18 _UL_(1 << 24) #define PIN_PC17G_CATB_SENSE18 _L_(81) /**< \brief CATB signal: SENSE18 on PC17 mux G */ #define MUX_PC17G_CATB_SENSE18 _L_(6) #define PINMUX_PC17G_CATB_SENSE18 ((PIN_PC17G_CATB_SENSE18 << 16) | MUX_PC17G_CATB_SENSE18) #define GPIO_PC17G_CATB_SENSE18 _UL_(1 << 17) #define PIN_PA25G_CATB_SENSE19 _L_(25) /**< \brief CATB signal: SENSE19 on PA25 mux G */ #define MUX_PA25G_CATB_SENSE19 _L_(6) #define PINMUX_PA25G_CATB_SENSE19 ((PIN_PA25G_CATB_SENSE19 << 16) | MUX_PA25G_CATB_SENSE19) #define GPIO_PA25G_CATB_SENSE19 _UL_(1 << 25) #define PIN_PC18G_CATB_SENSE19 _L_(82) /**< \brief CATB signal: SENSE19 on PC18 mux G */ #define MUX_PC18G_CATB_SENSE19 _L_(6) #define PINMUX_PC18G_CATB_SENSE19 ((PIN_PC18G_CATB_SENSE19 << 16) | MUX_PC18G_CATB_SENSE19) #define GPIO_PC18G_CATB_SENSE19 _UL_(1 << 18) #define PIN_PA26G_CATB_SENSE20 _L_(26) /**< \brief CATB signal: SENSE20 on PA26 mux G */ #define MUX_PA26G_CATB_SENSE20 _L_(6) #define PINMUX_PA26G_CATB_SENSE20 ((PIN_PA26G_CATB_SENSE20 << 16) | MUX_PA26G_CATB_SENSE20) #define GPIO_PA26G_CATB_SENSE20 _UL_(1 << 26) #define PIN_PC19G_CATB_SENSE20 _L_(83) /**< \brief CATB signal: SENSE20 on PC19 mux G */ #define MUX_PC19G_CATB_SENSE20 _L_(6) #define PINMUX_PC19G_CATB_SENSE20 ((PIN_PC19G_CATB_SENSE20 << 16) | MUX_PC19G_CATB_SENSE20) #define GPIO_PC19G_CATB_SENSE20 _UL_(1 << 19) #define PIN_PB00G_CATB_SENSE21 _L_(32) /**< \brief CATB signal: SENSE21 on PB00 mux G */ #define MUX_PB00G_CATB_SENSE21 _L_(6) #define PINMUX_PB00G_CATB_SENSE21 ((PIN_PB00G_CATB_SENSE21 << 16) | MUX_PB00G_CATB_SENSE21) #define GPIO_PB00G_CATB_SENSE21 _UL_(1 << 0) #define PIN_PC20G_CATB_SENSE21 _L_(84) /**< \brief CATB signal: SENSE21 on PC20 mux G */ #define MUX_PC20G_CATB_SENSE21 _L_(6) #define PINMUX_PC20G_CATB_SENSE21 ((PIN_PC20G_CATB_SENSE21 << 16) | MUX_PC20G_CATB_SENSE21) #define GPIO_PC20G_CATB_SENSE21 _UL_(1 << 20) #define PIN_PB01G_CATB_SENSE22 _L_(33) /**< \brief CATB signal: SENSE22 on PB01 mux G */ #define MUX_PB01G_CATB_SENSE22 _L_(6) #define PINMUX_PB01G_CATB_SENSE22 ((PIN_PB01G_CATB_SENSE22 << 16) | MUX_PB01G_CATB_SENSE22) #define GPIO_PB01G_CATB_SENSE22 _UL_(1 << 1) #define PIN_PC21G_CATB_SENSE22 _L_(85) /**< \brief CATB signal: SENSE22 on PC21 mux G */ #define MUX_PC21G_CATB_SENSE22 _L_(6) #define PINMUX_PC21G_CATB_SENSE22 ((PIN_PC21G_CATB_SENSE22 << 16) | MUX_PC21G_CATB_SENSE22) #define GPIO_PC21G_CATB_SENSE22 _UL_(1 << 21) #define PIN_PB02G_CATB_SENSE23 _L_(34) /**< \brief CATB signal: SENSE23 on PB02 mux G */ #define MUX_PB02G_CATB_SENSE23 _L_(6) #define PINMUX_PB02G_CATB_SENSE23 ((PIN_PB02G_CATB_SENSE23 << 16) | MUX_PB02G_CATB_SENSE23) #define GPIO_PB02G_CATB_SENSE23 _UL_(1 << 2) #define PIN_PC22G_CATB_SENSE23 _L_(86) /**< \brief CATB signal: SENSE23 on PC22 mux G */ #define MUX_PC22G_CATB_SENSE23 _L_(6) #define PINMUX_PC22G_CATB_SENSE23 ((PIN_PC22G_CATB_SENSE23 << 16) | MUX_PC22G_CATB_SENSE23) #define GPIO_PC22G_CATB_SENSE23 _UL_(1 << 22) #define PIN_PB04G_CATB_SENSE24 _L_(36) /**< \brief CATB signal: SENSE24 on PB04 mux G */ #define MUX_PB04G_CATB_SENSE24 _L_(6) #define PINMUX_PB04G_CATB_SENSE24 ((PIN_PB04G_CATB_SENSE24 << 16) | MUX_PB04G_CATB_SENSE24) #define GPIO_PB04G_CATB_SENSE24 _UL_(1 << 4) #define PIN_PC24G_CATB_SENSE24 _L_(88) /**< \brief CATB signal: SENSE24 on PC24 mux G */ #define MUX_PC24G_CATB_SENSE24 _L_(6) #define PINMUX_PC24G_CATB_SENSE24 ((PIN_PC24G_CATB_SENSE24 << 16) | MUX_PC24G_CATB_SENSE24) #define GPIO_PC24G_CATB_SENSE24 _UL_(1 << 24) #define PIN_PB05G_CATB_SENSE25 _L_(37) /**< \brief CATB signal: SENSE25 on PB05 mux G */ #define MUX_PB05G_CATB_SENSE25 _L_(6) #define PINMUX_PB05G_CATB_SENSE25 ((PIN_PB05G_CATB_SENSE25 << 16) | MUX_PB05G_CATB_SENSE25) #define GPIO_PB05G_CATB_SENSE25 _UL_(1 << 5) #define PIN_PC25G_CATB_SENSE25 _L_(89) /**< \brief CATB signal: SENSE25 on PC25 mux G */ #define MUX_PC25G_CATB_SENSE25 _L_(6) #define PINMUX_PC25G_CATB_SENSE25 ((PIN_PC25G_CATB_SENSE25 << 16) | MUX_PC25G_CATB_SENSE25) #define GPIO_PC25G_CATB_SENSE25 _UL_(1 << 25) #define PIN_PB06G_CATB_SENSE26 _L_(38) /**< \brief CATB signal: SENSE26 on PB06 mux G */ #define MUX_PB06G_CATB_SENSE26 _L_(6) #define PINMUX_PB06G_CATB_SENSE26 ((PIN_PB06G_CATB_SENSE26 << 16) | MUX_PB06G_CATB_SENSE26) #define GPIO_PB06G_CATB_SENSE26 _UL_(1 << 6) #define PIN_PC26G_CATB_SENSE26 _L_(90) /**< \brief CATB signal: SENSE26 on PC26 mux G */ #define MUX_PC26G_CATB_SENSE26 _L_(6) #define PINMUX_PC26G_CATB_SENSE26 ((PIN_PC26G_CATB_SENSE26 << 16) | MUX_PC26G_CATB_SENSE26) #define GPIO_PC26G_CATB_SENSE26 _UL_(1 << 26) #define PIN_PB07G_CATB_SENSE27 _L_(39) /**< \brief CATB signal: SENSE27 on PB07 mux G */ #define MUX_PB07G_CATB_SENSE27 _L_(6) #define PINMUX_PB07G_CATB_SENSE27 ((PIN_PB07G_CATB_SENSE27 << 16) | MUX_PB07G_CATB_SENSE27) #define GPIO_PB07G_CATB_SENSE27 _UL_(1 << 7) #define PIN_PC27G_CATB_SENSE27 _L_(91) /**< \brief CATB signal: SENSE27 on PC27 mux G */ #define MUX_PC27G_CATB_SENSE27 _L_(6) #define PINMUX_PC27G_CATB_SENSE27 ((PIN_PC27G_CATB_SENSE27 << 16) | MUX_PC27G_CATB_SENSE27) #define GPIO_PC27G_CATB_SENSE27 _UL_(1 << 27) #define PIN_PB08G_CATB_SENSE28 _L_(40) /**< \brief CATB signal: SENSE28 on PB08 mux G */ #define MUX_PB08G_CATB_SENSE28 _L_(6) #define PINMUX_PB08G_CATB_SENSE28 ((PIN_PB08G_CATB_SENSE28 << 16) | MUX_PB08G_CATB_SENSE28) #define GPIO_PB08G_CATB_SENSE28 _UL_(1 << 8) #define PIN_PC28G_CATB_SENSE28 _L_(92) /**< \brief CATB signal: SENSE28 on PC28 mux G */ #define MUX_PC28G_CATB_SENSE28 _L_(6) #define PINMUX_PC28G_CATB_SENSE28 ((PIN_PC28G_CATB_SENSE28 << 16) | MUX_PC28G_CATB_SENSE28) #define GPIO_PC28G_CATB_SENSE28 _UL_(1 << 28) #define PIN_PB09G_CATB_SENSE29 _L_(41) /**< \brief CATB signal: SENSE29 on PB09 mux G */ #define MUX_PB09G_CATB_SENSE29 _L_(6) #define PINMUX_PB09G_CATB_SENSE29 ((PIN_PB09G_CATB_SENSE29 << 16) | MUX_PB09G_CATB_SENSE29) #define GPIO_PB09G_CATB_SENSE29 _UL_(1 << 9) #define PIN_PC29G_CATB_SENSE29 _L_(93) /**< \brief CATB signal: SENSE29 on PC29 mux G */ #define MUX_PC29G_CATB_SENSE29 _L_(6) #define PINMUX_PC29G_CATB_SENSE29 ((PIN_PC29G_CATB_SENSE29 << 16) | MUX_PC29G_CATB_SENSE29) #define GPIO_PC29G_CATB_SENSE29 _UL_(1 << 29) #define PIN_PB10G_CATB_SENSE30 _L_(42) /**< \brief CATB signal: SENSE30 on PB10 mux G */ #define MUX_PB10G_CATB_SENSE30 _L_(6) #define PINMUX_PB10G_CATB_SENSE30 ((PIN_PB10G_CATB_SENSE30 << 16) | MUX_PB10G_CATB_SENSE30) #define GPIO_PB10G_CATB_SENSE30 _UL_(1 << 10) #define PIN_PC30G_CATB_SENSE30 _L_(94) /**< \brief CATB signal: SENSE30 on PC30 mux G */ #define MUX_PC30G_CATB_SENSE30 _L_(6) #define PINMUX_PC30G_CATB_SENSE30 ((PIN_PC30G_CATB_SENSE30 << 16) | MUX_PC30G_CATB_SENSE30) #define GPIO_PC30G_CATB_SENSE30 _UL_(1 << 30) #define PIN_PB11G_CATB_SENSE31 _L_(43) /**< \brief CATB signal: SENSE31 on PB11 mux G */ #define MUX_PB11G_CATB_SENSE31 _L_(6) #define PINMUX_PB11G_CATB_SENSE31 ((PIN_PB11G_CATB_SENSE31 << 16) | MUX_PB11G_CATB_SENSE31) #define GPIO_PB11G_CATB_SENSE31 _UL_(1 << 11) #define PIN_PC31G_CATB_SENSE31 _L_(95) /**< \brief CATB signal: SENSE31 on PC31 mux G */ #define MUX_PC31G_CATB_SENSE31 _L_(6) #define PINMUX_PC31G_CATB_SENSE31 ((PIN_PC31G_CATB_SENSE31 << 16) | MUX_PC31G_CATB_SENSE31) #define GPIO_PC31G_CATB_SENSE31 _UL_(1 << 31) /* ========== GPIO definition for LCDCA peripheral ========== */ #define PIN_PA12F_LCDCA_COM0 _L_(12) /**< \brief LCDCA signal: COM0 on PA12 mux F */ #define MUX_PA12F_LCDCA_COM0 _L_(5) #define PINMUX_PA12F_LCDCA_COM0 ((PIN_PA12F_LCDCA_COM0 << 16) | MUX_PA12F_LCDCA_COM0) #define GPIO_PA12F_LCDCA_COM0 _UL_(1 << 12) #define PIN_PA11F_LCDCA_COM1 _L_(11) /**< \brief LCDCA signal: COM1 on PA11 mux F */ #define MUX_PA11F_LCDCA_COM1 _L_(5) #define PINMUX_PA11F_LCDCA_COM1 ((PIN_PA11F_LCDCA_COM1 << 16) | MUX_PA11F_LCDCA_COM1) #define GPIO_PA11F_LCDCA_COM1 _UL_(1 << 11) #define PIN_PA10F_LCDCA_COM2 _L_(10) /**< \brief LCDCA signal: COM2 on PA10 mux F */ #define MUX_PA10F_LCDCA_COM2 _L_(5) #define PINMUX_PA10F_LCDCA_COM2 ((PIN_PA10F_LCDCA_COM2 << 16) | MUX_PA10F_LCDCA_COM2) #define GPIO_PA10F_LCDCA_COM2 _UL_(1 << 10) #define PIN_PA09F_LCDCA_COM3 _L_(9) /**< \brief LCDCA signal: COM3 on PA09 mux F */ #define MUX_PA09F_LCDCA_COM3 _L_(5) #define PINMUX_PA09F_LCDCA_COM3 ((PIN_PA09F_LCDCA_COM3 << 16) | MUX_PA09F_LCDCA_COM3) #define GPIO_PA09F_LCDCA_COM3 _UL_(1 << 9) #define PIN_PC15F_LCDCA_SEG0 _L_(79) /**< \brief LCDCA signal: SEG0 on PC15 mux F */ #define MUX_PC15F_LCDCA_SEG0 _L_(5) #define PINMUX_PC15F_LCDCA_SEG0 ((PIN_PC15F_LCDCA_SEG0 << 16) | MUX_PC15F_LCDCA_SEG0) #define GPIO_PC15F_LCDCA_SEG0 _UL_(1 << 15) #define PIN_PC16F_LCDCA_SEG1 _L_(80) /**< \brief LCDCA signal: SEG1 on PC16 mux F */ #define MUX_PC16F_LCDCA_SEG1 _L_(5) #define PINMUX_PC16F_LCDCA_SEG1 ((PIN_PC16F_LCDCA_SEG1 << 16) | MUX_PC16F_LCDCA_SEG1) #define GPIO_PC16F_LCDCA_SEG1 _UL_(1 << 16) #define PIN_PC17F_LCDCA_SEG2 _L_(81) /**< \brief LCDCA signal: SEG2 on PC17 mux F */ #define MUX_PC17F_LCDCA_SEG2 _L_(5) #define PINMUX_PC17F_LCDCA_SEG2 ((PIN_PC17F_LCDCA_SEG2 << 16) | MUX_PC17F_LCDCA_SEG2) #define GPIO_PC17F_LCDCA_SEG2 _UL_(1 << 17) #define PIN_PC18F_LCDCA_SEG3 _L_(82) /**< \brief LCDCA signal: SEG3 on PC18 mux F */ #define MUX_PC18F_LCDCA_SEG3 _L_(5) #define PINMUX_PC18F_LCDCA_SEG3 ((PIN_PC18F_LCDCA_SEG3 << 16) | MUX_PC18F_LCDCA_SEG3) #define GPIO_PC18F_LCDCA_SEG3 _UL_(1 << 18) #define PIN_PC19F_LCDCA_SEG4 _L_(83) /**< \brief LCDCA signal: SEG4 on PC19 mux F */ #define MUX_PC19F_LCDCA_SEG4 _L_(5) #define PINMUX_PC19F_LCDCA_SEG4 ((PIN_PC19F_LCDCA_SEG4 << 16) | MUX_PC19F_LCDCA_SEG4) #define GPIO_PC19F_LCDCA_SEG4 _UL_(1 << 19) #define PIN_PA13F_LCDCA_SEG5 _L_(13) /**< \brief LCDCA signal: SEG5 on PA13 mux F */ #define MUX_PA13F_LCDCA_SEG5 _L_(5) #define PINMUX_PA13F_LCDCA_SEG5 ((PIN_PA13F_LCDCA_SEG5 << 16) | MUX_PA13F_LCDCA_SEG5) #define GPIO_PA13F_LCDCA_SEG5 _UL_(1 << 13) #define PIN_PA14F_LCDCA_SEG6 _L_(14) /**< \brief LCDCA signal: SEG6 on PA14 mux F */ #define MUX_PA14F_LCDCA_SEG6 _L_(5) #define PINMUX_PA14F_LCDCA_SEG6 ((PIN_PA14F_LCDCA_SEG6 << 16) | MUX_PA14F_LCDCA_SEG6) #define GPIO_PA14F_LCDCA_SEG6 _UL_(1 << 14) #define PIN_PA15F_LCDCA_SEG7 _L_(15) /**< \brief LCDCA signal: SEG7 on PA15 mux F */ #define MUX_PA15F_LCDCA_SEG7 _L_(5) #define PINMUX_PA15F_LCDCA_SEG7 ((PIN_PA15F_LCDCA_SEG7 << 16) | MUX_PA15F_LCDCA_SEG7) #define GPIO_PA15F_LCDCA_SEG7 _UL_(1 << 15) #define PIN_PA16F_LCDCA_SEG8 _L_(16) /**< \brief LCDCA signal: SEG8 on PA16 mux F */ #define MUX_PA16F_LCDCA_SEG8 _L_(5) #define PINMUX_PA16F_LCDCA_SEG8 ((PIN_PA16F_LCDCA_SEG8 << 16) | MUX_PA16F_LCDCA_SEG8) #define GPIO_PA16F_LCDCA_SEG8 _UL_(1 << 16) #define PIN_PA17F_LCDCA_SEG9 _L_(17) /**< \brief LCDCA signal: SEG9 on PA17 mux F */ #define MUX_PA17F_LCDCA_SEG9 _L_(5) #define PINMUX_PA17F_LCDCA_SEG9 ((PIN_PA17F_LCDCA_SEG9 << 16) | MUX_PA17F_LCDCA_SEG9) #define GPIO_PA17F_LCDCA_SEG9 _UL_(1 << 17) #define PIN_PC20F_LCDCA_SEG10 _L_(84) /**< \brief LCDCA signal: SEG10 on PC20 mux F */ #define MUX_PC20F_LCDCA_SEG10 _L_(5) #define PINMUX_PC20F_LCDCA_SEG10 ((PIN_PC20F_LCDCA_SEG10 << 16) | MUX_PC20F_LCDCA_SEG10) #define GPIO_PC20F_LCDCA_SEG10 _UL_(1 << 20) #define PIN_PC21F_LCDCA_SEG11 _L_(85) /**< \brief LCDCA signal: SEG11 on PC21 mux F */ #define MUX_PC21F_LCDCA_SEG11 _L_(5) #define PINMUX_PC21F_LCDCA_SEG11 ((PIN_PC21F_LCDCA_SEG11 << 16) | MUX_PC21F_LCDCA_SEG11) #define GPIO_PC21F_LCDCA_SEG11 _UL_(1 << 21) #define PIN_PC22F_LCDCA_SEG12 _L_(86) /**< \brief LCDCA signal: SEG12 on PC22 mux F */ #define MUX_PC22F_LCDCA_SEG12 _L_(5) #define PINMUX_PC22F_LCDCA_SEG12 ((PIN_PC22F_LCDCA_SEG12 << 16) | MUX_PC22F_LCDCA_SEG12) #define GPIO_PC22F_LCDCA_SEG12 _UL_(1 << 22) #define PIN_PC23F_LCDCA_SEG13 _L_(87) /**< \brief LCDCA signal: SEG13 on PC23 mux F */ #define MUX_PC23F_LCDCA_SEG13 _L_(5) #define PINMUX_PC23F_LCDCA_SEG13 ((PIN_PC23F_LCDCA_SEG13 << 16) | MUX_PC23F_LCDCA_SEG13) #define GPIO_PC23F_LCDCA_SEG13 _UL_(1 << 23) #define PIN_PB08F_LCDCA_SEG14 _L_(40) /**< \brief LCDCA signal: SEG14 on PB08 mux F */ #define MUX_PB08F_LCDCA_SEG14 _L_(5) #define PINMUX_PB08F_LCDCA_SEG14 ((PIN_PB08F_LCDCA_SEG14 << 16) | MUX_PB08F_LCDCA_SEG14) #define GPIO_PB08F_LCDCA_SEG14 _UL_(1 << 8) #define PIN_PB09F_LCDCA_SEG15 _L_(41) /**< \brief LCDCA signal: SEG15 on PB09 mux F */ #define MUX_PB09F_LCDCA_SEG15 _L_(5) #define PINMUX_PB09F_LCDCA_SEG15 ((PIN_PB09F_LCDCA_SEG15 << 16) | MUX_PB09F_LCDCA_SEG15) #define GPIO_PB09F_LCDCA_SEG15 _UL_(1 << 9) #define PIN_PB10F_LCDCA_SEG16 _L_(42) /**< \brief LCDCA signal: SEG16 on PB10 mux F */ #define MUX_PB10F_LCDCA_SEG16 _L_(5) #define PINMUX_PB10F_LCDCA_SEG16 ((PIN_PB10F_LCDCA_SEG16 << 16) | MUX_PB10F_LCDCA_SEG16) #define GPIO_PB10F_LCDCA_SEG16 _UL_(1 << 10) #define PIN_PB11F_LCDCA_SEG17 _L_(43) /**< \brief LCDCA signal: SEG17 on PB11 mux F */ #define MUX_PB11F_LCDCA_SEG17 _L_(5) #define PINMUX_PB11F_LCDCA_SEG17 ((PIN_PB11F_LCDCA_SEG17 << 16) | MUX_PB11F_LCDCA_SEG17) #define GPIO_PB11F_LCDCA_SEG17 _UL_(1 << 11) #define PIN_PA18F_LCDCA_SEG18 _L_(18) /**< \brief LCDCA signal: SEG18 on PA18 mux F */ #define MUX_PA18F_LCDCA_SEG18 _L_(5) #define PINMUX_PA18F_LCDCA_SEG18 ((PIN_PA18F_LCDCA_SEG18 << 16) | MUX_PA18F_LCDCA_SEG18) #define GPIO_PA18F_LCDCA_SEG18 _UL_(1 << 18) #define PIN_PA19F_LCDCA_SEG19 _L_(19) /**< \brief LCDCA signal: SEG19 on PA19 mux F */ #define MUX_PA19F_LCDCA_SEG19 _L_(5) #define PINMUX_PA19F_LCDCA_SEG19 ((PIN_PA19F_LCDCA_SEG19 << 16) | MUX_PA19F_LCDCA_SEG19) #define GPIO_PA19F_LCDCA_SEG19 _UL_(1 << 19) #define PIN_PA20F_LCDCA_SEG20 _L_(20) /**< \brief LCDCA signal: SEG20 on PA20 mux F */ #define MUX_PA20F_LCDCA_SEG20 _L_(5) #define PINMUX_PA20F_LCDCA_SEG20 ((PIN_PA20F_LCDCA_SEG20 << 16) | MUX_PA20F_LCDCA_SEG20) #define GPIO_PA20F_LCDCA_SEG20 _UL_(1 << 20) #define PIN_PB07F_LCDCA_SEG21 _L_(39) /**< \brief LCDCA signal: SEG21 on PB07 mux F */ #define MUX_PB07F_LCDCA_SEG21 _L_(5) #define PINMUX_PB07F_LCDCA_SEG21 ((PIN_PB07F_LCDCA_SEG21 << 16) | MUX_PB07F_LCDCA_SEG21) #define GPIO_PB07F_LCDCA_SEG21 _UL_(1 << 7) #define PIN_PB06F_LCDCA_SEG22 _L_(38) /**< \brief LCDCA signal: SEG22 on PB06 mux F */ #define MUX_PB06F_LCDCA_SEG22 _L_(5) #define PINMUX_PB06F_LCDCA_SEG22 ((PIN_PB06F_LCDCA_SEG22 << 16) | MUX_PB06F_LCDCA_SEG22) #define GPIO_PB06F_LCDCA_SEG22 _UL_(1 << 6) #define PIN_PA08F_LCDCA_SEG23 _L_(8) /**< \brief LCDCA signal: SEG23 on PA08 mux F */ #define MUX_PA08F_LCDCA_SEG23 _L_(5) #define PINMUX_PA08F_LCDCA_SEG23 ((PIN_PA08F_LCDCA_SEG23 << 16) | MUX_PA08F_LCDCA_SEG23) #define GPIO_PA08F_LCDCA_SEG23 _UL_(1 << 8) #define PIN_PC24F_LCDCA_SEG24 _L_(88) /**< \brief LCDCA signal: SEG24 on PC24 mux F */ #define MUX_PC24F_LCDCA_SEG24 _L_(5) #define PINMUX_PC24F_LCDCA_SEG24 ((PIN_PC24F_LCDCA_SEG24 << 16) | MUX_PC24F_LCDCA_SEG24) #define GPIO_PC24F_LCDCA_SEG24 _UL_(1 << 24) #define PIN_PC25F_LCDCA_SEG25 _L_(89) /**< \brief LCDCA signal: SEG25 on PC25 mux F */ #define MUX_PC25F_LCDCA_SEG25 _L_(5) #define PINMUX_PC25F_LCDCA_SEG25 ((PIN_PC25F_LCDCA_SEG25 << 16) | MUX_PC25F_LCDCA_SEG25) #define GPIO_PC25F_LCDCA_SEG25 _UL_(1 << 25) #define PIN_PC26F_LCDCA_SEG26 _L_(90) /**< \brief LCDCA signal: SEG26 on PC26 mux F */ #define MUX_PC26F_LCDCA_SEG26 _L_(5) #define PINMUX_PC26F_LCDCA_SEG26 ((PIN_PC26F_LCDCA_SEG26 << 16) | MUX_PC26F_LCDCA_SEG26) #define GPIO_PC26F_LCDCA_SEG26 _UL_(1 << 26) #define PIN_PC27F_LCDCA_SEG27 _L_(91) /**< \brief LCDCA signal: SEG27 on PC27 mux F */ #define MUX_PC27F_LCDCA_SEG27 _L_(5) #define PINMUX_PC27F_LCDCA_SEG27 ((PIN_PC27F_LCDCA_SEG27 << 16) | MUX_PC27F_LCDCA_SEG27) #define GPIO_PC27F_LCDCA_SEG27 _UL_(1 << 27) #define PIN_PC28F_LCDCA_SEG28 _L_(92) /**< \brief LCDCA signal: SEG28 on PC28 mux F */ #define MUX_PC28F_LCDCA_SEG28 _L_(5) #define PINMUX_PC28F_LCDCA_SEG28 ((PIN_PC28F_LCDCA_SEG28 << 16) | MUX_PC28F_LCDCA_SEG28) #define GPIO_PC28F_LCDCA_SEG28 _UL_(1 << 28) #define PIN_PC29F_LCDCA_SEG29 _L_(93) /**< \brief LCDCA signal: SEG29 on PC29 mux F */ #define MUX_PC29F_LCDCA_SEG29 _L_(5) #define PINMUX_PC29F_LCDCA_SEG29 ((PIN_PC29F_LCDCA_SEG29 << 16) | MUX_PC29F_LCDCA_SEG29) #define GPIO_PC29F_LCDCA_SEG29 _UL_(1 << 29) #define PIN_PC30F_LCDCA_SEG30 _L_(94) /**< \brief LCDCA signal: SEG30 on PC30 mux F */ #define MUX_PC30F_LCDCA_SEG30 _L_(5) #define PINMUX_PC30F_LCDCA_SEG30 ((PIN_PC30F_LCDCA_SEG30 << 16) | MUX_PC30F_LCDCA_SEG30) #define GPIO_PC30F_LCDCA_SEG30 _UL_(1 << 30) #define PIN_PC31F_LCDCA_SEG31 _L_(95) /**< \brief LCDCA signal: SEG31 on PC31 mux F */ #define MUX_PC31F_LCDCA_SEG31 _L_(5) #define PINMUX_PC31F_LCDCA_SEG31 ((PIN_PC31F_LCDCA_SEG31 << 16) | MUX_PC31F_LCDCA_SEG31) #define GPIO_PC31F_LCDCA_SEG31 _UL_(1 << 31) #define PIN_PB12F_LCDCA_SEG32 _L_(44) /**< \brief LCDCA signal: SEG32 on PB12 mux F */ #define MUX_PB12F_LCDCA_SEG32 _L_(5) #define PINMUX_PB12F_LCDCA_SEG32 ((PIN_PB12F_LCDCA_SEG32 << 16) | MUX_PB12F_LCDCA_SEG32) #define GPIO_PB12F_LCDCA_SEG32 _UL_(1 << 12) #define PIN_PB13F_LCDCA_SEG33 _L_(45) /**< \brief LCDCA signal: SEG33 on PB13 mux F */ #define MUX_PB13F_LCDCA_SEG33 _L_(5) #define PINMUX_PB13F_LCDCA_SEG33 ((PIN_PB13F_LCDCA_SEG33 << 16) | MUX_PB13F_LCDCA_SEG33) #define GPIO_PB13F_LCDCA_SEG33 _UL_(1 << 13) #define PIN_PA21F_LCDCA_SEG34 _L_(21) /**< \brief LCDCA signal: SEG34 on PA21 mux F */ #define MUX_PA21F_LCDCA_SEG34 _L_(5) #define PINMUX_PA21F_LCDCA_SEG34 ((PIN_PA21F_LCDCA_SEG34 << 16) | MUX_PA21F_LCDCA_SEG34) #define GPIO_PA21F_LCDCA_SEG34 _UL_(1 << 21) #define PIN_PA22F_LCDCA_SEG35 _L_(22) /**< \brief LCDCA signal: SEG35 on PA22 mux F */ #define MUX_PA22F_LCDCA_SEG35 _L_(5) #define PINMUX_PA22F_LCDCA_SEG35 ((PIN_PA22F_LCDCA_SEG35 << 16) | MUX_PA22F_LCDCA_SEG35) #define GPIO_PA22F_LCDCA_SEG35 _UL_(1 << 22) #define PIN_PB14F_LCDCA_SEG36 _L_(46) /**< \brief LCDCA signal: SEG36 on PB14 mux F */ #define MUX_PB14F_LCDCA_SEG36 _L_(5) #define PINMUX_PB14F_LCDCA_SEG36 ((PIN_PB14F_LCDCA_SEG36 << 16) | MUX_PB14F_LCDCA_SEG36) #define GPIO_PB14F_LCDCA_SEG36 _UL_(1 << 14) #define PIN_PB15F_LCDCA_SEG37 _L_(47) /**< \brief LCDCA signal: SEG37 on PB15 mux F */ #define MUX_PB15F_LCDCA_SEG37 _L_(5) #define PINMUX_PB15F_LCDCA_SEG37 ((PIN_PB15F_LCDCA_SEG37 << 16) | MUX_PB15F_LCDCA_SEG37) #define GPIO_PB15F_LCDCA_SEG37 _UL_(1 << 15) #define PIN_PA23F_LCDCA_SEG38 _L_(23) /**< \brief LCDCA signal: SEG38 on PA23 mux F */ #define MUX_PA23F_LCDCA_SEG38 _L_(5) #define PINMUX_PA23F_LCDCA_SEG38 ((PIN_PA23F_LCDCA_SEG38 << 16) | MUX_PA23F_LCDCA_SEG38) #define GPIO_PA23F_LCDCA_SEG38 _UL_(1 << 23) #define PIN_PA24F_LCDCA_SEG39 _L_(24) /**< \brief LCDCA signal: SEG39 on PA24 mux F */ #define MUX_PA24F_LCDCA_SEG39 _L_(5) #define PINMUX_PA24F_LCDCA_SEG39 ((PIN_PA24F_LCDCA_SEG39 << 16) | MUX_PA24F_LCDCA_SEG39) #define GPIO_PA24F_LCDCA_SEG39 _UL_(1 << 24) /* ========== GPIO definition for USBC peripheral ========== */ #define PIN_PA25A_USBC_DM _L_(25) /**< \brief USBC signal: DM on PA25 mux A */ #define MUX_PA25A_USBC_DM _L_(0) #define PINMUX_PA25A_USBC_DM ((PIN_PA25A_USBC_DM << 16) | MUX_PA25A_USBC_DM) #define GPIO_PA25A_USBC_DM _UL_(1 << 25) #define PIN_PA26A_USBC_DP _L_(26) /**< \brief USBC signal: DP on PA26 mux A */ #define MUX_PA26A_USBC_DP _L_(0) #define PINMUX_PA26A_USBC_DP ((PIN_PA26A_USBC_DP << 16) | MUX_PA26A_USBC_DP) #define GPIO_PA26A_USBC_DP _UL_(1 << 26) /* ========== GPIO definition for PEVC peripheral ========== */ #define PIN_PA08C_PEVC_PAD_EVT0 _L_(8) /**< \brief PEVC signal: PAD_EVT0 on PA08 mux C */ #define MUX_PA08C_PEVC_PAD_EVT0 _L_(2) #define PINMUX_PA08C_PEVC_PAD_EVT0 ((PIN_PA08C_PEVC_PAD_EVT0 << 16) | MUX_PA08C_PEVC_PAD_EVT0) #define GPIO_PA08C_PEVC_PAD_EVT0 _UL_(1 << 8) #define PIN_PB12C_PEVC_PAD_EVT0 _L_(44) /**< \brief PEVC signal: PAD_EVT0 on PB12 mux C */ #define MUX_PB12C_PEVC_PAD_EVT0 _L_(2) #define PINMUX_PB12C_PEVC_PAD_EVT0 ((PIN_PB12C_PEVC_PAD_EVT0 << 16) | MUX_PB12C_PEVC_PAD_EVT0) #define GPIO_PB12C_PEVC_PAD_EVT0 _UL_(1 << 12) #define PIN_PC07C_PEVC_PAD_EVT0 _L_(71) /**< \brief PEVC signal: PAD_EVT0 on PC07 mux C */ #define MUX_PC07C_PEVC_PAD_EVT0 _L_(2) #define PINMUX_PC07C_PEVC_PAD_EVT0 ((PIN_PC07C_PEVC_PAD_EVT0 << 16) | MUX_PC07C_PEVC_PAD_EVT0) #define GPIO_PC07C_PEVC_PAD_EVT0 _UL_(1 << 7) #define PIN_PC24C_PEVC_PAD_EVT0 _L_(88) /**< \brief PEVC signal: PAD_EVT0 on PC24 mux C */ #define MUX_PC24C_PEVC_PAD_EVT0 _L_(2) #define PINMUX_PC24C_PEVC_PAD_EVT0 ((PIN_PC24C_PEVC_PAD_EVT0 << 16) | MUX_PC24C_PEVC_PAD_EVT0) #define GPIO_PC24C_PEVC_PAD_EVT0 _UL_(1 << 24) #define PIN_PA09C_PEVC_PAD_EVT1 _L_(9) /**< \brief PEVC signal: PAD_EVT1 on PA09 mux C */ #define MUX_PA09C_PEVC_PAD_EVT1 _L_(2) #define PINMUX_PA09C_PEVC_PAD_EVT1 ((PIN_PA09C_PEVC_PAD_EVT1 << 16) | MUX_PA09C_PEVC_PAD_EVT1) #define GPIO_PA09C_PEVC_PAD_EVT1 _UL_(1 << 9) #define PIN_PB13C_PEVC_PAD_EVT1 _L_(45) /**< \brief PEVC signal: PAD_EVT1 on PB13 mux C */ #define MUX_PB13C_PEVC_PAD_EVT1 _L_(2) #define PINMUX_PB13C_PEVC_PAD_EVT1 ((PIN_PB13C_PEVC_PAD_EVT1 << 16) | MUX_PB13C_PEVC_PAD_EVT1) #define GPIO_PB13C_PEVC_PAD_EVT1 _UL_(1 << 13) #define PIN_PC08C_PEVC_PAD_EVT1 _L_(72) /**< \brief PEVC signal: PAD_EVT1 on PC08 mux C */ #define MUX_PC08C_PEVC_PAD_EVT1 _L_(2) #define PINMUX_PC08C_PEVC_PAD_EVT1 ((PIN_PC08C_PEVC_PAD_EVT1 << 16) | MUX_PC08C_PEVC_PAD_EVT1) #define GPIO_PC08C_PEVC_PAD_EVT1 _UL_(1 << 8) #define PIN_PC25C_PEVC_PAD_EVT1 _L_(89) /**< \brief PEVC signal: PAD_EVT1 on PC25 mux C */ #define MUX_PC25C_PEVC_PAD_EVT1 _L_(2) #define PINMUX_PC25C_PEVC_PAD_EVT1 ((PIN_PC25C_PEVC_PAD_EVT1 << 16) | MUX_PC25C_PEVC_PAD_EVT1) #define GPIO_PC25C_PEVC_PAD_EVT1 _UL_(1 << 25) #define PIN_PA10C_PEVC_PAD_EVT2 _L_(10) /**< \brief PEVC signal: PAD_EVT2 on PA10 mux C */ #define MUX_PA10C_PEVC_PAD_EVT2 _L_(2) #define PINMUX_PA10C_PEVC_PAD_EVT2 ((PIN_PA10C_PEVC_PAD_EVT2 << 16) | MUX_PA10C_PEVC_PAD_EVT2) #define GPIO_PA10C_PEVC_PAD_EVT2 _UL_(1 << 10) #define PIN_PC11C_PEVC_PAD_EVT2 _L_(75) /**< \brief PEVC signal: PAD_EVT2 on PC11 mux C */ #define MUX_PC11C_PEVC_PAD_EVT2 _L_(2) #define PINMUX_PC11C_PEVC_PAD_EVT2 ((PIN_PC11C_PEVC_PAD_EVT2 << 16) | MUX_PC11C_PEVC_PAD_EVT2) #define GPIO_PC11C_PEVC_PAD_EVT2 _UL_(1 << 11) #define PIN_PC26C_PEVC_PAD_EVT2 _L_(90) /**< \brief PEVC signal: PAD_EVT2 on PC26 mux C */ #define MUX_PC26C_PEVC_PAD_EVT2 _L_(2) #define PINMUX_PC26C_PEVC_PAD_EVT2 ((PIN_PC26C_PEVC_PAD_EVT2 << 16) | MUX_PC26C_PEVC_PAD_EVT2) #define GPIO_PC26C_PEVC_PAD_EVT2 _UL_(1 << 26) #define PIN_PB09B_PEVC_PAD_EVT2 _L_(41) /**< \brief PEVC signal: PAD_EVT2 on PB09 mux B */ #define MUX_PB09B_PEVC_PAD_EVT2 _L_(1) #define PINMUX_PB09B_PEVC_PAD_EVT2 ((PIN_PB09B_PEVC_PAD_EVT2 << 16) | MUX_PB09B_PEVC_PAD_EVT2) #define GPIO_PB09B_PEVC_PAD_EVT2 _UL_(1 << 9) #define PIN_PA11C_PEVC_PAD_EVT3 _L_(11) /**< \brief PEVC signal: PAD_EVT3 on PA11 mux C */ #define MUX_PA11C_PEVC_PAD_EVT3 _L_(2) #define PINMUX_PA11C_PEVC_PAD_EVT3 ((PIN_PA11C_PEVC_PAD_EVT3 << 16) | MUX_PA11C_PEVC_PAD_EVT3) #define GPIO_PA11C_PEVC_PAD_EVT3 _UL_(1 << 11) #define PIN_PC27C_PEVC_PAD_EVT3 _L_(91) /**< \brief PEVC signal: PAD_EVT3 on PC27 mux C */ #define MUX_PC27C_PEVC_PAD_EVT3 _L_(2) #define PINMUX_PC27C_PEVC_PAD_EVT3 ((PIN_PC27C_PEVC_PAD_EVT3 << 16) | MUX_PC27C_PEVC_PAD_EVT3) #define GPIO_PC27C_PEVC_PAD_EVT3 _UL_(1 << 27) #define PIN_PB10B_PEVC_PAD_EVT3 _L_(42) /**< \brief PEVC signal: PAD_EVT3 on PB10 mux B */ #define MUX_PB10B_PEVC_PAD_EVT3 _L_(1) #define PINMUX_PB10B_PEVC_PAD_EVT3 ((PIN_PB10B_PEVC_PAD_EVT3 << 16) | MUX_PB10B_PEVC_PAD_EVT3) #define GPIO_PB10B_PEVC_PAD_EVT3 _UL_(1 << 10) /* ========== GPIO definition for SCIF peripheral ========== */ #define PIN_PA19E_SCIF_GCLK0 _L_(19) /**< \brief SCIF signal: GCLK0 on PA19 mux E */ #define MUX_PA19E_SCIF_GCLK0 _L_(4) #define PINMUX_PA19E_SCIF_GCLK0 ((PIN_PA19E_SCIF_GCLK0 << 16) | MUX_PA19E_SCIF_GCLK0) #define GPIO_PA19E_SCIF_GCLK0 _UL_(1 << 19) #define PIN_PB10E_SCIF_GCLK0 _L_(42) /**< \brief SCIF signal: GCLK0 on PB10 mux E */ #define MUX_PB10E_SCIF_GCLK0 _L_(4) #define PINMUX_PB10E_SCIF_GCLK0 ((PIN_PB10E_SCIF_GCLK0 << 16) | MUX_PB10E_SCIF_GCLK0) #define GPIO_PB10E_SCIF_GCLK0 _UL_(1 << 10) #define PIN_PC26E_SCIF_GCLK0 _L_(90) /**< \brief SCIF signal: GCLK0 on PC26 mux E */ #define MUX_PC26E_SCIF_GCLK0 _L_(4) #define PINMUX_PC26E_SCIF_GCLK0 ((PIN_PC26E_SCIF_GCLK0 << 16) | MUX_PC26E_SCIF_GCLK0) #define GPIO_PC26E_SCIF_GCLK0 _UL_(1 << 26) #define PIN_PA02A_SCIF_GCLK0 _L_(2) /**< \brief SCIF signal: GCLK0 on PA02 mux A */ #define MUX_PA02A_SCIF_GCLK0 _L_(0) #define PINMUX_PA02A_SCIF_GCLK0 ((PIN_PA02A_SCIF_GCLK0 << 16) | MUX_PA02A_SCIF_GCLK0) #define GPIO_PA02A_SCIF_GCLK0 _UL_(1 << 2) #define PIN_PA20E_SCIF_GCLK1 _L_(20) /**< \brief SCIF signal: GCLK1 on PA20 mux E */ #define MUX_PA20E_SCIF_GCLK1 _L_(4) #define PINMUX_PA20E_SCIF_GCLK1 ((PIN_PA20E_SCIF_GCLK1 << 16) | MUX_PA20E_SCIF_GCLK1) #define GPIO_PA20E_SCIF_GCLK1 _UL_(1 << 20) #define PIN_PB11E_SCIF_GCLK1 _L_(43) /**< \brief SCIF signal: GCLK1 on PB11 mux E */ #define MUX_PB11E_SCIF_GCLK1 _L_(4) #define PINMUX_PB11E_SCIF_GCLK1 ((PIN_PB11E_SCIF_GCLK1 << 16) | MUX_PB11E_SCIF_GCLK1) #define GPIO_PB11E_SCIF_GCLK1 _UL_(1 << 11) #define PIN_PC27E_SCIF_GCLK1 _L_(91) /**< \brief SCIF signal: GCLK1 on PC27 mux E */ #define MUX_PC27E_SCIF_GCLK1 _L_(4) #define PINMUX_PC27E_SCIF_GCLK1 ((PIN_PC27E_SCIF_GCLK1 << 16) | MUX_PC27E_SCIF_GCLK1) #define GPIO_PC27E_SCIF_GCLK1 _UL_(1 << 27) #define PIN_PB12E_SCIF_GCLK2 _L_(44) /**< \brief SCIF signal: GCLK2 on PB12 mux E */ #define MUX_PB12E_SCIF_GCLK2 _L_(4) #define PINMUX_PB12E_SCIF_GCLK2 ((PIN_PB12E_SCIF_GCLK2 << 16) | MUX_PB12E_SCIF_GCLK2) #define GPIO_PB12E_SCIF_GCLK2 _UL_(1 << 12) #define PIN_PC28E_SCIF_GCLK2 _L_(92) /**< \brief SCIF signal: GCLK2 on PC28 mux E */ #define MUX_PC28E_SCIF_GCLK2 _L_(4) #define PINMUX_PC28E_SCIF_GCLK2 ((PIN_PC28E_SCIF_GCLK2 << 16) | MUX_PC28E_SCIF_GCLK2) #define GPIO_PC28E_SCIF_GCLK2 _UL_(1 << 28) #define PIN_PB13E_SCIF_GCLK3 _L_(45) /**< \brief SCIF signal: GCLK3 on PB13 mux E */ #define MUX_PB13E_SCIF_GCLK3 _L_(4) #define PINMUX_PB13E_SCIF_GCLK3 ((PIN_PB13E_SCIF_GCLK3 << 16) | MUX_PB13E_SCIF_GCLK3) #define GPIO_PB13E_SCIF_GCLK3 _UL_(1 << 13) #define PIN_PC29E_SCIF_GCLK3 _L_(93) /**< \brief SCIF signal: GCLK3 on PC29 mux E */ #define MUX_PC29E_SCIF_GCLK3 _L_(4) #define PINMUX_PC29E_SCIF_GCLK3 ((PIN_PC29E_SCIF_GCLK3 << 16) | MUX_PC29E_SCIF_GCLK3) #define GPIO_PC29E_SCIF_GCLK3 _UL_(1 << 29) #define PIN_PA23E_SCIF_GCLK_IN0 _L_(23) /**< \brief SCIF signal: GCLK_IN0 on PA23 mux E */ #define MUX_PA23E_SCIF_GCLK_IN0 _L_(4) #define PINMUX_PA23E_SCIF_GCLK_IN0 ((PIN_PA23E_SCIF_GCLK_IN0 << 16) | MUX_PA23E_SCIF_GCLK_IN0) #define GPIO_PA23E_SCIF_GCLK_IN0 _UL_(1 << 23) #define PIN_PB14E_SCIF_GCLK_IN0 _L_(46) /**< \brief SCIF signal: GCLK_IN0 on PB14 mux E */ #define MUX_PB14E_SCIF_GCLK_IN0 _L_(4) #define PINMUX_PB14E_SCIF_GCLK_IN0 ((PIN_PB14E_SCIF_GCLK_IN0 << 16) | MUX_PB14E_SCIF_GCLK_IN0) #define GPIO_PB14E_SCIF_GCLK_IN0 _UL_(1 << 14) #define PIN_PC30E_SCIF_GCLK_IN0 _L_(94) /**< \brief SCIF signal: GCLK_IN0 on PC30 mux E */ #define MUX_PC30E_SCIF_GCLK_IN0 _L_(4) #define PINMUX_PC30E_SCIF_GCLK_IN0 ((PIN_PC30E_SCIF_GCLK_IN0 << 16) | MUX_PC30E_SCIF_GCLK_IN0) #define GPIO_PC30E_SCIF_GCLK_IN0 _UL_(1 << 30) #define PIN_PA24E_SCIF_GCLK_IN1 _L_(24) /**< \brief SCIF signal: GCLK_IN1 on PA24 mux E */ #define MUX_PA24E_SCIF_GCLK_IN1 _L_(4) #define PINMUX_PA24E_SCIF_GCLK_IN1 ((PIN_PA24E_SCIF_GCLK_IN1 << 16) | MUX_PA24E_SCIF_GCLK_IN1) #define GPIO_PA24E_SCIF_GCLK_IN1 _UL_(1 << 24) #define PIN_PB15E_SCIF_GCLK_IN1 _L_(47) /**< \brief SCIF signal: GCLK_IN1 on PB15 mux E */ #define MUX_PB15E_SCIF_GCLK_IN1 _L_(4) #define PINMUX_PB15E_SCIF_GCLK_IN1 ((PIN_PB15E_SCIF_GCLK_IN1 << 16) | MUX_PB15E_SCIF_GCLK_IN1) #define GPIO_PB15E_SCIF_GCLK_IN1 _UL_(1 << 15) #define PIN_PC31E_SCIF_GCLK_IN1 _L_(95) /**< \brief SCIF signal: GCLK_IN1 on PC31 mux E */ #define MUX_PC31E_SCIF_GCLK_IN1 _L_(4) #define PINMUX_PC31E_SCIF_GCLK_IN1 ((PIN_PC31E_SCIF_GCLK_IN1 << 16) | MUX_PC31E_SCIF_GCLK_IN1) #define GPIO_PC31E_SCIF_GCLK_IN1 _UL_(1 << 31) /* ========== GPIO definition for EIC peripheral ========== */ #define PIN_PB01C_EIC_EXTINT0 _L_(33) /**< \brief EIC signal: EXTINT0 on PB01 mux C */ #define MUX_PB01C_EIC_EXTINT0 _L_(2) #define PINMUX_PB01C_EIC_EXTINT0 ((PIN_PB01C_EIC_EXTINT0 << 16) | MUX_PB01C_EIC_EXTINT0) #define GPIO_PB01C_EIC_EXTINT0 _UL_(1 << 1) #define PIN_PB01C_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ #define PIN_PA06C_EIC_EXTINT1 _L_(6) /**< \brief EIC signal: EXTINT1 on PA06 mux C */ #define MUX_PA06C_EIC_EXTINT1 _L_(2) #define PINMUX_PA06C_EIC_EXTINT1 ((PIN_PA06C_EIC_EXTINT1 << 16) | MUX_PA06C_EIC_EXTINT1) #define GPIO_PA06C_EIC_EXTINT1 _UL_(1 << 6) #define PIN_PA06C_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ #define PIN_PA16C_EIC_EXTINT1 _L_(16) /**< \brief EIC signal: EXTINT1 on PA16 mux C */ #define MUX_PA16C_EIC_EXTINT1 _L_(2) #define PINMUX_PA16C_EIC_EXTINT1 ((PIN_PA16C_EIC_EXTINT1 << 16) | MUX_PA16C_EIC_EXTINT1) #define GPIO_PA16C_EIC_EXTINT1 _UL_(1 << 16) #define PIN_PA16C_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ #define PIN_PC24B_EIC_EXTINT1 _L_(88) /**< \brief EIC signal: EXTINT1 on PC24 mux B */ #define MUX_PC24B_EIC_EXTINT1 _L_(1) #define PINMUX_PC24B_EIC_EXTINT1 ((PIN_PC24B_EIC_EXTINT1 << 16) | MUX_PC24B_EIC_EXTINT1) #define GPIO_PC24B_EIC_EXTINT1 _UL_(1 << 24) #define PIN_PC24B_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ #define PIN_PA04C_EIC_EXTINT2 _L_(4) /**< \brief EIC signal: EXTINT2 on PA04 mux C */ #define MUX_PA04C_EIC_EXTINT2 _L_(2) #define PINMUX_PA04C_EIC_EXTINT2 ((PIN_PA04C_EIC_EXTINT2 << 16) | MUX_PA04C_EIC_EXTINT2) #define GPIO_PA04C_EIC_EXTINT2 _UL_(1 << 4) #define PIN_PA04C_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ #define PIN_PA17C_EIC_EXTINT2 _L_(17) /**< \brief EIC signal: EXTINT2 on PA17 mux C */ #define MUX_PA17C_EIC_EXTINT2 _L_(2) #define PINMUX_PA17C_EIC_EXTINT2 ((PIN_PA17C_EIC_EXTINT2 << 16) | MUX_PA17C_EIC_EXTINT2) #define GPIO_PA17C_EIC_EXTINT2 _UL_(1 << 17) #define PIN_PA17C_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ #define PIN_PC25B_EIC_EXTINT2 _L_(89) /**< \brief EIC signal: EXTINT2 on PC25 mux B */ #define MUX_PC25B_EIC_EXTINT2 _L_(1) #define PINMUX_PC25B_EIC_EXTINT2 ((PIN_PC25B_EIC_EXTINT2 << 16) | MUX_PC25B_EIC_EXTINT2) #define GPIO_PC25B_EIC_EXTINT2 _UL_(1 << 25) #define PIN_PC25B_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ #define PIN_PA05C_EIC_EXTINT3 _L_(5) /**< \brief EIC signal: EXTINT3 on PA05 mux C */ #define MUX_PA05C_EIC_EXTINT3 _L_(2) #define PINMUX_PA05C_EIC_EXTINT3 ((PIN_PA05C_EIC_EXTINT3 << 16) | MUX_PA05C_EIC_EXTINT3) #define GPIO_PA05C_EIC_EXTINT3 _UL_(1 << 5) #define PIN_PA05C_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ #define PIN_PA18C_EIC_EXTINT3 _L_(18) /**< \brief EIC signal: EXTINT3 on PA18 mux C */ #define MUX_PA18C_EIC_EXTINT3 _L_(2) #define PINMUX_PA18C_EIC_EXTINT3 ((PIN_PA18C_EIC_EXTINT3 << 16) | MUX_PA18C_EIC_EXTINT3) #define GPIO_PA18C_EIC_EXTINT3 _UL_(1 << 18) #define PIN_PA18C_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ #define PIN_PC26B_EIC_EXTINT3 _L_(90) /**< \brief EIC signal: EXTINT3 on PC26 mux B */ #define MUX_PC26B_EIC_EXTINT3 _L_(1) #define PINMUX_PC26B_EIC_EXTINT3 ((PIN_PC26B_EIC_EXTINT3 << 16) | MUX_PC26B_EIC_EXTINT3) #define GPIO_PC26B_EIC_EXTINT3 _UL_(1 << 26) #define PIN_PC26B_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ #define PIN_PA07C_EIC_EXTINT4 _L_(7) /**< \brief EIC signal: EXTINT4 on PA07 mux C */ #define MUX_PA07C_EIC_EXTINT4 _L_(2) #define PINMUX_PA07C_EIC_EXTINT4 ((PIN_PA07C_EIC_EXTINT4 << 16) | MUX_PA07C_EIC_EXTINT4) #define GPIO_PA07C_EIC_EXTINT4 _UL_(1 << 7) #define PIN_PA07C_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ #define PIN_PA19C_EIC_EXTINT4 _L_(19) /**< \brief EIC signal: EXTINT4 on PA19 mux C */ #define MUX_PA19C_EIC_EXTINT4 _L_(2) #define PINMUX_PA19C_EIC_EXTINT4 ((PIN_PA19C_EIC_EXTINT4 << 16) | MUX_PA19C_EIC_EXTINT4) #define GPIO_PA19C_EIC_EXTINT4 _UL_(1 << 19) #define PIN_PA19C_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ #define PIN_PC27B_EIC_EXTINT4 _L_(91) /**< \brief EIC signal: EXTINT4 on PC27 mux B */ #define MUX_PC27B_EIC_EXTINT4 _L_(1) #define PINMUX_PC27B_EIC_EXTINT4 ((PIN_PC27B_EIC_EXTINT4 << 16) | MUX_PC27B_EIC_EXTINT4) #define GPIO_PC27B_EIC_EXTINT4 _UL_(1 << 27) #define PIN_PC27B_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ #define PIN_PA20C_EIC_EXTINT5 _L_(20) /**< \brief EIC signal: EXTINT5 on PA20 mux C */ #define MUX_PA20C_EIC_EXTINT5 _L_(2) #define PINMUX_PA20C_EIC_EXTINT5 ((PIN_PA20C_EIC_EXTINT5 << 16) | MUX_PA20C_EIC_EXTINT5) #define GPIO_PA20C_EIC_EXTINT5 _UL_(1 << 20) #define PIN_PA20C_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ #define PIN_PC03B_EIC_EXTINT5 _L_(67) /**< \brief EIC signal: EXTINT5 on PC03 mux B */ #define MUX_PC03B_EIC_EXTINT5 _L_(1) #define PINMUX_PC03B_EIC_EXTINT5 ((PIN_PC03B_EIC_EXTINT5 << 16) | MUX_PC03B_EIC_EXTINT5) #define GPIO_PC03B_EIC_EXTINT5 _UL_(1 << 3) #define PIN_PC03B_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ #define PIN_PA21C_EIC_EXTINT6 _L_(21) /**< \brief EIC signal: EXTINT6 on PA21 mux C */ #define MUX_PA21C_EIC_EXTINT6 _L_(2) #define PINMUX_PA21C_EIC_EXTINT6 ((PIN_PA21C_EIC_EXTINT6 << 16) | MUX_PA21C_EIC_EXTINT6) #define GPIO_PA21C_EIC_EXTINT6 _UL_(1 << 21) #define PIN_PA21C_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ #define PIN_PC04B_EIC_EXTINT6 _L_(68) /**< \brief EIC signal: EXTINT6 on PC04 mux B */ #define MUX_PC04B_EIC_EXTINT6 _L_(1) #define PINMUX_PC04B_EIC_EXTINT6 ((PIN_PC04B_EIC_EXTINT6 << 16) | MUX_PC04B_EIC_EXTINT6) #define GPIO_PC04B_EIC_EXTINT6 _UL_(1 << 4) #define PIN_PC04B_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ #define PIN_PA22C_EIC_EXTINT7 _L_(22) /**< \brief EIC signal: EXTINT7 on PA22 mux C */ #define MUX_PA22C_EIC_EXTINT7 _L_(2) #define PINMUX_PA22C_EIC_EXTINT7 ((PIN_PA22C_EIC_EXTINT7 << 16) | MUX_PA22C_EIC_EXTINT7) #define GPIO_PA22C_EIC_EXTINT7 _UL_(1 << 22) #define PIN_PA22C_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ #define PIN_PC05B_EIC_EXTINT7 _L_(69) /**< \brief EIC signal: EXTINT7 on PC05 mux B */ #define MUX_PC05B_EIC_EXTINT7 _L_(1) #define PINMUX_PC05B_EIC_EXTINT7 ((PIN_PC05B_EIC_EXTINT7 << 16) | MUX_PC05B_EIC_EXTINT7) #define GPIO_PC05B_EIC_EXTINT7 _UL_(1 << 5) #define PIN_PC05B_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ #define PIN_PA23C_EIC_EXTINT8 _L_(23) /**< \brief EIC signal: EXTINT8 on PA23 mux C */ #define MUX_PA23C_EIC_EXTINT8 _L_(2) #define PINMUX_PA23C_EIC_EXTINT8 ((PIN_PA23C_EIC_EXTINT8 << 16) | MUX_PA23C_EIC_EXTINT8) #define GPIO_PA23C_EIC_EXTINT8 _UL_(1 << 23) #define PIN_PA23C_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ #define PIN_PC06B_EIC_EXTINT8 _L_(70) /**< \brief EIC signal: EXTINT8 on PC06 mux B */ #define MUX_PC06B_EIC_EXTINT8 _L_(1) #define PINMUX_PC06B_EIC_EXTINT8 ((PIN_PC06B_EIC_EXTINT8 << 16) | MUX_PC06B_EIC_EXTINT8) #define GPIO_PC06B_EIC_EXTINT8 _UL_(1 << 6) #define PIN_PC06B_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ #endif /* _SAM4LC8C_PIO_ */