/* * Autogenerated file * * SPDX-License-Identifier: Apache-2.0 */ #include /* pa0_gpio */ #define PA0_GPIO \ SAM_PINMUX(a, 0, gpio, gpio) /* pa0a_pwmc0_pwmh0 */ #define PA0A_PWMC0_PWMH0 \ SAM_PINMUX(a, 0, a, periph) /* pa0b_tc0_tioa0 */ #define PA0B_TC0_TIOA0 \ SAM_PINMUX(a, 0, b, periph) /* pa0c_ebi_a17_ba1 */ #define PA0C_EBI_A17_BA1 \ SAM_PINMUX(a, 0, c, periph) /* pa0d_i2sc0_mck */ #define PA0D_I2SC0_MCK \ SAM_PINMUX(a, 0, d, periph) /* pa0x_supc_wkup0 */ #define PA0X_SUPC_WKUP0 \ SAM_PINMUX(a, 0, wkup0, wakeup) /* pa1_gpio */ #define PA1_GPIO \ SAM_PINMUX(a, 1, gpio, gpio) /* pa1a_pwmc0_pwml0 */ #define PA1A_PWMC0_PWML0 \ SAM_PINMUX(a, 1, a, periph) /* pa1b_tc0_tiob0 */ #define PA1B_TC0_TIOB0 \ SAM_PINMUX(a, 1, b, periph) /* pa1c_ebi_a18 */ #define PA1C_EBI_A18 \ SAM_PINMUX(a, 1, c, periph) /* pa1d_i2sc0_ck */ #define PA1D_I2SC0_CK \ SAM_PINMUX(a, 1, d, periph) /* pa1x_supc_wkup1 */ #define PA1X_SUPC_WKUP1 \ SAM_PINMUX(a, 1, wkup1, wakeup) /* pa2_gpio */ #define PA2_GPIO \ SAM_PINMUX(a, 2, gpio, gpio) /* pa2a_pwmc0_pwmh1 */ #define PA2A_PWMC0_PWMH1 \ SAM_PINMUX(a, 2, a, periph) /* pa2c_dacc_datrg */ #define PA2C_DACC_DATRG \ SAM_PINMUX(a, 2, c, periph) /* pa2x_supc_wkup2 */ #define PA2X_SUPC_WKUP2 \ SAM_PINMUX(a, 2, wkup2, wakeup) /* pa3_gpio */ #define PA3_GPIO \ SAM_PINMUX(a, 3, gpio, gpio) /* pa3a_twi0_twd */ #define PA3A_TWI0_TWD \ SAM_PINMUX(a, 3, a, periph) /* pa3b_lon_col1 */ #define PA3B_LON_COL1 \ SAM_PINMUX(a, 3, b, periph) /* pa3c_pmc_pck2 */ #define PA3C_PMC_PCK2 \ SAM_PINMUX(a, 3, c, periph) /* pa3x_pio_piodc0 */ #define PA3X_PIO_PIODC0 \ SAM_PINMUX(a, 3, x, extra) /* pa4_gpio */ #define PA4_GPIO \ SAM_PINMUX(a, 4, gpio, gpio) /* pa4a_twi0_twck */ #define PA4A_TWI0_TWCK \ SAM_PINMUX(a, 4, a, periph) /* pa4b_tc0_tclk0 */ #define PA4B_TC0_TCLK0 \ SAM_PINMUX(a, 4, b, periph) /* pa4c_uart1_txd */ #define PA4C_UART1_TXD \ SAM_PINMUX(a, 4, c, periph) /* pa4x_pio_piodc1 */ #define PA4X_PIO_PIODC1 \ SAM_PINMUX(a, 4, x, extra) /* pa4x_supc_wkup3 */ #define PA4X_SUPC_WKUP3 \ SAM_PINMUX(a, 4, wkup3, wakeup) /* pa5_gpio */ #define PA5_GPIO \ SAM_PINMUX(a, 5, gpio, gpio) /* pa5a_pwmc1_pwml3 */ #define PA5A_PWMC1_PWML3 \ SAM_PINMUX(a, 5, a, periph) /* pa5b_isi_d4 */ #define PA5B_ISI_D4 \ SAM_PINMUX(a, 5, b, periph) /* pa5c_uart1_rxd */ #define PA5C_UART1_RXD \ SAM_PINMUX(a, 5, c, periph) /* pa5x_pio_piodc2 */ #define PA5X_PIO_PIODC2 \ SAM_PINMUX(a, 5, x, extra) /* pa5x_supc_wkup4 */ #define PA5X_SUPC_WKUP4 \ SAM_PINMUX(a, 5, wkup4, wakeup) /* pa6_gpio */ #define PA6_GPIO \ SAM_PINMUX(a, 6, gpio, gpio) /* pa6b_pmc_pck0 */ #define PA6B_PMC_PCK0 \ SAM_PINMUX(a, 6, b, periph) /* pa6c_uart1_txd */ #define PA6C_UART1_TXD \ SAM_PINMUX(a, 6, c, periph) /* pa7_gpio */ #define PA7_GPIO \ SAM_PINMUX(a, 7, gpio, gpio) /* pa7b_pwmc0_pwmh3 */ #define PA7B_PWMC0_PWMH3 \ SAM_PINMUX(a, 7, b, periph) /* pa7s_supc_xin32 */ #define PA7S_SUPC_XIN32 \ SAM_PINMUX(a, 7, s, system) /* pa8_gpio */ #define PA8_GPIO \ SAM_PINMUX(a, 8, gpio, gpio) /* pa8a_pwmc1_pwmh3 */ #define PA8A_PWMC1_PWMH3 \ SAM_PINMUX(a, 8, a, periph) /* pa8b_afe0_adtrg */ #define PA8B_AFE0_ADTRG \ SAM_PINMUX(a, 8, b, periph) /* pa8s_supc_xout32 */ #define PA8S_SUPC_XOUT32 \ SAM_PINMUX(a, 8, s, system) /* pa9_gpio */ #define PA9_GPIO \ SAM_PINMUX(a, 9, gpio, gpio) /* pa9a_uart0_rxd */ #define PA9A_UART0_RXD \ SAM_PINMUX(a, 9, a, periph) /* pa9b_isi_d3 */ #define PA9B_ISI_D3 \ SAM_PINMUX(a, 9, b, periph) /* pa9c_pwmc0_pwmfi0 */ #define PA9C_PWMC0_PWMFI0 \ SAM_PINMUX(a, 9, c, periph) /* pa9x_pio_piodc3 */ #define PA9X_PIO_PIODC3 \ SAM_PINMUX(a, 9, x, extra) /* pa9x_supc_wkup6 */ #define PA9X_SUPC_WKUP6 \ SAM_PINMUX(a, 9, wkup6, wakeup) /* pa10_gpio */ #define PA10_GPIO \ SAM_PINMUX(a, 10, gpio, gpio) /* pa10a_uart0_txd */ #define PA10A_UART0_TXD \ SAM_PINMUX(a, 10, a, periph) /* pa10b_pwmc0_pwmextrg0 */ #define PA10B_PWMC0_PWMEXTRG0 \ SAM_PINMUX(a, 10, b, periph) /* pa10c_ssc_rd */ #define PA10C_SSC_RD \ SAM_PINMUX(a, 10, c, periph) /* pa10x_pio_piodc4 */ #define PA10X_PIO_PIODC4 \ SAM_PINMUX(a, 10, x, extra) /* pa11_gpio */ #define PA11_GPIO \ SAM_PINMUX(a, 11, gpio, gpio) /* pa11a_qspi_qcs */ #define PA11A_QSPI_QCS \ SAM_PINMUX(a, 11, a, periph) /* pa11b_pwmc0_pwmh0 */ #define PA11B_PWMC0_PWMH0 \ SAM_PINMUX(a, 11, b, periph) /* pa11c_pwmc1_pwml0 */ #define PA11C_PWMC1_PWML0 \ SAM_PINMUX(a, 11, c, periph) /* pa11x_pio_piodc5 */ #define PA11X_PIO_PIODC5 \ SAM_PINMUX(a, 11, x, extra) /* pa11x_supc_wkup7 */ #define PA11X_SUPC_WKUP7 \ SAM_PINMUX(a, 11, wkup7, wakeup) /* pa12_gpio */ #define PA12_GPIO \ SAM_PINMUX(a, 12, gpio, gpio) /* pa12a_qspi_qio1 */ #define PA12A_QSPI_QIO1 \ SAM_PINMUX(a, 12, a, periph) /* pa12b_pwmc0_pwmh1 */ #define PA12B_PWMC0_PWMH1 \ SAM_PINMUX(a, 12, b, periph) /* pa12c_pwmc1_pwmh0 */ #define PA12C_PWMC1_PWMH0 \ SAM_PINMUX(a, 12, c, periph) /* pa12x_pio_piodc6 */ #define PA12X_PIO_PIODC6 \ SAM_PINMUX(a, 12, x, extra) /* pa13_gpio */ #define PA13_GPIO \ SAM_PINMUX(a, 13, gpio, gpio) /* pa13a_qspi_qio0 */ #define PA13A_QSPI_QIO0 \ SAM_PINMUX(a, 13, a, periph) /* pa13b_pwmc0_pwmh2 */ #define PA13B_PWMC0_PWMH2 \ SAM_PINMUX(a, 13, b, periph) /* pa13c_pwmc1_pwml1 */ #define PA13C_PWMC1_PWML1 \ SAM_PINMUX(a, 13, c, periph) /* pa13x_pio_piodc7 */ #define PA13X_PIO_PIODC7 \ SAM_PINMUX(a, 13, x, extra) /* pa14_gpio */ #define PA14_GPIO \ SAM_PINMUX(a, 14, gpio, gpio) /* pa14a_qspi_qsck */ #define PA14A_QSPI_QSCK \ SAM_PINMUX(a, 14, a, periph) /* pa14b_pwmc0_pwmh3 */ #define PA14B_PWMC0_PWMH3 \ SAM_PINMUX(a, 14, b, periph) /* pa14c_pwmc1_pwmh1 */ #define PA14C_PWMC1_PWMH1 \ SAM_PINMUX(a, 14, c, periph) /* pa14x_pio_pioden1 */ #define PA14X_PIO_PIODEN1 \ SAM_PINMUX(a, 14, x, extra) /* pa14x_supc_wkup8 */ #define PA14X_SUPC_WKUP8 \ SAM_PINMUX(a, 14, wkup8, wakeup) /* pa15_gpio */ #define PA15_GPIO \ SAM_PINMUX(a, 15, gpio, gpio) /* pa15a_ebi_d14 */ #define PA15A_EBI_D14 \ SAM_PINMUX(a, 15, a, periph) /* pa15b_tc0_tioa1 */ #define PA15B_TC0_TIOA1 \ SAM_PINMUX(a, 15, b, periph) /* pa15c_pwmc0_pwml3 */ #define PA15C_PWMC0_PWML3 \ SAM_PINMUX(a, 15, c, periph) /* pa15d_i2sc0_ws */ #define PA15D_I2SC0_WS \ SAM_PINMUX(a, 15, d, periph) /* pa16_gpio */ #define PA16_GPIO \ SAM_PINMUX(a, 16, gpio, gpio) /* pa16a_ebi_d15 */ #define PA16A_EBI_D15 \ SAM_PINMUX(a, 16, a, periph) /* pa16b_tc0_tiob1 */ #define PA16B_TC0_TIOB1 \ SAM_PINMUX(a, 16, b, periph) /* pa16c_pwmc0_pwml2 */ #define PA16C_PWMC0_PWML2 \ SAM_PINMUX(a, 16, c, periph) /* pa16d_i2sc0_di */ #define PA16D_I2SC0_DI \ SAM_PINMUX(a, 16, d, periph) /* pa17_gpio */ #define PA17_GPIO \ SAM_PINMUX(a, 17, gpio, gpio) /* pa17a_qspi_qio2 */ #define PA17A_QSPI_QIO2 \ SAM_PINMUX(a, 17, a, periph) /* pa17b_pmc_pck1 */ #define PA17B_PMC_PCK1 \ SAM_PINMUX(a, 17, b, periph) /* pa17c_pwmc0_pwmh3 */ #define PA17C_PWMC0_PWMH3 \ SAM_PINMUX(a, 17, c, periph) /* pa17x_afe0_ad6 */ #define PA17X_AFE0_AD6 \ SAM_PINMUX(a, 17, x, extra) /* pa18_gpio */ #define PA18_GPIO \ SAM_PINMUX(a, 18, gpio, gpio) /* pa18a_pwmc1_pwmextrg1 */ #define PA18A_PWMC1_PWMEXTRG1 \ SAM_PINMUX(a, 18, a, periph) /* pa18b_pmc_pck2 */ #define PA18B_PMC_PCK2 \ SAM_PINMUX(a, 18, b, periph) /* pa18c_ebi_a14 */ #define PA18C_EBI_A14 \ SAM_PINMUX(a, 18, c, periph) /* pa18x_afe0_ad7 */ #define PA18X_AFE0_AD7 \ SAM_PINMUX(a, 18, x, extra) /* pa19_gpio */ #define PA19_GPIO \ SAM_PINMUX(a, 19, gpio, gpio) /* pa19b_pwmc0_pwml0 */ #define PA19B_PWMC0_PWML0 \ SAM_PINMUX(a, 19, b, periph) /* pa19c_ebi_a15 */ #define PA19C_EBI_A15 \ SAM_PINMUX(a, 19, c, periph) /* pa19d_i2sc1_mck */ #define PA19D_I2SC1_MCK \ SAM_PINMUX(a, 19, d, periph) /* pa19x_afe0_ad8 */ #define PA19X_AFE0_AD8 \ SAM_PINMUX(a, 19, x, extra) /* pa19x_supc_wkup9 */ #define PA19X_SUPC_WKUP9 \ SAM_PINMUX(a, 19, wkup9, wakeup) /* pa20_gpio */ #define PA20_GPIO \ SAM_PINMUX(a, 20, gpio, gpio) /* pa20b_pwmc0_pwml1 */ #define PA20B_PWMC0_PWML1 \ SAM_PINMUX(a, 20, b, periph) /* pa20c_ebi_a16_ba0 */ #define PA20C_EBI_A16_BA0 \ SAM_PINMUX(a, 20, c, periph) /* pa20d_i2sc1_ck */ #define PA20D_I2SC1_CK \ SAM_PINMUX(a, 20, d, periph) /* pa20x_afe0_ad9 */ #define PA20X_AFE0_AD9 \ SAM_PINMUX(a, 20, x, extra) /* pa20x_supc_wkup10 */ #define PA20X_SUPC_WKUP10 \ SAM_PINMUX(a, 20, wkup10, wakeup) /* pa21_gpio */ #define PA21_GPIO \ SAM_PINMUX(a, 21, gpio, gpio) /* pa21a_usart1_rxd */ #define PA21A_USART1_RXD \ SAM_PINMUX(a, 21, a, periph) /* pa21b_pmc_pck1 */ #define PA21B_PMC_PCK1 \ SAM_PINMUX(a, 21, b, periph) /* pa21c_pwmc1_pwmfi0 */ #define PA21C_PWMC1_PWMFI0 \ SAM_PINMUX(a, 21, c, periph) /* pa21x_afe0_ad1 */ #define PA21X_AFE0_AD1 \ SAM_PINMUX(a, 21, x, extra) /* pa21x_pio_piodcen2 */ #define PA21X_PIO_PIODCEN2 \ SAM_PINMUX(a, 21, x, extra) /* pa22_gpio */ #define PA22_GPIO \ SAM_PINMUX(a, 22, gpio, gpio) /* pa22a_ssc_rk */ #define PA22A_SSC_RK \ SAM_PINMUX(a, 22, a, periph) /* pa22b_pwmc0_pwmextrg1 */ #define PA22B_PWMC0_PWMEXTRG1 \ SAM_PINMUX(a, 22, b, periph) /* pa22c_ebi_ncs2 */ #define PA22C_EBI_NCS2 \ SAM_PINMUX(a, 22, c, periph) /* pa22x_pio_piodcclk */ #define PA22X_PIO_PIODCCLK \ SAM_PINMUX(a, 22, x, extra) /* pa23_gpio */ #define PA23_GPIO \ SAM_PINMUX(a, 23, gpio, gpio) /* pa23a_usart1_sck */ #define PA23A_USART1_SCK \ SAM_PINMUX(a, 23, a, periph) /* pa23b_pwmc0_pwmh0 */ #define PA23B_PWMC0_PWMH0 \ SAM_PINMUX(a, 23, b, periph) /* pa23c_ebi_a19 */ #define PA23C_EBI_A19 \ SAM_PINMUX(a, 23, c, periph) /* pa23d_pwmc1_pwml2 */ #define PA23D_PWMC1_PWML2 \ SAM_PINMUX(a, 23, d, periph) /* pa24_gpio */ #define PA24_GPIO \ SAM_PINMUX(a, 24, gpio, gpio) /* pa24a_usart1_rts */ #define PA24A_USART1_RTS \ SAM_PINMUX(a, 24, a, periph) /* pa24b_pwmc0_pwmh1 */ #define PA24B_PWMC0_PWMH1 \ SAM_PINMUX(a, 24, b, periph) /* pa24c_ebi_a20 */ #define PA24C_EBI_A20 \ SAM_PINMUX(a, 24, c, periph) /* pa24d_isi_pck */ #define PA24D_ISI_PCK \ SAM_PINMUX(a, 24, d, periph) /* pa25_gpio */ #define PA25_GPIO \ SAM_PINMUX(a, 25, gpio, gpio) /* pa25a_usart1_cts */ #define PA25A_USART1_CTS \ SAM_PINMUX(a, 25, a, periph) /* pa25b_pwmc0_pwmh2 */ #define PA25B_PWMC0_PWMH2 \ SAM_PINMUX(a, 25, b, periph) /* pa25c_ebi_a23 */ #define PA25C_EBI_A23 \ SAM_PINMUX(a, 25, c, periph) /* pa25d_hsmci_mcck */ #define PA25D_HSMCI_MCCK \ SAM_PINMUX(a, 25, d, periph) /* pa26_gpio */ #define PA26_GPIO \ SAM_PINMUX(a, 26, gpio, gpio) /* pa26a_usart1_dcd */ #define PA26A_USART1_DCD \ SAM_PINMUX(a, 26, a, periph) /* pa26b_tc0_tioa2 */ #define PA26B_TC0_TIOA2 \ SAM_PINMUX(a, 26, b, periph) /* pa26c_hsmci_mcda2 */ #define PA26C_HSMCI_MCDA2 \ SAM_PINMUX(a, 26, c, periph) /* pa26d_pwmc1_pwmfi1 */ #define PA26D_PWMC1_PWMFI1 \ SAM_PINMUX(a, 26, d, periph) /* pa27_gpio */ #define PA27_GPIO \ SAM_PINMUX(a, 27, gpio, gpio) /* pa27a_usart1_dtr */ #define PA27A_USART1_DTR \ SAM_PINMUX(a, 27, a, periph) /* pa27b_tc0_tiob2 */ #define PA27B_TC0_TIOB2 \ SAM_PINMUX(a, 27, b, periph) /* pa27c_hsmci_mcda3 */ #define PA27C_HSMCI_MCDA3 \ SAM_PINMUX(a, 27, c, periph) /* pa27d_isi_d7 */ #define PA27D_ISI_D7 \ SAM_PINMUX(a, 27, d, periph) /* pa28_gpio */ #define PA28_GPIO \ SAM_PINMUX(a, 28, gpio, gpio) /* pa28a_usart1_dsr */ #define PA28A_USART1_DSR \ SAM_PINMUX(a, 28, a, periph) /* pa28b_tc0_tclk1 */ #define PA28B_TC0_TCLK1 \ SAM_PINMUX(a, 28, b, periph) /* pa28c_hsmci_mccda */ #define PA28C_HSMCI_MCCDA \ SAM_PINMUX(a, 28, c, periph) /* pa28d_pwmc1_pwmfi2 */ #define PA28D_PWMC1_PWMFI2 \ SAM_PINMUX(a, 28, d, periph) /* pa29_gpio */ #define PA29_GPIO \ SAM_PINMUX(a, 29, gpio, gpio) /* pa29a_usart1_ri */ #define PA29A_USART1_RI \ SAM_PINMUX(a, 29, a, periph) /* pa29b_tc0_tclk2 */ #define PA29B_TC0_TCLK2 \ SAM_PINMUX(a, 29, b, periph) /* pa30_gpio */ #define PA30_GPIO \ SAM_PINMUX(a, 30, gpio, gpio) /* pa30a_pwmc0_pwml2 */ #define PA30A_PWMC0_PWML2 \ SAM_PINMUX(a, 30, a, periph) /* pa30b_pwmc1_pwmextrg0 */ #define PA30B_PWMC1_PWMEXTRG0 \ SAM_PINMUX(a, 30, b, periph) /* pa30c_hsmci_mcda0 */ #define PA30C_HSMCI_MCDA0 \ SAM_PINMUX(a, 30, c, periph) /* pa30d_i2sc0_do */ #define PA30D_I2SC0_DO \ SAM_PINMUX(a, 30, d, periph) /* pa30x_supc_wkup11 */ #define PA30X_SUPC_WKUP11 \ SAM_PINMUX(a, 30, wkup11, wakeup) /* pa31_gpio */ #define PA31_GPIO \ SAM_PINMUX(a, 31, gpio, gpio) /* pa31a_spi0_npcs1 */ #define PA31A_SPI0_NPCS1 \ SAM_PINMUX(a, 31, a, periph) /* pa31b_pmc_pck2 */ #define PA31B_PMC_PCK2 \ SAM_PINMUX(a, 31, b, periph) /* pa31c_hsmci_mcda1 */ #define PA31C_HSMCI_MCDA1 \ SAM_PINMUX(a, 31, c, periph) /* pa31d_pwmc1_pwmh2 */ #define PA31D_PWMC1_PWMH2 \ SAM_PINMUX(a, 31, d, periph) /* pb0_gpio */ #define PB0_GPIO \ SAM_PINMUX(b, 0, gpio, gpio) /* pb0a_pwmc0_pwmh0 */ #define PB0A_PWMC0_PWMH0 \ SAM_PINMUX(b, 0, a, periph) /* pb0c_usart0_rxd */ #define PB0C_USART0_RXD \ SAM_PINMUX(b, 0, c, periph) /* pb0d_ssc_tf */ #define PB0D_SSC_TF \ SAM_PINMUX(b, 0, d, periph) /* pb0x_afe0_ad10 */ #define PB0X_AFE0_AD10 \ SAM_PINMUX(b, 0, x, extra) /* pb0x_rtc_out0 */ #define PB0X_RTC_OUT0 \ SAM_PINMUX(b, 0, x, extra) /* pb1_gpio */ #define PB1_GPIO \ SAM_PINMUX(b, 1, gpio, gpio) /* pb1a_pwmc0_pwmh1 */ #define PB1A_PWMC0_PWMH1 \ SAM_PINMUX(b, 1, a, periph) /* pb1c_usart0_txd */ #define PB1C_USART0_TXD \ SAM_PINMUX(b, 1, c, periph) /* pb1d_ssc_tk */ #define PB1D_SSC_TK \ SAM_PINMUX(b, 1, d, periph) /* pb1x_afe1_ad0 */ #define PB1X_AFE1_AD0 \ SAM_PINMUX(b, 1, x, extra) /* pb1x_rtc_out1 */ #define PB1X_RTC_OUT1 \ SAM_PINMUX(b, 1, x, extra) /* pb2_gpio */ #define PB2_GPIO \ SAM_PINMUX(b, 2, gpio, gpio) /* pb2c_usart0_cts */ #define PB2C_USART0_CTS \ SAM_PINMUX(b, 2, c, periph) /* pb2d_spi0_npcs0 */ #define PB2D_SPI0_NPCS0 \ SAM_PINMUX(b, 2, d, periph) /* pb2x_afe0_ad5 */ #define PB2X_AFE0_AD5 \ SAM_PINMUX(b, 2, x, extra) /* pb3_gpio */ #define PB3_GPIO \ SAM_PINMUX(b, 3, gpio, gpio) /* pb3b_pmc_pck2 */ #define PB3B_PMC_PCK2 \ SAM_PINMUX(b, 3, b, periph) /* pb3c_usart0_rts */ #define PB3C_USART0_RTS \ SAM_PINMUX(b, 3, c, periph) /* pb3d_isi_d2 */ #define PB3D_ISI_D2 \ SAM_PINMUX(b, 3, d, periph) /* pb3x_afe0_ad2 */ #define PB3X_AFE0_AD2 \ SAM_PINMUX(b, 3, x, extra) /* pb3x_supc_wkup12 */ #define PB3X_SUPC_WKUP12 \ SAM_PINMUX(b, 3, wkup12, wakeup) /* pb4_gpio */ #define PB4_GPIO \ SAM_PINMUX(b, 4, gpio, gpio) /* pb4a_twi1_twd */ #define PB4A_TWI1_TWD \ SAM_PINMUX(b, 4, a, periph) /* pb4b_pwmc0_pwmh2 */ #define PB4B_PWMC0_PWMH2 \ SAM_PINMUX(b, 4, b, periph) /* pb4d_usart1_txd */ #define PB4D_USART1_TXD \ SAM_PINMUX(b, 4, d, periph) /* pb4s_jtag_tdi */ #define PB4S_JTAG_TDI \ SAM_PINMUX(b, 4, s, system) /* pb5_gpio */ #define PB5_GPIO \ SAM_PINMUX(b, 5, gpio, gpio) /* pb5a_twi1_twck */ #define PB5A_TWI1_TWCK \ SAM_PINMUX(b, 5, a, periph) /* pb5b_pwmc0_pwml0 */ #define PB5B_PWMC0_PWML0 \ SAM_PINMUX(b, 5, b, periph) /* pb5d_ssc_td */ #define PB5D_SSC_TD \ SAM_PINMUX(b, 5, d, periph) /* pb5s_jtag_tdo */ #define PB5S_JTAG_TDO \ SAM_PINMUX(b, 5, s, system) /* pb5s_swd_traceswo */ #define PB5S_SWD_TRACESWO \ SAM_PINMUX(b, 5, s, system) /* pb5x_supc_wkup13 */ #define PB5X_SUPC_WKUP13 \ SAM_PINMUX(b, 5, wkup13, wakeup) /* pb6_gpio */ #define PB6_GPIO \ SAM_PINMUX(b, 6, gpio, gpio) /* pb6s_jtag_tms */ #define PB6S_JTAG_TMS \ SAM_PINMUX(b, 6, s, system) /* pb6s_swd_swdio */ #define PB6S_SWD_SWDIO \ SAM_PINMUX(b, 6, s, system) /* pb7_gpio */ #define PB7_GPIO \ SAM_PINMUX(b, 7, gpio, gpio) /* pb7s_jtag_tck */ #define PB7S_JTAG_TCK \ SAM_PINMUX(b, 7, s, system) /* pb7s_swd_swclk */ #define PB7S_SWD_SWCLK \ SAM_PINMUX(b, 7, s, system) /* pb8_gpio */ #define PB8_GPIO \ SAM_PINMUX(b, 8, gpio, gpio) /* pb8s_supc_xout */ #define PB8S_SUPC_XOUT \ SAM_PINMUX(b, 8, s, system) /* pb9_gpio */ #define PB9_GPIO \ SAM_PINMUX(b, 9, gpio, gpio) /* pb9s_supc_xin */ #define PB9S_SUPC_XIN \ SAM_PINMUX(b, 9, s, system) /* pb12_gpio */ #define PB12_GPIO \ SAM_PINMUX(b, 12, gpio, gpio) /* pb12a_pwmc0_pwml1 */ #define PB12A_PWMC0_PWML1 \ SAM_PINMUX(b, 12, a, periph) /* pb12d_pcm_pck0 */ #define PB12D_PCM_PCK0 \ SAM_PINMUX(b, 12, d, periph) /* pb12s_flash_erase */ #define PB12S_FLASH_ERASE \ SAM_PINMUX(b, 12, s, system) /* pb13_gpio */ #define PB13_GPIO \ SAM_PINMUX(b, 13, gpio, gpio) /* pb13a_pwmc0_pwml2 */ #define PB13A_PWMC0_PWML2 \ SAM_PINMUX(b, 13, a, periph) /* pb13b_pcm_pck0 */ #define PB13B_PCM_PCK0 \ SAM_PINMUX(b, 13, b, periph) /* pb13c_usart0_sck */ #define PB13C_USART0_SCK \ SAM_PINMUX(b, 13, c, periph) /* pb13x_dacc_dac0 */ #define PB13X_DACC_DAC0 \ SAM_PINMUX(b, 13, x, extra) /* pc0_gpio */ #define PC0_GPIO \ SAM_PINMUX(c, 0, gpio, gpio) /* pc0a_ebi_d0 */ #define PC0A_EBI_D0 \ SAM_PINMUX(c, 0, a, periph) /* pc0b_pwmc0_pwml0 */ #define PC0B_PWMC0_PWML0 \ SAM_PINMUX(c, 0, b, periph) /* pc0x_afe1_ad9 */ #define PC0X_AFE1_AD9 \ SAM_PINMUX(c, 0, x, extra) /* pc1_gpio */ #define PC1_GPIO \ SAM_PINMUX(c, 1, gpio, gpio) /* pc1a_ebi_d1 */ #define PC1A_EBI_D1 \ SAM_PINMUX(c, 1, a, periph) /* pc1b_pwmc0_pwml1 */ #define PC1B_PWMC0_PWML1 \ SAM_PINMUX(c, 1, b, periph) /* pc2_gpio */ #define PC2_GPIO \ SAM_PINMUX(c, 2, gpio, gpio) /* pc2a_ebi_d2 */ #define PC2A_EBI_D2 \ SAM_PINMUX(c, 2, a, periph) /* pc2b_pwmc0_pwml2 */ #define PC2B_PWMC0_PWML2 \ SAM_PINMUX(c, 2, b, periph) /* pc3_gpio */ #define PC3_GPIO \ SAM_PINMUX(c, 3, gpio, gpio) /* pc3a_ebi_d3 */ #define PC3A_EBI_D3 \ SAM_PINMUX(c, 3, a, periph) /* pc3b_pwmc0_pwml3 */ #define PC3B_PWMC0_PWML3 \ SAM_PINMUX(c, 3, b, periph) /* pc4_gpio */ #define PC4_GPIO \ SAM_PINMUX(c, 4, gpio, gpio) /* pc4a_ebi_d4 */ #define PC4A_EBI_D4 \ SAM_PINMUX(c, 4, a, periph) /* pc5_gpio */ #define PC5_GPIO \ SAM_PINMUX(c, 5, gpio, gpio) /* pc5a_ebi_d5 */ #define PC5A_EBI_D5 \ SAM_PINMUX(c, 5, a, periph) /* pc5b_tc2_tioa6 */ #define PC5B_TC2_TIOA6 \ SAM_PINMUX(c, 5, b, periph) /* pc6_gpio */ #define PC6_GPIO \ SAM_PINMUX(c, 6, gpio, gpio) /* pc6a_ebi_d6 */ #define PC6A_EBI_D6 \ SAM_PINMUX(c, 6, a, periph) /* pc6b_tc2_tiob6 */ #define PC6B_TC2_TIOB6 \ SAM_PINMUX(c, 6, b, periph) /* pc7_gpio */ #define PC7_GPIO \ SAM_PINMUX(c, 7, gpio, gpio) /* pc7a_ebi_d7 */ #define PC7A_EBI_D7 \ SAM_PINMUX(c, 7, a, periph) /* pc7b_tc2_tclk6 */ #define PC7B_TC2_TCLK6 \ SAM_PINMUX(c, 7, b, periph) /* pc8_gpio */ #define PC8_GPIO \ SAM_PINMUX(c, 8, gpio, gpio) /* pc8a_ebi_nwe_nwr0 */ #define PC8A_EBI_NWE_NWR0 \ SAM_PINMUX(c, 8, a, periph) /* pc8b_tc2_tioa7 */ #define PC8B_TC2_TIOA7 \ SAM_PINMUX(c, 8, b, periph) /* pc9_gpio */ #define PC9_GPIO \ SAM_PINMUX(c, 9, gpio, gpio) /* pc9a_ebi_nandoe */ #define PC9A_EBI_NANDOE \ SAM_PINMUX(c, 9, a, periph) /* pc9b_tc2_tiob7 */ #define PC9B_TC2_TIOB7 \ SAM_PINMUX(c, 9, b, periph) /* pc10_gpio */ #define PC10_GPIO \ SAM_PINMUX(c, 10, gpio, gpio) /* pc10a_ebi_nandwe */ #define PC10A_EBI_NANDWE \ SAM_PINMUX(c, 10, a, periph) /* pc10b_tc2_tclk7 */ #define PC10B_TC2_TCLK7 \ SAM_PINMUX(c, 10, b, periph) /* pc11_gpio */ #define PC11_GPIO \ SAM_PINMUX(c, 11, gpio, gpio) /* pc11a_ebi_nrd */ #define PC11A_EBI_NRD \ SAM_PINMUX(c, 11, a, periph) /* pc11b_tc2_tioa8 */ #define PC11B_TC2_TIOA8 \ SAM_PINMUX(c, 11, b, periph) /* pc12_gpio */ #define PC12_GPIO \ SAM_PINMUX(c, 12, gpio, gpio) /* pc12a_ebi_ncs3 */ #define PC12A_EBI_NCS3 \ SAM_PINMUX(c, 12, a, periph) /* pc12b_tc2_tiob8 */ #define PC12B_TC2_TIOB8 \ SAM_PINMUX(c, 12, b, periph) /* pc12x_afe1_ad3 */ #define PC12X_AFE1_AD3 \ SAM_PINMUX(c, 12, x, extra) /* pc13_gpio */ #define PC13_GPIO \ SAM_PINMUX(c, 13, gpio, gpio) /* pc13a_ebi_nwait */ #define PC13A_EBI_NWAIT \ SAM_PINMUX(c, 13, a, periph) /* pc13b_pwmc0_pwmh3 */ #define PC13B_PWMC0_PWMH3 \ SAM_PINMUX(c, 13, b, periph) /* pc13c_ebi_sda10 */ #define PC13C_EBI_SDA10 \ SAM_PINMUX(c, 13, c, periph) /* pc13x_afe1_ad1 */ #define PC13X_AFE1_AD1 \ SAM_PINMUX(c, 13, x, extra) /* pc14_gpio */ #define PC14_GPIO \ SAM_PINMUX(c, 14, gpio, gpio) /* pc14a_ebi_ncs0 */ #define PC14A_EBI_NCS0 \ SAM_PINMUX(c, 14, a, periph) /* pc14b_tc2_tclk8 */ #define PC14B_TC2_TCLK8 \ SAM_PINMUX(c, 14, b, periph) /* pc15_gpio */ #define PC15_GPIO \ SAM_PINMUX(c, 15, gpio, gpio) /* pc15a_ebi_ncs1_sdcs */ #define PC15A_EBI_NCS1_SDCS \ SAM_PINMUX(c, 15, a, periph) /* pc15b_pwmc0_pwml3 */ #define PC15B_PWMC0_PWML3 \ SAM_PINMUX(c, 15, b, periph) /* pc15x_afe1_ad2 */ #define PC15X_AFE1_AD2 \ SAM_PINMUX(c, 15, x, extra) /* pc16_gpio */ #define PC16_GPIO \ SAM_PINMUX(c, 16, gpio, gpio) /* pc16a_ebi_a21_nandale */ #define PC16A_EBI_A21_NANDALE \ SAM_PINMUX(c, 16, a, periph) /* pc17_gpio */ #define PC17_GPIO \ SAM_PINMUX(c, 17, gpio, gpio) /* pc17a_ebi_a22_nandcle */ #define PC17A_EBI_A22_NANDCLE \ SAM_PINMUX(c, 17, a, periph) /* pc18_gpio */ #define PC18_GPIO \ SAM_PINMUX(c, 18, gpio, gpio) /* pc18a_ebi_a0_nbs0 */ #define PC18A_EBI_A0_NBS0 \ SAM_PINMUX(c, 18, a, periph) /* pc18b_pwmc0_pwml1 */ #define PC18B_PWMC0_PWML1 \ SAM_PINMUX(c, 18, b, periph) /* pc19_gpio */ #define PC19_GPIO \ SAM_PINMUX(c, 19, gpio, gpio) /* pc19a_ebi_a1 */ #define PC19A_EBI_A1 \ SAM_PINMUX(c, 19, a, periph) /* pc19b_pwmc0_pwmh2 */ #define PC19B_PWMC0_PWMH2 \ SAM_PINMUX(c, 19, b, periph) /* pc20_gpio */ #define PC20_GPIO \ SAM_PINMUX(c, 20, gpio, gpio) /* pc20a_ebi_a2 */ #define PC20A_EBI_A2 \ SAM_PINMUX(c, 20, a, periph) /* pc20b_pwmc0_pwml2 */ #define PC20B_PWMC0_PWML2 \ SAM_PINMUX(c, 20, b, periph) /* pc21_gpio */ #define PC21_GPIO \ SAM_PINMUX(c, 21, gpio, gpio) /* pc21a_ebi_a3 */ #define PC21A_EBI_A3 \ SAM_PINMUX(c, 21, a, periph) /* pc21b_pwmc0_pwmh3 */ #define PC21B_PWMC0_PWMH3 \ SAM_PINMUX(c, 21, b, periph) /* pc22_gpio */ #define PC22_GPIO \ SAM_PINMUX(c, 22, gpio, gpio) /* pc22a_ebi_a4 */ #define PC22A_EBI_A4 \ SAM_PINMUX(c, 22, a, periph) /* pc22b_pwmc0_pwml3 */ #define PC22B_PWMC0_PWML3 \ SAM_PINMUX(c, 22, b, periph) /* pc23_gpio */ #define PC23_GPIO \ SAM_PINMUX(c, 23, gpio, gpio) /* pc23a_ebi_a5 */ #define PC23A_EBI_A5 \ SAM_PINMUX(c, 23, a, periph) /* pc23b_tc1_tioa3 */ #define PC23B_TC1_TIOA3 \ SAM_PINMUX(c, 23, b, periph) /* pc24_gpio */ #define PC24_GPIO \ SAM_PINMUX(c, 24, gpio, gpio) /* pc24a_ebi_a6 */ #define PC24A_EBI_A6 \ SAM_PINMUX(c, 24, a, periph) /* pc24b_tc1_tiob3 */ #define PC24B_TC1_TIOB3 \ SAM_PINMUX(c, 24, b, periph) /* pc24c_spi1_spck */ #define PC24C_SPI1_SPCK \ SAM_PINMUX(c, 24, c, periph) /* pc25_gpio */ #define PC25_GPIO \ SAM_PINMUX(c, 25, gpio, gpio) /* pc25a_ebi_a7 */ #define PC25A_EBI_A7 \ SAM_PINMUX(c, 25, a, periph) /* pc25b_tc1_tclk3 */ #define PC25B_TC1_TCLK3 \ SAM_PINMUX(c, 25, b, periph) /* pc25c_spi1_npcs0 */ #define PC25C_SPI1_NPCS0 \ SAM_PINMUX(c, 25, c, periph) /* pc26_gpio */ #define PC26_GPIO \ SAM_PINMUX(c, 26, gpio, gpio) /* pc26a_ebi_a8 */ #define PC26A_EBI_A8 \ SAM_PINMUX(c, 26, a, periph) /* pc26b_tc1_tioa4 */ #define PC26B_TC1_TIOA4 \ SAM_PINMUX(c, 26, b, periph) /* pc26c_spi1_miso */ #define PC26C_SPI1_MISO \ SAM_PINMUX(c, 26, c, periph) /* pc26x_afe1_ad7 */ #define PC26X_AFE1_AD7 \ SAM_PINMUX(c, 26, x, extra) /* pc27_gpio */ #define PC27_GPIO \ SAM_PINMUX(c, 27, gpio, gpio) /* pc27a_ebi_a9 */ #define PC27A_EBI_A9 \ SAM_PINMUX(c, 27, a, periph) /* pc27b_tc1_tiob4 */ #define PC27B_TC1_TIOB4 \ SAM_PINMUX(c, 27, b, periph) /* pc27c_spi1_mosi */ #define PC27C_SPI1_MOSI \ SAM_PINMUX(c, 27, c, periph) /* pc27x_afe1_ad8 */ #define PC27X_AFE1_AD8 \ SAM_PINMUX(c, 27, x, extra) /* pc28_gpio */ #define PC28_GPIO \ SAM_PINMUX(c, 28, gpio, gpio) /* pc28a_ebi_a10 */ #define PC28A_EBI_A10 \ SAM_PINMUX(c, 28, a, periph) /* pc28b_tc1_tclk4 */ #define PC28B_TC1_TCLK4 \ SAM_PINMUX(c, 28, b, periph) /* pc28c_spi1_npcs1 */ #define PC28C_SPI1_NPCS1 \ SAM_PINMUX(c, 28, c, periph) /* pc29_gpio */ #define PC29_GPIO \ SAM_PINMUX(c, 29, gpio, gpio) /* pc29a_ebi_a11 */ #define PC29A_EBI_A11 \ SAM_PINMUX(c, 29, a, periph) /* pc29b_tc1_tioa5 */ #define PC29B_TC1_TIOA5 \ SAM_PINMUX(c, 29, b, periph) /* pc29c_spi1_npcs2 */ #define PC29C_SPI1_NPCS2 \ SAM_PINMUX(c, 29, c, periph) /* pc29x_afe1_ad4 */ #define PC29X_AFE1_AD4 \ SAM_PINMUX(c, 29, x, extra) /* pc30_gpio */ #define PC30_GPIO \ SAM_PINMUX(c, 30, gpio, gpio) /* pc30a_ebi_a12 */ #define PC30A_EBI_A12 \ SAM_PINMUX(c, 30, a, periph) /* pc30b_tc1_tiob5 */ #define PC30B_TC1_TIOB5 \ SAM_PINMUX(c, 30, b, periph) /* pc30c_spi1_npcs3 */ #define PC30C_SPI1_NPCS3 \ SAM_PINMUX(c, 30, c, periph) /* pc30x_afe1_ad5 */ #define PC30X_AFE1_AD5 \ SAM_PINMUX(c, 30, x, extra) /* pc31_gpio */ #define PC31_GPIO \ SAM_PINMUX(c, 31, gpio, gpio) /* pc31a_ebi_a13 */ #define PC31A_EBI_A13 \ SAM_PINMUX(c, 31, a, periph) /* pc31b_tc1_tclk5 */ #define PC31B_TC1_TCLK5 \ SAM_PINMUX(c, 31, b, periph) /* pc31x_afe1_ad6 */ #define PC31X_AFE1_AD6 \ SAM_PINMUX(c, 31, x, extra) /* pd0_gpio */ #define PD0_GPIO \ SAM_PINMUX(d, 0, gpio, gpio) /* pd0b_pwmc1_pwml0 */ #define PD0B_PWMC1_PWML0 \ SAM_PINMUX(d, 0, b, periph) /* pd0c_spi1_npcs1 */ #define PD0C_SPI1_NPCS1 \ SAM_PINMUX(d, 0, c, periph) /* pd0d_usart0_dcd */ #define PD0D_USART0_DCD \ SAM_PINMUX(d, 0, d, periph) /* pd0x_dacc_dac1 */ #define PD0X_DACC_DAC1 \ SAM_PINMUX(d, 0, x, extra) /* pd1_gpio */ #define PD1_GPIO \ SAM_PINMUX(d, 1, gpio, gpio) /* pd1b_pwmc1_pwmh0 */ #define PD1B_PWMC1_PWMH0 \ SAM_PINMUX(d, 1, b, periph) /* pd1c_spi1_npcs2 */ #define PD1C_SPI1_NPCS2 \ SAM_PINMUX(d, 1, c, periph) /* pd1d_usart0_dtr */ #define PD1D_USART0_DTR \ SAM_PINMUX(d, 1, d, periph) /* pd2_gpio */ #define PD2_GPIO \ SAM_PINMUX(d, 2, gpio, gpio) /* pd2b_pwmc1_pwml1 */ #define PD2B_PWMC1_PWML1 \ SAM_PINMUX(d, 2, b, periph) /* pd2c_spi1_npcs3 */ #define PD2C_SPI1_NPCS3 \ SAM_PINMUX(d, 2, c, periph) /* pd2d_usart0_dsr */ #define PD2D_USART0_DSR \ SAM_PINMUX(d, 2, d, periph) /* pd3_gpio */ #define PD3_GPIO \ SAM_PINMUX(d, 3, gpio, gpio) /* pd3b_pwmc1_pwmh1 */ #define PD3B_PWMC1_PWMH1 \ SAM_PINMUX(d, 3, b, periph) /* pd3c_uart4_txd */ #define PD3C_UART4_TXD \ SAM_PINMUX(d, 3, c, periph) /* pd3d_usart0_ri */ #define PD3D_USART0_RI \ SAM_PINMUX(d, 3, d, periph) /* pd4_gpio */ #define PD4_GPIO \ SAM_PINMUX(d, 4, gpio, gpio) /* pd4b_pwmc1_pwml2 */ #define PD4B_PWMC1_PWML2 \ SAM_PINMUX(d, 4, b, periph) /* pd4c_trace_d0 */ #define PD4C_TRACE_D0 \ SAM_PINMUX(d, 4, c, periph) /* pd4d_usart2_dcd */ #define PD4D_USART2_DCD \ SAM_PINMUX(d, 4, d, periph) /* pd5_gpio */ #define PD5_GPIO \ SAM_PINMUX(d, 5, gpio, gpio) /* pd5b_pwmc1_pwmh2 */ #define PD5B_PWMC1_PWMH2 \ SAM_PINMUX(d, 5, b, periph) /* pd5c_trace_d1 */ #define PD5C_TRACE_D1 \ SAM_PINMUX(d, 5, c, periph) /* pd5d_usart2_dtr */ #define PD5D_USART2_DTR \ SAM_PINMUX(d, 5, d, periph) /* pd6_gpio */ #define PD6_GPIO \ SAM_PINMUX(d, 6, gpio, gpio) /* pd6b_pwmc1_pwml3 */ #define PD6B_PWMC1_PWML3 \ SAM_PINMUX(d, 6, b, periph) /* pd6c_trace_d2 */ #define PD6C_TRACE_D2 \ SAM_PINMUX(d, 6, c, periph) /* pd6d_usart2_dsr */ #define PD6D_USART2_DSR \ SAM_PINMUX(d, 6, d, periph) /* pd7_gpio */ #define PD7_GPIO \ SAM_PINMUX(d, 7, gpio, gpio) /* pd7b_pwmc1_pwmh3 */ #define PD7B_PWMC1_PWMH3 \ SAM_PINMUX(d, 7, b, periph) /* pd7c_trace_d3 */ #define PD7C_TRACE_D3 \ SAM_PINMUX(d, 7, c, periph) /* pd7d_usart2_ri */ #define PD7D_USART2_RI \ SAM_PINMUX(d, 7, d, periph) /* pd8_gpio */ #define PD8_GPIO \ SAM_PINMUX(d, 8, gpio, gpio) /* pd8b_pwmc0_pwmfi1 */ #define PD8B_PWMC0_PWMFI1 \ SAM_PINMUX(d, 8, b, periph) /* pd8d_trace_clk */ #define PD8D_TRACE_CLK \ SAM_PINMUX(d, 8, d, periph) /* pd9_gpio */ #define PD9_GPIO \ SAM_PINMUX(d, 9, gpio, gpio) /* pd9b_pwmc0_pwmfi2 */ #define PD9B_PWMC0_PWMFI2 \ SAM_PINMUX(d, 9, b, periph) /* pd9c_afe1_adtrg */ #define PD9C_AFE1_ADTRG \ SAM_PINMUX(d, 9, c, periph) /* pd10_gpio */ #define PD10_GPIO \ SAM_PINMUX(d, 10, gpio, gpio) /* pd10b_pwmc0_pwml0 */ #define PD10B_PWMC0_PWML0 \ SAM_PINMUX(d, 10, b, periph) /* pd10c_ssc_td */ #define PD10C_SSC_TD \ SAM_PINMUX(d, 10, c, periph) /* pd11_gpio */ #define PD11_GPIO \ SAM_PINMUX(d, 11, gpio, gpio) /* pd11b_pwmc0_pwmh0 */ #define PD11B_PWMC0_PWMH0 \ SAM_PINMUX(d, 11, b, periph) /* pd11d_isi_d5 */ #define PD11D_ISI_D5 \ SAM_PINMUX(d, 11, d, periph) /* pd12_gpio */ #define PD12_GPIO \ SAM_PINMUX(d, 12, gpio, gpio) /* pd12c_spi0_npcs2 */ #define PD12C_SPI0_NPCS2 \ SAM_PINMUX(d, 12, c, periph) /* pd12d_isi_d6 */ #define PD12D_ISI_D6 \ SAM_PINMUX(d, 12, d, periph) /* pd13_gpio */ #define PD13_GPIO \ SAM_PINMUX(d, 13, gpio, gpio) /* pd13c_ebi_sda10 */ #define PD13C_EBI_SDA10 \ SAM_PINMUX(d, 13, c, periph) /* pd14_gpio */ #define PD14_GPIO \ SAM_PINMUX(d, 14, gpio, gpio) /* pd14c_ebi_sdcke */ #define PD14C_EBI_SDCKE \ SAM_PINMUX(d, 14, c, periph) /* pd15_gpio */ #define PD15_GPIO \ SAM_PINMUX(d, 15, gpio, gpio) /* pd15b_usart2_rxd */ #define PD15B_USART2_RXD \ SAM_PINMUX(d, 15, b, periph) /* pd15c_ebi_nwr1_nbs1 */ #define PD15C_EBI_NWR1_NBS1 \ SAM_PINMUX(d, 15, c, periph) /* pd16_gpio */ #define PD16_GPIO \ SAM_PINMUX(d, 16, gpio, gpio) /* pd16b_usart2_txd */ #define PD16B_USART2_TXD \ SAM_PINMUX(d, 16, b, periph) /* pd16c_ebi_ras */ #define PD16C_EBI_RAS \ SAM_PINMUX(d, 16, c, periph) /* pd17_gpio */ #define PD17_GPIO \ SAM_PINMUX(d, 17, gpio, gpio) /* pd17b_usart2_sck */ #define PD17B_USART2_SCK \ SAM_PINMUX(d, 17, b, periph) /* pd17c_ebi_cas */ #define PD17C_EBI_CAS \ SAM_PINMUX(d, 17, c, periph) /* pd18_gpio */ #define PD18_GPIO \ SAM_PINMUX(d, 18, gpio, gpio) /* pd18a_ebi_ncs1_sdcs */ #define PD18A_EBI_NCS1_SDCS \ SAM_PINMUX(d, 18, a, periph) /* pd18b_usart2_rts */ #define PD18B_USART2_RTS \ SAM_PINMUX(d, 18, b, periph) /* pd18c_uart4_rxd */ #define PD18C_UART4_RXD \ SAM_PINMUX(d, 18, c, periph) /* pd19_gpio */ #define PD19_GPIO \ SAM_PINMUX(d, 19, gpio, gpio) /* pd19a_ebi_ncs3 */ #define PD19A_EBI_NCS3 \ SAM_PINMUX(d, 19, a, periph) /* pd19b_usart2_cts */ #define PD19B_USART2_CTS \ SAM_PINMUX(d, 19, b, periph) /* pd19c_uart4_txd */ #define PD19C_UART4_TXD \ SAM_PINMUX(d, 19, c, periph) /* pd20_gpio */ #define PD20_GPIO \ SAM_PINMUX(d, 20, gpio, gpio) /* pd20a_pwmc0_pwmh0 */ #define PD20A_PWMC0_PWMH0 \ SAM_PINMUX(d, 20, a, periph) /* pd20b_spi0_miso */ #define PD20B_SPI0_MISO \ SAM_PINMUX(d, 20, b, periph) /* pd21_gpio */ #define PD21_GPIO \ SAM_PINMUX(d, 21, gpio, gpio) /* pd21a_pwmc0_pwmh1 */ #define PD21A_PWMC0_PWMH1 \ SAM_PINMUX(d, 21, a, periph) /* pd21b_spi0_mosi */ #define PD21B_SPI0_MOSI \ SAM_PINMUX(d, 21, b, periph) /* pd21c_tc3_tioa11 */ #define PD21C_TC3_TIOA11 \ SAM_PINMUX(d, 21, c, periph) /* pd21d_isi_d1 */ #define PD21D_ISI_D1 \ SAM_PINMUX(d, 21, d, periph) /* pd22_gpio */ #define PD22_GPIO \ SAM_PINMUX(d, 22, gpio, gpio) /* pd22a_pwmc0_pwmh2 */ #define PD22A_PWMC0_PWMH2 \ SAM_PINMUX(d, 22, a, periph) /* pd22b_spi0_spck */ #define PD22B_SPI0_SPCK \ SAM_PINMUX(d, 22, b, periph) /* pd22c_tc3_tiob11 */ #define PD22C_TC3_TIOB11 \ SAM_PINMUX(d, 22, c, periph) /* pd22d_isi_d0 */ #define PD22D_ISI_D0 \ SAM_PINMUX(d, 22, d, periph) /* pd23_gpio */ #define PD23_GPIO \ SAM_PINMUX(d, 23, gpio, gpio) /* pd23a_pwmc0_pwmh3 */ #define PD23A_PWMC0_PWMH3 \ SAM_PINMUX(d, 23, a, periph) /* pd23c_ebi_sdck */ #define PD23C_EBI_SDCK \ SAM_PINMUX(d, 23, c, periph) /* pd24_gpio */ #define PD24_GPIO \ SAM_PINMUX(d, 24, gpio, gpio) /* pd24a_pwmc0_pwml0 */ #define PD24A_PWMC0_PWML0 \ SAM_PINMUX(d, 24, a, periph) /* pd24b_ssc_rf */ #define PD24B_SSC_RF \ SAM_PINMUX(d, 24, b, periph) /* pd24c_tc3_tclk11 */ #define PD24C_TC3_TCLK11 \ SAM_PINMUX(d, 24, c, periph) /* pd24d_isi_hsync */ #define PD24D_ISI_HSYNC \ SAM_PINMUX(d, 24, d, periph) /* pd25_gpio */ #define PD25_GPIO \ SAM_PINMUX(d, 25, gpio, gpio) /* pd25a_pwmc0_pwml1 */ #define PD25A_PWMC0_PWML1 \ SAM_PINMUX(d, 25, a, periph) /* pd25b_spi0_npcs1 */ #define PD25B_SPI0_NPCS1 \ SAM_PINMUX(d, 25, b, periph) /* pd25c_uart2_rxd */ #define PD25C_UART2_RXD \ SAM_PINMUX(d, 25, c, periph) /* pd25d_isi_vsync */ #define PD25D_ISI_VSYNC \ SAM_PINMUX(d, 25, d, periph) /* pd26_gpio */ #define PD26_GPIO \ SAM_PINMUX(d, 26, gpio, gpio) /* pd26a_pwmc0_pwml2 */ #define PD26A_PWMC0_PWML2 \ SAM_PINMUX(d, 26, a, periph) /* pd26b_ssc_td */ #define PD26B_SSC_TD \ SAM_PINMUX(d, 26, b, periph) /* pd26c_uart2_txd */ #define PD26C_UART2_TXD \ SAM_PINMUX(d, 26, c, periph) /* pd26d_uart1_txd */ #define PD26D_UART1_TXD \ SAM_PINMUX(d, 26, d, periph) /* pd27_gpio */ #define PD27_GPIO \ SAM_PINMUX(d, 27, gpio, gpio) /* pd27a_pwmc0_pwml3 */ #define PD27A_PWMC0_PWML3 \ SAM_PINMUX(d, 27, a, periph) /* pd27b_spi0_npcs3 */ #define PD27B_SPI0_NPCS3 \ SAM_PINMUX(d, 27, b, periph) /* pd27c_twi2_twd */ #define PD27C_TWI2_TWD \ SAM_PINMUX(d, 27, c, periph) /* pd27d_isi_d8 */ #define PD27D_ISI_D8 \ SAM_PINMUX(d, 27, d, periph) /* pd28_gpio */ #define PD28_GPIO \ SAM_PINMUX(d, 28, gpio, gpio) /* pd28a_uart3_rxd */ #define PD28A_UART3_RXD \ SAM_PINMUX(d, 28, a, periph) /* pd28c_twi2_twck */ #define PD28C_TWI2_TWCK \ SAM_PINMUX(d, 28, c, periph) /* pd28d_isi_d9 */ #define PD28D_ISI_D9 \ SAM_PINMUX(d, 28, d, periph) /* pd28x_supc_wkup5 */ #define PD28X_SUPC_WKUP5 \ SAM_PINMUX(d, 28, wkup5, wakeup) /* pd29_gpio */ #define PD29_GPIO \ SAM_PINMUX(d, 29, gpio, gpio) /* pd29c_ebi_sdwe */ #define PD29C_EBI_SDWE \ SAM_PINMUX(d, 29, c, periph) /* pd30_gpio */ #define PD30_GPIO \ SAM_PINMUX(d, 30, gpio, gpio) /* pd30a_uart3_txd */ #define PD30A_UART3_TXD \ SAM_PINMUX(d, 30, a, periph) /* pd30d_isi_d10 */ #define PD30D_ISI_D10 \ SAM_PINMUX(d, 30, d, periph) /* pd30x_afe0_ad0 */ #define PD30X_AFE0_AD0 \ SAM_PINMUX(d, 30, x, extra) /* pd31_gpio */ #define PD31_GPIO \ SAM_PINMUX(d, 31, gpio, gpio) /* pd31a_qspi_qio3 */ #define PD31A_QSPI_QIO3 \ SAM_PINMUX(d, 31, a, periph) /* pd31b_uart3_txd */ #define PD31B_UART3_TXD \ SAM_PINMUX(d, 31, b, periph) /* pd31c_pmc_pck2 */ #define PD31C_PMC_PCK2 \ SAM_PINMUX(d, 31, c, periph) /* pd31d_isi_d11 */ #define PD31D_ISI_D11 \ SAM_PINMUX(d, 31, d, periph) /* pe0_gpio */ #define PE0_GPIO \ SAM_PINMUX(e, 0, gpio, gpio) /* pe0a_ebi_d8 */ #define PE0A_EBI_D8 \ SAM_PINMUX(e, 0, a, periph) /* pe0b_tc3_tioa9 */ #define PE0B_TC3_TIOA9 \ SAM_PINMUX(e, 0, b, periph) /* pe0c_i2sc1_ws */ #define PE0C_I2SC1_WS \ SAM_PINMUX(e, 0, c, periph) /* pe0x_afe1_ad11 */ #define PE0X_AFE1_AD11 \ SAM_PINMUX(e, 0, x, extra) /* pe1_gpio */ #define PE1_GPIO \ SAM_PINMUX(e, 1, gpio, gpio) /* pe1a_ebi_d9 */ #define PE1A_EBI_D9 \ SAM_PINMUX(e, 1, a, periph) /* pe1b_tc3_tiob9 */ #define PE1B_TC3_TIOB9 \ SAM_PINMUX(e, 1, b, periph) /* pe1c_i2sc1_do */ #define PE1C_I2SC1_DO \ SAM_PINMUX(e, 1, c, periph) /* pe2_gpio */ #define PE2_GPIO \ SAM_PINMUX(e, 2, gpio, gpio) /* pe2a_ebi_d10 */ #define PE2A_EBI_D10 \ SAM_PINMUX(e, 2, a, periph) /* pe2b_tc3_tclk9 */ #define PE2B_TC3_TCLK9 \ SAM_PINMUX(e, 2, b, periph) /* pe2c_i2sc1_di */ #define PE2C_I2SC1_DI \ SAM_PINMUX(e, 2, c, periph) /* pe3_gpio */ #define PE3_GPIO \ SAM_PINMUX(e, 3, gpio, gpio) /* pe3a_ebi_d11 */ #define PE3A_EBI_D11 \ SAM_PINMUX(e, 3, a, periph) /* pe3b_tc3_tioa10 */ #define PE3B_TC3_TIOA10 \ SAM_PINMUX(e, 3, b, periph) /* pe3x_afe1_ad10 */ #define PE3X_AFE1_AD10 \ SAM_PINMUX(e, 3, x, extra) /* pe4_gpio */ #define PE4_GPIO \ SAM_PINMUX(e, 4, gpio, gpio) /* pe4a_ebi_d12 */ #define PE4A_EBI_D12 \ SAM_PINMUX(e, 4, a, periph) /* pe4b_tc3_tiob10 */ #define PE4B_TC3_TIOB10 \ SAM_PINMUX(e, 4, b, periph) /* pe4x_afe1_ad4 */ #define PE4X_AFE1_AD4 \ SAM_PINMUX(e, 4, x, extra) /* pe5_gpio */ #define PE5_GPIO \ SAM_PINMUX(e, 5, gpio, gpio) /* pe5a_ebi_d13 */ #define PE5A_EBI_D13 \ SAM_PINMUX(e, 5, a, periph) /* pe5b_tc3_tclk10 */ #define PE5B_TC3_TCLK10 \ SAM_PINMUX(e, 5, b, periph) /* pe5x_afe1_ad3 */ #define PE5X_AFE1_AD3 \ SAM_PINMUX(e, 5, x, extra)