//*****************************************************************************
//
//! @file am_hal_sysctrl.h
//!
//! @brief Functions for interfacing with the M4F system control registers
//!
//! @addtogroup sysctrl3p SYSCTRL - System Control
//! @ingroup apollo3p_hal
//! @{
//
//*****************************************************************************

//*****************************************************************************
//
// Copyright (c) 2024, Ambiq Micro, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision release_sdk_3_2_0-dd5f40c14b of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_SYSCTRL_H
#define AM_HAL_SYSCTRL_H

#ifdef __cplusplus
extern "C"
{
#endif


//*****************************************************************************
//
//! @brief Option to Enable Deepsleep Minimum Power
//!
//! This workaround is required to achieve best deepsleep performance with
//! Apollo3 Plus. Please note that at 3V operation or higher, with temperatures
//! at or below 0C, a small subset of devices will experience increased current
//! draw, up to 15uA in deepsleep, with this workaround enabled.
//!
//! For Apollo3 Plus devices manufactured before 01/28/2021, the
//! am3p_patch_ota_FLASHCACHEPGCTRL_CV.bin patch must be installed. Please
//! reference the following Knowledgebase Article for more details:
//! https://support.ambiq.com/hc/en-us/articles/4410288947213
//!
//! AM_HAL_SYSCTRL_DEEPSLEEP_WA:
//!  Default: Undefined
//
//*****************************************************************************
//#define AM_HAL_SYSCTRL_DEEPSLEEP_WA

//*****************************************************************************
//
// !Definitions for sleep mode parameter
//
//*****************************************************************************
#define AM_HAL_SYSCTRL_SLEEP_DEEP       true
#define AM_HAL_SYSCTRL_SLEEP_NORMAL     false

//*****************************************************************************
//
// !Special registers.
//
//*****************************************************************************
#define PATCHVER2   0x50023828

//*****************************************************************************
//
//! Control operations for SysCtrl
//
//*****************************************************************************
typedef enum
{
    AM_HAL_SYSCTRL_CONTROL_DEEPSLEEP_MINPWR_DIS,
    AM_HAL_SYSCTRL_CONTROL_DEEPSLEEP_MINPWR_EN,
} am_hal_sysctrl_control_e;

//*****************************************************************************
//
//! Definition of Global Power State enumeration
//
//*****************************************************************************
typedef enum
{
  AM_HAL_SYSCTRL_WAKE,
  AM_HAL_SYSCTRL_NORMALSLEEP,
  AM_HAL_SYSCTRL_DEEPSLEEP
} am_hal_sysctrl_power_state_e;

//*****************************************************************************
//
// !Write flush - This function will hold the bus until all queued write
// !operations have completed, thereby guaranteeing that all writes have
// !been flushed.
//
//*****************************************************************************
#define SYNC_READ       0x5FFF0000
#define am_hal_sysctrl_bus_write_flush()        AM_REGVAL(SYNC_READ)

//******************************************************************************
//
// External Globals.
//
//******************************************************************************
extern uint32_t g_am_hal_sysctrl_sleep_count;

//*****************************************************************************
//
// External function definitions
//
//*****************************************************************************

//*****************************************************************************
//! @brief Apply various specific commands/controls on the SYSCTRL module
//!
//! @param eControl
//! @param pArgs
//! @return uint32_t
//*****************************************************************************
extern uint32_t am_hal_sysctrl_control(am_hal_sysctrl_control_e eControl, void *pArgs);

//*****************************************************************************
//
//! @brief Place the core into sleep or deepsleep.
//!
//! This function puts the MCU to sleep or deepsleep depending on bSleepDeep.
//!
//! @param bSleepDeep - False for Normal, or True for Deep sleep.
//!     Valid values for bSleepDeep are:
//!     - AM_HAL_SYSCTRL_SLEEP_NORMAL
//!     - AM_HAL_SYSCTRL_SLEEP_DEEP
//
//*****************************************************************************
extern void am_hal_sysctrl_sleep(bool bSleepDeep);

//*****************************************************************************
//
//! @brief Enable the floating point module.
//!
//! Call this function to enable the ARM hardware floating point module.
//
//*****************************************************************************
extern void am_hal_sysctrl_fpu_enable(void);

//*****************************************************************************
//
//! @brief Disable the floating point module.
//!
//! Call this function to disable the ARM hardware floating point module.
//
//*****************************************************************************
extern void am_hal_sysctrl_fpu_disable(void);

//*****************************************************************************
//
//! @brief Enable stacking of FPU registers on exception entry.
//!
//! @param bLazy - Set to "true" to enable "lazy stacking".
//!
//! This function allows the core to save floating-point information to the
//! stack on exception entry. Setting the bLazy option enables "lazy stacking"
//! for interrupt handlers.  Normally, mixing floating-point code and interrupt
//! driven routines causes increased interrupt latency, because the core must
//! save extra information to the stack upon exception entry. With the lazy
//! stacking option enabled, the core will skip the saving of floating-point
//! registers when possible, reducing average interrupt latency.
//!
//! @note At reset of the Cortex M4, the ASPEN and LSPEN bits are set to 1,
//! enabling Lazy mode by default. Therefore this function will generally
//! only have an effect when setting for full-context save (or when switching
//! from full-context to lazy mode).
//! @par
//! @note See also:
//! infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0298a/DAFGGBJD.html/n
//! https://developer.arm.com/documentation/dai0298/a/?lang=en
//! @par
//! @note Three valid FPU context saving modes are possible.
//! 1. Lazy           ASPEN=1 LSPEN=1 am_hal_sysctrl_fpu_stacking_enable(true)
//!                                   and default.
//! 2. Full-context   ASPEN=1 LSPEN=0 am_hal_sysctrl_fpu_stacking_enable(false)
//! 3. No FPU state   ASPEN=0 LSPEN=0 am_hal_sysctrl_fpu_stacking_disable()
//! 4. Invalid        ASPEN=0 LSPEN=1
//
//*****************************************************************************
extern void am_hal_sysctrl_fpu_stacking_enable(bool bLazy);

//*****************************************************************************
//
//! @brief Disable FPU register stacking on exception entry.
//!
//! This function disables all stacking of floating point registers for
//! interrupt handlers.  This mode should only be used when it is absolutely
//! known that no FPU instructions will be executed in an ISR.
//
//*****************************************************************************
extern void am_hal_sysctrl_fpu_stacking_disable(void);

//*****************************************************************************
//
//! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl.
//!
//! This function issues a system wide reset (Apollo POR level reset).
//
//*****************************************************************************
extern void am_hal_sysctrl_aircr_reset(void);
#ifdef __cplusplus
}
#endif

#endif // AM_HAL_SYSCTRL_H

//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************