UART0 UART 0x40042000 0 0x1000 registers UART0 UART0 IRQ 14 CTRL Control Register. 0x00 32 ENABLE UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled. 0 1 dis UART disabled. FIFOs are flushed. Clock is gated off for power savings. 0 en UART enabled. 1 PARITY_EN Enable/disable Parity bit (9th character). 1 1 dis No Parity 0 en Parity enabled as 9th bit 1 PARITY When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1; Space parity = always 0. 2 2 Even Even parity selected. 0 ODD Odd parity selected. 1 MARK Mark parity selected. 2 SPACE Space parity selected. 3 PARMD Selects parity based on 1s or 0s count (when PARITY_EN=1). 4 1 1 Parity calculation is based on number of 1s in frame. 0 0 Parity calculation is based on number of 0s in frame. 1 TX_FLUSH Flushes the TX FIFO buffer. 5 1 RX_FLUSH Flushes the RX FIFO buffer. 6 1 BITACC If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation. 7 1 FRAME Frame accuracy. 0 BIT Bit accuracy. 1 CHAR_SIZE Selects UART character size. 8 2 5 5 bits. 0 6 6 bits. 1 7 7 bits. 2 8 8 bits. 3 STOPBITS Selects the number of stop bits that will be generated. 10 1 1 1 stop bit. 0 1_5 1.5 stop bits. 1 FLOW_CTRL Enables/disables hardware flow control. 11 1 en HW Flow Control with RTS/CTS enabled 1 dis HW Flow Control disabled 0 FLOW_POL RTS/CTS polarity. 12 1 0 RTS/CTS asserted is logic 0. 0 1 RTS/CTS asserted is logic 1. 1 NULL_MODEM NULL Modem Support (RTS/CTS and TXD/RXD swap). 13 1 DIS Direct convention. 0 EN Null Modem Mode. 1 BREAK Break control bit. It causes a break condition to be transmitted to receiving UART. 14 1 DIS Break characters are not generated. 0 EN Break characters are sent (all the bits are at '0' including start/parity/stop). 1 CLKSEL Baud Rate Clock Source Select. Selects the baud rate clock. 15 1 SYSTEM System clock. 0 ALTERNATE Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. 1 RX_TO RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read. 16 8 THRESH_CTRL Threshold Control register. 0x04 32 RX_FIFO_THRESH RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. 0 6 TX_FIFO_THRESH TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. 8 6 RTS_FIFO_THRESH RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. 16 6 STATUS Status Register. 0x08 32 read-only TX_BUSY Read-only flag indicating the UART transmit status. 0 1 read-only RX_BUSY Read-only flag indicating the UARTreceiver status. 1 1 read-only PARITY 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. 2 1 read-only BREAK Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). 3 1 read-only RX_EMPTY Read-only flag indicating the RX FIFO state. 4 1 read-only RX_FULL Read-only flag indicating the RX FIFO state. 5 1 read-only TX_EMPTY Read-only flag indicating the TX FIFO state. 6 1 read-only TX_FULL Read-only flag indicating the TX FIFO state. 7 1 read-only RX_FIFO_CNT Indicates the number of bytes currently in the RX FIFO. 8 6 read-only TX_FIFO_CNT Indicates the number of bytes currently in the TX FIFO. 16 6 read-only INT_EN Interrupt Enable Register. 0x0C 32 RX_FRAME_ERROR Enable for RX Frame Error Interrupt. 0 1 RX_PARITY_ERROR Enable for RX Parity Error interrupt. 1 1 CTS_CHANGE Enable for CTS signal change interrupt. 2 1 RX_OVERRUN Enable for RX FIFO OVerrun interrupt. 3 1 RX_FIFO_THRESH Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. 4 1 TX_FIFO_ALMOST_EMPTY Enable for interrupt when TX FIFO has only one byte remaining. 5 1 TX_FIFO_THRESH Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. 6 1 BREAK Enable for received BREAK character interrupt. 7 1 RX_TIMEOUT Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). 8 1 LAST_BREAK Enable for Last break character interrupt. 9 1 INT_FL Interrupt Status Flags. 0x10 32 oneToClear FRAME FLAG for RX Frame Error Interrupt. 0 1 PARITY FLAG for RX Parity Error interrupt. 1 1 CTS_CHANGE FLAG for CTS signal change interrupt. 2 1 RX_OVERRUN FLAG for RX FIFO Overrun interrupt. 3 1 RX_FIFO_THRESH FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. 4 1 TX_FIFO_ALMOST_EMPTY FLAG for interrupt when TX FIFO has only one byte remaining. 5 1 TX_FIFO_THRESH FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. 6 1 BREAK FLAG for received BREAK character interrupt. 7 1 RX_TIMEOUT FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). 8 1 LAST_BREAK FLAG for Last break character interrupt. 9 1 BAUD0 Baud rate register. Integer portion. 0x14 32 IBAUD Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). 0 12 FACTOR FACTOR must be chosen to have IDIV> 0. factor used in calculation = 128 > > FACTOR. 16 3 128 Baud Factor 128 0 64 Baud Factor 64 1 32 Baud Factor 32 2 16 Baud Factor 16 3 BAUD1 Baud rate register. Decimal Setting. 0x18 32 DBAUD Decimal portion of baud rate divisor value. DIV = InputClock/ (factor*Baud Rate Frequency). DDIV= (DIV-IDIV) *128. 0 12 FIFO FIFO Data buffer. 0x1C 32 FIFO Load/unload location for TX and RX FIFO buffers. 0 8 DMA DMA Configuration. 0x20 32 TXDMA_EN TX DMA channel enable. 0 1 dis DMA is disabled 0 en DMA is enabled 1 RXDMA_EN RX DMA channel enable. 1 1 dis DMA is disabled 0 en DMA is enabled 1 RXDMA_START Receive DMA Start. 3 1 RXDMA_AUTO_TO Receive DMA Timeout Start. 5 1 TXDMA_LEVEL TX threshold for DMA transmission. 8 6 RXDMA_LEVEL RX threshold for DMA transmission. 16 6 TX_FIFO Transmit FIFO Status register. 0x24 32 DATA Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned). 0 8