TRNG Random Number Generator. 0x400B5000 0x00 0x1000 registers TRNG TRNG interrupt. 4 CTRL TRNG Control Register. 0x00 0xFFFFFFC0 RNG_IE To enable IRQ generation when a new 32-bit Random number is ready. 2 1 dis Disable 0 en Enable 1 RNG_ISC Clears the RNG interrupt occuring after an 128-bit random number is ready. 3 1 clear Clear the RNG interrupt. 1 RNG_I4S This bit is set when a new 128 bit random number is ready to be read (using 4 consecutive reads of TRNG_DATA. When set, an interrupt will be generated if TRNG_CTRL.rng_ie = 1. This bit is cleared by setting TRNG_CTRL.rng_isc. 4 1 not_ready 128-bit random number not ready. 0 ready 128-bit random number ready. 1 RNG_IS This bit is set when a new 32 bit random number is available in TRNG_DATA. 5 1 not_ready 32-bit random number not ready. 0 ready 32-bit random number ready. 1 AESKG When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. 6 1 DATA Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x04 read-only DATA Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. 0 32