TMR Low-Power Configurable Timer 0x40010000 0x00 0x1000 registers TMR 1 CNT Timer Counter Register. 0x00 read-write COUNT The current count value for the timer. This field increments as the timer counts. 0 32 CMP Timer Compare Register. 0x04 read-write COMPARE The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. 0 32 PWM Timer PWM Register. 0x08 read-write PWM Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. 0 32 INTFL Timer Interrupt Status Register. 0x0C read-write IRQ_A Interrupt Flag for Timer A. 0 1 WRDONE_A Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. 8 1 WR_DIS_A Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. 9 1 IRQ_B Interrupt Flag for Timer B. 16 1 WRDONE_B Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. 24 1 WR_DIS_B Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. 25 1 CTRL0 Timer Control Register. 0x10 read-write MODE_A Mode Select for Timer A 0 4 ONE_SHOT One-Shot Mode 0 CONTINUOUS Continuous Mode 1 COUNTER Counter Mode 2 PWM PWM Mode 3 CAPTURE Capture Mode 4 COMPARE Compare Mode 5 GATED Gated Mode 6 CAPCOMP Capture/Compare Mode 7 DUAL_EDGE Dual Edge Capture Mode 8 IGATED Inactive Gated Mode 14 CLKDIV_A Clock Divider Select for Timer A 4 4 DIV_BY_1 Prescaler Divide-By-1 0 DIV_BY_2 Prescaler Divide-By-2 1 DIV_BY_4 Prescaler Divide-By-4 2 DIV_BY_8 Prescaler Divide-By-8 3 DIV_BY_16 Prescaler Divide-By-16 4 DIV_BY_32 Prescaler Divide-By-32 5 DIV_BY_64 Prescaler Divide-By-64 6 DIV_BY_128 Prescaler Divide-By-128 7 DIV_BY_256 Prescaler Divide-By-256 8 DIV_BY_512 Prescaler Divide-By-512 9 DIV_BY_1024 Prescaler Divide-By-1024 10 DIV_BY_2048 Prescaler Divide-By-2048 11 DIV_BY_4096 TBD 12 POL_A Timer Polarity for Timer A 8 1 PWMSYNC_A PWM Synchronization Mode for Timer A 9 1 NOLHPOL_A PWM Phase A (Non-Overlapping High) Polarity for Timer A 10 1 NOLLPOL_A PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A 11 1 PWMCKBD_A PWM Phase A-Prime Output Disable for Timer A 12 1 RST_A Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. 13 1 CLKEN_A Write 1 to Enable CLK_TMR for Timer A 14 1 EN_A Enable for Timer A 15 1 MODE_B Mode Select for Timer B 16 4 ONE_SHOT One-Shot Mode 0 CONTINUOUS Continuous Mode 1 COUNTER Counter Mode 2 PWM PWM Mode 3 CAPTURE Capture Mode 4 COMPARE Compare Mode 5 GATED Gated Mode 6 CAPCOMP Capture/Compare Mode 7 DUAL_EDGE Dual Edge Capture Mode 8 IGATED Inactive Gated Mode 14 CLKDIV_B Clock Divider Select for Timer B 20 4 DIV_BY_1 Prescaler Divide-By-1 0 DIV_BY_2 Prescaler Divide-By-2 1 DIV_BY_4 Prescaler Divide-By-4 2 DIV_BY_8 Prescaler Divide-By-8 3 DIV_BY_16 Prescaler Divide-By-16 4 DIV_BY_32 Prescaler Divide-By-32 5 DIV_BY_64 Prescaler Divide-By-64 6 DIV_BY_128 Prescaler Divide-By-128 7 DIV_BY_256 Prescaler Divide-By-256 8 DIV_BY_512 Prescaler Divide-By-512 9 DIV_BY_1024 Prescaler Divide-By-1024 10 DIV_BY_2048 Prescaler Divide-By-2048 11 DIV_BY_4096 TBD 12 POL_B Timer Polarity for Timer B 24 1 PWMSYNC_B PWM Synchronization Mode for Timer B 25 1 NOLHPOL_B PWM Phase A (Non-Overlapping High) Polarity for Timer B 26 1 NOLLPOL_B PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B 27 1 PWMCKBD_B PWM Phase A-Prime Output Disable for Timer B 28 1 RST_B Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. 29 1 CLKEN_B Write 1 to Enable CLK_TMR for Timer B 30 1 EN_B Enable for Timer B 31 1 NOLCMP Timer Non-Overlapping Compare Register. 0x14 read-write LO_A Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 0 8 HI_A Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 8 8 LO_B Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 16 8 HI_B Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 24 8 CTRL1 Timer Configuration Register. 0x18 read-write CLKSEL_A Timer Clock Select for Timer A 0 2 CLKEN_A Timer A Enable Status 2 1 CLKRDY_A CLK_TMR Ready Flag for Timer A 3 1 EVENT_SEL_A Event Select for Timer A 4 3 NEGTRIG_A Negative Edge Trigger for Event for Timer A 7 1 IE_A Interrupt Enable for Timer A 8 1 CAPEVENT_SEL_A Capture Event Select for Timer A 9 2 SW_CAPEVENT_A Software Capture Event for Timer A 11 1 WE_A Wake-Up Enable for Timer A 12 1 OUTEN_A OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A 13 1 OUTBEN_A PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A 14 1 CLKSEL_B Timer Clock Select for Timer B 16 2 CLKEN_B Timer B Enable Status 18 1 CLKRDY_B CLK_TMR Ready Flag for Timer B 19 1 EVENT_SEL_B Event Select for Timer B 20 3 NEGTRIG_B Negative Edge Trigger for Event for Timer B 23 1 IE_B Interrupt Enable for Timer B 24 1 CAPEVENT_SEL_B Capture Event Select for Timer B 25 2 SW_CAPEVENT_B Software Capture Event for Timer B 27 1 WE_B Wake-Up Enable for Timer B 28 1 CASCADE Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. 31 1 WKFL Timer Wakeup Status Register. 0x1C read-write A Wake-Up Flag for Timer A 0 1 B Wake-Up Flag for Timer B 16 1