MCR Misc Control. 0x40106C00 0x00 0x400 registers RST Low Power Reset Control Register 0x04 LPTMR0 Low Power Timer0 Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 LPTMR1 Low Power Timer1 Reset. 1 1 LPUART0 Low Power UART0 Reset. 2 1 RTC RTC Reset. 3 1 CLKCTRL Clock Control. 0x08 ERTCO_PD 32KHz Crystal Oscillator Power Down. 16 1 ERTCO_EN 32KHz Crystal Oscillator Enable. 17 1 dis Is Disabled. 0 en Is Enabled. 1 AINCOMP AIN Comparator. 0x0C PD AIN Comparator Power Down control. 0 2 HYST AIN Comparator Hysteresis control. 2 2 NSEL_COMP0 Negative input select for AIN Comparator 0. 16 4 PSEL_COMP0 Positive input select for AIN Comparator 0 20 4 NSEL_COMP1 Negative input select for AIN Comparator 1 24 4 PSEL_COMP1 Positive input select for AIN Comparator 1 28 4 LPPIOCTRL Low Power Peripheral IO Control Register. 0x10 LPTMR0_I Enable control for LPTMR0 input. 0 1 LPTMR0_O Enable control for LPTMR0 output. 1 1 LPTMR1_I Enable control for LPTMR1 input. 2 1 LPTMR1_O Enable control for LPTMR1 output. 3 1 LPUART0_RX Enable control for LPUART0 RX. 4 1 LPUART0_TX Enable control for LPUART0 TX. 5 1 LPUART0_CTS Enable control for LPUART0 CTS. 6 1 LPUART0_RTS Enable control for LPUART0 RTS. 7 1 PCLKDIS Low Power Peripheral Clock Disable. 0x24 LPTMR0 Low Power Timer0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 LPTMR1 Low Power Timer1 Clock Disable. 1 1 LPUART0 Low Power UART0 Clock Disable. 2 1 AESKEY AES Key Pointer and Status. 0x34 PTR AESKEY Pointer and Status. 0 16 ADC_CFG0 ADC Cfig Register0. 0x38 LP_5K_DIS Disable 5K divider option in low power modes 0 1 en Enable. 0 dis Disable. 1 LP_50K_DIS Disable 50K divider option in low power modes 1 1 EN Enable. 0 DIS Disable. 1 EXT_REF External Reference 2 1 REF_SEL Reference Select 3 1 ADC_CFG1 ADC Config Register1. 0x3C CH0_PU_DYN ADC PU Dynamic Control for CH0 0 1 dis divider select always used. 0 en divider select only used when channel is selected. 1 CH1_PU_DYN ADC PU Dynamic Control for CH1 1 1 CH2_PU_DYN ADC PU Dynamic Control for CH2 2 1 CH3_PU_DYN ADC PU Dynamic Control for CH3 3 1 CH4_PU_DYN ADC PU Dynamic Control for CH4 4 1 CH5_PU_DYN ADC PU Dynamic Control for CH5 5 1 CH6_PU_DYN ADC PU Dynamic Control for CH6 6 1 CH7_PU_DYN ADC PU Dynamic Control for CH7 7 1 CH8_PU_DYN ADC PU Dynamic Control for CH8 8 1 CH9_PU_DYN ADC PU Dynamic Control for CH9 9 1 CH10_PU_DYN ADC PU Dynamic Control for CH10 10 1 CH11_PU_DYN ADC PU Dynamic Control for CH11 11 1 CH12_PU_DYN ADC PU Dynamic Control for CH12 12 1 ADC_CFG2 ADC Config Register2. 0x40 CH0 Divider Select for channel 0 0 2 div1 Pass through, no divider. 0 div2_5k Divide by 2, 5Kohm. 1 div2_50k Divide by 2, 50Kohm. 2 CH1 Divider Select for channel 1 2 2 CH2 Divider Select for channel 2 4 2 CH3 Divider Select for channel 3 6 2 CH4 Divider Select for channel 4 8 2 CH5 Divider Select for channel 5 10 2 CH6 Divider Select for channel 6 12 2 CH7 Divider Select for channel 7 14 2 CH8 Divider Select for channel 8 16 2 CH9 Divider Select for channel 9 18 2 CH10 Divider Select for channel 10 20 2 CH11 Divider Select for channel 11 22 2 CH12 Divider Select for channel 12 24 2 ADC_CFG3 ADC Config Register3. 0x44 VREFM VREFM 0 7 VREFP VREFP 8 7 IDRV IDRV 16 4 VCM VCM 20 2 ATB ATB 22 2 D_IBOOST D_IBOOST 24 1