MCR Misc Control. 0x40006C00 0x00 0x400 registers RST Reset Register. 0x04 TMR3 TMR3 (LPTMR0) Reset. Setting this bit to 1 resets TMR3 (LPTMR0) block. 0 1 RTC Real Time Clock Reset. 3 1 CLKCTRL System CLock Control Register. 0x08 ERTCO_PD 32kHz Crystal Oscillator Power Down. Setting this bit powers down the ERTCO analog circuitry. 16 1 ERTCO_EN 32kHz Crystal Oscillator Enable. 17 1 AINCOMP AIN Comparator Control Register. 0x0C PD AIN Compatator Power Down control. Before AIN Comparator is powered on, the positive and negative inputs selects for the comparator should be configured. 0 2 HYST AIN Comparator Hysteresis control. 2 2 NSEL_COMP0 Negative input select for Comparator 0. No more than 1 input channel can be selected at any time. Corresponding GPIO must be configured for AF4. 16 2 PSEL_COMP0 Positive input select for AIN Comparator 0. No more than 1 input channel can be selected at any time. Corresponding GPIO must be configured for AF4. 20 2 NSEL_COMP1 Negative input select for Comparator 1. No more than 1 input channel can be selected at any time. Corresponding GPIO must be configured for AF4. 24 2 PSEL_COMP1 Positive input select for AIN Comparator 1. No more than 1 input channel can be selected at any time. Corresponding GPIO must be configured for AF4. 28 2 LPPIOCTRL Low Power Peripheral IO Control Register. 0x10 TMR3_IN Enable control for TMR3 (LPTMR0) input. If enabled, the associated GPIO input is connected to the peripheral; otherwise the input to the peripheral is forced low. 0 1 TMR3_OUT Enable control for LPTMR0 output. If enabled and peripheral clock also enabled (PCLKDIS.LPTMR0), the peripheral output controls the associated GPIO in output mode; otherwise GPIO control comes from GPIO control module. 1 1 TMR3_OUT_N Enable control for TMR3 (LPTMR0) complementary output. If enabled and peripheral clock also enabled (PCLKDIS.TMR3), the peripheral output controls the associated GPIO in output mode; otherwise GPIO control comes from GPIO control module 2 1 PCLKDIS Peripheral Clock Disable Register. 0x24 TMR3 TMR3 (LPTMR0) Clock Disable. 0 1 AESKEY AES Key Pointer and Status Register. 0x34 PTR AES Key Pointer/Status 0 16 ADCCFG0 ADC Config Register 0. 0x38 LP_EXTCLK_EN Enable input driver for LP External Clock. 0 1 EXT_REF External Reference Select. 2 1 INT_REF Internal Reference Select Option, when not using External Reference. 3 1 ADCCFG1 ADC Config Register 1. 0x3C THRU_PAD_SW_EN Enable the MUX switch, switch placed in padring, used in the buffer path. Each pad has a separate THRU_PAD_SW_EN signal. 0 4 AIN_INP_EN AIN Input Enable. 4 4 THRU_EN Enable the MUX switches, switch placed in analog_sys, used in the buffer path. 8 1 AMP_EN Enable the buffer amplifier used in the buffer path. 9 1 AMP_RRI_EN Enable the buffer amplifier to operatore for Rail to Rail Input, Active High. If it is low, only NMOS Input pair will be operating which would restrict the range, 10 1 DIVSEL Select one of the three different signal paths. 11 2 ADCCFG2 ADC Config Register 2. 0x40 VREFM Trimming code for VREFM output of reference buffer. 0 7 VREFP Trimming code for VREFP output of reference buffer. 8 7 IDRV Trimming code for reference buffer drive strength. 16 4 VCM Trimming code for VCM output of reference buffer. 20 2 D_IBOOST Trimming value for extra drive current in reference buffer outputs 24 1