GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE. 0 1 dis Boundary Scan TAP port disabled. 0 en Boundary Scan TAP port enabled. 1 SBUSARB System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 1 2 fix Fixed Burst abritration. 0 round Round-robin scheme. 1 FPU_DIS Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. 5 1 SFCC_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 CHKRES1 Result of CPU1 ROM1 Checksum. 11 1 CCHK1 Compute CPU1 ROM1 Checksum 12 1 CCHK0 Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 SWD_DIS Serial Wire Debug Disable. 14 1 CHKRES0 ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 RST0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT0 Watchdog Timer 0 Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TMR0 Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TMR3 Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 TMR4 Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. 9 1 TMR5 Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. 10 1 UART0 UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI0 SPI 0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 I2C0 I2C 0 Reset. 16 1 CRYPTO Crypto Reset. 18 1 USB USB Reset. 23 1 TRNG TRNG Reset. 24 1 ADC ADC Reset. 26 1 UART2 UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 PCLK_DIV PCLK Divider. 3 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 ISO The internal 60 MHz oscillator is used for the system clock. 0 ERFO The external 32 MHz input is used for the system clock. 2 INRO 8 kHz LIRC is used for the system clock. 3 IPO The internal 100 MHz oscillator is used for the system clock. 4 IBRO The internal 7.3725 MHz oscillator is used for the system clock. 5 ERTCO External 32 kHz input is used for the system clock. 6 CRYPTOCLK_DIV Cryptographic clock divider 12 1 non_div The cryptographic accelerator clock is running in non-divided mode. 0 div The cryptographic accelerator clock is running in divided mode. 1 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 IPO_DIV IPO Divider. 14 2 DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 DIV8 Divide by 8. 3 ERFO_EN 27 MHz Crystal Oscillator Enable. 16 1 dis Is Disabled. 0 en Is Enabled. 1 ISO_EN 60 MHz Internal Oscillator Enable. 18 1 IPO_EN 100 MHz Clock Enable. 19 1 IBRO_EN 7.3725 MHz Clock Enable. 20 1 IBRO_VS 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO. 21 1 Vcor VCore Supply 0 1V Dedicated 1V regulated supply. 1 ERFO_RDY 32 MHz Oscillator Ready 24 1 read-only not Is not Ready. 0 ready Is Ready. 1 ERTCO_RDY 32 kHz Crystal Oscillator Ready 25 1 ISO_RDY 60 MHz Oscillator Ready. 26 1 IPO_RDY 100 MHz Clock Ready. 27 1 IBRO_RDY 7.3725 MHz HIRC Ready. 28 1 INRO_RDY 8 kHz Low Frequency Reference Clock Ready. 29 1 PM Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 sleep Sleep Mode. 1 deepsleep DeepSleep Mode. 2 shutdown ShutDown Mode. 3 backup Backup Mode. 4 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTC_WE RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 USB_WE USB Wake Up Enable. This bit enables USB IRQ as wakeup source 6 1 ERFO_PD 27 MHz power down. This bit selects the 27 MHz clock power state in DEEPSLEEP mode. 12 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 ISO_PD 60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode. 15 1 IPO_PD 100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. 16 1 IBRO_PD 7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. 17 1 ERFO_BP 27MHz Oscillator Bypass. 20 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 SKBDFRQ GCR Frequency Indicator for Secure Keyboard. 0 3 ADCFRQ ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ) 10 4 AONCLKDIV AON Clock Divider. These bits define the AON Domain Clock Divider. 14 2 div4 0 div8 1 div16 2 div32 3 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Clock Disable. 1 1 USB USB Clock Disable. 3 1 DMA DMA Clock Disable. 5 1 SPI0 SPI 0 Clock Disable. 6 1 SPI1 SPI 1 Clock Disable. 7 1 UART0 UART 0 Clock Disable. 9 1 UART1 UART 1 Clock Disable. 10 1 I2C0 I2C 0 Clock Disable. 13 1 CRYPTO Crypto Clock Disable. 14 1 TMR0 Timer 0 Clock Disable. 15 1 TMR1 Timer 1 Clock Disable. 16 1 TMR2 Timer 2 Clock Disable. 17 1 TMR3 Timer 3 Clock Disable. 18 1 TMR4 Timer 4 Clock Disable. 19 1 TMR5 Timer 5 Clock Disable. 20 1 SKBD Secure Keypad Clock Disable. 22 1 ADC ADC Clock Disable. 23 1 HTMR0 High Speed Timer 0 Clock Disable. 26 1 HTMR1 High Speed Timer 1 Clock Disable. 27 1 I2C1 I2C 1 Clock Disable. 28 1 PT Pluse Train Clock Disable. 29 1 SPIXIP SPI XIP Clock Disable. 30 1 SPIXIPC SPI XIPC Clock Disable. 31 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 RAM4_WS System RAM4 WS Select. 4 1 RAM5_WS System RAM5 WS Select. 5 1 RAM6_WS System RAM6 WS Select. 6 1 ROM1_WS ROM1 WS Select. 7 1 RAM0LS_EN System RAM 0 Light Sleep Mode. 16 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 RAM1LS_EN System RAM 1 Light Sleep Mode. 17 1 RAM2LS_EN System RAM 2 Light Sleep Mode. 18 1 RAM3LS_EN System RAM 3 Light Sleep Mode. 19 1 RAM4LS_EN System RAM 4 Light Sleep Mode. 20 1 RAM5LS_EN System RAM 5 Light Sleep Mode. 21 1 RAM6LS_EN System RAM 6 Light Sleep Mode. 22 1 ICCXIPLS_EN ICACHE-XIP RAM Light Sleep Mode. 25 1 CRYPTOLS_EN MEU RAM Light Sleep Mode. 27 1 USBLS_EN USB FIFO Light Sleep Mode. 28 1 ROM0LS_EN ROM0 Light Sleep Mode. 29 1 ROM1LS_EN ROM1 Light Sleep Mode. 30 1 MAALS_EN MAA Light Sleep Mode. 31 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM Block 0 Zeroization. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM Block 1 Zeroization. 1 1 RAM2 System RAM Block 2 Zeroization. 2 1 RAM3 System RAM Block 3 Zeroization. 3 1 RAM4 System RAM Block 4 Zeroization. 4 1 RAM5 System RAM Block 5 Zeroization. 5 1 RAM6 System RAM Block 6 Zeroization. 6 1 ICCXIP Internal ICC XIP Data and Tag RAM Zeroization. 9 1 CRYPTO MEU Memory Zeroization. 12 1 USBFIFO USB FIFO Zeroization. 13 1 SCCLKCTRL Smart Card Clock Control. 0x34 0x00000000 SC0CLK_DIV Smart Card0 Clock Divider 0 6 SC1CLK_DIV Smart Card1 Clock Divider 8 6 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 CODEINTERR Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. 1 1 norm Normal Operating Condition. 0 code Code Integrity Error. 1 SCMEMF System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. 5 1 norm Normal Operating Condition. 0 memory Memory Fault. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset_read read reset_done Reset complete. 0 busy Starts reset or indicates reset in progress. 1 PT PT Reset. 1 1 SPIXIP SPI XIPF Reset. 3 1 SPIXIPM SPI XIP Master Reset. 4 1 WDT1 WDT1 Reset. 8 1 SPI3 SPI3 Reset. 9 1 AC Auto-Cal Reset. 14 1 SEMA Semaphore Reset. 16 1 UART3 UART3 Reset. 18 1 SKBD SKBD Reset. 21 1 MSRADC MSRADC Reset. 22 1 SC0 SC0 Reset. 23 1 SC1 SC1 Reset. 24 1 HTMR0 HTIMER0 Reset. 28 1 HTMR1 HTIMER1 Reset. 29 1 CPU1 CPU1 Reset. 31 1 PCLKDIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Clock Disable. 1 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 TRNG TRNG Clock Disable. 2 1 OTP OTP Clock Disable. 3 1 WDT0 Watchdog 0 Clock Disable. 4 1 WDT1 Watchdog 1 Clock Disable. 5 1 SEMA Semaphore Disable. 9 1 SPI3 SPI3 Clock Disable. 14 1 UART3 UART3 Clock Disable. 22 1 MSRADC MSRADC Clock Disable. 25 1 SC0 SC0 Clock Disable. 26 1 SC1 SC1 Clock Disable. 27 1 CPU1 CPU1 Clock Disable. 31 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 RX Enable RXEV pin event. When this bit is set, RXEV event from the CPU is output to GPIO1.9. 1 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9. 2 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 CIE Code Integrity Error Interrupt Enable. 1 1 SCMF System Cache Memory Fault Interrupt Enable. 5 1 IPOCNT IPO Warmup Count Register. 0x58 WMUPCNT TBD 0 10