GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE SBUSARB System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 1 2 Fix Fixed Burst abritration. 0 Round Round-robin scheme. 1 FLASH_PAGE_FLIP . 4 1 dis Physical layout matches logical layout. 0 en Bottom half mapped to logical top half and vice versa. 1 FPU_DIS Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4 5 1 en FPU Enabled. 0 dis FPU Disabled. 1 ICC0_FLUSH Internal Cache Controller Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 SWD_DIS Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set) 14 1 en SWD Enabled. 0 dis SWD Disabled. 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 RST0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT0 Watchdog Timer Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TMR0 Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TMR3 Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 UART0 UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI0 SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 SPI2 SPI2 Reset. Setting this bit to 1 resets all SPI 1 blocks. 15 1 I2C0 I2C0 Reset. 16 1 CTB Crypto Toolbox Reset. 18 1 TRNG TRNG Reset. 24 1 ADC ADC Reset. 26 1 UART2 UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 ERFO 32MHz Crystal is used for the system clock. 2 INRO 80kHz LIRC is used for the system clock. 3 IPO The internal 96 MHz oscillator is used for the system clock. 4 IBRO The internal 8 MHz oscillator is used for the system clock. 5 ERTCO 32kHz is used for the system clock. 6 EXTCLK External clock on gpio0 28 (AF4). 7 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 IPO_DIV Divides the HIRC96M clock before the system clock prescaler, will affect HIRC96M Autocalibration. 14 2 div1 divide clock by 1 0 div2 divide clock by 2 1 div4 divide clock by 4 2 div8 divide clock by 8 3 ERFO_EN 32MHz Crystal Oscillator Enable. 16 1 dis Is Disabled. 0 en Is Enabled. 1 IPO_EN 96MHz High Frequency Internal Reference Clock Enable. 19 1 IBRO_EN 8MHz High Frequency Internal Reference Clock Enable. 20 1 IBRO_VS 8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M. 21 1 1V Dedicated 1v regulated supply. 0 Vcor VCore Supply 1 ERFO_RDY 32MHz Crystal Oscillator Ready 24 1 read-only busy Is not Ready. 0 ready Is Ready. 1 ERTCO_RDY 32kHz Crystal Oscillator Ready 25 1 read-only busy Is not Ready. 0 ready Is Ready. 1 IPO_RDY 96MHz HIRC Ready. 27 1 IBRO_RDY 8MHz HIRC Ready. 28 1 INRO_RDY 8kHz Low Frequency Reference Clock Ready. 29 1 EXTCLK_RDY External Clock (GPIO0[11] AF2) 31 1 PM Power Management. 0x0C MODE Operating Mode. This three bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 shutdown Shutdown Mode. 3 backup Backup Mode. 4 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTC_WE RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 LPTMR0_WE TIMER4 Wake Up Enable. This bit enables TIMER4 as wakeup source. 6 1 LPTMR1_WE TIMER5 Wake Up Enable. This bit enables TIMER5 as wakeup source. 7 1 LPUART0_WE LPUART3 Wake Up Enable. This bit enables LPUART3 as wakeup source. 8 1 AINCOMP_WE AINCOMP Wake Up Enable. This bit enables AINCOMP as wakeup source. 9 1 ERFO_PD 32MHz power down. This bit selects 32MHz Crystal power state in DEEPSLEEP mode. 12 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 IPO_PD 96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode. 16 1 IBRO_PD 8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode. 17 1 ERFO_BP 32MHz Oscillator Bypass 20 1 dis Bypass Disabled. 0 en Bypass Enabled. 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 AON_CLKDIV Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider 0 3 div4 0 div8 1 div16 2 div32 3 DIV_CLK_OUT_CTRL DIV_CLK_OUT Control 14 2 off HART clock off. 0 div2 HART clock HIRC8M Div 2. 1 div4 HART clock XO32M Div 4. 2 div8 HART clock XO32M Div 8. 3 DIV_CLK_OUT_EN DIV_CLK_OUT Enable 16 1 dis HART clock Disable. 0 en HART clock Enable. 1 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Disable. 1 1 DMA DMA Disable. 5 1 SPI0 SPI 0 Disable. 6 1 SPI1 SPI 1 Disable. 7 1 SPI2 SPI 2 Disable. 8 1 UART0 UART 0 Disable. 9 1 UART1 UART 1 Disable. 10 1 I2C0 I2C 0 Disable. 13 1 CTB Crypto Disable. 14 1 TMR0 Timer 0 Disable. 15 1 TMR1 Timer 1 Disable. 16 1 TMR2 Timer 2 Disable. 17 1 TMR3 Timer 3 Disable. 18 1 ADC ADC Clock Disable. 23 1 I2C1 I2C 1 Disable. 28 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 RAMWS_EN System RAM Wait State enable 4 1 no no SRAM wait state. 0 en SRAM wait state enabled. 1 RAM0LS_EN System RAM 0 Light Sleep Mode. 8 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 RAM1LS_EN System RAM 1 Light Sleep Mode. 9 1 RAM2LS_EN System RAM 2 Light Sleep Mode. 10 1 RAM3LS_EN System RAM 3 Light Sleep Mode. 11 1 ICC0LS_EN ICache RAM Light Sleep Mode. 12 1 ROMLS_EN ROM Light Sleep Mode. 13 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM 0 Block. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM 1 zeroization. 1 1 RAM2 System RAM 2 zeroization. 2 1 RAMCB System RAM check bit zeroization. 3 1 ICC0 Instruction Cache. 4 1 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset Reset. 1 reset_done Reset complete. 0 WDT1 WDT1 Reset. 8 1 AES WDT1 Reset. 10 1 AC AC Reset. 14 1 I2C2 I2C2 Reset. 17 1 I2S I2S Reset. 23 1 QDEC QDEC Reset. 25 1 PCLKDIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Disable. 1 1 en Enable. 0 dis Disable. 1 TRNG TRNG Disable. 2 1 WDT0 WDT0 Disable. 4 1 WDT1 WDT1 Disable. 5 1 ICC0 ICACHE Disable. 11 1 AES AES Clock Disable. 15 1 I2C2 I2C2 Disable. 21 1 I2S I2S Clock Disable. 23 1 QDEC Quadrature Decoder Interface Clock Disable. 25 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 dis Event Disable. 0 en Event Enable. 1 RX Enable RXEV pin event. When this bit is set, a logic high of GPIO0[20] (AF1) will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 dis Event Disable. 0 en Event Enable. 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[21] (AF1). 2 1 dis Event Disable. 0 en Event Enable. 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 ECCERR ECC Error Register 0x64 RAM0_1 ECC System RAM0 and RAM1 Error Flag. Write 1 to clear. 0 1 RAM2 ECC System RAM2 Error Flag. Write 1 to clear. 1 1 RAM3 ECC System RAM3 Error Flag. Write 1 to clear. 2 1 ICC0 ECC Icache Error Flag. Write 1 to clear. 3 1 FLASH0 ECC Flash0 Error Flag. Write 1 to clear. 4 1 FLASH1 ECC Flash1 Error Flag. Write 1 to clear. 5 1 ECCCED ECC Correctable Error Detect Register 0x68 RAM0_1 ECC System RAM0 and RAM1 Error Flag. Write 1 to clear. 0 1 RAM2 ECC System RAM2 Error Flag. Write 1 to clear. 1 1 RAM3 ECC System RAM3 Error Flag. Write 1 to clear. 2 1 ICC0 ECC Icache Error Flag. Write 1 to clear. 3 1 FLASH0 ECC Flash0 Error Flag. Write 1 to clear. 4 1 FLASH1 ECC Flash1 Error Flag. Write 1 to clear. 5 1 ECCIE ECC IRQ Enable Register 0x6C RAM0_1 ECC System RAM0 and RAM1 Error interrupt enable. 0 1 dis interrupt disabled. 0 en interrupt enabled. 1 RAM2 ECC System RAM2 Error interrupt enable. 1 1 RAM3 ECC System RAM3 Error interrupt enable. 2 1 ICC0 ECC Icache Error interrupt enable. 3 1 FLASH0 ECC Flash0 Error interrupt enable. 4 1 FLASH1 ECC Flash1 Error interrupt enable. 5 1 ECCADDR ECC Error Address Register 0x70 DATARAMADDR ECC Error Address/TAG RAM Error Address. 0 14 DATARAMBANK ECC Error Address/DATA RAM Error Bank. 14 1 DATARAMERR ECC Error Address/DATA RAM Error Address. 15 1 TAGRAMADDR ECC Error Address/TAG RAM Error Address. 16 14 TAGRAMBANK ECC Error Address/TAG RAM Error Bank. 30 1 TAGRAMERR ECC Error Address/TAG RAM Error. 31 1