GCR Global Control Registers. 0x40000000 0 0x400 registers SCON System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. 0 1 dis Boundary Scan TAP port disabled. 0 en Boundary Scan TAP port enabled. 1 SBUSARB System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 1 2 fix Fixed Burst abritration. 0 round Round-robin scheme. 1 FLASH_PAGE_FLIP Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 4 1 normal Physical layout matches logical layout. 0 swapped Bottom half mapped to logical top half and vice versa. 1 CCACHE_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 DCACHE_FLUSH Data Cache Flush. The system cache(s) will be flushed when this bit is set. 7 1 normal Normal System Cache Operation 0 flush System Cache is flushed 1 SRCC_DIS SPIXR Cache Controller Disable. Disables the SRCC used for SPIXR code and data cache. Setting this field disables the cache and bypasses the cache line buffer. 9 1 en Is enabled. 0 dis Is Disabled. 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 OVR Operating Voltage Range. Setting these bits according to the VCore voltage allows the on-chip Random-Access memories to operate in their optimal timing range. 16 2 0_9V 0.9V +/- 10% 0 1_0V 1.0V +/- 10% 1 1_1V 1.1V +/- 10% 2 RSTR0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT0 Watchdog Timer Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TIMER0 Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TIMER1 Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TIMER2 Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TIMER3 Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 TIMER4 Timer3 Reset. Setting this bit to 1 resets Timer 4 blocks. 9 1 TIMER5 Timer3 Reset. Setting this bit to 1 resets Timer 5 blocks. 10 1 UART0 UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI1 SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 13 1 SPI2 SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. 14 1 I2C0 I2C0 Reset. 16 1 RTC Real Time Clock Reset. 17 1 CRYPTO Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block. 18 1 SMPHR SMPHR Reset. Setting this bit to 1 resets the SMPHR block. 22 1 USB USB Reset. Setting this bit resets both USB blocks. 23 1 ADC Analog to Digital Reset. 26 1 DMA1 DMA 1 Reset. 27 1 UART2 UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. 28 1 SRST Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PRST Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYSTEM System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCN Clock Control. 0x08 0x00000008 PSC Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 CLKSEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 HIRC HIRC Clock 0 XTAL32M 32MHz Crystal is used for the system clock. 2 LIRC8 8kHz LIRC is used for the system clock. 3 HIRC96 The internal 96 MHz oscillator is used for the system clock. 4 HIRC8 The internal 8 MHz oscillator is used for the system clock. 5 XTAL32k 32kHz is used for the system clock. 6 CKRDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 CCD Cryptographic clock divider 15 1 read-only non_div The cryptographic accelerator clock is running in non-divided mode. 0 div The cryptographic accelerator clock is running in divided mode. 1 X32M_EN 32MHz Crystal Oscillator Enable. 16 1 dis Is Disabled. 0 en Is Enabled. 1 X32K_EN 32kHz Crystal Oscillator Enable. 17 1 dis Is Disabled. 0 en Is Enabled. 1 HIRC_EN 60MHz High Frequency Internal Reference Clock Enable. 18 1 HIRC96M_EN 96MHz High Frequency Internal Reference Clock Enable. 19 1 HIRC8M_EN 8MHz High Frequency Internal Reference Clock Enable. 20 1 HIRC8M_VS 8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M. 21 1 Vcor VCore Supply 0 1V Dedicated 1v regulated supply. 1 X32M_RDY 32MHz Crystal Oscillator Ready 24 1 read-only not Is not Ready. 0 ready Is Ready. 1 X32K_RDY 32kHz Crystal Oscillator Ready 25 1 read-only not Is not Ready. 0 ready Is Ready. 1 HIRC_RDY 60MHz HIRC Ready. 26 1 HIRC96M_RDY 96MHz HIRC Ready. 27 1 HIRC8M_RDY 8MHz HIRC Ready. 28 1 PM Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 deepsleep DeepSleep Mode. 2 shutdown Shutdown Mode. 3 backup Backup Mode. 4 GPIOWKEN GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTCWKEN RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 USBWKEN USB Wake Up Enable. This bit enables USB activity as wakeup source. 6 1 WUTWKEN WUT Wake Up Enable. This bit enables WUT IRQ as wakeup source. 7 1 compwken COMPARATOR Input Wake Up Enable. This bit enables COMP IRQ activity as wakeup source. 8 1 HIRCPD HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode. 15 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 HIRC96MPD 96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode. 16 1 HIRC8MPD 8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode. 17 1 XTALPB 32MHz Bluetooth Oscillator Bypass. 20 1 PCKDIV Peripheral Clock Divider. 0x18 0x00000001 SDHCFRQ SDHC Clock Frequency. This bits defines the clock frequency of SDHC. 7 1 48MHz 0 24MHz 1 ADCFRQ ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/(ADCFRQ). 10 4 AONCD Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider. 14 2 div_4 PCLK divide by 4. 0 div_8 PCLK divide by 8. 1 div_16 PCLK divide by 16. 2 div_32 PCLK divide by 32. 3 PERCKCN0 Peripheral Clock Disable. 0x24 GPIO0D GPIO0 Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1D GPIO1 Disable. 1 1 USBD USB Disable. 3 1 DMAD DMA Disable. 5 1 SPI1D SPI 1 Disable. 6 1 SPI2D SPI 2 Disable. 7 1 UART0D UART 0 Disable. 9 1 UART1D UART 1 Disable. 10 1 I2C0D I2C 0 Disable. 13 1 CRYPTOD Crypto Disable. 14 1 TIMER0D Timer 0 Disable. 15 1 TIMER1D Timer 1 Disable. 16 1 TIMER2D Timer 2 Disable. 17 1 TIMER3D Timer 3 Disable. 18 1 TIMER4D Timer 4 Disable. 19 1 TIMER5D Timer 5 Disable. 20 1 ADCD ADC Disable. 23 1 I2C1D I2C 1 Disable. 28 1 PTD PT Clock Disable. 29 1 SPIXIPD SPI XiP Disable. 30 1 SPIMD SPI XiP Master Controller Disable. 31 1 MEMCKCN Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 SYSRAM0LS System RAM 0 Light Sleep Mode. 16 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM1LS System RAM 1 Light Sleep Mode. 17 1 SYSRAM2LS System RAM 2 Light Sleep Mode. 18 1 SYSRAM3LS System RAM 3 Light Sleep Mode. 19 1 SYSRAM4LS System RAM 4 Light Sleep Mode. 20 1 SYSRAM5LS System RAM 5 Light Sleep Mode. 21 1 SYSRAM6LS System RAM 6 Light Sleep Mode. 22 1 ICACHELS ICache RAM Light Sleep Mode. 24 1 ICACHEXIPLS ICACHE-XIP RAM Light Sleep Mode. 25 1 SCACHELS SysCache RAM Light Sleep Mode. 26 1 CRYPTOLS CRYPTO RAM Light Sleep Mode. 27 1 USBLS USB FIFO Light Sleep Mode. 28 1 ROM0LS ROM Light Sleep Mode. 29 1 ROM1LS ROM1 Light Sleep Mode. 30 1 ICACHE1LS ICache RAM Light Sleep Mode. 31 1 MEMZCN Memory Zeroize Control. 0x2C SRAM0Z System RAM Block 0. 0 1 nop No operation/complete. 0 start Start operation. 1 SRAM1Z System RAM Block 1. 1 1 SRAM2 System RAM Block 2. 2 1 SRAM3Z System RAM Block 3. 3 1 SRAM4Z System RAM Block 4. 4 1 SRAM5Z System RAM Block 5. 5 1 SRAM6Z System RAM Block 6. 6 1 ICACHEZ Instruction Cache. 8 1 ICACHEXIPZ Instruction Cache XIP Data and Tag Ram zeroizatoin. 9 1 SCACHEDATAZ System Cache Data Ram Zeroization. 10 1 SCACHETAGZ System Cache Tag Zeroization. 11 1 CRYPTOZ Crypto (MAA) Memory. 12 1 USBFIFOZ USB FIFO Zeroizatoin. 13 1 ICACHE1Z Instruction Cache. 14 1 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 CODEINTERR Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. 1 1 norm Normal Operating Condition. 0 code Code Integrity Error. 1 SCMEMF System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. 5 1 norm Normal Operating Condition. 0 memory Memory Fault. 1 RSTR1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset_read read reset_done Reset complete. 0 busy Starts reset or indicates reset in progress. 1 PT PT Reset. 1 1 SPIXIP SPI XiP Master Reset. 3 1 XSPIM GSPI XiP Master Controller Reset. 4 1 SDHC SDHC/SDIO Reset. 6 1 OWIRE OWIRE Reset. 7 1 WDT1 WDT1 Reset. 8 1 SPI0 SPI0 Reset. 9 1 SPIXMEM SPIXMEM Reset. 15 1 SMPHR SMPHR Reset. 16 1 WDT2 WDT2 Reset. 17 1 BTLE BTLE Reset. 18 1 AUDIO AUDIO Reset. 19 1 I2C2 I2C2 Reset. 20 1 RPU RPU Reset. 21 1 HTMR0 HTMR0 Reset. 22 1 HTMR1 HTMR1 Reset. 23 1 DVS DVS Reset. 24 1 SIMO SIMO Reset. 25 1 PERCKCN1 Peripheral Clock Disable. 0x48 BTLED BTLE Disable. 0 1 en Enable. 0 dis Disable. 1 UART2D UART2 Disable. 1 1 en Enable. 0 dis Disable. 1 TRNGD TRNG Disable. 2 1 SCACHED System Cache Clock Disable. 7 1 SDMAD SDMA Clock Disable. 8 1 SMPHRD Semaphore Clock Disable. 9 1 SDHCD SDHC/SDIO Clock Disable. 10 1 ICACHEXIPD ICache XIP Clock Disable. 12 1 OWIRED One-Wire Clock Disable. 13 1 SPI0D SPI0 Clock Disable. 14 1 SPIXIPDD SPI-XIP Data Clock Disable 20 1 DMA1D DMA1 Clock Disable 21 1 AUDIOD AUDIO Clock Disable 23 1 I2C2D I2C 2 Clock Disable 24 1 HTMR0D HTMR 0 Clock Disable 25 1 HTMR1D HTMR 1 Clock Disable 26 1 WDT0D WDT0 Clock Disable 27 1 WDT1D WDT1 Clock Disable 28 1 WDT2D WDT2 Clock Disable 29 1 CPU1D CPU1 Clock Disable 31 1 EVENT_EN Event Enable Register. 0x4C CPU0DMAEVENT Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 CPU0DMA1EVENT Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 CPU0TXEVENT Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. 2 1 CPU1DMAEVENT Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 3 1 CPU1DMA1EVENT Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. 4 1 CPU1TXEVENT Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. 5 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSSIE System Status Interrupt Enable Register. 0x54 ICEULIE ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 CIEIE Code Integrity Error Interrupt Enable. 1 1 SCMFIE System Cache Memory Fault Interrupt Enable. 5 1 ECC_ER ECC Error Register 0x64 SYSRAM0ECCERR ECC System RAM0 Error Flag. Write 1 to clear. 0 1 SYSRAM1ECCERR ECC System RAM1 Error Flag. Write 1 to clear. 1 1 SYSRAM2ECCERR ECC System RAM2 Error Flag. Write 1 to clear. 2 1 SYSRAM3ECCERR ECC System RAM3 Error Flag. Write 1 to clear. 3 1 SYSRAM4ECCERR ECC System RAM4 Error Flag. Write 1 to clear. 4 1 SYSRAM5ECCERR ECC System RAM5 Error Flag. Write 1 to clear. 5 1 SYSRAM6ECCERR ECC System RAM6 Error Flag. Write 1 to clear. 6 1 IC0ECCERR ECC Icache0 Error Flag. Write 1 to clear. 8 1 IC1ECCERR ECC Icache1 Error Flag. Write 1 to clear. 9 1 ICXIPECCERR ECC IcacheXIP Error Flag. Write 1 to clear. 10 1 FL0ECCERR ECC Flash0 Error Flag. Write 1 to clear. 11 1 FL1ECCERR ECC Flash1 Error Flag. Write 1 to clear. 12 1 ECC_CED ECC Correctable Error Detected Register 0x68 SYSRAM0ECCNDED ECC System RAM0 Error Flag. Write 1 to clear. 0 1 SYSRAM1ECCNDED ECC System RAM1 Not Double Error Detect. Write 1 to clear. 1 1 SYSRAM2ECCNDED ECC System RAM2 Not Double Error Detect. Write 1 to clear. 2 1 SYSRAM3ECCNDED ECC System RAM3 Not Double Error Detect. Write 1 to clear. 3 1 SYSRAM4ECCNDED ECC System RAM4 Not Double Error Detect. Write 1 to clear. 4 1 SYSRAM5ECCNDED ECC System RAM5 Not Double Error Detect. Write 1 to clear. 5 1 IC0ECCNDED ECC Icache0 Not Double Error Detect. Write 1 to clear. 8 1 IC1ECCNDED ECC Icache1 Not Double Error Detect. Write 1 to clear. 9 1 ICXIPECCNDED ECC IcacheXIP Not Double Error Detect. Write 1 to clear. 10 1 FL0ECCNDED ECC Flash0 Not Double Error Detect. Write 1 to clear. 11 1 FL1ECCNDED ECC Flash1 Not Double Error Detect. Write 1 to clear. 12 1 ECC_IRQEN ECC IRQ Enable Register 0x6C SYSRAM0ECCEN System RAM0 ECC Error Interrupt Enable 0 1 SYSRAM1ECCEN System RAM1 ECC Error Interrupt Enable 1 1 SYSRAM2ECCEN System RAM2 ECC Error Interrupt Enable 2 1 SYSRAM3ECCEN System RAM3 ECC Error Interrupt Enable 3 1 SYSRAM4ECCEN System RAM4 ECC Error Interrupt Enable 4 1 SYSRAM5ECCEN System RAM5 ECC Error Interrupt Enable 5 1 IC0ECCEN Icache0 ECC Error Interrupt Enable 8 1 IC1ECCEN Icache1 ECC Error Interrupt Enable 9 1 ICXIPECCEN IcacheXIP ECC Error Interrupt Enable 10 1 FL0ECCEN Flash0 NError ECC Interrupt Enable 11 1 FL1ECCEN Flash1 ECC Error Interrupt Enable 12 1 ECC_ERRAD ECC Error Address Register 0x70 DATARAMADDR ECC Error Address.Data Ram Address. 0 13 DATARAMBANK ECC Error Address.Data Error Bank. 14 1 DATARAMERR ECC Error Address.Data Ram Error. 15 1 TAGRAMADDR ECC Error Address.Tag Ram Address. 16 13 TAGRAMBANK ECC Error Address.Tag Ram Bank. 30 1 TAGRAMERR ECC Error Address.Tag Ram Error. 31 1 BTLE_LDOCR BTLE LDO Control Register 0x74 LDOTXEN LDOTX Enable 0 1 dis disabled. 0 en enabled. 1 LDOTXOPULLD LDOTX PULL Disable 1 1 en enabled. 0 dis disabled. 1 LDOTXVSEL LDOTX Voltage Setting 2 2 0_7 0.7V 0 0_85 0.85V 1 0_9 0.9V 2 1_1 1.1V 3 LDORXEN LDORX Enable 4 1 dis disabled. 0 en enabled. 1 LDORXPULLD LDORX Pulldown 5 1 en enabled. 0 dis disabled. 1 LDORXVSEL LDORX Output Voltage Setting 6 2 0_7 0.7V 0 0_85 0.85V 1 0_9 0.9V 2 1_1 1.1V 3 LDORXBYP LDORX Bypass Enable 8 1 dis disabled. 0 en enabled. 1 LDORXDISCH LDORX Discharge 9 1 dis disabled. 0 en enabled. 1 LDOTXBYP LDOTX Bypass Enable 10 1 dis disabled. 0 en enabled. 1 LDOTXDISCH LDOTX Discharge 11 1 dis disabled. 0 en enabled. 1 LDOTXENDLY LDOTX Enable Delay 12 1 dis disabled. 0 en enabled. 1 LDORXENDLY LDORX Enable Delay 13 1 dis disabled. 0 en enabled. 1 LDORXBYPENENDLY LDOTX Bypass Enable Delay 14 1 LDOTXBYPENENDLY LDORX Bypass Enable Delay 15 1 BTLE_LDODCR BTLE LDO Delay Register 0x78 BYPDLYCNT Bypass Delay Count. Count delay base on PCLK. 0 8 LDORXDLYCNT LDORX Delay Count. Count delay base on PCLK/128. 8 9 LDOTXDLYCNT LDOTX Delay Count. Count delay base on PCLK/128. 20 9 GP0 General Purpose Register 0 0x80 GPR0 User-defined register RAM. 0 32 APB_ASYNC APB Asynchronous Bridge Select Register 0x84 APBASYNCI2C0 Feeds I2C0 with either PCLK or 7.37MHz Clk 0 1 pclk PCLK Source 0 7mclk 7.37MHz Source 1 APBASYNCI2C1 Feeds I2C1 with either PCLK or 7.37MHz Clk 1 1 APBASYNCI2C2 Feeds I2C2 with either PCLK or 7.37MHz Clk 2 1 APBASYNCPT Feeds PT with either PCLK or 7.37MHz Clk 3 1