GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE SBUSARB System bus arbitration scheme. These bits are used to select between Fixed burst arbitration and Round Robin scheme. The Round Robin scheme is selected by default. 1 2 FPUS_DIS Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. 5 1 ICC0_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 SWD_DIS Serial Wire Debug Disable. 14 1 CHKRES ROM Checksum Result. This bit is valid when the checksum is done and the CCHK bit is cleared. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 RST0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT Watchdog Timer 0 Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 TMR0 Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 UART0 UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI0 SPI 0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 I2C0 I2C 0 Reset. 16 1 CAN CAN Reset. 19 1 TRNG TRNG Reset. This reset is only available during the manufacture testing phase. 24 1 ADC ADC Reset. 26 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 ERFO The external 32 MHz input is used for the system clock. 2 INRO 8 kHz LIRC is used for the system clock. 3 IPO The internal 100 MHz oscillator is used for the system clock. 4 IBRO The internal 7.3725 MHz oscillator is used for the system clock. 5 ERTCO External 32 kHz input is used for the system clock. 6 EXTCLK External clock input is used for the system clock. 7 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 IPO_DIV HIRC96M Source Clock Divider. 14 2 DIV1 Div 1 0 DIV2 Div 2 1 DIV4 Div 4 2 DIV8 Div 8 3 ERFO_EN 32 MHz Crystal Oscillator Enable. 16 1 dis Is Disabled. 0 en Is Enabled. 1 IPO_EN 100 MHz Clock Enable. 19 1 IBRO_EN 7.3725 MHz Clock Enable. 20 1 IBRO_VS 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO. 21 1 Vcor VCore Supply 0 1V Dedicated 1V regulated supply. 1 ERFO_RDY 32 MHz Oscillator Ready 24 1 read-only not Is not Ready. 0 ready Is Ready. 1 ERTCO_RDY 32 kHz Crystal Oscillator Ready 25 1 IPO_RDY 100 MHz Clock Ready. 27 1 IBRO_RDY 7.3725 MHz HIRC Ready. 28 1 INRO_RDY 8 kHz Low Frequency Reference Clock Ready. 29 1 EXTCLK_RDY External Clock GPIO0_28 AF2 Ready. Clock is ready when AF2 is enabled for GPIO0_28 31 1 PM Power Management. 0x0C MODE Operating Mode. This three bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 backup Backup Mode. 4 shutdown Shutdown Mode 7 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTC_WE RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 TMR3_WE TMR3 (LPTMR0) Wake Up Enable. This bit enables TMR3 IRQ as wakeup source 6 1 AINCOMP_WE AINCOMP Wake Up Enable. This bit enables the AINCOMP Timer as wakeup source. 7 1 ERFO_BP ERFO Bypass 20 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 AON_CLKDIV Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. 0 2 DIV4 div4 0 DIV8 div8 1 DIV16 div16 2 DIV32 div8 3 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 DMA DMA Clock Disable. 5 1 SPI0 SPI 0 Clock Disable. 6 1 SPI1 SPI 1 Clock Disable. 7 1 UART0 UART 0 Clock Disable. 9 1 UART1 UART 1 Clock Disable. 10 1 I2C0 I2C 0 Clock Disable. 13 1 TMR0 Timer 0 Clock Disable. 15 1 TMR1 Timer 1 Clock Disable. 16 1 TMR2 Timer 2 Clock Disable. 17 1 ADC ADC Clock Disable. 23 1 I2C1 I2C 1 Clock Disable. 28 1 PT Pluse Train Clock Disable. 29 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 RAMWS_EN System RAM Wait State enable. 4 1 RAM0LS_EN System RAM 0 Light Sleep mode. 8 1 RAM1LS_EN System RAM 1 Light Sleep mode. 9 1 RAM2LS_EN System RAM 2 Light Sleep mode. 10 1 RAM3LS_EN System RAM 3 Light Sleep mode. 11 1 ICC0LS_EN Internal Cache Controller RAM Light Sleep mode. 12 1 ROMLS_EN ROM Light Sleep mode. 13 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM Block 0 Zeroization. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM Block 1 Zeroization. 1 1 RAM2 System RAM Block 2 Zeroization. 2 1 RAMCB System RAM Check Bit Block Zeroization. 3 1 ICC0 Internal Cache Controller Data and Tag RAM Zeroization. 4 1 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset_read read reset_done Reset complete. 0 busy Starts reset or indicates reset in progress. 1 PT PT Reset. 1 1 AES AES Reset. 10 1 AC AC Reset. 14 1 I2S I2S Reset. 23 1 PCLKDIS1 Peripheral Clock Disable. 0x48 TRNG TRNG Clock Disable. 2 1 WDT Watchdog Timer 0 Disable. 4 1 CAN CAN Clock Disable. 11 1 AES AES Clock Disable. 15 1 AES_KEY AES Keys Clock Disable. 16 1 I2S I2S Clock Disable. 23 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 RX Enable RXEV pin event. When this bit is set, RXEV event from the CPU is output to GPIO1.9. 1 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9. 2 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 ECCERR ECC Error Register 0x64 RAM0_1 ECC System RAM0 or RAM1 Error Flag. Write 1 to clear. 0 1 RAM2 ECC System RAM2 Error Flag. Write 1 to clear. 1 1 RAM3 ECC System RAM3 Error Flag. Write 1 to clear. 2 1 ICC0 ECC ICACHE Error Flag. Write 1 to clear. 3 1 FLASH0 ECC Flash 0 Error Flag. Write 1 to clear. 4 1 FLASH1 ECC Flash 1 Error Flag. Write 1 to clear. 5 1 ECCCED ECC Not Double Error Detect Register 0x68 RAM0_1 ECC System RAM0 or RAM1 Not Double Error Flag. Write 1 to clear. 0 1 RAM2 ECC System RAM2 Not Double Error Flag. Write 1 to clear. 1 1 RAM3 ECC System RAM3 Not Double Error Flag. Write 1 to clear. 2 1 ICC0 ECC ICACHE Not Double Error Flag. Write 1 to clear. 3 1 FLASH0 ECC Flash 0 Not Double Error Flag. Write 1 to clear. 4 1 FLASH1 ECC Flash 1 Not Double Error Flag. Write 1 to clear. 5 1 ECCIE ECC IRQ Enable Register 0x6C RAM0_1 System RAM0 or RAM1 ECC Interrupt Enable. 0 1 RAM2 System RAM2 ECC Interrupt Enable. 1 1 RAM3 System RAM3 ECC Interrupt Enable. 2 1 ICC0 ICACHE ECC Interrupt Enable. 3 1 FLASH0 Flash 0 ECC Interrupt Enable. 4 1 FLASH1 Flash 1 ECC Interrupt Enable. 5 1 ECCADDR ECC Error Address Register 0x70 ERRADDR Error Address. 0 32