GCR Global Control Registers. 0x40000000 0 0x400 registers SCON System Control. 0x00 0xFFFFFFFE FLASH_PAGE_FLIP Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 4 1 normal Physical layout matches logical layout. 0 swapped Bottom half mapped to logical top half and vice versa. 1 FPU_DIS Floating Point Unit Disable 5 1 enable enable Floating point unit 0 disable disable floating point unit 1 ICC0_FLUSH Instruction Cache Controller Flush. Write 1 to flush the internal flash cache. This bit is cleared by hardware when the flush is complete. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 SWD_DIS Serial Wire Debug Disable 14 1 enable Enable JTAG SWD 0 disable Disable JTAG SWD 1 RST0 Reset. 0x04 DMA DMA Reset. 0 1 WDT0 Watchdog Timer Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 TIMER0 Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TIMER1 Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TIMER2 Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 UART0 UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI0 SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 I2C0 I2C0 Reset. 16 1 RTC Real Time Clock Reset. 17 1 SOFT Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYSTEM System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLK_CTRL Clock Control. 0x08 0x00000008 PSC Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 CLKSEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 HIRC The internal 96 MHz oscillator is used for the system clock. 0 nanoRing The nano-ring output is used for the system clock. 3 hfxIn HFXIN is used for the system clock. 6 CLKRDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 X32K_EN 32kHz Crystal Oscillator Enable. 17 1 dis Is Disabled. 0 en Is Enabled. 1 HIRC_EN 60MHz High Frequency Internal Reference Clock Enable. 18 1 X32K_RDY 32kHz Crystal Oscillator Ready 25 1 read-only not Is not Ready. 0 ready Is Ready. 1 HIRC_RDY 60MHz HIRC Ready. 26 1 LIRC8K_RDY 8kHz Low Frequency Reference Clock Ready. 29 1 PM Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 shutdown Shutdown Mode. 3 backup Backup Mode. 4 GPIOWK_EN GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTCWK_EN RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 HFIOPD HFIO DEEPSLEEP Auto Off. When set, the High-Frequency Internal Oscillator is automatically powered off when in DEEPSLEEP mode. 15 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 PCLK_DIS0 Peripheral Clock Disable. 0x24 GPIO0D GPIO0 Disable. 0 1 GPIODisable en enable it. 0 dis disable it. 1 DMAD DMA Disable. 5 1 GPIODisable en enable it. 0 dis disable it. 1 SPI0D SPI 0 Disable. 6 1 GPIODisable en enable it. 0 dis disable it. 1 SPI1D SPI 1 Disable. 7 1 GPIODisable en enable it. 0 dis disable it. 1 UART0D UART 0 Disable. 9 1 GPIODisable en enable it. 0 dis disable it. 1 UART1D UART 1 Disable. 10 1 GPIODisable en enable it. 0 dis disable it. 1 I2C0D I2C 0 Disable. 13 1 GPIODisable en enable it. 0 dis disable it. 1 TIMER0D Timer 0 Disable. 15 1 GPIODisable en enable it. 0 dis disable it. 1 TIMER1D Timer 1 Disable. 16 1 GPIODisable en enable it. 0 dis disable it. 1 TIMER2D Timer 2 Disable. 17 1 GPIODisable en enable it. 0 dis disable it. 1 I2C1D I2C 1 Disable. 28 1 GPIODisable en enable it. 0 dis disable it. 1 MEM_CTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 RAM0_LS System RAM 0 Light Sleep Mode. 8 1 active Memory is active. 0 light_sleep Memory is in Light Sleep mode. 1 RAM1_LS System RAM 1 Light Sleep Mode. 9 1 active Memory is active. 0 light_sleep Memory is in Light Sleep mode. 1 RAM2_LS System RAM 2 Light Sleep Mode. 10 1 active Memory is active. 0 light_sleep Memory is in Light Sleep mode. 1 RAM3_LS System RAM 3 Light Sleep Mode. 11 1 active Memory is active. 0 light_sleep Memory is in Light Sleep mode. 1 ICACHE_RET ICache RAM Light Sleep Mode. 12 1 active Memory is active. 0 light_sleep Memory is in Light Sleep mode. 1 MEM_ZCTRL Memory Zeroize Control. 0x2C SRAM_ZERO System RAM Block 0. 0 1 nop No operation/complete. 0 start Start operation. 1 ICACHE_ZERO Instruction Cache. 1 1 nop No operation/complete. 0 start Start operation. 1 SYS_STAT System Status Register. 0x40 ICECLOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset_write write RFU Reserved. Do not use. 0 reset Starts reset operation. 1 reset_read read reset_done Reset complete. 0 busy Reset in progress. 1 PCLK_DIS1 Peripheral Clock Disable. 0x48 FLCD Secure Flash Controller Disable. 3 1 en Enable. 0 dis Disable. 1 ICCD ICache Clock Disable. 11 1 en Enable. 0 dis Disable. 1 EVTEN Event Enable Register. 0x4C DMAEVENT Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 RX_EVT Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 REV Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYS_IE System Status Interrupt Enable 0x54 ICEULIE Arm ICE Unlocked Interrupt Enable. Set this bit to enable a PWRSEQ IRQ if the Arm ICE is unlocked. 0 1