GCR Global Control Registers. 0x40000000 0 0x400 registers SCON System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. 0 1 dis Boundary Scan TAP port disabled. 0 en Boundary Scan TAP port enabled. 1 FLASH_PAGE_FLIP Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 4 1 normal Physical layout matches logical layout. 0 flipped Bottom half mapped to logical top half and vice versa. 1 CCACHE_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 DCACHE_FLUSH Write 1 to flush the external memory controller's 16KB cache. This bit is automatically cleared to 0 when the flush is complete. 7 1 normal Normal External Cache Operation 0 flush External cache being flushed. 1 DCACHE_DIS Disable EMCC used for SPIXR or HyperBus/Xccela Bus code and data cache. 9 1 enabled EMCC enabled. 0 disabled EMCC disabled and line buffer bypassed. 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 OVR These bits select the operating voltage range. 16 2 0v9 0.9V +/- 10%. 0 1V 1.0V +/- 10%. 1 1V1 1.1V +/- 10%. 2 RST0 Reset. 0x04 DMA DMA Reset. 0 1 WDT0 Watchdog Timer Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 GPIO2 GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states. 4 1 TIMER0 Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TIMER1 Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TIMER2 Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TIMER3 Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 TIMER4 Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. 9 1 TIMER5 Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. 10 1 UART0 UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI0 SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 SPI2 SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. 15 1 I2C0 I2C0 Reset. 16 1 RTC RTC Reset. 17 1 TPU Trust Protection Unit Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block. 18 1 HBC HyperBus/Xccela controller reset. 21 1 TFT TFT controller reset. 22 1 USB USB Reset. 23 1 ADC Analog to Digital converter reset. 26 1 UART2 UART 2 reset. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLK_CTRL Clock Control. 0x08 0x00000008 SYSCLK_PRESCALE Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSOSC_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 CRYPTO Internal Primary Oscilatior Clock 0 HFXIN 24MHz Internal Oscillator is used for the system clock. 2 NANORING 8kHz Internal Nano Ring Oscillator is used for the system clock. 3 HIRC96 120 MHz Internal Oscillator. 4 HIRC8 Internal 7.3728MHz oscillator. 5 X32K External 32KHz oscillator. 6 SYSOSC_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 CCD Cryptographic clock divider 15 1 read-only non_div The cryptographic accelerator clock is running in non-divided mode. 0 div The cryptographic accelerator clock is running in divided mode. 1 X32K_EN 32KHz External Clock Enable. 17 1 CRYPTO_EN 50MHz High Frequency Internal Reference Clock Enable. 18 1 HIRC96_EN 120MHz High Frequency Internal Reference Clock Enable. 19 1 HIRC8_EN 7.3728MHz High Frequency Internal Reference Clock Enable. 20 1 HIRC8_VS 7.3728MHz Internal Oscillator Voltage Source Select 21 1 X32K_RDY 32KHz External Oscillator Ready. 25 1 CRYPTO_RDY 50MHz Internal Oscillator Ready. 26 1 HIRC96_RDY 120MHz Internal Oscillator Ready. 27 1 HIRC8_RDY 7.3728MHz Internal Oscillator Ready. 28 1 NANORING_RDY Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. 29 1 PMR Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 shutdown Shutdown Mode. 3 backup Backup Mode. 4 GPIOWKEN GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 RTCWKEN RTC Wake Up Enable. This bit enables an RTC alarm to wake the device from any low-power mode to ACTIVE mode. 5 1 USBWKEN USB Wake Up Enable. This enables a USB wakeup event to cause the device to exit from all low power modes into ACTIVE mode. 6 1 CRYPTOPD Crypto Oscilator Power Down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. 15 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 HIRC96PD 120MHz Internal Oscillator power down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. 16 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 HIRC8PD 7.3728MHz Internal Oscillator power down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. 17 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 PCLK_DIV Peripheral Clock Divider. 0x18 0x00000001 SDHCFRQ This bit selects the frequency of the SDHC clock. If set, the clock oscillates at 50Mhz, otherwise it will oscillate at 60MHz. 7 1 60M SDHC Freq = 120MHz/2. 0 50M SDHC Freq = 50Mhz. 1 ADCFRQ ADC Clock divider. ADC Clock Frequency = Periph_Clock/adcfrq. Values 0 and 1 invalid. 10 4 div2 ADC Freq = Periph_Clock/2. 2 div3 ADC Freq = Periph_Clock/3. 3 div4 ADC Freq = Periph_Clock/4. 4 div5 ADC Freq = Periph_Clock/5. 5 div6 ADC Freq = Periph_Clock/6. 6 div7 ADC Freq = Periph_Clock/7. 7 div8 ADC Freq = Periph_Clock/8. 8 div9 ADC Freq = Periph_Clock/9. 9 div10 ADC Freq = Periph_Clock/10. 10 div11 ADC Freq = Periph_Clock/11. 11 div12 ADC Freq = Periph_Clock/12. 12 div13 ADC Freq = Periph_Clock/13. 13 div14 ADC Freq = Periph_Clock/14. 14 div15 ADC Freq = Periph_Clock/15. 15 AONDIV Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider. 14 2 div4 PCLK divide by 4. 0 div8 PCLK divide by 8. 1 div16 PCLK divide by 16. 2 div32 PCLK divide by 32. 3 PCLK_DIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Disable. 1 1 en enable it. 0 dis disable it. 1 GPIO2 GPIO2 Disable. 2 1 en enable it. 0 dis disable it. 1 USB USB Disable. 3 1 en enable it. 0 dis disable it. 1 TFT TFT Disable. 4 1 en enable it. 0 dis disable it. 1 DMA DMA Disable. 5 1 en enable it. 0 dis disable it. 1 SPI0 SPI 0 Disable. 6 1 en enable it. 0 dis disable it. 1 SPI1 SPI 1 Disable. 7 1 en enable it. 0 dis disable it. 1 SPI2 SPI 2 Disable. 8 1 en enable it. 0 dis disable it. 1 UART0 UART 0 Disable. 9 1 en enable it. 0 dis disable it. 1 UART1 UART 1 Disable. 10 1 en enable it. 0 dis disable it. 1 I2C0 I2C 0 Disable. 13 1 en enable it. 0 dis disable it. 1 TPU Trust Protection Unit Disable. 14 1 en enable it. 0 dis disable it. 1 TIMER0 Timer 0 Disable. 15 1 en enable it. 0 dis disable it. 1 TIMER1 Timer 1 Disable. 16 1 en enable it. 0 dis disable it. 1 TIMER2 Timer 2 Disable. 17 1 en enable it. 0 dis disable it. 1 TIMER3 Timer 3 Disable. 18 1 en enable it. 0 dis disable it. 1 TIMER4 Timer 4 Disable. 19 1 en enable it. 0 dis disable it. 1 TIMER5 Timer 5 Disable. 20 1 en enable it. 0 dis disable it. 1 ADC ADC Disable. 23 1 en enable it. 0 dis disable it. 1 I2C1 I2C 1 Disable. 28 1 en enable it. 0 dis disable it. 1 PT Pulse Train Engine Disable. 29 1 en enable it. 0 dis disable it. 1 SPIXIPF SPI-XIPF Disable. 30 1 en enable it. 0 dis disable it. 1 SPIXIPM XSPI Master Clock Disable. 31 1 en enable it. 0 dis disable it. 1 MEM_CLK Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 1. 0 3 SYSRAM0LS System RAM 0 Light Sleep Mode. Write 1 to put RAM0 in light sleep power mode. 16 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM1LS System RAM 1 Light Sleep Mode. Write 1 to put RAM1 in light sleep power mode. 17 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM2LS System RAM 2 Light Sleep Mode. Write 1 to put RAM2 in light sleep power mode. 18 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM3LS System RAM 3 Light Sleep Mode. Write 1 to put RAM3 in light sleep power mode. 19 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM4LS System RAM 4 Light Sleep Mode. Write 1 to put RAM4 in light sleep power mode. 20 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM5LS System RAM 4 Light Sleep Mode. Write 1 to put RAM5 in light sleep power mode. 21 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM6LS System RAM 4 Light Sleep Mode. Write 1 to put RAM6 in light sleep power mode. 22 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 ICACHELS ICache RAM Light Sleep Mode. 24 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 ICACHEXIPLS SPI-XIPF Instruction Cache RAM Light Sleep Mode. 25 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SCACHELS Internal RAM Cache Light Sleep Mode. 26 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 CRYPTOLS Crypto RAM Light Sleep Mode. 27 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 USBLS USB FIFO Light Sleep Mode. 28 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 ROMLS ROM Light Sleep Mode. 29 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 MEM_ZERO Memory Zeroize Control. 0x2C SRAM0Z System RAM Block 0. 0 1 nop No operation/complete. 0 start Start operation. 1 SRAM1Z System RAM Block 1. 1 1 nop No operation/complete. 0 start Start operation. 1 SRAM2Z System RAM Block 2. 2 1 nop No operation/complete. 0 start Start operation. 1 SRAM3Z System RAM Block 3. 3 1 nop No operation/complete. 0 start Start operation. 1 SRAM4Z System RAM Block 4. 4 1 nop No operation/complete. 0 start Start operation. 1 SRAM5Z System RAM Block 5. 5 1 nop No operation/complete. 0 start Start operation. 1 SRAM6Z System RAM Block 6. 6 1 nop No operation/complete. 0 start Start operation. 1 ICACHEZ Instruction Cache (ICC0) zeroization. 8 1 nop No operation/complete. 0 start Start operation. 1 ICACHEXIPZ SPI-XIPF Instruction Cache (ICC1) zeroization. 9 1 nop No operation/complete. 0 start Start operation. 1 SCACHEDATAZ EMCC data zeroization. 10 1 nop No operation/complete. 0 start Start operation. 1 SCACHETAGZ EMCC tag zeroization. 11 1 nop No operation/complete. 0 start Start operation. 1 CRYPTOZ Crypto MAA Memory zeroization. 12 1 nop No operation/complete. 0 start Start operation. 1 USBFIFOZ USB FIFO zeroization. 13 1 nop No operation/complete. 0 start Start operation. 1 SYS_STAT System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 CODEINTERR Flash SPI-XIPF Code Integrity Error Status Flag. 1 1 noerr . 0 err SPI-XIPF code integrity error. 1 SCMEMF HyperBus/Xccela Cache Memory Error Status Flag. 5 1 noerr Normal operation. 0 memfault HyperBus/Xccela cahce memory fault. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 PT Pulse Train Reset. 1 1 SPIXIP SPI-XIPF Reset. 3 1 XSPIM XSPI Master Reset. 4 1 GPIO3 GPIO3 Reset. 5 1 SDHC SDHC Reset. 6 1 OWIRE One-Wire Reset. 7 1 WDT1 WDT1 Reset. 8 1 SPI3 SPI3 Reset. 9 1 I2S I2S (SPIMSS) Reset. 10 1 XIPR SPIXR Reset. 15 1 SEMA Semaphore Block Reset. 16 1 PCLK_DIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Disable. 1 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 TRNG TRNG Disable. 2 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SFLC Secore Flash Controller Clock Disable. 3 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 HBC HyperBus/Xccela Clock Disable. 4 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 GPIO3 GPIO3 Disable. 6 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SCACHE System Cache Clock Disable. 7 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SDMA Smart DMA Clock Disable. 8 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SEMA Semaphore Block Clock Disable. 9 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SDHC SDHC Controller Clock Disable. 10 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 ICACHE Flash Instruction Cache Clock Disable. 11 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 ICACHEXIPF SPI-XIPF Flash Clock Disable. 12 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 OW One-Wire Clock Disable. 13 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SPI3 SPI3 Clock Disable. 14 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 I2S I2S (SPIMSS) Clock Disable. 15 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SPIXIPR SPIXR RAM Clock Disable. 20 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 EVENT_EN Event Enable Register. 0x4C DMAEVENT Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 dis DMA CTZ Event will not wake up the device. 0 en DMA CTZ Event Wake-up Enabled. 1 RXEVENT Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 dis A receive event is not generated when an external input transitions from low to high. 0 en A receive event is generated when external event is triggered. 1 TXEVENT Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. 2 1 dis Transmit event disabled. 0 en A transmit event is enabled on Send Event instruction. 1 REV Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYS_STAT_IE System Status Interrupt Enable Register. 0x54 ICEULIE ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 CIEIE SPI-XIPF Code Intergrity Error Interrupt Enable. 1 1 dis disabled. 0 en enabled. 1 SCMFIE HyperBus/Xccela Cache Memory Fault Interrupt Enable. 5 1 dis disabled. 0 en enabled. 1