GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. 0 1 dis Boundary Scan TAP port disabled. 0 en Boundary Scan TAP port enabled. 1 FLASH0_PAGE_FLIP Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 4 1 normal Physical layout matches logical layout. 0 swapped Bottom half mapped to logical top half and vice versa. 1 ICC0_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 MDU_KEYSZ MDU Key Size. This register defines the size of AES key that is used in the memory protection logic. 21 1 128b 128 bit key 0 256b 256 bit key 1 RST0 Reset. 0x04 DMA DMA Reset. 0 1 WDT0 Watchdog Timer Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TMR0 Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TMR3 Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 UART0 UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 SPI0 SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 I2C0 I2C0 Reset. 16 1 CRYPTO Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block. 18 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 IPO Internal Primary Oscilatior Clock 0 INRO 8kHz Internal Nano Ring Oscillator is used for the system clock. 3 IBRO The internal Baud Rate oscillator is used for the system clock. 5 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 CCD Cryptographic clock divider 15 1 read-only non_div The cryptographic accelerator clock is running in non-divided mode. 0 div The cryptographic accelerator clock is running in divided mode. 1 IPO_EN 96MHz High Frequency Internal Reference Clock Enable. 18 1 IBRO_EN 8MHz High Frequency Internal Reference Clock Enable. 20 1 IBRO_VS 7.3728MHz Internal Oscillator Voltage Source Select 21 1 IPO_RDY Internal Primary Oscillator Ready. 26 1 IBRO_RDY Internal Baud Rate Oscillator Ready. 28 1 INRO_RDY Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. 29 1 PM Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 deepsleep DeepSleep Mode. 2 shutdown Shutdown Mode. 3 backup Backup Mode. 4 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 IPO_PD Internal Primary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. 15 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 IBRO_PD Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. 17 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 PCF These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. 0 3 96MHz 2 48MHz 3 24MHz 4 12MHz 5 6MHz 6 3MHz 7 PCFWEN PCF Write Enable. This bit allows the PCF Register bits to be updated by Software. 3 1 blocked Writes to PCF are blocked. 0 allowed Writes to PCF are allowed 1 AON_CLKDIV Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider. 14 2 div_4 PCLK divide by 4. 0 div_8 PCLK divide by 8. 1 div_16 PCLK divide by 16. 2 div_32 PCLK divide by 32. 3 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Disable. 1 1 DMA DMA Disable. 5 1 SPI0 SPI 0 Disable. 6 1 SPI1 SPI 1 Disable. 7 1 UART0 UART 0 Disable. 9 1 I2C0 I2C 0 Disable. 13 1 CRYPTO Crypto Disable. 14 1 TMR0 Timer 0 Disable. 15 1 TMR1 Timer 1 Disable. 16 1 TMR2 Timer 2 Disable. 17 1 TMR3 Timer 3 Disable. 18 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 RAMWS_EN SRAM Wait State Enable 4 1 RAM0LS_EN System RAM 0 Light Sleep Mode. 16 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 RAM1LS_EN System RAM 1 Light Sleep Mode. 17 1 RAM2LS_EN System RAM 2 Light Sleep Mode. 18 1 RAM3LS_EN System RAM 3 Light Sleep Mode. 19 1 RAM4LS_EN System RAM 4 Light Sleep Mode. 20 1 ICC0LS_EN ICache RAM Light Sleep Mode. 24 1 ROMLS_EN ROM Light Sleep Mode. 29 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM Block 0. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM Block 1. 1 1 RAM2 System RAM Block 2. 2 1 RAM3 System RAM Block 3. 3 1 RAM4 System RAM Block 4. 4 1 ICC0 Instruction Cache. 8 1 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 RST1 Reset 1. 0x44 WDT1 WDT1 Reset. 8 1 SFES Serial Flash Emulation Slave Reset. 28 1 PCLKDIS1 Peripheral Clock Disable. 0x48 TRNG TRNG Disable. 2 1 WDT0 WDT0 Clock Disable 27 1 WDT1 WDT1 Clock Disable 28 1 SFES Serial Flash emulation slave Clock Disable 30 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 RX Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. 2 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 ECCERR ECC Error Register 0x64 RAM0 ECC System RAM0 Error Flag. Write 1 to clear. 0 1 RAM1 ECC System RAM1 Error Flag. Write 1 to clear. 1 1 RAM2 ECC System RAM2 Error Flag. Write 1 to clear. 2 1 RAM3 ECC System RAM3 Error Flag. Write 1 to clear. 3 1 RAM4 ECC System RAM4 Error Flag. Write 1 to clear. 4 1 ECCCED ECC Not Double Error Detect Register 0x68 RAM0 ECC System RAM0 Error Flag. Write 1 to clear. 0 1 RAM1 ECC System RAM1 Not Double Error Detect. Write 1 to clear. 1 1 RAM2 ECC System RAM2 Not Double Error Detect. Write 1 to clear. 2 1 RAM3 ECC System RAM3 Not Double Error Detect. Write 1 to clear. 3 1 RAM4 ECC System RAM4 Not Double Error Detect. Write 1 to clear. 4 1 ECCIE ECC IRQ Enable Register 0x6C RAM0 ECC System RAM0 Interrupt Enable. 0 1 RAM1 ECC System RAM1 Interrupt Enable. 1 1 RAM2 ECC System RAM2 Interrupt Enable. 2 1 RAM3 ECC System RAM3 Interrupt Enable. 3 1 RAM4 ECC System RAM4 Interrupt Enable. 4 1 ECCADDR ECC Error Address Register 0x70 DATARAMADDR ECC Error Address/DATA RAM Error Address 0 14 DATARAMBANK ECC Error Address/DATA RAM Error Bank 14 1 DATARAMERR DATA RAM ERROR 15 1 TAGRAMADDR ECC Error Address/TAG RAM Error Address 16 14 TAGRAMBANK ECC Error Address/TAG RAM Error Bank 30 1 TAGRAMERR TAG RAM ERROR 31 1