GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE. 0 1 FLASH_PAGE_FLIP Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 4 1 normal Physical layout matches logical layout. 0 swapped Bottom half mapped to logical top half and vice versa. 1 ICC0_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 ROMDONE ROM_DONE status. Used to disable SWD interface during system initialization procedure 12 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 SWD_DIS Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set). 14 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 OVR Operating Voltage Range. 16 2 V0_9 0.9V 0 V1_0 1.0V 1 V1_1 1.1V 2 RST0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT0 Watchdog Timer 0 Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TMR0 Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TMR3 Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 UART0 UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI1 SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 13 1 I2C0 I2C 0 Reset. 16 1 RTC Real Time Clock Reset. 17 1 SMPHR Semaphore Reset. 22 1 USB USB Reset. 23 1 TRNG TRNG Reset. This reset is only available during the manufacture testing phase. 24 1 CNN CNN Reset. 25 1 ADC ADC Reset. 26 1 UART2 UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the IPLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 ISO The internal 60 MHz oscillator is used for the system clock. 0 IPLL The internal 120 MHz IPLL is used for the system clock. 1 EBO The external 25 MHz input is used for the system clock. 2 INRO 8 kHz LIRC is used for the system clock. 3 IPO The internal 100 MHz oscillator is used for the system clock. 4 IBRO The internal 7.3725 MHz oscillator is used for the system clock. 5 ERTCO External 32 kHz input is used for the system clock. 6 EXTCLK External clock input is used for the system clock. 7 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 EBO_EN External Base Oscillator 16 1 dis Is Disabled. 0 en Is Enabled. 1 ERTCO_EN 32 kHz Oscillator Enable. 17 1 ISO_EN 60 MHz Internal Oscillator Enable. 18 1 IPO_EN 100 MHz Clock Enable. 19 1 IBRO_EN 7.3725 MHz Clock Enable. 20 1 IBRO_VS 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO. 21 1 Vcor VCore Supply 0 1V Dedicated 1V regulated supply. 1 EBO_RDY External Base Oscillator Ready. 24 1 read-only not Is not Ready. 0 ready Is Ready. 1 ERTCO_RDY 32 kHz Crystal Oscillator Ready. 25 1 ISO_RDY 60 MHz Oscillator Ready. 26 1 IPO_RDY 100 MHz Clock Ready. 27 1 IBRO_RDY 7.3725 MHz HIRC Ready. 28 1 INRO_RDY 8 kHz Low Frequency Reference Clock Ready. 29 1 PM Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 4 active Active Mode. 0 sleep Cortex-M4 Active, RISC-V Sleep Mode. 1 standby Standby Mode. 2 backup Backup Mode. 4 lpm LPM or CM4 Deep Sleep Mode. 8 upm UPM. 9 powerdown Power Down Mode. 10 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTC_WE RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 USB_WE USB Wake Up Enable. This bit enables USB IRQ as wakeup source 6 1 WUT_WE WUT Wake Up Enable. This bit enables the Wake-Up Timer as wakeup source. 7 1 AINCOMP_WE AIN COMP Wake Up Enable. This bit enables AIN COMP as wakeup source. 9 1 ISO_PD 60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode. 15 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 IPO_PD 100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. 16 1 IBRO_PD 7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. 17 1 EBO_BP EBO Bypass 20 1 IPLL_CTRL IPLL Control 0x10 EN 0 1 RDY 1 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 SDIOCLKDIV 7 1 IPO_DIV2 48 MHz 0 IPO_DIV4 24 MHz 1 CNNCLKDIV CNN Clock Divider. 14 3 div2 0 div4 1 div8 2 div16 3 div1 4 CNNCLKSEL CNN Clock Select. 17 2 PCLK 0 ISO 1 IPLL 3 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Clock Disable. 1 1 USB USB Clock Disable. 3 1 DMA DMA Clock Disable. 5 1 SPI1 SPI 1 Clock Disable. 6 1 UART0 UART 0 Clock Disable. 9 1 UART1 UART 1 Clock Disable. 10 1 I2C0 I2C 0 Clock Disable. 13 1 TMR0 Timer 0 Clock Disable. 15 1 TMR1 Timer 1 Clock Disable. 16 1 TMR2 Timer 2 Clock Disable. 17 1 TMR3 Timer 3 Clock Disable. 18 1 ADC ADC Clock Disable. 23 1 CNN CNN Clock Disable. 25 1 I2C1 I2C 1 Clock Disable. 28 1 PT Pluse Train Clock Disable. 29 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 SYSRAM0ECC SYSRAM0 ECC Select. 16 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM Block 0 Zeroization. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM Block 1 Zeroization. 1 1 RAM2 System RAM Block 2 Zeroization. 2 1 RAM3 System RAM Block 3 Zeroization. 3 1 RAM4 System RAM Block 4 Zeroization. 4 1 RAM5 System RAM Block 5 Zeroization. 5 1 RAM6 System RAM Block 6 Zeroization. 6 1 RAM7 System RAM Block 7 Zeroization. 7 1 RAM0ECC System RAM Block 0 ECC Zeroization. 8 1 ICC0 Instruction Cache 0 Zeroization. 9 1 ICC1 Instruction Cache 1 Zeroization. 10 1 USBFIFO USB FIFO Zeroization. 11 1 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset_read read reset_done Reset complete. 0 busy Starts reset or indicates reset in progress. 1 PT PT Reset. 1 1 SDHC SDHC Reset. 6 1 OWM OWM Reset. 7 1 CRC CRC Reset. 9 1 AES AES Reset. 10 1 SPI0 SPI 0 Reset. 11 1 CSI2PHY CSI2 PHY Reset. 14 1 SMPHR SMPHR Reset. 16 1 I2S I2S Reset. 19 1 I2C2 I2C2 Reset. 20 1 DVS DVS Reset. 24 1 SIMO SIMO Reset. 25 1 PCIF PCIF Reset. 26 1 CSI2 CSI2 Reset. 27 1 CPU1 CPU1 Reset. 31 1 PCLKDIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Clock Disable. 1 1 en Enable. 0 dis Disable. 1 TRNG TRNG Clock Disable. 2 1 SMPHR SMPHR Clock Disable. 9 1 SDHC SDHC Clock Disable. 10 1 OWM One-Wire Clock Disable. 13 1 CRC CRC Clock Disable. 14 1 AES AES Clock Disable. 15 1 SPI0 SPI0 AHB. 16 1 PCIF Parallel Camera Interface Clock Disable. 18 1 I2S I2S Clock Disable. 23 1 I2C2 I2C2 Clock Disable. 24 1 WDT0 Watch Dog Timer 0 Clock Disable. 27 1 CSI2 CSI2 Clock Disable. 30 1 CPU1 CPU1 Clock Disable. 31 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9. 2 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 ECCERR ECC Error Register 0x64 RAM ECC System RAM0 Error Flag. Write 1 to clear. 0 1 ECCCED ECC Not Double Error Detect Register 0x68 RAM ECC System RAM0 Error Flag. Write 1 to clear. 0 1 ECCIE ECC IRQ Enable Register 0x6C RAM ECC System RAM0 Error Interrup Enable 0 1 ECCADDR ECC Error Address Register 0x70 ECCERRAD ECC Error Address. 0 32 GPR0 General Purpose Register 0 0x80