SPIXFC SPI XiP Flash Configuration Controller 0x40027000 0 0x1000 registers SPIXFC SPIXFC IRQ 38 CFG Configuration Register. 0x00 SSEL Slaves Select. 0 3 slave0 Slave 0 is selected. 0 MODE Defines SPI Mode, Only valid values are 0 and 3. 4 2 mode0 SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. 0 mode3 SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. 3 PGSZ Page Size. 6 2 4bytes 4 bytes. 0 8bytes 8 bytes. 1 16bytes 16 bytes. 2 32bytes 32 bytes. 3 HICLK SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. 8 4 16CLK 16 system clocks. 0 1CLK 1 system clocks. 1 2CLK 2 system clocks. 2 3CLK 3 system clocks. 3 4CLK 4 system clocks. 4 5CLK 5 system clocks. 5 6CLK 6 system clocks. 6 7CLK 7 system clocks. 7 8CLK 8 system clocks. 8 9CLK 9 system clocks. 9 10CLK 10 system clocks. 10 11CLK 11 system clocks. 11 12CLK 12 system clocks. 12 13CLK 13 system clocks. 13 14CLK 14 system clocks. 14 15CLK 15 system clocks. 15 LOCLK SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. 12 4 16CLK 16 system clocks. 0 1CLK 1 system clocks. 1 2CLK 2 system clocks. 2 3CLK 3 system clocks. 3 4CLK 4 system clocks. 4 5CLK 5 system clocks. 5 6CLK 6 system clocks. 6 7CLK 7 system clocks. 7 8CLK 8 system clocks. 8 9CLK 9 system clocks. 9 10CLK 10 system clocks. 10 11CLK 11 system clocks. 11 12CLK 12 system clocks. 12 13CLK 13 system clocks. 13 14CLK 14 system clocks. 14 15CLK 15 system clocks. 15 SSACT Slaves Select Activate Timing. 16 2 0CLK 0 sytem clocks. 0 2CLK 2 sytem clocks. 1 4CLK 4 sytem clocks. 2 8CLK 8 sytem clocks. 3 INACT Slaves Select Inactive Timing. 18 2 4CLK 4 sytem clocks. 0 6CLK 6 sytem clocks. 1 8CLK 8 sytem clocks. 2 12CLK 12 sytem clocks. 3 IOSMPL Sample Delay 20 4 NODLY No sample clock delay. 0 1CLK 1 system clocks. 1 2CLK 2 system clocks. 2 3CLK 3 system clocks. 3 4CLK 4 system clocks. 4 5CLK 5 system clocks. 5 6CLK 6 system clocks. 6 7CLK 7 system clocks. 7 8CLK 8 system clocks. 8 9CLK 9 system clocks. 9 10CLK 10 system clocks. 10 11CLK 11 system clocks. 11 12CLK 12 system clocks. 12 13CLK 13 system clocks. 13 14CLK 14 system clocks. 14 15CLK 15 system clocks. 15 SS_POL SPIX Controller Slave Select Polarity Register. 0x04 SSPOL_0 Slave Select Polarity. 0 1 activeLo Active Low. 0 activeHi Active High. 1 GEN_CTRL SPIX Controller General Controller Register. 0x08 ENABLE SPI Master enable. 0 1 dis Disable SPI Master, putting a reset state. 0 en Enable SPI Master for processing transactions. 1 TFIFOEN Transaction FIFO Enable. 1 1 dis Disable Transaction FIFO. 0 en Enable Transaction FIFO. 1 RFIFOEN Result FIFO Enable. 2 1 dis Disable Result FIFO. 0 en Enable Result FIFO. 1 BBMODE Bit-Bang Mode. 3 1 dis Disable Bit-Bang Mode. 0 en Enable Bit-Bang Mode. 1 SSDR This bits reflects the state of the currently selected slave select. 4 1 output0 Selected Slave select output = 0. 0 output1 Selected Slave select output = 1. 1 SCKDR SSCLK Drive and State. 6 1 sck0 SCLK is 0. 0 sck1 SCLK is 1. 1 SDATAIN SDIO Input Data Value. 8 4 SDIO0 SDIO[0] 1 SDIO1 SDIO[1] 2 SDIO2 SDIO[2] 4 SDIO3 SDIO[3] 8 BBDAT No description available. 12 4 SDIO0 SDIO[0] 1 SDIO1 SDIO[1] 2 SDIO2 SDIO[2] 4 SDIO3 SDIO[3] 8 BBDATOEN Bit Bang SDIO Output Enable. 16 4 SDIO0 SDIO[0] 1 SDIO1 SDIO[1] 2 SDIO2 SDIO[2] 4 SDIO3 SDIO[3] 8 SIMPLE Simple Mode Enable. 20 1 dis Disable Simple Mode. 0 en Enable Simple Mode. 1 SIMPLERX Simple Receive Enable. 21 1 initSPI Initiate SPI transaction. 1 SMPLSS Simple Mode Slave Select. 22 1 deassertSS Deassert Slave select when SIMPLE = 1. 1 SCKFB Enable SCLK Feedback Mode. 24 1 dis 0 en 1 SCKFBINV SCK Invert. 25 1 normal 0 invert 1 FIFO_CTRL SPIX Controller FIFO Control and Status Register. 0x0C TFIFOLVL Transaction FIFO Almost Empty Level. 0 4 TFIFOCNT Transaction FIFO Used. 8 5 RFIFOLVL Results FIFO Almost Full Level. 16 5 RFIFOCNT Result FIFO Used. 24 6 SP_CTRL SPIX Controller Special Control Register. 0x10 SAMPL Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the next slave select assertion. 0 1 dis Disable sample mode. 0 en Enable sample mode. 1 SDIO_OUT SDIO Output Value Sample Mode 4 4 SDIO0 SDIO[0] 0x1 SDIO1 SDIO[1] 0x2 SDIO2 SDIO[2] 0x4 SDIO3 SDIO[3] 0x8 SDIO_OUT_EN SDIO Output Enable Sample Mode 8 4 SDIO0 SDIO[0] 0x1 SDIO1 SDIO[1] 0x2 SDIO2 SDIO[2] 0x4 SDIO3 SDIO[3] 0x8 SCKINH3 SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. 16 1 en Allow trailing SCLK low pulse prior to Slave Select de-assertion. 0 dis Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. 1 INT_FL SPIX Controller Interrupt Status Register. 0x14 TSTALL Transaction Stalled Interrupt Flag. 0 1 clear Clear interrupt. 1 RSTALL Results Stalled Interrupt Flag. 1 1 clear Clear interrupt. 1 TRDY Transaction Ready Interrupt Status. 2 1 clear Clear interrupt. 1 RDONE Results Done Interrupt Status. 3 1 clear Clear interrupt. 1 TFIFOAE Transaction FIFO Almost Empty Flag. 4 1 clear Clear interrupt. 1 RFIFOAF Results FIFO Almost Full Flag. 5 1 clear Clear interrupt. 1 INT_EN SPIX Controller Interrupt Enable Register. 0x18 TSTALLIE Transaction Stalled Interrupt Enable. 0 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 RSTALLIE Results Stalled Interrupt Enable. 1 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 TRDYIE Transaction Ready Interrupt Enable. 2 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 RDONEIE Results Done Interrupt Enable. 3 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 TFIFOAEIE Transaction FIFO Almost Empty Interrupt Enable. 4 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 RFIFOAFIE Results FIFO Almost Full Interrupt Enable. 5 1 dis Disable Interrupt. 0 en Enable Interrupt. 1