SPIXFC SPI XiP Flash Configuration Controller 0x40027000 0 0x1000 registers SPIXFC SPIXFC IRQ 38 CFG Configuration Register. 0x00 SSEL Slaves Select. 0 3 Slave_0 Slave 0 is selected. 0 Slave_1 Slave 1 is selected. 1 MODE Defines SPI Mode, Only valid values are 0 and 3. 4 2 SPIX_Mode_0 SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. 0 SPIX_Mode_3 SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. 3 PAGE_SIZE Page Size. 6 2 4_bytes 4 bytes. 0 8_bytes 8 bytes. 1 16_bytes 16 bytes. 2 32_bytes 32 bytes. 3 HI_CLK SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. 8 4 16_SCLK 16 system clocks. 0 LO_CLK SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. 12 4 16_SCLK 16 system clocks. 0 SSACT Slaves Select Activate Timing. 16 2 0_CLKS 0 sytem clocks. 0 2_CLKS 2 sytem clocks. 1 4_CLKS 4 sytem clocks. 2 8_CLKS 8 sytem clocks. 3 SSIACT Slaves Select Inactive Timing. 18 2 4_CLKS 4 sytem clocks. 0 6_CLKS 6 sytem clocks. 1 8_CLKS 8 sytem clocks. 2 12_CLKS 12 sytem clocks. 3 IOSMPL Sample Delay 20 4 SS_POL SPIX Controller Slave Select Polarity Register. 0x04 SS_POLARITY Slave Select Polarity. 0 1 lo Active Low. 0 hi Active High. 1 GEN_CTRL SPIX Controller General Controller Register. 0x08 ENABLE SPI Master enable. 0 1 dis Disable SPI Master, putting a reset state. 0 en Enable SPI Master for processing transactions. 1 TX_FIFO_EN Transaction FIFO Enable. 1 1 dis_txfifo Disable Transaction FIFO. 0 en_txfifo Enable Transaction FIFO. 1 RX_FIFO_EN Result FIFO Enable. 2 1 DIS_RXFIFO Disable Result FIFO. 0 EN_RXFIFO Enable Result FIFO. 1 BBMODE Bit-Bang Mode. 3 1 dis Disable Bit-Bang Mode. 0 en Enable Bit-Bang Mode. 1 SSDR This bits reflects the state of the currently selected slave select. 4 1 output0 Selected Slave select output = 0. 0 output1 Selected Slave select output = 1. 1 SCLK_DR SSCLK Drive and State. 6 1 SCLK_0 SCLK is 0. 0 SCLK_1 SCLK is 1. 1 SDIO_DATA_IN SDIO Input Data Value. 8 4 SDIO0 SDIO[0] 0 SDIO1 SDIO[1] 1 SDIO2 SDIO[2] 2 SDIO3 SDIO[3] 3 BB_DATA No description available. 12 4 SDIO0 SDIO[0] 0 SDIO1 SDIO[1] 1 SDIO2 SDIO[2] 2 SDIO3 SDIO[3] 3 BB_DATA_OUT_EN Bit Bang SDIO Output Enable. 16 4 SDIO0 SDIO[0] 0 SDIO1 SDIO[1] 1 SDIO2 SDIO[2] 2 SDIO3 SDIO[3] 3 SIMPLE Simple Mode Enable. 20 1 SIMPLE_RX Simple Receive Enable. 21 1 SIMPLE_SS Simple Mode Slave Select. 22 1 SCLK_FB Enable SCLK Feedback Mode. 24 1 Dis 0 En 1 SCLK_FB_INVERT SCK Invert. 25 1 FIFO_CTRL SPIX Controller FIFO Control and Status Register. 0x0C TX_FIFO_AE_LVL Transaction FIFO Almost Empty Level. 0 4 TX_FIFO_CNT Transaction FIFO Used. 8 5 RX_FIFO_AF_LVL Results FIFO Almost Full Level. 16 5 RX_FIFO_CNT Result FIFO Used. 24 6 SP_CTRL SPIX Controller Special Control Register. 0x10 SAMPL Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the next slave select assertion. 0 1 SDIO_OUT SDIO Output Value Sample Mode 4 4 SDIO_OUT_EN SDIO Output Enable Sample Mode 8 4 SCLKINH3 SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. 16 1 EN Allow trailing SCLK low pulse prior to Slave Select de-assertion. 0 DIS Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. 1 INT_FL SPIX Controller Interrupt Status Register. 0x14 TX_STALLED Transaction Stalled Interrupt Flag. 0 1 CLR Normal FIFO Transaction. 0 SET Stalled FIFO Transaction. 1 RX_STALLED Results Stalled Interrupt Flag. 1 1 CLR Normal FIFO Operation. 0 SET Stalled FIFO. 1 TX_READY Transaction Ready Interrupt Status. 2 1 CLR FIFO Transaction not ready. 0 SET FIFO Transaction ready. 1 RX_DONE Results Done Interrupt Status. 3 1 CLR Results FIFO ready. 0 SET Results FIFO Not ready. 1 TX_FIFO_AE Transaction FIFO Almost Empty Flag. 4 1 CLR Transaction FIFO not Almost Empty. 0 SET Transaction FIFO Almost Empty. 1 RX_FIFO_AF Results FIFO Almost Full Flag. 5 1 CLR Results FIFO level below the Almost Full level. 0 SET Results FIFO level at Almost Full level. 1 INT_EN SPIX Controller Interrupt Enable Register. 0x18 TX_STALLED Transaction Stalled Interrupt Enable. 0 1 EN Disable Transaction Stalled Interrupt. 0 DIS Enable Transaction Stalled Interrupt. 1 RX_STALLED Results Stalled Interrupt Enable. 1 1 EN Disable Results Stalled Interrupt. 0 DIS Enable Results Stalled Interrupt. 1 TX_READY Transaction Ready Interrupt Enable. 2 1 EN Disable FIFO Transaction Ready Interrupt. 0 DIS Enable FIFO Transaction Ready Interrupt. 1 RX_DONE Results Done Interrupt Enable. 3 1 EN Disable Results Done Interrupt. 0 DIS Enable Results Done Interrupt. 1 TX_FIFO_AE Transaction FIFO Almost Empty Interrupt Enable. 4 1 EN Disable Transaction FIFO Almost Empty Interrupt. 0 DIS Enable Transaction FIFO Almost Empty Interrupt. 1 RX_FIFO_AF Results FIFO Almost Full Interrupt Enable. 5 1 EN Disable Results FIFO Almost Full Interrupt. 0 DIS Enable Results FIFO Almost Full Interrupt. 1