SPIMSS Serial Peripheral Interface. SPIMSS 0x40019000 0x00 0x1000 registers DATA SPI 16-bit Data Access 0x00 16 read-write DATA SPI data. 0 16 CTRL SPI Control Register. 0x04 ENABLE SPI Enable. 0 1 dis_en_enum disable 0 enable 1 MMEN SPI Master Mode Enable. 1 1 slv_mst_enum slave 0 master 1 WOR Wired OR (open drain) Enable. 2 1 dis_en_enum disable 0 enable 1 CLKPOL Clock Polarity. 3 1 spi_pol_enum idleLo SCLK idles Low (0) after character transmission/reception. 0 idleHi SCLK idles High (1) after character transmission/reception. 1 PHASE Phase Select. 4 1 spi_phase_enum activeEdge Transmit on active edge of SCLK. 0 inactiveEdge Transmit on inactive edge of SCLK. 1 BIRQ Baud Rate Generator Timer Interrupt Request. 5 1 dis_en_enum disable 0 enable 1 STR Start SPI Interrupt. 6 1 start_op_enum complete No operation/complete. 0 start Start operation. 1 IRQE Interrupt Request Enable. 7 1 dis_en_enum disable 0 enable 1 INT_FL SPI Interrupt Flag Register. 0x08 0x00000001 SLAS Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning. 0 1 read-only sel_enum selected 0 notSelected 1 TXST Transmit Status. 1 1 read-only busy_enum idle 0 busy 1 TUND Transmit Underrun. 2 1 oneToClear event_flag_enum noEvent The event has not occurred. 0 occurred The event has occurred. 1 ROVR Receive Overrun. 3 1 event_flag_enum noEvent The event has not occurred. 0 occurred The event has occurred. 1 ABT Slave Mode Transaction Abort. 4 1 event_flag_enum noEvent The event has not occurred. 0 occurred The event has occurred. 1 COL Collision. 5 1 event_flag_enum noEvent The event has not occurred. 0 occurred The event has occurred. 1 TOVR Transmit Overrun. 6 1 event_flag_enum noEvent The event has not occurred. 0 occurred The event has occurred. 1 IRQ SPI Interrupt Request. 7 1 oneToClear flag_enum inactive No interrupt is pending. 0 pending An interrupt is pending. 1 MODE SPI Mode Register. 0x0C SSV Slave Select Value. 0 1 lo_hi_enum lo The SSEL pin will be driven low. 0 hi The SSEL pin will be driven high. 1 SS_IO Slave Select I/O. 1 1 input_output_enum input 0 output 1 NUMBITS 2 4 spi_bits_enum bits16 0 bits1 1 bits2 2 bits3 3 bits4 4 bits5 5 bits6 6 bits7 7 bits8 8 bits9 9 bits10 10 bits11 11 bits12 12 bits13 13 bits14 14 bits15 15 TX_LJ Transmit Left Justify. 7 1 dis_en_enum disable 0 enable 1 BRG Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4). 0x14 0x0000FFFF DIV Baud Rate Reload Value. 0 16 DMA SPI DMA Register. 0x18 0x00070007 TX_FIFO_LVL Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs. 0 3 fifo_level_enum entry1 0 entries2 1 entries3 2 entries4 3 entries5 4 entries6 5 entries7 6 entries8 7 TX_FIFO_CLR Transmit FIFO Clear. 4 1 write-only start_op_enum complete No operation/complete. 0 start Start operation. 1 TX_FIFO_CNT Transmit FIFO Count. 8 4 read-only TX_DMA_EN Transmit DMA Enable. 15 1 dis_en_enum disable 0 enable 1 RX_FIFO_LVL Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request. 16 3 fifo_level_enum entry1 0 entries2 1 entries3 2 entries4 3 entries5 4 entries6 5 entries7 6 entries8 7 RX_FIFO_CLR Receive FIFO Clear. 20 1 start_op_enum complete No operation/complete. 0 start Start operation. 1 RX_FIFO_CNT Receive FIFO Count. 24 4 read-only RX_DMA_EN Receive DMA Enable. 31 1 dis_en_enum disable 0 enable 1 I2S_CTRL I2S Control Register. 0x1C I2S_EN I2S Mode Enable. 0 1 dis_en_enum disable 0 enable 1 I2S_MUTE I2S Mute transmit. 1 1 normal Normal Transmit. 0 replaced Transmit data is replaced with 0. 1 I2S_PAUSE I2S Pause transmit/receive. 2 1 normal Normal Transmit. 0 halt Halt transmit and receive FIFO and DMA access, transmit 0's. 1 I2S_MONO I2S Monophonic Audio Mode. 3 1 stereophonic Stereophonic audio. 0 monophonic Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored. 1 I2S_LJ I2S Left Justify. 4 1 normal Normal I2S audio protocol. 0 replaced Audio data is synchronized with SSEL. 1