SMON The Security Monitor block used to monitor system threat conditions. 0x40004000 0x00 0x400 registers EXTSCN External Sensor Control Register. 0x00 0x3800FFC0 EXTS_EN0 External Sensor Enable for input/output pair 0. 0 1 dis Disable. 0 en Enable. 1 EXTS_EN1 External Sensor Enable for input/output pair 1. 1 1 dis Disable. 0 en Enable. 1 EXTS_EN2 External Sensor Enable for input/output pair 2. 2 1 dis Disable. 0 en Enable. 1 EXTS_EN3 External Sensor Enable for input/output pair 3. 3 1 dis Disable. 0 en Enable. 1 EXTS_EN4 External Sensor Enable for input/output pair 4. 4 1 dis Disable. 0 en Enable. 1 EXTS_EN5 External Sensor Enable for input/output pair 5. 5 1 dis Disable. 0 en Enable. 1 EXTCNT External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered. 16 5 EXTFRQ External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair. 21 3 freq2000Hz Div 4 (2000Hz). 0 freq1000Hz Div 8 (1000Hz). 1 freq500Hz Div 16 (500Hz). 2 freq250Hz Div 32 (250Hz). 3 freq125Hz Div 64 (125Hz). 4 freq63Hz Div 128 (63Hz). 5 freq31Hz Div 256 (31Hz). 6 RFU Reserved. Do not use. 7 DIVCLK Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor. 24 3 div1 Divide by 1 (8000 Hz). 0 div2 Divide by 2 (4000 Hz). 1 div4 Divide by 4 (2000 Hz). 2 div8 Divide by 8 (1000 Hz). 3 div16 Divide by 16 (500 Hz). 4 div32 Divide by 32 (250 Hz). 5 div64 Divide by 64 (125 Hz). 6 BUSY Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain. 30 1 read-only idle Idle. 0 busy Update in Progress. 1 LOCK Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. 31 1 unlocked Unlocked. 0 locked Locked. 1 INTSCN Internal Sensor Control Register. 0x04 0x7F00FFF7 SHIELD_EN Die Shield Enable. 0 1 dis Disable. 0 en Enable. 1 TEMP_EN Temperature Sensor Enable. 1 1 dis Disable. 0 en Enable. 1 VBAT_EN Battery Monitor Enable. 2 1 dis Disable. 0 en Enable. 1 DFD_EN Digital Fault Dector Enable 3 1 DFD_NMI Digital Fault NMI Enable 4 1 DFD_STDBY Digital Fault Dector Stand by Enable 8 1 PUF_TRIM_ERASE Erase puf trim Enable 10 1 LOTEMP_SEL Low Temperature Detection Select. 16 1 neg50C -50 degrees C. 0 neg30C -30 degrees C. 1 VCORELOEN VCORE Undervoltage Detect Enable. 18 1 dis Disable. 0 en Enable. 1 VCOREHIEN VCORE Overvoltage Detect Enable. 19 1 dis Disable. 0 en Enable. 1 VDDLOEN VDD Undervoltage Detect Enable. 20 1 dis Disable. 0 en Enable. 1 VDDHIEN VDD Overvoltage Detect Enable. 21 1 dis Disable. 0 en Enable. 1 VGLEN Voltage Glitch Detection Enable. 22 1 dis Disable. 0 en Enable. 1 LOCK Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. 31 1 unlocked Unlocked. 0 locked Locked. 1 SECALM Security Alarm Register. 0x08 0x00000000 0x00000000 DRS Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware. 0 1 complete No operation/complete. 0 start Start operation. 1 KEYWIPE Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped. 1 1 complete No operation/complete. 0 start Start operation. 1 SHIELDF Die Shield Flag. 2 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 LOTEMP Low Temperature Detect. 3 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 HITEMP High Temperature Detect. 4 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATLO Battery Undervoltage Detect. 5 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATHI Battery Overvoltage Detect. 6 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTF External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. 7 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VDDLO VDD Undervoltage Detect Flag. 8 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VCORELO VCORE Undervoltage Detect Flag. 9 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VCOREHI VCORE Overvoltage Detect Flag. 10 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VDDHI VDD Overvoltage Flag. 11 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VGL Voltage Glitch Detection Flag. 12 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT0 External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 16 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT1 External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 17 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT2 External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 18 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT3 External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 19 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT4 External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 20 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT5 External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 21 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN0 External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 24 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN1 External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 25 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN2 External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 26 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN3 External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 27 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN4 External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 28 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN5 External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 29 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 SECDIAG Security Diagnostic Register. 0x0C read-only 0x00000001 0xFFC0FE02 BORF Battery-On-Reset Flag. This bit is set once the back up battery is conneted. 0 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 SHIELDF Die Shield Flag. 2 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 LOTEMP Low Temperature Detect. 3 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 HITEMP High Temperature Detect. 4 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATLO Battery Undervoltage Detect. 5 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATHI Battery Overvoltage Detect. 6 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 DYNF Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. 7 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 AESKT AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR. 8 1 incomplete Key has not been transferred. 0 complete Key has been transferred. 1 EXTSTAT0 External Sensor 0 Detect. 16 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT1 External Sensor 1 Detect. 17 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT2 External Sensor 2 Detect. 18 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT3 External Sensor 3 Detect. 19 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT4 External Sensor 4 Detect. 20 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT5 External Sensor 5 Detect. 21 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 DLRTC DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred. 0x10 read-only 0x00000000 DLRTC DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured. 0 32 MEUCFG MEU Configuration 0x24 0x00000000 MEUCFG Configuration plain/encrypted area of the backed NVSRAM. 0 7 SECST Security Monitor Status Register. 0x34 read-only EXTSRS External Sensor Control Register Status. 0 1 allowed Access authorized. 0 notAllowed Access not authorized. 1 INTSRS Internal Sensor Control Register Status. 1 1 allowed Access authorized. 0 notAllowed Access not authorized. 1 SECALRS Security Alarm Register Status. 2 1 allowed Access authorized. 0 notAllowed Access not authorized. 1 SDBE Security Monitor Self Destruct Byte. 0x38 DBYTE Self Destruct Byte 0 8 SBDEN Self-Destruct Byte ENable. 31 1