PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers LPCN Low Power Control Register. 0x00 RAM0RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 1 dis Disable Ram Retention. 0 en Enable System RAM 0 retention. 1 RAM1RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 1 1 dis Disable Ram Retention. 0 en Enable System RAM 1 retention. 1 RAM2RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 2 1 dis Disable Ram Retention. 0 en Enable System RAM 2 retention. 1 RAM3RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 3 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 OVR Operating Voltage Range 4 2 0_9V 0.9V 24MHz 0 1_0V 1.0V 48MHz 1 1_1V 1.1V 96MHz 2 VCORE_DET_BYPASS Block Auto-Detect 6 1 enabled enable 0 Disable disable 1 RETREG_EN Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. 8 1 dis Disabled. 0 en Enabled. 1 STORAGE_EN STORAGE Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep. 9 1 dis Disabled. 0 en Enabled. 1 FASTWK_EN Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). 10 1 dis Disabled. 0 en Enabled. 1 BG_DIS Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode (default). 1 VCOREPOR_DIS VDDC (Vcore) Power on reset Monitor Disable.This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. 12 1 en Enable 0 dis Disabled. 1 LDO_DIS Disable Main LDO 16 1 en Enable 0 dis Disabled. 1 VCORE_EXT Use external VCORE for 1V supply 17 1 dis disable 0 en use Vcore for retention. 1 VCOREMON_DIS VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. 20 1 en Enable 0 dis Disabled. 1 VDDAMON_DIS VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 22 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 PORVDDMON_DIS VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. 25 1 dis Disabled. 0 en Enabled. 1 INRO_EN INRO remains on in all power modes if this bit is set otherwise it is controled by the LP controller 28 1 ERTCO_EN XRTCO remains on in all power modes if this bit is set otherwise it is controled by the LP controller 29 1 ERTCO_PD Powerdown ERTCO. 31 1 LPWKST0 Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 ST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 1 LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 EN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPWKST1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 LPPWKST Low Power Peripheral Wakeup Status Register. 0x30 LPTMR0 LPTM0 Wakeup Flag. 0 1 LPTMR1 LPTMR1 Wakeup Flag. 1 1 LPUART0 LPUART0 Wakeup Flag. 2 1 LPPWKEN Low Power Peripheral Wakeup Enable Register. 0x34 LPTMR0 TIMER4 Wakeup Enable. This bit allows wakeup from the TIMER4. 0 1 LPTMR1 TIMER5 Wakeup Enable. This bit allows wakeup from the TIMER5. 1 1 LPUART0 LPUART Wakeup Enable. This bit allows wakeup from the LPUART. 2 1 LPMEMSD Low Power Memory Shutdown Control. 0x40 RAM0 System RAM block 0 Shut Down. 0 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM1 System RAM block 1 Shut Down. 1 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM2 System RAM block 2 Shut Down. 2 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM3 System RAM block 3 Shut Down. 3 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 GP0 General Purpose Register 0 0x48 GP1 General Purpose Register 1 0x4C