PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers LPCN Low Power Control Register. 0x00 RAMRET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 2 OVR Operating Voltage Range 4 2 0_9V 0.9V 24MHz 0 1_0V 1.0V 48MHz 1 1_1V 1.1V 96MHz 2 RETREG_EN Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. 8 1 dis Disabled. 0 en Enabled. 1 FASTWK_EN Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). 10 1 dis Disabled. 0 en Enabled. 1 BG_DIS Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode (default). 1 VCOREPOR_DIS VCore Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. 12 1 dis Disabled. 0 en Enabled. 1 LDO_DIS Disable Main LDO 16 1 VCOREMON_DIS Vcore Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. 20 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VRTCMON_DIS VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. 21 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VDDAMON_DIS VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 22 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VDDIOMON_DIS VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 23 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VDDIOHMON_DIS VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 24 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 PORVDDBMON_DIS VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. 27 1 dis Disabled. 0 en Enabled. 1 LPWKST0 Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 ST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 1 LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 EN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPWKST1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 LPWKST2 Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. 0x14 LPWKEN2 Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. 0x18 LPWKST3 Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. 0x1C LPWKEN3 Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. 0x20 LPPWKST Low Power Peripheral Wakeup Status Register. 0x30 USBLS USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. 0 2 USBVBUS USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. 2 1 HA0 Hardware Accelerator 0 Detect Wakeup Status Flag 3 1 BBMOD Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode. 16 1 RST Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup 17 1 SDMA1 Smart DMA (1) Detect Wakeup Flag (write one to clear). This bit will be set when the SDMA IRQ transitions from low to high or high to low 18 1 LPPWKEN Low Power Peripheral Wakeup Enable Register. 0x34 USBLS USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set. 0 2 USBVBUS USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. 2 1 SDMA0 Smart DMA Wakeup Enable. This bit allows wakeup from the Smart DMA IRQ. 3 1 SDMA1 Smart DMA Wakeup Enable. This bit allows wakeup from the Smart DMA IRQ. 18 1 LPMEMSD Low Power Memory Shutdown Control. 0x40 RAM0 System RAM block 0 Shut Down. 0 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM1 System RAM block 1 Shut Down. 1 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM2 System RAM block 2 Shut Down. 2 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM3 System RAM block 3 Shut Down. 3 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM4 System RAM block 4 Shut Down. 4 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM5 System RAM block 5 Shut Down. 5 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICACHE Instruction Cache RAM Shut Down. 7 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICACHEXIP XiP Instruction Cache RAM Shut Down. 8 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRCC System Cache RAM Shut Down. 9 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 USBFIFO USB FIFO Shut Down. 11 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ROM ROM Shut Down. 12 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 LPVDDPD Low Power VDD Domain Power Down Control. 0x44 GP0 General Purpose Register 0 0x48 GP1 General Purpose Register 1 0x4C