PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers CTRL Low Power Control Register. 0x00 RAMRET System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 2 dis Disable Ram Retention. 0 en1 Enable System RAM 0 retention. 1 en2 Enable System RAM 0 and 1 retention. 2 en3 Enable System RAM 0 and 1 retention, if RREGEN=0, Enable all System RAM retention. 3 RREGEN Backup Mode RAM Retention Regulator Enable 8 1 dis Disabled. 0 en Enabled. 1 BKGRND Background Mode Enable. This bit allows low-power background mode operations, while the CPU is in DeepSleep. 9 1 dis Disabled. 0 en Enabled. 1 FWKM Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). 10 1 dis Disabled. 0 en Enabled. 1 BGOFF Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode(default). 1 PORVCOREMD VCORE POR Monitor for DEEPSLEEP and BACKUP Disable Write 1 to disable the power failure monitor. With the power failure monitor enabled, if the voltage drops below the trigger voltage the device enters a Power-On Reset. 12 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VCOREMD VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. 20 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VRTCMD VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. 21 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDAMD VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 22 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDIOMD VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 23 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDIOHMD VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 24 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 PORVDDIOMD VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 25 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 PORVDDIOHMD VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 26 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDBMD VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. 27 1 en Enabled. 0 dis Disabled. 1 GPIO0_WK_FL Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 32 GPIO0_WK_EN Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 32 GPIO1_WK_FL Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 32 GPIO1_WK_EN Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 32 GPIO2_WK_FL Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO2. 0x14 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 32 GPIO2_WK_EN Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x18 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 32 GPIO3_WK_FL Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO3. 0x1C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 10 GPIO3_WK_EN Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO3. 0x20 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 10 USB_WK_FL Low Power Peripheral Wakeup Status Register. 0x30 USBLSWKST USB UTMI Linestate Detect Wakeup Flag(write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. 0 2 dplus D Plus line state change. 0 dminus D Minus line state change. 1 USBVBUSWKST USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. 2 1 normal Normal operation. 0 stchng Disabled. 1 USB_WK_EN Low Power Peripheral Wakeup Enable Register. 0x34 USBLSWKEN USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set. 0 2 dis Disable. 0 en Enabled. 3 USBVBUSWKEN USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. 2 1 dis Disable. 0 en Enabled. 1 MEM_PWR Low Power Memory Shutdown Control. 0x40 SRAM0SD System RAM block 0 Shut Down. 0 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM1SD System RAM block 1 Shut Down. 1 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM2SD System RAM block 2 Shut Down. 2 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM3SD System RAM block 3 Shut Down. 3 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM4SD System RAM block 4 Shut Down. 4 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM5SD System RAM block 5 Shut Down. 5 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM6SD System RAM block 6 Shut Down. 6 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICACHESD Instruction Cache RAM Shut Down. 7 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICACHEXIPSD XiP Instruction Cache RAM Shut Down. 8 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SCACHESD System Cache RAM Shut Down. 9 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 CRYPTOSD Crypto MAA RAM Shut Down. 10 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 USBFIFOSD USB FIFO Shut Down. 11 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ROMSD ROM Shut Down. 12 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1