I2C0 Inter-Integrated Circuit. I2C 0x4001D000 32 0x00 0x1000 registers I2C0 I2C0 IRQ 13 CTRL0 Control Register0. 0x00 I2CEN I2C Enable. [0:0] read-write dis Disable I2C. 0 en enable I2C. 1 MST Master Mode Enable. [1:1] read-write slave_mode Slave Mode. 0 master_mode Master Mode. 1 GCEN General Call Address Enable. [2:2] read-write dis Ignore Gneral Call Address. 0 en Acknowledge general call address. 1 IRXM Interactive Receive Mode. [3:3] read-write dis Disable Interactive Receive Mode. 0 en Enable Interactive Receive Mode. 1 ACK Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. [4:4] read-write ack return ACK (pulling SDA LOW). 0 nack return NACK (leaving SDA HIGH). 1 SCLO SCL Output. This bits control SCL output when SWOE =1. [6:6] read-write drive_scl_low Drive SCL low. 0 release_scl Release SCL. 1 SDAO SDA Output. This bits control SDA output when SWOE = 1. [7:7] read-write drive_sda_low Drive SDA low. 0 release_sda Release SDA. 1 SCL SCL status. This bit reflects the logic gate of SCL signal. [8:8] read-only SDA SDA status. THis bit reflects the logic gate of SDA signal. [9:9] read-only SWOE Software Output Enable. [10:10] read-write outputs_disable I2C Outputs SCLO and SDAO disabled. 0 outputs_enable I2C Outputs SCLO and SDAO enabled. 1 READ Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. [11:11] read-only write Write. 0 read Read. 1 SCL_STRD This bit will disable slave clock stretching when set. [12:12] read-write en Slave clock stretching enabled. 0 dis Slave clock stretching disabled. 1 SCL_PPM SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. [13:13] read-write dis Standard open-drain operation: drive low for 0, Hi-Z for 1 0 en Non-standard push-pull operation: drive low for 0, drive high for 1 1 HSMODE Hs-mode Enable. 15 1 dis Hs-mode disabled. 0 en Hs-mode enabled. 1 STATUS Status Register. 0x04 BUSY Bus Status. [0:0] read-only idle I2C Bus Idle. 0 busy I2C Bus Busy. 1 RXE RX empty. [1:1] read-only not_empty Not Empty. 0 empty Empty. 1 RXF RX Full. [2:2] read-only not_full Not Full. 0 full Full. 1 TXE TX Empty. [3:3] not_empty Not Empty. 0 empty Empty. 1 TXF TX Full. [4:4] not_empty Not Empty. 0 empty Empty. 1 CKMD Clock Mode. [5:5] read-only not_actively_driving_scl_clock Device not actively driving SCL clock cycles. 0 actively_driving_scl_clock Device operating as master and actively driving SCL clock cycles. 1 STAT Controller Status. [11:8] idle Controller Idle. 0 mtx_addr master Transmit address. 1 mrx_addr_ack Master Receive address ACK. 2 mtx_ex_addr Master Transmit extended address. 3 mrx_ex_addr Master Receive extended address ACK. 4 srx_addr Slave Receive address. 5 stx_addr_ack Slave Transmit address ACK. 6 srx_ex_addr Slave Receive extended address. 7 stx_ex_addr_ack Slave Transmit extended address ACK. 8 tx Transmit data (master or slave). 9 rx_ack Receive data ACK (master or slave). 10 rx Receive data (master or slave). 11 tx_ack Transmit data ACK (master or slave). 12 nack NACK stage (master or slave). 13 by_st Bystander state (ongoing transaction but not participant- another master addressing another slave). 15 INTFL0 Interrupt Status Register. 0x08 DONEI Transfer Done Interrupt. [0:0] INT_FL0_Done inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 IRXMI Interactive Receive Interrupt. [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 GCI Slave General Call Address Match Interrupt. [2:2] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 AMI Slave Address Match Interrupt. [3:3] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 RXTHI Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. [4:4] inactive No interrupt is pending. 0 pending An interrupt is pending. RX_FIFO equal or more bytes than the threshold. 1 TXTHI Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. [5:5] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 STOPI STOP Interrupt. [6:6] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 ADRACKI Address Acknowledge Interrupt. [7:7] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ARBERI Arbritation error Interrupt. [8:8] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TOERI timeout Error Interrupt. [9:9] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADRERI Address NACK Error Interrupt. [10:10] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DATERI Data NACK Error Interrupt. [11:11] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DNRERI Do Not Respond Error Interrupt. [12:12] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 STRTERI Start Error Interrupt. [13:13] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 STOPERI Stop Error Interrupt. [14:14] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TXLOI Transmit Lock Out Interrupt. [15:15] MAMI Multiple Slave Address Match Interrupt. [19:16] INTEN0 Interrupt Enable Register. 0x0C read-write DONEIE Transfer Done Interrupt Enable. [0:0] read-write dis Interrupt disabled. 0 en Interrupt enabled when DONE = 1. 1 IRXMIE Description not available. [1:1] read-write dis Interrupt disabled. 0 en Interrupt enabled when RX_MODE = 1. 1 GCIE Slave mode general call address match received input enable. [2:2] read-write dis Interrupt disabled. 0 en Interrupt enabled when GEN_CTRL_ADDR = 1. 1 AMIE Slave mode incoming address match interrupt. [3:3] read-write dis Interrupt disabled. 0 en Interrupt enabled when ADDR_MATCH = 1. 1 RXTHIE RX FIFO Above Treshold Level Interrupt Enable. [4:4] read-write dis Interrupt disabled. 0 en Interrupt enabled. 1 TXTHIE TX FIFO Below Treshold Level Interrupt Enable. [5:5] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOPIE Stop Interrupt Enable [6:6] read-write dis Interrupt disabled. 0 en Interrupt enabled when STOP = 1. 1 ADRACKIE Received Address ACK from Slave Interrupt. [7:7] dis Interrupt disabled. 0 en Interrupt enabled. 1 ARBERIE Master Mode Arbitration Lost Interrupt. [8:8] dis Interrupt disabled. 0 en Interrupt enabled. 1 TOERIE Timeout Error Interrupt Enable. [9:9] dis Interrupt disabled. 0 en Interrupt enabled. 1 ADRERIE Master Mode Address NACK Received Interrupt. [10:10] dis Interrupt disabled. 0 en Interrupt enabled. 1 DATERIE Master Mode Data NACK Received Interrupt. [11:11] dis Interrupt disabled. 0 en Interrupt enabled. 1 DNRERIE Slave Mode Do Not Respond Interrupt. [12:12] dis Interrupt disabled. 0 en Interrupt enabled. 1 STRTERIE Out of Sequence START condition detected interrupt. [13:13] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOPERIE Out of Sequence STOP condition detected interrupt. [14:14] dis Interrupt disabled. 0 en Interrupt enabled. 1 TXLOIE TX FIFO Locked Out Interrupt. [15:15] dis Interrupt disabled. 0 en Interrupt enabled when TXLOIE = 1. 1 MAMIE Multiple Slave Address Match Interrupt Enable. [19:16] INTFL1 Interrupt Status Register 1. 0x10 RXOFI Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. [0:0] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TXUFI Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 INTEN1 Interrupt Staus Register 1. 0x14 read-write RXOFIE Receiver Overflow Interrupt Enable. [0:0] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 TXUFIE Transmit Underflow Interrupt Enable. [1:1] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 FIFOLEN FIFO Configuration Register. 0x18 RXLEN Receive FIFO Length. [7:0] read-only TXLEN Transmit FIFO Length. [15:8] read-only RXCTRL0 Receive Control Register 0. 0x1C DNR Do Not Respond. [0:0] respond Always respond to address match. 0 not_respond_rx_fifo_empty Do not respond to address match when RX_FIFO is not empty. 1 RXFSH Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. [7:7] not_flushed FIFO not flushed. 0 flush Flush RX_FIFO. 1 RXTH Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. [11:8] RXCTRL1 Receive Control Register 1. 0x20 RXCNT Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. [7:0] RXFIFO Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. [11:8] read-only TXCTRL0 Transmit Control Register 0. 0x24 TXPRELD Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. [0:0] TX_READY_MODE Transmit FIFO Ready Manual Mode. [1:1] en HW control of I2CTXRDY enabled. 0 dis HW control of I2CTXRDY disabled. 1 TXFSH Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. [7:7] not_flushed FIFO not flushed. 0 flush Flush TX_FIFO. 1 TXTH Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. [11:8] TXCTRL1 Transmit Control Register 1. 0x28 TXRDY Transmit FIFO Preload Ready. [0:0] TXLAST Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware). [1:1] hold_scl_low Hold SCL low on TX_FIFO empty. 0 end_transaction End transaction on TX_FIFO empty. 1 FLSH_GCADDR_DIS TX FIFO Auto Flush Disable on General Call Address Match.Setting this field to 1 disables the TX FIFO Automatic Flush when a General Call Address Match occurs. [2:2] autoflush_en The TX FIFO is automatically flushed on a General Call Address Match. 0 autoflush_dis The TX FIFO is not flushed on a General Call Address Match. 1 FLSH_SLADDR_DIS TX FIFO Auto Flush Disable for Slave Address Match. Setting this field to 1 disables the TX FIFO Automatic Flush when a Slave Address Match occurs. [4:4] autoflush_en The TX FIFO is automatically flushed on a Slave Address Match. 0 autoflush_dis The TX FIFO is not flushed on a Slave Address Match. 1 FLSH_NACK_DIS TX FIFO Auto Flush Disable for NACK. Setting this field to 1 disables the TX FIFO Automatic Flush when a NACK is received at the end of a slave transaction. [5:5] autoflush_en The TX FIFO is automatically flushed if a NACK is received at the end of a slave transaction. 0 autoflush_dis The TX FIFO is not flushed when a NACK is received at the end of a slave transaction. 1 TXFIFO Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. [11:8] read-only FIFO Data Register. 0x2C DATA Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. 0 8 MSTR_MODE Master Control Register. 0x30 START Setting this bit to 1 will start a master transfer. [0:0] RESTART Setting this bit to 1 will generate a repeated START. [1:1] STOP Setting this bit to 1 will generate a STOP condition. [2:2] SEA Slave Extend Address Select. [7:7] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 CLKLO Clock Low Register. 0x34 SCL_LO Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. [8:0] CLKHI Clock high Register. 0x38 SCL_HI Clock High. In master mode, these bits define the SCL high period. [8:0] HS_CLK HS-Mode Clock Control Register 0x3C HS_CLK_LO Slave Address. [7:0] HS_CLK_HI Slave Address. [15:8] TIMEOUT Timeout Register 0x40 TO Timeout [15:0] SLADDR Slave Address Register. 0x44 SLA Slave Address. [9:0] SLADIS Slave Address Disable. [10:10] SLAIDX Slave Address Index. [14:11] EA Extended Address Select. [15:15] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 DMA DMA Register. 0x48 TXEN TX channel enable. [0:0] dis Disable. 0 en Enable. 1 RXEN RX channel enable. [1:1] dis Disable. 0 en Enable. 1