HTMR High Speed Timer Module. 0x4001B000 0x00 0xFFF registers HTimer HTimer interrupt. 93 SEC HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter. 0x00 0x00000000 RTS HTimer Long Interval Counter. 0 31 SSEC HTimer Short Interval Counter. This counter ticks ever t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 RTSS HTimer Short Interval Counter. 0 8 RAS Long Interval Alarm. 0x08 0x00000000 RAS HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0] 0 20 RSSA HTimer Short Interval Alarm. This register contains the reload value for the short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover. 0x0C 0x00000000 RSSA This register contains the reload value for the short interval alarm. 0 32 CTRL HTimer Control Register. 0x10 0x00000008 0xFFFFFF38 HTEN HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 ADE Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 ASE Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 RDY HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register. 4 1 busy Register has not updated. 0 ready Ready. 1 RDYE HTimer Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 ALDF Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active 0 pending Active 1 ALSF Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active 0 Pending Active 1 WE Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits. 15 1 dis Not active 0 en Active 1