HA Hardware Accelerator 0x40036000 0x00 0x1000 registers HA Smart DMA interrupt. 60 IP Q30E Instruction Pointer. 0x00 read-only SP Q30E Stack Pointer. 0x04 read-only DP0 Q30E Data Pointer 0. 0x08 read-only DP1 Q30E Data Pointer 1. 0x0C read-only BP Q30E Frame Pointer Base. 0x10 read-only OFFS Q30E Frame Pointer Offset. 0x14 read-only LC0 Q30E Loop Counter 0. 0x18 read-only LC1 Q30E Loop Counter 1. 0x1C read-only A0 Q30E Accumulator 0. 0x20 read-only A1 Q30E Accumulator 1. 0x24 read-only A2 Q30E Accumulator 2. 0x28 read-only A3 Q30E Accumulator 3. 0x2C read-only WDCN Q30E Watchdog Control. 0x30 read-only INT_MUX_CTRL0 Interrupt Mux Control 0. 0x80 read-write INTSEL16 Interrupt Selection For 16th Interrupt. 0 8 INTSEL17 Interrupt Selection For 17th Interrupt. 8 8 INTSEL18 Interrupt Selection For 18th Interrupt. 16 8 INTSEL19 Interrupt Selection For 19th Interrupt. 24 8 INT_MUX_CTRL1 Interrupt Mux Control 1. 0x84 read-write INTSEL20 Interrupt Selection For 20th Interrupt. 0 8 INTSEL21 Interrupt Selection For 21st Interrupt. 8 8 INTSEL22 Interrupt Selection For 22nd Interrupt. 16 8 INTSEL23 Interrupt Selection For 23rd Interrupt. 24 8 INT_MUX_CTRL2 Interrupt Mux Control 2. 0x88 read-write INTSEL24 Interrupt Selection For 24th Interrupt. 0 8 INTSEL25 Interrupt Selection For 25th Interrupt. 8 8 INTSEL26 Interrupt Selection For 26th Interrupt. 16 8 INTSEL27 Interrupt Selection For 27th Interrupt. 24 8 INT_MUX_CTRL3 Interrupt Mux Control 3. 0x8C read-write INTSEL28 Interrupt Selection For 28th Interrupt. 0 8 INTSEL29 Interrupt Selection For 29th Interrupt. 8 8 INTSEL30 Interrupt Selection For 30th Interrupt. 16 8 INTSEL31 Interrupt Selection For 31st Interrupt. 24 8 IP_ADDR Configurable starting IP address for Q30E. 0x90 read-write START_IP_ADDR Starting IP address for Q30E 0 32 CTRL Control Register. 0x94 read-write EN Enable SDMA. 0 1 dis Disable SDMA. 0 en Enable SDMA. 1 INT_IN_CTRL Interrupt Input From CPU Control Register. 0xA0 read-write INTSET Set Interrupt Flag. 0 1 dis Set interrupt Flag to 0. 0 set Set Interrupt Flag to 1. 1 INT_IN_FLAG Interrupt Input From CPU Flag. 0xA4 read-write INTFLAG Interrupt Flag. 0 1 no_eff No Effect. 0 clear INT_IN_FLAG =0 1 INT_IN_IE Interrupt Input From CPU Enable. 0xA8 read-write INT_IN_EN Interrupt Enable. 0 1 IRQ_FLAG Interrupt Output To CPU Flag. 0xB0 read-write IRQ_FLAG Interrupt Flag. 0 1 IRQ_IE Interrupt Output To CPU Control Register. 0xB4 read-write IRQ_EN Interrupt Enable. 0 1