FLC Flash Memory Control. FLSH_ 0x40029000 0x00 0x1000 registers Flash_Controller Flash Controller interrupt. 23 ADDR Flash Write Address. 0x00 ADDR Address for next operation. 0 32 CLKDIV Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. 0x04 0x00000064 CLKDIV Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. 0 8 CTRL Flash Control Register. 0x08 WR Write. This bit is automatically cleared after the operation. 0 1 complete No operation/complete. 0 start Start operation. 1 ME Mass Erase. This bit is automatically cleared after the operation. 1 1 PGE Page Erase. This bit is automatically cleared after the operation. 2 1 WDTH TBD 4 1 ERASE_CODE Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. 8 8 nop No operation. 0 erasePage Enable Page Erase. 0x55 eraseAll Enable Mass Erase. The debug port must be enabled. 0xAA PEND Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. 24 1 read-only idle Idle. 0 busy Busy. 1 LVE Low Voltage enable. 25 1 UNLOCK Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. 28 4 unlocked Flash Unlocked. 2 locked Flash Locked. 3 INTR Flash Interrupt Register. 0x024 DONE Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 AF Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. 1 1 noerr No Failure. 0 error Failure occurs. 1 PROG_PROT_ERR Program Protection Error. 2 1 noerr No Failure. 0 error Failure occurs. 1 MASS_ER_PROT_ERR TBD 3 1 noerr No Failure. 0 error Failure occurs. 1 PAGE_ER_PROT_ERR TBD 4 1 noerr No Failure. 0 error Failure occurs. 1 PROT_AREA_PROT_ERR TBD 5 1 noerr No Failure. 0 error Failure occurs. 1 DONEIE Flash Done Interrupt Enable. 8 1 dis Disable. 0 en Enable. 1 AFIE 9 1 dis Disable. 0 en Enable. 1 PROTIE 10 1 dis Disable. 0 en Enable. 1 4 4 DATA[%s] Flash Write Data. 0x30 DATA Data next operation. 0 32 ACTRL Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. 0x40 write-only ACTRL Access control. 0 32 WELR0 Access control. 0x80 read-write WELR0 TBD 0 32 RLR0 Access control. 0x84 read-write RLR0 TBD 0 32 WELR1 Access control. 0x88 read-write WELR1 TBD 0 32 RLR1 Access control. 0x8C read-write RLR1 TBD 0 32 WELR2 Access control. 0x90 read-write WELR2 TBD 0 32 RLR2 Access control. 0x94 read-write RLR2 TBD 0 32 WELR3 Access control. 0x98 read-write WELR3 TBD 0 32 RLR3 Access control. 0x9C read-write RLR3 TBD 0 32 WELR4 Access control. 0xA0 read-write WELR4 TBD 0 32 RLR4 Access control. 0xA4 read-write RLR4 TBD 0 32 WELR5 Access control. 0xA8 read-write WELR5 TBD 0 32 RLR5 Access control. 0xAC read-write RLR5 TBD 0 32