DMA DMA Controller Fully programmable, chaining capable DMA channels. 0x40028000 32 0x00 0x1000 registers DMA0 28 DMA1 29 DMA2 30 DMA3 31 DMA4 68 DMA5 69 DMA6 70 DMA7 71 DMA8 72 DMA9 73 DMA10 74 DMA11 75 DMA12 76 DMA13 77 DMA14 78 DMA15 79 CN DMA Control Register. 0x000 CH0_IEN Channel 0 Interrupt Enable. 0 1 dis Disable. 0 en Enable. 1 CH2_IEN Channel 2 Interrupt Enable. 2 1 CH3_IEN Channel 3 Interrupt Enable. 3 1 CH4_IEN Channel 4 Interrupt Enable. 4 1 CH5_IEN Channel 5 Interrupt Enable. 5 1 CH6_IEN Channel 6 Interrupt Enable. 6 1 CH7_IEN Channel 7 Interrupt Enable. 7 1 INTR DMA Interrupt Register. 0x004 read-only CH0_IPEND Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CH1_IPEND 1 1 CH2_IPEND 2 1 CH3_IPEND 3 1 CH4_IPEND 4 1 CH5_IPEND 5 1 CH6_IPEND 6 1 CH7_IPEND 7 1 8 0x20 CH[%s] DMA Channel registers. dma_ch 0x100 read-write CFG DMA Channel Configuration Register. 0x000 CHEN Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 RLDEN Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. 1 1 dis Disable. 0 en Enable. 1 PRI DMA Priority. 2 2 high Highest Priority. 0 medHigh Medium High Priority. 1 medLow Medium Low Priority. 2 low Lowest Priority. 3 REQSEL Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. 4 6 MEMTOMEM Memory To Memory 0x00 SPI0RX SPI0 RX 0x01 SPI1RX SPI1 RX 0x02 UART0RX UART0 RX 0x04 UART1RX UART1 RX 0x05 I2C0RX I2C0 RX 0x07 I2C1RX I2C1 RX 0x08 ADC Analog-to-Digital Converter Channel 0x09 I2C2RX I2C2 RX 0x0A UART2RX UART2 RX 0x0E SPI2RX SPI2 RX 0x0F USBRXEP1 USB Endpoint 1 RX 0x11 USBRXEP2 USB Endpoint 2 RX 0x12 USBRXEP3 USB Endpoint 3 RX 0x13 USBRXEP4 USB Endpoint 4 RX 0x14 USBRXEP5 USB Endpoint 5 RX 0x15 USBRXEP6 USB Endpoint 6 RX 0x16 USBRXEP7 USB Endpoint 7 RX 0x17 USBRXEP8 USB Endpoint 8 RX 0x18 USBRXEP9 USB Endpoint 9 RX 0x19 USBRXEP10 USB Endpoint 10 RX 0x1A USBRXEP11 USB Endpoint 11 RX 0x1B SPI0TX SPI0 TX 0x21 SPI1TX SPI1 TX 0x22 UART0TX UART0 TX 0x24 UART1TX UART1 TX 0x25 I2C0TX I2C0 TX 0x27 I2C1TX I2C1 TX 0x28 I2C2TX I2C2 TX 0x2A UART2TX UART2 TX 0x2E SPI2TX SPI3 TX 0x2F USBTXEP1 USB Endpoint 1 TX 0x31 USBTXEP2 USB Endpoint 2 TX 0x32 USBTXEP3 USB Endpoint 3 TX 0x33 USBTXEP4 USB Endpoint 4 TX 0x34 USBTXEP5 USB Endpoint 5 TX 0x35 USBTXEP6 USB Endpoint 6 TX 0x36 USBTXEP7 USB Endpoint 7 TX 0x37 USBTXEP8 USB Endpoint 8 TX 0x38 USBTXEP9 USB Endpoint 9 TX 0x39 USBTXEP10 USB Endpoint 10 TX 0x3A USBTXEP11 USB Endpoint 11 TX 0x3B REQWAIT Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. 10 1 dis Disable. 0 en Enable. 1 TOSEL Timeout Period Select. 11 3 to4 Timeout of 3 to 4 prescale clocks. 0 to8 Timeout of 7 to 8 prescale clocks. 1 to16 Timeout of 15 to 16 prescale clocks. 2 to32 Timeout of 31 to 32 prescale clocks. 3 to64 Timeout of 63 to 64 prescale clocks. 4 to128 Timeout of 127 to 128 prescale clocks. 5 to256 Timeout of 255 to 256 prescale clocks. 6 to512 Timeout of 511 to 512 prescale clocks. 7 PSSEL Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. 14 2 dis Disable timer. 0 div256 hclk / 256. 1 div64k hclk / 64k. 2 div16M hclk / 16M. 3 SRCWD Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. 16 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 SRCINC Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. 18 1 dis Disable. 0 en Enable. 1 DSTWD Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). 20 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 DSTINC Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. 22 1 dis Disable. 0 en Enable. 1 BRST Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. 24 5 CHDIEN Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. 30 1 dis Disable. 0 en Enable. 1 CTZIEN Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. 31 1 dis Disable. 0 en Enable. 1 ST DMA Channel Status Register. 0x004 CH_ST Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). 0 1 read-only dis Disable. 0 en Enable. 1 IPEND Channel Interrupt. 1 1 read-only inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CTZ_ST Count-to-Zero (CTZ) Event Interrupt Flag 2 1 oneToClear RLD_ST Reload Event Interrupt Flag. 3 1 oneToClear BUS_ERR Bus Error. Indicates that an AHB abort was received and the channel has been disabled. 4 1 oneToClear TO_ST Time-Out Event Interrupt Flag. 6 1 oneToClear SRC Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. 0x008 SRC 0 32 DST Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. 0x00C DST 0 32 CNT DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. 0x010 CNT DMA Counter. 0 24 SRC_RLD Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. 0x014 SRC_RLD Source Address Reload Value. 0 31 DST_RLD Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. 0x018 DST_RLD Destination Address Reload Value. 0 31 CNT_RLD DMA Channel Count Reload Register. 0x01C CNT_RLD Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. 0 24 RLDEN Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. 31 1 dis Disable. 0 en Enable. 1